[11:58:15.866] <TB1> INFO: *** Welcome to pxar ***
[11:58:15.866] <TB1> INFO: *** Today: 2016/10/26
[11:58:15.872] <TB1> INFO: *** Version: c8ba-dirty
[11:58:15.872] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C15.dat
[11:58:15.872] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//tbmParameters_C1b.dat
[11:58:15.873] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//defaultMaskFile.dat
[11:58:15.873] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters_C15.dat
[11:58:15.932] <TB1> INFO: clk: 4
[11:58:15.932] <TB1> INFO: ctr: 4
[11:58:15.932] <TB1> INFO: sda: 19
[11:58:15.932] <TB1> INFO: tin: 9
[11:58:15.932] <TB1> INFO: level: 15
[11:58:15.932] <TB1> INFO: triggerdelay: 0
[11:58:15.932] <TB1> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[11:58:15.932] <TB1> INFO: Log level: INFO
[11:58:15.940] <TB1> INFO: Found DTB DTB_WXBYFL
[11:58:15.950] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[11:58:15.952] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
------------------------------------------------------
[11:58:15.953] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[11:58:17.439] <TB1> INFO: DUT info:
[11:58:17.439] <TB1> INFO: The DUT currently contains the following objects:
[11:58:17.439] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[11:58:17.439] <TB1> INFO: TBM Core alpha (0): 7 registers set
[11:58:17.439] <TB1> INFO: TBM Core beta (1): 7 registers set
[11:58:17.439] <TB1> INFO: TBM Core alpha (2): 7 registers set
[11:58:17.439] <TB1> INFO: TBM Core beta (3): 7 registers set
[11:58:17.439] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:58:17.439] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.439] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:17.840] <TB1> INFO: enter 'restricted' command line mode
[11:58:17.840] <TB1> INFO: enter test to run
[11:58:17.840] <TB1> INFO: test: pretest no parameter change
[11:58:17.840] <TB1> INFO: running: pretest
[11:58:18.399] <TB1> INFO: ######################################################################
[11:58:18.399] <TB1> INFO: PixTestPretest::doTest()
[11:58:18.399] <TB1> INFO: ######################################################################
[11:58:18.400] <TB1> INFO: ----------------------------------------------------------------------
[11:58:18.400] <TB1> INFO: PixTestPretest::programROC()
[11:58:18.400] <TB1> INFO: ----------------------------------------------------------------------
[11:58:36.414] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:58:36.414] <TB1> INFO: IA differences per ROC: 20.1 20.9 17.7 20.1 16.9 18.5 17.7 21.7 16.1 20.1 17.7 17.7 20.9 19.3 19.3 18.5
[11:58:36.449] <TB1> INFO: ----------------------------------------------------------------------
[11:58:36.449] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:58:36.449] <TB1> INFO: ----------------------------------------------------------------------
[11:58:57.683] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 389.1 mA = 24.3188 mA/ROC
[11:58:57.683] <TB1> INFO: i(loss) [mA/ROC]: 20.1 19.3 20.9 19.3 19.3 20.1 20.1 19.3 19.3 20.1 20.9 20.1 19.3 19.3 19.3 19.3
[11:58:57.714] <TB1> INFO: ----------------------------------------------------------------------
[11:58:57.714] <TB1> INFO: PixTestPretest::findTiming()
[11:58:57.714] <TB1> INFO: ----------------------------------------------------------------------
[11:58:57.714] <TB1> INFO: PixTestCmd::init()

[11:59:28.749] <TB1> INFO: TBM phases: 160MHz: 7, 400MHz: 6, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:59:28.749] <TB1> INFO: (success/tries = 100/100), width = 3
[11:59:30.249] <TB1> INFO: ----------------------------------------------------------------------
[11:59:30.249] <TB1> INFO: PixTestPretest::findWorkingPixel()
[11:59:30.249] <TB1> INFO: ----------------------------------------------------------------------
[11:59:30.340] <TB1> INFO: Expecting 231680 events.
[11:59:40.066] <TB1> INFO: 231680 events read in total (9134ms).
[11:59:40.073] <TB1> INFO: Test took 9822ms.
[11:59:40.325] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:59:40.355] <TB1> INFO: ----------------------------------------------------------------------
[11:59:40.355] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[11:59:40.355] <TB1> INFO: ----------------------------------------------------------------------
[11:59:40.447] <TB1> INFO: Expecting 231680 events.
[11:59:50.282] <TB1> INFO: 231680 events read in total (9243ms).
[11:59:50.292] <TB1> INFO: Test took 9934ms.
[11:59:50.549] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[11:59:50.549] <TB1> INFO: CalDel: 99 100 92 106 110 114 107 105 112 81 82 103 95 106 111 83
[11:59:50.549] <TB1> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 52 52 51 58 52 51 52
[11:59:50.552] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C0.dat
[11:59:50.552] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C1.dat
[11:59:50.552] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C2.dat
[11:59:50.552] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C3.dat
[11:59:50.552] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C4.dat
[11:59:50.552] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C5.dat
[11:59:50.553] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C6.dat
[11:59:50.553] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C7.dat
[11:59:50.553] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C8.dat
[11:59:50.553] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C9.dat
[11:59:50.553] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C10.dat
[11:59:50.553] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C11.dat
[11:59:50.553] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C12.dat
[11:59:50.553] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C13.dat
[11:59:50.553] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C14.dat
[11:59:50.553] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C15.dat
[11:59:50.553] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//tbmParameters_C0a.dat
[11:59:50.554] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//tbmParameters_C0b.dat
[11:59:50.554] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//tbmParameters_C1a.dat
[11:59:50.554] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//tbmParameters_C1b.dat
[11:59:50.554] <TB1> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[11:59:50.695] <TB1> INFO: enter test to run
[11:59:50.695] <TB1> INFO: test: FullTest no parameter change
[11:59:50.695] <TB1> INFO: running: fulltest
[11:59:50.696] <TB1> INFO: ######################################################################
[11:59:50.696] <TB1> INFO: PixTestFullTest::doTest()
[11:59:50.696] <TB1> INFO: ######################################################################
[11:59:50.697] <TB1> INFO: ######################################################################
[11:59:50.697] <TB1> INFO: PixTestAlive::doTest()
[11:59:50.697] <TB1> INFO: ######################################################################
[11:59:50.698] <TB1> INFO: ----------------------------------------------------------------------
[11:59:50.698] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:59:50.698] <TB1> INFO: ----------------------------------------------------------------------
[11:59:50.931] <TB1> INFO: Expecting 41600 events.
[11:59:54.412] <TB1> INFO: 41600 events read in total (2890ms).
[11:59:54.413] <TB1> INFO: Test took 3714ms.
[11:59:54.637] <TB1> INFO: PixTestAlive::aliveTest() done
[11:59:54.638] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:59:54.639] <TB1> INFO: ----------------------------------------------------------------------
[11:59:54.639] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:59:54.639] <TB1> INFO: ----------------------------------------------------------------------
[11:59:54.872] <TB1> INFO: Expecting 41600 events.
[11:59:57.884] <TB1> INFO: 41600 events read in total (2420ms).
[11:59:57.885] <TB1> INFO: Test took 3245ms.
[11:59:57.885] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:59:58.121] <TB1> INFO: PixTestAlive::maskTest() done
[11:59:58.121] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:59:58.122] <TB1> INFO: ----------------------------------------------------------------------
[11:59:58.122] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:59:58.122] <TB1> INFO: ----------------------------------------------------------------------
[11:59:58.356] <TB1> INFO: Expecting 41600 events.
[12:00:01.904] <TB1> INFO: 41600 events read in total (2957ms).
[12:00:01.904] <TB1> INFO: Test took 3781ms.
[12:00:02.132] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[12:00:02.132] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:00:02.132] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:00:02.132] <TB1> INFO: Decoding statistics:
[12:00:02.132] <TB1> INFO: General information:
[12:00:02.132] <TB1> INFO: 16bit words read: 0
[12:00:02.132] <TB1> INFO: valid events total: 0
[12:00:02.132] <TB1> INFO: empty events: 0
[12:00:02.132] <TB1> INFO: valid events with pixels: 0
[12:00:02.132] <TB1> INFO: valid pixel hits: 0
[12:00:02.132] <TB1> INFO: Event errors: 0
[12:00:02.132] <TB1> INFO: start marker: 0
[12:00:02.132] <TB1> INFO: stop marker: 0
[12:00:02.132] <TB1> INFO: overflow: 0
[12:00:02.132] <TB1> INFO: invalid 5bit words: 0
[12:00:02.132] <TB1> INFO: invalid XOR eye diagram: 0
[12:00:02.132] <TB1> INFO: frame (failed synchr.): 0
[12:00:02.133] <TB1> INFO: idle data (no TBM trl): 0
[12:00:02.133] <TB1> INFO: no data (only TBM hdr): 0
[12:00:02.133] <TB1> INFO: TBM errors: 0
[12:00:02.133] <TB1> INFO: flawed TBM headers: 0
[12:00:02.133] <TB1> INFO: flawed TBM trailers: 0
[12:00:02.133] <TB1> INFO: event ID mismatches: 0
[12:00:02.133] <TB1> INFO: ROC errors: 0
[12:00:02.133] <TB1> INFO: missing ROC header(s): 0
[12:00:02.133] <TB1> INFO: misplaced readback start: 0
[12:00:02.133] <TB1> INFO: Pixel decoding errors: 0
[12:00:02.133] <TB1> INFO: pixel data incomplete: 0
[12:00:02.133] <TB1> INFO: pixel address: 0
[12:00:02.133] <TB1> INFO: pulse height fill bit: 0
[12:00:02.133] <TB1> INFO: buffer corruption: 0
[12:00:02.139] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C15.dat
[12:00:02.140] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[12:00:02.140] <TB1> INFO: ######################################################################
[12:00:02.140] <TB1> INFO: PixTestReadback::doTest()
[12:00:02.140] <TB1> INFO: ######################################################################
[12:00:02.140] <TB1> INFO: ----------------------------------------------------------------------
[12:00:02.140] <TB1> INFO: PixTestReadback::CalibrateVd()
[12:00:02.140] <TB1> INFO: ----------------------------------------------------------------------
[12:00:12.130] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C0.dat
[12:00:12.130] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C1.dat
[12:00:12.130] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C2.dat
[12:00:12.130] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C3.dat
[12:00:12.130] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C4.dat
[12:00:12.130] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C5.dat
[12:00:12.130] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C6.dat
[12:00:12.130] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C7.dat
[12:00:12.130] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C8.dat
[12:00:12.131] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C9.dat
[12:00:12.131] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C10.dat
[12:00:12.131] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C11.dat
[12:00:12.131] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C12.dat
[12:00:12.131] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C13.dat
[12:00:12.131] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C14.dat
[12:00:12.131] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C15.dat
[12:00:12.159] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:00:12.159] <TB1> INFO: ----------------------------------------------------------------------
[12:00:12.159] <TB1> INFO: PixTestReadback::CalibrateVa()
[12:00:12.159] <TB1> INFO: ----------------------------------------------------------------------
[12:00:22.045] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C0.dat
[12:00:22.045] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C1.dat
[12:00:22.045] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C2.dat
[12:00:22.045] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C3.dat
[12:00:22.046] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C4.dat
[12:00:22.046] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C5.dat
[12:00:22.046] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C6.dat
[12:00:22.046] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C7.dat
[12:00:22.046] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C8.dat
[12:00:22.046] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C9.dat
[12:00:22.046] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C10.dat
[12:00:22.046] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C11.dat
[12:00:22.046] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C12.dat
[12:00:22.046] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C13.dat
[12:00:22.046] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C14.dat
[12:00:22.046] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C15.dat
[12:00:22.073] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:00:22.073] <TB1> INFO: ----------------------------------------------------------------------
[12:00:22.073] <TB1> INFO: PixTestReadback::readbackVbg()
[12:00:22.073] <TB1> INFO: ----------------------------------------------------------------------
[12:00:29.719] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:00:29.719] <TB1> INFO: ----------------------------------------------------------------------
[12:00:29.719] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[12:00:29.719] <TB1> INFO: ----------------------------------------------------------------------
[12:00:29.719] <TB1> INFO: Vbg will be calibrated using Vd calibration
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 166.1calibrated Vbg = 1.14071 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 149.8calibrated Vbg = 1.13393 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 149.3calibrated Vbg = 1.13034 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 157.1calibrated Vbg = 1.14214 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 152calibrated Vbg = 1.13983 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 149.9calibrated Vbg = 1.14054 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 153.4calibrated Vbg = 1.14024 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 151.7calibrated Vbg = 1.14403 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 165.3calibrated Vbg = 1.13599 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 160.7calibrated Vbg = 1.13365 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 160.1calibrated Vbg = 1.14151 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 146.7calibrated Vbg = 1.12593 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 162.9calibrated Vbg = 1.14167 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152.7calibrated Vbg = 1.14618 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 153.1calibrated Vbg = 1.13968 :::*/*/*/*/
[12:00:29.719] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 162.8calibrated Vbg = 1.14706 :::*/*/*/*/
[12:00:29.721] <TB1> INFO: ----------------------------------------------------------------------
[12:00:29.721] <TB1> INFO: PixTestReadback::CalibrateIa()
[12:00:29.721] <TB1> INFO: ----------------------------------------------------------------------
[12:03:09.998] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C0.dat
[12:03:09.998] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C1.dat
[12:03:09.998] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C2.dat
[12:03:09.998] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C3.dat
[12:03:09.998] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C4.dat
[12:03:09.998] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C5.dat
[12:03:09.998] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C6.dat
[12:03:09.998] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C7.dat
[12:03:09.998] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C8.dat
[12:03:09.999] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C9.dat
[12:03:09.999] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C10.dat
[12:03:09.999] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C11.dat
[12:03:09.999] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C12.dat
[12:03:09.999] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C13.dat
[12:03:09.999] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C14.dat
[12:03:09.999] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C15.dat
[12:03:10.028] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:03:10.029] <TB1> INFO: PixTestReadback::doTest() done
[12:03:10.029] <TB1> INFO: Decoding statistics:
[12:03:10.029] <TB1> INFO: General information:
[12:03:10.029] <TB1> INFO: 16bit words read: 1536
[12:03:10.029] <TB1> INFO: valid events total: 256
[12:03:10.029] <TB1> INFO: empty events: 256
[12:03:10.029] <TB1> INFO: valid events with pixels: 0
[12:03:10.029] <TB1> INFO: valid pixel hits: 0
[12:03:10.029] <TB1> INFO: Event errors: 0
[12:03:10.029] <TB1> INFO: start marker: 0
[12:03:10.029] <TB1> INFO: stop marker: 0
[12:03:10.029] <TB1> INFO: overflow: 0
[12:03:10.029] <TB1> INFO: invalid 5bit words: 0
[12:03:10.029] <TB1> INFO: invalid XOR eye diagram: 0
[12:03:10.029] <TB1> INFO: frame (failed synchr.): 0
[12:03:10.029] <TB1> INFO: idle data (no TBM trl): 0
[12:03:10.029] <TB1> INFO: no data (only TBM hdr): 0
[12:03:10.030] <TB1> INFO: TBM errors: 0
[12:03:10.030] <TB1> INFO: flawed TBM headers: 0
[12:03:10.030] <TB1> INFO: flawed TBM trailers: 0
[12:03:10.030] <TB1> INFO: event ID mismatches: 0
[12:03:10.030] <TB1> INFO: ROC errors: 0
[12:03:10.030] <TB1> INFO: missing ROC header(s): 0
[12:03:10.030] <TB1> INFO: misplaced readback start: 0
[12:03:10.030] <TB1> INFO: Pixel decoding errors: 0
[12:03:10.030] <TB1> INFO: pixel data incomplete: 0
[12:03:10.030] <TB1> INFO: pixel address: 0
[12:03:10.030] <TB1> INFO: pulse height fill bit: 0
[12:03:10.030] <TB1> INFO: buffer corruption: 0
[12:03:10.080] <TB1> INFO: ######################################################################
[12:03:10.080] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:03:10.080] <TB1> INFO: ######################################################################
[12:03:10.082] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:03:10.093] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:03:10.093] <TB1> INFO: run 1 of 1
[12:03:10.324] <TB1> INFO: Expecting 3120000 events.
[12:03:41.838] <TB1> INFO: 666650 events read in total (30922ms).











[12:04:12.222] <TB1> INFO: 1327810 events read in total (61306ms).











[12:04:42.709] <TB1> INFO: 1986060 events read in total (91793ms).











[12:05:12.951] <TB1> INFO: 2645065 events read in total (122035ms).
[12:05:34.870] <TB1> INFO: 3120000 events read in total (143954ms).
[12:05:34.947] <TB1> INFO: Test took 144855ms.
[12:05:58.226] <TB1> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 168 seconds
[12:05:58.226] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 7 0 0 0 0 1 0 0
[12:05:58.226] <TB1> INFO: separation cut (per ROC): 107 106 108 102 107 107 104 105 103 109 119 108 104 102 104 104
[12:05:58.226] <TB1> INFO: Decoding statistics:
[12:05:58.226] <TB1> INFO: General information:
[12:05:58.226] <TB1> INFO: 16bit words read: 0
[12:05:58.226] <TB1> INFO: valid events total: 0
[12:05:58.226] <TB1> INFO: empty events: 0
[12:05:58.226] <TB1> INFO: valid events with pixels: 0
[12:05:58.226] <TB1> INFO: valid pixel hits: 0
[12:05:58.226] <TB1> INFO: Event errors: 0
[12:05:58.226] <TB1> INFO: start marker: 0
[12:05:58.226] <TB1> INFO: stop marker: 0
[12:05:58.226] <TB1> INFO: overflow: 0
[12:05:58.226] <TB1> INFO: invalid 5bit words: 0
[12:05:58.226] <TB1> INFO: invalid XOR eye diagram: 0
[12:05:58.226] <TB1> INFO: frame (failed synchr.): 0
[12:05:58.226] <TB1> INFO: idle data (no TBM trl): 0
[12:05:58.226] <TB1> INFO: no data (only TBM hdr): 0
[12:05:58.226] <TB1> INFO: TBM errors: 0
[12:05:58.226] <TB1> INFO: flawed TBM headers: 0
[12:05:58.226] <TB1> INFO: flawed TBM trailers: 0
[12:05:58.226] <TB1> INFO: event ID mismatches: 0
[12:05:58.226] <TB1> INFO: ROC errors: 0
[12:05:58.226] <TB1> INFO: missing ROC header(s): 0
[12:05:58.226] <TB1> INFO: misplaced readback start: 0
[12:05:58.226] <TB1> INFO: Pixel decoding errors: 0
[12:05:58.226] <TB1> INFO: pixel data incomplete: 0
[12:05:58.226] <TB1> INFO: pixel address: 0
[12:05:58.226] <TB1> INFO: pulse height fill bit: 0
[12:05:58.226] <TB1> INFO: buffer corruption: 0
[12:05:58.275] <TB1> INFO: ######################################################################
[12:05:58.275] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:05:58.275] <TB1> INFO: ######################################################################
[12:05:58.276] <TB1> INFO: ----------------------------------------------------------------------
[12:05:58.276] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:05:58.276] <TB1> INFO: ----------------------------------------------------------------------
[12:05:58.276] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:05:58.287] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[12:05:58.287] <TB1> INFO: run 1 of 1
[12:05:58.546] <TB1> INFO: Expecting 36608000 events.
[12:06:22.370] <TB1> INFO: 677200 events read in total (23232ms).
[12:06:45.837] <TB1> INFO: 1344800 events read in total (46699ms).
[12:07:08.893] <TB1> INFO: 2011050 events read in total (69755ms).
[12:07:31.870] <TB1> INFO: 2676950 events read in total (92732ms).
[12:07:55.132] <TB1> INFO: 3341400 events read in total (115994ms).
[12:08:18.098] <TB1> INFO: 4005400 events read in total (138960ms).
[12:08:40.961] <TB1> INFO: 4669150 events read in total (161823ms).
[12:09:04.520] <TB1> INFO: 5331600 events read in total (185382ms).
[12:09:27.394] <TB1> INFO: 5995100 events read in total (208256ms).
[12:09:50.261] <TB1> INFO: 6659850 events read in total (231123ms).
[12:10:13.569] <TB1> INFO: 7323100 events read in total (254431ms).
[12:10:37.156] <TB1> INFO: 7984850 events read in total (278018ms).
[12:10:59.943] <TB1> INFO: 8647850 events read in total (300805ms).
[12:11:22.834] <TB1> INFO: 9310550 events read in total (323696ms).
[12:11:46.021] <TB1> INFO: 9974700 events read in total (346883ms).
[12:12:08.993] <TB1> INFO: 10635200 events read in total (369855ms).
[12:12:32.150] <TB1> INFO: 11297200 events read in total (393012ms).
[12:12:55.329] <TB1> INFO: 11957750 events read in total (416191ms).
[12:13:18.362] <TB1> INFO: 12620150 events read in total (439224ms).
[12:13:41.166] <TB1> INFO: 13279700 events read in total (462028ms).
[12:14:04.216] <TB1> INFO: 13941400 events read in total (485078ms).
[12:14:27.248] <TB1> INFO: 14600600 events read in total (508110ms).
[12:14:50.541] <TB1> INFO: 15261550 events read in total (531403ms).
[12:15:13.663] <TB1> INFO: 15921500 events read in total (554525ms).
[12:15:36.718] <TB1> INFO: 16582900 events read in total (577580ms).
[12:16:00.097] <TB1> INFO: 17242100 events read in total (600959ms).
[12:16:22.907] <TB1> INFO: 17899850 events read in total (623769ms).
[12:16:46.151] <TB1> INFO: 18559300 events read in total (647013ms).
[12:17:09.264] <TB1> INFO: 19218050 events read in total (670126ms).
[12:17:32.356] <TB1> INFO: 19875800 events read in total (693218ms).
[12:17:55.357] <TB1> INFO: 20531150 events read in total (716219ms).
[12:18:18.210] <TB1> INFO: 21188450 events read in total (739072ms).
[12:18:41.071] <TB1> INFO: 21844400 events read in total (761933ms).
[12:19:04.413] <TB1> INFO: 22501550 events read in total (785275ms).
[12:19:27.249] <TB1> INFO: 23153550 events read in total (808111ms).
[12:19:50.183] <TB1> INFO: 23810050 events read in total (831045ms).
[12:20:13.223] <TB1> INFO: 24463400 events read in total (854085ms).
[12:20:36.334] <TB1> INFO: 25120550 events read in total (877196ms).
[12:20:59.377] <TB1> INFO: 25775250 events read in total (900239ms).
[12:21:22.326] <TB1> INFO: 26431900 events read in total (923188ms).
[12:21:45.295] <TB1> INFO: 27085650 events read in total (946157ms).
[12:22:08.265] <TB1> INFO: 27739450 events read in total (969127ms).
[12:22:31.250] <TB1> INFO: 28394400 events read in total (992112ms).
[12:22:54.033] <TB1> INFO: 29046350 events read in total (1014895ms).
[12:23:17.188] <TB1> INFO: 29700050 events read in total (1038050ms).
[12:23:40.259] <TB1> INFO: 30353350 events read in total (1061121ms).
[12:24:03.283] <TB1> INFO: 31008150 events read in total (1084145ms).
[12:24:26.136] <TB1> INFO: 31659700 events read in total (1106998ms).
[12:24:49.057] <TB1> INFO: 32314800 events read in total (1129919ms).
[12:25:12.217] <TB1> INFO: 32967900 events read in total (1153079ms).
[12:25:35.074] <TB1> INFO: 33624050 events read in total (1175936ms).
[12:25:58.053] <TB1> INFO: 34278200 events read in total (1198915ms).
[12:26:20.719] <TB1> INFO: 34934600 events read in total (1221581ms).
[12:26:44.282] <TB1> INFO: 35591200 events read in total (1245144ms).
[12:27:07.170] <TB1> INFO: 36252350 events read in total (1268032ms).
[12:27:19.328] <TB1> INFO: 36608000 events read in total (1280190ms).
[12:27:19.379] <TB1> INFO: Test took 1281092ms.
[12:27:19.813] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:21.537] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:23.078] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:24.666] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:26.256] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:27.811] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:29.748] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:31.450] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:33.471] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:35.403] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:37.702] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:39.325] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:40.811] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:42.546] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:44.503] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:46.396] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:27:48.438] <TB1> INFO: PixTestScurves::scurves() done
[12:27:48.438] <TB1> INFO: Vcal mean: 121.55 110.11 110.47 108.40 120.40 114.60 113.24 110.33 115.80 125.55 114.34 117.59 122.81 120.21 110.91 114.69
[12:27:48.438] <TB1> INFO: Vcal RMS: 6.23 4.70 5.04 5.17 5.99 5.51 4.88 5.04 6.35 6.68 4.94 5.83 7.22 6.84 5.11 5.46
[12:27:48.438] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1310 seconds
[12:27:48.438] <TB1> INFO: Decoding statistics:
[12:27:48.438] <TB1> INFO: General information:
[12:27:48.438] <TB1> INFO: 16bit words read: 0
[12:27:48.438] <TB1> INFO: valid events total: 0
[12:27:48.438] <TB1> INFO: empty events: 0
[12:27:48.438] <TB1> INFO: valid events with pixels: 0
[12:27:48.438] <TB1> INFO: valid pixel hits: 0
[12:27:48.438] <TB1> INFO: Event errors: 0
[12:27:48.438] <TB1> INFO: start marker: 0
[12:27:48.438] <TB1> INFO: stop marker: 0
[12:27:48.438] <TB1> INFO: overflow: 0
[12:27:48.438] <TB1> INFO: invalid 5bit words: 0
[12:27:48.438] <TB1> INFO: invalid XOR eye diagram: 0
[12:27:48.438] <TB1> INFO: frame (failed synchr.): 0
[12:27:48.438] <TB1> INFO: idle data (no TBM trl): 0
[12:27:48.438] <TB1> INFO: no data (only TBM hdr): 0
[12:27:48.438] <TB1> INFO: TBM errors: 0
[12:27:48.438] <TB1> INFO: flawed TBM headers: 0
[12:27:48.438] <TB1> INFO: flawed TBM trailers: 0
[12:27:48.438] <TB1> INFO: event ID mismatches: 0
[12:27:48.438] <TB1> INFO: ROC errors: 0
[12:27:48.438] <TB1> INFO: missing ROC header(s): 0
[12:27:48.438] <TB1> INFO: misplaced readback start: 0
[12:27:48.438] <TB1> INFO: Pixel decoding errors: 0
[12:27:48.438] <TB1> INFO: pixel data incomplete: 0
[12:27:48.438] <TB1> INFO: pixel address: 0
[12:27:48.438] <TB1> INFO: pulse height fill bit: 0
[12:27:48.438] <TB1> INFO: buffer corruption: 0
[12:27:48.503] <TB1> INFO: ######################################################################
[12:27:48.503] <TB1> INFO: PixTestTrim::doTest()
[12:27:48.503] <TB1> INFO: ######################################################################
[12:27:48.504] <TB1> INFO: ----------------------------------------------------------------------
[12:27:48.504] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:27:48.504] <TB1> INFO: ----------------------------------------------------------------------
[12:27:48.543] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:27:48.543] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:27:48.551] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:27:48.551] <TB1> INFO: run 1 of 1
[12:27:48.806] <TB1> INFO: Expecting 5025280 events.
[12:28:20.283] <TB1> INFO: 823456 events read in total (30881ms).
[12:28:50.372] <TB1> INFO: 1644464 events read in total (60970ms).
[12:29:20.636] <TB1> INFO: 2463112 events read in total (91234ms).
[12:29:51.252] <TB1> INFO: 3277504 events read in total (121850ms).
[12:30:21.850] <TB1> INFO: 4088488 events read in total (152448ms).
[12:30:52.168] <TB1> INFO: 4897880 events read in total (182766ms).
[12:30:57.514] <TB1> INFO: 5025280 events read in total (188112ms).
[12:30:57.558] <TB1> INFO: Test took 189006ms.
[12:31:16.604] <TB1> INFO: ROC 0 VthrComp = 124
[12:31:16.604] <TB1> INFO: ROC 1 VthrComp = 120
[12:31:16.604] <TB1> INFO: ROC 2 VthrComp = 121
[12:31:16.604] <TB1> INFO: ROC 3 VthrComp = 112
[12:31:16.604] <TB1> INFO: ROC 4 VthrComp = 123
[12:31:16.604] <TB1> INFO: ROC 5 VthrComp = 117
[12:31:16.604] <TB1> INFO: ROC 6 VthrComp = 121
[12:31:16.605] <TB1> INFO: ROC 7 VthrComp = 120
[12:31:16.605] <TB1> INFO: ROC 8 VthrComp = 107
[12:31:16.605] <TB1> INFO: ROC 9 VthrComp = 127
[12:31:16.605] <TB1> INFO: ROC 10 VthrComp = 128
[12:31:16.605] <TB1> INFO: ROC 11 VthrComp = 125
[12:31:16.605] <TB1> INFO: ROC 12 VthrComp = 127
[12:31:16.605] <TB1> INFO: ROC 13 VthrComp = 115
[12:31:16.605] <TB1> INFO: ROC 14 VthrComp = 116
[12:31:16.606] <TB1> INFO: ROC 15 VthrComp = 119
[12:31:16.861] <TB1> INFO: Expecting 41600 events.
[12:31:20.319] <TB1> INFO: 41600 events read in total (2867ms).
[12:31:20.320] <TB1> INFO: Test took 3713ms.
[12:31:20.329] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:31:20.329] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:31:20.337] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:31:20.337] <TB1> INFO: run 1 of 1
[12:31:20.615] <TB1> INFO: Expecting 5025280 events.
[12:31:47.246] <TB1> INFO: 589160 events read in total (26040ms).
[12:32:13.144] <TB1> INFO: 1177648 events read in total (51938ms).
[12:32:39.485] <TB1> INFO: 1766008 events read in total (78279ms).
[12:33:05.251] <TB1> INFO: 2354128 events read in total (104045ms).
[12:33:31.192] <TB1> INFO: 2940304 events read in total (129986ms).
[12:33:57.050] <TB1> INFO: 3524912 events read in total (155844ms).
[12:34:22.792] <TB1> INFO: 4109344 events read in total (181586ms).
[12:34:48.939] <TB1> INFO: 4693672 events read in total (207733ms).
[12:35:03.572] <TB1> INFO: 5025280 events read in total (222366ms).
[12:35:03.630] <TB1> INFO: Test took 223293ms.
[12:35:28.155] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 60.5561 for pixel 40/1 mean/min/max = 46.3732/32.0161/60.7303
[12:35:28.155] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 58.4734 for pixel 24/26 mean/min/max = 45.4224/32.208/58.6368
[12:35:28.155] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 59.2297 for pixel 0/0 mean/min/max = 45.3477/31.3851/59.3102
[12:35:28.155] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 60.1141 for pixel 15/7 mean/min/max = 46.3601/32.5694/60.1508
[12:35:28.156] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 60.9546 for pixel 1/2 mean/min/max = 46.2996/31.4706/61.1285
[12:35:28.156] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 59.3111 for pixel 0/27 mean/min/max = 45.5799/31.7229/59.4368
[12:35:28.156] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 57.211 for pixel 28/15 mean/min/max = 44.9922/32.6802/57.3042
[12:35:28.157] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 58.0325 for pixel 9/12 mean/min/max = 45.1279/32.1089/58.1468
[12:35:28.157] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 67.9746 for pixel 0/5 mean/min/max = 50.7176/33.4476/67.9875
[12:35:28.157] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 60.8804 for pixel 0/2 mean/min/max = 45.4028/29.7867/61.0188
[12:35:28.157] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 57.2978 for pixel 21/5 mean/min/max = 44.5108/31.5621/57.4595
[12:35:28.158] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 60.706 for pixel 0/10 mean/min/max = 45.645/30.5295/60.7605
[12:35:28.158] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 64.2013 for pixel 3/28 mean/min/max = 47.3363/30.3888/64.2837
[12:35:28.158] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 61.7661 for pixel 51/72 mean/min/max = 46.9073/31.9417/61.8729
[12:35:28.158] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 59.1817 for pixel 4/13 mean/min/max = 45.3641/31.4379/59.2904
[12:35:28.159] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 60.4321 for pixel 35/40 mean/min/max = 45.5581/30.6328/60.4834
[12:35:28.159] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:35:28.247] <TB1> INFO: Expecting 411648 events.
[12:35:37.844] <TB1> INFO: 411648 events read in total (9005ms).
[12:35:37.853] <TB1> INFO: Expecting 411648 events.
[12:35:47.207] <TB1> INFO: 411648 events read in total (8951ms).
[12:35:47.216] <TB1> INFO: Expecting 411648 events.
[12:35:56.521] <TB1> INFO: 411648 events read in total (8902ms).
[12:35:56.538] <TB1> INFO: Expecting 411648 events.
[12:36:05.874] <TB1> INFO: 411648 events read in total (8933ms).
[12:36:05.888] <TB1> INFO: Expecting 411648 events.
[12:36:15.176] <TB1> INFO: 411648 events read in total (8885ms).
[12:36:15.192] <TB1> INFO: Expecting 411648 events.
[12:36:24.433] <TB1> INFO: 411648 events read in total (8838ms).
[12:36:24.452] <TB1> INFO: Expecting 411648 events.
[12:36:33.793] <TB1> INFO: 411648 events read in total (8938ms).
[12:36:33.825] <TB1> INFO: Expecting 411648 events.
[12:36:43.087] <TB1> INFO: 411648 events read in total (8859ms).
[12:36:43.110] <TB1> INFO: Expecting 411648 events.
[12:36:52.374] <TB1> INFO: 411648 events read in total (8861ms).
[12:36:52.401] <TB1> INFO: Expecting 411648 events.
[12:37:01.726] <TB1> INFO: 411648 events read in total (8922ms).
[12:37:01.754] <TB1> INFO: Expecting 411648 events.
[12:37:11.064] <TB1> INFO: 411648 events read in total (8907ms).
[12:37:11.102] <TB1> INFO: Expecting 411648 events.
[12:37:20.383] <TB1> INFO: 411648 events read in total (8878ms).
[12:37:20.419] <TB1> INFO: Expecting 411648 events.
[12:37:29.816] <TB1> INFO: 411648 events read in total (8994ms).
[12:37:29.852] <TB1> INFO: Expecting 411648 events.
[12:37:39.106] <TB1> INFO: 411648 events read in total (8851ms).
[12:37:39.145] <TB1> INFO: Expecting 411648 events.
[12:37:48.527] <TB1> INFO: 411648 events read in total (8979ms).
[12:37:48.567] <TB1> INFO: Expecting 411648 events.
[12:37:57.859] <TB1> INFO: 411648 events read in total (8889ms).
[12:37:57.905] <TB1> INFO: Test took 149746ms.
[12:37:58.789] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:37:58.801] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:37:58.801] <TB1> INFO: run 1 of 1
[12:37:59.034] <TB1> INFO: Expecting 5025280 events.
[12:38:25.804] <TB1> INFO: 588464 events read in total (26179ms).
[12:38:51.892] <TB1> INFO: 1176760 events read in total (52267ms).
[12:39:18.058] <TB1> INFO: 1764144 events read in total (78433ms).
[12:39:44.284] <TB1> INFO: 2350776 events read in total (104659ms).
[12:40:10.655] <TB1> INFO: 2935992 events read in total (131030ms).
[12:40:37.282] <TB1> INFO: 3523760 events read in total (157657ms).
[12:41:03.237] <TB1> INFO: 4109416 events read in total (183612ms).
[12:41:29.304] <TB1> INFO: 4694568 events read in total (209679ms).
[12:41:44.316] <TB1> INFO: 5025280 events read in total (224691ms).
[12:41:44.411] <TB1> INFO: Test took 225610ms.
[12:42:06.868] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 2.500000 .. 147.532215
[12:42:07.156] <TB1> INFO: Expecting 208000 events.
[12:42:16.577] <TB1> INFO: 208000 events read in total (8829ms).
[12:42:16.579] <TB1> INFO: Test took 9709ms.
[12:42:16.624] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 157 (-1/-1) hits flags = 528 (plus default)
[12:42:16.632] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:42:16.632] <TB1> INFO: run 1 of 1
[12:42:16.910] <TB1> INFO: Expecting 5191680 events.
[12:42:43.495] <TB1> INFO: 583136 events read in total (25993ms).
[12:43:09.611] <TB1> INFO: 1165752 events read in total (52109ms).
[12:43:35.111] <TB1> INFO: 1748544 events read in total (77609ms).
[12:44:00.912] <TB1> INFO: 2331208 events read in total (103410ms).
[12:44:26.987] <TB1> INFO: 2913560 events read in total (129485ms).
[12:44:52.907] <TB1> INFO: 3495016 events read in total (155405ms).
[12:45:18.895] <TB1> INFO: 4075624 events read in total (181393ms).
[12:45:44.743] <TB1> INFO: 4656952 events read in total (207241ms).
[12:46:08.895] <TB1> INFO: 5191680 events read in total (231393ms).
[12:46:08.992] <TB1> INFO: Test took 232360ms.
[12:46:34.527] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.373761 .. 47.201938
[12:46:34.760] <TB1> INFO: Expecting 208000 events.
[12:46:44.572] <TB1> INFO: 208000 events read in total (9220ms).
[12:46:44.573] <TB1> INFO: Test took 10045ms.
[12:46:44.651] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 57 (-1/-1) hits flags = 528 (plus default)
[12:46:44.662] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:46:44.662] <TB1> INFO: run 1 of 1
[12:46:44.940] <TB1> INFO: Expecting 1364480 events.
[12:47:13.612] <TB1> INFO: 651608 events read in total (28080ms).
[12:47:41.472] <TB1> INFO: 1300800 events read in total (55940ms).
[12:47:44.593] <TB1> INFO: 1364480 events read in total (59062ms).
[12:47:44.621] <TB1> INFO: Test took 59959ms.
[12:47:58.834] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 26.278753 .. 47.833386
[12:47:59.124] <TB1> INFO: Expecting 208000 events.
[12:48:08.641] <TB1> INFO: 208000 events read in total (8925ms).
[12:48:08.642] <TB1> INFO: Test took 9806ms.
[12:48:08.689] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[12:48:08.698] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:48:08.698] <TB1> INFO: run 1 of 1
[12:48:08.976] <TB1> INFO: Expecting 1397760 events.
[12:48:37.836] <TB1> INFO: 656120 events read in total (28268ms).
[12:49:06.009] <TB1> INFO: 1310240 events read in total (56441ms).
[12:49:10.212] <TB1> INFO: 1397760 events read in total (60644ms).
[12:49:10.245] <TB1> INFO: Test took 61548ms.
[12:49:23.387] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 25.032394 .. 46.086565
[12:49:23.624] <TB1> INFO: Expecting 208000 events.
[12:49:33.395] <TB1> INFO: 208000 events read in total (9179ms).
[12:49:33.396] <TB1> INFO: Test took 10006ms.
[12:49:33.471] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 56 (-1/-1) hits flags = 528 (plus default)
[12:49:33.482] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:49:33.482] <TB1> INFO: run 1 of 1
[12:49:33.760] <TB1> INFO: Expecting 1397760 events.
[12:50:02.348] <TB1> INFO: 663424 events read in total (27996ms).
[12:50:30.200] <TB1> INFO: 1326184 events read in total (55848ms).
[12:50:33.602] <TB1> INFO: 1397760 events read in total (59251ms).
[12:50:33.627] <TB1> INFO: Test took 60145ms.
[12:50:46.339] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:50:46.339] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:50:46.350] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:50:46.350] <TB1> INFO: run 1 of 1
[12:50:46.641] <TB1> INFO: Expecting 1364480 events.
[12:51:15.046] <TB1> INFO: 666936 events read in total (27813ms).
[12:51:43.152] <TB1> INFO: 1333560 events read in total (55919ms).
[12:51:45.043] <TB1> INFO: 1364480 events read in total (57810ms).
[12:51:45.073] <TB1> INFO: Test took 58724ms.
[12:51:57.113] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C0.dat
[12:51:57.113] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C1.dat
[12:51:57.113] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C2.dat
[12:51:57.113] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C3.dat
[12:51:57.114] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C4.dat
[12:51:57.114] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C5.dat
[12:51:57.114] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C6.dat
[12:51:57.114] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C7.dat
[12:51:57.114] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C8.dat
[12:51:57.114] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C9.dat
[12:51:57.114] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C10.dat
[12:51:57.114] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C11.dat
[12:51:57.114] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C12.dat
[12:51:57.114] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C13.dat
[12:51:57.114] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C14.dat
[12:51:57.115] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C15.dat
[12:51:57.115] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C0.dat
[12:51:57.122] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C1.dat
[12:51:57.130] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C2.dat
[12:51:57.138] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C3.dat
[12:51:57.145] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C4.dat
[12:51:57.153] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C5.dat
[12:51:57.161] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C6.dat
[12:51:57.168] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C7.dat
[12:51:57.176] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C8.dat
[12:51:57.184] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C9.dat
[12:51:57.191] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C10.dat
[12:51:57.199] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C11.dat
[12:51:57.207] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C12.dat
[12:51:57.214] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C13.dat
[12:51:57.222] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C14.dat
[12:51:57.230] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C15.dat
[12:51:57.237] <TB1> INFO: PixTestTrim::trimTest() done
[12:51:57.237] <TB1> INFO: vtrim: 139 135 131 131 139 130 134 131 124 131 130 120 147 116 125 149
[12:51:57.237] <TB1> INFO: vthrcomp: 124 120 121 112 123 117 121 120 107 127 128 125 127 115 116 119
[12:51:57.237] <TB1> INFO: vcal mean: 34.94 34.89 34.93 34.94 34.97 34.92 34.92 34.91 35.19 34.97 34.89 34.84 34.90 34.94 34.93 34.96
[12:51:57.237] <TB1> INFO: vcal RMS: 1.21 1.08 1.09 1.04 1.19 1.10 1.02 1.00 1.56 1.46 1.04 1.20 1.23 1.13 1.12 1.19
[12:51:57.238] <TB1> INFO: bits mean: 9.97 10.25 10.01 9.92 10.02 9.86 10.36 9.86 8.69 10.21 10.30 9.61 9.96 9.12 9.85 10.72
[12:51:57.238] <TB1> INFO: bits RMS: 2.44 2.37 2.54 2.41 2.48 2.57 2.27 2.52 2.68 2.65 2.42 2.86 2.54 2.82 2.62 2.30
[12:51:57.245] <TB1> INFO: ----------------------------------------------------------------------
[12:51:57.245] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:51:57.245] <TB1> INFO: ----------------------------------------------------------------------
[12:51:57.248] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:51:57.260] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:51:57.260] <TB1> INFO: run 1 of 1
[12:51:57.541] <TB1> INFO: Expecting 4160000 events.
[12:52:30.333] <TB1> INFO: 748705 events read in total (32200ms).
[12:53:02.379] <TB1> INFO: 1491540 events read in total (64246ms).
[12:53:34.273] <TB1> INFO: 2230720 events read in total (96140ms).
[12:54:06.409] <TB1> INFO: 2964785 events read in total (128276ms).
[12:54:38.100] <TB1> INFO: 3696365 events read in total (159967ms).
[12:54:58.547] <TB1> INFO: 4160000 events read in total (180414ms).
[12:54:58.599] <TB1> INFO: Test took 181339ms.
[12:55:26.632] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[12:55:26.641] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:55:26.641] <TB1> INFO: run 1 of 1
[12:55:26.874] <TB1> INFO: Expecting 4326400 events.
[12:55:58.827] <TB1> INFO: 714115 events read in total (31361ms).
[12:56:30.087] <TB1> INFO: 1423460 events read in total (62621ms).
[12:57:01.336] <TB1> INFO: 2129665 events read in total (93871ms).
[12:57:32.542] <TB1> INFO: 2831600 events read in total (125076ms).
[12:58:03.211] <TB1> INFO: 3530745 events read in total (155745ms).
[12:58:34.325] <TB1> INFO: 4230295 events read in total (186859ms).
[12:58:38.980] <TB1> INFO: 4326400 events read in total (191514ms).
[12:58:39.037] <TB1> INFO: Test took 192396ms.
[12:59:07.704] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[12:59:07.712] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:59:07.712] <TB1> INFO: run 1 of 1
[12:59:07.944] <TB1> INFO: Expecting 4264000 events.
[12:59:39.840] <TB1> INFO: 717445 events read in total (31304ms).
[13:00:11.351] <TB1> INFO: 1430540 events read in total (62815ms).
[13:00:42.619] <TB1> INFO: 2140045 events read in total (94083ms).
[13:01:13.859] <TB1> INFO: 2844580 events read in total (125323ms).
[13:01:44.844] <TB1> INFO: 3547205 events read in total (156308ms).
[13:02:16.109] <TB1> INFO: 4252070 events read in total (187573ms).
[13:02:17.015] <TB1> INFO: 4264000 events read in total (188479ms).
[13:02:17.072] <TB1> INFO: Test took 189360ms.
[13:02:45.575] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[13:02:45.584] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:02:45.584] <TB1> INFO: run 1 of 1
[13:02:45.816] <TB1> INFO: Expecting 4284800 events.
[13:03:17.823] <TB1> INFO: 716275 events read in total (31413ms).
[13:03:49.178] <TB1> INFO: 1428195 events read in total (62768ms).
[13:04:20.926] <TB1> INFO: 2136385 events read in total (94517ms).
[13:04:52.150] <TB1> INFO: 2839945 events read in total (125740ms).
[13:05:23.044] <TB1> INFO: 3541310 events read in total (156634ms).
[13:05:54.088] <TB1> INFO: 4244260 events read in total (187678ms).
[13:05:56.301] <TB1> INFO: 4284800 events read in total (189891ms).
[13:05:56.355] <TB1> INFO: Test took 190770ms.
[13:06:23.577] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[13:06:23.586] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:06:23.586] <TB1> INFO: run 1 of 1
[13:06:23.817] <TB1> INFO: Expecting 4326400 events.
[13:06:55.853] <TB1> INFO: 713960 events read in total (31444ms).
[13:07:27.442] <TB1> INFO: 1423415 events read in total (63033ms).
[13:07:58.700] <TB1> INFO: 2129500 events read in total (94291ms).
[13:08:29.495] <TB1> INFO: 2831210 events read in total (125086ms).
[13:09:00.245] <TB1> INFO: 3530410 events read in total (155836ms).
[13:09:31.145] <TB1> INFO: 4229805 events read in total (186736ms).
[13:09:35.629] <TB1> INFO: 4326400 events read in total (191220ms).
[13:09:35.705] <TB1> INFO: Test took 192119ms.
[13:10:02.689] <TB1> INFO: PixTestTrim::trimBitTest() done
[13:10:02.690] <TB1> INFO: PixTestTrim::doTest() done, duration: 2534 seconds
[13:10:02.690] <TB1> INFO: Decoding statistics:
[13:10:02.690] <TB1> INFO: General information:
[13:10:02.690] <TB1> INFO: 16bit words read: 0
[13:10:02.690] <TB1> INFO: valid events total: 0
[13:10:02.690] <TB1> INFO: empty events: 0
[13:10:02.690] <TB1> INFO: valid events with pixels: 0
[13:10:02.690] <TB1> INFO: valid pixel hits: 0
[13:10:02.690] <TB1> INFO: Event errors: 0
[13:10:02.690] <TB1> INFO: start marker: 0
[13:10:02.690] <TB1> INFO: stop marker: 0
[13:10:02.690] <TB1> INFO: overflow: 0
[13:10:02.690] <TB1> INFO: invalid 5bit words: 0
[13:10:02.690] <TB1> INFO: invalid XOR eye diagram: 0
[13:10:02.690] <TB1> INFO: frame (failed synchr.): 0
[13:10:02.690] <TB1> INFO: idle data (no TBM trl): 0
[13:10:02.690] <TB1> INFO: no data (only TBM hdr): 0
[13:10:02.690] <TB1> INFO: TBM errors: 0
[13:10:02.690] <TB1> INFO: flawed TBM headers: 0
[13:10:02.690] <TB1> INFO: flawed TBM trailers: 0
[13:10:02.690] <TB1> INFO: event ID mismatches: 0
[13:10:02.690] <TB1> INFO: ROC errors: 0
[13:10:02.690] <TB1> INFO: missing ROC header(s): 0
[13:10:02.690] <TB1> INFO: misplaced readback start: 0
[13:10:02.690] <TB1> INFO: Pixel decoding errors: 0
[13:10:02.691] <TB1> INFO: pixel data incomplete: 0
[13:10:02.691] <TB1> INFO: pixel address: 0
[13:10:02.691] <TB1> INFO: pulse height fill bit: 0
[13:10:02.691] <TB1> INFO: buffer corruption: 0
[13:10:03.309] <TB1> INFO: ######################################################################
[13:10:03.309] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:10:03.309] <TB1> INFO: ######################################################################
[13:10:03.604] <TB1> INFO: Expecting 41600 events.
[13:10:07.035] <TB1> INFO: 41600 events read in total (2840ms).
[13:10:07.036] <TB1> INFO: Test took 3725ms.
[13:10:07.475] <TB1> INFO: Expecting 41600 events.
[13:10:11.120] <TB1> INFO: 41600 events read in total (3053ms).
[13:10:11.121] <TB1> INFO: Test took 3880ms.
[13:10:11.412] <TB1> INFO: Expecting 41600 events.
[13:10:15.016] <TB1> INFO: 41600 events read in total (3012ms).
[13:10:15.017] <TB1> INFO: Test took 3869ms.
[13:10:15.305] <TB1> INFO: Expecting 41600 events.
[13:10:18.920] <TB1> INFO: 41600 events read in total (3023ms).
[13:10:18.921] <TB1> INFO: Test took 3881ms.
[13:10:19.213] <TB1> INFO: Expecting 41600 events.
[13:10:22.789] <TB1> INFO: 41600 events read in total (2984ms).
[13:10:22.789] <TB1> INFO: Test took 3841ms.
[13:10:23.077] <TB1> INFO: Expecting 41600 events.
[13:10:26.540] <TB1> INFO: 41600 events read in total (2871ms).
[13:10:26.541] <TB1> INFO: Test took 3729ms.
[13:10:26.829] <TB1> INFO: Expecting 41600 events.
[13:10:30.449] <TB1> INFO: 41600 events read in total (3028ms).
[13:10:30.450] <TB1> INFO: Test took 3886ms.
[13:10:30.738] <TB1> INFO: Expecting 41600 events.
[13:10:34.343] <TB1> INFO: 41600 events read in total (3013ms).
[13:10:34.343] <TB1> INFO: Test took 3870ms.
[13:10:34.632] <TB1> INFO: Expecting 41600 events.
[13:10:38.150] <TB1> INFO: 41600 events read in total (2927ms).
[13:10:38.151] <TB1> INFO: Test took 3784ms.
[13:10:38.463] <TB1> INFO: Expecting 41600 events.
[13:10:42.039] <TB1> INFO: 41600 events read in total (2985ms).
[13:10:42.040] <TB1> INFO: Test took 3866ms.
[13:10:42.337] <TB1> INFO: Expecting 41600 events.
[13:10:45.962] <TB1> INFO: 41600 events read in total (3034ms).
[13:10:45.963] <TB1> INFO: Test took 3900ms.
[13:10:46.254] <TB1> INFO: Expecting 41600 events.
[13:10:49.730] <TB1> INFO: 41600 events read in total (2884ms).
[13:10:49.731] <TB1> INFO: Test took 3741ms.
[13:10:50.019] <TB1> INFO: Expecting 41600 events.
[13:10:53.539] <TB1> INFO: 41600 events read in total (2928ms).
[13:10:53.540] <TB1> INFO: Test took 3786ms.
[13:10:53.831] <TB1> INFO: Expecting 41600 events.
[13:10:57.304] <TB1> INFO: 41600 events read in total (2881ms).
[13:10:57.304] <TB1> INFO: Test took 3737ms.
[13:10:57.623] <TB1> INFO: Expecting 41600 events.
[13:11:01.356] <TB1> INFO: 41600 events read in total (3141ms).
[13:11:01.356] <TB1> INFO: Test took 4025ms.
[13:11:01.648] <TB1> INFO: Expecting 41600 events.
[13:11:05.318] <TB1> INFO: 41600 events read in total (3079ms).
[13:11:05.319] <TB1> INFO: Test took 3936ms.
[13:11:05.606] <TB1> INFO: Expecting 41600 events.
[13:11:09.282] <TB1> INFO: 41600 events read in total (3084ms).
[13:11:09.283] <TB1> INFO: Test took 3941ms.
[13:11:09.573] <TB1> INFO: Expecting 41600 events.
[13:11:13.297] <TB1> INFO: 41600 events read in total (3132ms).
[13:11:13.298] <TB1> INFO: Test took 3989ms.
[13:11:13.586] <TB1> INFO: Expecting 41600 events.
[13:11:17.201] <TB1> INFO: 41600 events read in total (3024ms).
[13:11:17.202] <TB1> INFO: Test took 3881ms.
[13:11:17.490] <TB1> INFO: Expecting 41600 events.
[13:11:21.010] <TB1> INFO: 41600 events read in total (2929ms).
[13:11:21.011] <TB1> INFO: Test took 3786ms.
[13:11:21.298] <TB1> INFO: Expecting 41600 events.
[13:11:24.925] <TB1> INFO: 41600 events read in total (3035ms).
[13:11:24.926] <TB1> INFO: Test took 3892ms.
[13:11:25.274] <TB1> INFO: Expecting 41600 events.
[13:11:28.849] <TB1> INFO: 41600 events read in total (2984ms).
[13:11:28.850] <TB1> INFO: Test took 3897ms.
[13:11:29.138] <TB1> INFO: Expecting 41600 events.
[13:11:32.727] <TB1> INFO: 41600 events read in total (2998ms).
[13:11:32.727] <TB1> INFO: Test took 3854ms.
[13:11:33.015] <TB1> INFO: Expecting 41600 events.
[13:11:36.605] <TB1> INFO: 41600 events read in total (2998ms).
[13:11:36.606] <TB1> INFO: Test took 3855ms.
[13:11:36.894] <TB1> INFO: Expecting 41600 events.
[13:11:40.515] <TB1> INFO: 41600 events read in total (3030ms).
[13:11:40.516] <TB1> INFO: Test took 3887ms.
[13:11:40.804] <TB1> INFO: Expecting 41600 events.
[13:11:44.274] <TB1> INFO: 41600 events read in total (2878ms).
[13:11:44.275] <TB1> INFO: Test took 3735ms.
[13:11:44.563] <TB1> INFO: Expecting 41600 events.
[13:11:48.102] <TB1> INFO: 41600 events read in total (2948ms).
[13:11:48.103] <TB1> INFO: Test took 3805ms.
[13:11:48.395] <TB1> INFO: Expecting 41600 events.
[13:11:52.018] <TB1> INFO: 41600 events read in total (3032ms).
[13:11:52.019] <TB1> INFO: Test took 3889ms.
[13:11:52.308] <TB1> INFO: Expecting 41600 events.
[13:11:56.119] <TB1> INFO: 41600 events read in total (3217ms).
[13:11:56.120] <TB1> INFO: Test took 4077ms.
[13:11:56.412] <TB1> INFO: Expecting 2560 events.
[13:11:57.301] <TB1> INFO: 2560 events read in total (297ms).
[13:11:57.302] <TB1> INFO: Test took 1166ms.
[13:11:57.609] <TB1> INFO: Expecting 2560 events.
[13:11:58.493] <TB1> INFO: 2560 events read in total (292ms).
[13:11:58.493] <TB1> INFO: Test took 1191ms.
[13:11:58.801] <TB1> INFO: Expecting 2560 events.
[13:11:59.686] <TB1> INFO: 2560 events read in total (293ms).
[13:11:59.686] <TB1> INFO: Test took 1192ms.
[13:11:59.993] <TB1> INFO: Expecting 2560 events.
[13:12:00.879] <TB1> INFO: 2560 events read in total (294ms).
[13:12:00.879] <TB1> INFO: Test took 1193ms.
[13:12:01.187] <TB1> INFO: Expecting 2560 events.
[13:12:02.065] <TB1> INFO: 2560 events read in total (286ms).
[13:12:02.065] <TB1> INFO: Test took 1185ms.
[13:12:02.373] <TB1> INFO: Expecting 2560 events.
[13:12:03.251] <TB1> INFO: 2560 events read in total (286ms).
[13:12:03.251] <TB1> INFO: Test took 1186ms.
[13:12:03.559] <TB1> INFO: Expecting 2560 events.
[13:12:04.435] <TB1> INFO: 2560 events read in total (284ms).
[13:12:04.435] <TB1> INFO: Test took 1184ms.
[13:12:04.743] <TB1> INFO: Expecting 2560 events.
[13:12:05.620] <TB1> INFO: 2560 events read in total (285ms).
[13:12:05.620] <TB1> INFO: Test took 1184ms.
[13:12:05.929] <TB1> INFO: Expecting 2560 events.
[13:12:06.807] <TB1> INFO: 2560 events read in total (287ms).
[13:12:06.807] <TB1> INFO: Test took 1186ms.
[13:12:07.115] <TB1> INFO: Expecting 2560 events.
[13:12:07.997] <TB1> INFO: 2560 events read in total (291ms).
[13:12:07.997] <TB1> INFO: Test took 1190ms.
[13:12:08.305] <TB1> INFO: Expecting 2560 events.
[13:12:09.189] <TB1> INFO: 2560 events read in total (292ms).
[13:12:09.189] <TB1> INFO: Test took 1191ms.
[13:12:09.497] <TB1> INFO: Expecting 2560 events.
[13:12:10.377] <TB1> INFO: 2560 events read in total (288ms).
[13:12:10.377] <TB1> INFO: Test took 1187ms.
[13:12:10.685] <TB1> INFO: Expecting 2560 events.
[13:12:11.568] <TB1> INFO: 2560 events read in total (291ms).
[13:12:11.568] <TB1> INFO: Test took 1191ms.
[13:12:11.875] <TB1> INFO: Expecting 2560 events.
[13:12:12.760] <TB1> INFO: 2560 events read in total (293ms).
[13:12:12.760] <TB1> INFO: Test took 1192ms.
[13:12:13.067] <TB1> INFO: Expecting 2560 events.
[13:12:13.950] <TB1> INFO: 2560 events read in total (291ms).
[13:12:13.951] <TB1> INFO: Test took 1191ms.
[13:12:14.258] <TB1> INFO: Expecting 2560 events.
[13:12:15.140] <TB1> INFO: 2560 events read in total (290ms).
[13:12:15.140] <TB1> INFO: Test took 1190ms.
[13:12:15.143] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:12:15.449] <TB1> INFO: Expecting 655360 events.
[13:12:30.063] <TB1> INFO: 655360 events read in total (14022ms).
[13:12:30.074] <TB1> INFO: Expecting 655360 events.
[13:12:44.522] <TB1> INFO: 655360 events read in total (14045ms).
[13:12:44.536] <TB1> INFO: Expecting 655360 events.
[13:12:58.000] <TB1> INFO: 655360 events read in total (14061ms).
[13:12:59.017] <TB1> INFO: Expecting 655360 events.
[13:13:13.481] <TB1> INFO: 655360 events read in total (14061ms).
[13:13:13.504] <TB1> INFO: Expecting 655360 events.
[13:13:27.990] <TB1> INFO: 655360 events read in total (14083ms).
[13:13:28.019] <TB1> INFO: Expecting 655360 events.
[13:13:42.562] <TB1> INFO: 655360 events read in total (14140ms).
[13:13:42.593] <TB1> INFO: Expecting 655360 events.
[13:13:56.991] <TB1> INFO: 655360 events read in total (13995ms).
[13:13:57.025] <TB1> INFO: Expecting 655360 events.
[13:14:11.531] <TB1> INFO: 655360 events read in total (14104ms).
[13:14:11.588] <TB1> INFO: Expecting 655360 events.
[13:14:26.028] <TB1> INFO: 655360 events read in total (14039ms).
[13:14:26.072] <TB1> INFO: Expecting 655360 events.
[13:14:40.574] <TB1> INFO: 655360 events read in total (14099ms).
[13:14:40.622] <TB1> INFO: Expecting 655360 events.
[13:14:55.228] <TB1> INFO: 655360 events read in total (14203ms).
[13:14:55.307] <TB1> INFO: Expecting 655360 events.
[13:15:09.714] <TB1> INFO: 655360 events read in total (14004ms).
[13:15:09.789] <TB1> INFO: Expecting 655360 events.
[13:15:24.450] <TB1> INFO: 655360 events read in total (14258ms).
[13:15:24.514] <TB1> INFO: Expecting 655360 events.
[13:15:38.952] <TB1> INFO: 655360 events read in total (14035ms).
[13:15:39.021] <TB1> INFO: Expecting 655360 events.
[13:15:53.655] <TB1> INFO: 655360 events read in total (14231ms).
[13:15:53.725] <TB1> INFO: Expecting 655360 events.
[13:16:08.293] <TB1> INFO: 655360 events read in total (14165ms).
[13:16:08.368] <TB1> INFO: Test took 233225ms.
[13:16:08.448] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:08.715] <TB1> INFO: Expecting 655360 events.
[13:16:23.221] <TB1> INFO: 655360 events read in total (13915ms).
[13:16:23.231] <TB1> INFO: Expecting 655360 events.
[13:16:37.616] <TB1> INFO: 655360 events read in total (13982ms).
[13:16:37.631] <TB1> INFO: Expecting 655360 events.
[13:16:52.166] <TB1> INFO: 655360 events read in total (14132ms).
[13:16:52.193] <TB1> INFO: Expecting 655360 events.
[13:17:06.431] <TB1> INFO: 655360 events read in total (13835ms).
[13:17:06.453] <TB1> INFO: Expecting 655360 events.
[13:17:20.855] <TB1> INFO: 655360 events read in total (13999ms).
[13:17:20.884] <TB1> INFO: Expecting 655360 events.
[13:17:35.419] <TB1> INFO: 655360 events read in total (14132ms).
[13:17:35.463] <TB1> INFO: Expecting 655360 events.
[13:17:49.816] <TB1> INFO: 655360 events read in total (13950ms).
[13:17:49.851] <TB1> INFO: Expecting 655360 events.
[13:18:04.369] <TB1> INFO: 655360 events read in total (14115ms).
[13:18:04.407] <TB1> INFO: Expecting 655360 events.
[13:18:18.715] <TB1> INFO: 655360 events read in total (13905ms).
[13:18:18.757] <TB1> INFO: Expecting 655360 events.
[13:18:32.894] <TB1> INFO: 655360 events read in total (13734ms).
[13:18:32.943] <TB1> INFO: Expecting 655360 events.
[13:18:47.474] <TB1> INFO: 655360 events read in total (14128ms).
[13:18:47.553] <TB1> INFO: Expecting 655360 events.
[13:19:01.791] <TB1> INFO: 655360 events read in total (13835ms).
[13:19:01.845] <TB1> INFO: Expecting 655360 events.
[13:19:16.260] <TB1> INFO: 655360 events read in total (14012ms).
[13:19:16.321] <TB1> INFO: Expecting 655360 events.
[13:19:30.705] <TB1> INFO: 655360 events read in total (13981ms).
[13:19:30.770] <TB1> INFO: Expecting 655360 events.
[13:19:45.465] <TB1> INFO: 655360 events read in total (14292ms).
[13:19:45.568] <TB1> INFO: Expecting 655360 events.
[13:19:59.916] <TB1> INFO: 655360 events read in total (13946ms).
[13:19:59.989] <TB1> INFO: Test took 231541ms.
[13:20:00.145] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.150] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:20:00.155] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.159] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.164] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.169] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:20:00.175] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.180] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.185] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:20:00.190] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.195] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:20:00.199] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.204] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.209] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.214] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.218] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:20:00.223] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:20:00.228] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:20:00.234] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:20:00.239] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:20:00.244] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[13:20:00.248] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[13:20:00.253] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[13:20:00.258] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.263] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.268] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.273] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.278] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:20:00.283] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:20:00.287] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:20:00.292] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:20:00.297] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:20:00.302] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:20:00.307] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[13:20:00.341] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C0.dat
[13:20:00.341] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C1.dat
[13:20:00.341] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C2.dat
[13:20:00.341] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C3.dat
[13:20:00.341] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C4.dat
[13:20:00.341] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C5.dat
[13:20:00.342] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C6.dat
[13:20:00.342] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C7.dat
[13:20:00.342] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C8.dat
[13:20:00.342] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C9.dat
[13:20:00.342] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C10.dat
[13:20:00.342] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C11.dat
[13:20:00.342] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C12.dat
[13:20:00.342] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C13.dat
[13:20:00.342] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C14.dat
[13:20:00.342] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C15.dat
[13:20:00.638] <TB1> INFO: Expecting 41600 events.
[13:20:03.765] <TB1> INFO: 41600 events read in total (2536ms).
[13:20:03.766] <TB1> INFO: Test took 3421ms.
[13:20:04.209] <TB1> INFO: Expecting 41600 events.
[13:20:07.332] <TB1> INFO: 41600 events read in total (2532ms).
[13:20:07.332] <TB1> INFO: Test took 3355ms.
[13:20:07.777] <TB1> INFO: Expecting 41600 events.
[13:20:10.957] <TB1> INFO: 41600 events read in total (2588ms).
[13:20:10.958] <TB1> INFO: Test took 3412ms.
[13:20:11.177] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:11.266] <TB1> INFO: Expecting 2560 events.
[13:20:12.153] <TB1> INFO: 2560 events read in total (296ms).
[13:20:12.154] <TB1> INFO: Test took 977ms.
[13:20:12.155] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:12.462] <TB1> INFO: Expecting 2560 events.
[13:20:13.346] <TB1> INFO: 2560 events read in total (292ms).
[13:20:13.347] <TB1> INFO: Test took 1192ms.
[13:20:13.348] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:13.655] <TB1> INFO: Expecting 2560 events.
[13:20:14.543] <TB1> INFO: 2560 events read in total (296ms).
[13:20:14.543] <TB1> INFO: Test took 1195ms.
[13:20:14.545] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:14.852] <TB1> INFO: Expecting 2560 events.
[13:20:15.736] <TB1> INFO: 2560 events read in total (293ms).
[13:20:15.736] <TB1> INFO: Test took 1191ms.
[13:20:15.738] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:16.044] <TB1> INFO: Expecting 2560 events.
[13:20:16.932] <TB1> INFO: 2560 events read in total (296ms).
[13:20:16.932] <TB1> INFO: Test took 1194ms.
[13:20:16.935] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:17.240] <TB1> INFO: Expecting 2560 events.
[13:20:18.124] <TB1> INFO: 2560 events read in total (292ms).
[13:20:18.124] <TB1> INFO: Test took 1189ms.
[13:20:18.126] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:18.433] <TB1> INFO: Expecting 2560 events.
[13:20:19.317] <TB1> INFO: 2560 events read in total (293ms).
[13:20:19.317] <TB1> INFO: Test took 1191ms.
[13:20:19.319] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:19.626] <TB1> INFO: Expecting 2560 events.
[13:20:20.509] <TB1> INFO: 2560 events read in total (292ms).
[13:20:20.509] <TB1> INFO: Test took 1190ms.
[13:20:20.511] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:20.817] <TB1> INFO: Expecting 2560 events.
[13:20:21.697] <TB1> INFO: 2560 events read in total (288ms).
[13:20:21.697] <TB1> INFO: Test took 1186ms.
[13:20:21.699] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:22.006] <TB1> INFO: Expecting 2560 events.
[13:20:22.886] <TB1> INFO: 2560 events read in total (289ms).
[13:20:22.886] <TB1> INFO: Test took 1187ms.
[13:20:22.888] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:23.194] <TB1> INFO: Expecting 2560 events.
[13:20:24.078] <TB1> INFO: 2560 events read in total (292ms).
[13:20:24.078] <TB1> INFO: Test took 1190ms.
[13:20:24.080] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:24.387] <TB1> INFO: Expecting 2560 events.
[13:20:25.266] <TB1> INFO: 2560 events read in total (288ms).
[13:20:25.266] <TB1> INFO: Test took 1186ms.
[13:20:25.268] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:25.575] <TB1> INFO: Expecting 2560 events.
[13:20:26.458] <TB1> INFO: 2560 events read in total (292ms).
[13:20:26.459] <TB1> INFO: Test took 1191ms.
[13:20:26.460] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:26.767] <TB1> INFO: Expecting 2560 events.
[13:20:27.646] <TB1> INFO: 2560 events read in total (288ms).
[13:20:27.646] <TB1> INFO: Test took 1186ms.
[13:20:27.648] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:27.955] <TB1> INFO: Expecting 2560 events.
[13:20:28.836] <TB1> INFO: 2560 events read in total (290ms).
[13:20:28.836] <TB1> INFO: Test took 1188ms.
[13:20:28.838] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:29.145] <TB1> INFO: Expecting 2560 events.
[13:20:30.025] <TB1> INFO: 2560 events read in total (289ms).
[13:20:30.025] <TB1> INFO: Test took 1187ms.
[13:20:30.027] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:30.333] <TB1> INFO: Expecting 2560 events.
[13:20:31.215] <TB1> INFO: 2560 events read in total (290ms).
[13:20:31.216] <TB1> INFO: Test took 1189ms.
[13:20:31.217] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:31.524] <TB1> INFO: Expecting 2560 events.
[13:20:32.407] <TB1> INFO: 2560 events read in total (292ms).
[13:20:32.407] <TB1> INFO: Test took 1190ms.
[13:20:32.409] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:32.716] <TB1> INFO: Expecting 2560 events.
[13:20:33.596] <TB1> INFO: 2560 events read in total (288ms).
[13:20:33.596] <TB1> INFO: Test took 1187ms.
[13:20:33.598] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:33.904] <TB1> INFO: Expecting 2560 events.
[13:20:34.789] <TB1> INFO: 2560 events read in total (293ms).
[13:20:34.789] <TB1> INFO: Test took 1191ms.
[13:20:34.791] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:35.097] <TB1> INFO: Expecting 2560 events.
[13:20:35.977] <TB1> INFO: 2560 events read in total (288ms).
[13:20:35.977] <TB1> INFO: Test took 1186ms.
[13:20:35.979] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:36.285] <TB1> INFO: Expecting 2560 events.
[13:20:37.163] <TB1> INFO: 2560 events read in total (286ms).
[13:20:37.163] <TB1> INFO: Test took 1184ms.
[13:20:37.165] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:37.471] <TB1> INFO: Expecting 2560 events.
[13:20:38.351] <TB1> INFO: 2560 events read in total (288ms).
[13:20:38.352] <TB1> INFO: Test took 1187ms.
[13:20:38.353] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:38.661] <TB1> INFO: Expecting 2560 events.
[13:20:39.544] <TB1> INFO: 2560 events read in total (292ms).
[13:20:39.544] <TB1> INFO: Test took 1191ms.
[13:20:39.546] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:39.852] <TB1> INFO: Expecting 2560 events.
[13:20:40.736] <TB1> INFO: 2560 events read in total (292ms).
[13:20:40.736] <TB1> INFO: Test took 1190ms.
[13:20:40.738] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:41.046] <TB1> INFO: Expecting 2560 events.
[13:20:41.933] <TB1> INFO: 2560 events read in total (295ms).
[13:20:41.933] <TB1> INFO: Test took 1195ms.
[13:20:41.935] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:42.241] <TB1> INFO: Expecting 2560 events.
[13:20:43.126] <TB1> INFO: 2560 events read in total (293ms).
[13:20:43.126] <TB1> INFO: Test took 1191ms.
[13:20:43.128] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:43.434] <TB1> INFO: Expecting 2560 events.
[13:20:44.318] <TB1> INFO: 2560 events read in total (292ms).
[13:20:44.319] <TB1> INFO: Test took 1191ms.
[13:20:44.321] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:44.627] <TB1> INFO: Expecting 2560 events.
[13:20:45.508] <TB1> INFO: 2560 events read in total (289ms).
[13:20:45.509] <TB1> INFO: Test took 1188ms.
[13:20:45.510] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:45.817] <TB1> INFO: Expecting 2560 events.
[13:20:46.701] <TB1> INFO: 2560 events read in total (292ms).
[13:20:46.701] <TB1> INFO: Test took 1191ms.
[13:20:46.703] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:47.010] <TB1> INFO: Expecting 2560 events.
[13:20:47.893] <TB1> INFO: 2560 events read in total (292ms).
[13:20:47.893] <TB1> INFO: Test took 1190ms.
[13:20:47.895] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:48.202] <TB1> INFO: Expecting 2560 events.
[13:20:49.086] <TB1> INFO: 2560 events read in total (293ms).
[13:20:49.086] <TB1> INFO: Test took 1191ms.
[13:20:49.548] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 646 seconds
[13:20:49.548] <TB1> INFO: PH scale (per ROC): 45 38 74 61 66 55 65 52 53 44 48 70 30 54 60 48
[13:20:49.548] <TB1> INFO: PH offset (per ROC): 99 90 124 127 129 121 129 131 121 109 90 127 81 129 129 89
[13:20:49.553] <TB1> INFO: Decoding statistics:
[13:20:49.553] <TB1> INFO: General information:
[13:20:49.553] <TB1> INFO: 16bit words read: 127890
[13:20:49.553] <TB1> INFO: valid events total: 20480
[13:20:49.553] <TB1> INFO: empty events: 17975
[13:20:49.553] <TB1> INFO: valid events with pixels: 2505
[13:20:49.553] <TB1> INFO: valid pixel hits: 2505
[13:20:49.553] <TB1> INFO: Event errors: 0
[13:20:49.553] <TB1> INFO: start marker: 0
[13:20:49.553] <TB1> INFO: stop marker: 0
[13:20:49.553] <TB1> INFO: overflow: 0
[13:20:49.553] <TB1> INFO: invalid 5bit words: 0
[13:20:49.553] <TB1> INFO: invalid XOR eye diagram: 0
[13:20:49.553] <TB1> INFO: frame (failed synchr.): 0
[13:20:49.554] <TB1> INFO: idle data (no TBM trl): 0
[13:20:49.554] <TB1> INFO: no data (only TBM hdr): 0
[13:20:49.554] <TB1> INFO: TBM errors: 0
[13:20:49.554] <TB1> INFO: flawed TBM headers: 0
[13:20:49.554] <TB1> INFO: flawed TBM trailers: 0
[13:20:49.554] <TB1> INFO: event ID mismatches: 0
[13:20:49.554] <TB1> INFO: ROC errors: 0
[13:20:49.554] <TB1> INFO: missing ROC header(s): 0
[13:20:49.554] <TB1> INFO: misplaced readback start: 0
[13:20:49.554] <TB1> INFO: Pixel decoding errors: 0
[13:20:49.554] <TB1> INFO: pixel data incomplete: 0
[13:20:49.554] <TB1> INFO: pixel address: 0
[13:20:49.554] <TB1> INFO: pulse height fill bit: 0
[13:20:49.554] <TB1> INFO: buffer corruption: 0
[13:20:49.816] <TB1> INFO: ######################################################################
[13:20:49.816] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:20:49.816] <TB1> INFO: ######################################################################
[13:20:49.829] <TB1> INFO: scanning low vcal = 10
[13:20:50.100] <TB1> INFO: Expecting 41600 events.
[13:20:53.670] <TB1> INFO: 41600 events read in total (2978ms).
[13:20:53.670] <TB1> INFO: Test took 3841ms.
[13:20:53.671] <TB1> INFO: scanning low vcal = 20
[13:20:53.968] <TB1> INFO: Expecting 41600 events.
[13:20:57.537] <TB1> INFO: 41600 events read in total (2977ms).
[13:20:57.537] <TB1> INFO: Test took 3865ms.
[13:20:57.539] <TB1> INFO: scanning low vcal = 30
[13:20:57.839] <TB1> INFO: Expecting 41600 events.
[13:21:01.478] <TB1> INFO: 41600 events read in total (3048ms).
[13:21:01.479] <TB1> INFO: Test took 3940ms.
[13:21:01.481] <TB1> INFO: scanning low vcal = 40
[13:21:01.758] <TB1> INFO: Expecting 41600 events.
[13:21:05.705] <TB1> INFO: 41600 events read in total (3355ms).
[13:21:05.706] <TB1> INFO: Test took 4225ms.
[13:21:05.709] <TB1> INFO: scanning low vcal = 50
[13:21:05.986] <TB1> INFO: Expecting 41600 events.
[13:21:09.961] <TB1> INFO: 41600 events read in total (3384ms).
[13:21:09.962] <TB1> INFO: Test took 4253ms.
[13:21:09.964] <TB1> INFO: scanning low vcal = 60
[13:21:10.241] <TB1> INFO: Expecting 41600 events.
[13:21:14.195] <TB1> INFO: 41600 events read in total (3363ms).
[13:21:14.195] <TB1> INFO: Test took 4231ms.
[13:21:14.198] <TB1> INFO: scanning low vcal = 70
[13:21:14.474] <TB1> INFO: Expecting 41600 events.
[13:21:18.476] <TB1> INFO: 41600 events read in total (3410ms).
[13:21:18.476] <TB1> INFO: Test took 4278ms.
[13:21:18.479] <TB1> INFO: scanning low vcal = 80
[13:21:18.756] <TB1> INFO: Expecting 41600 events.
[13:21:22.762] <TB1> INFO: 41600 events read in total (3415ms).
[13:21:22.763] <TB1> INFO: Test took 4284ms.
[13:21:22.766] <TB1> INFO: scanning low vcal = 90
[13:21:23.059] <TB1> INFO: Expecting 41600 events.
[13:21:27.064] <TB1> INFO: 41600 events read in total (3414ms).
[13:21:27.065] <TB1> INFO: Test took 4299ms.
[13:21:27.069] <TB1> INFO: scanning low vcal = 100
[13:21:27.344] <TB1> INFO: Expecting 41600 events.
[13:21:31.309] <TB1> INFO: 41600 events read in total (3373ms).
[13:21:31.310] <TB1> INFO: Test took 4241ms.
[13:21:31.312] <TB1> INFO: scanning low vcal = 110
[13:21:31.589] <TB1> INFO: Expecting 41600 events.
[13:21:35.606] <TB1> INFO: 41600 events read in total (3425ms).
[13:21:35.607] <TB1> INFO: Test took 4295ms.
[13:21:35.609] <TB1> INFO: scanning low vcal = 120
[13:21:35.886] <TB1> INFO: Expecting 41600 events.
[13:21:39.933] <TB1> INFO: 41600 events read in total (3456ms).
[13:21:39.934] <TB1> INFO: Test took 4325ms.
[13:21:39.936] <TB1> INFO: scanning low vcal = 130
[13:21:40.213] <TB1> INFO: Expecting 41600 events.
[13:21:44.161] <TB1> INFO: 41600 events read in total (3356ms).
[13:21:44.162] <TB1> INFO: Test took 4225ms.
[13:21:44.164] <TB1> INFO: scanning low vcal = 140
[13:21:44.441] <TB1> INFO: Expecting 41600 events.
[13:21:48.399] <TB1> INFO: 41600 events read in total (3367ms).
[13:21:48.399] <TB1> INFO: Test took 4235ms.
[13:21:48.402] <TB1> INFO: scanning low vcal = 150
[13:21:48.679] <TB1> INFO: Expecting 41600 events.
[13:21:52.636] <TB1> INFO: 41600 events read in total (3366ms).
[13:21:52.636] <TB1> INFO: Test took 4234ms.
[13:21:52.639] <TB1> INFO: scanning low vcal = 160
[13:21:52.916] <TB1> INFO: Expecting 41600 events.
[13:21:56.878] <TB1> INFO: 41600 events read in total (3371ms).
[13:21:56.878] <TB1> INFO: Test took 4239ms.
[13:21:56.881] <TB1> INFO: scanning low vcal = 170
[13:21:57.158] <TB1> INFO: Expecting 41600 events.
[13:22:01.123] <TB1> INFO: 41600 events read in total (3371ms).
[13:22:01.124] <TB1> INFO: Test took 4243ms.
[13:22:01.126] <TB1> INFO: scanning low vcal = 180
[13:22:01.403] <TB1> INFO: Expecting 41600 events.
[13:22:05.390] <TB1> INFO: 41600 events read in total (3396ms).
[13:22:05.391] <TB1> INFO: Test took 4265ms.
[13:22:05.393] <TB1> INFO: scanning low vcal = 190
[13:22:05.670] <TB1> INFO: Expecting 41600 events.
[13:22:09.648] <TB1> INFO: 41600 events read in total (3386ms).
[13:22:09.649] <TB1> INFO: Test took 4255ms.
[13:22:09.652] <TB1> INFO: scanning low vcal = 200
[13:22:09.945] <TB1> INFO: Expecting 41600 events.
[13:22:13.905] <TB1> INFO: 41600 events read in total (3369ms).
[13:22:13.906] <TB1> INFO: Test took 4254ms.
[13:22:13.909] <TB1> INFO: scanning low vcal = 210
[13:22:14.185] <TB1> INFO: Expecting 41600 events.
[13:22:18.142] <TB1> INFO: 41600 events read in total (3365ms).
[13:22:18.142] <TB1> INFO: Test took 4233ms.
[13:22:18.145] <TB1> INFO: scanning low vcal = 220
[13:22:18.422] <TB1> INFO: Expecting 41600 events.
[13:22:22.446] <TB1> INFO: 41600 events read in total (3433ms).
[13:22:22.447] <TB1> INFO: Test took 4302ms.
[13:22:22.449] <TB1> INFO: scanning low vcal = 230
[13:22:22.726] <TB1> INFO: Expecting 41600 events.
[13:22:26.770] <TB1> INFO: 41600 events read in total (3453ms).
[13:22:26.771] <TB1> INFO: Test took 4322ms.
[13:22:26.773] <TB1> INFO: scanning low vcal = 240
[13:22:27.050] <TB1> INFO: Expecting 41600 events.
[13:22:31.069] <TB1> INFO: 41600 events read in total (3428ms).
[13:22:31.070] <TB1> INFO: Test took 4297ms.
[13:22:31.073] <TB1> INFO: scanning low vcal = 250
[13:22:31.386] <TB1> INFO: Expecting 41600 events.
[13:22:35.395] <TB1> INFO: 41600 events read in total (3418ms).
[13:22:35.396] <TB1> INFO: Test took 4323ms.
[13:22:35.400] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[13:22:35.713] <TB1> INFO: Expecting 41600 events.
[13:22:39.835] <TB1> INFO: 41600 events read in total (3531ms).
[13:22:39.836] <TB1> INFO: Test took 4436ms.
[13:22:39.839] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[13:22:40.154] <TB1> INFO: Expecting 41600 events.
[13:22:44.140] <TB1> INFO: 41600 events read in total (3394ms).
[13:22:44.141] <TB1> INFO: Test took 4302ms.
[13:22:44.143] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[13:22:44.420] <TB1> INFO: Expecting 41600 events.
[13:22:48.411] <TB1> INFO: 41600 events read in total (3399ms).
[13:22:48.411] <TB1> INFO: Test took 4268ms.
[13:22:48.414] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[13:22:48.690] <TB1> INFO: Expecting 41600 events.
[13:22:52.682] <TB1> INFO: 41600 events read in total (3400ms).
[13:22:52.682] <TB1> INFO: Test took 4268ms.
[13:22:52.685] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:22:52.962] <TB1> INFO: Expecting 41600 events.
[13:22:56.965] <TB1> INFO: 41600 events read in total (3412ms).
[13:22:56.965] <TB1> INFO: Test took 4280ms.
[13:22:57.366] <TB1> INFO: PixTestGainPedestal::measure() done
[13:23:32.312] <TB1> INFO: PixTestGainPedestal::fit() done
[13:23:32.312] <TB1> INFO: non-linearity mean: 0.937 0.985 0.987 0.982 0.983 0.981 0.984 0.975 0.984 0.926 0.903 0.984 1.055 0.984 0.980 0.927
[13:23:32.312] <TB1> INFO: non-linearity RMS: 0.063 0.184 0.003 0.003 0.003 0.004 0.003 0.005 0.003 0.102 0.125 0.003 0.078 0.003 0.004 0.107
[13:23:32.312] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[13:23:32.335] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[13:23:32.358] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[13:23:32.381] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[13:23:32.403] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[13:23:32.426] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[13:23:32.449] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[13:23:32.472] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[13:23:32.494] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[13:23:32.517] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[13:23:32.540] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[13:23:32.563] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[13:23:32.586] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[13:23:32.609] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[13:23:32.632] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[13:23:32.654] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[13:23:32.677] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 162 seconds
[13:23:32.677] <TB1> INFO: Decoding statistics:
[13:23:32.677] <TB1> INFO: General information:
[13:23:32.677] <TB1> INFO: 16bit words read: 3327684
[13:23:32.677] <TB1> INFO: valid events total: 332800
[13:23:32.677] <TB1> INFO: empty events: 0
[13:23:32.677] <TB1> INFO: valid events with pixels: 332800
[13:23:32.677] <TB1> INFO: valid pixel hits: 665442
[13:23:32.677] <TB1> INFO: Event errors: 0
[13:23:32.677] <TB1> INFO: start marker: 0
[13:23:32.677] <TB1> INFO: stop marker: 0
[13:23:32.677] <TB1> INFO: overflow: 0
[13:23:32.677] <TB1> INFO: invalid 5bit words: 0
[13:23:32.677] <TB1> INFO: invalid XOR eye diagram: 0
[13:23:32.677] <TB1> INFO: frame (failed synchr.): 0
[13:23:32.677] <TB1> INFO: idle data (no TBM trl): 0
[13:23:32.677] <TB1> INFO: no data (only TBM hdr): 0
[13:23:32.677] <TB1> INFO: TBM errors: 0
[13:23:32.677] <TB1> INFO: flawed TBM headers: 0
[13:23:32.677] <TB1> INFO: flawed TBM trailers: 0
[13:23:32.677] <TB1> INFO: event ID mismatches: 0
[13:23:32.677] <TB1> INFO: ROC errors: 0
[13:23:32.677] <TB1> INFO: missing ROC header(s): 0
[13:23:32.677] <TB1> INFO: misplaced readback start: 0
[13:23:32.677] <TB1> INFO: Pixel decoding errors: 0
[13:23:32.677] <TB1> INFO: pixel data incomplete: 0
[13:23:32.677] <TB1> INFO: pixel address: 0
[13:23:32.677] <TB1> INFO: pulse height fill bit: 0
[13:23:32.677] <TB1> INFO: buffer corruption: 0
[13:23:32.693] <TB1> INFO: Decoding statistics:
[13:23:32.693] <TB1> INFO: General information:
[13:23:32.693] <TB1> INFO: 16bit words read: 3457110
[13:23:32.693] <TB1> INFO: valid events total: 353536
[13:23:32.693] <TB1> INFO: empty events: 18231
[13:23:32.693] <TB1> INFO: valid events with pixels: 335305
[13:23:32.693] <TB1> INFO: valid pixel hits: 667947
[13:23:32.693] <TB1> INFO: Event errors: 0
[13:23:32.693] <TB1> INFO: start marker: 0
[13:23:32.693] <TB1> INFO: stop marker: 0
[13:23:32.693] <TB1> INFO: overflow: 0
[13:23:32.693] <TB1> INFO: invalid 5bit words: 0
[13:23:32.693] <TB1> INFO: invalid XOR eye diagram: 0
[13:23:32.693] <TB1> INFO: frame (failed synchr.): 0
[13:23:32.693] <TB1> INFO: idle data (no TBM trl): 0
[13:23:32.693] <TB1> INFO: no data (only TBM hdr): 0
[13:23:32.693] <TB1> INFO: TBM errors: 0
[13:23:32.693] <TB1> INFO: flawed TBM headers: 0
[13:23:32.693] <TB1> INFO: flawed TBM trailers: 0
[13:23:32.693] <TB1> INFO: event ID mismatches: 0
[13:23:32.693] <TB1> INFO: ROC errors: 0
[13:23:32.693] <TB1> INFO: missing ROC header(s): 0
[13:23:32.693] <TB1> INFO: misplaced readback start: 0
[13:23:32.693] <TB1> INFO: Pixel decoding errors: 0
[13:23:32.693] <TB1> INFO: pixel data incomplete: 0
[13:23:32.693] <TB1> INFO: pixel address: 0
[13:23:32.693] <TB1> INFO: pulse height fill bit: 0
[13:23:32.693] <TB1> INFO: buffer corruption: 0
[13:23:32.693] <TB1> INFO: enter test to run
[13:23:32.693] <TB1> INFO: test: exit no parameter change
[13:23:32.731] <TB1> QUIET: Connection to board 153 closed.
[13:23:32.732] <TB1> INFO: pXar: this is the end, my friend