[09:03:25.822] <TB2> INFO: *** Welcome to pxar ***
[09:03:25.822] <TB2> INFO: *** Today: 2015/09/02
[09:03:25.822] <TB2> INFO: readRocDacs: /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C0.dat .. /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C15.dat
[09:03:25.825] <TB2> INFO: readTbmDacs: /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//tbmParameters_C0a.dat .. /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//tbmParameters_C0b.dat
[09:03:25.825] <TB2> INFO: readMaskFile: /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//defaultMaskFile.dat
[09:03:25.825] <TB2> INFO: readTrimFile: /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters_C0.dat .. /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters_C15.dat
[09:03:25.898] <TB2> INFO: clk: 4
[09:03:25.898] <TB2> INFO: ctr: 4
[09:03:25.898] <TB2> INFO: sda: 19
[09:03:25.898] <TB2> INFO: tin: 9
[09:03:25.898] <TB2> INFO: level: 15
[09:03:25.898] <TB2> INFO: triggerdelay: 0
[09:03:25.898] <TB2> QUIET: Instanciating API for pxar prod-10
[09:03:25.898] <TB2> INFO: Log level: INFO
[09:03:25.905] <TB2> INFO: Found DTB DTB_WXC55Z
[09:03:25.916] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[09:03:25.920] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.2
SW version: 4.4
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[09:03:25.922] <TB2> INFO: RPC call hashes of host and DTB match: 397073690
[09:03:27.456] <TB2> INFO: DUT info:
[09:03:27.457] <TB2> INFO: The DUT currently contains the following objects:
[09:03:27.457] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:03:27.457] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:03:27.457] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:03:27.457] <TB2> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[09:03:27.457] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.457] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[09:03:27.858] <TB2> INFO: enter 'restricted' command line mode
[09:03:27.858] <TB2> INFO: enter test to run
[09:03:27.858] <TB2> INFO: test: pretest no parameter change
[09:03:27.858] <TB2> INFO: running: pretest
[09:03:27.867] <TB2> INFO: ######################################################################
[09:03:27.867] <TB2> INFO: PixTestPretest::doTest()
[09:03:27.867] <TB2> INFO: ######################################################################
[09:03:27.869] <TB2> INFO: ----------------------------------------------------------------------
[09:03:27.869] <TB2> INFO: PixTestPretest::programROC()
[09:03:27.869] <TB2> INFO: ----------------------------------------------------------------------
[09:03:45.886] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[09:03:45.886] <TB2> INFO: IA differences per ROC: 17.7 18.5 20.9 18.5 16.9 18.5 18.5 17.7 20.1 17.7 19.3 17.7 20.1 19.3 18.5 20.1
[09:03:45.955] <TB2> INFO: ----------------------------------------------------------------------
[09:03:45.955] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[09:03:45.956] <TB2> INFO: ----------------------------------------------------------------------
[09:04:05.516] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 383.5 mA = 23.9688 mA/ROC
[09:04:05.519] <TB2> INFO: ----------------------------------------------------------------------
[09:04:05.519] <TB2> INFO: PixTestPretest::findWorkingPixel()
[09:04:05.519] <TB2> INFO: ----------------------------------------------------------------------
[09:04:05.658] <TB2> INFO: Expecting 231680 events.
[09:04:15.103] <TB2> INFO: 231680 events read in total (8726ms).
[09:04:15.167] <TB2> INFO: Test took 9643ms.
[09:04:15.415] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[09:04:15.445] <TB2> INFO: ----------------------------------------------------------------------
[09:04:15.445] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[09:04:15.445] <TB2> INFO: ----------------------------------------------------------------------
[09:04:15.579] <TB2> INFO: Expecting 231680 events.
[09:04:24.931] <TB2> INFO: 231680 events read in total (8635ms).
[09:04:24.935] <TB2> INFO: Test took 9487ms.
[09:04:25.259] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[09:04:25.259] <TB2> INFO: CalDel: 151 155 158 171 168 144 161 173 143 143 149 164 146 135 174 140
[09:04:25.259] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[09:04:25.262] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C0.dat
[09:04:25.262] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C1.dat
[09:04:25.263] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C2.dat
[09:04:25.263] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C3.dat
[09:04:25.263] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C4.dat
[09:04:25.263] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C5.dat
[09:04:25.263] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C6.dat
[09:04:25.264] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C7.dat
[09:04:25.264] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C8.dat
[09:04:25.264] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C9.dat
[09:04:25.264] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C10.dat
[09:04:25.264] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C11.dat
[09:04:25.265] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C12.dat
[09:04:25.265] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C13.dat
[09:04:25.265] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C14.dat
[09:04:25.265] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters_C15.dat
[09:04:25.265] <TB2> INFO: write tbm parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//tbmParameters_C0a.dat
[09:04:25.265] <TB2> INFO: write tbm parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//tbmParameters_C0b.dat
[09:04:25.266] <TB2> INFO: PixTestPretest::doTest() done, duration: 57 seconds
[09:04:25.356] <TB2> INFO: enter test to run
[09:04:25.356] <TB2> INFO: test: fulltest no parameter change
[09:04:25.356] <TB2> INFO: running: fulltest
[09:04:25.356] <TB2> INFO: ######################################################################
[09:04:25.356] <TB2> INFO: PixTestFullTest::doTest()
[09:04:25.356] <TB2> INFO: ######################################################################
[09:04:25.358] <TB2> INFO: ######################################################################
[09:04:25.358] <TB2> INFO: PixTestAlive::doTest()
[09:04:25.358] <TB2> INFO: ######################################################################
[09:04:25.359] <TB2> INFO: ----------------------------------------------------------------------
[09:04:25.359] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:04:25.359] <TB2> INFO: ----------------------------------------------------------------------
[09:04:25.671] <TB2> INFO: Expecting 41600 events.
[09:04:30.048] <TB2> INFO: 41600 events read in total (3660ms).
[09:04:30.049] <TB2> INFO: Test took 4688ms.
[09:04:30.055] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:04:30.351] <TB2> INFO: PixTestAlive::aliveTest() done
[09:04:30.351] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0
[09:04:30.353] <TB2> INFO: ----------------------------------------------------------------------
[09:04:30.353] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:04:30.353] <TB2> INFO: ----------------------------------------------------------------------
[09:04:30.669] <TB2> INFO: Expecting 41600 events.
[09:04:33.833] <TB2> INFO: 41600 events read in total (2448ms).
[09:04:33.834] <TB2> INFO: Test took 3479ms.
[09:04:33.834] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:04:33.834] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[09:04:34.150] <TB2> INFO: PixTestAlive::maskTest() done
[09:04:34.150] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:04:34.152] <TB2> INFO: ----------------------------------------------------------------------
[09:04:34.152] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:04:34.152] <TB2> INFO: ----------------------------------------------------------------------
[09:04:34.466] <TB2> INFO: Expecting 41600 events.
[09:04:38.896] <TB2> INFO: 41600 events read in total (3713ms).
[09:04:38.896] <TB2> INFO: Test took 4742ms.
[09:04:38.903] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:04:39.186] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[09:04:39.186] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:04:39.186] <TB2> INFO: PixTestAlive::doTest() done, duration: 13 seconds
[09:04:39.198] <TB2> INFO: ######################################################################
[09:04:39.198] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[09:04:39.198] <TB2> INFO: ######################################################################
[09:04:39.201] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 2 (plus default)
[09:04:39.286] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[09:04:39.287] <TB2> INFO: run 1 of 1
[09:04:39.594] <TB2> INFO: Expecting 3120000 events.
[09:05:14.329] <TB2> INFO: 841845 events read in total (34019ms).
[09:05:47.334] <TB2> INFO: 1673530 events read in total (67024ms).
[09:06:21.514] <TB2> INFO: 2518025 events read in total (101205ms).
[09:06:45.598] <TB2> INFO: 3120000 events read in total (125288ms).
[09:06:45.667] <TB2> INFO: Test took 126380ms.
[09:06:45.800] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:07:09.434] <TB2> INFO: PixTestBBMap::doTest() done, duration: 150 seconds
[09:07:09.434] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 24
[09:07:09.434] <TB2> INFO: separation cut (per ROC): 86 73 79 68 70 84 87 93 86 85 89 70 92 70 66 78
[09:07:09.510] <TB2> INFO: ######################################################################
[09:07:09.510] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[09:07:09.510] <TB2> INFO: ######################################################################
[09:07:09.511] <TB2> INFO: ----------------------------------------------------------------------
[09:07:09.511] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[09:07:09.511] <TB2> INFO: ----------------------------------------------------------------------
[09:07:09.511] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 0 .. 149 (-1/-1) hits flags = 16 (plus default)
[09:07:09.520] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[09:07:09.520] <TB2> INFO: run 1 of 1
[09:07:09.837] <TB2> INFO: Expecting 31200000 events.
[09:07:37.549] <TB2> INFO: 939400 events read in total (26996ms).
[09:08:04.934] <TB2> INFO: 1865000 events read in total (54381ms).
[09:08:32.126] <TB2> INFO: 2785650 events read in total (81573ms).
[09:08:59.158] <TB2> INFO: 3708550 events read in total (108605ms).
[09:09:26.668] <TB2> INFO: 4626750 events read in total (136115ms).
[09:09:53.807] <TB2> INFO: 5547350 events read in total (163254ms).
[09:10:20.868] <TB2> INFO: 6462450 events read in total (190315ms).
[09:10:47.913] <TB2> INFO: 7383700 events read in total (217360ms).
[09:11:14.386] <TB2> INFO: 8299450 events read in total (243833ms).
[09:11:41.420] <TB2> INFO: 9216500 events read in total (270867ms).
[09:12:08.740] <TB2> INFO: 10131650 events read in total (298187ms).
[09:12:36.297] <TB2> INFO: 11050850 events read in total (325744ms).
[09:13:03.435] <TB2> INFO: 11965300 events read in total (352882ms).
[09:13:30.406] <TB2> INFO: 12880350 events read in total (379853ms).
[09:13:57.584] <TB2> INFO: 13794300 events read in total (407031ms).
[09:14:24.210] <TB2> INFO: 14708700 events read in total (433657ms).
[09:14:51.679] <TB2> INFO: 15622200 events read in total (461126ms).
[09:15:18.715] <TB2> INFO: 16527700 events read in total (488162ms).
[09:15:45.649] <TB2> INFO: 17433750 events read in total (515096ms).
[09:16:12.206] <TB2> INFO: 18337050 events read in total (541653ms).
[09:16:39.341] <TB2> INFO: 19242950 events read in total (568788ms).
[09:17:06.528] <TB2> INFO: 20143400 events read in total (595975ms).
[09:17:33.634] <TB2> INFO: 21047700 events read in total (623081ms).
[09:18:00.086] <TB2> INFO: 21949250 events read in total (649533ms).
[09:18:27.389] <TB2> INFO: 22851600 events read in total (676836ms).
[09:18:54.153] <TB2> INFO: 23751700 events read in total (703600ms).
[09:19:21.435] <TB2> INFO: 24654400 events read in total (730882ms).
[09:19:48.518] <TB2> INFO: 25554800 events read in total (757965ms).
[09:20:15.786] <TB2> INFO: 26456150 events read in total (785233ms).
[09:20:42.819] <TB2> INFO: 27357200 events read in total (812266ms).
[09:21:08.327] <TB2> INFO: 28259650 events read in total (837774ms).
[09:21:33.712] <TB2> INFO: 29164650 events read in total (863159ms).
[09:22:00.398] <TB2> INFO: 30071700 events read in total (889845ms).
[09:22:23.000] <TB2> INFO: 30987900 events read in total (912447ms).
[09:22:28.342] <TB2> INFO: 31200000 events read in total (917789ms).
[09:22:28.374] <TB2> INFO: Test took 918854ms.
[09:22:28.456] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:22:28.562] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:29.975] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:31.551] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:33.011] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:34.501] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:35.998] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:37.542] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:38.967] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:40.330] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:41.685] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:43.055] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:44.431] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:45.819] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:47.205] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:48.643] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:50.070] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:22:51.589] <TB2> INFO: PixTestScurves::scurves() done
[09:22:51.589] <TB2> INFO: Vcal mean: 90.28 80.81 83.12 77.47 79.93 82.67 94.91 92.77 89.05 84.74 82.71 81.10 85.09 73.39 76.54 93.46
[09:22:51.589] <TB2> INFO: Vcal RMS: 6.15 4.68 5.03 4.68 4.32 5.04 5.87 6.69 5.83 5.23 5.12 4.71 4.79 4.93 4.25 5.22
[09:22:51.589] <TB2> INFO: PixTestScurves::fullTest() done, duration: 942 seconds
[09:22:51.667] <TB2> INFO: ######################################################################
[09:22:51.667] <TB2> INFO: PixTestTrim::doTest()
[09:22:51.667] <TB2> INFO: ######################################################################
[09:22:51.668] <TB2> INFO: ----------------------------------------------------------------------
[09:22:51.669] <TB2> INFO: PixTestTrim::trimTest() ntrig = 20, vcal = 35
[09:22:51.669] <TB2> INFO: ----------------------------------------------------------------------
[09:22:51.757] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[09:22:51.757] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[09:22:51.767] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[09:22:51.767] <TB2> INFO: run 1 of 1
[09:22:52.084] <TB2> INFO: Expecting 13312000 events.
[09:23:22.201] <TB2> INFO: 1084200 events read in total (29401ms).
[09:23:51.788] <TB2> INFO: 2165900 events read in total (58988ms).
[09:24:21.715] <TB2> INFO: 3243900 events read in total (88915ms).
[09:24:51.617] <TB2> INFO: 4319420 events read in total (118817ms).
[09:25:21.457] <TB2> INFO: 5389440 events read in total (148657ms).
[09:25:50.831] <TB2> INFO: 6456060 events read in total (178031ms).
[09:26:20.226] <TB2> INFO: 7528820 events read in total (207426ms).
[09:26:49.768] <TB2> INFO: 8603720 events read in total (236968ms).
[09:27:17.443] <TB2> INFO: 9681840 events read in total (264643ms).
[09:27:46.877] <TB2> INFO: 10757580 events read in total (294077ms).
[09:28:16.073] <TB2> INFO: 11833760 events read in total (323273ms).
[09:28:44.234] <TB2> INFO: 12913220 events read in total (351434ms).
[09:28:53.847] <TB2> INFO: 13312000 events read in total (361047ms).
[09:28:53.880] <TB2> INFO: Test took 362113ms.
[09:28:53.934] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:29:12.430] <TB2> INFO: ROC 0 VthrComp = 92
[09:29:12.430] <TB2> INFO: ROC 1 VthrComp = 84
[09:29:12.431] <TB2> INFO: ROC 2 VthrComp = 90
[09:29:12.431] <TB2> INFO: ROC 3 VthrComp = 81
[09:29:12.431] <TB2> INFO: ROC 4 VthrComp = 84
[09:29:12.431] <TB2> INFO: ROC 5 VthrComp = 89
[09:29:12.431] <TB2> INFO: ROC 6 VthrComp = 94
[09:29:12.431] <TB2> INFO: ROC 7 VthrComp = 92
[09:29:12.432] <TB2> INFO: ROC 8 VthrComp = 94
[09:29:12.432] <TB2> INFO: ROC 9 VthrComp = 90
[09:29:12.432] <TB2> INFO: ROC 10 VthrComp = 90
[09:29:12.432] <TB2> INFO: ROC 11 VthrComp = 84
[09:29:12.432] <TB2> INFO: ROC 12 VthrComp = 91
[09:29:12.432] <TB2> INFO: ROC 13 VthrComp = 79
[09:29:12.432] <TB2> INFO: ROC 14 VthrComp = 81
[09:29:12.433] <TB2> INFO: ROC 15 VthrComp = 101
[09:29:12.433] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[09:29:12.433] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[09:29:12.445] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[09:29:12.445] <TB2> INFO: run 1 of 1
[09:29:12.779] <TB2> INFO: Expecting 13312000 events.
[09:29:40.782] <TB2> INFO: 780260 events read in total (27287ms).
[09:30:08.736] <TB2> INFO: 1556980 events read in total (55242ms).
[09:30:36.094] <TB2> INFO: 2332780 events read in total (82599ms).
[09:31:03.520] <TB2> INFO: 3108760 events read in total (110025ms).
[09:31:30.208] <TB2> INFO: 3884300 events read in total (136713ms).
[09:31:57.303] <TB2> INFO: 4660660 events read in total (163808ms).
[09:32:24.562] <TB2> INFO: 5436060 events read in total (191067ms).
[09:32:51.503] <TB2> INFO: 6212000 events read in total (218008ms).
[09:33:18.820] <TB2> INFO: 6984880 events read in total (245325ms).
[09:33:45.888] <TB2> INFO: 7755400 events read in total (272393ms).
[09:34:13.546] <TB2> INFO: 8523740 events read in total (300051ms).
[09:34:38.845] <TB2> INFO: 9291300 events read in total (325350ms).
[09:35:04.486] <TB2> INFO: 10057420 events read in total (350991ms).
[09:35:28.944] <TB2> INFO: 10823920 events read in total (375449ms).
[09:35:53.604] <TB2> INFO: 11589200 events read in total (400109ms).
[09:36:17.701] <TB2> INFO: 12355880 events read in total (424206ms).
[09:36:43.013] <TB2> INFO: 13123860 events read in total (449518ms).
[09:36:48.843] <TB2> INFO: 13312000 events read in total (455348ms).
[09:36:48.889] <TB2> INFO: Test took 456444ms.
[09:36:49.030] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:37:12.319] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 62.4273 for pixel 15/0 mean/min/max = 47.1016/31.7476/62.4556
[09:37:12.320] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 59.0981 for pixel 2/3 mean/min/max = 45.6147/32.0904/59.1391
[09:37:12.322] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 58.3778 for pixel 18/3 mean/min/max = 45.2669/32.1316/58.4021
[09:37:12.322] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 57.4641 for pixel 0/47 mean/min/max = 44.8272/32.1474/57.507
[09:37:12.323] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 57.3325 for pixel 26/3 mean/min/max = 44.9518/32.4833/57.4203
[09:37:12.325] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 59.2833 for pixel 20/78 mean/min/max = 45.9649/32.4338/59.4959
[09:37:12.326] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 60.254 for pixel 12/70 mean/min/max = 46.221/32.1719/60.2701
[09:37:12.326] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 63.4992 for pixel 0/14 mean/min/max = 47.81/31.9306/63.6893
[09:37:12.327] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 60.4265 for pixel 5/77 mean/min/max = 45.9037/31.3357/60.4717
[09:37:12.327] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 59.2431 for pixel 0/29 mean/min/max = 45.6056/31.8354/59.3758
[09:37:12.328] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 58.4062 for pixel 8/6 mean/min/max = 45.3551/32.2856/58.4246
[09:37:12.328] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 58.5591 for pixel 11/59 mean/min/max = 45.5044/32.3709/58.638
[09:37:12.329] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 56.9746 for pixel 24/1 mean/min/max = 44.9519/32.7641/57.1396
[09:37:12.329] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 59.1954 for pixel 3/7 mean/min/max = 46.5075/33.6857/59.3293
[09:37:12.330] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 56.8202 for pixel 5/79 mean/min/max = 44.6543/32.4111/56.8975
[09:37:12.330] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 57.2642 for pixel 0/5 mean/min/max = 44.5891/31.5465/57.6317
[09:37:12.331] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:37:12.463] <TB2> INFO: Expecting 1029120 events.
[09:37:38.161] <TB2> INFO: 1029120 events read in total (24982ms).
[09:37:38.166] <TB2> INFO: Expecting 1029120 events.
[09:38:03.795] <TB2> INFO: 1029120 events read in total (25094ms).
[09:38:03.801] <TB2> INFO: Expecting 1029120 events.
[09:38:29.086] <TB2> INFO: 1029120 events read in total (24745ms).
[09:38:29.096] <TB2> INFO: Expecting 1029120 events.
[09:38:53.897] <TB2> INFO: 1029120 events read in total (24273ms).
[09:38:53.908] <TB2> INFO: Expecting 1029120 events.
[09:39:19.372] <TB2> INFO: 1029120 events read in total (24931ms).
[09:39:19.385] <TB2> INFO: Expecting 1029120 events.
[09:39:44.871] <TB2> INFO: 1029120 events read in total (24956ms).
[09:39:44.886] <TB2> INFO: Expecting 1029120 events.
[09:40:10.294] <TB2> INFO: 1029120 events read in total (24881ms).
[09:40:10.311] <TB2> INFO: Expecting 1029120 events.
[09:40:35.389] <TB2> INFO: 1029120 events read in total (24550ms).
[09:40:35.407] <TB2> INFO: Expecting 1029120 events.
[09:41:00.966] <TB2> INFO: 1029120 events read in total (25031ms).
[09:41:00.987] <TB2> INFO: Expecting 1029120 events.
[09:41:26.416] <TB2> INFO: 1029120 events read in total (24902ms).
[09:41:26.440] <TB2> INFO: Expecting 1029120 events.
[09:41:52.370] <TB2> INFO: 1029120 events read in total (25403ms).
[09:41:52.396] <TB2> INFO: Expecting 1029120 events.
[09:42:17.677] <TB2> INFO: 1029120 events read in total (24753ms).
[09:42:17.704] <TB2> INFO: Expecting 1029120 events.
[09:42:42.917] <TB2> INFO: 1029120 events read in total (24686ms).
[09:42:42.947] <TB2> INFO: Expecting 1029120 events.
[09:43:08.206] <TB2> INFO: 1029120 events read in total (24731ms).
[09:43:08.236] <TB2> INFO: Expecting 1029120 events.
[09:43:33.498] <TB2> INFO: 1029120 events read in total (24734ms).
[09:43:33.530] <TB2> INFO: Expecting 1029120 events.
[09:43:58.562] <TB2> INFO: 1029120 events read in total (24505ms).
[09:43:58.596] <TB2> INFO: Test took 406265ms.
[09:43:59.602] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 20 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[09:43:59.611] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[09:43:59.611] <TB2> INFO: run 1 of 1
[09:43:59.918] <TB2> INFO: Expecting 16640000 events.
[09:44:27.852] <TB2> INFO: 725320 events read in total (27217ms).
[09:44:54.781] <TB2> INFO: 1447120 events read in total (54146ms).
[09:45:21.236] <TB2> INFO: 2169040 events read in total (80601ms).
[09:45:48.640] <TB2> INFO: 2890840 events read in total (108005ms).
[09:46:15.757] <TB2> INFO: 3612040 events read in total (135122ms).
[09:46:42.394] <TB2> INFO: 4333540 events read in total (161759ms).
[09:47:09.131] <TB2> INFO: 5054580 events read in total (188496ms).
[09:47:36.390] <TB2> INFO: 5776900 events read in total (215755ms).
[09:48:02.974] <TB2> INFO: 6498540 events read in total (242339ms).
[09:48:29.640] <TB2> INFO: 7219440 events read in total (269005ms).
[09:48:56.518] <TB2> INFO: 7941360 events read in total (295883ms).
[09:49:23.214] <TB2> INFO: 8660140 events read in total (322579ms).
[09:49:50.065] <TB2> INFO: 9377420 events read in total (349430ms).
[09:50:16.480] <TB2> INFO: 10093360 events read in total (375845ms).
[09:50:42.612] <TB2> INFO: 10807860 events read in total (401977ms).
[09:51:07.969] <TB2> INFO: 11522560 events read in total (427334ms).
[09:51:35.069] <TB2> INFO: 12236860 events read in total (454434ms).
[09:52:02.200] <TB2> INFO: 12950420 events read in total (481565ms).
[09:52:29.244] <TB2> INFO: 13662680 events read in total (508609ms).
[09:52:55.892] <TB2> INFO: 14374700 events read in total (535257ms).
[09:53:22.588] <TB2> INFO: 15088680 events read in total (561953ms).
[09:53:48.921] <TB2> INFO: 15801280 events read in total (588286ms).
[09:54:13.105] <TB2> INFO: 16515680 events read in total (612470ms).
[09:54:17.380] <TB2> INFO: 16640000 events read in total (616745ms).
[09:54:17.444] <TB2> INFO: Test took 617833ms.
[09:54:17.652] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:54:44.020] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 0.009523 .. 53.783439
[09:54:44.097] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 20 dacrange: 0 .. 63 (-1/-1) hits flags = 16 (plus default)
[09:54:44.105] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[09:54:44.106] <TB2> INFO: run 1 of 1
[09:54:44.412] <TB2> INFO: Expecting 5324800 events.
[09:55:13.863] <TB2> INFO: 910640 events read in total (28735ms).
[09:55:42.198] <TB2> INFO: 1823220 events read in total (57070ms).
[09:56:10.420] <TB2> INFO: 2734880 events read in total (85292ms).
[09:56:39.425] <TB2> INFO: 3643560 events read in total (114297ms).
[09:57:08.316] <TB2> INFO: 4546940 events read in total (143188ms).
[09:57:29.250] <TB2> INFO: 5324800 events read in total (164122ms).
[09:57:29.268] <TB2> INFO: Test took 165162ms.
[09:57:29.311] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:57:43.703] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 17.890631 .. 45.985618
[09:57:43.784] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 20 dacrange: 7 .. 55 (-1/-1) hits flags = 16 (plus default)
[09:57:43.795] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[09:57:43.795] <TB2> INFO: run 1 of 1
[09:57:44.113] <TB2> INFO: Expecting 4076800 events.
[09:58:15.431] <TB2> INFO: 925900 events read in total (30602ms).
[09:58:45.519] <TB2> INFO: 1852380 events read in total (60690ms).
[09:59:15.752] <TB2> INFO: 2778060 events read in total (90923ms).
[09:59:41.333] <TB2> INFO: 3701300 events read in total (116504ms).
[09:59:52.370] <TB2> INFO: 4076800 events read in total (127541ms).
[09:59:52.381] <TB2> INFO: Test took 128586ms.
[09:59:52.412] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:00:06.129] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 22.720522 .. 42.595465
[10:00:06.205] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 20 dacrange: 12 .. 52 (-1/-1) hits flags = 16 (plus default)
[10:00:06.213] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[10:00:06.213] <TB2> INFO: run 1 of 1
[10:00:06.518] <TB2> INFO: Expecting 3411200 events.
[10:00:37.271] <TB2> INFO: 922800 events read in total (30037ms).
[10:01:07.854] <TB2> INFO: 1845740 events read in total (60620ms).
[10:01:37.779] <TB2> INFO: 2767580 events read in total (90546ms).
[10:01:55.217] <TB2> INFO: 3411200 events read in total (107983ms).
[10:01:55.236] <TB2> INFO: Test took 109023ms.
[10:01:55.265] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:02:08.152] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 25.443155 .. 42.492411
[10:02:08.228] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 20 dacrange: 15 .. 52 (-1/-1) hits flags = 16 (plus default)
[10:02:08.237] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[10:02:08.237] <TB2> INFO: run 1 of 1
[10:02:08.541] <TB2> INFO: Expecting 3161600 events.
[10:02:38.740] <TB2> INFO: 900760 events read in total (29482ms).
[10:03:05.962] <TB2> INFO: 1801880 events read in total (56704ms).
[10:03:33.929] <TB2> INFO: 2702900 events read in total (84671ms).
[10:03:46.639] <TB2> INFO: 3161600 events read in total (97381ms).
[10:03:46.658] <TB2> INFO: Test took 98422ms.
[10:03:46.691] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:03:59.383] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[10:03:59.383] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 20 dacrange: 15 .. 55 (-1/-1) hits flags = 16 (plus default)
[10:03:59.391] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[10:03:59.391] <TB2> INFO: run 1 of 1
[10:03:59.694] <TB2> INFO: Expecting 3411200 events.
[10:04:28.516] <TB2> INFO: 878980 events read in total (28103ms).
[10:04:57.033] <TB2> INFO: 1758340 events read in total (56620ms).
[10:05:22.600] <TB2> INFO: 2636960 events read in total (82187ms).
[10:05:44.004] <TB2> INFO: 3411200 events read in total (103591ms).
[10:05:44.020] <TB2> INFO: Test took 104629ms.
[10:05:44.055] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:05:57.522] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C0.dat
[10:05:57.522] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C1.dat
[10:05:57.522] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C2.dat
[10:05:57.522] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C3.dat
[10:05:57.522] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C4.dat
[10:05:57.523] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C5.dat
[10:05:57.523] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C6.dat
[10:05:57.523] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C7.dat
[10:05:57.523] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C8.dat
[10:05:57.523] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C9.dat
[10:05:57.523] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C10.dat
[10:05:57.523] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C11.dat
[10:05:57.523] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C12.dat
[10:05:57.523] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C13.dat
[10:05:57.524] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C14.dat
[10:05:57.524] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C15.dat
[10:05:57.524] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C0.dat
[10:05:57.530] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C1.dat
[10:05:57.537] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C2.dat
[10:05:57.544] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C3.dat
[10:05:57.550] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C4.dat
[10:05:57.557] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C5.dat
[10:05:57.564] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C6.dat
[10:05:57.570] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C7.dat
[10:05:57.577] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C8.dat
[10:05:57.583] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C9.dat
[10:05:57.590] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C10.dat
[10:05:57.597] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C11.dat
[10:05:57.603] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C12.dat
[10:05:57.610] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C13.dat
[10:05:57.616] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C14.dat
[10:05:57.623] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//trimParameters35_C15.dat
[10:05:57.629] <TB2> INFO: PixTestTrim::trimTest() done
[10:05:57.629] <TB2> INFO: vtrim: 114 97 102 82 94 91 103 106 109 106 109 90 88 99 79 95
[10:05:57.629] <TB2> INFO: vthrcomp: 92 84 90 81 84 89 94 92 94 90 90 84 91 79 81 101
[10:05:57.629] <TB2> INFO: vcal mean: 35.02 34.99 34.94 34.93 34.98 34.99 34.97 34.95 35.00 35.00 34.96 34.96 34.98 34.98 34.98 34.96
[10:05:57.629] <TB2> INFO: vcal RMS: 0.79 0.68 0.75 1.01 0.66 0.66 0.73 0.82 0.72 0.72 0.70 0.70 0.66 0.64 0.65 0.70
[10:05:57.629] <TB2> INFO: bits mean: 9.25 9.23 9.59 9.11 9.40 9.01 9.24 8.62 9.24 9.17 9.48 9.15 9.26 8.59 9.28 9.31
[10:05:57.629] <TB2> INFO: bits RMS: 2.73 2.77 2.70 2.89 2.70 2.77 2.73 2.93 2.88 2.83 2.69 2.76 2.68 2.75 2.79 2.90
[10:05:57.636] <TB2> INFO: ----------------------------------------------------------------------
[10:05:57.636] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 10, vtrims = 254 126 63 32
[10:05:57.636] <TB2> INFO: ----------------------------------------------------------------------
[10:05:57.638] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 10 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[10:05:57.647] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:05:57.647] <TB2> INFO: run 1 of 1
[10:05:57.956] <TB2> INFO: Expecting 8320000 events.
[10:06:27.011] <TB2> INFO: 915480 events read in total (28339ms).
[10:06:57.840] <TB2> INFO: 1822950 events read in total (59168ms).
[10:07:28.266] <TB2> INFO: 2728280 events read in total (89594ms).
[10:07:58.909] <TB2> INFO: 3631570 events read in total (120237ms).
[10:08:26.860] <TB2> INFO: 4531110 events read in total (148188ms).
[10:08:57.273] <TB2> INFO: 5425480 events read in total (178601ms).
[10:09:27.624] <TB2> INFO: 6319400 events read in total (208952ms).
[10:09:57.986] <TB2> INFO: 7212940 events read in total (239314ms).
[10:10:27.242] <TB2> INFO: 8109400 events read in total (268570ms).
[10:10:33.901] <TB2> INFO: 8320000 events read in total (275229ms).
[10:10:33.953] <TB2> INFO: Test took 276306ms.
[10:10:34.089] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:11:02.495] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 10 dacrange: 0 .. 168 (-1/-1) hits flags = 16 (plus default)
[10:11:02.505] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:11:02.505] <TB2> INFO: run 1 of 1
[10:11:02.823] <TB2> INFO: Expecting 7030400 events.
[10:11:33.160] <TB2> INFO: 943930 events read in total (29616ms).
[10:12:04.784] <TB2> INFO: 1878710 events read in total (61240ms).
[10:12:34.166] <TB2> INFO: 2810450 events read in total (90622ms).
[10:13:05.309] <TB2> INFO: 3737960 events read in total (121765ms).
[10:13:36.927] <TB2> INFO: 4657640 events read in total (153383ms).
[10:14:08.582] <TB2> INFO: 5576630 events read in total (185038ms).
[10:14:40.265] <TB2> INFO: 6496160 events read in total (216721ms).
[10:14:58.016] <TB2> INFO: 7030400 events read in total (234472ms).
[10:14:58.051] <TB2> INFO: Test took 235546ms.
[10:14:58.142] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:15:22.813] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 10 dacrange: 0 .. 154 (-1/-1) hits flags = 16 (plus default)
[10:15:22.822] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:15:22.822] <TB2> INFO: run 1 of 1
[10:15:23.130] <TB2> INFO: Expecting 6448000 events.
[10:15:54.852] <TB2> INFO: 979670 events read in total (31006ms).
[10:16:27.299] <TB2> INFO: 1949130 events read in total (63454ms).
[10:17:00.078] <TB2> INFO: 2915040 events read in total (96233ms).
[10:17:33.189] <TB2> INFO: 3871820 events read in total (129343ms).
[10:18:05.732] <TB2> INFO: 4822610 events read in total (161886ms).
[10:18:38.583] <TB2> INFO: 5774350 events read in total (194737ms).
[10:19:01.190] <TB2> INFO: 6448000 events read in total (217344ms).
[10:19:01.217] <TB2> INFO: Test took 218395ms.
[10:19:01.289] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:19:24.087] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 10 dacrange: 0 .. 155 (-1/-1) hits flags = 16 (plus default)
[10:19:24.096] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:19:24.096] <TB2> INFO: run 1 of 1
[10:19:24.408] <TB2> INFO: Expecting 6489600 events.
[10:19:53.051] <TB2> INFO: 976100 events read in total (27927ms).
[10:20:25.128] <TB2> INFO: 1941820 events read in total (60004ms).
[10:20:57.111] <TB2> INFO: 2904310 events read in total (91988ms).
[10:21:29.829] <TB2> INFO: 3857560 events read in total (124705ms).
[10:22:02.532] <TB2> INFO: 4805720 events read in total (157408ms).
[10:22:34.871] <TB2> INFO: 5754240 events read in total (189747ms).
[10:22:59.246] <TB2> INFO: 6489600 events read in total (214122ms).
[10:22:59.282] <TB2> INFO: Test took 215185ms.
[10:22:59.358] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:23:22.283] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 10 dacrange: 0 .. 155 (-1/-1) hits flags = 16 (plus default)
[10:23:22.292] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:23:22.292] <TB2> INFO: run 1 of 1
[10:23:22.597] <TB2> INFO: Expecting 6489600 events.
[10:23:52.731] <TB2> INFO: 975100 events read in total (29418ms).
[10:24:23.618] <TB2> INFO: 1940180 events read in total (60305ms).
[10:24:54.840] <TB2> INFO: 2901580 events read in total (91528ms).
[10:25:23.865] <TB2> INFO: 3854340 events read in total (120552ms).
[10:25:54.958] <TB2> INFO: 4801660 events read in total (151645ms).
[10:26:26.308] <TB2> INFO: 5749680 events read in total (182995ms).
[10:26:51.127] <TB2> INFO: 6489600 events read in total (207814ms).
[10:26:51.158] <TB2> INFO: Test took 208866ms.
[10:26:51.232] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:27:14.021] <TB2> INFO: PixTestTrim::trimBitTest() done
[10:27:14.023] <TB2> INFO: PixTestTrim::doTest() done, duration: 3862 seconds
[10:27:14.717] <TB2> INFO: ######################################################################
[10:27:14.717] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[10:27:14.717] <TB2> INFO: ######################################################################
[10:27:15.023] <TB2> INFO: Expecting 41600 events.
[10:27:19.569] <TB2> INFO: 41600 events read in total (3830ms).
[10:27:19.569] <TB2> INFO: Test took 4851ms.
[10:27:19.575] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:27:20.153] <TB2> INFO: Expecting 41600 events.
[10:27:24.793] <TB2> INFO: 41600 events read in total (3923ms).
[10:27:24.793] <TB2> INFO: Test took 4954ms.
[10:27:24.799] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:27:25.146] <TB2> INFO: Expecting 41600 events.
[10:27:29.917] <TB2> INFO: 41600 events read in total (4055ms).
[10:27:29.918] <TB2> INFO: Test took 5096ms.
[10:27:29.924] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:27:29.931] <TB2> INFO: The DUT currently contains the following objects:
[10:27:29.931] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:29.931] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:29.931] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:29.931] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:29.931] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:29.931] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:30.270] <TB2> INFO: Expecting 2560 events.
[10:27:31.340] <TB2> INFO: 2560 events read in total (354ms).
[10:27:31.341] <TB2> INFO: Test took 1410ms.
[10:27:31.341] <TB2> INFO: The DUT currently contains the following objects:
[10:27:31.341] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:31.341] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:31.341] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:31.341] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:31.341] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.341] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.341] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.341] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.341] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.341] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.341] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.341] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.342] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.342] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.342] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.342] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.342] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.342] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.342] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.342] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:31.755] <TB2> INFO: Expecting 2560 events.
[10:27:32.855] <TB2> INFO: 2560 events read in total (383ms).
[10:27:32.856] <TB2> INFO: Test took 1514ms.
[10:27:32.856] <TB2> INFO: The DUT currently contains the following objects:
[10:27:32.856] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:32.856] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:32.856] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:32.857] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:32.857] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:32.857] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:33.270] <TB2> INFO: Expecting 2560 events.
[10:27:34.354] <TB2> INFO: 2560 events read in total (368ms).
[10:27:34.354] <TB2> INFO: Test took 1497ms.
[10:27:34.355] <TB2> INFO: The DUT currently contains the following objects:
[10:27:34.355] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:34.355] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:34.355] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:34.355] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:34.355] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.355] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:34.768] <TB2> INFO: Expecting 2560 events.
[10:27:35.837] <TB2> INFO: 2560 events read in total (353ms).
[10:27:35.837] <TB2> INFO: Test took 1482ms.
[10:27:35.838] <TB2> INFO: The DUT currently contains the following objects:
[10:27:35.838] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:35.838] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:35.838] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:35.838] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:35.838] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:35.838] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:36.252] <TB2> INFO: Expecting 2560 events.
[10:27:37.348] <TB2> INFO: 2560 events read in total (380ms).
[10:27:37.349] <TB2> INFO: Test took 1510ms.
[10:27:37.349] <TB2> INFO: The DUT currently contains the following objects:
[10:27:37.349] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:37.349] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:37.349] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:37.349] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:37.350] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.350] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:37.763] <TB2> INFO: Expecting 2560 events.
[10:27:38.831] <TB2> INFO: 2560 events read in total (352ms).
[10:27:38.831] <TB2> INFO: Test took 1481ms.
[10:27:38.831] <TB2> INFO: The DUT currently contains the following objects:
[10:27:38.832] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:38.832] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:38.832] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:38.832] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:38.832] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:38.832] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:39.245] <TB2> INFO: Expecting 2560 events.
[10:27:40.306] <TB2> INFO: 2560 events read in total (345ms).
[10:27:40.307] <TB2> INFO: Test took 1475ms.
[10:27:40.308] <TB2> INFO: The DUT currently contains the following objects:
[10:27:40.308] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:40.308] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:40.308] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:40.308] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:40.308] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.308] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:40.721] <TB2> INFO: Expecting 2560 events.
[10:27:41.781] <TB2> INFO: 2560 events read in total (344ms).
[10:27:41.781] <TB2> INFO: Test took 1472ms.
[10:27:41.782] <TB2> INFO: The DUT currently contains the following objects:
[10:27:41.782] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:41.782] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:41.782] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:41.782] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:41.782] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:41.782] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:42.196] <TB2> INFO: Expecting 2560 events.
[10:27:43.257] <TB2> INFO: 2560 events read in total (345ms).
[10:27:43.257] <TB2> INFO: Test took 1475ms.
[10:27:43.258] <TB2> INFO: The DUT currently contains the following objects:
[10:27:43.258] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:43.258] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:43.258] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:43.258] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:43.258] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.258] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:43.672] <TB2> INFO: Expecting 2560 events.
[10:27:44.749] <TB2> INFO: 2560 events read in total (361ms).
[10:27:44.749] <TB2> INFO: Test took 1491ms.
[10:27:44.749] <TB2> INFO: The DUT currently contains the following objects:
[10:27:44.749] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:44.749] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:44.749] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:44.749] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:44.749] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:44.749] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:45.163] <TB2> INFO: Expecting 2560 events.
[10:27:46.224] <TB2> INFO: 2560 events read in total (345ms).
[10:27:46.224] <TB2> INFO: Test took 1475ms.
[10:27:46.224] <TB2> INFO: The DUT currently contains the following objects:
[10:27:46.224] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:46.224] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:46.224] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:46.224] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:46.224] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.224] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:46.638] <TB2> INFO: Expecting 2560 events.
[10:27:47.699] <TB2> INFO: 2560 events read in total (345ms).
[10:27:47.699] <TB2> INFO: Test took 1475ms.
[10:27:47.699] <TB2> INFO: The DUT currently contains the following objects:
[10:27:47.699] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:47.699] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:47.699] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:47.699] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:47.699] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:47.699] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:48.113] <TB2> INFO: Expecting 2560 events.
[10:27:49.173] <TB2> INFO: 2560 events read in total (344ms).
[10:27:49.173] <TB2> INFO: Test took 1474ms.
[10:27:49.173] <TB2> INFO: The DUT currently contains the following objects:
[10:27:49.173] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:49.173] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:49.173] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:49.173] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:49.173] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.173] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.173] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.173] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.173] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.173] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.173] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.173] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.173] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.173] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.173] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.173] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.174] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.174] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.174] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.174] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:49.587] <TB2> INFO: Expecting 2560 events.
[10:27:50.648] <TB2> INFO: 2560 events read in total (345ms).
[10:27:50.648] <TB2> INFO: Test took 1474ms.
[10:27:50.648] <TB2> INFO: The DUT currently contains the following objects:
[10:27:50.648] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:50.648] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:50.648] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:50.648] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:50.648] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:50.648] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:51.062] <TB2> INFO: Expecting 2560 events.
[10:27:52.122] <TB2> INFO: 2560 events read in total (344ms).
[10:27:52.122] <TB2> INFO: Test took 1474ms.
[10:27:52.123] <TB2> INFO: The DUT currently contains the following objects:
[10:27:52.123] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:27:52.123] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:27:52.123] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:27:52.123] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:27:52.123] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.123] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:27:52.537] <TB2> INFO: Expecting 2560 events.
[10:27:53.597] <TB2> INFO: 2560 events read in total (344ms).
[10:27:53.597] <TB2> INFO: Test took 1474ms.
[10:27:53.600] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:27:54.013] <TB2> INFO: Expecting 655360 events.
[10:28:10.484] <TB2> INFO: 655360 events read in total (15755ms).
[10:28:10.493] <TB2> INFO: Expecting 655360 events.
[10:28:27.446] <TB2> INFO: 655360 events read in total (16423ms).
[10:28:27.458] <TB2> INFO: Expecting 655360 events.
[10:28:44.159] <TB2> INFO: 655360 events read in total (16174ms).
[10:28:44.174] <TB2> INFO: Expecting 655360 events.
[10:29:03.138] <TB2> INFO: 655360 events read in total (18436ms).
[10:29:03.159] <TB2> INFO: Expecting 655360 events.
[10:29:22.137] <TB2> INFO: 655360 events read in total (18451ms).
[10:29:22.162] <TB2> INFO: Expecting 655360 events.
[10:29:41.171] <TB2> INFO: 655360 events read in total (18482ms).
[10:29:41.196] <TB2> INFO: Expecting 655360 events.
[10:29:58.067] <TB2> INFO: 655360 events read in total (16343ms).
[10:29:58.099] <TB2> INFO: Expecting 655360 events.
[10:30:16.076] <TB2> INFO: 655360 events read in total (17449ms).
[10:30:16.112] <TB2> INFO: Expecting 655360 events.
[10:30:35.139] <TB2> INFO: 655360 events read in total (18500ms).
[10:30:35.175] <TB2> INFO: Expecting 655360 events.
[10:30:54.021] <TB2> INFO: 655360 events read in total (18319ms).
[10:30:54.060] <TB2> INFO: Expecting 655360 events.
[10:31:12.556] <TB2> INFO: 655360 events read in total (17969ms).
[10:31:12.604] <TB2> INFO: Expecting 655360 events.
[10:31:31.802] <TB2> INFO: 655360 events read in total (18671ms).
[10:31:31.852] <TB2> INFO: Expecting 655360 events.
[10:31:50.574] <TB2> INFO: 655360 events read in total (18195ms).
[10:31:50.623] <TB2> INFO: Expecting 655360 events.
[10:32:09.666] <TB2> INFO: 655360 events read in total (18515ms).
[10:32:09.725] <TB2> INFO: Expecting 655360 events.
[10:32:28.974] <TB2> INFO: 655360 events read in total (18721ms).
[10:32:29.042] <TB2> INFO: Expecting 655360 events.
[10:32:47.709] <TB2> INFO: 655360 events read in total (18139ms).
[10:32:47.774] <TB2> INFO: Test took 294174ms.
[10:32:47.851] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:32:48.162] <TB2> INFO: Expecting 655360 events.
[10:33:06.873] <TB2> INFO: 655360 events read in total (17995ms).
[10:33:06.881] <TB2> INFO: Expecting 655360 events.
[10:33:25.879] <TB2> INFO: 655360 events read in total (18470ms).
[10:33:25.892] <TB2> INFO: Expecting 655360 events.
[10:33:44.686] <TB2> INFO: 655360 events read in total (18266ms).
[10:33:44.703] <TB2> INFO: Expecting 655360 events.
[10:34:02.113] <TB2> INFO: 655360 events read in total (16883ms).
[10:34:02.132] <TB2> INFO: Expecting 655360 events.
[10:34:20.616] <TB2> INFO: 655360 events read in total (17956ms).
[10:34:20.641] <TB2> INFO: Expecting 655360 events.
[10:34:39.454] <TB2> INFO: 655360 events read in total (18286ms).
[10:34:39.480] <TB2> INFO: Expecting 655360 events.
[10:34:57.893] <TB2> INFO: 655360 events read in total (17886ms).
[10:34:57.926] <TB2> INFO: Expecting 655360 events.
[10:35:15.966] <TB2> INFO: 655360 events read in total (17512ms).
[10:35:16.000] <TB2> INFO: Expecting 655360 events.
[10:35:33.261] <TB2> INFO: 655360 events read in total (16733ms).
[10:35:33.298] <TB2> INFO: Expecting 655360 events.
[10:35:50.739] <TB2> INFO: 655360 events read in total (16913ms).
[10:35:50.782] <TB2> INFO: Expecting 655360 events.
[10:36:08.692] <TB2> INFO: 655360 events read in total (17382ms).
[10:36:08.736] <TB2> INFO: Expecting 655360 events.
[10:36:26.055] <TB2> INFO: 655360 events read in total (16792ms).
[10:36:26.104] <TB2> INFO: Expecting 655360 events.
[10:36:43.089] <TB2> INFO: 655360 events read in total (16458ms).
[10:36:43.139] <TB2> INFO: Expecting 655360 events.
[10:37:01.476] <TB2> INFO: 655360 events read in total (17809ms).
[10:37:01.530] <TB2> INFO: Expecting 655360 events.
[10:37:20.260] <TB2> INFO: 655360 events read in total (18203ms).
[10:37:20.323] <TB2> INFO: Expecting 655360 events.
[10:37:37.657] <TB2> INFO: 655360 events read in total (16806ms).
[10:37:37.728] <TB2> INFO: Test took 289878ms.
[10:37:37.923] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:37.930] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:37.936] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:37.943] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:37.950] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[10:37:37.957] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:37.964] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:37.971] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:37.978] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:37.985] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:37.992] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:37.999] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:38.006] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:38.013] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:38.020] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:38.027] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:38.034] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:37:38.071] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C0.dat
[10:37:38.072] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C1.dat
[10:37:38.072] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C2.dat
[10:37:38.072] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C3.dat
[10:37:38.072] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C4.dat
[10:37:38.072] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C5.dat
[10:37:38.072] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C6.dat
[10:37:38.072] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C7.dat
[10:37:38.072] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C8.dat
[10:37:38.072] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C9.dat
[10:37:38.072] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C10.dat
[10:37:38.073] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C11.dat
[10:37:38.073] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C12.dat
[10:37:38.073] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C13.dat
[10:37:38.073] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C14.dat
[10:37:38.073] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//dacParameters35_C15.dat
[10:37:38.382] <TB2> INFO: Expecting 41600 events.
[10:37:42.853] <TB2> INFO: 41600 events read in total (3755ms).
[10:37:42.854] <TB2> INFO: Test took 4778ms.
[10:37:43.388] <TB2> INFO: Expecting 41600 events.
[10:37:48.049] <TB2> INFO: 41600 events read in total (3945ms).
[10:37:48.049] <TB2> INFO: Test took 4965ms.
[10:37:48.593] <TB2> INFO: Expecting 41600 events.
[10:37:53.290] <TB2> INFO: 41600 events read in total (3981ms).
[10:37:53.290] <TB2> INFO: Test took 5008ms.
[10:37:53.527] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:37:53.660] <TB2> INFO: Expecting 2560 events.
[10:37:54.742] <TB2> INFO: 2560 events read in total (366ms).
[10:37:54.743] <TB2> INFO: Test took 1216ms.
[10:37:54.745] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:37:55.158] <TB2> INFO: Expecting 2560 events.
[10:37:56.221] <TB2> INFO: 2560 events read in total (347ms).
[10:37:56.221] <TB2> INFO: Test took 1476ms.
[10:37:56.223] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:37:56.636] <TB2> INFO: Expecting 2560 events.
[10:37:57.705] <TB2> INFO: 2560 events read in total (353ms).
[10:37:57.705] <TB2> INFO: Test took 1483ms.
[10:37:57.707] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:37:58.121] <TB2> INFO: Expecting 2560 events.
[10:37:59.192] <TB2> INFO: 2560 events read in total (354ms).
[10:37:59.192] <TB2> INFO: Test took 1485ms.
[10:37:59.195] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:37:59.608] <TB2> INFO: Expecting 2560 events.
[10:38:00.678] <TB2> INFO: 2560 events read in total (354ms).
[10:38:00.678] <TB2> INFO: Test took 1483ms.
[10:38:00.680] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:01.094] <TB2> INFO: Expecting 2560 events.
[10:38:02.162] <TB2> INFO: 2560 events read in total (352ms).
[10:38:02.162] <TB2> INFO: Test took 1482ms.
[10:38:02.165] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:02.578] <TB2> INFO: Expecting 2560 events.
[10:38:03.647] <TB2> INFO: 2560 events read in total (353ms).
[10:38:03.647] <TB2> INFO: Test took 1482ms.
[10:38:03.649] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:04.063] <TB2> INFO: Expecting 2560 events.
[10:38:05.131] <TB2> INFO: 2560 events read in total (352ms).
[10:38:05.132] <TB2> INFO: Test took 1483ms.
[10:38:05.134] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:05.547] <TB2> INFO: Expecting 2560 events.
[10:38:06.632] <TB2> INFO: 2560 events read in total (368ms).
[10:38:06.633] <TB2> INFO: Test took 1499ms.
[10:38:06.635] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:07.049] <TB2> INFO: Expecting 2560 events.
[10:38:08.119] <TB2> INFO: 2560 events read in total (354ms).
[10:38:08.119] <TB2> INFO: Test took 1484ms.
[10:38:08.122] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:08.534] <TB2> INFO: Expecting 2560 events.
[10:38:09.604] <TB2> INFO: 2560 events read in total (354ms).
[10:38:09.604] <TB2> INFO: Test took 1482ms.
[10:38:09.606] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:10.020] <TB2> INFO: Expecting 2560 events.
[10:38:11.119] <TB2> INFO: 2560 events read in total (383ms).
[10:38:11.119] <TB2> INFO: Test took 1513ms.
[10:38:11.122] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:11.535] <TB2> INFO: Expecting 2560 events.
[10:38:12.617] <TB2> INFO: 2560 events read in total (366ms).
[10:38:12.618] <TB2> INFO: Test took 1496ms.
[10:38:12.620] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:13.033] <TB2> INFO: Expecting 2560 events.
[10:38:14.100] <TB2> INFO: 2560 events read in total (351ms).
[10:38:14.101] <TB2> INFO: Test took 1481ms.
[10:38:14.103] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:14.516] <TB2> INFO: Expecting 2560 events.
[10:38:15.581] <TB2> INFO: 2560 events read in total (348ms).
[10:38:15.581] <TB2> INFO: Test took 1478ms.
[10:38:15.585] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:15.997] <TB2> INFO: Expecting 2560 events.
[10:38:17.067] <TB2> INFO: 2560 events read in total (354ms).
[10:38:17.067] <TB2> INFO: Test took 1482ms.
[10:38:17.070] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:17.482] <TB2> INFO: Expecting 2560 events.
[10:38:18.566] <TB2> INFO: 2560 events read in total (367ms).
[10:38:18.566] <TB2> INFO: Test took 1496ms.
[10:38:18.569] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:18.982] <TB2> INFO: Expecting 2560 events.
[10:38:20.053] <TB2> INFO: 2560 events read in total (355ms).
[10:38:20.053] <TB2> INFO: Test took 1484ms.
[10:38:20.056] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:20.469] <TB2> INFO: Expecting 2560 events.
[10:38:21.537] <TB2> INFO: 2560 events read in total (352ms).
[10:38:21.538] <TB2> INFO: Test took 1482ms.
[10:38:21.539] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:21.954] <TB2> INFO: Expecting 2560 events.
[10:38:23.024] <TB2> INFO: 2560 events read in total (353ms).
[10:38:23.024] <TB2> INFO: Test took 1485ms.
[10:38:23.027] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:23.440] <TB2> INFO: Expecting 2560 events.
[10:38:24.522] <TB2> INFO: 2560 events read in total (366ms).
[10:38:24.522] <TB2> INFO: Test took 1495ms.
[10:38:24.525] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:24.938] <TB2> INFO: Expecting 2560 events.
[10:38:26.022] <TB2> INFO: 2560 events read in total (368ms).
[10:38:26.022] <TB2> INFO: Test took 1497ms.
[10:38:26.025] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:26.438] <TB2> INFO: Expecting 2560 events.
[10:38:27.535] <TB2> INFO: 2560 events read in total (381ms).
[10:38:27.536] <TB2> INFO: Test took 1512ms.
[10:38:27.538] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:27.952] <TB2> INFO: Expecting 2560 events.
[10:38:29.018] <TB2> INFO: 2560 events read in total (350ms).
[10:38:29.019] <TB2> INFO: Test took 1481ms.
[10:38:29.022] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:29.435] <TB2> INFO: Expecting 2560 events.
[10:38:30.496] <TB2> INFO: 2560 events read in total (345ms).
[10:38:30.497] <TB2> INFO: Test took 1475ms.
[10:38:30.499] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:30.913] <TB2> INFO: Expecting 2560 events.
[10:38:31.983] <TB2> INFO: 2560 events read in total (354ms).
[10:38:31.983] <TB2> INFO: Test took 1484ms.
[10:38:31.986] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:32.399] <TB2> INFO: Expecting 2560 events.
[10:38:33.467] <TB2> INFO: 2560 events read in total (352ms).
[10:38:33.468] <TB2> INFO: Test took 1483ms.
[10:38:33.470] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:33.883] <TB2> INFO: Expecting 2560 events.
[10:38:34.980] <TB2> INFO: 2560 events read in total (381ms).
[10:38:34.980] <TB2> INFO: Test took 1510ms.
[10:38:34.983] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:35.396] <TB2> INFO: Expecting 2560 events.
[10:38:36.464] <TB2> INFO: 2560 events read in total (352ms).
[10:38:36.464] <TB2> INFO: Test took 1481ms.
[10:38:36.467] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:36.880] <TB2> INFO: Expecting 2560 events.
[10:38:37.950] <TB2> INFO: 2560 events read in total (353ms).
[10:38:37.950] <TB2> INFO: Test took 1483ms.
[10:38:37.953] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:38.366] <TB2> INFO: Expecting 2560 events.
[10:38:39.448] <TB2> INFO: 2560 events read in total (366ms).
[10:38:39.448] <TB2> INFO: Test took 1495ms.
[10:38:39.451] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:38:39.864] <TB2> INFO: Expecting 2560 events.
[10:38:40.933] <TB2> INFO: 2560 events read in total (353ms).
[10:38:40.933] <TB2> INFO: Test took 1482ms.
[10:38:41.550] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 686 seconds
[10:38:41.550] <TB2> INFO: PH scale (per ROC): 80 80 79 80 85 86 75 79 88 83 85 80 80 83 80 84
[10:38:41.550] <TB2> INFO: PH offset (per ROC): 159 159 164 165 167 150 171 159 160 167 158 165 163 144 150 147
[10:38:41.745] <TB2> INFO: ######################################################################
[10:38:41.745] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[10:38:41.745] <TB2> INFO: ######################################################################
[10:38:41.755] <TB2> INFO: scanning low vcal = 10
[10:38:42.061] <TB2> INFO: Expecting 41600 events.
[10:38:45.693] <TB2> INFO: 41600 events read in total (2916ms).
[10:38:45.693] <TB2> INFO: Test took 3938ms.
[10:38:45.695] <TB2> INFO: scanning low vcal = 20
[10:38:46.108] <TB2> INFO: Expecting 41600 events.
[10:38:49.741] <TB2> INFO: 41600 events read in total (2917ms).
[10:38:49.741] <TB2> INFO: Test took 4046ms.
[10:38:49.743] <TB2> INFO: scanning low vcal = 30
[10:38:50.156] <TB2> INFO: Expecting 41600 events.
[10:38:53.806] <TB2> INFO: 41600 events read in total (2934ms).
[10:38:53.807] <TB2> INFO: Test took 4064ms.
[10:38:53.809] <TB2> INFO: scanning low vcal = 40
[10:38:54.215] <TB2> INFO: Expecting 41600 events.
[10:38:58.408] <TB2> INFO: 41600 events read in total (3477ms).
[10:38:58.408] <TB2> INFO: Test took 4599ms.
[10:38:58.411] <TB2> INFO: scanning low vcal = 50
[10:38:58.760] <TB2> INFO: Expecting 41600 events.
[10:39:02.999] <TB2> INFO: 41600 events read in total (3522ms).
[10:39:03.000] <TB2> INFO: Test took 4589ms.
[10:39:03.002] <TB2> INFO: scanning low vcal = 60
[10:39:03.358] <TB2> INFO: Expecting 41600 events.
[10:39:07.594] <TB2> INFO: 41600 events read in total (3520ms).
[10:39:07.595] <TB2> INFO: Test took 4593ms.
[10:39:07.597] <TB2> INFO: scanning low vcal = 70
[10:39:07.944] <TB2> INFO: Expecting 41600 events.
[10:39:12.186] <TB2> INFO: 41600 events read in total (3526ms).
[10:39:12.187] <TB2> INFO: Test took 4590ms.
[10:39:12.189] <TB2> INFO: scanning low vcal = 80
[10:39:12.537] <TB2> INFO: Expecting 41600 events.
[10:39:16.763] <TB2> INFO: 41600 events read in total (3510ms).
[10:39:16.764] <TB2> INFO: Test took 4575ms.
[10:39:16.767] <TB2> INFO: scanning low vcal = 90
[10:39:17.101] <TB2> INFO: Expecting 41600 events.
[10:39:21.451] <TB2> INFO: 41600 events read in total (3633ms).
[10:39:21.452] <TB2> INFO: Test took 4685ms.
[10:39:21.455] <TB2> INFO: scanning low vcal = 100
[10:39:21.808] <TB2> INFO: Expecting 41600 events.
[10:39:26.040] <TB2> INFO: 41600 events read in total (3516ms).
[10:39:26.041] <TB2> INFO: Test took 4586ms.
[10:39:26.043] <TB2> INFO: scanning low vcal = 110
[10:39:26.398] <TB2> INFO: Expecting 41600 events.
[10:39:30.596] <TB2> INFO: 41600 events read in total (3482ms).
[10:39:30.596] <TB2> INFO: Test took 4553ms.
[10:39:30.599] <TB2> INFO: scanning low vcal = 120
[10:39:30.951] <TB2> INFO: Expecting 41600 events.
[10:39:35.144] <TB2> INFO: 41600 events read in total (3477ms).
[10:39:35.145] <TB2> INFO: Test took 4546ms.
[10:39:35.148] <TB2> INFO: scanning low vcal = 130
[10:39:35.498] <TB2> INFO: Expecting 41600 events.
[10:39:39.712] <TB2> INFO: 41600 events read in total (3498ms).
[10:39:39.713] <TB2> INFO: Test took 4565ms.
[10:39:39.715] <TB2> INFO: scanning low vcal = 140
[10:39:40.062] <TB2> INFO: Expecting 41600 events.
[10:39:44.272] <TB2> INFO: 41600 events read in total (3494ms).
[10:39:44.273] <TB2> INFO: Test took 4558ms.
[10:39:44.276] <TB2> INFO: scanning low vcal = 150
[10:39:44.629] <TB2> INFO: Expecting 41600 events.
[10:39:48.911] <TB2> INFO: 41600 events read in total (3566ms).
[10:39:48.911] <TB2> INFO: Test took 4635ms.
[10:39:48.914] <TB2> INFO: scanning low vcal = 160
[10:39:49.259] <TB2> INFO: Expecting 41600 events.
[10:39:53.468] <TB2> INFO: 41600 events read in total (3493ms).
[10:39:53.468] <TB2> INFO: Test took 4554ms.
[10:39:53.472] <TB2> INFO: scanning low vcal = 170
[10:39:53.819] <TB2> INFO: Expecting 41600 events.
[10:39:58.061] <TB2> INFO: 41600 events read in total (3526ms).
[10:39:58.061] <TB2> INFO: Test took 4589ms.
[10:39:58.065] <TB2> INFO: scanning low vcal = 180
[10:39:58.416] <TB2> INFO: Expecting 41600 events.
[10:40:02.689] <TB2> INFO: 41600 events read in total (3557ms).
[10:40:02.689] <TB2> INFO: Test took 4624ms.
[10:40:02.692] <TB2> INFO: scanning low vcal = 190
[10:40:03.044] <TB2> INFO: Expecting 41600 events.
[10:40:07.302] <TB2> INFO: 41600 events read in total (3542ms).
[10:40:07.303] <TB2> INFO: Test took 4611ms.
[10:40:07.306] <TB2> INFO: scanning low vcal = 200
[10:40:07.655] <TB2> INFO: Expecting 41600 events.
[10:40:11.864] <TB2> INFO: 41600 events read in total (3493ms).
[10:40:11.864] <TB2> INFO: Test took 4558ms.
[10:40:11.867] <TB2> INFO: scanning low vcal = 210
[10:40:12.211] <TB2> INFO: Expecting 41600 events.
[10:40:16.460] <TB2> INFO: 41600 events read in total (3533ms).
[10:40:16.461] <TB2> INFO: Test took 4594ms.
[10:40:16.463] <TB2> INFO: scanning low vcal = 220
[10:40:16.817] <TB2> INFO: Expecting 41600 events.
[10:40:21.066] <TB2> INFO: 41600 events read in total (3533ms).
[10:40:21.066] <TB2> INFO: Test took 4603ms.
[10:40:21.069] <TB2> INFO: scanning low vcal = 230
[10:40:21.423] <TB2> INFO: Expecting 41600 events.
[10:40:25.668] <TB2> INFO: 41600 events read in total (3529ms).
[10:40:25.668] <TB2> INFO: Test took 4599ms.
[10:40:25.671] <TB2> INFO: scanning low vcal = 240
[10:40:26.027] <TB2> INFO: Expecting 41600 events.
[10:40:30.380] <TB2> INFO: 41600 events read in total (3637ms).
[10:40:30.380] <TB2> INFO: Test took 4709ms.
[10:40:30.383] <TB2> INFO: scanning low vcal = 250
[10:40:30.734] <TB2> INFO: Expecting 41600 events.
[10:40:35.040] <TB2> INFO: 41600 events read in total (3590ms).
[10:40:35.040] <TB2> INFO: Test took 4657ms.
[10:40:35.044] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[10:40:35.393] <TB2> INFO: Expecting 41600 events.
[10:40:39.616] <TB2> INFO: 41600 events read in total (3507ms).
[10:40:39.617] <TB2> INFO: Test took 4573ms.
[10:40:39.619] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[10:40:39.971] <TB2> INFO: Expecting 41600 events.
[10:40:44.232] <TB2> INFO: 41600 events read in total (3545ms).
[10:40:44.232] <TB2> INFO: Test took 4613ms.
[10:40:44.235] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[10:40:44.588] <TB2> INFO: Expecting 41600 events.
[10:40:48.899] <TB2> INFO: 41600 events read in total (3594ms).
[10:40:48.900] <TB2> INFO: Test took 4665ms.
[10:40:48.902] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[10:40:49.251] <TB2> INFO: Expecting 41600 events.
[10:40:53.696] <TB2> INFO: 41600 events read in total (3729ms).
[10:40:53.697] <TB2> INFO: Test took 4795ms.
[10:40:53.699] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[10:40:54.043] <TB2> INFO: Expecting 41600 events.
[10:40:58.362] <TB2> INFO: 41600 events read in total (3602ms).
[10:40:58.362] <TB2> INFO: Test took 4663ms.
[10:40:59.083] <TB2> INFO: PixTestGainPedestal::measure() done
[10:41:32.085] <TB2> INFO: PixTestGainPedestal::fit() done
[10:41:32.085] <TB2> INFO: non-linearity mean: 0.963 0.960 0.958 0.960 0.958 0.957 0.965 0.956 0.962 0.960 0.948 0.955 0.958 0.956 0.958 0.948
[10:41:32.085] <TB2> INFO: non-linearity RMS: 0.005 0.005 0.005 0.006 0.006 0.005 0.005 0.006 0.006 0.006 0.007 0.006 0.005 0.005 0.007 0.006
[10:41:32.086] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C0.dat
[10:41:32.112] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C1.dat
[10:41:32.139] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C2.dat
[10:41:32.160] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C3.dat
[10:41:32.178] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C4.dat
[10:41:32.197] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C5.dat
[10:41:32.215] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C6.dat
[10:41:32.235] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C7.dat
[10:41:32.253] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C8.dat
[10:41:32.280] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C9.dat
[10:41:32.300] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C10.dat
[10:41:32.318] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C11.dat
[10:41:32.336] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C12.dat
[10:41:32.354] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C13.dat
[10:41:32.373] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C14.dat
[10:41:32.400] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//phCalibrationFitErr35_C15.dat
[10:41:32.420] <TB2> INFO: PixTestGainPedestal::doTest() done, duration: 170 seconds
[10:41:32.426] <TB2> INFO: readReadbackCal: /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C0.dat .. /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C15.dat
[10:41:32.427] <TB2> INFO: PixTestReadback::doTest() start.
[10:41:32.428] <TB2> INFO: PixTestReadback::RES sent once
[10:41:54.160] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C0.dat
[10:41:54.161] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C1.dat
[10:41:54.161] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C2.dat
[10:41:54.161] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C3.dat
[10:41:54.161] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C4.dat
[10:41:54.161] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C5.dat
[10:41:54.161] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C6.dat
[10:41:54.161] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C7.dat
[10:41:54.161] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C8.dat
[10:41:54.161] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C9.dat
[10:41:54.161] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C10.dat
[10:41:54.161] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C11.dat
[10:41:54.161] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C12.dat
[10:41:54.162] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C13.dat
[10:41:54.162] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C14.dat
[10:41:54.162] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C15.dat
[10:41:54.191] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:41:54.191] <TB2> INFO: PixTestReadback::RES sent once
[10:42:15.855] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C0.dat
[10:42:15.856] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C1.dat
[10:42:15.856] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C2.dat
[10:42:15.856] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C3.dat
[10:42:15.856] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C4.dat
[10:42:15.856] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C5.dat
[10:42:15.856] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C6.dat
[10:42:15.856] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C7.dat
[10:42:15.856] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C8.dat
[10:42:15.856] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C9.dat
[10:42:15.857] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C10.dat
[10:42:15.857] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C11.dat
[10:42:15.857] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C12.dat
[10:42:15.857] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C13.dat
[10:42:15.857] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C14.dat
[10:42:15.857] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C15.dat
[10:42:15.882] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:42:15.883] <TB2> INFO: PixTestReadback::RES sent once
[10:42:32.740] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:42:32.740] <TB2> INFO: Vbg will be calibrated using Vd calibration
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 158.9calibrated Vbg = 1.19313 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 152.5calibrated Vbg = 1.18899 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 146calibrated Vbg = 1.19402 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 255calibrated Vbg = 1.1775 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 150.1calibrated Vbg = 1.19556 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 154.1calibrated Vbg = 1.20411 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 149calibrated Vbg = 1.19954 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 255calibrated Vbg = 1.1775 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 147.9calibrated Vbg = 1.20468 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154.6calibrated Vbg = 1.20309 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 149.7calibrated Vbg = 1.19985 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 255calibrated Vbg = 1.1775 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 149.8calibrated Vbg = 1.19018 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152.4calibrated Vbg = 1.19249 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 151.9calibrated Vbg = 1.20091 :::*/*/*/*/
[10:42:32.740] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 255calibrated Vbg = 1.1775 :::*/*/*/*/
[10:42:32.743] <TB2> INFO: PixTestReadback::RES sent once
[10:47:12.927] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C0.dat
[10:47:12.928] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C1.dat
[10:47:12.928] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C2.dat
[10:47:12.928] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C3.dat
[10:47:12.928] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C4.dat
[10:47:12.928] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C5.dat
[10:47:12.928] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C6.dat
[10:47:12.928] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C7.dat
[10:47:12.928] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C8.dat
[10:47:12.928] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C9.dat
[10:47:12.928] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C10.dat
[10:47:12.929] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C11.dat
[10:47:12.929] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C12.dat
[10:47:12.929] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C13.dat
[10:47:12.929] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C14.dat
[10:47:12.929] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//000_FulltestPxar_m20//readbackCal_C15.dat
[10:47:12.958] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:47:12.959] <TB2> INFO: PixTestReadback::doTest() done
[10:47:12.972] <TB2> INFO: enter test to run
[10:47:12.972] <TB2> INFO: test: exit no parameter change
[10:47:13.547] <TB2> QUIET: Connection to board 156 closed.
[10:47:13.627] <TB2> INFO: pXar: this is the end, my friend