[11:30:19.418] <TB2> INFO: *** Welcome to pxar ***
[11:30:19.419] <TB2> INFO: *** Today: 2015/07/24
[11:30:19.419] <TB2> INFO: readRocDacs: /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C0.dat .. /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C15.dat
[11:30:19.419] <TB2> INFO: readTbmDacs: /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//tbmParameters_C0a.dat .. /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//tbmParameters_C0b.dat
[11:30:19.420] <TB2> INFO: readMaskFile: /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//defaultMaskFile.dat
[11:30:19.420] <TB2> INFO: readTrimFile: /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters_C0.dat .. /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters_C15.dat
[11:30:19.485] <TB2> INFO: clk: 4
[11:30:19.485] <TB2> INFO: ctr: 4
[11:30:19.485] <TB2> INFO: sda: 19
[11:30:19.485] <TB2> INFO: tin: 9
[11:30:19.485] <TB2> INFO: level: 15
[11:30:19.485] <TB2> INFO: triggerdelay: 0
[11:30:19.485] <TB2> QUIET: Instanciating API for pxar v2.2.5+46~gdbe75a1
[11:30:19.485] <TB2> INFO: Log level: INFO
[11:30:19.495] <TB2> INFO: Found DTB DTB_WXC55Z
[11:30:19.507] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[11:30:19.510] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.0
SW version: 4.0
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[11:30:19.514] <TB2> INFO: RPC call hashes of host and DTB match: 447413373
[11:30:21.090] <TB2> INFO: DUT info:
[11:30:21.090] <TB2> INFO: The DUT currently contains the following objects:
[11:30:21.090] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[11:30:21.090] <TB2> INFO: TBM Core alpha (0): 7 registers set
[11:30:21.090] <TB2> INFO: TBM Core beta (1): 7 registers set
[11:30:21.090] <TB2> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[11:30:21.090] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.090] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.091] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.091] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.091] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.091] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.091] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.091] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.091] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.091] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.091] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.091] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.091] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.091] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.091] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.091] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:30:21.494] <TB2> INFO: enter 'restricted' command line mode
[11:30:21.494] <TB2> INFO: enter test to run
[11:30:21.494] <TB2> INFO: test: pretest no parameter change
[11:30:21.494] <TB2> INFO: running: pretest
[11:30:21.503] <TB2> INFO: ######################################################################
[11:30:21.504] <TB2> INFO: PixTestPretest::doTest()
[11:30:21.504] <TB2> INFO: ######################################################################
[11:30:21.505] <TB2> INFO: ----------------------------------------------------------------------
[11:30:21.505] <TB2> INFO: PixTestPretest::programROC()
[11:30:21.505] <TB2> INFO: ----------------------------------------------------------------------
[11:30:39.523] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:30:39.523] <TB2> INFO: IA differences per ROC: 17.7 20.1 21.7 17.7 18.5 16.9 18.5 17.7 18.5 18.5 16.9 19.3 19.3 19.3 16.1 17.7
[11:30:39.591] <TB2> INFO: ----------------------------------------------------------------------
[11:30:39.591] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:30:39.591] <TB2> INFO: ----------------------------------------------------------------------
[11:30:59.138] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 379.4 mA = 23.7125 mA/ROC
[11:30:59.141] <TB2> INFO: ----------------------------------------------------------------------
[11:30:59.141] <TB2> INFO: PixTestPretest::findWorkingPixel()
[11:30:59.141] <TB2> INFO: ----------------------------------------------------------------------
[11:31:08.512] <TB2> INFO: Test took 9365ms.
[11:31:08.806] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:31:08.839] <TB2> INFO: ----------------------------------------------------------------------
[11:31:08.839] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[11:31:08.839] <TB2> INFO: ----------------------------------------------------------------------
[11:31:17.928] <TB2> INFO: Test took 9083ms.
[11:31:18.235] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[11:31:18.235] <TB2> INFO: CalDel: 124 133 129 133 135 142 122 130 140 123 122 145 139 142 142 144
[11:31:18.236] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[11:31:18.239] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C0.dat
[11:31:18.240] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C1.dat
[11:31:18.240] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C2.dat
[11:31:18.240] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C3.dat
[11:31:18.240] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C4.dat
[11:31:18.240] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C5.dat
[11:31:18.241] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C6.dat
[11:31:18.241] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C7.dat
[11:31:18.241] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C8.dat
[11:31:18.242] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C9.dat
[11:31:18.242] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C10.dat
[11:31:18.242] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C11.dat
[11:31:18.242] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C12.dat
[11:31:18.243] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C13.dat
[11:31:18.243] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C14.dat
[11:31:18.243] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters_C15.dat
[11:31:18.243] <TB2> INFO: PixTestPretest::doTest() done, duration: 56 seconds
[11:31:18.337] <TB2> INFO: enter test to run
[11:31:18.337] <TB2> INFO: test: fulltest no parameter change
[11:31:18.338] <TB2> INFO: running: fulltest
[11:31:18.338] <TB2> INFO: ######################################################################
[11:31:18.338] <TB2> INFO: PixTestFullTest::doTest()
[11:31:18.338] <TB2> INFO: ######################################################################
[11:31:18.339] <TB2> INFO: ######################################################################
[11:31:18.339] <TB2> INFO: PixTestAlive::doTest()
[11:31:18.339] <TB2> INFO: ######################################################################
[11:31:18.341] <TB2> INFO: ----------------------------------------------------------------------
[11:31:18.341] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:31:18.341] <TB2> INFO: ----------------------------------------------------------------------
[11:31:21.997] <TB2> INFO: Test took 3655ms.
[11:31:22.024] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:31:22.246] <TB2> INFO: PixTestAlive::aliveTest() done
[11:31:22.246] <TB2> INFO: number of dead pixels (per ROC): 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
[11:31:22.249] <TB2> INFO: ----------------------------------------------------------------------
[11:31:22.249] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:31:22.249] <TB2> INFO: ----------------------------------------------------------------------
[11:31:25.112] <TB2> INFO: Test took 2861ms.
[11:31:25.115] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:31:25.116] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:31:25.333] <TB2> INFO: PixTestAlive::maskTest() done
[11:31:25.334] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:31:25.335] <TB2> INFO: ----------------------------------------------------------------------
[11:31:25.335] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:31:25.335] <TB2> INFO: ----------------------------------------------------------------------
[11:31:29.086] <TB2> INFO: Test took 3750ms.
[11:31:29.112] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:31:29.339] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[11:31:29.339] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:31:29.339] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:31:29.352] <TB2> INFO: ######################################################################
[11:31:29.352] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:31:29.353] <TB2> INFO: ######################################################################
[11:31:29.355] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (30) hits flags = 2 (plus default)
[11:31:29.408] <TB2> INFO: dacScan step from 0 .. 29
[11:31:53.059] <TB2> INFO: Test took 23650ms.
[11:31:53.098] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:31:53.098] <TB2> INFO: dacScan step from 30 .. 59
[11:32:20.822] <TB2> INFO: Test took 27724ms.
[11:32:21.005] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:32:21.031] <TB2> INFO: dacScan step from 60 .. 89
[11:32:54.226] <TB2> INFO: Test took 33195ms.
[11:32:54.576] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:32:54.653] <TB2> INFO: dacScan step from 90 .. 119
[11:33:25.738] <TB2> INFO: Test took 31085ms.
[11:33:26.046] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:33:26.123] <TB2> INFO: dacScan step from 120 .. 149
[11:33:53.979] <TB2> INFO: Test took 27856ms.
[11:33:54.158] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:34:16.959] <TB2> INFO: PixTestBBMap::doTest() done, duration: 167 seconds
[11:34:16.959] <TB2> INFO: number of dead bumps (per ROC): 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0
[11:34:16.959] <TB2> INFO: separation cut (per ROC): 71 104 100 85 81 69 93 74 80 68 78 77 69 71 66 71
[11:34:17.044] <TB2> INFO: ######################################################################
[11:34:17.044] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50
[11:34:17.044] <TB2> INFO: ######################################################################
[11:34:17.045] <TB2> INFO: ----------------------------------------------------------------------
[11:34:17.045] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50
[11:34:17.045] <TB2> INFO: ----------------------------------------------------------------------
[11:34:17.045] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 0 .. 149 (4) hits flags = 16 (plus default)
[11:34:17.054] <TB2> INFO: dacScan step from 0 .. 3
[11:34:38.398] <TB2> INFO: Test took 21344ms.
[11:34:38.425] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:34:38.425] <TB2> INFO: dacScan step from 4 .. 7
[11:34:59.989] <TB2> INFO: Test took 21564ms.
[11:35:00.018] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:35:00.018] <TB2> INFO: dacScan step from 8 .. 11
[11:35:21.564] <TB2> INFO: Test took 21546ms.
[11:35:21.595] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:35:21.595] <TB2> INFO: dacScan step from 12 .. 15
[11:35:43.127] <TB2> INFO: Test took 21532ms.
[11:35:43.154] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:35:43.154] <TB2> INFO: dacScan step from 16 .. 19
[11:36:04.705] <TB2> INFO: Test took 21550ms.
[11:36:04.737] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:36:04.737] <TB2> INFO: dacScan step from 20 .. 23
[11:36:26.322] <TB2> INFO: Test took 21585ms.
[11:36:26.348] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:36:26.348] <TB2> INFO: dacScan step from 24 .. 27
[11:36:47.871] <TB2> INFO: Test took 21522ms.
[11:36:47.897] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:36:47.897] <TB2> INFO: dacScan step from 28 .. 31
[11:37:09.494] <TB2> INFO: Test took 21597ms.
[11:37:09.521] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:37:09.521] <TB2> INFO: dacScan step from 32 .. 35
[11:37:31.012] <TB2> INFO: Test took 21491ms.
[11:37:31.038] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:37:31.038] <TB2> INFO: dacScan step from 36 .. 39
[11:37:52.571] <TB2> INFO: Test took 21533ms.
[11:37:52.598] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:37:52.598] <TB2> INFO: dacScan step from 40 .. 43
[11:38:14.054] <TB2> INFO: Test took 21456ms.
[11:38:14.088] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:38:14.088] <TB2> INFO: dacScan step from 44 .. 47
[11:38:35.703] <TB2> INFO: Test took 21615ms.
[11:38:35.734] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:38:35.734] <TB2> INFO: dacScan step from 48 .. 51
[11:38:57.187] <TB2> INFO: Test took 21453ms.
[11:38:57.215] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:38:57.216] <TB2> INFO: dacScan step from 52 .. 55
[11:39:18.824] <TB2> INFO: Test took 21608ms.
[11:39:18.860] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:39:18.860] <TB2> INFO: dacScan step from 56 .. 59
[11:39:41.031] <TB2> INFO: Test took 22170ms.
[11:39:41.075] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:39:41.075] <TB2> INFO: dacScan step from 60 .. 63
[11:40:04.269] <TB2> INFO: Test took 23194ms.
[11:40:04.325] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:40:04.326] <TB2> INFO: dacScan step from 64 .. 67
[11:40:27.720] <TB2> INFO: Test took 23394ms.
[11:40:27.791] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:40:27.794] <TB2> INFO: dacScan step from 68 .. 71
[11:40:52.576] <TB2> INFO: Test took 24782ms.
[11:40:52.654] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:40:52.658] <TB2> INFO: dacScan step from 72 .. 75
[11:41:19.175] <TB2> INFO: Test took 26509ms.
[11:41:19.275] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:41:19.282] <TB2> INFO: dacScan step from 76 .. 79
[11:41:48.457] <TB2> INFO: Test took 29175ms.
[11:41:48.584] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:41:48.592] <TB2> INFO: dacScan step from 80 .. 83
[11:42:20.538] <TB2> INFO: Test took 31946ms.
[11:42:20.721] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:42:20.732] <TB2> INFO: dacScan step from 84 .. 87


[11:42:54.313] <TB2> INFO: Test took 33581ms.
[11:42:54.607] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:42:54.616] <TB2> INFO: dacScan step from 88 .. 91


[11:43:28.631] <TB2> INFO: Test took 34015ms.
[11:43:28.837] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:43:28.849] <TB2> INFO: dacScan step from 92 .. 95


[11:44:03.597] <TB2> INFO: Test took 34748ms.
[11:44:03.843] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:44:03.855] <TB2> INFO: dacScan step from 96 .. 99


[11:44:38.049] <TB2> INFO: Test took 34194ms.
[11:44:38.287] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:44:38.297] <TB2> INFO: dacScan step from 100 .. 103



[11:45:12.491] <TB2> INFO: Test took 34194ms.
[11:45:12.759] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:45:12.771] <TB2> INFO: dacScan step from 104 .. 107


[11:45:46.677] <TB2> INFO: Test took 33906ms.
[11:45:46.941] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:45:46.954] <TB2> INFO: dacScan step from 108 .. 111
[11:46:21.404] <TB2> INFO: Test took 34450ms.
[11:46:21.748] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:46:21.761] <TB2> INFO: dacScan step from 112 .. 115
[11:46:56.349] <TB2> INFO: Test took 34588ms.
[11:46:56.639] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:46:56.653] <TB2> INFO: dacScan step from 116 .. 119
[11:47:30.813] <TB2> INFO: Test took 34160ms.
[11:47:31.049] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:47:31.060] <TB2> INFO: dacScan step from 120 .. 123
[11:48:05.464] <TB2> INFO: Test took 34404ms.
[11:48:05.685] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:48:05.695] <TB2> INFO: dacScan step from 124 .. 127
[11:48:37.894] <TB2> INFO: Test took 32199ms.
[11:48:38.112] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:48:38.123] <TB2> INFO: dacScan step from 128 .. 131
[11:49:09.547] <TB2> INFO: Test took 31424ms.
[11:49:09.776] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:49:09.787] <TB2> INFO: dacScan step from 132 .. 135
[11:49:42.682] <TB2> INFO: Test took 32894ms.
[11:49:42.932] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:49:42.942] <TB2> INFO: dacScan step from 136 .. 139
[11:50:17.209] <TB2> INFO: Test took 34267ms.
[11:50:17.445] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:50:17.455] <TB2> INFO: dacScan step from 140 .. 143
[11:50:51.501] <TB2> INFO: Test took 34046ms.
[11:50:51.739] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:50:51.754] <TB2> INFO: dacScan step from 144 .. 147
[11:51:23.852] <TB2> INFO: Test took 32098ms.
[11:51:24.081] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:51:24.091] <TB2> INFO: dacScan step from 148 .. 149
[11:51:41.693] <TB2> INFO: Test took 17600ms.
[11:51:41.883] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:51:41.894] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:51:43.338] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:51:44.700] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:51:46.078] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:51:47.482] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:51:49.015] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:51:50.714] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:51:52.449] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:51:54.270] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:51:55.911] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:51:57.579] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:51:59.256] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:52:00.782] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:52:02.422] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:52:04.019] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:52:05.703] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:52:07.419] <TB2> INFO: PixTestScurves::scurves() done
[11:52:07.419] <TB2> INFO: Vcal mean: 78.21 101.87 91.22 84.07 89.72 82.06 84.05 73.26 87.41 71.96 83.43 79.61 60.95 80.30 74.80 76.46
[11:52:07.419] <TB2> INFO: Vcal RMS: 4.15 6.55 5.41 5.55 5.28 4.83 5.57 4.40 4.80 4.85 5.14 4.26 4.75 4.46 4.08 4.00
[11:52:07.419] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1070 seconds
[11:52:07.511] <TB2> INFO: ######################################################################
[11:52:07.511] <TB2> INFO: PixTestTrim::doTest()
[11:52:07.511] <TB2> INFO: ######################################################################
[11:52:07.512] <TB2> INFO: ----------------------------------------------------------------------
[11:52:07.512] <TB2> INFO: PixTestTrim::trimTest() ntrig = 10, vcal = 35
[11:52:07.512] <TB2> INFO: ----------------------------------------------------------------------
[11:52:07.600] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[11:52:07.600] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 5 dacrange: 0 .. 159 (20) hits flags = 16 (plus default)
[11:52:07.609] <TB2> INFO: dacScan step from 0 .. 19
[11:52:24.037] <TB2> INFO: Test took 16428ms.
[11:52:24.064] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:52:24.064] <TB2> INFO: dacScan step from 20 .. 39
[11:52:40.223] <TB2> INFO: Test took 16158ms.
[11:52:40.249] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:52:40.249] <TB2> INFO: dacScan step from 40 .. 59
[11:52:56.579] <TB2> INFO: Test took 16330ms.
[11:52:56.606] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:52:56.606] <TB2> INFO: dacScan step from 60 .. 79
[11:53:13.334] <TB2> INFO: Test took 16728ms.
[11:53:13.363] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:53:13.364] <TB2> INFO: dacScan step from 80 .. 99
[11:53:32.648] <TB2> INFO: Test took 19284ms.
[11:53:32.748] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:53:32.762] <TB2> INFO: dacScan step from 100 .. 119
[11:53:54.661] <TB2> INFO: Test took 21899ms.
[11:53:54.837] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:53:54.874] <TB2> INFO: dacScan step from 120 .. 139
[11:54:14.597] <TB2> INFO: Test took 19723ms.
[11:54:14.733] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:54:14.757] <TB2> INFO: dacScan step from 140 .. 159
[11:54:31.677] <TB2> INFO: Test took 16920ms.
[11:54:31.742] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:54:53.769] <TB2> INFO: ROC 0 VthrComp = 82
[11:54:53.769] <TB2> INFO: ROC 1 VthrComp = 103
[11:54:53.770] <TB2> INFO: ROC 2 VthrComp = 100
[11:54:53.770] <TB2> INFO: ROC 3 VthrComp = 89
[11:54:53.770] <TB2> INFO: ROC 4 VthrComp = 93
[11:54:53.770] <TB2> INFO: ROC 5 VthrComp = 85
[11:54:53.770] <TB2> INFO: ROC 6 VthrComp = 90
[11:54:53.770] <TB2> INFO: ROC 7 VthrComp = 80
[11:54:53.770] <TB2> INFO: ROC 8 VthrComp = 96
[11:54:53.770] <TB2> INFO: ROC 9 VthrComp = 78
[11:54:53.770] <TB2> INFO: ROC 10 VthrComp = 87
[11:54:53.770] <TB2> INFO: ROC 11 VthrComp = 87
[11:54:53.770] <TB2> INFO: ROC 12 VthrComp = 69
[11:54:53.771] <TB2> INFO: ROC 13 VthrComp = 86
[11:54:53.771] <TB2> INFO: ROC 14 VthrComp = 79
[11:54:53.771] <TB2> INFO: ROC 15 VthrComp = 82
[11:54:53.771] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[11:54:53.771] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 5 dacrange: 0 .. 159 (20) hits flags = 16 (plus default)
[11:54:53.779] <TB2> INFO: dacScan step from 0 .. 19
[11:55:10.042] <TB2> INFO: Test took 16263ms.
[11:55:10.068] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:55:10.068] <TB2> INFO: dacScan step from 20 .. 39
[11:55:27.320] <TB2> INFO: Test took 17251ms.
[11:55:27.361] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:55:27.365] <TB2> INFO: dacScan step from 40 .. 59
[11:55:48.945] <TB2> INFO: Test took 21580ms.
[11:55:49.112] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:55:49.153] <TB2> INFO: dacScan step from 60 .. 79
[11:56:11.839] <TB2> INFO: Test took 22685ms.
[11:56:12.053] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:56:12.111] <TB2> INFO: dacScan step from 80 .. 99
[11:56:34.441] <TB2> INFO: Test took 22330ms.
[11:56:34.604] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:56:34.649] <TB2> INFO: dacScan step from 100 .. 119
[11:56:57.451] <TB2> INFO: Test took 22802ms.
[11:56:57.615] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:56:57.661] <TB2> INFO: dacScan step from 120 .. 139
[11:57:20.527] <TB2> INFO: Test took 22866ms.
[11:57:20.710] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:57:20.757] <TB2> INFO: dacScan step from 140 .. 159
[11:57:43.665] <TB2> INFO: Test took 22908ms.
[11:57:43.831] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:58:11.562] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 57.4989 for pixel 20/8 mean/min/max = 45.1757/32.7989/57.5525
[11:58:11.562] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 64.6714 for pixel 0/77 mean/min/max = 48.8313/32.8435/64.8192
[11:58:11.562] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 58.2143 for pixel 0/9 mean/min/max = 44.889/31.5075/58.2706
[11:58:11.563] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 59.8666 for pixel 5/79 mean/min/max = 46.0991/32.0559/60.1424
[11:58:11.563] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 58.6684 for pixel 0/59 mean/min/max = 45.3806/31.9866/58.7745
[11:58:11.563] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 59.9331 for pixel 2/7 mean/min/max = 46.2563/32.5249/59.9877
[11:58:11.564] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 60.4517 for pixel 0/58 mean/min/max = 45.9568/31.4032/60.5104
[11:58:11.564] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 56.5835 for pixel 0/71 mean/min/max = 44.649/32.6916/56.6064
[11:58:11.564] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 56.1945 for pixel 6/2 mean/min/max = 44.162/31.8304/56.4937
[11:58:11.564] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 59.0282 for pixel 2/55 mean/min/max = 47.0012/34.9484/59.0541
[11:58:11.565] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 58.3076 for pixel 0/17 mean/min/max = 45.1587/31.9281/58.3893
[11:58:11.565] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 56.376 for pixel 45/79 mean/min/max = 44.2037/31.9897/56.4177
[11:58:11.565] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 55.6935 for pixel 16/74 mean/min/max = 43.4814/31.2278/55.7349
[11:58:11.566] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 57.1782 for pixel 0/38 mean/min/max = 44.8826/32.5403/57.2249
[11:58:11.566] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 57.0369 for pixel 8/12 mean/min/max = 46.133/35.1862/57.0799
[11:58:11.566] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 55.5841 for pixel 51/78 mean/min/max = 44.168/32.6645/55.6714
[11:58:11.566] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:01.751] <TB2> INFO: Test took 110185ms.
[12:00:03.261] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 10 dacrange: 0 .. 199 (20) hits flags = 16 (plus default)
[12:00:03.270] <TB2> INFO: dacScan step from 0 .. 19
[12:00:28.874] <TB2> INFO: Test took 25604ms.
[12:00:28.927] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:00:28.929] <TB2> INFO: dacScan step from 20 .. 39
[12:01:02.407] <TB2> INFO: Test took 33478ms.
[12:01:02.649] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:01:02.680] <TB2> INFO: dacScan step from 40 .. 59



[12:01:38.073] <TB2> INFO: Test took 35393ms.
[12:01:38.383] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:01:38.428] <TB2> INFO: dacScan step from 60 .. 79





[12:02:13.739] <TB2> INFO: Test took 35311ms.
[12:02:14.028] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:02:14.081] <TB2> INFO: dacScan step from 80 .. 99


[12:02:52.648] <TB2> INFO: Test took 38566ms.
[12:02:52.916] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:02:52.961] <TB2> INFO: dacScan step from 100 .. 119


[12:03:30.722] <TB2> INFO: Test took 37761ms.
[12:03:31.020] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:03:31.070] <TB2> INFO: dacScan step from 120 .. 139



[12:04:09.182] <TB2> INFO: Test took 38112ms.
[12:04:09.453] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:04:09.498] <TB2> INFO: dacScan step from 140 .. 159


[12:04:47.373] <TB2> INFO: Test took 37875ms.
[12:04:47.657] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:04:47.700] <TB2> INFO: dacScan step from 160 .. 179



[12:05:25.338] <TB2> INFO: Test took 37637ms.
[12:05:25.671] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:05:25.716] <TB2> INFO: dacScan step from 180 .. 199


[12:06:01.143] <TB2> INFO: Test took 35427ms.
[12:06:01.418] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:06:27.753] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 0.030066 .. 255.000000
[12:06:27.837] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 4 dacrange: 0 .. 255 (20) hits flags = 16 (plus default)
[12:06:27.846] <TB2> INFO: dacScan step from 0 .. 19
[12:06:42.457] <TB2> INFO: Test took 14611ms.
[12:06:42.477] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:06:42.477] <TB2> INFO: dacScan step from 20 .. 39
[12:06:58.735] <TB2> INFO: Test took 16258ms.
[12:06:58.825] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:06:58.840] <TB2> INFO: dacScan step from 40 .. 59
[12:07:17.903] <TB2> INFO: Test took 19063ms.
[12:07:18.140] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:07:18.239] <TB2> INFO: dacScan step from 60 .. 79
[12:07:37.077] <TB2> INFO: Test took 18838ms.
[12:07:37.233] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:07:37.289] <TB2> INFO: dacScan step from 80 .. 99
[12:07:57.037] <TB2> INFO: Test took 19748ms.
[12:07:57.179] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:07:57.227] <TB2> INFO: dacScan step from 100 .. 119
[12:08:15.967] <TB2> INFO: Test took 18740ms.
[12:08:16.135] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:08:16.183] <TB2> INFO: dacScan step from 120 .. 139
[12:08:36.274] <TB2> INFO: Test took 20091ms.
[12:08:36.441] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:08:36.490] <TB2> INFO: dacScan step from 140 .. 159
[12:08:55.407] <TB2> INFO: Test took 18917ms.
[12:08:55.544] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:08:55.592] <TB2> INFO: dacScan step from 160 .. 179
[12:09:14.505] <TB2> INFO: Test took 18913ms.
[12:09:14.667] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:09:14.713] <TB2> INFO: dacScan step from 180 .. 199
[12:09:35.328] <TB2> INFO: Test took 20615ms.
[12:09:35.519] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:09:35.572] <TB2> INFO: dacScan step from 200 .. 219
[12:09:55.304] <TB2> INFO: Test took 19732ms.
[12:09:55.459] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:09:55.507] <TB2> INFO: dacScan step from 220 .. 239
[12:10:14.413] <TB2> INFO: Test took 18906ms.
[12:10:14.553] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:10:14.593] <TB2> INFO: dacScan step from 240 .. 255
[12:10:30.173] <TB2> INFO: Test took 15580ms.
[12:10:30.339] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:11:01.023] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 0.351079 .. 44.968355
[12:11:01.118] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 4 dacrange: 0 .. 54 (20) hits flags = 16 (plus default)
[12:11:01.127] <TB2> INFO: dacScan step from 0 .. 19
[12:11:15.727] <TB2> INFO: Test took 14600ms.
[12:11:15.756] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:11:15.756] <TB2> INFO: dacScan step from 20 .. 39
[12:11:32.545] <TB2> INFO: Test took 16788ms.
[12:11:32.626] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:11:32.644] <TB2> INFO: dacScan step from 40 .. 54
[12:11:47.543] <TB2> INFO: Test took 14899ms.
[12:11:47.659] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:12:04.045] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 0.351079 .. 41.984336
[12:12:04.124] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 4 dacrange: 0 .. 51 (20) hits flags = 16 (plus default)
[12:12:04.134] <TB2> INFO: dacScan step from 0 .. 19
[12:12:18.641] <TB2> INFO: Test took 14507ms.
[12:12:18.665] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:12:18.665] <TB2> INFO: dacScan step from 20 .. 39
[12:12:34.783] <TB2> INFO: Test took 16118ms.
[12:12:34.857] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:12:34.874] <TB2> INFO: dacScan step from 40 .. 51
[12:12:47.957] <TB2> INFO: Test took 13083ms.
[12:12:48.060] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:13:03.984] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 0.351079 .. 40.981887
[12:13:04.064] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 4 dacrange: 0 .. 50 (20) hits flags = 16 (plus default)
[12:13:04.073] <TB2> INFO: dacScan step from 0 .. 19
[12:13:18.821] <TB2> INFO: Test took 14748ms.
[12:13:18.846] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:13:18.846] <TB2> INFO: dacScan step from 20 .. 39
[12:13:35.093] <TB2> INFO: Test took 16247ms.
[12:13:35.169] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:13:35.190] <TB2> INFO: dacScan step from 40 .. 50
[12:13:47.345] <TB2> INFO: Test took 12155ms.
[12:13:47.438] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:14:02.761] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:14:02.761] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 10 dacrange: 15 .. 55 (20) hits flags = 16 (plus default)
[12:14:02.769] <TB2> INFO: dacScan step from 15 .. 34
[12:14:29.205] <TB2> INFO: Test took 26436ms.
[12:14:29.277] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:14:29.291] <TB2> INFO: dacScan step from 35 .. 54


[12:15:04.195] <TB2> INFO: Test took 34904ms.
[12:15:04.506] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:15:04.561] <TB2> INFO: dacScan step from 55 .. 55
[12:15:08.998] <TB2> INFO: Test took 4437ms.
[12:15:09.013] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:15:23.121] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C0.dat
[12:15:23.121] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C1.dat
[12:15:23.122] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C2.dat
[12:15:23.122] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C3.dat
[12:15:23.122] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C4.dat
[12:15:23.122] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C5.dat
[12:15:23.122] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C6.dat
[12:15:23.122] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C7.dat
[12:15:23.122] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C8.dat
[12:15:23.122] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C9.dat
[12:15:23.122] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C10.dat
[12:15:23.123] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C11.dat
[12:15:23.123] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C12.dat
[12:15:23.123] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C13.dat
[12:15:23.123] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C14.dat
[12:15:23.123] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C15.dat
[12:15:23.123] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C0.dat
[12:15:23.131] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C1.dat
[12:15:23.137] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C2.dat
[12:15:23.145] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C3.dat
[12:15:23.154] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C4.dat
[12:15:23.164] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C5.dat
[12:15:23.173] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C6.dat
[12:15:23.183] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C7.dat
[12:15:23.192] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C8.dat
[12:15:23.198] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C9.dat
[12:15:23.205] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C10.dat
[12:15:23.214] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C11.dat
[12:15:23.223] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C12.dat
[12:15:23.231] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C13.dat
[12:15:23.241] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C14.dat
[12:15:23.250] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//trimParameters35_C15.dat
[12:15:23.259] <TB2> INFO: PixTestTrim::trimTest() done
[12:15:23.260] <TB2> INFO: vtrim: 101 124 109 192 111 114 118 106 116 114 101 92 90 105 103 97
[12:15:23.260] <TB2> INFO: vthrcomp: 82 103 100 89 93 85 90 80 96 78 87 87 69 86 79 82
[12:15:23.260] <TB2> INFO: vcal mean: 35.05 35.10 34.99 34.96 35.03 35.05 35.02 35.06 35.03 35.04 35.04 35.02 35.05 35.04 35.03 35.05
[12:15:23.260] <TB2> INFO: vcal RMS: 1.02 1.19 1.00 1.84 1.07 1.06 1.00 0.93 1.03 0.98 1.05 0.99 0.98 1.05 0.92 1.02
[12:15:23.260] <TB2> INFO: bits mean: 10.05 8.88 9.40 11.58 9.79 9.81 9.78 9.75 10.64 9.17 9.50 9.96 10.64 9.72 8.98 9.89
[12:15:23.260] <TB2> INFO: bits RMS: 2.37 2.62 2.85 1.67 2.54 2.49 2.63 2.53 2.24 2.37 2.72 2.59 2.39 2.59 2.39 2.53
[12:15:23.267] <TB2> INFO: ----------------------------------------------------------------------
[12:15:23.267] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 10, vtrims = 254 126 63 32
[12:15:23.267] <TB2> INFO: ----------------------------------------------------------------------
[12:15:23.269] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 10 dacrange: 0 .. 199 (20) hits flags = 16 (plus default)
[12:15:23.277] <TB2> INFO: dacScan step from 0 .. 19
[12:15:48.281] <TB2> INFO: Test took 25004ms.
[12:15:48.317] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:15:48.317] <TB2> INFO: dacScan step from 20 .. 39
[12:16:13.569] <TB2> INFO: Test took 25252ms.
[12:16:13.609] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:16:13.609] <TB2> INFO: dacScan step from 40 .. 59
[12:16:37.747] <TB2> INFO: Test took 24138ms.
[12:16:37.784] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:16:37.784] <TB2> INFO: dacScan step from 60 .. 79
[12:17:02.365] <TB2> INFO: Test took 24581ms.
[12:17:02.415] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:17:02.415] <TB2> INFO: dacScan step from 80 .. 99
[12:17:30.658] <TB2> INFO: Test took 28243ms.
[12:17:30.797] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:17:30.814] <TB2> INFO: dacScan step from 100 .. 119

[12:18:07.275] <TB2> INFO: Test took 36461ms.
[12:18:07.557] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:18:07.593] <TB2> INFO: dacScan step from 120 .. 139
[12:18:45.840] <TB2> INFO: Test took 38247ms.
[12:18:46.130] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:18:46.173] <TB2> INFO: dacScan step from 140 .. 159
[12:19:22.117] <TB2> INFO: Test took 35944ms.
[12:19:22.459] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:19:22.521] <TB2> INFO: dacScan step from 160 .. 179
[12:20:00.718] <TB2> INFO: Test took 38197ms.
[12:20:00.999] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:20:01.044] <TB2> INFO: dacScan step from 180 .. 199
[12:20:38.544] <TB2> INFO: Test took 37500ms.
[12:20:38.831] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:21:06.996] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 10 dacrange: 0 .. 172 (20) hits flags = 16 (plus default)
[12:21:07.004] <TB2> INFO: dacScan step from 0 .. 19
[12:21:32.273] <TB2> INFO: Test took 25269ms.
[12:21:32.311] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:21:32.311] <TB2> INFO: dacScan step from 20 .. 39
[12:21:57.629] <TB2> INFO: Test took 25317ms.
[12:21:57.666] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:21:57.666] <TB2> INFO: dacScan step from 40 .. 59
[12:22:22.973] <TB2> INFO: Test took 25307ms.
[12:22:23.017] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:22:23.017] <TB2> INFO: dacScan step from 60 .. 79
[12:22:48.940] <TB2> INFO: Test took 25922ms.
[12:22:49.000] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:22:49.001] <TB2> INFO: dacScan step from 80 .. 99
[12:23:18.785] <TB2> INFO: Test took 29784ms.
[12:23:18.967] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:23:18.985] <TB2> INFO: dacScan step from 100 .. 119


[12:23:56.586] <TB2> INFO: Test took 37600ms.
[12:23:56.851] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:23:56.886] <TB2> INFO: dacScan step from 120 .. 139





[12:24:34.664] <TB2> INFO: Test took 37778ms.
[12:24:34.956] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:24:35.000] <TB2> INFO: dacScan step from 140 .. 159
[12:25:10.276] <TB2> INFO: Test took 35276ms.
[12:25:10.550] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:25:10.596] <TB2> INFO: dacScan step from 160 .. 172
[12:25:34.810] <TB2> INFO: Test took 24214ms.
[12:25:34.999] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:26:00.794] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 10 dacrange: 0 .. 160 (20) hits flags = 16 (plus default)
[12:26:00.802] <TB2> INFO: dacScan step from 0 .. 19
[12:26:25.832] <TB2> INFO: Test took 25030ms.
[12:26:25.873] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:26:25.873] <TB2> INFO: dacScan step from 20 .. 39
[12:26:50.702] <TB2> INFO: Test took 24829ms.
[12:26:50.736] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:26:50.736] <TB2> INFO: dacScan step from 40 .. 59
[12:27:15.151] <TB2> INFO: Test took 24415ms.
[12:27:15.185] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:27:15.185] <TB2> INFO: dacScan step from 60 .. 79
[12:27:41.111] <TB2> INFO: Test took 25926ms.
[12:27:41.164] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:27:41.165] <TB2> INFO: dacScan step from 80 .. 99
[12:28:13.249] <TB2> INFO: Test took 32084ms.
[12:28:13.417] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:28:13.434] <TB2> INFO: dacScan step from 100 .. 119


[12:28:51.097] <TB2> INFO: Test took 37663ms.
[12:28:51.391] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:28:51.434] <TB2> INFO: dacScan step from 120 .. 139

[12:29:28.379] <TB2> INFO: Test took 36946ms.
[12:29:28.660] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:29:28.703] <TB2> INFO: dacScan step from 140 .. 159
[12:30:04.602] <TB2> INFO: Test took 35899ms.
[12:30:04.938] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:30:04.993] <TB2> INFO: dacScan step from 160 .. 160
[12:30:09.379] <TB2> INFO: Test took 4386ms.
[12:30:09.393] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:30:31.980] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 10 dacrange: 0 .. 160 (20) hits flags = 16 (plus default)
[12:30:31.988] <TB2> INFO: dacScan step from 0 .. 19
[12:30:57.179] <TB2> INFO: Test took 25191ms.
[12:30:57.214] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:30:57.214] <TB2> INFO: dacScan step from 20 .. 39
[12:31:21.314] <TB2> INFO: Test took 24100ms.
[12:31:21.353] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:31:21.353] <TB2> INFO: dacScan step from 40 .. 59
[12:31:46.800] <TB2> INFO: Test took 25447ms.
[12:31:46.841] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:31:46.841] <TB2> INFO: dacScan step from 60 .. 79
[12:32:12.868] <TB2> INFO: Test took 26027ms.
[12:32:12.919] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:32:12.921] <TB2> INFO: dacScan step from 80 .. 99
[12:32:43.528] <TB2> INFO: Test took 30607ms.
[12:32:43.697] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:32:43.714] <TB2> INFO: dacScan step from 100 .. 119


[12:33:22.151] <TB2> INFO: Test took 38437ms.
[12:33:22.478] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:33:22.535] <TB2> INFO: dacScan step from 120 .. 139

[12:33:59.423] <TB2> INFO: Test took 36888ms.
[12:33:59.699] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:33:59.745] <TB2> INFO: dacScan step from 140 .. 159
[12:34:36.522] <TB2> INFO: Test took 36777ms.
[12:34:36.831] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:34:36.875] <TB2> INFO: dacScan step from 160 .. 160
[12:34:41.489] <TB2> INFO: Test took 4614ms.
[12:34:41.510] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:35:04.467] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 10 dacrange: 0 .. 160 (20) hits flags = 16 (plus default)
[12:35:04.477] <TB2> INFO: dacScan step from 0 .. 19
[12:35:29.822] <TB2> INFO: Test took 25345ms.
[12:35:29.857] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:35:29.857] <TB2> INFO: dacScan step from 20 .. 39
[12:35:54.951] <TB2> INFO: Test took 25094ms.
[12:35:54.989] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:35:54.989] <TB2> INFO: dacScan step from 40 .. 59
[12:36:20.460] <TB2> INFO: Test took 25471ms.
[12:36:20.501] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:36:20.501] <TB2> INFO: dacScan step from 60 .. 79
[12:36:46.563] <TB2> INFO: Test took 26062ms.
[12:36:46.623] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:36:46.624] <TB2> INFO: dacScan step from 80 .. 99
[12:37:18.670] <TB2> INFO: Test took 32046ms.
[12:37:18.861] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:37:18.879] <TB2> INFO: dacScan step from 100 .. 119



[12:37:56.856] <TB2> INFO: Test took 37977ms.
[12:37:57.169] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:37:57.209] <TB2> INFO: dacScan step from 120 .. 139





[12:38:34.834] <TB2> INFO: Test took 37625ms.
[12:38:35.138] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:38:35.201] <TB2> INFO: dacScan step from 140 .. 159
[12:39:12.983] <TB2> INFO: Test took 37781ms.
[12:39:13.278] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:39:13.325] <TB2> INFO: dacScan step from 160 .. 160
[12:39:18.016] <TB2> INFO: Test took 4690ms.
[12:39:18.038] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:39:41.584] <TB2> INFO: PixTestTrim::trimBitTest() done
[12:39:41.585] <TB2> INFO: PixTestTrim::doTest() done, duration: 2854 seconds
[12:39:42.308] <TB2> INFO: ######################################################################
[12:39:42.308] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:39:42.308] <TB2> INFO: ######################################################################
[12:39:46.037] <TB2> INFO: Test took 3727ms.
[12:39:46.065] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:39:50.018] <TB2> INFO: Test took 3755ms.
[12:39:50.086] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:39:53.882] <TB2> INFO: Test took 3786ms.
[12:39:53.946] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:39:53.952] <TB2> INFO: The DUT currently contains the following objects:
[12:39:53.952] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:39:53.952] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:39:53.952] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:39:53.952] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:53.953] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:53.953] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.076] <TB2> INFO: Test took 1123ms.
[12:39:55.077] <TB2> INFO: The DUT currently contains the following objects:
[12:39:55.077] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:39:55.077] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:39:55.077] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:39:55.077] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:55.077] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.077] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.077] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.077] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.077] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.077] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.077] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.077] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.077] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.077] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.077] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.077] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.078] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.078] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.078] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:55.078] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.185] <TB2> INFO: Test took 1107ms.
[12:39:56.186] <TB2> INFO: The DUT currently contains the following objects:
[12:39:56.186] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:39:56.186] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:39:56.186] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:39:56.186] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:56.186] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.186] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.186] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.186] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.186] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.186] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.186] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.186] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.186] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.186] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.187] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.187] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.187] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.187] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.187] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:56.187] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.323] <TB2> INFO: Test took 1136ms.
[12:39:57.325] <TB2> INFO: The DUT currently contains the following objects:
[12:39:57.325] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:39:57.325] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:39:57.325] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:39:57.325] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:57.325] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:57.325] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.435] <TB2> INFO: Test took 1110ms.
[12:39:58.436] <TB2> INFO: The DUT currently contains the following objects:
[12:39:58.436] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:39:58.436] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:39:58.436] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:39:58.436] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:58.436] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.436] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.436] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.436] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.436] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.437] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.437] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.437] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.437] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.437] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.437] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.437] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.437] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.437] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.437] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:58.437] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.558] <TB2> INFO: Test took 1121ms.
[12:39:59.559] <TB2> INFO: The DUT currently contains the following objects:
[12:39:59.559] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:39:59.559] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:39:59.559] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:39:59.559] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:59.559] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.559] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.559] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.559] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.559] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.560] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.560] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.560] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.560] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.560] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.560] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.560] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.560] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.560] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.560] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:59.560] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.669] <TB2> INFO: Test took 1109ms.
[12:40:00.670] <TB2> INFO: The DUT currently contains the following objects:
[12:40:00.670] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:40:00.670] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:40:00.670] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:40:00.670] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:40:00.670] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.670] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.670] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.670] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.670] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.670] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.670] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.670] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.670] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.671] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.671] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.671] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.671] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.671] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.671] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:00.671] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.791] <TB2> INFO: Test took 1120ms.
[12:40:01.792] <TB2> INFO: The DUT currently contains the following objects:
[12:40:01.792] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:40:01.793] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:40:01.793] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:40:01.793] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:40:01.793] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:01.793] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.927] <TB2> INFO: Test took 1134ms.
[12:40:02.929] <TB2> INFO: The DUT currently contains the following objects:
[12:40:02.929] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:40:02.929] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:40:02.929] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:40:02.929] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:40:02.929] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:02.929] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.052] <TB2> INFO: Test took 1123ms.
[12:40:04.053] <TB2> INFO: The DUT currently contains the following objects:
[12:40:04.053] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:40:04.053] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:40:04.053] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:40:04.053] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:40:04.053] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.053] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.053] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.053] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.053] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.053] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.053] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.053] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.053] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.053] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.053] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.053] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.054] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.054] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.054] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:04.054] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.161] <TB2> INFO: Test took 1107ms.
[12:40:05.162] <TB2> INFO: The DUT currently contains the following objects:
[12:40:05.162] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:40:05.162] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:40:05.162] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:40:05.162] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:40:05.162] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.162] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.162] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.162] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.162] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.162] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.162] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.162] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.162] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.162] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.162] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.162] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.162] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.163] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.163] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:05.163] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.269] <TB2> INFO: Test took 1106ms.
[12:40:06.271] <TB2> INFO: The DUT currently contains the following objects:
[12:40:06.271] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:40:06.271] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:40:06.271] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:40:06.271] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:40:06.271] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:06.271] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.394] <TB2> INFO: Test took 1123ms.
[12:40:07.396] <TB2> INFO: The DUT currently contains the following objects:
[12:40:07.396] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:40:07.396] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:40:07.396] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:40:07.396] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:40:07.396] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:07.396] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.520] <TB2> INFO: Test took 1124ms.
[12:40:08.521] <TB2> INFO: The DUT currently contains the following objects:
[12:40:08.521] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:40:08.521] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:40:08.521] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:40:08.521] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:40:08.521] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.521] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.521] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.522] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.522] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.522] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.522] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.522] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.522] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.522] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.522] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.522] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.522] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.522] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.522] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:08.522] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.629] <TB2> INFO: Test took 1107ms.
[12:40:09.630] <TB2> INFO: The DUT currently contains the following objects:
[12:40:09.630] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:40:09.630] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:40:09.630] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:40:09.630] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:40:09.630] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.630] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.630] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.630] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.630] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.630] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.630] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.630] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.630] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.630] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.630] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.631] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.631] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.631] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.631] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:09.631] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.753] <TB2> INFO: Test took 1122ms.
[12:40:10.754] <TB2> INFO: The DUT currently contains the following objects:
[12:40:10.754] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:40:10.754] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:40:10.754] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:40:10.754] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:40:10.754] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.754] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.754] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.754] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.754] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.755] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.755] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.755] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.755] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.755] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.755] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.755] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.755] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.755] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.755] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:10.755] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:40:11.861] <TB2> INFO: Test took 1106ms.
[12:40:11.865] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:44:36.934] <TB2> INFO: Test took 265069ms.
[12:44:38.619] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:48:48.590] <TB2> INFO: Test took 249971ms.
[12:48:50.159] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.165] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.172] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.178] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.185] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.191] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.198] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.204] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.211] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.217] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.224] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.230] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.237] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.243] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.249] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.256] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:48:50.303] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C0.dat
[12:48:50.303] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C1.dat
[12:48:50.303] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C2.dat
[12:48:50.303] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C3.dat
[12:48:50.303] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C4.dat
[12:48:50.303] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C5.dat
[12:48:50.303] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C6.dat
[12:48:50.303] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C7.dat
[12:48:50.304] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C8.dat
[12:48:50.304] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C9.dat
[12:48:50.304] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C10.dat
[12:48:50.304] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C11.dat
[12:48:50.304] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C12.dat
[12:48:50.304] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C13.dat
[12:48:50.304] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C14.dat
[12:48:50.304] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//dacParameters35_C15.dat
[12:48:53.968] <TB2> INFO: Test took 3661ms.
[12:48:57.771] <TB2> INFO: Test took 3540ms.
[12:49:01.614] <TB2> INFO: Test took 3581ms.
[12:49:01.880] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:02.806] <TB2> INFO: Test took 926ms.
[12:49:02.808] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:03.909] <TB2> INFO: Test took 1101ms.
[12:49:03.911] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:05.013] <TB2> INFO: Test took 1102ms.
[12:49:05.015] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:06.115] <TB2> INFO: Test took 1100ms.
[12:49:06.117] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:07.247] <TB2> INFO: Test took 1130ms.
[12:49:07.249] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:08.365] <TB2> INFO: Test took 1116ms.
[12:49:08.370] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:09.500] <TB2> INFO: Test took 1130ms.
[12:49:09.502] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:10.605] <TB2> INFO: Test took 1103ms.
[12:49:10.607] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:11.723] <TB2> INFO: Test took 1116ms.
[12:49:11.725] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:12.854] <TB2> INFO: Test took 1129ms.
[12:49:12.857] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:13.973] <TB2> INFO: Test took 1116ms.
[12:49:13.975] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:15.077] <TB2> INFO: Test took 1102ms.
[12:49:15.080] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:16.196] <TB2> INFO: Test took 1116ms.
[12:49:16.198] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:17.314] <TB2> INFO: Test took 1116ms.
[12:49:17.316] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:18.433] <TB2> INFO: Test took 1117ms.
[12:49:18.435] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:19.552] <TB2> INFO: Test took 1117ms.
[12:49:19.554] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:20.670] <TB2> INFO: Test took 1116ms.
[12:49:20.673] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:21.774] <TB2> INFO: Test took 1102ms.
[12:49:21.776] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:22.878] <TB2> INFO: Test took 1102ms.
[12:49:22.880] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:23.996] <TB2> INFO: Test took 1116ms.
[12:49:23.998] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:25.114] <TB2> INFO: Test took 1116ms.
[12:49:25.116] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:26.233] <TB2> INFO: Test took 1117ms.
[12:49:26.235] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:27.336] <TB2> INFO: Test took 1101ms.
[12:49:27.338] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:28.469] <TB2> INFO: Test took 1131ms.
[12:49:28.471] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:29.616] <TB2> INFO: Test took 1145ms.
[12:49:29.619] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:30.749] <TB2> INFO: Test took 1131ms.
[12:49:30.751] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:31.882] <TB2> INFO: Test took 1131ms.
[12:49:31.884] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:33.013] <TB2> INFO: Test took 1129ms.
[12:49:33.015] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:34.116] <TB2> INFO: Test took 1101ms.
[12:49:34.118] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:35.220] <TB2> INFO: Test took 1102ms.
[12:49:35.222] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:36.323] <TB2> INFO: Test took 1102ms.
[12:49:36.325] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:37.426] <TB2> INFO: Test took 1101ms.
[12:49:37.929] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 595 seconds
[12:49:37.929] <TB2> INFO: PH scale (per ROC): 90 94 95 89 78 88 85 91 83 98 80 92 98 74 95 92
[12:49:37.929] <TB2> INFO: PH offset (per ROC): 163 157 159 148 167 163 158 146 157 127 151 164 129 155 137 134
[12:49:38.096] <TB2> INFO: ######################################################################
[12:49:38.096] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[12:49:38.096] <TB2> INFO: ######################################################################
[12:49:38.105] <TB2> INFO: scanning low vcal = 10
[12:49:42.005] <TB2> INFO: Test took 3900ms.
[12:49:42.008] <TB2> INFO: scanning low vcal = 20
[12:49:45.903] <TB2> INFO: Test took 3895ms.
[12:49:45.907] <TB2> INFO: scanning low vcal = 30
[12:49:49.778] <TB2> INFO: Test took 3871ms.
[12:49:49.784] <TB2> INFO: scanning low vcal = 40
[12:49:54.341] <TB2> INFO: Test took 4557ms.
[12:49:54.395] <TB2> INFO: scanning low vcal = 50
[12:49:58.879] <TB2> INFO: Test took 4484ms.
[12:49:58.932] <TB2> INFO: scanning low vcal = 60
[12:50:03.473] <TB2> INFO: Test took 4541ms.
[12:50:03.526] <TB2> INFO: scanning low vcal = 70
[12:50:08.015] <TB2> INFO: Test took 4489ms.
[12:50:08.069] <TB2> INFO: scanning low vcal = 80
[12:50:12.618] <TB2> INFO: Test took 4549ms.
[12:50:12.671] <TB2> INFO: scanning low vcal = 90
[12:50:17.247] <TB2> INFO: Test took 4576ms.
[12:50:17.301] <TB2> INFO: scanning low vcal = 100
[12:50:21.792] <TB2> INFO: Test took 4491ms.
[12:50:21.846] <TB2> INFO: scanning low vcal = 110
[12:50:26.296] <TB2> INFO: Test took 4450ms.
[12:50:26.349] <TB2> INFO: scanning low vcal = 120
[12:50:30.862] <TB2> INFO: Test took 4513ms.
[12:50:30.916] <TB2> INFO: scanning low vcal = 130
[12:50:35.404] <TB2> INFO: Test took 4488ms.
[12:50:35.458] <TB2> INFO: scanning low vcal = 140
[12:50:39.874] <TB2> INFO: Test took 4416ms.
[12:50:39.928] <TB2> INFO: scanning low vcal = 150
[12:50:44.384] <TB2> INFO: Test took 4456ms.
[12:50:44.437] <TB2> INFO: scanning low vcal = 160
[12:50:49.007] <TB2> INFO: Test took 4570ms.
[12:50:49.059] <TB2> INFO: scanning low vcal = 170
[12:50:53.735] <TB2> INFO: Test took 4676ms.
[12:50:53.788] <TB2> INFO: scanning low vcal = 180
[12:50:58.152] <TB2> INFO: Test took 4364ms.
[12:50:58.204] <TB2> INFO: scanning low vcal = 190
[12:51:02.741] <TB2> INFO: Test took 4537ms.
[12:51:02.793] <TB2> INFO: scanning low vcal = 200
[12:51:07.253] <TB2> INFO: Test took 4460ms.
[12:51:07.306] <TB2> INFO: scanning low vcal = 210
[12:51:11.737] <TB2> INFO: Test took 4430ms.
[12:51:11.791] <TB2> INFO: scanning low vcal = 220
[12:51:16.178] <TB2> INFO: Test took 4387ms.
[12:51:16.231] <TB2> INFO: scanning low vcal = 230
[12:51:20.671] <TB2> INFO: Test took 4440ms.
[12:51:20.724] <TB2> INFO: scanning low vcal = 240
[12:51:25.256] <TB2> INFO: Test took 4532ms.
[12:51:25.309] <TB2> INFO: scanning low vcal = 250
[12:51:29.834] <TB2> INFO: Test took 4525ms.
[12:51:29.889] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[12:51:34.295] <TB2> INFO: Test took 4406ms.
[12:51:34.347] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[12:51:38.678] <TB2> INFO: Test took 4331ms.
[12:51:38.731] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[12:51:43.213] <TB2> INFO: Test took 4482ms.
[12:51:43.266] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[12:51:47.741] <TB2> INFO: Test took 4475ms.
[12:51:47.794] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:51:52.198] <TB2> INFO: Test took 4404ms.
[12:51:52.648] <TB2> INFO: PixTestGainPedestal::measure() done
[12:52:22.480] <TB2> INFO: PixTestGainPedestal::fit() done
[12:52:22.480] <TB2> INFO: non-linearity mean: 0.950 0.959 0.952 0.950 0.956 0.953 0.946 0.958 0.957 0.955 0.948 0.952 0.950 0.955 0.957 0.956
[12:52:22.480] <TB2> INFO: non-linearity RMS: 0.006 0.005 0.006 0.008 0.006 0.006 0.006 0.006 0.005 0.005 0.007 0.007 0.007 0.005 0.006 0.006
[12:52:22.480] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C0.dat
[12:52:22.498] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C1.dat
[12:52:22.515] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C2.dat
[12:52:22.533] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C3.dat
[12:52:22.550] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C4.dat
[12:52:22.567] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C5.dat
[12:52:22.585] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C6.dat
[12:52:22.602] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C7.dat
[12:52:22.619] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C8.dat
[12:52:22.637] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C9.dat
[12:52:22.654] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C10.dat
[12:52:22.671] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C11.dat
[12:52:22.689] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C12.dat
[12:52:22.707] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C13.dat
[12:52:22.724] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C14.dat
[12:52:22.741] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//002_FulltestPxar_m20//phCalibrationFitErr35_C15.dat
[12:52:22.759] <TB2> INFO: PixTestGainPedestal::doTest() done, duration: 164 seconds
[12:52:22.765] <TB2> INFO: enter test to run
[12:52:22.765] <TB2> INFO: test: exit no parameter change
[12:52:23.206] <TB2> QUIET: Connection to board 156 closed.
[12:52:23.285] <TB2> INFO: pXar: this is the end, my friend