[18:02:34.054] <TB1> INFO: *** Welcome to pxar ***
[18:02:34.054] <TB1> INFO: *** Today: 2015/10/30
[18:02:34.075] <TB1> INFO: *** Version: 9da6-dirty
[18:02:34.075] <TB1> INFO: readRocDacs: /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C0.dat .. /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C15.dat
[18:02:34.078] <TB1> INFO: readTbmDacs: /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//tbmParameters_C0a.dat .. /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//tbmParameters_C0b.dat
[18:02:34.078] <TB1> INFO: readMaskFile: /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//defaultMaskFile.dat
[18:02:34.078] <TB1> INFO: readTrimFile: /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters_C0.dat .. /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters_C15.dat
[18:02:34.245] <TB1> INFO: clk: 4
[18:02:34.245] <TB1> INFO: ctr: 4
[18:02:34.245] <TB1> INFO: sda: 19
[18:02:34.245] <TB1> INFO: tin: 9
[18:02:34.245] <TB1> INFO: level: 15
[18:02:34.245] <TB1> INFO: triggerdelay: 0
[18:02:34.245] <TB1> QUIET: Instanciating API for pxar prod-11
[18:02:34.245] <TB1> INFO: Log level: INFO
[18:02:34.258] <TB1> INFO: Found DTB DTB_WWVH60
[18:02:34.270] <TB1> QUIET: Connection to board DTB_WWVH60 opened.
[18:02:34.274] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 129
HW version: DTB1.2
FW version: 4.2
SW version: 4.4
USB id: DTB_WWVH60
MAC address: 40D855118081
Hostname: pixelDTB129
Comment:
------------------------------------------------------
[18:02:34.277] <TB1> INFO: RPC call hashes of host and DTB match: 397073690
[18:02:35.921] <TB1> INFO: DUT info:
[18:02:35.921] <TB1> INFO: The DUT currently contains the following objects:
[18:02:35.921] <TB1> INFO: 2 TBM Cores tbm08c (2 ON)
[18:02:35.921] <TB1> INFO: TBM Core alpha (0): 7 registers set
[18:02:35.921] <TB1> INFO: TBM Core beta (1): 7 registers set
[18:02:35.921] <TB1> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[18:02:35.921] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.921] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.921] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.921] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.921] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.921] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.922] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.922] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.922] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.922] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.922] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.922] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.922] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.922] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.922] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:35.922] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[18:02:36.328] <TB1> INFO: enter 'restricted' command line mode
[18:02:36.328] <TB1> INFO: enter test to run
[18:02:36.328] <TB1> INFO: test: FullTest no parameter change
[18:02:36.328] <TB1> INFO: running: fulltest
[18:02:36.337] <TB1> INFO: ######################################################################
[18:02:36.337] <TB1> INFO: PixTestFullTest::doTest()
[18:02:36.337] <TB1> INFO: ######################################################################
[18:02:36.342] <TB1> INFO: ######################################################################
[18:02:36.342] <TB1> INFO: PixTestPretest::doTest()
[18:02:36.342] <TB1> INFO: ######################################################################
[18:02:36.344] <TB1> INFO: ----------------------------------------------------------------------
[18:02:36.344] <TB1> INFO: PixTestPretest::programROC()
[18:02:36.344] <TB1> INFO: ----------------------------------------------------------------------
[18:02:54.362] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[18:02:54.362] <TB1> INFO: IA differences per ROC: 16.9 18.5 16.9 16.9 19.3 16.1 17.7 16.9 17.7 17.7 18.5 19.3 16.9 18.5 21.7 17.7
[18:02:54.442] <TB1> INFO: ----------------------------------------------------------------------
[18:02:54.442] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[18:02:54.442] <TB1> INFO: ----------------------------------------------------------------------
[18:03:14.024] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 393.1 mA = 24.5688 mA/ROC
[18:03:14.027] <TB1> INFO: ----------------------------------------------------------------------
[18:03:14.027] <TB1> INFO: PixTestPretest::findTiming()
[18:03:14.027] <TB1> INFO: ----------------------------------------------------------------------
[18:03:14.027] <TB1> INFO: PixTestCmd::init()
[18:03:14.663] <TB1> WARNING: Not unmasking DUT, not setting Calibrate bits!
[18:04:47.353] <TB1> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):4, header/trailer: 1, token: 1
[18:04:47.353] <TB1> INFO: (success/tries = 100/100), width = 3
[18:04:47.359] <TB1> INFO: ----------------------------------------------------------------------
[18:04:47.360] <TB1> INFO: PixTestPretest::findWorkingPixel()
[18:04:47.360] <TB1> INFO: ----------------------------------------------------------------------
[18:04:47.509] <TB1> INFO: Expecting 231680 events.
[18:04:52.698] <TB1> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (1) != Token Chain Length (8)
[18:04:52.702] <TB1> ERROR: <datapipe.cc/CheckEventID:L457> Channel 0 Event ID mismatch: local ID (21) != TBM ID (2)
[18:04:55.623] <TB1> INFO: 231680 events read in total (7335ms).
[18:04:55.633] <TB1> INFO: Test took 8264ms.
[18:04:56.080] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[18:04:56.116] <TB1> INFO: ----------------------------------------------------------------------
[18:04:56.116] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[18:04:56.116] <TB1> INFO: ----------------------------------------------------------------------
[18:04:56.260] <TB1> INFO: Expecting 231680 events.
[18:05:04.351] <TB1> INFO: 231680 events read in total (7312ms).
[18:05:04.360] <TB1> INFO: Test took 8237ms.
[18:05:04.821] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[18:05:04.821] <TB1> INFO: CalDel: 124 139 112 133 116 120 138 144 128 121 121 112 124 112 107 133
[18:05:04.822] <TB1> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[18:05:04.827] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C0.dat
[18:05:04.827] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C1.dat
[18:05:04.828] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C2.dat
[18:05:04.828] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C3.dat
[18:05:04.829] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C4.dat
[18:05:04.829] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C5.dat
[18:05:04.829] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C6.dat
[18:05:04.829] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C7.dat
[18:05:04.829] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C8.dat
[18:05:04.830] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C9.dat
[18:05:04.830] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C10.dat
[18:05:04.831] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C11.dat
[18:05:04.831] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C12.dat
[18:05:04.831] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C13.dat
[18:05:04.832] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C14.dat
[18:05:04.832] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters_C15.dat
[18:05:04.832] <TB1> INFO: write tbm parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//tbmParameters_C0a.dat
[18:05:04.832] <TB1> INFO: write tbm parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//tbmParameters_C0b.dat
[18:05:04.833] <TB1> INFO: PixTestPretest::doTest() done, duration: 148 seconds
[18:05:04.833] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:05:04.833] <TB1> INFO: Decoding statistics:
[18:05:04.833] <TB1> INFO: General information:
[18:05:04.833] <TB1> INFO: 16bit words read: 7034754
[18:05:04.833] <TB1> INFO: valid events total: 463360
[18:05:04.833] <TB1> INFO: empty events: 306210
[18:05:04.833] <TB1> INFO: valid events with pixels: 157150
[18:05:04.833] <TB1> INFO: valid pixel hits: 737217
[18:05:04.833] <TB1> INFO: Event errors: 0
[18:05:04.833] <TB1> INFO: start marker: 0
[18:05:04.833] <TB1> INFO: stop marker: 0
[18:05:04.833] <TB1> INFO: overflow: 0
[18:05:04.833] <TB1> INFO: invalid 5bit words: 0
[18:05:04.833] <TB1> INFO: invalid XOR eye diagram: 0
[18:05:04.833] <TB1> INFO: TBM errors: 0
[18:05:04.833] <TB1> INFO: flawed TBM headers: 0
[18:05:04.833] <TB1> INFO: flawed TBM trailers: 0
[18:05:04.833] <TB1> INFO: event ID mismatches: 0
[18:05:04.833] <TB1> INFO: ROC errors: 0
[18:05:04.833] <TB1> INFO: missing ROC header(s): 0
[18:05:04.833] <TB1> INFO: misplaced readback start: 0
[18:05:04.833] <TB1> INFO: Pixel decoding errors: 0
[18:05:04.833] <TB1> INFO: pixel data incomplete: 0
[18:05:04.833] <TB1> INFO: pixel address: 0
[18:05:04.833] <TB1> INFO: pulse height fill bit: 0
[18:05:04.833] <TB1> INFO: buffer corruption: 0
[18:05:04.936] <TB1> INFO: ######################################################################
[18:05:04.936] <TB1> INFO: PixTestAlive::doTest()
[18:05:04.936] <TB1> INFO: ######################################################################
[18:05:04.939] <TB1> INFO: ----------------------------------------------------------------------
[18:05:04.939] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[18:05:04.939] <TB1> INFO: ----------------------------------------------------------------------
[18:05:05.328] <TB1> INFO: Expecting 41600 events.
[18:05:09.965] <TB1> INFO: 41600 events read in total (3859ms).
[18:05:09.967] <TB1> INFO: Test took 5025ms.
[18:05:09.980] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:05:10.407] <TB1> INFO: PixTestAlive::aliveTest() done
[18:05:10.407] <TB1> INFO: number of dead pixels (per ROC): 1 89 58 3 1 10 39 3 11 44 34 0 0 17 6 0
[18:05:10.410] <TB1> INFO: ----------------------------------------------------------------------
[18:05:10.410] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[18:05:10.410] <TB1> INFO: ----------------------------------------------------------------------
[18:05:10.800] <TB1> INFO: Expecting 41600 events.
[18:05:14.011] <TB1> INFO: 41600 events read in total (2432ms).
[18:05:14.012] <TB1> INFO: Test took 3598ms.
[18:05:14.012] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:05:14.013] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[18:05:14.480] <TB1> INFO: PixTestAlive::maskTest() done
[18:05:14.480] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[18:05:14.482] <TB1> INFO: ----------------------------------------------------------------------
[18:05:14.482] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[18:05:14.482] <TB1> INFO: ----------------------------------------------------------------------
[18:05:14.848] <TB1> INFO: Expecting 41600 events.
[18:05:19.555] <TB1> INFO: 41600 events read in total (3928ms).
[18:05:19.560] <TB1> INFO: Test took 5073ms.
[18:05:19.574] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:05:19.999] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[18:05:19.999] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[18:05:19.999] <TB1> INFO: PixTestAlive::doTest() done, duration: 15 seconds
[18:05:19.000] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:05:19.000] <TB1> INFO: Decoding statistics:
[18:05:19.000] <TB1> INFO: General information:
[18:05:19.000] <TB1> INFO: 16bit words read: 0
[18:05:19.000] <TB1> INFO: valid events total: 0
[18:05:19.000] <TB1> INFO: empty events: 0
[18:05:19.000] <TB1> INFO: valid events with pixels: 0
[18:05:19.000] <TB1> INFO: valid pixel hits: 0
[18:05:19.000] <TB1> INFO: Event errors: 0
[18:05:19.000] <TB1> INFO: start marker: 0
[18:05:19.000] <TB1> INFO: stop marker: 0
[18:05:19.000] <TB1> INFO: overflow: 0
[18:05:19.002] <TB1> INFO: invalid 5bit words: 0
[18:05:20.006] <TB1> INFO: invalid XOR eye diagram: 0
[18:05:20.006] <TB1> INFO: TBM errors: 0
[18:05:20.006] <TB1> INFO: flawed TBM headers: 0
[18:05:20.006] <TB1> INFO: flawed TBM trailers: 0
[18:05:20.006] <TB1> INFO: event ID mismatches: 0
[18:05:20.006] <TB1> INFO: ROC errors: 0
[18:05:20.006] <TB1> INFO: missing ROC header(s): 0
[18:05:20.006] <TB1> INFO: misplaced readback start: 0
[18:05:20.006] <TB1> INFO: Pixel decoding errors: 0
[18:05:20.006] <TB1> INFO: pixel data incomplete: 0
[18:05:20.006] <TB1> INFO: pixel address: 0
[18:05:20.006] <TB1> INFO: pulse height fill bit: 0
[18:05:20.006] <TB1> INFO: buffer corruption: 0
[18:05:20.016] <TB1> INFO: ######################################################################
[18:05:20.016] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[18:05:20.016] <TB1> INFO: ######################################################################
[18:05:20.020] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[18:05:20.059] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[18:05:20.059] <TB1> INFO: run 1 of 1
[18:05:20.478] <TB1> INFO: Expecting 3120000 events.
[18:06:12.063] <TB1> INFO: 1232065 events read in total (50806ms).
[18:07:03.494] <TB1> INFO: 2455760 events read in total (102237ms).
[18:07:34.105] <TB1> INFO: 3120000 events read in total (132848ms).
[18:07:34.210] <TB1> INFO: Test took 134152ms.
[18:07:34.354] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:08:38.349] <TB1> INFO: PixTestBBMap::doTest() done, duration: 198 seconds
[18:08:38.349] <TB1> INFO: number of dead bumps (per ROC): 0 3 1 0 0 0 4 0 1 2 2 0 0 0 0 0
[18:08:38.349] <TB1> INFO: separation cut (per ROC): 119 150 134 123 130 133 129 121 130 133 130 132 117 142 141 126
[18:08:38.349] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:08:38.349] <TB1> INFO: Decoding statistics:
[18:08:38.349] <TB1> INFO: General information:
[18:08:38.349] <TB1> INFO: 16bit words read: 0
[18:08:38.349] <TB1> INFO: valid events total: 0
[18:08:38.349] <TB1> INFO: empty events: 0
[18:08:38.349] <TB1> INFO: valid events with pixels: 0
[18:08:38.349] <TB1> INFO: valid pixel hits: 0
[18:08:38.349] <TB1> INFO: Event errors: 0
[18:08:38.349] <TB1> INFO: start marker: 0
[18:08:38.349] <TB1> INFO: stop marker: 0
[18:08:38.349] <TB1> INFO: overflow: 0
[18:08:38.349] <TB1> INFO: invalid 5bit words: 0
[18:08:38.349] <TB1> INFO: invalid XOR eye diagram: 0
[18:08:38.349] <TB1> INFO: TBM errors: 0
[18:08:38.349] <TB1> INFO: flawed TBM headers: 0
[18:08:38.349] <TB1> INFO: flawed TBM trailers: 0
[18:08:38.350] <TB1> INFO: event ID mismatches: 0
[18:08:38.351] <TB1> INFO: ROC errors: 0
[18:08:38.351] <TB1> INFO: missing ROC header(s): 0
[18:08:38.351] <TB1> INFO: misplaced readback start: 0
[18:08:38.351] <TB1> INFO: Pixel decoding errors: 0
[18:08:38.351] <TB1> INFO: pixel data incomplete: 0
[18:08:38.351] <TB1> INFO: pixel address: 0
[18:08:38.351] <TB1> INFO: pulse height fill bit: 0
[18:08:38.351] <TB1> INFO: buffer corruption: 0
[18:08:38.476] <TB1> INFO: ######################################################################
[18:08:38.476] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[18:08:38.476] <TB1> INFO: ######################################################################
[18:08:38.476] <TB1> INFO: ----------------------------------------------------------------------
[18:08:38.477] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[18:08:38.477] <TB1> INFO: ----------------------------------------------------------------------
[18:08:38.477] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 150 (-1/-1) hits flags = 528 (plus default)
[18:08:38.505] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[18:08:38.505] <TB1> INFO: run 1 of 1
[18:08:38.949] <TB1> INFO: Expecting 26208000 events.
[18:09:18.539] <TB1> INFO: 1236350 events read in total (38810ms).
[18:09:59.822] <TB1> INFO: 2446000 events read in total (80093ms).
[18:10:38.360] <TB1> INFO: 3659650 events read in total (118631ms).
[18:11:16.586] <TB1> INFO: 4862800 events read in total (156857ms).
[18:11:54.863] <TB1> INFO: 6068500 events read in total (195134ms).
[18:12:33.274] <TB1> INFO: 7266900 events read in total (233545ms).
[18:13:11.842] <TB1> INFO: 8460500 events read in total (272113ms).
[18:13:50.265] <TB1> INFO: 9660000 events read in total (310536ms).
[18:14:29.114] <TB1> INFO: 10848700 events read in total (349385ms).
[18:15:11.430] <TB1> INFO: 12039150 events read in total (391701ms).
[18:15:51.450] <TB1> INFO: 13222400 events read in total (431721ms).
[18:16:29.614] <TB1> INFO: 14386850 events read in total (469885ms).
[18:17:07.939] <TB1> INFO: 15552700 events read in total (508210ms).
[18:17:46.085] <TB1> INFO: 16715300 events read in total (546356ms).
[18:18:24.748] <TB1> INFO: 17875050 events read in total (585019ms).
[18:19:03.271] <TB1> INFO: 19035950 events read in total (623542ms).
[18:19:41.662] <TB1> INFO: 20197850 events read in total (661933ms).
[18:20:20.151] <TB1> INFO: 21355850 events read in total (700422ms).
[18:20:58.358] <TB1> INFO: 22513850 events read in total (738629ms).
[18:21:36.865] <TB1> INFO: 23677050 events read in total (777136ms).
[18:22:18.478] <TB1> INFO: 24842800 events read in total (818749ms).
[18:22:59.555] <TB1> INFO: 26023900 events read in total (859826ms).
[18:23:06.660] <TB1> INFO: 26208000 events read in total (866931ms).
[18:23:06.772] <TB1> INFO: Test took 868267ms.
[18:23:06.915] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:23:07.373] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:23:11.888] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:23:15.363] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:23:18.521] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:23:23.222] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:23:27.095] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:23:32.258] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:23:36.927] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:23:41.300] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:23:45.992] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:23:50.573] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:23:55.647] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:23:59.644] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:24:02.988] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:24:05.620] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:24:08.886] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:24:11.648] <TB1> INFO: PixTestScurves::scurves() done
[18:24:11.648] <TB1> INFO: Vcal mean: 95.59 103.52 105.27 97.66 102.03 109.40 100.71 103.03 109.89 101.58 103.39 104.71 88.76 107.37 106.31 111.67
[18:24:11.648] <TB1> INFO: Vcal RMS: 4.97 17.19 13.57 5.44 5.37 7.17 10.96 6.36 7.55 11.55 11.21 5.75 5.13 8.24 6.33 4.50
[18:24:11.661] <TB1> INFO: PixTestScurves::fullTest() done, duration: 933 seconds
[18:24:11.662] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:24:11.662] <TB1> INFO: Decoding statistics:
[18:24:11.662] <TB1> INFO: General information:
[18:24:11.663] <TB1> INFO: 16bit words read: 0
[18:24:11.663] <TB1> INFO: valid events total: 0
[18:24:11.664] <TB1> INFO: empty events: 0
[18:24:11.664] <TB1> INFO: valid events with pixels: 0
[18:24:11.664] <TB1> INFO: valid pixel hits: 0
[18:24:11.664] <TB1> INFO: Event errors: 0
[18:24:11.664] <TB1> INFO: start marker: 0
[18:24:11.664] <TB1> INFO: stop marker: 0
[18:24:11.664] <TB1> INFO: overflow: 0
[18:24:11.664] <TB1> INFO: invalid 5bit words: 0
[18:24:11.664] <TB1> INFO: invalid XOR eye diagram: 0
[18:24:11.664] <TB1> INFO: TBM errors: 0
[18:24:11.664] <TB1> INFO: flawed TBM headers: 0
[18:24:11.664] <TB1> INFO: flawed TBM trailers: 0
[18:24:11.664] <TB1> INFO: event ID mismatches: 0
[18:24:11.664] <TB1> INFO: ROC errors: 0
[18:24:11.665] <TB1> INFO: missing ROC header(s): 0
[18:24:11.665] <TB1> INFO: misplaced readback start: 0
[18:24:11.665] <TB1> INFO: Pixel decoding errors: 0
[18:24:11.666] <TB1> INFO: pixel data incomplete: 0
[18:24:11.666] <TB1> INFO: pixel address: 0
[18:24:11.666] <TB1> INFO: pulse height fill bit: 0
[18:24:11.666] <TB1> INFO: buffer corruption: 0
[18:24:11.794] <TB1> INFO: ######################################################################
[18:24:11.794] <TB1> INFO: PixTestTrim::doTest()
[18:24:11.794] <TB1> INFO: ######################################################################
[18:24:11.800] <TB1> INFO: ----------------------------------------------------------------------
[18:24:11.801] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[18:24:11.801] <TB1> INFO: ----------------------------------------------------------------------
[18:24:11.892] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[18:24:11.892] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[18:24:11.924] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:24:11.924] <TB1> INFO: run 1 of 1
[18:24:12.299] <TB1> INFO: Expecting 5025280 events.
[18:25:02.861] <TB1> INFO: 1427824 events read in total (49781ms).
[18:25:52.129] <TB1> INFO: 2839864 events read in total (99050ms).
[18:26:43.142] <TB1> INFO: 4258696 events read in total (150063ms).
[18:27:18.064] <TB1> INFO: 5025280 events read in total (184984ms).
[18:27:18.147] <TB1> INFO: Test took 186223ms.
[18:27:18.291] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:28:26.454] <TB1> INFO: ROC 0 VthrComp = 96
[18:28:26.455] <TB1> INFO: ROC 1 VthrComp = 96
[18:28:26.455] <TB1> INFO: ROC 2 VthrComp = 104
[18:28:26.455] <TB1> INFO: ROC 3 VthrComp = 100
[18:28:26.456] <TB1> INFO: ROC 4 VthrComp = 105
[18:28:26.457] <TB1> INFO: ROC 5 VthrComp = 106
[18:28:26.458] <TB1> INFO: ROC 6 VthrComp = 98
[18:28:26.460] <TB1> INFO: ROC 7 VthrComp = 99
[18:28:26.461] <TB1> INFO: ROC 8 VthrComp = 103
[18:28:26.462] <TB1> INFO: ROC 9 VthrComp = 102
[18:28:26.462] <TB1> INFO: ROC 10 VthrComp = 100
[18:28:26.464] <TB1> INFO: ROC 11 VthrComp = 104
[18:28:26.465] <TB1> INFO: ROC 12 VthrComp = 92
[18:28:26.466] <TB1> INFO: ROC 13 VthrComp = 110
[18:28:26.469] <TB1> INFO: ROC 14 VthrComp = 108
[18:28:26.470] <TB1> INFO: ROC 15 VthrComp = 105
[18:28:26.475] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[18:28:26.476] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[18:28:26.498] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:28:26.498] <TB1> INFO: run 1 of 1
[18:28:26.902] <TB1> INFO: Expecting 5025280 events.
[18:29:09.440] <TB1> INFO: 899672 events read in total (41756ms).
[18:29:51.161] <TB1> INFO: 1796040 events read in total (83477ms).
[18:30:32.210] <TB1> INFO: 2689984 events read in total (124526ms).
[18:31:13.181] <TB1> INFO: 3574736 events read in total (165497ms).
[18:31:58.591] <TB1> INFO: 4457864 events read in total (210907ms).
[18:32:30.502] <TB1> INFO: 5025280 events read in total (242818ms).
[18:32:30.643] <TB1> INFO: Test took 244145ms.
[18:32:30.955] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:33:23.217] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 57.0068 for pixel 47/1 mean/min/max = 44.8205/32.593/57.048
[18:33:23.219] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 73.6118 for pixel 1/75 mean/min/max = 53.7545/33.8916/73.6175
[18:33:23.220] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 62.8917 for pixel 14/63 mean/min/max = 49.3523/35.6821/63.0226
[18:33:23.220] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 55.9011 for pixel 0/14 mean/min/max = 44.6419/32.8677/56.4161
[18:33:23.221] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 59.2299 for pixel 0/52 mean/min/max = 46.9693/34.6758/59.2628
[18:33:23.222] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 61.6151 for pixel 5/17 mean/min/max = 48.3614/34.9839/61.7388
[18:33:23.223] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 60.6156 for pixel 13/3 mean/min/max = 47.8208/35.0128/60.6288
[18:33:23.224] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 61.4657 for pixel 2/19 mean/min/max = 47.2478/32.6471/61.8485
[18:33:23.224] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 61.3801 for pixel 34/18 mean/min/max = 48.3768/35.295/61.4586
[18:33:23.225] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 58.5585 for pixel 0/69 mean/min/max = 47.3241/35.8295/58.8188
[18:33:23.226] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 65.0793 for pixel 10/12 mean/min/max = 48.7854/32.4836/65.0871
[18:33:23.226] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 61.8365 for pixel 0/45 mean/min/max = 47.55/33.2129/61.887
[18:33:23.227] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 57.0753 for pixel 9/75 mean/min/max = 45.4203/33.7535/57.087
[18:33:23.228] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 59.7604 for pixel 0/10 mean/min/max = 47.8571/35.8435/59.8707
[18:33:23.229] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 59.4722 for pixel 51/29 mean/min/max = 47.5184/35.5278/59.5091
[18:33:23.231] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 62.5082 for pixel 6/27 mean/min/max = 48.8957/35.2557/62.5357
[18:33:23.231] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:33:23.368] <TB1> INFO: Expecting 411648 events.
[18:33:32.450] <TB1> INFO: 411648 events read in total (8302ms).
[18:33:32.465] <TB1> INFO: Expecting 411648 events.
[18:33:41.102] <TB1> INFO: 411648 events read in total (8014ms).
[18:33:41.121] <TB1> INFO: Expecting 411648 events.
[18:33:49.718] <TB1> INFO: 411648 events read in total (7973ms).
[18:33:49.739] <TB1> INFO: Expecting 411648 events.
[18:33:58.322] <TB1> INFO: 411648 events read in total (7946ms).
[18:33:58.347] <TB1> INFO: Expecting 411648 events.
[18:34:06.979] <TB1> INFO: 411648 events read in total (7996ms).
[18:34:07.010] <TB1> INFO: Expecting 411648 events.
[18:34:15.597] <TB1> INFO: 411648 events read in total (7963ms).
[18:34:15.637] <TB1> INFO: Expecting 411648 events.
[18:34:24.235] <TB1> INFO: 411648 events read in total (7981ms).
[18:34:24.273] <TB1> INFO: Expecting 411648 events.
[18:34:32.847] <TB1> INFO: 411648 events read in total (7948ms).
[18:34:32.887] <TB1> INFO: Expecting 411648 events.
[18:34:41.468] <TB1> INFO: 411648 events read in total (7959ms).
[18:34:41.511] <TB1> INFO: Expecting 411648 events.
[18:34:50.153] <TB1> INFO: 411648 events read in total (8022ms).
[18:34:50.202] <TB1> INFO: Expecting 411648 events.
[18:34:58.890] <TB1> INFO: 411648 events read in total (8082ms).
[18:34:58.953] <TB1> INFO: Expecting 411648 events.
[18:35:07.509] <TB1> INFO: 411648 events read in total (7962ms).
[18:35:07.563] <TB1> INFO: Expecting 411648 events.
[18:35:16.315] <TB1> INFO: 411648 events read in total (8157ms).
[18:35:16.385] <TB1> INFO: Expecting 411648 events.
[18:35:25.419] <TB1> INFO: 411648 events read in total (8448ms).
[18:35:25.493] <TB1> INFO: Expecting 411648 events.
[18:35:34.619] <TB1> INFO: 411648 events read in total (8552ms).
[18:35:34.691] <TB1> INFO: Expecting 411648 events.
[18:35:43.267] <TB1> INFO: 411648 events read in total (8009ms).
[18:35:43.332] <TB1> INFO: Test took 140101ms.
[18:35:44.847] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[18:35:44.874] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:35:44.874] <TB1> INFO: run 1 of 1
[18:35:45.291] <TB1> INFO: Expecting 5025280 events.
[18:36:25.630] <TB1> INFO: 878712 events read in total (39560ms).
[18:37:05.207] <TB1> INFO: 1754632 events read in total (79137ms).
[18:37:45.041] <TB1> INFO: 2628544 events read in total (118972ms).
[18:38:24.483] <TB1> INFO: 3491800 events read in total (158413ms).
[18:39:10.053] <TB1> INFO: 4352872 events read in total (203983ms).
[18:39:45.592] <TB1> INFO: 5025280 events read in total (239522ms).
[18:39:45.730] <TB1> INFO: Test took 240856ms.
[18:39:46.030] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:40:34.937] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 0.084751 .. 255.000000
[18:40:35.019] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[18:40:35.045] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:40:35.045] <TB1> INFO: run 1 of 1
[18:40:35.413] <TB1> INFO: Expecting 8519680 events.
[18:41:14.280] <TB1> INFO: 829264 events read in total (38088ms).
[18:41:52.812] <TB1> INFO: 1657792 events read in total (76620ms).
[18:42:30.843] <TB1> INFO: 2486224 events read in total (114652ms).
[18:43:09.144] <TB1> INFO: 3313656 events read in total (152952ms).
[18:43:47.756] <TB1> INFO: 4142296 events read in total (191564ms).
[18:44:25.413] <TB1> INFO: 4970112 events read in total (229221ms).
[18:45:03.102] <TB1> INFO: 5798736 events read in total (266910ms).
[18:45:41.083] <TB1> INFO: 6627600 events read in total (304891ms).
[18:46:20.804] <TB1> INFO: 7456488 events read in total (344612ms).
[18:47:06.981] <TB1> INFO: 8285912 events read in total (390789ms).
[18:47:21.172] <TB1> INFO: 8519680 events read in total (404980ms).
[18:47:21.599] <TB1> INFO: Test took 406554ms.
[18:47:22.407] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:48:25.907] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 0.947649 .. 183.731032
[18:48:25.993] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 0 .. 193 (-1/-1) hits flags = 528 (plus default)
[18:48:26.022] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:48:26.022] <TB1> INFO: run 1 of 1
[18:48:26.433] <TB1> INFO: Expecting 6456320 events.
[18:49:05.052] <TB1> INFO: 852008 events read in total (37832ms).
[18:49:43.200] <TB1> INFO: 1703152 events read in total (75980ms).
[18:50:21.621] <TB1> INFO: 2553352 events read in total (114401ms).
[18:50:59.257] <TB1> INFO: 3403656 events read in total (152037ms).
[18:51:37.857] <TB1> INFO: 4253672 events read in total (190637ms).
[18:52:20.902] <TB1> INFO: 5105152 events read in total (233682ms).
[18:53:07.863] <TB1> INFO: 5956912 events read in total (280643ms).
[18:53:35.134] <TB1> INFO: 6456320 events read in total (307914ms).
[18:53:35.305] <TB1> INFO: Test took 309283ms.
[18:53:35.678] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:54:31.067] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 0.947649 .. 100.604619
[18:54:31.152] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 0 .. 110 (-1/-1) hits flags = 528 (plus default)
[18:54:31.177] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:54:31.178] <TB1> INFO: run 1 of 1
[18:54:31.551] <TB1> INFO: Expecting 3694080 events.
[18:55:13.470] <TB1> INFO: 934832 events read in total (41140ms).
[18:56:02.784] <TB1> INFO: 1868696 events read in total (90454ms).
[18:56:44.404] <TB1> INFO: 2802576 events read in total (132075ms).
[18:57:24.408] <TB1> INFO: 3694080 events read in total (172078ms).
[18:57:24.505] <TB1> INFO: Test took 173328ms.
[18:57:24.729] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[18:58:08.189] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 0.947649 .. 81.238176
[18:58:08.324] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 0 .. 91 (-1/-1) hits flags = 528 (plus default)
[18:58:08.365] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:58:08.373] <TB1> INFO: run 1 of 1
[18:58:09.011] <TB1> INFO: Expecting 3061760 events.
[18:59:00.418] <TB1> INFO: 981624 events read in total (50619ms).
[18:59:44.165] <TB1> INFO: 1961992 events read in total (94369ms).
[19:00:30.197] <TB1> INFO: 2943704 events read in total (140399ms).
[19:00:35.229] <TB1> INFO: 3061760 events read in total (145430ms).
[19:00:35.285] <TB1> INFO: Test took 146907ms.
[19:00:35.428] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[19:01:12.804] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[19:01:12.804] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[19:01:12.828] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:01:12.829] <TB1> INFO: run 1 of 1
[19:01:13.194] <TB1> INFO: Expecting 1364480 events.
[19:02:01.196] <TB1> INFO: 1079216 events read in total (47224ms).
[19:02:12.521] <TB1> INFO: 1364480 events read in total (58550ms).
[19:02:12.552] <TB1> INFO: Test took 59724ms.
[19:02:12.620] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[19:02:39.552] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C0.dat
[19:02:39.552] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C1.dat
[19:02:39.553] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C2.dat
[19:02:39.553] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C3.dat
[19:02:39.553] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C4.dat
[19:02:39.553] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C5.dat
[19:02:39.553] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C6.dat
[19:02:39.553] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C7.dat
[19:02:39.553] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C8.dat
[19:02:39.554] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C9.dat
[19:02:39.554] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C10.dat
[19:02:39.554] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C11.dat
[19:02:39.554] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C12.dat
[19:02:39.554] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C13.dat
[19:02:39.554] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C14.dat
[19:02:39.554] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C15.dat
[19:02:39.555] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C0.dat
[19:02:39.569] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C1.dat
[19:02:39.585] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C2.dat
[19:02:39.597] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C3.dat
[19:02:39.609] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C4.dat
[19:02:39.619] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C5.dat
[19:02:39.630] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C6.dat
[19:02:39.642] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C7.dat
[19:02:39.652] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C8.dat
[19:02:39.663] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C9.dat
[19:02:39.675] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C10.dat
[19:02:39.690] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C11.dat
[19:02:39.703] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C12.dat
[19:02:39.715] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C13.dat
[19:02:39.727] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C14.dat
[19:02:39.739] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//trimParameters35_C15.dat
[19:02:39.752] <TB1> INFO: PixTestTrim::trimTest() done
[19:02:39.752] <TB1> INFO: vtrim: 89 150 118 97 114 111 109 126 107 111 140 108 99 111 111 115
[19:02:39.752] <TB1> INFO: vthrcomp: 96 96 104 100 105 106 98 99 103 102 100 104 92 110 108 105
[19:02:39.752] <TB1> INFO: vcal mean: 35.06 34.30 34.50 35.01 35.03 34.98 34.66 34.98 34.98 34.63 34.73 35.03 35.02 34.95 34.93 34.99
[19:02:39.752] <TB1> INFO: vcal RMS: 1.06 5.05 4.15 1.30 1.07 1.98 3.43 1.42 1.83 3.64 3.30 0.96 0.91 2.36 1.59 1.01
[19:02:39.752] <TB1> INFO: bits mean: 9.35 7.74 8.43 9.53 8.76 8.21 8.65 9.48 8.69 8.35 9.10 8.43 9.25 8.33 8.01 8.44
[19:02:39.752] <TB1> INFO: bits RMS: 2.79 2.69 2.52 2.64 2.59 2.61 2.58 2.55 2.35 2.59 2.55 2.89 2.56 2.50 2.69 2.50
[19:02:39.770] <TB1> INFO: ----------------------------------------------------------------------
[19:02:39.770] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[19:02:39.770] <TB1> INFO: ----------------------------------------------------------------------
[19:02:39.779] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[19:02:39.806] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:02:39.808] <TB1> INFO: run 1 of 1
[19:02:40.238] <TB1> INFO: Expecting 4160000 events.
[19:03:39.926] <TB1> INFO: 1239755 events read in total (58909ms).
[19:04:35.133] <TB1> INFO: 2455465 events read in total (114116ms).
[19:05:24.485] <TB1> INFO: 3657945 events read in total (163469ms).
[19:05:47.200] <TB1> INFO: 4160000 events read in total (186183ms).
[19:05:47.318] <TB1> INFO: Test took 187509ms.
[19:05:47.520] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[19:06:47.521] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 211 (-1/-1) hits flags = 528 (plus default)
[19:06:47.548] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:06:47.548] <TB1> INFO: run 1 of 1
[19:06:47.963] <TB1> INFO: Expecting 4409600 events.
[19:07:50.779] <TB1> INFO: 1147595 events read in total (62037ms).
[19:08:39.454] <TB1> INFO: 2278925 events read in total (110713ms).
[19:09:27.485] <TB1> INFO: 3395960 events read in total (158744ms).
[19:10:11.072] <TB1> INFO: 4409600 events read in total (202330ms).
[19:10:11.200] <TB1> INFO: Test took 203652ms.
[19:10:11.434] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[19:11:13.347] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 197 (-1/-1) hits flags = 528 (plus default)
[19:11:13.371] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:11:13.371] <TB1> INFO: run 1 of 1
[19:11:13.695] <TB1> INFO: Expecting 4118400 events.
[19:12:04.098] <TB1> INFO: 1190435 events read in total (49620ms).
[19:13:04.682] <TB1> INFO: 2358115 events read in total (110205ms).
[19:13:55.392] <TB1> INFO: 3512150 events read in total (160915ms).
[19:14:22.903] <TB1> INFO: 4118400 events read in total (188425ms).
[19:14:23.023] <TB1> INFO: Test took 189651ms.
[19:14:23.239] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[19:15:23.975] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[19:15:24.004] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:15:24.004] <TB1> INFO: run 1 of 1
[19:15:24.441] <TB1> INFO: Expecting 4243200 events.
[19:16:15.932] <TB1> INFO: 1170205 events read in total (50712ms).
[19:17:15.186] <TB1> INFO: 2320850 events read in total (109966ms).
[19:18:04.032] <TB1> INFO: 3457700 events read in total (158812ms).
[19:18:41.237] <TB1> INFO: 4243200 events read in total (196017ms).
[19:18:41.357] <TB1> INFO: Test took 197353ms.
[19:18:41.603] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[19:19:42.041] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[19:19:42.092] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:19:42.092] <TB1> INFO: run 1 of 1
[19:19:42.496] <TB1> INFO: Expecting 4097600 events.
[19:20:32.072] <TB1> INFO: 1191375 events read in total (48799ms).
[19:21:22.452] <TB1> INFO: 2360690 events read in total (99179ms).
[19:22:10.479] <TB1> INFO: 3516695 events read in total (147205ms).
[19:22:34.318] <TB1> INFO: 4097600 events read in total (171044ms).
[19:22:34.427] <TB1> INFO: Test took 172335ms.
[19:22:34.615] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[19:23:29.633] <TB1> INFO: PixTestTrim::trimBitTest() done
[19:23:29.646] <TB1> INFO: PixTestTrim::doTest() done, duration: 3557 seconds
[19:23:29.646] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[19:23:29.646] <TB1> INFO: Decoding statistics:
[19:23:29.646] <TB1> INFO: General information:
[19:23:29.646] <TB1> INFO: 16bit words read: 0
[19:23:29.646] <TB1> INFO: valid events total: 0
[19:23:29.646] <TB1> INFO: empty events: 0
[19:23:29.646] <TB1> INFO: valid events with pixels: 0
[19:23:29.646] <TB1> INFO: valid pixel hits: 0
[19:23:29.646] <TB1> INFO: Event errors: 0
[19:23:29.646] <TB1> INFO: start marker: 0
[19:23:29.646] <TB1> INFO: stop marker: 0
[19:23:29.646] <TB1> INFO: overflow: 0
[19:23:29.646] <TB1> INFO: invalid 5bit words: 0
[19:23:29.646] <TB1> INFO: invalid XOR eye diagram: 0
[19:23:29.646] <TB1> INFO: TBM errors: 0
[19:23:29.646] <TB1> INFO: flawed TBM headers: 0
[19:23:29.646] <TB1> INFO: flawed TBM trailers: 0
[19:23:29.646] <TB1> INFO: event ID mismatches: 0
[19:23:29.646] <TB1> INFO: ROC errors: 0
[19:23:29.646] <TB1> INFO: missing ROC header(s): 0
[19:23:29.646] <TB1> INFO: misplaced readback start: 0
[19:23:29.646] <TB1> INFO: Pixel decoding errors: 0
[19:23:29.646] <TB1> INFO: pixel data incomplete: 0
[19:23:29.646] <TB1> INFO: pixel address: 0
[19:23:29.646] <TB1> INFO: pulse height fill bit: 0
[19:23:29.647] <TB1> INFO: buffer corruption: 0
[19:23:30.882] <TB1> INFO: ######################################################################
[19:23:30.882] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[19:23:30.883] <TB1> INFO: ######################################################################
[19:23:31.266] <TB1> INFO: Expecting 41600 events.
[19:23:35.954] <TB1> INFO: 41600 events read in total (3909ms).
[19:23:35.956] <TB1> INFO: Test took 5058ms.
[19:23:35.969] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[19:23:36.759] <TB1> INFO: Expecting 41600 events.
[19:23:41.426] <TB1> INFO: 41600 events read in total (3889ms).
[19:23:41.427] <TB1> INFO: Test took 5061ms.
[19:23:41.439] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[19:23:41.890] <TB1> INFO: Expecting 41600 events.
[19:23:46.572] <TB1> INFO: 41600 events read in total (3903ms).
[19:23:46.574] <TB1> INFO: Test took 5077ms.
[19:23:46.585] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[19:23:47.047] <TB1> INFO: Expecting 2560 events.
[19:23:48.079] <TB1> INFO: 2560 events read in total (253ms).
[19:23:48.079] <TB1> INFO: Test took 1479ms.
[19:23:48.650] <TB1> INFO: Expecting 2560 events.
[19:23:49.683] <TB1> INFO: 2560 events read in total (254ms).
[19:23:49.683] <TB1> INFO: Test took 1603ms.
[19:23:50.256] <TB1> INFO: Expecting 2560 events.
[19:23:51.287] <TB1> INFO: 2560 events read in total (252ms).
[19:23:51.288] <TB1> INFO: Test took 1604ms.
[19:23:51.859] <TB1> INFO: Expecting 2560 events.
[19:23:52.890] <TB1> INFO: 2560 events read in total (251ms).
[19:23:52.890] <TB1> INFO: Test took 1602ms.
[19:23:53.462] <TB1> INFO: Expecting 2560 events.
[19:23:54.490] <TB1> INFO: 2560 events read in total (249ms).
[19:23:54.490] <TB1> INFO: Test took 1599ms.
[19:23:55.062] <TB1> INFO: Expecting 2560 events.
[19:23:56.090] <TB1> INFO: 2560 events read in total (249ms).
[19:23:56.090] <TB1> INFO: Test took 1599ms.
[19:23:56.661] <TB1> INFO: Expecting 2560 events.
[19:23:57.694] <TB1> INFO: 2560 events read in total (254ms).
[19:23:57.695] <TB1> INFO: Test took 1604ms.
[19:23:58.266] <TB1> INFO: Expecting 2560 events.
[19:23:59.294] <TB1> INFO: 2560 events read in total (248ms).
[19:23:59.297] <TB1> INFO: Test took 1601ms.
[19:23:59.869] <TB1> INFO: Expecting 2560 events.
[19:24:00.899] <TB1> INFO: 2560 events read in total (251ms).
[19:24:00.900] <TB1> INFO: Test took 1597ms.
[19:24:01.470] <TB1> INFO: Expecting 2560 events.
[19:24:02.501] <TB1> INFO: 2560 events read in total (252ms).
[19:24:02.504] <TB1> INFO: Test took 1603ms.
[19:24:03.072] <TB1> INFO: Expecting 2560 events.
[19:24:04.106] <TB1> INFO: 2560 events read in total (255ms).
[19:24:04.106] <TB1> INFO: Test took 1599ms.
[19:24:04.677] <TB1> INFO: Expecting 2560 events.
[19:24:05.707] <TB1> INFO: 2560 events read in total (252ms).
[19:24:05.708] <TB1> INFO: Test took 1600ms.
[19:24:06.278] <TB1> INFO: Expecting 2560 events.
[19:24:07.309] <TB1> INFO: 2560 events read in total (252ms).
[19:24:07.309] <TB1> INFO: Test took 1598ms.
[19:24:07.881] <TB1> INFO: Expecting 2560 events.
[19:24:08.908] <TB1> INFO: 2560 events read in total (249ms).
[19:24:08.908] <TB1> INFO: Test took 1598ms.
[19:24:09.481] <TB1> INFO: Expecting 2560 events.
[19:24:10.508] <TB1> INFO: 2560 events read in total (249ms).
[19:24:10.514] <TB1> INFO: Test took 1605ms.
[19:24:11.080] <TB1> INFO: Expecting 2560 events.
[19:24:12.107] <TB1> INFO: 2560 events read in total (249ms).
[19:24:12.108] <TB1> INFO: Test took 1590ms.
[19:24:12.113] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:24:12.682] <TB1> INFO: Expecting 655360 events.
[19:24:26.260] <TB1> INFO: 655360 events read in total (12799ms).
[19:24:26.284] <TB1> INFO: Expecting 655360 events.
[19:24:39.548] <TB1> INFO: 655360 events read in total (12737ms).
[19:24:39.582] <TB1> INFO: Expecting 655360 events.
[19:24:52.952] <TB1> INFO: 655360 events read in total (12844ms).
[19:24:52.997] <TB1> INFO: Expecting 655360 events.
[19:25:06.753] <TB1> INFO: 655360 events read in total (13230ms).
[19:25:06.800] <TB1> INFO: Expecting 655360 events.
[19:25:20.723] <TB1> INFO: 655360 events read in total (13397ms).
[19:25:20.765] <TB1> INFO: Expecting 655360 events.
[19:25:34.060] <TB1> INFO: 655360 events read in total (12768ms).
[19:25:34.121] <TB1> INFO: Expecting 655360 events.
[19:25:47.387] <TB1> INFO: 655360 events read in total (12739ms).
[19:25:47.444] <TB1> INFO: Expecting 655360 events.
[19:26:00.782] <TB1> INFO: 655360 events read in total (12811ms).
[19:26:00.856] <TB1> INFO: Expecting 655360 events.
[19:26:14.260] <TB1> INFO: 655360 events read in total (12877ms).
[19:26:14.345] <TB1> INFO: Expecting 655360 events.
[19:26:27.705] <TB1> INFO: 655360 events read in total (12833ms).
[19:26:27.788] <TB1> INFO: Expecting 655360 events.
[19:26:41.167] <TB1> INFO: 655360 events read in total (12853ms).
[19:26:41.269] <TB1> INFO: Expecting 655360 events.
[19:26:54.697] <TB1> INFO: 655360 events read in total (12901ms).
[19:26:54.807] <TB1> INFO: Expecting 655360 events.
[19:27:08.229] <TB1> INFO: 655360 events read in total (12895ms).
[19:27:08.343] <TB1> INFO: Expecting 655360 events.
[19:27:21.789] <TB1> INFO: 655360 events read in total (12920ms).
[19:27:21.912] <TB1> INFO: Expecting 655360 events.
[19:27:35.356] <TB1> INFO: 655360 events read in total (12917ms).
[19:27:35.483] <TB1> INFO: Expecting 655360 events.
[19:27:48.836] <TB1> INFO: 655360 events read in total (12827ms).
[19:27:48.960] <TB1> INFO: Test took 216848ms.
[19:27:49.107] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:49.472] <TB1> INFO: Expecting 655360 events.
[19:28:03.013] <TB1> INFO: 655360 events read in total (12763ms).
[19:28:03.034] <TB1> INFO: Expecting 655360 events.
[19:28:16.174] <TB1> INFO: 655360 events read in total (12613ms).
[19:28:16.203] <TB1> INFO: Expecting 655360 events.
[19:28:29.475] <TB1> INFO: 655360 events read in total (12745ms).
[19:28:29.508] <TB1> INFO: Expecting 655360 events.
[19:28:42.854] <TB1> INFO: 655360 events read in total (12819ms).
[19:28:42.898] <TB1> INFO: Expecting 655360 events.
[19:28:58.702] <TB1> INFO: 655360 events read in total (15277ms).
[19:28:58.743] <TB1> INFO: Expecting 655360 events.
[19:29:12.051] <TB1> INFO: 655360 events read in total (12781ms).
[19:29:12.103] <TB1> INFO: Expecting 655360 events.
[19:29:25.424] <TB1> INFO: 655360 events read in total (12794ms).
[19:29:25.499] <TB1> INFO: Expecting 655360 events.
[19:29:38.696] <TB1> INFO: 655360 events read in total (12663ms).
[19:29:38.760] <TB1> INFO: Expecting 655360 events.
[19:29:52.046] <TB1> INFO: 655360 events read in total (12759ms).
[19:29:52.124] <TB1> INFO: Expecting 655360 events.
[19:30:05.717] <TB1> INFO: 655360 events read in total (13066ms).
[19:30:05.791] <TB1> INFO: Expecting 655360 events.
[19:30:19.279] <TB1> INFO: 655360 events read in total (12961ms).
[19:30:19.379] <TB1> INFO: Expecting 655360 events.
[19:30:33.581] <TB1> INFO: 655360 events read in total (13675ms).
[19:30:33.702] <TB1> INFO: Expecting 655360 events.
[19:30:47.222] <TB1> INFO: 655360 events read in total (12993ms).
[19:30:47.379] <TB1> INFO: Expecting 655360 events.
[19:31:00.945] <TB1> INFO: 655360 events read in total (13038ms).
[19:31:01.119] <TB1> INFO: Expecting 655360 events.
[19:31:14.788] <TB1> INFO: 655360 events read in total (13142ms).
[19:31:14.931] <TB1> INFO: Expecting 655360 events.
[19:31:28.304] <TB1> INFO: 655360 events read in total (12846ms).
[19:31:28.449] <TB1> INFO: Test took 219342ms.
[19:31:28.834] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:28.856] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:28.879] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:28.898] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:28.920] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:28.941] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:28.966] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:28.988] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:29.014] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:29.038] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:29.057] <TB1> INFO: For ROC 9: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[19:31:29.062] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[19:31:29.088] <TB1> INFO: For ROC 9: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[19:31:29.093] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[19:31:29.116] <TB1> INFO: For ROC 9: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[19:31:29.123] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[19:31:29.147] <TB1> INFO: For ROC 9: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[19:31:29.152] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[19:31:29.182] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:29.206] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:29.228] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:29.250] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:29.267] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:29.287] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:31:29.341] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C0.dat
[19:31:29.341] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C1.dat
[19:31:29.342] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C2.dat
[19:31:29.342] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C3.dat
[19:31:29.342] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C4.dat
[19:31:29.343] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C5.dat
[19:31:29.344] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C6.dat
[19:31:29.344] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C7.dat
[19:31:29.344] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C8.dat
[19:31:29.344] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C9.dat
[19:31:29.344] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C10.dat
[19:31:29.345] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C11.dat
[19:31:29.345] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C12.dat
[19:31:29.345] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C13.dat
[19:31:29.345] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C14.dat
[19:31:29.345] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//dacParameters35_C15.dat
[19:31:29.751] <TB1> INFO: Expecting 41600 events.
[19:31:34.036] <TB1> INFO: 41600 events read in total (3507ms).
[19:31:34.038] <TB1> INFO: Test took 4683ms.
[19:31:34.806] <TB1> INFO: Expecting 41600 events.
[19:31:39.118] <TB1> INFO: 41600 events read in total (3534ms).
[19:31:39.120] <TB1> INFO: Test took 4741ms.
[19:31:39.794] <TB1> INFO: Expecting 41600 events.
[19:31:44.629] <TB1> INFO: 41600 events read in total (4057ms).
[19:31:44.631] <TB1> INFO: Test took 5177ms.
[19:31:44.984] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:31:45.147] <TB1> INFO: Expecting 2560 events.
[19:31:46.214] <TB1> INFO: 2560 events read in total (283ms).
[19:31:46.221] <TB1> INFO: Test took 1237ms.
[19:31:46.228] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:31:46.812] <TB1> INFO: Expecting 2560 events.
[19:31:47.873] <TB1> INFO: 2560 events read in total (283ms).
[19:31:47.881] <TB1> INFO: Test took 1654ms.
[19:31:47.896] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:31:48.516] <TB1> INFO: Expecting 2560 events.
[19:31:49.556] <TB1> INFO: 2560 events read in total (257ms).
[19:31:49.562] <TB1> INFO: Test took 1666ms.
[19:31:49.578] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:31:50.162] <TB1> INFO: Expecting 2560 events.
[19:31:51.238] <TB1> INFO: 2560 events read in total (281ms).
[19:31:51.240] <TB1> INFO: Test took 1662ms.
[19:31:51.249] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:31:51.836] <TB1> INFO: Expecting 2560 events.
[19:31:52.891] <TB1> INFO: 2560 events read in total (276ms).
[19:31:52.895] <TB1> INFO: Test took 1646ms.
[19:31:52.907] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:31:53.490] <TB1> INFO: Expecting 2560 events.
[19:31:54.556] <TB1> INFO: 2560 events read in total (280ms).
[19:31:54.556] <TB1> INFO: Test took 1649ms.
[19:31:54.574] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:31:55.161] <TB1> INFO: Expecting 2560 events.
[19:31:56.207] <TB1> INFO: 2560 events read in total (261ms).
[19:31:56.207] <TB1> INFO: Test took 1633ms.
[19:31:56.209] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:31:56.780] <TB1> INFO: Expecting 2560 events.
[19:31:57.808] <TB1> INFO: 2560 events read in total (250ms).
[19:31:57.809] <TB1> INFO: Test took 1600ms.
[19:31:57.814] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:31:58.406] <TB1> INFO: Expecting 2560 events.
[19:31:59.439] <TB1> INFO: 2560 events read in total (252ms).
[19:31:59.439] <TB1> INFO: Test took 1625ms.
[19:31:59.447] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:00.012] <TB1> INFO: Expecting 2560 events.
[19:32:01.039] <TB1> INFO: 2560 events read in total (248ms).
[19:32:01.040] <TB1> INFO: Test took 1593ms.
[19:32:01.048] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:01.616] <TB1> INFO: Expecting 2560 events.
[19:32:02.644] <TB1> INFO: 2560 events read in total (250ms).
[19:32:02.654] <TB1> INFO: Test took 1606ms.
[19:32:02.661] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:03.217] <TB1> INFO: Expecting 2560 events.
[19:32:04.245] <TB1> INFO: 2560 events read in total (250ms).
[19:32:04.246] <TB1> INFO: Test took 1585ms.
[19:32:04.249] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:04.819] <TB1> INFO: Expecting 2560 events.
[19:32:05.846] <TB1> INFO: 2560 events read in total (249ms).
[19:32:05.846] <TB1> INFO: Test took 1597ms.
[19:32:05.850] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:06.426] <TB1> INFO: Expecting 2560 events.
[19:32:07.454] <TB1> INFO: 2560 events read in total (250ms).
[19:32:07.454] <TB1> INFO: Test took 1605ms.
[19:32:07.458] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:08.027] <TB1> INFO: Expecting 2560 events.
[19:32:09.054] <TB1> INFO: 2560 events read in total (248ms).
[19:32:09.056] <TB1> INFO: Test took 1598ms.
[19:32:09.061] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:09.628] <TB1> INFO: Expecting 2560 events.
[19:32:10.660] <TB1> INFO: 2560 events read in total (251ms).
[19:32:10.665] <TB1> INFO: Test took 1605ms.
[19:32:10.672] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:11.236] <TB1> INFO: Expecting 2560 events.
[19:32:12.262] <TB1> INFO: 2560 events read in total (247ms).
[19:32:12.262] <TB1> INFO: Test took 1590ms.
[19:32:12.268] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:12.835] <TB1> INFO: Expecting 2560 events.
[19:32:13.860] <TB1> INFO: 2560 events read in total (246ms).
[19:32:13.861] <TB1> INFO: Test took 1593ms.
[19:32:13.870] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:14.434] <TB1> INFO: Expecting 2560 events.
[19:32:15.487] <TB1> INFO: 2560 events read in total (274ms).
[19:32:15.497] <TB1> INFO: Test took 1627ms.
[19:32:15.523] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:16.062] <TB1> INFO: Expecting 2560 events.
[19:32:17.094] <TB1> INFO: 2560 events read in total (250ms).
[19:32:17.094] <TB1> INFO: Test took 1576ms.
[19:32:17.102] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:17.670] <TB1> INFO: Expecting 2560 events.
[19:32:18.698] <TB1> INFO: 2560 events read in total (249ms).
[19:32:18.699] <TB1> INFO: Test took 1597ms.
[19:32:18.709] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:19.271] <TB1> INFO: Expecting 2560 events.
[19:32:20.300] <TB1> INFO: 2560 events read in total (248ms).
[19:32:20.300] <TB1> INFO: Test took 1591ms.
[19:32:20.308] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:20.878] <TB1> INFO: Expecting 2560 events.
[19:32:21.918] <TB1> INFO: 2560 events read in total (249ms).
[19:32:21.918] <TB1> INFO: Test took 1610ms.
[19:32:21.928] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:22.498] <TB1> INFO: Expecting 2560 events.
[19:32:23.529] <TB1> INFO: 2560 events read in total (253ms).
[19:32:23.530] <TB1> INFO: Test took 1603ms.
[19:32:23.534] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:24.103] <TB1> INFO: Expecting 2560 events.
[19:32:25.131] <TB1> INFO: 2560 events read in total (250ms).
[19:32:25.131] <TB1> INFO: Test took 1598ms.
[19:32:25.137] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:25.705] <TB1> INFO: Expecting 2560 events.
[19:32:26.733] <TB1> INFO: 2560 events read in total (249ms).
[19:32:26.733] <TB1> INFO: Test took 1597ms.
[19:32:26.744] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:27.318] <TB1> INFO: Expecting 2560 events.
[19:32:28.346] <TB1> INFO: 2560 events read in total (250ms).
[19:32:28.346] <TB1> INFO: Test took 1603ms.
[19:32:28.353] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:28.920] <TB1> INFO: Expecting 2560 events.
[19:32:29.946] <TB1> INFO: 2560 events read in total (248ms).
[19:32:29.948] <TB1> INFO: Test took 1596ms.
[19:32:29.951] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:30.523] <TB1> INFO: Expecting 2560 events.
[19:32:31.551] <TB1> INFO: 2560 events read in total (249ms).
[19:32:31.552] <TB1> INFO: Test took 1602ms.
[19:32:31.559] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:32.129] <TB1> INFO: Expecting 2560 events.
[19:32:33.159] <TB1> INFO: 2560 events read in total (253ms).
[19:32:33.161] <TB1> INFO: Test took 1602ms.
[19:32:33.167] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:33.739] <TB1> INFO: Expecting 2560 events.
[19:32:34.767] <TB1> INFO: 2560 events read in total (249ms).
[19:32:34.768] <TB1> INFO: Test took 1602ms.
[19:32:34.775] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:32:35.342] <TB1> INFO: Expecting 2560 events.
[19:32:36.372] <TB1> INFO: 2560 events read in total (251ms).
[19:32:36.375] <TB1> INFO: Test took 1601ms.
[19:32:37.197] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 546 seconds
[19:32:37.206] <TB1> INFO: PH scale (per ROC): 70 64 75 80 73 70 71 73 74 75 73 67 80 76 70 72
[19:32:37.213] <TB1> INFO: PH offset (per ROC): 166 188 178 186 176 194 177 178 165 176 197 181 174 167 187 176
[19:32:37.234] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[19:32:37.248] <TB1> INFO: Decoding statistics:
[19:32:37.252] <TB1> INFO: General information:
[19:32:37.252] <TB1> INFO: 16bit words read: 66452
[19:32:37.252] <TB1> INFO: valid events total: 5120
[19:32:37.252] <TB1> INFO: empty events: 2614
[19:32:37.252] <TB1> INFO: valid events with pixels: 2506
[19:32:37.252] <TB1> INFO: valid pixel hits: 2506
[19:32:37.252] <TB1> INFO: Event errors: 0
[19:32:37.252] <TB1> INFO: start marker: 0
[19:32:37.252] <TB1> INFO: stop marker: 0
[19:32:37.252] <TB1> INFO: overflow: 0
[19:32:37.252] <TB1> INFO: invalid 5bit words: 0
[19:32:37.253] <TB1> INFO: invalid XOR eye diagram: 0
[19:32:37.253] <TB1> INFO: TBM errors: 0
[19:32:37.253] <TB1> INFO: flawed TBM headers: 0
[19:32:37.253] <TB1> INFO: flawed TBM trailers: 0
[19:32:37.253] <TB1> INFO: event ID mismatches: 0
[19:32:37.253] <TB1> INFO: ROC errors: 0
[19:32:37.253] <TB1> INFO: missing ROC header(s): 0
[19:32:37.253] <TB1> INFO: misplaced readback start: 0
[19:32:37.253] <TB1> INFO: Pixel decoding errors: 0
[19:32:37.253] <TB1> INFO: pixel data incomplete: 0
[19:32:37.253] <TB1> INFO: pixel address: 0
[19:32:37.253] <TB1> INFO: pulse height fill bit: 0
[19:32:37.253] <TB1> INFO: buffer corruption: 0
[19:32:37.636] <TB1> INFO: ######################################################################
[19:32:37.636] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[19:32:37.636] <TB1> INFO: ######################################################################
[19:32:37.679] <TB1> INFO: scanning low vcal = 10
[19:32:38.122] <TB1> INFO: Expecting 41600 events.
[19:32:41.557] <TB1> INFO: 41600 events read in total (2656ms).
[19:32:41.558] <TB1> INFO: Test took 3879ms.
[19:32:41.564] <TB1> INFO: scanning low vcal = 20
[19:32:42.141] <TB1> INFO: Expecting 41600 events.
[19:32:45.585] <TB1> INFO: 41600 events read in total (2666ms).
[19:32:45.586] <TB1> INFO: Test took 4022ms.
[19:32:45.594] <TB1> INFO: scanning low vcal = 30
[19:32:46.164] <TB1> INFO: Expecting 41600 events.
[19:32:49.721] <TB1> INFO: 41600 events read in total (2778ms).
[19:32:49.733] <TB1> INFO: Test took 4139ms.
[19:32:49.739] <TB1> INFO: scanning low vcal = 40
[19:32:50.281] <TB1> INFO: Expecting 41600 events.
[19:32:54.372] <TB1> INFO: 41600 events read in total (3312ms).
[19:32:54.374] <TB1> INFO: Test took 4635ms.
[19:32:54.386] <TB1> INFO: scanning low vcal = 50
[19:32:54.834] <TB1> INFO: Expecting 41600 events.
[19:32:58.909] <TB1> INFO: 41600 events read in total (3296ms).
[19:32:58.910] <TB1> INFO: Test took 4524ms.
[19:32:58.918] <TB1> INFO: scanning low vcal = 60
[19:32:59.381] <TB1> INFO: Expecting 41600 events.
[19:33:03.436] <TB1> INFO: 41600 events read in total (3276ms).
[19:33:03.444] <TB1> INFO: Test took 4525ms.
[19:33:03.454] <TB1> INFO: scanning low vcal = 70
[19:33:03.949] <TB1> INFO: Expecting 41600 events.
[19:33:08.035] <TB1> INFO: 41600 events read in total (3307ms).
[19:33:08.039] <TB1> INFO: Test took 4584ms.
[19:33:08.047] <TB1> INFO: scanning low vcal = 80
[19:33:08.451] <TB1> INFO: Expecting 41600 events.
[19:33:12.511] <TB1> INFO: 41600 events read in total (3282ms).
[19:33:12.519] <TB1> INFO: Test took 4472ms.
[19:33:12.527] <TB1> INFO: scanning low vcal = 90
[19:33:12.975] <TB1> INFO: Expecting 41600 events.
[19:33:17.081] <TB1> INFO: 41600 events read in total (3328ms).
[19:33:17.090] <TB1> INFO: Test took 4563ms.
[19:33:17.108] <TB1> INFO: scanning low vcal = 100
[19:33:17.550] <TB1> INFO: Expecting 41600 events.
[19:33:21.561] <TB1> INFO: 41600 events read in total (3230ms).
[19:33:21.562] <TB1> INFO: Test took 4454ms.
[19:33:21.575] <TB1> INFO: scanning low vcal = 110
[19:33:22.058] <TB1> INFO: Expecting 41600 events.
[19:33:26.162] <TB1> INFO: 41600 events read in total (3325ms).
[19:33:26.190] <TB1> INFO: Test took 4615ms.
[19:33:26.213] <TB1> INFO: scanning low vcal = 120
[19:33:26.596] <TB1> INFO: Expecting 41600 events.
[19:33:30.680] <TB1> INFO: 41600 events read in total (3306ms).
[19:33:30.682] <TB1> INFO: Test took 4456ms.
[19:33:30.696] <TB1> INFO: scanning low vcal = 130
[19:33:31.135] <TB1> INFO: Expecting 41600 events.
[19:33:35.222] <TB1> INFO: 41600 events read in total (3308ms).
[19:33:35.223] <TB1> INFO: Test took 4527ms.
[19:33:35.232] <TB1> INFO: scanning low vcal = 140
[19:33:35.686] <TB1> INFO: Expecting 41600 events.
[19:33:39.756] <TB1> INFO: 41600 events read in total (3291ms).
[19:33:39.758] <TB1> INFO: Test took 4525ms.
[19:33:39.768] <TB1> INFO: scanning low vcal = 150
[19:33:40.225] <TB1> INFO: Expecting 41600 events.
[19:33:44.237] <TB1> INFO: 41600 events read in total (3234ms).
[19:33:44.239] <TB1> INFO: Test took 4471ms.
[19:33:44.248] <TB1> INFO: scanning low vcal = 160
[19:33:44.685] <TB1> INFO: Expecting 41600 events.
[19:33:48.801] <TB1> INFO: 41600 events read in total (3337ms).
[19:33:48.806] <TB1> INFO: Test took 4557ms.
[19:33:48.817] <TB1> INFO: scanning low vcal = 170
[19:33:49.213] <TB1> INFO: Expecting 41600 events.
[19:33:53.301] <TB1> INFO: 41600 events read in total (3306ms).
[19:33:53.302] <TB1> INFO: Test took 4485ms.
[19:33:53.319] <TB1> INFO: scanning low vcal = 180
[19:33:53.768] <TB1> INFO: Expecting 41600 events.
[19:33:57.824] <TB1> INFO: 41600 events read in total (3278ms).
[19:33:57.825] <TB1> INFO: Test took 4506ms.
[19:33:57.833] <TB1> INFO: scanning low vcal = 190
[19:33:58.313] <TB1> INFO: Expecting 41600 events.
[19:34:02.387] <TB1> INFO: 41600 events read in total (3295ms).
[19:34:02.389] <TB1> INFO: Test took 4556ms.
[19:34:02.400] <TB1> INFO: scanning low vcal = 200
[19:34:02.834] <TB1> INFO: Expecting 41600 events.
[19:34:06.971] <TB1> INFO: 41600 events read in total (3358ms).
[19:34:06.981] <TB1> INFO: Test took 4581ms.
[19:34:06.992] <TB1> INFO: scanning low vcal = 210
[19:34:07.522] <TB1> INFO: Expecting 41600 events.
[19:34:11.695] <TB1> INFO: 41600 events read in total (3393ms).
[19:34:11.697] <TB1> INFO: Test took 4705ms.
[19:34:11.707] <TB1> INFO: scanning low vcal = 220
[19:34:12.213] <TB1> INFO: Expecting 41600 events.
[19:34:16.265] <TB1> INFO: 41600 events read in total (3274ms).
[19:34:16.267] <TB1> INFO: Test took 4560ms.
[19:34:16.280] <TB1> INFO: scanning low vcal = 230
[19:34:16.731] <TB1> INFO: Expecting 41600 events.
[19:34:20.738] <TB1> INFO: 41600 events read in total (3229ms).
[19:34:20.739] <TB1> INFO: Test took 4457ms.
[19:34:20.744] <TB1> INFO: scanning low vcal = 240
[19:34:21.216] <TB1> INFO: Expecting 41600 events.
[19:34:25.230] <TB1> INFO: 41600 events read in total (3235ms).
[19:34:25.231] <TB1> INFO: Test took 4486ms.
[19:34:25.238] <TB1> INFO: scanning low vcal = 250
[19:34:25.690] <TB1> INFO: Expecting 41600 events.
[19:34:29.751] <TB1> INFO: 41600 events read in total (3283ms).
[19:34:29.752] <TB1> INFO: Test took 4514ms.
[19:34:29.760] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[19:34:30.226] <TB1> INFO: Expecting 41600 events.
[19:34:34.297] <TB1> INFO: 41600 events read in total (3293ms).
[19:34:34.299] <TB1> INFO: Test took 4537ms.
[19:34:34.306] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[19:34:34.772] <TB1> INFO: Expecting 41600 events.
[19:34:38.826] <TB1> INFO: 41600 events read in total (3275ms).
[19:34:38.827] <TB1> INFO: Test took 4522ms.
[19:34:38.838] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[19:34:39.264] <TB1> INFO: Expecting 41600 events.
[19:34:43.298] <TB1> INFO: 41600 events read in total (3256ms).
[19:34:43.299] <TB1> INFO: Test took 4460ms.
[19:34:43.306] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[19:34:43.784] <TB1> INFO: Expecting 41600 events.
[19:34:47.842] <TB1> INFO: 41600 events read in total (3279ms).
[19:34:47.843] <TB1> INFO: Test took 4537ms.
[19:34:47.849] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[19:34:48.330] <TB1> INFO: Expecting 41600 events.
[19:34:52.347] <TB1> INFO: 41600 events read in total (3238ms).
[19:34:52.348] <TB1> INFO: Test took 4498ms.
[19:34:53.270] <TB1> INFO: PixTestGainPedestal::measure() done
[19:36:05.434] <TB1> INFO: PixTestGainPedestal::fit() done
[19:36:05.434] <TB1> INFO: non-linearity mean: 0.962 0.915 0.956 0.958 0.956 0.961 0.960 0.954 0.961 0.962 0.961 0.955 0.966 0.964 0.960 0.960
[19:36:05.434] <TB1> INFO: non-linearity RMS: 0.007 0.043 0.007 0.007 0.006 0.008 0.008 0.008 0.007 0.006 0.007 0.006 0.005 0.005 0.007 0.007
[19:36:05.435] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C0.dat
[19:36:05.471] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C1.dat
[19:36:05.505] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C2.dat
[19:36:05.539] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C3.dat
[19:36:05.574] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C4.dat
[19:36:05.610] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C5.dat
[19:36:05.646] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C6.dat
[19:36:05.683] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C7.dat
[19:36:05.719] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C8.dat
[19:36:05.756] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C9.dat
[19:36:05.791] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C10.dat
[19:36:05.828] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C11.dat
[19:36:05.864] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C12.dat
[19:36:05.901] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C13.dat
[19:36:05.936] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C14.dat
[19:36:05.972] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//phCalibrationFitErr35_C15.dat
[19:36:06.008] <TB1> INFO: PixTestGainPedestal::doTest() done, duration: 208 seconds
[19:36:06.009] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[19:36:06.009] <TB1> INFO: Decoding statistics:
[19:36:06.009] <TB1> INFO: General information:
[19:36:06.009] <TB1> INFO: 16bit words read: 2325634
[19:36:06.009] <TB1> INFO: valid events total: 83200
[19:36:06.009] <TB1> INFO: empty events: 0
[19:36:06.009] <TB1> INFO: valid events with pixels: 83200
[19:36:06.009] <TB1> INFO: valid pixel hits: 663617
[19:36:06.009] <TB1> INFO: Event errors: 0
[19:36:06.009] <TB1> INFO: start marker: 0
[19:36:06.009] <TB1> INFO: stop marker: 0
[19:36:06.009] <TB1> INFO: overflow: 0
[19:36:06.009] <TB1> INFO: invalid 5bit words: 0
[19:36:06.009] <TB1> INFO: invalid XOR eye diagram: 0
[19:36:06.009] <TB1> INFO: TBM errors: 0
[19:36:06.009] <TB1> INFO: flawed TBM headers: 0
[19:36:06.009] <TB1> INFO: flawed TBM trailers: 0
[19:36:06.009] <TB1> INFO: event ID mismatches: 0
[19:36:06.009] <TB1> INFO: ROC errors: 0
[19:36:06.009] <TB1> INFO: missing ROC header(s): 0
[19:36:06.009] <TB1> INFO: misplaced readback start: 0
[19:36:06.009] <TB1> INFO: Pixel decoding errors: 0
[19:36:06.009] <TB1> INFO: pixel data incomplete: 0
[19:36:06.009] <TB1> INFO: pixel address: 0
[19:36:06.009] <TB1> INFO: pulse height fill bit: 0
[19:36:06.009] <TB1> INFO: buffer corruption: 0
[19:36:06.023] <TB1> INFO: readReadbackCal: /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C0.dat .. /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C15.dat
[19:36:06.025] <TB1> INFO: ######################################################################
[19:36:06.026] <TB1> INFO: PixTestTrim::doTest()
[19:36:06.026] <TB1> INFO: ######################################################################
[19:36:06.027] <TB1> INFO: PixTestReadback::RES sent once
[19:36:18.619] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C0.dat
[19:36:18.619] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C1.dat
[19:36:18.619] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C2.dat
[19:36:18.619] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C3.dat
[19:36:18.619] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C4.dat
[19:36:18.620] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C5.dat
[19:36:18.620] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C6.dat
[19:36:18.620] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C7.dat
[19:36:18.620] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C8.dat
[19:36:18.620] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C9.dat
[19:36:18.620] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C10.dat
[19:36:18.621] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C11.dat
[19:36:18.621] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C12.dat
[19:36:18.621] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C13.dat
[19:36:18.621] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C14.dat
[19:36:18.621] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C15.dat
[19:36:18.661] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[19:36:18.663] <TB1> INFO: PixTestReadback::RES sent once
[19:36:31.225] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C0.dat
[19:36:31.225] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C1.dat
[19:36:31.225] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C2.dat
[19:36:31.225] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C3.dat
[19:36:31.225] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C4.dat
[19:36:31.225] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C5.dat
[19:36:31.225] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C6.dat
[19:36:31.225] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C7.dat
[19:36:31.226] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C8.dat
[19:36:31.226] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C9.dat
[19:36:31.226] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C10.dat
[19:36:31.226] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C11.dat
[19:36:31.226] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C12.dat
[19:36:31.226] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C13.dat
[19:36:31.226] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C14.dat
[19:36:31.226] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C15.dat
[19:36:31.271] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[19:36:31.272] <TB1> INFO: PixTestReadback::RES sent once
[19:36:40.956] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[19:36:40.957] <TB1> INFO: Vbg will be calibrated using Vd calibration
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 148.3calibrated Vbg = 1.22569 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 153calibrated Vbg = 1.2255 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 162calibrated Vbg = 1.22951 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 149.1calibrated Vbg = 1.23465 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 154calibrated Vbg = 1.23989 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 157.2calibrated Vbg = 1.23968 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 155.3calibrated Vbg = 1.23591 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 153.4calibrated Vbg = 1.239 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 148.1calibrated Vbg = 1.23646 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 151.9calibrated Vbg = 1.24344 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 161.5calibrated Vbg = 1.2393 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 152.2calibrated Vbg = 1.23859 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 150.1calibrated Vbg = 1.2304 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152.9calibrated Vbg = 1.22417 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 161calibrated Vbg = 1.23215 :::*/*/*/*/
[19:36:40.957] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 151.7calibrated Vbg = 1.21926 :::*/*/*/*/
[19:36:40.961] <TB1> INFO: PixTestReadback::RES sent once
[19:39:50.967] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C0.dat
[19:39:50.967] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C1.dat
[19:39:50.967] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C2.dat
[19:39:50.967] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C3.dat
[19:39:50.967] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C4.dat
[19:39:50.968] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C5.dat
[19:39:50.968] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C6.dat
[19:39:50.968] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C7.dat
[19:39:50.969] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C8.dat
[19:39:50.969] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C9.dat
[19:39:50.969] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C10.dat
[19:39:50.969] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C11.dat
[19:39:50.969] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C12.dat
[19:39:50.969] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C13.dat
[19:39:50.970] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C14.dat
[19:39:50.970] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//004_Fulltest_p17//readbackCal_C15.dat
[19:39:51.008] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[19:39:51.010] <TB1> INFO: PixTestReadback::doTest() done
[19:39:51.010] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[19:39:51.010] <TB1> INFO: Decoding statistics:
[19:39:51.010] <TB1> INFO: General information:
[19:39:51.010] <TB1> INFO: 16bit words read: 768
[19:39:51.010] <TB1> INFO: valid events total: 64
[19:39:51.010] <TB1> INFO: empty events: 64
[19:39:51.010] <TB1> INFO: valid events with pixels: 0
[19:39:51.010] <TB1> INFO: valid pixel hits: 0
[19:39:51.010] <TB1> INFO: Event errors: 0
[19:39:51.010] <TB1> INFO: start marker: 0
[19:39:51.010] <TB1> INFO: stop marker: 0
[19:39:51.010] <TB1> INFO: overflow: 0
[19:39:51.010] <TB1> INFO: invalid 5bit words: 0
[19:39:51.010] <TB1> INFO: invalid XOR eye diagram: 0
[19:39:51.010] <TB1> INFO: TBM errors: 0
[19:39:51.010] <TB1> INFO: flawed TBM headers: 0
[19:39:51.010] <TB1> INFO: flawed TBM trailers: 0
[19:39:51.010] <TB1> INFO: event ID mismatches: 0
[19:39:51.011] <TB1> INFO: ROC errors: 0
[19:39:51.011] <TB1> INFO: missing ROC header(s): 0
[19:39:51.011] <TB1> INFO: misplaced readback start: 0
[19:39:51.011] <TB1> INFO: Pixel decoding errors: 0
[19:39:51.011] <TB1> INFO: pixel data incomplete: 0
[19:39:51.011] <TB1> INFO: pixel address: 0
[19:39:51.011] <TB1> INFO: pulse height fill bit: 0
[19:39:51.011] <TB1> INFO: buffer corruption: 0
[19:39:51.042] <TB1> INFO: Decoding statistics:
[19:39:51.043] <TB1> INFO: General information:
[19:39:51.043] <TB1> INFO: 16bit words read: 9427608
[19:39:51.043] <TB1> INFO: valid events total: 551744
[19:39:51.043] <TB1> INFO: empty events: 308888
[19:39:51.043] <TB1> INFO: valid events with pixels: 242856
[19:39:51.043] <TB1> INFO: valid pixel hits: 1403340
[19:39:51.043] <TB1> INFO: Event errors: 0
[19:39:51.043] <TB1> INFO: start marker: 0
[19:39:51.043] <TB1> INFO: stop marker: 0
[19:39:51.043] <TB1> INFO: overflow: 0
[19:39:51.043] <TB1> INFO: invalid 5bit words: 0
[19:39:51.043] <TB1> INFO: invalid XOR eye diagram: 0
[19:39:51.043] <TB1> INFO: TBM errors: 0
[19:39:51.043] <TB1> INFO: flawed TBM headers: 0
[19:39:51.043] <TB1> INFO: flawed TBM trailers: 0
[19:39:51.043] <TB1> INFO: event ID mismatches: 0
[19:39:51.043] <TB1> INFO: ROC errors: 0
[19:39:51.043] <TB1> INFO: missing ROC header(s): 0
[19:39:51.043] <TB1> INFO: misplaced readback start: 0
[19:39:51.043] <TB1> INFO: Pixel decoding errors: 0
[19:39:51.043] <TB1> INFO: pixel data incomplete: 0
[19:39:51.043] <TB1> INFO: pixel address: 0
[19:39:51.043] <TB1> INFO: pulse height fill bit: 0
[19:39:51.043] <TB1> INFO: buffer corruption: 0
[19:39:51.043] <TB1> INFO: enter test to run
[19:39:51.043] <TB1> INFO: test: no parameter change
[19:39:51.288] <TB1> QUIET: Connection to board 129 closed.
[19:39:51.293] <TB1> INFO: pXar: this is the end, my friend