[13:51:21.513] <TB1> INFO: *** Welcome to pxar ***
[13:51:21.514] <TB1> INFO: *** Today: 2015/10/29
[13:51:21.527] <TB1> INFO: *** Version: 9da6-dirty
[13:51:21.527] <TB1> INFO: readRocDacs: /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C0.dat .. /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C15.dat
[13:51:21.528] <TB1> INFO: readTbmDacs: /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//tbmParameters_C0b.dat
[13:51:21.528] <TB1> INFO: readMaskFile: /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//defaultMaskFile.dat
[13:51:21.528] <TB1> INFO: readTrimFile: /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters_C0.dat .. /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters_C15.dat
[13:51:21.677] <TB1> INFO: clk: 4
[13:51:21.677] <TB1> INFO: ctr: 4
[13:51:21.677] <TB1> INFO: sda: 19
[13:51:21.678] <TB1> INFO: tin: 9
[13:51:21.678] <TB1> INFO: level: 15
[13:51:21.678] <TB1> INFO: triggerdelay: 0
[13:51:21.678] <TB1> QUIET: Instanciating API for pxar prod-11
[13:51:21.678] <TB1> INFO: Log level: INFO
[13:51:21.686] <TB1> INFO: Found DTB DTB_WWVH60
[13:51:21.694] <TB1> QUIET: Connection to board DTB_WWVH60 opened.
[13:51:21.699] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 129
HW version: DTB1.2
FW version: 4.2
SW version: 4.4
USB id: DTB_WWVH60
MAC address: 40D855118081
Hostname: pixelDTB129
Comment:
------------------------------------------------------
[13:51:21.702] <TB1> INFO: RPC call hashes of host and DTB match: 397073690
[13:51:23.404] <TB1> INFO: DUT info:
[13:51:23.404] <TB1> INFO: The DUT currently contains the following objects:
[13:51:23.404] <TB1> INFO: 2 TBM Cores tbm08c (2 ON)
[13:51:23.404] <TB1> INFO: TBM Core alpha (0): 7 registers set
[13:51:23.404] <TB1> INFO: TBM Core beta (1): 7 registers set
[13:51:23.404] <TB1> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[13:51:23.404] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.404] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.404] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.404] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.404] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.404] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.405] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.405] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.405] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.405] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.405] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.405] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.405] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.405] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.405] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.405] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:23.809] <TB1> INFO: enter 'restricted' command line mode
[13:51:23.809] <TB1> INFO: enter test to run
[13:51:23.809] <TB1> INFO: test: FullTest no parameter change
[13:51:23.809] <TB1> INFO: running: fulltest
[13:51:23.816] <TB1> INFO: ######################################################################
[13:51:23.816] <TB1> INFO: PixTestFullTest::doTest()
[13:51:23.816] <TB1> INFO: ######################################################################
[13:51:23.820] <TB1> INFO: ######################################################################
[13:51:23.820] <TB1> INFO: PixTestPretest::doTest()
[13:51:23.820] <TB1> INFO: ######################################################################
[13:51:23.822] <TB1> INFO: ----------------------------------------------------------------------
[13:51:23.822] <TB1> INFO: PixTestPretest::programROC()
[13:51:23.822] <TB1> INFO: ----------------------------------------------------------------------
[13:51:41.842] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:51:41.842] <TB1> INFO: IA differences per ROC: 16.1 15.3 17.7 17.7 18.5 19.3 19.3 19.3 17.7 16.1 16.9 16.9 16.1 16.9 17.7 17.7
[13:51:41.919] <TB1> INFO: ----------------------------------------------------------------------
[13:51:41.919] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:51:41.919] <TB1> INFO: ----------------------------------------------------------------------
[13:51:47.205] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 392.3 mA = 24.5187 mA/ROC
[13:51:47.207] <TB1> INFO: ----------------------------------------------------------------------
[13:51:47.207] <TB1> INFO: PixTestPretest::findTiming()
[13:51:47.207] <TB1> INFO: ----------------------------------------------------------------------
[13:51:47.207] <TB1> INFO: PixTestCmd::init()
[13:51:47.840] <TB1> WARNING: Not unmasking DUT, not setting Calibrate bits!
[13:53:21.182] <TB1> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):4, header/trailer: 1, token: 1
[13:53:21.183] <TB1> INFO: (success/tries = 100/100), width = 4
[13:53:21.186] <TB1> INFO: ----------------------------------------------------------------------
[13:53:21.186] <TB1> INFO: PixTestPretest::findWorkingPixel()
[13:53:21.186] <TB1> INFO: ----------------------------------------------------------------------
[13:53:21.333] <TB1> INFO: Expecting 231680 events.
[13:53:26.524] <TB1> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (1) != Token Chain Length (8)
[13:53:26.527] <TB1> ERROR: <datapipe.cc/CheckEventID:L457> Channel 0 Event ID mismatch: local ID (21) != TBM ID (2)
[13:53:29.410] <TB1> INFO: 231680 events read in total (7298ms).
[13:53:29.424] <TB1> INFO: Test took 8232ms.
[13:53:29.868] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[13:53:29.906] <TB1> INFO: ----------------------------------------------------------------------
[13:53:29.906] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[13:53:29.906] <TB1> INFO: ----------------------------------------------------------------------
[13:53:30.047] <TB1> INFO: Expecting 231680 events.
[13:53:38.159] <TB1> INFO: 231680 events read in total (7333ms).
[13:53:38.168] <TB1> INFO: Test took 8255ms.
[13:53:38.640] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[13:53:38.640] <TB1> INFO: CalDel: 116 123 133 133 123 143 126 126 107 136 125 119 139 121 124 131
[13:53:38.641] <TB1> INFO: VthrComp: 51 51 54 51 51 51 51 51 52 51 51 51 51 51 51 51
[13:53:38.645] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C0.dat
[13:53:38.646] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C1.dat
[13:53:38.646] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C2.dat
[13:53:38.646] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C3.dat
[13:53:38.647] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C4.dat
[13:53:38.647] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C5.dat
[13:53:38.647] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C6.dat
[13:53:38.647] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C7.dat
[13:53:38.648] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C8.dat
[13:53:38.648] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C9.dat
[13:53:38.648] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C10.dat
[13:53:38.648] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C11.dat
[13:53:38.648] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C12.dat
[13:53:38.648] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C13.dat
[13:53:38.648] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C14.dat
[13:53:38.648] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C15.dat
[13:53:38.649] <TB1> INFO: write tbm parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//tbmParameters_C0a.dat
[13:53:38.649] <TB1> INFO: write tbm parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//tbmParameters_C0b.dat
[13:53:38.649] <TB1> INFO: PixTestPretest::doTest() done, duration: 134 seconds
[13:53:38.649] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:53:38.649] <TB1> INFO: Decoding statistics:
[13:53:38.649] <TB1> INFO: General information:
[13:53:38.649] <TB1> INFO: 16bit words read: 7139972
[13:53:38.649] <TB1> INFO: valid events total: 463360
[13:53:38.649] <TB1> INFO: empty events: 303729
[13:53:38.649] <TB1> INFO: valid events with pixels: 159631
[13:53:38.649] <TB1> INFO: valid pixel hits: 789826
[13:53:38.649] <TB1> INFO: Event errors: 0
[13:53:38.649] <TB1> INFO: start marker: 0
[13:53:38.649] <TB1> INFO: stop marker: 0
[13:53:38.649] <TB1> INFO: overflow: 0
[13:53:38.649] <TB1> INFO: invalid 5bit words: 0
[13:53:38.649] <TB1> INFO: invalid XOR eye diagram: 0
[13:53:38.649] <TB1> INFO: TBM errors: 0
[13:53:38.649] <TB1> INFO: flawed TBM headers: 0
[13:53:38.649] <TB1> INFO: flawed TBM trailers: 0
[13:53:38.649] <TB1> INFO: event ID mismatches: 0
[13:53:38.649] <TB1> INFO: ROC errors: 0
[13:53:38.649] <TB1> INFO: missing ROC header(s): 0
[13:53:38.649] <TB1> INFO: misplaced readback start: 0
[13:53:38.649] <TB1> INFO: Pixel decoding errors: 0
[13:53:38.649] <TB1> INFO: pixel data incomplete: 0
[13:53:38.649] <TB1> INFO: pixel address: 0
[13:53:38.649] <TB1> INFO: pulse height fill bit: 0
[13:53:38.649] <TB1> INFO: buffer corruption: 0
[13:53:38.756] <TB1> INFO: ######################################################################
[13:53:38.756] <TB1> INFO: PixTestAlive::doTest()
[13:53:38.756] <TB1> INFO: ######################################################################
[13:53:38.757] <TB1> INFO: ----------------------------------------------------------------------
[13:53:38.757] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:53:38.757] <TB1> INFO: ----------------------------------------------------------------------
[13:53:39.108] <TB1> INFO: Expecting 41600 events.
[13:53:43.748] <TB1> INFO: 41600 events read in total (3861ms).
[13:53:43.751] <TB1> INFO: Test took 4990ms.
[13:53:43.763] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:53:44.190] <TB1> INFO: PixTestAlive::aliveTest() done
[13:53:44.190] <TB1> INFO: number of dead pixels (per ROC): 1 6 1 0 0 0 9 3 0 0 0 0 0 2 0 0
[13:53:44.192] <TB1> INFO: ----------------------------------------------------------------------
[13:53:44.192] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:53:44.192] <TB1> INFO: ----------------------------------------------------------------------
[13:53:44.541] <TB1> INFO: Expecting 41600 events.
[13:53:47.767] <TB1> INFO: 41600 events read in total (2447ms).
[13:53:47.767] <TB1> INFO: Test took 3572ms.
[13:53:47.767] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:53:47.768] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[13:53:48.236] <TB1> INFO: PixTestAlive::maskTest() done
[13:53:48.236] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:53:48.267] <TB1> INFO: ----------------------------------------------------------------------
[13:53:48.267] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:53:48.267] <TB1> INFO: ----------------------------------------------------------------------
[13:53:48.681] <TB1> INFO: Expecting 41600 events.
[13:53:53.284] <TB1> INFO: 41600 events read in total (3824ms).
[13:53:53.285] <TB1> INFO: Test took 5012ms.
[13:53:53.295] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:53:53.727] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[13:53:53.727] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:53:53.728] <TB1> INFO: PixTestAlive::doTest() done, duration: 14 seconds
[13:53:53.728] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:53:53.728] <TB1> INFO: Decoding statistics:
[13:53:53.728] <TB1> INFO: General information:
[13:53:53.728] <TB1> INFO: 16bit words read: 0
[13:53:53.728] <TB1> INFO: valid events total: 0
[13:53:53.728] <TB1> INFO: empty events: 0
[13:53:53.728] <TB1> INFO: valid events with pixels: 0
[13:53:53.729] <TB1> INFO: valid pixel hits: 0
[13:53:53.729] <TB1> INFO: Event errors: 0
[13:53:53.729] <TB1> INFO: start marker: 0
[13:53:53.729] <TB1> INFO: stop marker: 0
[13:53:53.729] <TB1> INFO: overflow: 0
[13:53:53.729] <TB1> INFO: invalid 5bit words: 0
[13:53:53.729] <TB1> INFO: invalid XOR eye diagram: 0
[13:53:53.729] <TB1> INFO: TBM errors: 0
[13:53:53.729] <TB1> INFO: flawed TBM headers: 0
[13:53:53.729] <TB1> INFO: flawed TBM trailers: 0
[13:53:53.729] <TB1> INFO: event ID mismatches: 0
[13:53:53.729] <TB1> INFO: ROC errors: 0
[13:53:53.729] <TB1> INFO: missing ROC header(s): 0
[13:53:53.729] <TB1> INFO: misplaced readback start: 0
[13:53:53.729] <TB1> INFO: Pixel decoding errors: 0
[13:53:53.729] <TB1> INFO: pixel data incomplete: 0
[13:53:53.729] <TB1> INFO: pixel address: 0
[13:53:53.729] <TB1> INFO: pulse height fill bit: 0
[13:53:53.729] <TB1> INFO: buffer corruption: 0
[13:53:53.753] <TB1> INFO: ######################################################################
[13:53:53.753] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[13:53:53.753] <TB1> INFO: ######################################################################
[13:53:53.756] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[13:53:53.826] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:53:53.826] <TB1> INFO: run 1 of 1
[13:53:54.252] <TB1> INFO: Expecting 3120000 events.
[13:54:46.773] <TB1> INFO: 1233610 events read in total (51742ms).
[13:55:38.432] <TB1> INFO: 2454050 events read in total (103401ms).
[13:56:06.595] <TB1> INFO: 3120000 events read in total (131565ms).
[13:56:06.674] <TB1> INFO: Test took 132848ms.
[13:56:06.797] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:57:12.702] <TB1> INFO: PixTestBBMap::doTest() done, duration: 198 seconds
[13:57:12.703] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0
[13:57:12.703] <TB1> INFO: separation cut (per ROC): 137 145 147 143 147 138 136 143 140 133 140 131 135 128 140 122
[13:57:12.703] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:57:12.703] <TB1> INFO: Decoding statistics:
[13:57:12.703] <TB1> INFO: General information:
[13:57:12.703] <TB1> INFO: 16bit words read: 0
[13:57:12.703] <TB1> INFO: valid events total: 0
[13:57:12.703] <TB1> INFO: empty events: 0
[13:57:12.703] <TB1> INFO: valid events with pixels: 0
[13:57:12.703] <TB1> INFO: valid pixel hits: 0
[13:57:12.703] <TB1> INFO: Event errors: 0
[13:57:12.703] <TB1> INFO: start marker: 0
[13:57:12.703] <TB1> INFO: stop marker: 0
[13:57:12.703] <TB1> INFO: overflow: 0
[13:57:12.703] <TB1> INFO: invalid 5bit words: 0
[13:57:12.703] <TB1> INFO: invalid XOR eye diagram: 0
[13:57:12.703] <TB1> INFO: TBM errors: 0
[13:57:12.703] <TB1> INFO: flawed TBM headers: 0
[13:57:12.703] <TB1> INFO: flawed TBM trailers: 0
[13:57:12.703] <TB1> INFO: event ID mismatches: 0
[13:57:12.703] <TB1> INFO: ROC errors: 0
[13:57:12.703] <TB1> INFO: missing ROC header(s): 0
[13:57:12.703] <TB1> INFO: misplaced readback start: 0
[13:57:12.703] <TB1> INFO: Pixel decoding errors: 0
[13:57:12.704] <TB1> INFO: pixel data incomplete: 0
[13:57:12.714] <TB1> INFO: pixel address: 0
[13:57:12.714] <TB1> INFO: pulse height fill bit: 0
[13:57:12.714] <TB1> INFO: buffer corruption: 0
[13:57:13.017] <TB1> INFO: ######################################################################
[13:57:13.017] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:57:13.025] <TB1> INFO: ######################################################################
[13:57:13.028] <TB1> INFO: ----------------------------------------------------------------------
[13:57:13.040] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:57:13.040] <TB1> INFO: ----------------------------------------------------------------------
[13:57:13.041] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:57:13.097] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[13:57:13.097] <TB1> INFO: run 1 of 1
[13:57:13.709] <TB1> INFO: Expecting 26208000 events.
[13:57:56.775] <TB1> INFO: 1255250 events read in total (42287ms).
[13:58:36.233] <TB1> INFO: 2483400 events read in total (81745ms).
[13:59:15.578] <TB1> INFO: 3711000 events read in total (121090ms).
[13:59:55.100] <TB1> INFO: 4935350 events read in total (160612ms).
[14:00:34.812] <TB1> INFO: 6161550 events read in total (200324ms).
[14:01:14.872] <TB1> INFO: 7382600 events read in total (240384ms).
[14:01:55.013] <TB1> INFO: 8604350 events read in total (280525ms).
[14:02:35.025] <TB1> INFO: 9828600 events read in total (320537ms).
[14:03:15.496] <TB1> INFO: 11048950 events read in total (361008ms).
[14:03:55.914] <TB1> INFO: 12267950 events read in total (401426ms).
[14:04:35.708] <TB1> INFO: 13474000 events read in total (441220ms).
[14:05:15.619] <TB1> INFO: 14672500 events read in total (481131ms).
[14:05:55.319] <TB1> INFO: 15870750 events read in total (520831ms).
[14:06:34.756] <TB1> INFO: 17065300 events read in total (560268ms).
[14:07:14.087] <TB1> INFO: 18260450 events read in total (599599ms).
[14:07:53.351] <TB1> INFO: 19448300 events read in total (638863ms).
[14:08:32.576] <TB1> INFO: 20638900 events read in total (678088ms).
[14:09:11.951] <TB1> INFO: 21833800 events read in total (717463ms).
[14:09:50.784] <TB1> INFO: 23023850 events read in total (756296ms).
[14:10:29.903] <TB1> INFO: 24220750 events read in total (795415ms).
[14:11:09.639] <TB1> INFO: 25419600 events read in total (835151ms).
[14:11:39.555] <TB1> INFO: 26208000 events read in total (865067ms).
[14:11:39.673] <TB1> INFO: Test took 866576ms.
[14:11:39.870] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:11:40.530] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:11:45.006] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:11:48.539] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:11:52.601] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:11:56.699] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:12:00.946] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:12:05.430] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:12:10.261] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:12:14.077] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:12:17.891] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:12:21.304] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:12:24.652] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:12:28.108] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:12:31.556] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:12:35.726] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:12:39.541] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:12:43.150] <TB1> INFO: PixTestScurves::scurves() done
[14:12:43.151] <TB1> INFO: Vcal mean: 101.19 108.13 118.50 109.18 113.43 105.70 103.22 107.73 114.44 101.38 112.86 100.65 103.17 103.47 111.24 103.63
[14:12:43.151] <TB1> INFO: Vcal RMS: 6.04 7.72 6.40 4.92 5.59 4.76 7.13 6.15 5.72 6.06 5.19 5.36 5.44 5.63 5.40 5.32
[14:12:43.151] <TB1> INFO: PixTestScurves::fullTest() done, duration: 930 seconds
[14:12:43.151] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:12:43.151] <TB1> INFO: Decoding statistics:
[14:12:43.151] <TB1> INFO: General information:
[14:12:43.151] <TB1> INFO: 16bit words read: 0
[14:12:43.151] <TB1> INFO: valid events total: 0
[14:12:43.151] <TB1> INFO: empty events: 0
[14:12:43.151] <TB1> INFO: valid events with pixels: 0
[14:12:43.151] <TB1> INFO: valid pixel hits: 0
[14:12:43.151] <TB1> INFO: Event errors: 0
[14:12:43.151] <TB1> INFO: start marker: 0
[14:12:43.151] <TB1> INFO: stop marker: 0
[14:12:43.152] <TB1> INFO: overflow: 0
[14:12:43.152] <TB1> INFO: invalid 5bit words: 0
[14:12:43.152] <TB1> INFO: invalid XOR eye diagram: 0
[14:12:43.152] <TB1> INFO: TBM errors: 0
[14:12:43.152] <TB1> INFO: flawed TBM headers: 0
[14:12:43.152] <TB1> INFO: flawed TBM trailers: 0
[14:12:43.152] <TB1> INFO: event ID mismatches: 0
[14:12:43.152] <TB1> INFO: ROC errors: 0
[14:12:43.152] <TB1> INFO: missing ROC header(s): 0
[14:12:43.152] <TB1> INFO: misplaced readback start: 0
[14:12:43.152] <TB1> INFO: Pixel decoding errors: 0
[14:12:43.152] <TB1> INFO: pixel data incomplete: 0
[14:12:43.155] <TB1> INFO: pixel address: 0
[14:12:43.155] <TB1> INFO: pulse height fill bit: 0
[14:12:43.155] <TB1> INFO: buffer corruption: 0
[14:12:43.301] <TB1> INFO: ######################################################################
[14:12:43.303] <TB1> INFO: PixTestTrim::doTest()
[14:12:43.303] <TB1> INFO: ######################################################################
[14:12:43.308] <TB1> INFO: ----------------------------------------------------------------------
[14:12:43.308] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[14:12:43.308] <TB1> INFO: ----------------------------------------------------------------------
[14:12:43.410] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:12:43.410] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:12:43.440] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:12:43.440] <TB1> INFO: run 1 of 1
[14:12:43.875] <TB1> INFO: Expecting 5025280 events.
[14:13:35.958] <TB1> INFO: 1432432 events read in total (51299ms).
[14:14:27.251] <TB1> INFO: 2856136 events read in total (102593ms).
[14:15:20.488] <TB1> INFO: 4271336 events read in total (155830ms).
[14:15:54.321] <TB1> INFO: 5025280 events read in total (189662ms).
[14:15:54.404] <TB1> INFO: Test took 190964ms.
[14:15:54.512] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:16:42.346] <TB1> INFO: ROC 0 VthrComp = 103
[14:16:42.358] <TB1> INFO: ROC 1 VthrComp = 106
[14:16:42.372] <TB1> INFO: ROC 2 VthrComp = 115
[14:16:42.378] <TB1> INFO: ROC 3 VthrComp = 112
[14:16:42.388] <TB1> INFO: ROC 4 VthrComp = 113
[14:16:42.388] <TB1> INFO: ROC 5 VthrComp = 108
[14:16:42.388] <TB1> INFO: ROC 6 VthrComp = 105
[14:16:42.389] <TB1> INFO: ROC 7 VthrComp = 109
[14:16:42.389] <TB1> INFO: ROC 8 VthrComp = 110
[14:16:42.389] <TB1> INFO: ROC 9 VthrComp = 100
[14:16:42.389] <TB1> INFO: ROC 10 VthrComp = 110
[14:16:42.390] <TB1> INFO: ROC 11 VthrComp = 103
[14:16:42.390] <TB1> INFO: ROC 12 VthrComp = 104
[14:16:42.390] <TB1> INFO: ROC 13 VthrComp = 102
[14:16:42.390] <TB1> INFO: ROC 14 VthrComp = 107
[14:16:42.390] <TB1> INFO: ROC 15 VthrComp = 101
[14:16:42.390] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:16:42.390] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:16:42.428] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:16:42.428] <TB1> INFO: run 1 of 1
[14:16:42.885] <TB1> INFO: Expecting 5025280 events.
[14:17:25.592] <TB1> INFO: 898456 events read in total (41925ms).
[14:18:07.464] <TB1> INFO: 1794672 events read in total (83797ms).
[14:18:49.096] <TB1> INFO: 2690024 events read in total (125429ms).
[14:19:31.536] <TB1> INFO: 3576368 events read in total (167869ms).
[14:20:20.381] <TB1> INFO: 4458448 events read in total (216714ms).
[14:20:48.420] <TB1> INFO: 5025280 events read in total (244753ms).
[14:20:48.618] <TB1> INFO: Test took 246191ms.
[14:20:49.007] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:21:47.551] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 61.7043 for pixel 3/28 mean/min/max = 47.1231/32.1849/62.0613
[14:21:47.552] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 65.6553 for pixel 5/9 mean/min/max = 49.4435/33.2242/65.6628
[14:21:47.552] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 68.0094 for pixel 36/5 mean/min/max = 51.8021/35.5174/68.0868
[14:21:47.553] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 59.3106 for pixel 24/52 mean/min/max = 46.4661/33.3489/59.5833
[14:21:47.554] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 62.4972 for pixel 47/79 mean/min/max = 48.2105/33.9113/62.5097
[14:21:47.554] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 58.7466 for pixel 51/19 mean/min/max = 46.7294/34.6294/58.8295
[14:21:47.555] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 59.7079 for pixel 51/0 mean/min/max = 46.5988/33.2682/59.9295
[14:21:47.555] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 62.7339 for pixel 3/77 mean/min/max = 48.4739/33.4606/63.4872
[14:21:47.556] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 67.9818 for pixel 6/79 mean/min/max = 52.0075/35.6455/68.3694
[14:21:47.557] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 62.8792 for pixel 4/74 mean/min/max = 47.3848/31.7744/62.9952
[14:21:47.559] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 62.8418 for pixel 0/78 mean/min/max = 48.679/34.4868/62.8711
[14:21:47.560] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 58.7734 for pixel 27/0 mean/min/max = 45.486/32.1348/58.8373
[14:21:47.561] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 61.1818 for pixel 15/11 mean/min/max = 47.3274/33.4706/61.1843
[14:21:47.562] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 60.4453 for pixel 18/1 mean/min/max = 46.923/33.3699/60.4761
[14:21:47.563] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 65.3637 for pixel 5/2 mean/min/max = 49.8377/34.0728/65.6026
[14:21:47.565] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 62.0003 for pixel 16/38 mean/min/max = 47.3591/32.6859/62.0322
[14:21:47.565] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:21:47.700] <TB1> INFO: Expecting 411648 events.
[14:21:56.881] <TB1> INFO: 411648 events read in total (8402ms).
[14:21:56.895] <TB1> INFO: Expecting 411648 events.
[14:22:05.958] <TB1> INFO: 411648 events read in total (8420ms).
[14:22:05.979] <TB1> INFO: Expecting 411648 events.
[14:22:14.967] <TB1> INFO: 411648 events read in total (8376ms).
[14:22:14.995] <TB1> INFO: Expecting 411648 events.
[14:22:24.011] <TB1> INFO: 411648 events read in total (8405ms).
[14:22:24.042] <TB1> INFO: Expecting 411648 events.
[14:22:32.981] <TB1> INFO: 411648 events read in total (8332ms).
[14:22:33.011] <TB1> INFO: Expecting 411648 events.
[14:22:41.912] <TB1> INFO: 411648 events read in total (8280ms).
[14:22:41.948] <TB1> INFO: Expecting 411648 events.
[14:22:50.933] <TB1> INFO: 411648 events read in total (8371ms).
[14:22:50.975] <TB1> INFO: Expecting 411648 events.
[14:23:00.078] <TB1> INFO: 411648 events read in total (8490ms).
[14:23:00.122] <TB1> INFO: Expecting 411648 events.
[14:23:08.977] <TB1> INFO: 411648 events read in total (8249ms).
[14:23:09.029] <TB1> INFO: Expecting 411648 events.
[14:23:18.228] <TB1> INFO: 411648 events read in total (8607ms).
[14:23:18.280] <TB1> INFO: Expecting 411648 events.
[14:23:27.403] <TB1> INFO: 411648 events read in total (8522ms).
[14:23:27.453] <TB1> INFO: Expecting 411648 events.
[14:23:36.543] <TB1> INFO: 411648 events read in total (8488ms).
[14:23:36.603] <TB1> INFO: Expecting 411648 events.
[14:23:45.404] <TB1> INFO: 411648 events read in total (8217ms).
[14:23:45.468] <TB1> INFO: Expecting 411648 events.
[14:23:54.587] <TB1> INFO: 411648 events read in total (8532ms).
[14:23:54.660] <TB1> INFO: Expecting 411648 events.
[14:24:03.904] <TB1> INFO: 411648 events read in total (8678ms).
[14:24:03.983] <TB1> INFO: Expecting 411648 events.
[14:24:13.297] <TB1> INFO: 411648 events read in total (8744ms).
[14:24:13.397] <TB1> INFO: Test took 145832ms.
[14:24:15.208] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:24:15.246] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:24:15.246] <TB1> INFO: run 1 of 1
[14:24:15.677] <TB1> INFO: Expecting 5025280 events.
[14:24:59.517] <TB1> INFO: 871744 events read in total (43062ms).
[14:25:42.660] <TB1> INFO: 1741640 events read in total (86205ms).
[14:26:26.095] <TB1> INFO: 2611360 events read in total (129641ms).
[14:27:11.721] <TB1> INFO: 3472560 events read in total (175266ms).
[14:27:57.220] <TB1> INFO: 4330368 events read in total (220765ms).
[14:28:39.545] <TB1> INFO: 5025280 events read in total (263090ms).
[14:28:39.722] <TB1> INFO: Test took 264476ms.
[14:28:40.094] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:29:31.887] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 0.078029 .. 255.000000
[14:29:31.991] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[14:29:32.020] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:29:32.020] <TB1> INFO: run 1 of 1
[14:29:32.450] <TB1> INFO: Expecting 8519680 events.
[14:30:13.434] <TB1> INFO: 826888 events read in total (40206ms).
[14:30:53.907] <TB1> INFO: 1653992 events read in total (80679ms).
[14:31:34.716] <TB1> INFO: 2481072 events read in total (121488ms).
[14:32:14.972] <TB1> INFO: 3308112 events read in total (161745ms).
[14:32:55.422] <TB1> INFO: 4135232 events read in total (202194ms).
[14:33:36.245] <TB1> INFO: 4962216 events read in total (243018ms).
[14:34:16.963] <TB1> INFO: 5788696 events read in total (283735ms).
[14:34:58.992] <TB1> INFO: 6614464 events read in total (325764ms).
[14:35:46.324] <TB1> INFO: 7440096 events read in total (373096ms).
[14:36:38.137] <TB1> INFO: 8266256 events read in total (424909ms).
[14:36:53.640] <TB1> INFO: 8519680 events read in total (440412ms).
[14:36:53.845] <TB1> INFO: Test took 441826ms.
[14:36:54.409] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:37:55.184] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 13.332950 .. 47.665824
[14:37:55.270] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 3 .. 57 (-1/-1) hits flags = 528 (plus default)
[14:37:55.298] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:37:55.298] <TB1> INFO: run 1 of 1
[14:37:55.726] <TB1> INFO: Expecting 1830400 events.
[14:38:48.011] <TB1> INFO: 1159360 events read in total (51494ms).
[14:39:18.934] <TB1> INFO: 1830400 events read in total (82417ms).
[14:39:18.983] <TB1> INFO: Test took 83686ms.
[14:39:19.058] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:39:48.230] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 19.353651 .. 43.769758
[14:39:48.343] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 9 .. 53 (-1/-1) hits flags = 528 (plus default)
[14:39:48.374] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:39:48.375] <TB1> INFO: run 1 of 1
[14:39:48.800] <TB1> INFO: Expecting 1497600 events.
[14:40:36.469] <TB1> INFO: 1159200 events read in total (46889ms).
[14:40:53.689] <TB1> INFO: 1497600 events read in total (64109ms).
[14:40:53.762] <TB1> INFO: Test took 65388ms.
[14:40:53.852] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:41:28.032] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 3.564957 .. 43.769758
[14:41:28.120] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 3 .. 53 (-1/-1) hits flags = 528 (plus default)
[14:41:28.147] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:41:28.147] <TB1> INFO: run 1 of 1
[14:41:28.549] <TB1> INFO: Expecting 1697280 events.
[14:42:18.799] <TB1> INFO: 1209416 events read in total (49471ms).
[14:42:41.909] <TB1> INFO: 1697280 events read in total (72581ms).
[14:42:41.965] <TB1> INFO: Test took 73818ms.
[14:42:42.028] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:43:15.752] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:43:15.753] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:43:15.802] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:43:15.809] <TB1> INFO: run 1 of 1
[14:43:16.270] <TB1> INFO: Expecting 1364480 events.
[14:44:02.311] <TB1> INFO: 1076456 events read in total (45263ms).
[14:44:15.839] <TB1> INFO: 1364480 events read in total (58791ms).
[14:44:15.879] <TB1> INFO: Test took 60060ms.
[14:44:15.947] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:44:43.975] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C0.dat
[14:44:43.975] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C1.dat
[14:44:43.975] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C2.dat
[14:44:43.975] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C3.dat
[14:44:43.976] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C4.dat
[14:44:43.976] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C5.dat
[14:44:43.976] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C6.dat
[14:44:43.976] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C7.dat
[14:44:43.976] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C8.dat
[14:44:43.976] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C9.dat
[14:44:43.976] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C10.dat
[14:44:43.976] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C11.dat
[14:44:43.977] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C12.dat
[14:44:43.977] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C13.dat
[14:44:43.977] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C14.dat
[14:44:43.977] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C15.dat
[14:44:43.992] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C0.dat
[14:44:44.015] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C1.dat
[14:44:44.032] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C2.dat
[14:44:44.055] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C3.dat
[14:44:44.082] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C4.dat
[14:44:44.098] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C5.dat
[14:44:44.109] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C6.dat
[14:44:44.145] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C7.dat
[14:44:44.169] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C8.dat
[14:44:44.180] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C9.dat
[14:44:44.214] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C10.dat
[14:44:44.238] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C11.dat
[14:44:44.249] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C12.dat
[14:44:44.286] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C13.dat
[14:44:44.314] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C14.dat
[14:44:44.330] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C15.dat
[14:44:44.361] <TB1> INFO: PixTestTrim::trimTest() done
[14:44:44.362] <TB1> INFO: vtrim: 117 141 146 197 110 93 92 119 124 119 123 95 119 112 136 112
[14:44:44.362] <TB1> INFO: vthrcomp: 103 106 115 112 113 108 105 109 110 100 110 103 104 102 107 101
[14:44:44.362] <TB1> INFO: vcal mean: 34.97 34.95 34.97 34.97 34.99 35.02 34.95 34.91 34.96 35.02 34.99 35.01 34.98 35.03 35.02 34.97
[14:44:44.362] <TB1> INFO: vcal RMS: 1.09 1.66 1.18 1.29 0.93 0.89 1.86 1.32 1.03 1.07 1.01 0.96 0.96 1.24 0.99 1.12
[14:44:44.362] <TB1> INFO: bits mean: 9.24 9.04 8.11 11.28 8.02 8.25 8.33 8.68 7.76 9.27 8.96 9.56 8.99 8.92 8.41 9.15
[14:44:44.362] <TB1> INFO: bits RMS: 2.63 2.45 2.36 1.66 2.81 2.73 2.93 2.62 2.45 2.69 2.40 2.70 2.59 2.68 2.56 2.58
[14:44:44.372] <TB1> INFO: ----------------------------------------------------------------------
[14:44:44.372] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:44:44.372] <TB1> INFO: ----------------------------------------------------------------------
[14:44:44.376] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:44:44.423] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:44:44.423] <TB1> INFO: run 1 of 1
[14:44:45.141] <TB1> INFO: Expecting 4160000 events.
[14:45:37.009] <TB1> INFO: 1250310 events read in total (51088ms).
[14:46:29.272] <TB1> INFO: 2485140 events read in total (103351ms).
[14:47:19.755] <TB1> INFO: 3707715 events read in total (153835ms).
[14:47:40.401] <TB1> INFO: 4160000 events read in total (174480ms).
[14:47:40.506] <TB1> INFO: Test took 176083ms.
[14:47:40.689] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:48:53.102] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 193 (-1/-1) hits flags = 528 (plus default)
[14:48:53.139] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:48:53.139] <TB1> INFO: run 1 of 1
[14:48:53.609] <TB1> INFO: Expecting 4035200 events.
[14:49:46.867] <TB1> INFO: 1212685 events read in total (52479ms).
[14:50:43.210] <TB1> INFO: 2411270 events read in total (108823ms).
[14:51:34.553] <TB1> INFO: 3597525 events read in total (160165ms).
[14:51:53.179] <TB1> INFO: 4035200 events read in total (178791ms).
[14:51:53.286] <TB1> INFO: Test took 180147ms.
[14:51:53.463] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:53:04.235] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 181 (-1/-1) hits flags = 528 (plus default)
[14:53:04.266] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:53:04.266] <TB1> INFO: run 1 of 1
[14:53:04.750] <TB1> INFO: Expecting 3785600 events.
[14:53:58.518] <TB1> INFO: 1261210 events read in total (52990ms).
[14:54:50.800] <TB1> INFO: 2503740 events read in total (105272ms).
[14:55:41.824] <TB1> INFO: 3738760 events read in total (156296ms).
[14:55:44.218] <TB1> INFO: 3785600 events read in total (158690ms).
[14:55:44.286] <TB1> INFO: Test took 160020ms.
[14:55:44.424] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:56:40.084] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 182 (-1/-1) hits flags = 528 (plus default)
[14:56:40.114] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:56:40.114] <TB1> INFO: run 1 of 1
[14:56:40.545] <TB1> INFO: Expecting 3806400 events.
[14:57:42.041] <TB1> INFO: 1255920 events read in total (60718ms).
[14:58:35.589] <TB1> INFO: 2493385 events read in total (114266ms).
[14:59:30.414] <TB1> INFO: 3721840 events read in total (169091ms).
[14:59:34.091] <TB1> INFO: 3806400 events read in total (172769ms).
[14:59:34.164] <TB1> INFO: Test took 174050ms.
[14:59:34.310] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:00:31.639] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 181 (-1/-1) hits flags = 528 (plus default)
[15:00:31.667] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:00:31.668] <TB1> INFO: run 1 of 1
[15:00:32.094] <TB1> INFO: Expecting 3785600 events.
[15:01:37.704] <TB1> INFO: 1259575 events read in total (64831ms).
[15:02:30.806] <TB1> INFO: 2500650 events read in total (117933ms).
[15:03:29.499] <TB1> INFO: 3734365 events read in total (176626ms).
[15:03:32.326] <TB1> INFO: 3785600 events read in total (179453ms).
[15:03:32.387] <TB1> INFO: Test took 180719ms.
[15:03:32.540] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:04:26.638] <TB1> INFO: PixTestTrim::trimBitTest() done
[15:04:26.643] <TB1> INFO: PixTestTrim::doTest() done, duration: 3103 seconds
[15:04:26.643] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:04:26.643] <TB1> INFO: Decoding statistics:
[15:04:26.643] <TB1> INFO: General information:
[15:04:26.643] <TB1> INFO: 16bit words read: 0
[15:04:26.643] <TB1> INFO: valid events total: 0
[15:04:26.644] <TB1> INFO: empty events: 0
[15:04:26.644] <TB1> INFO: valid events with pixels: 0
[15:04:26.644] <TB1> INFO: valid pixel hits: 0
[15:04:26.644] <TB1> INFO: Event errors: 0
[15:04:26.644] <TB1> INFO: start marker: 0
[15:04:26.644] <TB1> INFO: stop marker: 0
[15:04:26.644] <TB1> INFO: overflow: 0
[15:04:26.644] <TB1> INFO: invalid 5bit words: 0
[15:04:26.644] <TB1> INFO: invalid XOR eye diagram: 0
[15:04:26.644] <TB1> INFO: TBM errors: 0
[15:04:26.644] <TB1> INFO: flawed TBM headers: 0
[15:04:26.644] <TB1> INFO: flawed TBM trailers: 0
[15:04:26.644] <TB1> INFO: event ID mismatches: 0
[15:04:26.644] <TB1> INFO: ROC errors: 0
[15:04:26.644] <TB1> INFO: missing ROC header(s): 0
[15:04:26.644] <TB1> INFO: misplaced readback start: 0
[15:04:26.644] <TB1> INFO: Pixel decoding errors: 0
[15:04:26.644] <TB1> INFO: pixel data incomplete: 0
[15:04:26.644] <TB1> INFO: pixel address: 0
[15:04:26.644] <TB1> INFO: pulse height fill bit: 0
[15:04:26.644] <TB1> INFO: buffer corruption: 0
[15:04:28.004] <TB1> INFO: ######################################################################
[15:04:28.004] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[15:04:28.004] <TB1> INFO: ######################################################################
[15:04:28.400] <TB1> INFO: Expecting 41600 events.
[15:04:33.204] <TB1> INFO: 41600 events read in total (4026ms).
[15:04:33.210] <TB1> INFO: Test took 5198ms.
[15:04:33.223] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:04:33.973] <TB1> INFO: Expecting 41600 events.
[15:04:38.967] <TB1> INFO: 41600 events read in total (4216ms).
[15:04:38.968] <TB1> INFO: Test took 5365ms.
[15:04:38.983] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:04:39.424] <TB1> INFO: Expecting 41600 events.
[15:04:44.443] <TB1> INFO: 41600 events read in total (4239ms).
[15:04:44.446] <TB1> INFO: Test took 5440ms.
[15:04:44.461] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:04:44.866] <TB1> INFO: Expecting 2560 events.
[15:04:45.898] <TB1> INFO: 2560 events read in total (253ms).
[15:04:45.899] <TB1> INFO: Test took 1385ms.
[15:04:46.470] <TB1> INFO: Expecting 2560 events.
[15:04:47.499] <TB1> INFO: 2560 events read in total (249ms).
[15:04:47.499] <TB1> INFO: Test took 1600ms.
[15:04:48.074] <TB1> INFO: Expecting 2560 events.
[15:04:49.112] <TB1> INFO: 2560 events read in total (253ms).
[15:04:49.114] <TB1> INFO: Test took 1614ms.
[15:04:49.684] <TB1> INFO: Expecting 2560 events.
[15:04:50.713] <TB1> INFO: 2560 events read in total (251ms).
[15:04:50.713] <TB1> INFO: Test took 1592ms.
[15:04:51.291] <TB1> INFO: Expecting 2560 events.
[15:04:52.331] <TB1> INFO: 2560 events read in total (258ms).
[15:04:52.334] <TB1> INFO: Test took 1620ms.
[15:04:52.904] <TB1> INFO: Expecting 2560 events.
[15:04:53.937] <TB1> INFO: 2560 events read in total (254ms).
[15:04:53.937] <TB1> INFO: Test took 1596ms.
[15:04:54.509] <TB1> INFO: Expecting 2560 events.
[15:04:55.545] <TB1> INFO: 2560 events read in total (257ms).
[15:04:55.547] <TB1> INFO: Test took 1607ms.
[15:04:56.117] <TB1> INFO: Expecting 2560 events.
[15:04:57.151] <TB1> INFO: 2560 events read in total (256ms).
[15:04:57.152] <TB1> INFO: Test took 1599ms.
[15:04:57.725] <TB1> INFO: Expecting 2560 events.
[15:04:58.758] <TB1> INFO: 2560 events read in total (253ms).
[15:04:58.769] <TB1> INFO: Test took 1614ms.
[15:04:59.333] <TB1> INFO: Expecting 2560 events.
[15:05:00.363] <TB1> INFO: 2560 events read in total (252ms).
[15:05:00.369] <TB1> INFO: Test took 1595ms.
[15:05:00.938] <TB1> INFO: Expecting 2560 events.
[15:05:01.971] <TB1> INFO: 2560 events read in total (254ms).
[15:05:01.971] <TB1> INFO: Test took 1601ms.
[15:05:02.543] <TB1> INFO: Expecting 2560 events.
[15:05:03.573] <TB1> INFO: 2560 events read in total (251ms).
[15:05:03.574] <TB1> INFO: Test took 1603ms.
[15:05:04.152] <TB1> INFO: Expecting 2560 events.
[15:05:05.185] <TB1> INFO: 2560 events read in total (251ms).
[15:05:05.185] <TB1> INFO: Test took 1603ms.
[15:05:05.758] <TB1> INFO: Expecting 2560 events.
[15:05:06.787] <TB1> INFO: 2560 events read in total (249ms).
[15:05:06.788] <TB1> INFO: Test took 1602ms.
[15:05:07.360] <TB1> INFO: Expecting 2560 events.
[15:05:08.388] <TB1> INFO: 2560 events read in total (249ms).
[15:05:08.396] <TB1> INFO: Test took 1608ms.
[15:05:08.961] <TB1> INFO: Expecting 2560 events.
[15:05:09.993] <TB1> INFO: 2560 events read in total (254ms).
[15:05:09.001] <TB1> INFO: Test took 1598ms.
[15:05:10.011] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:05:10.567] <TB1> INFO: Expecting 655360 events.
[15:05:24.945] <TB1> INFO: 655360 events read in total (13591ms).
[15:05:25.034] <TB1> INFO: Expecting 655360 events.
[15:05:39.703] <TB1> INFO: 655360 events read in total (14131ms).
[15:05:39.743] <TB1> INFO: Expecting 655360 events.
[15:05:53.770] <TB1> INFO: 655360 events read in total (13499ms).
[15:05:53.817] <TB1> INFO: Expecting 655360 events.
[15:06:08.135] <TB1> INFO: 655360 events read in total (13792ms).
[15:06:08.192] <TB1> INFO: Expecting 655360 events.
[15:06:22.348] <TB1> INFO: 655360 events read in total (13629ms).
[15:06:22.396] <TB1> INFO: Expecting 655360 events.
[15:06:36.562] <TB1> INFO: 655360 events read in total (13639ms).
[15:06:36.617] <TB1> INFO: Expecting 655360 events.
[15:06:50.132] <TB1> INFO: 655360 events read in total (12988ms).
[15:06:50.204] <TB1> INFO: Expecting 655360 events.
[15:07:04.079] <TB1> INFO: 655360 events read in total (13348ms).
[15:07:04.151] <TB1> INFO: Expecting 655360 events.
[15:07:18.382] <TB1> INFO: 655360 events read in total (13704ms).
[15:07:18.523] <TB1> INFO: Expecting 655360 events.
[15:07:32.898] <TB1> INFO: 655360 events read in total (13845ms).
[15:07:33.051] <TB1> INFO: Expecting 655360 events.
[15:07:47.380] <TB1> INFO: 655360 events read in total (13803ms).
[15:07:47.473] <TB1> INFO: Expecting 655360 events.
[15:08:01.490] <TB1> INFO: 655360 events read in total (13490ms).
[15:08:01.588] <TB1> INFO: Expecting 655360 events.
[15:08:15.168] <TB1> INFO: 655360 events read in total (13053ms).
[15:08:15.289] <TB1> INFO: Expecting 655360 events.
[15:08:28.885] <TB1> INFO: 655360 events read in total (13065ms).
[15:08:28.985] <TB1> INFO: Expecting 655360 events.
[15:08:42.571] <TB1> INFO: 655360 events read in total (13057ms).
[15:08:42.729] <TB1> INFO: Expecting 655360 events.
[15:08:56.460] <TB1> INFO: 655360 events read in total (13204ms).
[15:08:56.608] <TB1> INFO: Test took 226597ms.
[15:08:56.779] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:08:57.138] <TB1> INFO: Expecting 655360 events.
[15:09:11.304] <TB1> INFO: 655360 events read in total (13388ms).
[15:09:11.324] <TB1> INFO: Expecting 655360 events.
[15:09:24.882] <TB1> INFO: 655360 events read in total (13029ms).
[15:09:24.905] <TB1> INFO: Expecting 655360 events.
[15:09:38.309] <TB1> INFO: 655360 events read in total (12877ms).
[15:09:38.343] <TB1> INFO: Expecting 655360 events.
[15:09:51.917] <TB1> INFO: 655360 events read in total (13045ms).
[15:09:51.961] <TB1> INFO: Expecting 655360 events.
[15:10:05.601] <TB1> INFO: 655360 events read in total (13113ms).
[15:10:05.652] <TB1> INFO: Expecting 655360 events.
[15:10:19.020] <TB1> INFO: 655360 events read in total (12841ms).
[15:10:19.086] <TB1> INFO: Expecting 655360 events.
[15:10:32.498] <TB1> INFO: 655360 events read in total (12886ms).
[15:10:32.565] <TB1> INFO: Expecting 655360 events.
[15:10:45.860] <TB1> INFO: 655360 events read in total (12768ms).
[15:10:45.936] <TB1> INFO: Expecting 655360 events.
[15:10:59.340] <TB1> INFO: 655360 events read in total (12877ms).
[15:10:59.421] <TB1> INFO: Expecting 655360 events.
[15:11:12.810] <TB1> INFO: 655360 events read in total (12863ms).
[15:11:12.902] <TB1> INFO: Expecting 655360 events.
[15:11:26.144] <TB1> INFO: 655360 events read in total (12716ms).
[15:11:26.246] <TB1> INFO: Expecting 655360 events.
[15:11:39.547] <TB1> INFO: 655360 events read in total (12771ms).
[15:11:39.652] <TB1> INFO: Expecting 655360 events.
[15:11:52.955] <TB1> INFO: 655360 events read in total (12777ms).
[15:11:53.061] <TB1> INFO: Expecting 655360 events.
[15:12:06.389] <TB1> INFO: 655360 events read in total (12801ms).
[15:12:06.513] <TB1> INFO: Expecting 655360 events.
[15:12:19.782] <TB1> INFO: 655360 events read in total (12742ms).
[15:12:19.924] <TB1> INFO: Expecting 655360 events.
[15:12:33.261] <TB1> INFO: 655360 events read in total (12809ms).
[15:12:33.402] <TB1> INFO: Test took 216623ms.
[15:12:33.742] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:33.756] <TB1> INFO: For ROC 0: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[15:12:33.760] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:12:33.774] <TB1> INFO: For ROC 0: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[15:12:33.778] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:12:33.792] <TB1> INFO: For ROC 0: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[15:12:33.795] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:12:33.810] <TB1> INFO: For ROC 0: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[15:12:33.815] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[15:12:33.828] <TB1> INFO: For ROC 0: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[15:12:33.833] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[15:12:33.847] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:33.860] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:33.874] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:33.889] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:33.904] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:33.919] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:33.933] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:33.947] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:33.962] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:33.977] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:33.991] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:34.006] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:34.022] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:34.037] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:34.051] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:12:34.098] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C0.dat
[15:12:34.099] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C1.dat
[15:12:34.100] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C2.dat
[15:12:34.100] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C3.dat
[15:12:34.100] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C4.dat
[15:12:34.100] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C5.dat
[15:12:34.102] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C6.dat
[15:12:34.104] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C7.dat
[15:12:34.105] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C8.dat
[15:12:34.105] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C9.dat
[15:12:34.105] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C10.dat
[15:12:34.106] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C11.dat
[15:12:34.107] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C12.dat
[15:12:34.108] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C13.dat
[15:12:34.109] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C14.dat
[15:12:34.110] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C15.dat
[15:12:34.488] <TB1> INFO: Expecting 41600 events.
[15:12:38.761] <TB1> INFO: 41600 events read in total (3495ms).
[15:12:38.762] <TB1> INFO: Test took 4648ms.
[15:12:39.452] <TB1> INFO: Expecting 41600 events.
[15:12:43.690] <TB1> INFO: 41600 events read in total (3456ms).
[15:12:43.694] <TB1> INFO: Test took 4606ms.
[15:12:44.368] <TB1> INFO: Expecting 41600 events.
[15:12:48.629] <TB1> INFO: 41600 events read in total (3482ms).
[15:12:48.631] <TB1> INFO: Test took 4609ms.
[15:12:48.984] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:12:49.118] <TB1> INFO: Expecting 2560 events.
[15:12:50.148] <TB1> INFO: 2560 events read in total (251ms).
[15:12:50.148] <TB1> INFO: Test took 1164ms.
[15:12:50.153] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:12:50.720] <TB1> INFO: Expecting 2560 events.
[15:12:51.749] <TB1> INFO: 2560 events read in total (250ms).
[15:12:51.751] <TB1> INFO: Test took 1598ms.
[15:12:51.754] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:12:52.322] <TB1> INFO: Expecting 2560 events.
[15:12:53.350] <TB1> INFO: 2560 events read in total (250ms).
[15:12:53.350] <TB1> INFO: Test took 1596ms.
[15:12:53.355] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:12:53.923] <TB1> INFO: Expecting 2560 events.
[15:12:54.951] <TB1> INFO: 2560 events read in total (249ms).
[15:12:54.951] <TB1> INFO: Test took 1596ms.
[15:12:54.957] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:12:55.525] <TB1> INFO: Expecting 2560 events.
[15:12:56.553] <TB1> INFO: 2560 events read in total (249ms).
[15:12:56.553] <TB1> INFO: Test took 1596ms.
[15:12:56.558] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:12:57.126] <TB1> INFO: Expecting 2560 events.
[15:12:58.154] <TB1> INFO: 2560 events read in total (250ms).
[15:12:58.154] <TB1> INFO: Test took 1596ms.
[15:12:58.160] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:12:58.726] <TB1> INFO: Expecting 2560 events.
[15:12:59.753] <TB1> INFO: 2560 events read in total (248ms).
[15:12:59.754] <TB1> INFO: Test took 1594ms.
[15:12:59.756] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:00.327] <TB1> INFO: Expecting 2560 events.
[15:13:01.353] <TB1> INFO: 2560 events read in total (248ms).
[15:13:01.354] <TB1> INFO: Test took 1598ms.
[15:13:01.360] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:01.926] <TB1> INFO: Expecting 2560 events.
[15:13:02.955] <TB1> INFO: 2560 events read in total (250ms).
[15:13:02.955] <TB1> INFO: Test took 1595ms.
[15:13:02.963] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:03.528] <TB1> INFO: Expecting 2560 events.
[15:13:04.556] <TB1> INFO: 2560 events read in total (250ms).
[15:13:04.556] <TB1> INFO: Test took 1593ms.
[15:13:04.562] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:05.131] <TB1> INFO: Expecting 2560 events.
[15:13:06.160] <TB1> INFO: 2560 events read in total (251ms).
[15:13:06.160] <TB1> INFO: Test took 1598ms.
[15:13:06.162] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:06.733] <TB1> INFO: Expecting 2560 events.
[15:13:07.761] <TB1> INFO: 2560 events read in total (250ms).
[15:13:07.762] <TB1> INFO: Test took 1600ms.
[15:13:07.768] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:08.337] <TB1> INFO: Expecting 2560 events.
[15:13:09.364] <TB1> INFO: 2560 events read in total (249ms).
[15:13:09.364] <TB1> INFO: Test took 1596ms.
[15:13:09.370] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:09.936] <TB1> INFO: Expecting 2560 events.
[15:13:10.963] <TB1> INFO: 2560 events read in total (248ms).
[15:13:10.964] <TB1> INFO: Test took 1594ms.
[15:13:10.969] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:11.537] <TB1> INFO: Expecting 2560 events.
[15:13:12.565] <TB1> INFO: 2560 events read in total (249ms).
[15:13:12.565] <TB1> INFO: Test took 1596ms.
[15:13:12.571] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:13.138] <TB1> INFO: Expecting 2560 events.
[15:13:14.166] <TB1> INFO: 2560 events read in total (249ms).
[15:13:14.167] <TB1> INFO: Test took 1596ms.
[15:13:14.172] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:14.739] <TB1> INFO: Expecting 2560 events.
[15:13:15.766] <TB1> INFO: 2560 events read in total (248ms).
[15:13:15.768] <TB1> INFO: Test took 1596ms.
[15:13:15.773] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:16.339] <TB1> INFO: Expecting 2560 events.
[15:13:17.367] <TB1> INFO: 2560 events read in total (249ms).
[15:13:17.368] <TB1> INFO: Test took 1595ms.
[15:13:17.374] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:17.942] <TB1> INFO: Expecting 2560 events.
[15:13:18.969] <TB1> INFO: 2560 events read in total (249ms).
[15:13:18.970] <TB1> INFO: Test took 1596ms.
[15:13:18.976] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:19.550] <TB1> INFO: Expecting 2560 events.
[15:13:20.578] <TB1> INFO: 2560 events read in total (249ms).
[15:13:20.578] <TB1> INFO: Test took 1602ms.
[15:13:20.584] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:21.151] <TB1> INFO: Expecting 2560 events.
[15:13:22.179] <TB1> INFO: 2560 events read in total (249ms).
[15:13:22.180] <TB1> INFO: Test took 1596ms.
[15:13:22.186] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:22.753] <TB1> INFO: Expecting 2560 events.
[15:13:23.781] <TB1> INFO: 2560 events read in total (249ms).
[15:13:23.781] <TB1> INFO: Test took 1595ms.
[15:13:23.787] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:24.354] <TB1> INFO: Expecting 2560 events.
[15:13:25.381] <TB1> INFO: 2560 events read in total (248ms).
[15:13:25.382] <TB1> INFO: Test took 1596ms.
[15:13:25.387] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:25.954] <TB1> INFO: Expecting 2560 events.
[15:13:26.981] <TB1> INFO: 2560 events read in total (249ms).
[15:13:26.981] <TB1> INFO: Test took 1595ms.
[15:13:26.986] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:27.554] <TB1> INFO: Expecting 2560 events.
[15:13:28.581] <TB1> INFO: 2560 events read in total (248ms).
[15:13:28.582] <TB1> INFO: Test took 1596ms.
[15:13:28.588] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:29.154] <TB1> INFO: Expecting 2560 events.
[15:13:30.181] <TB1> INFO: 2560 events read in total (249ms).
[15:13:30.182] <TB1> INFO: Test took 1594ms.
[15:13:30.188] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:30.755] <TB1> INFO: Expecting 2560 events.
[15:13:31.784] <TB1> INFO: 2560 events read in total (250ms).
[15:13:31.787] <TB1> INFO: Test took 1599ms.
[15:13:31.792] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:32.357] <TB1> INFO: Expecting 2560 events.
[15:13:33.388] <TB1> INFO: 2560 events read in total (252ms).
[15:13:33.388] <TB1> INFO: Test took 1597ms.
[15:13:33.391] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:33.961] <TB1> INFO: Expecting 2560 events.
[15:13:34.989] <TB1> INFO: 2560 events read in total (248ms).
[15:13:34.990] <TB1> INFO: Test took 1599ms.
[15:13:34.995] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:35.562] <TB1> INFO: Expecting 2560 events.
[15:13:36.589] <TB1> INFO: 2560 events read in total (248ms).
[15:13:36.590] <TB1> INFO: Test took 1595ms.
[15:13:36.597] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:37.163] <TB1> INFO: Expecting 2560 events.
[15:13:38.190] <TB1> INFO: 2560 events read in total (248ms).
[15:13:38.190] <TB1> INFO: Test took 1593ms.
[15:13:38.193] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:38.763] <TB1> INFO: Expecting 2560 events.
[15:13:39.794] <TB1> INFO: 2560 events read in total (252ms).
[15:13:39.794] <TB1> INFO: Test took 1601ms.
[15:13:40.579] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 552 seconds
[15:13:40.579] <TB1> INFO: PH scale (per ROC): 80 69 77 74 77 74 74 79 79 76 77 84 80 80 78 64
[15:13:40.579] <TB1> INFO: PH offset (per ROC): 156 170 163 163 161 156 161 159 162 166 173 148 155 159 162 163
[15:13:40.589] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:13:40.589] <TB1> INFO: Decoding statistics:
[15:13:40.589] <TB1> INFO: General information:
[15:13:40.589] <TB1> INFO: 16bit words read: 66442
[15:13:40.589] <TB1> INFO: valid events total: 5120
[15:13:40.589] <TB1> INFO: empty events: 2619
[15:13:40.589] <TB1> INFO: valid events with pixels: 2501
[15:13:40.589] <TB1> INFO: valid pixel hits: 2501
[15:13:40.589] <TB1> INFO: Event errors: 0
[15:13:40.589] <TB1> INFO: start marker: 0
[15:13:40.589] <TB1> INFO: stop marker: 0
[15:13:40.589] <TB1> INFO: overflow: 0
[15:13:40.589] <TB1> INFO: invalid 5bit words: 0
[15:13:40.589] <TB1> INFO: invalid XOR eye diagram: 0
[15:13:40.589] <TB1> INFO: TBM errors: 0
[15:13:40.589] <TB1> INFO: flawed TBM headers: 0
[15:13:40.589] <TB1> INFO: flawed TBM trailers: 0
[15:13:40.589] <TB1> INFO: event ID mismatches: 0
[15:13:40.589] <TB1> INFO: ROC errors: 0
[15:13:40.589] <TB1> INFO: missing ROC header(s): 0
[15:13:40.589] <TB1> INFO: misplaced readback start: 0
[15:13:40.589] <TB1> INFO: Pixel decoding errors: 0
[15:13:40.589] <TB1> INFO: pixel data incomplete: 0
[15:13:40.589] <TB1> INFO: pixel address: 0
[15:13:40.589] <TB1> INFO: pulse height fill bit: 0
[15:13:40.589] <TB1> INFO: buffer corruption: 0
[15:13:40.869] <TB1> INFO: ######################################################################
[15:13:40.869] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:13:40.869] <TB1> INFO: ######################################################################
[15:13:40.889] <TB1> INFO: scanning low vcal = 10
[15:13:41.232] <TB1> INFO: Expecting 41600 events.
[15:13:44.650] <TB1> INFO: 41600 events read in total (2640ms).
[15:13:44.650] <TB1> INFO: Test took 3761ms.
[15:13:44.653] <TB1> INFO: scanning low vcal = 20
[15:13:45.223] <TB1> INFO: Expecting 41600 events.
[15:13:48.665] <TB1> INFO: 41600 events read in total (2664ms).
[15:13:48.666] <TB1> INFO: Test took 4013ms.
[15:13:48.671] <TB1> INFO: scanning low vcal = 30
[15:13:49.238] <TB1> INFO: Expecting 41600 events.
[15:13:52.714] <TB1> INFO: 41600 events read in total (2697ms).
[15:13:52.715] <TB1> INFO: Test took 4044ms.
[15:13:52.720] <TB1> INFO: scanning low vcal = 40
[15:13:53.275] <TB1> INFO: Expecting 41600 events.
[15:13:57.247] <TB1> INFO: 41600 events read in total (3192ms).
[15:13:57.250] <TB1> INFO: Test took 4529ms.
[15:13:57.255] <TB1> INFO: scanning low vcal = 50
[15:13:57.710] <TB1> INFO: Expecting 41600 events.
[15:14:01.733] <TB1> INFO: 41600 events read in total (3244ms).
[15:14:01.736] <TB1> INFO: Test took 4481ms.
[15:14:01.742] <TB1> INFO: scanning low vcal = 60
[15:14:02.160] <TB1> INFO: Expecting 41600 events.
[15:14:06.189] <TB1> INFO: 41600 events read in total (3250ms).
[15:14:06.190] <TB1> INFO: Test took 4447ms.
[15:14:06.195] <TB1> INFO: scanning low vcal = 70
[15:14:06.643] <TB1> INFO: Expecting 41600 events.
[15:14:10.688] <TB1> INFO: 41600 events read in total (3264ms).
[15:14:10.690] <TB1> INFO: Test took 4495ms.
[15:14:10.696] <TB1> INFO: scanning low vcal = 80
[15:14:11.119] <TB1> INFO: Expecting 41600 events.
[15:14:15.155] <TB1> INFO: 41600 events read in total (3257ms).
[15:14:15.157] <TB1> INFO: Test took 4461ms.
[15:14:15.161] <TB1> INFO: scanning low vcal = 90
[15:14:15.590] <TB1> INFO: Expecting 41600 events.
[15:14:19.671] <TB1> INFO: 41600 events read in total (3302ms).
[15:14:19.673] <TB1> INFO: Test took 4512ms.
[15:14:19.681] <TB1> INFO: scanning low vcal = 100
[15:14:20.136] <TB1> INFO: Expecting 41600 events.
[15:14:24.111] <TB1> INFO: 41600 events read in total (3196ms).
[15:14:24.113] <TB1> INFO: Test took 4431ms.
[15:14:24.118] <TB1> INFO: scanning low vcal = 110
[15:14:24.596] <TB1> INFO: Expecting 41600 events.
[15:14:28.571] <TB1> INFO: 41600 events read in total (3197ms).
[15:14:28.573] <TB1> INFO: Test took 4455ms.
[15:14:28.579] <TB1> INFO: scanning low vcal = 120
[15:14:29.072] <TB1> INFO: Expecting 41600 events.
[15:14:33.063] <TB1> INFO: 41600 events read in total (3213ms).
[15:14:33.064] <TB1> INFO: Test took 4485ms.
[15:14:33.069] <TB1> INFO: scanning low vcal = 130
[15:14:33.540] <TB1> INFO: Expecting 41600 events.
[15:14:37.523] <TB1> INFO: 41600 events read in total (3204ms).
[15:14:37.524] <TB1> INFO: Test took 4455ms.
[15:14:37.530] <TB1> INFO: scanning low vcal = 140
[15:14:38.008] <TB1> INFO: Expecting 41600 events.
[15:14:42.013] <TB1> INFO: 41600 events read in total (3227ms).
[15:14:42.014] <TB1> INFO: Test took 4483ms.
[15:14:42.019] <TB1> INFO: scanning low vcal = 150
[15:14:42.483] <TB1> INFO: Expecting 41600 events.
[15:14:46.485] <TB1> INFO: 41600 events read in total (3223ms).
[15:14:46.490] <TB1> INFO: Test took 4471ms.
[15:14:46.494] <TB1> INFO: scanning low vcal = 160
[15:14:46.955] <TB1> INFO: Expecting 41600 events.
[15:14:50.965] <TB1> INFO: 41600 events read in total (3230ms).
[15:14:50.967] <TB1> INFO: Test took 4472ms.
[15:14:50.972] <TB1> INFO: scanning low vcal = 170
[15:14:51.423] <TB1> INFO: Expecting 41600 events.
[15:14:55.458] <TB1> INFO: 41600 events read in total (3257ms).
[15:14:55.460] <TB1> INFO: Test took 4488ms.
[15:14:55.470] <TB1> INFO: scanning low vcal = 180
[15:14:55.895] <TB1> INFO: Expecting 41600 events.
[15:14:59.908] <TB1> INFO: 41600 events read in total (3235ms).
[15:14:59.911] <TB1> INFO: Test took 4441ms.
[15:14:59.917] <TB1> INFO: scanning low vcal = 190
[15:15:00.369] <TB1> INFO: Expecting 41600 events.
[15:15:04.440] <TB1> INFO: 41600 events read in total (3293ms).
[15:15:04.443] <TB1> INFO: Test took 4526ms.
[15:15:04.448] <TB1> INFO: scanning low vcal = 200
[15:15:04.914] <TB1> INFO: Expecting 41600 events.
[15:15:09.028] <TB1> INFO: 41600 events read in total (3336ms).
[15:15:09.030] <TB1> INFO: Test took 4582ms.
[15:15:09.043] <TB1> INFO: scanning low vcal = 210
[15:15:09.578] <TB1> INFO: Expecting 41600 events.
[15:15:13.794] <TB1> INFO: 41600 events read in total (3438ms).
[15:15:13.796] <TB1> INFO: Test took 4753ms.
[15:15:13.801] <TB1> INFO: scanning low vcal = 220
[15:15:14.220] <TB1> INFO: Expecting 41600 events.
[15:15:18.249] <TB1> INFO: 41600 events read in total (3250ms).
[15:15:18.250] <TB1> INFO: Test took 4449ms.
[15:15:18.258] <TB1> INFO: scanning low vcal = 230
[15:15:18.680] <TB1> INFO: Expecting 41600 events.
[15:15:22.659] <TB1> INFO: 41600 events read in total (3200ms).
[15:15:22.660] <TB1> INFO: Test took 4402ms.
[15:15:22.667] <TB1> INFO: scanning low vcal = 240
[15:15:23.143] <TB1> INFO: Expecting 41600 events.
[15:15:27.181] <TB1> INFO: 41600 events read in total (3260ms).
[15:15:27.182] <TB1> INFO: Test took 4515ms.
[15:15:27.186] <TB1> INFO: scanning low vcal = 250
[15:15:27.612] <TB1> INFO: Expecting 41600 events.
[15:15:31.583] <TB1> INFO: 41600 events read in total (3192ms).
[15:15:31.585] <TB1> INFO: Test took 4399ms.
[15:15:31.594] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[15:15:32.066] <TB1> INFO: Expecting 41600 events.
[15:15:36.035] <TB1> INFO: 41600 events read in total (3190ms).
[15:15:36.036] <TB1> INFO: Test took 4442ms.
[15:15:36.042] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[15:15:36.529] <TB1> INFO: Expecting 41600 events.
[15:15:40.548] <TB1> INFO: 41600 events read in total (3241ms).
[15:15:40.550] <TB1> INFO: Test took 4507ms.
[15:15:40.559] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[15:15:40.992] <TB1> INFO: Expecting 41600 events.
[15:15:45.017] <TB1> INFO: 41600 events read in total (3246ms).
[15:15:45.019] <TB1> INFO: Test took 4460ms.
[15:15:45.027] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[15:15:45.452] <TB1> INFO: Expecting 41600 events.
[15:15:49.563] <TB1> INFO: 41600 events read in total (3332ms).
[15:15:49.565] <TB1> INFO: Test took 4538ms.
[15:15:49.574] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:15:50.015] <TB1> INFO: Expecting 41600 events.
[15:15:54.059] <TB1> INFO: 41600 events read in total (3265ms).
[15:15:54.060] <TB1> INFO: Test took 4484ms.
[15:15:55.012] <TB1> INFO: PixTestGainPedestal::measure() done
[15:17:09.343] <TB1> INFO: PixTestGainPedestal::fit() done
[15:17:09.343] <TB1> INFO: non-linearity mean: 0.959 0.953 0.954 0.955 0.959 0.953 0.959 0.961 0.955 0.951 0.956 0.954 0.954 0.956 0.959 0.961
[15:17:09.343] <TB1> INFO: non-linearity RMS: 0.004 0.006 0.006 0.005 0.005 0.006 0.006 0.006 0.006 0.006 0.005 0.006 0.006 0.006 0.005 0.006
[15:17:09.343] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[15:17:09.384] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[15:17:09.421] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[15:17:09.463] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[15:17:09.501] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[15:17:09.537] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[15:17:09.574] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[15:17:09.613] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[15:17:09.649] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[15:17:09.683] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[15:17:09.717] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[15:17:09.751] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[15:17:09.792] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[15:17:09.839] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[15:17:09.875] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[15:17:09.904] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[15:17:09.928] <TB1> INFO: PixTestGainPedestal::doTest() done, duration: 209 seconds
[15:17:09.928] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:17:09.928] <TB1> INFO: Decoding statistics:
[15:17:09.928] <TB1> INFO: General information:
[15:17:09.928] <TB1> INFO: 16bit words read: 2327726
[15:17:09.928] <TB1> INFO: valid events total: 83200
[15:17:09.928] <TB1> INFO: empty events: 0
[15:17:09.928] <TB1> INFO: valid events with pixels: 83200
[15:17:09.929] <TB1> INFO: valid pixel hits: 664663
[15:17:09.929] <TB1> INFO: Event errors: 0
[15:17:09.929] <TB1> INFO: start marker: 0
[15:17:09.929] <TB1> INFO: stop marker: 0
[15:17:09.929] <TB1> INFO: overflow: 0
[15:17:09.929] <TB1> INFO: invalid 5bit words: 0
[15:17:09.929] <TB1> INFO: invalid XOR eye diagram: 0
[15:17:09.929] <TB1> INFO: TBM errors: 0
[15:17:09.929] <TB1> INFO: flawed TBM headers: 0
[15:17:09.929] <TB1> INFO: flawed TBM trailers: 0
[15:17:09.929] <TB1> INFO: event ID mismatches: 0
[15:17:09.929] <TB1> INFO: ROC errors: 0
[15:17:09.929] <TB1> INFO: missing ROC header(s): 0
[15:17:09.929] <TB1> INFO: misplaced readback start: 0
[15:17:09.929] <TB1> INFO: Pixel decoding errors: 0
[15:17:09.929] <TB1> INFO: pixel data incomplete: 0
[15:17:09.929] <TB1> INFO: pixel address: 0
[15:17:09.929] <TB1> INFO: pulse height fill bit: 0
[15:17:09.929] <TB1> INFO: buffer corruption: 0
[15:17:09.942] <TB1> INFO: readReadbackCal: /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C0.dat .. /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C15.dat
[15:17:09.956] <TB1> INFO: ######################################################################
[15:17:09.956] <TB1> INFO: PixTestTrim::doTest()
[15:17:09.956] <TB1> INFO: ######################################################################
[15:17:09.959] <TB1> INFO: PixTestReadback::RES sent once
[15:17:23.368] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C0.dat
[15:17:23.371] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C1.dat
[15:17:23.375] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C2.dat
[15:17:23.385] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C3.dat
[15:17:23.388] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C4.dat
[15:17:23.392] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C5.dat
[15:17:23.401] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C6.dat
[15:17:23.404] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C7.dat
[15:17:23.412] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C8.dat
[15:17:23.416] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C9.dat
[15:17:23.419] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C10.dat
[15:17:23.426] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C11.dat
[15:17:23.427] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C12.dat
[15:17:23.435] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C13.dat
[15:17:23.439] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C14.dat
[15:17:23.442] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C15.dat
[15:17:23.544] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[15:17:23.548] <TB1> INFO: PixTestReadback::RES sent once
[15:17:36.623] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C0.dat
[15:17:36.623] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C1.dat
[15:17:36.623] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C2.dat
[15:17:36.624] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C3.dat
[15:17:36.624] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C4.dat
[15:17:36.624] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C5.dat
[15:17:36.625] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C6.dat
[15:17:36.625] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C7.dat
[15:17:36.625] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C8.dat
[15:17:36.625] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C9.dat
[15:17:36.625] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C10.dat
[15:17:36.625] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C11.dat
[15:17:36.625] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C12.dat
[15:17:36.625] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C13.dat
[15:17:36.626] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C14.dat
[15:17:36.626] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C15.dat
[15:17:36.682] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[15:17:36.683] <TB1> INFO: PixTestReadback::RES sent once
[15:17:46.608] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[15:17:46.608] <TB1> INFO: Vbg will be calibrated using Vd calibration
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 158.2calibrated Vbg = 1.18416 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 162.5calibrated Vbg = 1.18754 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 153.9calibrated Vbg = 1.19111 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 154.3calibrated Vbg = 1.19178 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 154.7calibrated Vbg = 1.2034 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 154.1calibrated Vbg = 1.20151 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 155calibrated Vbg = 1.20843 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 153.9calibrated Vbg = 1.20155 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 150.4calibrated Vbg = 1.20234 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 152.9calibrated Vbg = 1.19916 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 167calibrated Vbg = 1.20016 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 146calibrated Vbg = 1.19924 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 155.4calibrated Vbg = 1.19798 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 162.4calibrated Vbg = 1.19715 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 159.1calibrated Vbg = 1.19124 :::*/*/*/*/
[15:17:46.608] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 155calibrated Vbg = 1.19568 :::*/*/*/*/
[15:17:46.614] <TB1> INFO: PixTestReadback::RES sent once
[15:20:58.799] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C0.dat
[15:20:58.799] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C1.dat
[15:20:58.800] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C2.dat
[15:20:58.800] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C3.dat
[15:20:58.800] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C4.dat
[15:20:58.800] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C5.dat
[15:20:58.800] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C6.dat
[15:20:58.801] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C7.dat
[15:20:58.801] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C8.dat
[15:20:58.801] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C9.dat
[15:20:58.801] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C10.dat
[15:20:58.801] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C11.dat
[15:20:58.801] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C12.dat
[15:20:58.801] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C13.dat
[15:20:58.802] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C14.dat
[15:20:58.802] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3513_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C15.dat
[15:20:58.840] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[15:20:58.842] <TB1> INFO: PixTestReadback::doTest() done
[15:20:58.842] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:20:58.842] <TB1> INFO: Decoding statistics:
[15:20:58.842] <TB1> INFO: General information:
[15:20:58.842] <TB1> INFO: 16bit words read: 768
[15:20:58.842] <TB1> INFO: valid events total: 64
[15:20:58.842] <TB1> INFO: empty events: 64
[15:20:58.842] <TB1> INFO: valid events with pixels: 0
[15:20:58.842] <TB1> INFO: valid pixel hits: 0
[15:20:58.842] <TB1> INFO: Event errors: 0
[15:20:58.842] <TB1> INFO: start marker: 0
[15:20:58.842] <TB1> INFO: stop marker: 0
[15:20:58.842] <TB1> INFO: overflow: 0
[15:20:58.842] <TB1> INFO: invalid 5bit words: 0
[15:20:58.842] <TB1> INFO: invalid XOR eye diagram: 0
[15:20:58.842] <TB1> INFO: TBM errors: 0
[15:20:58.842] <TB1> INFO: flawed TBM headers: 0
[15:20:58.842] <TB1> INFO: flawed TBM trailers: 0
[15:20:58.842] <TB1> INFO: event ID mismatches: 0
[15:20:58.842] <TB1> INFO: ROC errors: 0
[15:20:58.842] <TB1> INFO: missing ROC header(s): 0
[15:20:58.842] <TB1> INFO: misplaced readback start: 0
[15:20:58.842] <TB1> INFO: Pixel decoding errors: 0
[15:20:58.842] <TB1> INFO: pixel data incomplete: 0
[15:20:58.842] <TB1> INFO: pixel address: 0
[15:20:58.842] <TB1> INFO: pulse height fill bit: 0
[15:20:58.842] <TB1> INFO: buffer corruption: 0
[15:20:58.922] <TB1> INFO: Decoding statistics:
[15:20:58.922] <TB1> INFO: General information:
[15:20:58.922] <TB1> INFO: 16bit words read: 9534908
[15:20:58.922] <TB1> INFO: valid events total: 551744
[15:20:58.922] <TB1> INFO: empty events: 306412
[15:20:58.922] <TB1> INFO: valid events with pixels: 245332
[15:20:58.922] <TB1> INFO: valid pixel hits: 1456990
[15:20:58.922] <TB1> INFO: Event errors: 0
[15:20:58.922] <TB1> INFO: start marker: 0
[15:20:58.922] <TB1> INFO: stop marker: 0
[15:20:58.922] <TB1> INFO: overflow: 0
[15:20:58.922] <TB1> INFO: invalid 5bit words: 0
[15:20:58.922] <TB1> INFO: invalid XOR eye diagram: 0
[15:20:58.922] <TB1> INFO: TBM errors: 0
[15:20:58.922] <TB1> INFO: flawed TBM headers: 0
[15:20:58.922] <TB1> INFO: flawed TBM trailers: 0
[15:20:58.922] <TB1> INFO: event ID mismatches: 0
[15:20:58.922] <TB1> INFO: ROC errors: 0
[15:20:58.922] <TB1> INFO: missing ROC header(s): 0
[15:20:58.922] <TB1> INFO: misplaced readback start: 0
[15:20:58.922] <TB1> INFO: Pixel decoding errors: 0
[15:20:58.922] <TB1> INFO: pixel data incomplete: 0
[15:20:58.922] <TB1> INFO: pixel address: 0
[15:20:58.922] <TB1> INFO: pulse height fill bit: 0
[15:20:58.922] <TB1> INFO: buffer corruption: 0
[15:20:58.930] <TB1> INFO: enter test to run
[15:20:58.930] <TB1> INFO: test: no parameter change
[15:20:59.294] <TB1> QUIET: Connection to board 129 closed.
[15:20:59.303] <TB1> INFO: pXar: this is the end, my friend