[13:51:11.591] <TB0> INFO: *** Welcome to pxar ***
[13:51:11.591] <TB0> INFO: *** Today: 2015/10/29
[13:51:11.603] <TB0> INFO: *** Version: 9da6-dirty
[13:51:11.603] <TB0> INFO: readRocDacs: /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C0.dat .. /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C15.dat
[13:51:11.604] <TB0> INFO: readTbmDacs: /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//tbmParameters_C0b.dat
[13:51:11.604] <TB0> INFO: readMaskFile: /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//defaultMaskFile.dat
[13:51:11.604] <TB0> INFO: readTrimFile: /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters_C0.dat .. /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters_C15.dat
[13:51:11.701] <TB0> INFO: clk: 4
[13:51:11.701] <TB0> INFO: ctr: 4
[13:51:11.701] <TB0> INFO: sda: 19
[13:51:11.701] <TB0> INFO: tin: 9
[13:51:11.701] <TB0> INFO: level: 15
[13:51:11.701] <TB0> INFO: triggerdelay: 0
[13:51:11.701] <TB0> QUIET: Instanciating API for pxar prod-11
[13:51:11.701] <TB0> INFO: Log level: INFO
[13:51:11.709] <TB0> INFO: Found DTB DTB_WWVBIQ
[13:51:11.716] <TB0> QUIET: Connection to board DTB_WWVBIQ opened.
[13:51:11.720] <TB0> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 127
HW version: DTB1.2
FW version: 4.2
SW version: 4.4
USB id: DTB_WWVBIQ
MAC address: 40D85511807F
Hostname: pixelDTB127
Comment:
------------------------------------------------------
[13:51:11.724] <TB0> INFO: RPC call hashes of host and DTB match: 397073690
[13:51:13.270] <TB0> INFO: DUT info:
[13:51:13.270] <TB0> INFO: The DUT currently contains the following objects:
[13:51:13.270] <TB0> INFO: 2 TBM Cores tbm08c (2 ON)
[13:51:13.270] <TB0> INFO: TBM Core alpha (0): 7 registers set
[13:51:13.270] <TB0> INFO: TBM Core beta (1): 7 registers set
[13:51:13.270] <TB0> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[13:51:13.270] <TB0> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.270] <TB0> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.270] <TB0> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.270] <TB0> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.270] <TB0> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.270] <TB0> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.270] <TB0> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.270] <TB0> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.270] <TB0> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.270] <TB0> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.270] <TB0> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.270] <TB0> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.270] <TB0> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.270] <TB0> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.270] <TB0> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.271] <TB0> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:51:13.674] <TB0> INFO: enter 'restricted' command line mode
[13:51:13.674] <TB0> INFO: enter test to run
[13:51:13.674] <TB0> INFO: test: FullTest no parameter change
[13:51:13.674] <TB0> INFO: running: fulltest
[13:51:13.678] <TB0> INFO: ######################################################################
[13:51:13.678] <TB0> INFO: PixTestFullTest::doTest()
[13:51:13.678] <TB0> INFO: ######################################################################
[13:51:13.682] <TB0> INFO: ######################################################################
[13:51:13.682] <TB0> INFO: PixTestPretest::doTest()
[13:51:13.682] <TB0> INFO: ######################################################################
[13:51:13.684] <TB0> INFO: ----------------------------------------------------------------------
[13:51:13.684] <TB0> INFO: PixTestPretest::programROC()
[13:51:13.684] <TB0> INFO: ----------------------------------------------------------------------
[13:51:31.703] <TB0> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:51:31.703] <TB0> INFO: IA differences per ROC: 16.1 16.1 17.7 16.9 15.3 15.3 15.3 14.5 18.5 14.5 16.9 16.9 17.7 16.9 16.1 16.9
[13:51:31.779] <TB0> INFO: ----------------------------------------------------------------------
[13:51:31.779] <TB0> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:51:31.779] <TB0> INFO: ----------------------------------------------------------------------
[13:51:51.357] <TB0> INFO: PixTestPretest::setVana() done, Module Ia 388.3 mA = 24.2687 mA/ROC
[13:51:51.358] <TB0> INFO: ----------------------------------------------------------------------
[13:51:51.359] <TB0> INFO: PixTestPretest::findTiming()
[13:51:51.359] <TB0> INFO: ----------------------------------------------------------------------
[13:51:51.359] <TB0> INFO: PixTestCmd::init()
[13:51:51.963] <TB0> WARNING: Not unmasking DUT, not setting Calibrate bits!
[13:53:40.837] <TB0> INFO: TBM phases: 160MHz: 4, 400MHz: 6, TBM delays: ROC(0/1):3, header/trailer: 1, token: 0
[13:53:40.837] <TB0> INFO: (success/tries = 100/100), width = 4
[13:53:40.841] <TB0> INFO: ----------------------------------------------------------------------
[13:53:40.841] <TB0> INFO: PixTestPretest::findWorkingPixel()
[13:53:40.841] <TB0> INFO: ----------------------------------------------------------------------
[13:53:40.984] <TB0> INFO: Expecting 231680 events.
[13:53:45.668] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (1) != Token Chain Length (8)
[13:53:45.672] <TB0> ERROR: <datapipe.cc/CheckEventID:L457> Channel 0 Event ID mismatch: local ID (21) != TBM ID (2)
[13:53:48.720] <TB0> INFO: 231680 events read in total (7020ms).
[13:53:48.730] <TB0> INFO: Test took 7884ms.
[13:53:49.100] <TB0> INFO: Found working pixel in all ROCs: col/row = 12/22
[13:53:49.145] <TB0> INFO: ----------------------------------------------------------------------
[13:53:49.145] <TB0> INFO: PixTestPretest::setVthrCompCalDel()
[13:53:49.145] <TB0> INFO: ----------------------------------------------------------------------
[13:53:49.291] <TB0> INFO: Expecting 231680 events.
[13:53:56.971] <TB0> INFO: 231680 events read in total (6965ms).
[13:53:56.982] <TB0> INFO: Test took 7828ms.
[13:53:57.369] <TB0> INFO: PixTestPretest::setVthrCompCalDel() done
[13:53:57.370] <TB0> INFO: CalDel: 101 125 154 129 124 87 118 118 125 143 123 124 135 138 129 110
[13:53:57.370] <TB0> INFO: VthrComp: 52 51 56 52 52 52 51 51 51 52 51 53 55 52 51 62
[13:53:57.376] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C0.dat
[13:53:57.376] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C1.dat
[13:53:57.376] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C2.dat
[13:53:57.377] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C3.dat
[13:53:57.377] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C4.dat
[13:53:57.377] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C5.dat
[13:53:57.377] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C6.dat
[13:53:57.377] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C7.dat
[13:53:57.378] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C8.dat
[13:53:57.378] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C9.dat
[13:53:57.378] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C10.dat
[13:53:57.378] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C11.dat
[13:53:57.378] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C12.dat
[13:53:57.379] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C13.dat
[13:53:57.379] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C14.dat
[13:53:57.379] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters_C15.dat
[13:53:57.379] <TB0> INFO: write tbm parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//tbmParameters_C0a.dat
[13:53:57.379] <TB0> INFO: write tbm parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//tbmParameters_C0b.dat
[13:53:57.380] <TB0> INFO: PixTestPretest::doTest() done, duration: 163 seconds
[13:53:57.380] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:53:57.380] <TB0> INFO: Decoding statistics:
[13:53:57.380] <TB0> INFO: General information:
[13:53:57.380] <TB0> INFO: 16bit words read: 7184734
[13:53:57.380] <TB0> INFO: valid events total: 463360
[13:53:57.380] <TB0> INFO: empty events: 261936
[13:53:57.380] <TB0> INFO: valid events with pixels: 201424
[13:53:57.380] <TB0> INFO: valid pixel hits: 812207
[13:53:57.380] <TB0> INFO: Event errors: 0
[13:53:57.380] <TB0> INFO: start marker: 0
[13:53:57.380] <TB0> INFO: stop marker: 0
[13:53:57.380] <TB0> INFO: overflow: 0
[13:53:57.380] <TB0> INFO: invalid 5bit words: 0
[13:53:57.380] <TB0> INFO: invalid XOR eye diagram: 0
[13:53:57.380] <TB0> INFO: TBM errors: 0
[13:53:57.380] <TB0> INFO: flawed TBM headers: 0
[13:53:57.380] <TB0> INFO: flawed TBM trailers: 0
[13:53:57.380] <TB0> INFO: event ID mismatches: 0
[13:53:57.380] <TB0> INFO: ROC errors: 0
[13:53:57.380] <TB0> INFO: missing ROC header(s): 0
[13:53:57.380] <TB0> INFO: misplaced readback start: 0
[13:53:57.380] <TB0> INFO: Pixel decoding errors: 0
[13:53:57.380] <TB0> INFO: pixel data incomplete: 0
[13:53:57.380] <TB0> INFO: pixel address: 0
[13:53:57.380] <TB0> INFO: pulse height fill bit: 0
[13:53:57.380] <TB0> INFO: buffer corruption: 0
[13:53:57.475] <TB0> INFO: ######################################################################
[13:53:57.475] <TB0> INFO: PixTestAlive::doTest()
[13:53:57.475] <TB0> INFO: ######################################################################
[13:53:57.477] <TB0> INFO: ----------------------------------------------------------------------
[13:53:57.477] <TB0> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:53:57.477] <TB0> INFO: ----------------------------------------------------------------------
[13:53:57.827] <TB0> INFO: Expecting 41600 events.
[13:54:02.238] <TB0> INFO: 41600 events read in total (3695ms).
[13:54:02.239] <TB0> INFO: Test took 4760ms.
[13:54:02.251] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:54:02.619] <TB0> INFO: PixTestAlive::aliveTest() done
[13:54:02.619] <TB0> INFO: number of dead pixels (per ROC): 2 3 0 3 0 0 3 0 0 1 0 0 1 1 1 2
[13:54:02.623] <TB0> INFO: ----------------------------------------------------------------------
[13:54:02.623] <TB0> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:54:02.623] <TB0> INFO: ----------------------------------------------------------------------
[13:54:02.996] <TB0> INFO: Expecting 41600 events.
[13:54:06.080] <TB0> INFO: 41600 events read in total (2369ms).
[13:54:06.086] <TB0> INFO: Test took 3460ms.
[13:54:06.086] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:54:06.087] <TB0> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[13:54:06.487] <TB0> INFO: PixTestAlive::maskTest() done
[13:54:06.488] <TB0> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:54:06.490] <TB0> INFO: ----------------------------------------------------------------------
[13:54:06.490] <TB0> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:54:06.490] <TB0> INFO: ----------------------------------------------------------------------
[13:54:06.899] <TB0> INFO: Expecting 41600 events.
[13:54:11.296] <TB0> INFO: 41600 events read in total (3680ms).
[13:54:11.297] <TB0> INFO: Test took 4804ms.
[13:54:11.308] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:54:11.680] <TB0> INFO: PixTestAlive::addressDecodingTest() done
[13:54:11.680] <TB0> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:54:11.680] <TB0> INFO: PixTestAlive::doTest() done, duration: 14 seconds
[13:54:11.680] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:54:11.680] <TB0> INFO: Decoding statistics:
[13:54:11.680] <TB0> INFO: General information:
[13:54:11.680] <TB0> INFO: 16bit words read: 0
[13:54:11.680] <TB0> INFO: valid events total: 0
[13:54:11.680] <TB0> INFO: empty events: 0
[13:54:11.680] <TB0> INFO: valid events with pixels: 0
[13:54:11.680] <TB0> INFO: valid pixel hits: 0
[13:54:11.680] <TB0> INFO: Event errors: 0
[13:54:11.680] <TB0> INFO: start marker: 0
[13:54:11.680] <TB0> INFO: stop marker: 0
[13:54:11.680] <TB0> INFO: overflow: 0
[13:54:11.680] <TB0> INFO: invalid 5bit words: 0
[13:54:11.681] <TB0> INFO: invalid XOR eye diagram: 0
[13:54:11.681] <TB0> INFO: TBM errors: 0
[13:54:11.681] <TB0> INFO: flawed TBM headers: 0
[13:54:11.681] <TB0> INFO: flawed TBM trailers: 0
[13:54:11.681] <TB0> INFO: event ID mismatches: 0
[13:54:11.681] <TB0> INFO: ROC errors: 0
[13:54:11.681] <TB0> INFO: missing ROC header(s): 0
[13:54:11.681] <TB0> INFO: misplaced readback start: 0
[13:54:11.681] <TB0> INFO: Pixel decoding errors: 0
[13:54:11.681] <TB0> INFO: pixel data incomplete: 0
[13:54:11.681] <TB0> INFO: pixel address: 0
[13:54:11.681] <TB0> INFO: pulse height fill bit: 0
[13:54:11.681] <TB0> INFO: buffer corruption: 0
[13:54:11.691] <TB0> INFO: ######################################################################
[13:54:11.691] <TB0> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[13:54:11.691] <TB0> INFO: ######################################################################
[13:54:11.694] <TB0> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[13:54:11.750] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:54:11.750] <TB0> INFO: run 1 of 1
[13:54:12.160] <TB0> INFO: Expecting 3120000 events.
[13:55:05.280] <TB0> INFO: 1284590 events read in total (52405ms).
[13:55:58.012] <TB0> INFO: 2548680 events read in total (105137ms).
[13:56:26.533] <TB0> INFO: 3120000 events read in total (133659ms).
[13:56:26.638] <TB0> INFO: Test took 134889ms.
[13:56:26.941] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:57:35.526] <TB0> INFO: PixTestBBMap::doTest() done, duration: 203 seconds
[13:57:35.526] <TB0> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:57:35.527] <TB0> INFO: separation cut (per ROC): 150 147 145 143 140 149 139 145 145 142 142 151 145 145 137 164
[13:57:35.527] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:57:35.527] <TB0> INFO: Decoding statistics:
[13:57:35.527] <TB0> INFO: General information:
[13:57:35.527] <TB0> INFO: 16bit words read: 0
[13:57:35.527] <TB0> INFO: valid events total: 0
[13:57:35.527] <TB0> INFO: empty events: 0
[13:57:35.527] <TB0> INFO: valid events with pixels: 0
[13:57:35.527] <TB0> INFO: valid pixel hits: 0
[13:57:35.527] <TB0> INFO: Event errors: 0
[13:57:35.527] <TB0> INFO: start marker: 0
[13:57:35.527] <TB0> INFO: stop marker: 0
[13:57:35.527] <TB0> INFO: overflow: 0
[13:57:35.527] <TB0> INFO: invalid 5bit words: 0
[13:57:35.527] <TB0> INFO: invalid XOR eye diagram: 0
[13:57:35.527] <TB0> INFO: TBM errors: 0
[13:57:35.527] <TB0> INFO: flawed TBM headers: 0
[13:57:35.527] <TB0> INFO: flawed TBM trailers: 0
[13:57:35.527] <TB0> INFO: event ID mismatches: 0
[13:57:35.527] <TB0> INFO: ROC errors: 0
[13:57:35.527] <TB0> INFO: missing ROC header(s): 0
[13:57:35.527] <TB0> INFO: misplaced readback start: 0
[13:57:35.527] <TB0> INFO: Pixel decoding errors: 0
[13:57:35.527] <TB0> INFO: pixel data incomplete: 0
[13:57:35.527] <TB0> INFO: pixel address: 0
[13:57:35.527] <TB0> INFO: pulse height fill bit: 0
[13:57:35.527] <TB0> INFO: buffer corruption: 0
[13:57:35.675] <TB0> INFO: ######################################################################
[13:57:35.675] <TB0> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:57:35.675] <TB0> INFO: ######################################################################
[13:57:35.676] <TB0> INFO: ----------------------------------------------------------------------
[13:57:35.676] <TB0> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:57:35.676] <TB0> INFO: ----------------------------------------------------------------------
[13:57:35.676] <TB0> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:57:35.723] <TB0> INFO: dacScan split into 1 runs with ntrig = 50
[13:57:35.723] <TB0> INFO: run 1 of 1
[13:57:36.133] <TB0> INFO: Expecting 26208000 events.
[13:58:18.268] <TB0> INFO: 1344450 events read in total (41418ms).
[13:58:59.464] <TB0> INFO: 2654300 events read in total (82614ms).
[13:59:40.449] <TB0> INFO: 3955150 events read in total (123599ms).
[14:00:21.478] <TB0> INFO: 5257150 events read in total (164628ms).
[14:01:02.231] <TB0> INFO: 6556200 events read in total (205381ms).
[14:01:42.407] <TB0> INFO: 7850350 events read in total (245557ms).
[14:02:22.319] <TB0> INFO: 9146400 events read in total (285469ms).
[14:03:02.155] <TB0> INFO: 10434600 events read in total (325305ms).
[14:03:42.187] <TB0> INFO: 11723650 events read in total (365337ms).
[14:04:21.710] <TB0> INFO: 13007000 events read in total (404860ms).
[14:05:00.853] <TB0> INFO: 14274100 events read in total (444003ms).
[14:05:40.227] <TB0> INFO: 15531800 events read in total (483377ms).
[14:06:19.376] <TB0> INFO: 16789450 events read in total (522526ms).
[14:06:58.463] <TB0> INFO: 18043950 events read in total (561613ms).
[14:07:37.628] <TB0> INFO: 19301900 events read in total (600778ms).
[14:08:17.117] <TB0> INFO: 20552700 events read in total (640267ms).
[14:08:56.592] <TB0> INFO: 21808050 events read in total (679742ms).
[14:09:35.920] <TB0> INFO: 23057250 events read in total (719070ms).
[14:10:15.547] <TB0> INFO: 24313300 events read in total (758697ms).
[14:10:55.013] <TB0> INFO: 25565050 events read in total (798163ms).
[14:11:14.819] <TB0> INFO: 26208000 events read in total (817969ms).
[14:11:14.877] <TB0> INFO: Test took 819154ms.
[14:11:14.991] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:11:15.338] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:11:18.347] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:11:21.154] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:11:24.134] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:11:27.377] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:11:30.453] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:11:33.548] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:11:36.720] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:11:39.852] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:11:42.900] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:11:46.143] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:11:49.826] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:11:53.119] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:11:56.600] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:12:01.994] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:12:07.307] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:12:11.909] <TB0> INFO: PixTestScurves::scurves() done
[14:12:11.909] <TB0> INFO: Vcal mean: 113.27 117.14 117.48 111.67 110.95 117.99 106.80 113.45 106.65 111.55 114.86 115.59 118.46 116.48 106.55 127.21
[14:12:11.909] <TB0> INFO: Vcal RMS: 5.90 7.21 8.52 6.58 5.12 5.84 6.10 5.82 5.44 5.67 5.66 5.89 6.25 6.34 5.46 8.16
[14:12:11.909] <TB0> INFO: PixTestScurves::fullTest() done, duration: 876 seconds
[14:12:11.910] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:12:11.910] <TB0> INFO: Decoding statistics:
[14:12:11.910] <TB0> INFO: General information:
[14:12:11.910] <TB0> INFO: 16bit words read: 0
[14:12:11.910] <TB0> INFO: valid events total: 0
[14:12:11.910] <TB0> INFO: empty events: 0
[14:12:11.910] <TB0> INFO: valid events with pixels: 0
[14:12:11.910] <TB0> INFO: valid pixel hits: 0
[14:12:11.910] <TB0> INFO: Event errors: 0
[14:12:11.910] <TB0> INFO: start marker: 0
[14:12:11.910] <TB0> INFO: stop marker: 0
[14:12:11.910] <TB0> INFO: overflow: 0
[14:12:11.910] <TB0> INFO: invalid 5bit words: 0
[14:12:11.910] <TB0> INFO: invalid XOR eye diagram: 0
[14:12:11.910] <TB0> INFO: TBM errors: 0
[14:12:11.910] <TB0> INFO: flawed TBM headers: 0
[14:12:11.910] <TB0> INFO: flawed TBM trailers: 0
[14:12:11.910] <TB0> INFO: event ID mismatches: 0
[14:12:11.910] <TB0> INFO: ROC errors: 0
[14:12:11.910] <TB0> INFO: missing ROC header(s): 0
[14:12:11.910] <TB0> INFO: misplaced readback start: 0
[14:12:11.910] <TB0> INFO: Pixel decoding errors: 0
[14:12:11.910] <TB0> INFO: pixel data incomplete: 0
[14:12:11.910] <TB0> INFO: pixel address: 0
[14:12:11.910] <TB0> INFO: pulse height fill bit: 0
[14:12:11.910] <TB0> INFO: buffer corruption: 0
[14:12:12.089] <TB0> INFO: ######################################################################
[14:12:12.089] <TB0> INFO: PixTestTrim::doTest()
[14:12:12.089] <TB0> INFO: ######################################################################
[14:12:12.091] <TB0> INFO: ----------------------------------------------------------------------
[14:12:12.091] <TB0> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[14:12:12.091] <TB0> INFO: ----------------------------------------------------------------------
[14:12:12.304] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:12:12.304] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:12:12.361] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:12:12.361] <TB0> INFO: run 1 of 1
[14:12:13.245] <TB0> INFO: Expecting 5025280 events.
[14:13:02.888] <TB0> INFO: 1460096 events read in total (48921ms).
[14:13:51.728] <TB0> INFO: 2909992 events read in total (97762ms).
[14:14:40.576] <TB0> INFO: 4343664 events read in total (146610ms).
[14:15:06.028] <TB0> INFO: 5025280 events read in total (172061ms).
[14:15:06.101] <TB0> INFO: Test took 173739ms.
[14:15:06.195] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:15:50.480] <TB0> INFO: ROC 0 VthrComp = 113
[14:15:50.481] <TB0> INFO: ROC 1 VthrComp = 111
[14:15:50.481] <TB0> INFO: ROC 2 VthrComp = 110
[14:15:50.486] <TB0> INFO: ROC 3 VthrComp = 107
[14:15:50.487] <TB0> INFO: ROC 4 VthrComp = 110
[14:15:50.487] <TB0> INFO: ROC 5 VthrComp = 110
[14:15:50.487] <TB0> INFO: ROC 6 VthrComp = 106
[14:15:50.487] <TB0> INFO: ROC 7 VthrComp = 109
[14:15:50.488] <TB0> INFO: ROC 8 VthrComp = 109
[14:15:50.488] <TB0> INFO: ROC 9 VthrComp = 108
[14:15:50.488] <TB0> INFO: ROC 10 VthrComp = 109
[14:15:50.488] <TB0> INFO: ROC 11 VthrComp = 113
[14:15:50.489] <TB0> INFO: ROC 12 VthrComp = 110
[14:15:50.489] <TB0> INFO: ROC 13 VthrComp = 110
[14:15:50.489] <TB0> INFO: ROC 14 VthrComp = 105
[14:15:50.490] <TB0> INFO: ROC 15 VthrComp = 78
[14:15:50.490] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:15:50.490] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:15:50.526] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:15:50.526] <TB0> INFO: run 1 of 1
[14:15:50.976] <TB0> INFO: Expecting 5025280 events.
[14:16:36.644] <TB0> INFO: 914072 events read in total (44953ms).
[14:17:16.814] <TB0> INFO: 1825872 events read in total (85123ms).
[14:17:57.011] <TB0> INFO: 2735040 events read in total (125321ms).
[14:18:36.327] <TB0> INFO: 3632000 events read in total (164636ms).
[14:19:15.835] <TB0> INFO: 4524976 events read in total (204144ms).
[14:19:39.045] <TB0> INFO: 5025280 events read in total (227354ms).
[14:19:39.163] <TB0> INFO: Test took 228637ms.
[14:19:39.429] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:20:31.120] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 63.9804 for pixel 16/5 mean/min/max = 49.2935/34.5069/64.0802
[14:20:31.121] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 67.4565 for pixel 51/77 mean/min/max = 51.1486/34.8154/67.4819
[14:20:31.123] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 74.2446 for pixel 5/1 mean/min/max = 54.6402/34.9547/74.3257
[14:20:31.124] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 66.895 for pixel 0/13 mean/min/max = 50.5637/34.0138/67.1136
[14:20:31.124] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 62.2276 for pixel 18/1 mean/min/max = 48.1731/34.0786/62.2676
[14:20:31.126] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 72.9693 for pixel 51/29 mean/min/max = 55.8043/38.5553/73.0533
[14:20:31.127] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 64.0254 for pixel 0/79 mean/min/max = 49.0591/33.9868/64.1313
[14:20:31.128] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 67.617 for pixel 2/79 mean/min/max = 51.4882/35.3134/67.663
[14:20:31.131] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 63.9946 for pixel 30/4 mean/min/max = 49.2835/34.4979/64.0691
[14:20:31.133] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 65.8285 for pixel 10/1 mean/min/max = 49.9837/34.063/65.9043
[14:20:31.134] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 68.4546 for pixel 12/47 mean/min/max = 52.2583/35.6307/68.8859
[14:20:31.135] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 67.3011 for pixel 2/1 mean/min/max = 50.9487/34.4896/67.4078
[14:20:31.136] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 73.4597 for pixel 0/12 mean/min/max = 55.7016/37.8299/73.5733
[14:20:31.137] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 69.7432 for pixel 0/1 mean/min/max = 52.8658/35.8577/69.8739
[14:20:31.139] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 62.8838 for pixel 32/5 mean/min/max = 48.4649/34.0291/62.9006
[14:20:31.141] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 125.409 for pixel 0/33 mean/min/max = 106.914/88.4037/125.424
[14:20:31.142] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:20:31.278] <TB0> INFO: Expecting 411648 events.
[14:20:40.743] <TB0> INFO: 411648 events read in total (8733ms).
[14:20:40.767] <TB0> INFO: Expecting 411648 events.
[14:20:50.151] <TB0> INFO: 411648 events read in total (8785ms).
[14:20:50.213] <TB0> INFO: Expecting 411648 events.
[14:20:58.967] <TB0> INFO: 411648 events read in total (8226ms).
[14:20:59.017] <TB0> INFO: Expecting 411648 events.
[14:21:07.938] <TB0> INFO: 411648 events read in total (8366ms).
[14:21:07.990] <TB0> INFO: Expecting 411648 events.
[14:21:17.368] <TB0> INFO: 411648 events read in total (8843ms).
[14:21:17.407] <TB0> INFO: Expecting 411648 events.
[14:21:27.155] <TB0> INFO: 411648 events read in total (9179ms).
[14:21:27.250] <TB0> INFO: Expecting 411648 events.
[14:21:37.017] <TB0> INFO: 411648 events read in total (9240ms).
[14:21:37.086] <TB0> INFO: Expecting 411648 events.
[14:21:46.743] <TB0> INFO: 411648 events read in total (9121ms).
[14:21:46.789] <TB0> INFO: Expecting 411648 events.
[14:21:55.808] <TB0> INFO: 411648 events read in total (8415ms).
[14:21:55.866] <TB0> INFO: Expecting 411648 events.
[14:22:04.842] <TB0> INFO: 411648 events read in total (8386ms).
[14:22:04.894] <TB0> INFO: Expecting 411648 events.
[14:22:13.862] <TB0> INFO: 411648 events read in total (8364ms).
[14:22:13.916] <TB0> INFO: Expecting 411648 events.
[14:22:22.946] <TB0> INFO: 411648 events read in total (8433ms).
[14:22:23.017] <TB0> INFO: Expecting 411648 events.
[14:22:31.929] <TB0> INFO: 411648 events read in total (8336ms).
[14:22:31.992] <TB0> INFO: Expecting 411648 events.
[14:22:40.912] <TB0> INFO: 411648 events read in total (8329ms).
[14:22:40.996] <TB0> INFO: Expecting 411648 events.
[14:22:49.966] <TB0> INFO: 411648 events read in total (8409ms).
[14:22:50.047] <TB0> INFO: Expecting 411648 events.
[14:22:58.838] <TB0> INFO: 411648 events read in total (8228ms).
[14:22:58.913] <TB0> INFO: Test took 147771ms.
[14:23:00.510] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:23:00.536] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:23:00.536] <TB0> INFO: run 1 of 1
[14:23:00.957] <TB0> INFO: Expecting 5025280 events.
[14:23:39.269] <TB0> INFO: 883792 events read in total (37597ms).
[14:24:18.270] <TB0> INFO: 1766480 events read in total (76598ms).
[14:25:00.558] <TB0> INFO: 2647328 events read in total (118886ms).
[14:25:42.824] <TB0> INFO: 3516872 events read in total (161152ms).
[14:26:24.753] <TB0> INFO: 4381616 events read in total (203082ms).
[14:26:55.612] <TB0> INFO: 5025280 events read in total (233940ms).
[14:26:55.761] <TB0> INFO: Test took 235224ms.
[14:26:56.053] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:27:46.384] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 0.175818 .. 255.000000
[14:27:46.499] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[14:27:46.528] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:27:46.528] <TB0> INFO: run 1 of 1
[14:27:46.926] <TB0> INFO: Expecting 8519680 events.
[14:28:37.228] <TB0> INFO: 825352 events read in total (49587ms).
[14:29:24.773] <TB0> INFO: 1650608 events read in total (97132ms).
[14:30:04.634] <TB0> INFO: 2475904 events read in total (136993ms).
[14:30:45.017] <TB0> INFO: 3301840 events read in total (177376ms).
[14:31:25.216] <TB0> INFO: 4127456 events read in total (217575ms).
[14:32:05.442] <TB0> INFO: 4954448 events read in total (257801ms).
[14:32:45.715] <TB0> INFO: 5781840 events read in total (298074ms).
[14:33:25.746] <TB0> INFO: 6609232 events read in total (338105ms).
[14:34:05.806] <TB0> INFO: 7436840 events read in total (378165ms).
[14:34:45.489] <TB0> INFO: 8264480 events read in total (417849ms).
[14:34:58.100] <TB0> INFO: 8519680 events read in total (430459ms).
[14:34:58.397] <TB0> INFO: Test took 431869ms.
[14:34:59.027] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:36:06.770] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 18.826320 .. 83.795580
[14:36:06.927] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 8 .. 93 (-1/-1) hits flags = 528 (plus default)
[14:36:06.955] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:36:06.955] <TB0> INFO: run 1 of 1
[14:36:07.416] <TB0> INFO: Expecting 2862080 events.
[14:37:00.519] <TB0> INFO: 933912 events read in total (52368ms).
[14:37:46.123] <TB0> INFO: 1867632 events read in total (97974ms).
[14:38:28.414] <TB0> INFO: 2801560 events read in total (140264ms).
[14:38:31.764] <TB0> INFO: 2862080 events read in total (143613ms).
[14:38:31.858] <TB0> INFO: Test took 144903ms.
[14:38:32.049] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:39:11.778] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 4.536908 .. 55.902065
[14:39:11.878] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 4 .. 65 (-1/-1) hits flags = 528 (plus default)
[14:39:11.906] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:39:11.906] <TB0> INFO: run 1 of 1
[14:39:12.324] <TB0> INFO: Expecting 2063360 events.
[14:40:03.450] <TB0> INFO: 1079288 events read in total (50410ms).
[14:40:45.879] <TB0> INFO: 2063360 events read in total (92839ms).
[14:40:45.935] <TB0> INFO: Test took 94030ms.
[14:40:46.061] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:41:23.988] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 7.147554 .. 54.796528
[14:41:24.100] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 7 .. 64 (-1/-1) hits flags = 528 (plus default)
[14:41:24.132] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:41:24.132] <TB0> INFO: run 1 of 1
[14:41:24.627] <TB0> INFO: Expecting 1930240 events.
[14:42:10.488] <TB0> INFO: 1066640 events read in total (45146ms).
[14:42:51.352] <TB0> INFO: 1930240 events read in total (86010ms).
[14:42:51.449] <TB0> INFO: Test took 87317ms.
[14:42:51.607] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:43:29.913] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:43:29.913] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:43:29.941] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:43:29.941] <TB0> INFO: run 1 of 1
[14:43:30.358] <TB0> INFO: Expecting 1364480 events.
[14:44:16.188] <TB0> INFO: 1077208 events read in total (45113ms).
[14:44:28.531] <TB0> INFO: 1364480 events read in total (57456ms).
[14:44:28.574] <TB0> INFO: Test took 58632ms.
[14:44:28.637] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:44:59.904] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C0.dat
[14:44:59.911] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C1.dat
[14:44:59.927] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C2.dat
[14:44:59.937] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C3.dat
[14:44:59.944] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C4.dat
[14:44:59.954] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C5.dat
[14:44:59.961] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C6.dat
[14:44:59.971] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C7.dat
[14:44:59.974] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C8.dat
[14:44:59.981] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C9.dat
[14:44:59.990] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C10.dat
[14:44:59.000] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C11.dat
[14:45:00.008] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C12.dat
[14:45:00.015] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C13.dat
[14:45:00.025] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C14.dat
[14:45:00.031] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C15.dat
[14:45:00.036] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C0.dat
[14:45:00.060] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C1.dat
[14:45:00.075] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C2.dat
[14:45:00.089] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C3.dat
[14:45:00.104] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C4.dat
[14:45:00.119] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C5.dat
[14:45:00.134] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C6.dat
[14:45:00.149] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C7.dat
[14:45:00.163] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C8.dat
[14:45:00.172] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C9.dat
[14:45:00.180] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C10.dat
[14:45:00.196] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C11.dat
[14:45:00.206] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C12.dat
[14:45:00.216] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C13.dat
[14:45:00.227] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C14.dat
[14:45:00.237] <TB0> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//trimParameters35_C15.dat
[14:45:00.247] <TB0> INFO: PixTestTrim::trimTest() done
[14:45:00.248] <TB0> INFO: vtrim: 121 126 119 119 115 146 98 130 129 125 137 134 142 137 123 236
[14:45:00.248] <TB0> INFO: vthrcomp: 113 111 110 107 110 110 106 109 109 108 109 113 110 110 105 78
[14:45:00.248] <TB0> INFO: vcal mean: 34.99 34.99 34.98 34.99 35.06 34.99 34.99 35.03 35.02 35.04 35.01 35.05 35.03 35.01 35.06 37.80
[14:45:00.248] <TB0> INFO: vcal RMS: 1.22 1.41 1.10 1.29 0.97 1.06 1.27 1.04 1.03 1.17 1.03 0.99 1.18 1.04 1.11 4.39
[14:45:00.248] <TB0> INFO: bits mean: 8.39 8.15 7.16 7.83 8.41 6.43 7.46 7.46 8.47 8.83 8.14 8.02 6.80 7.59 8.54 1.48
[14:45:00.248] <TB0> INFO: bits RMS: 2.53 2.49 2.59 2.73 2.68 2.29 2.91 2.55 2.50 2.39 2.33 2.55 2.36 2.47 2.62 0.85
[14:45:00.261] <TB0> INFO: ----------------------------------------------------------------------
[14:45:00.261] <TB0> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:45:00.261] <TB0> INFO: ----------------------------------------------------------------------
[14:45:00.264] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:45:00.295] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:45:00.295] <TB0> INFO: run 1 of 1
[14:45:00.721] <TB0> INFO: Expecting 4160000 events.
[14:45:54.006] <TB0> INFO: 1315965 events read in total (52563ms).
[14:46:45.888] <TB0> INFO: 2607800 events read in total (104446ms).
[14:47:37.321] <TB0> INFO: 3885870 events read in total (155879ms).
[14:47:49.879] <TB0> INFO: 4160000 events read in total (168436ms).
[14:47:49.976] <TB0> INFO: Test took 169682ms.
[14:47:50.140] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:49:00.535] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[14:49:00.563] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:49:00.563] <TB0> INFO: run 1 of 1
[14:49:00.974] <TB0> INFO: Expecting 4347200 events.
[14:49:53.254] <TB0> INFO: 1217210 events read in total (51565ms).
[14:50:48.037] <TB0> INFO: 2417455 events read in total (106348ms).
[14:51:37.811] <TB0> INFO: 3602275 events read in total (156122ms).
[14:52:12.919] <TB0> INFO: 4347200 events read in total (191230ms).
[14:52:13.029] <TB0> INFO: Test took 192467ms.
[14:52:13.214] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:53:23.555] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[14:53:23.607] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:53:23.608] <TB0> INFO: run 1 of 1
[14:53:24.052] <TB0> INFO: Expecting 4326400 events.
[14:54:14.368] <TB0> INFO: 1220355 events read in total (49595ms).
[14:55:05.319] <TB0> INFO: 2423890 events read in total (100546ms).
[14:55:56.006] <TB0> INFO: 3611490 events read in total (151234ms).
[14:56:27.382] <TB0> INFO: 4326400 events read in total (182609ms).
[14:56:27.483] <TB0> INFO: Test took 183876ms.
[14:56:27.677] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:57:31.141] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[14:57:31.168] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:57:31.168] <TB0> INFO: run 1 of 1
[14:57:31.591] <TB0> INFO: Expecting 4243200 events.
[14:58:22.292] <TB0> INFO: 1234050 events read in total (49985ms).
[14:59:14.425] <TB0> INFO: 2449085 events read in total (102119ms).
[15:00:08.666] <TB0> INFO: 3649210 events read in total (156359ms).
[15:00:33.153] <TB0> INFO: 4243200 events read in total (180846ms).
[15:00:33.246] <TB0> INFO: Test took 182078ms.
[15:00:33.419] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:01:34.217] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[15:01:34.255] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[15:01:34.258] <TB0> INFO: run 1 of 1
[15:01:34.984] <TB0> INFO: Expecting 4243200 events.
[15:02:26.170] <TB0> INFO: 1233600 events read in total (50470ms).
[15:03:20.308] <TB0> INFO: 2448350 events read in total (104608ms).
[15:04:15.064] <TB0> INFO: 3648030 events read in total (159364ms).
[15:04:40.268] <TB0> INFO: 4243200 events read in total (184568ms).
[15:04:40.359] <TB0> INFO: Test took 186097ms.
[15:04:40.526] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:05:38.782] <TB0> INFO: PixTestTrim::trimBitTest() done
[15:05:38.791] <TB0> INFO: PixTestTrim::doTest() done, duration: 3206 seconds
[15:05:38.791] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:05:38.791] <TB0> INFO: Decoding statistics:
[15:05:38.791] <TB0> INFO: General information:
[15:05:38.791] <TB0> INFO: 16bit words read: 0
[15:05:38.791] <TB0> INFO: valid events total: 0
[15:05:38.791] <TB0> INFO: empty events: 0
[15:05:38.791] <TB0> INFO: valid events with pixels: 0
[15:05:38.791] <TB0> INFO: valid pixel hits: 0
[15:05:38.791] <TB0> INFO: Event errors: 0
[15:05:38.791] <TB0> INFO: start marker: 0
[15:05:38.791] <TB0> INFO: stop marker: 0
[15:05:38.791] <TB0> INFO: overflow: 0
[15:05:38.791] <TB0> INFO: invalid 5bit words: 0
[15:05:38.791] <TB0> INFO: invalid XOR eye diagram: 0
[15:05:38.791] <TB0> INFO: TBM errors: 0
[15:05:38.791] <TB0> INFO: flawed TBM headers: 0
[15:05:38.791] <TB0> INFO: flawed TBM trailers: 0
[15:05:38.792] <TB0> INFO: event ID mismatches: 0
[15:05:38.792] <TB0> INFO: ROC errors: 0
[15:05:38.792] <TB0> INFO: missing ROC header(s): 0
[15:05:38.792] <TB0> INFO: misplaced readback start: 0
[15:05:38.792] <TB0> INFO: Pixel decoding errors: 0
[15:05:38.792] <TB0> INFO: pixel data incomplete: 0
[15:05:38.792] <TB0> INFO: pixel address: 0
[15:05:38.792] <TB0> INFO: pulse height fill bit: 0
[15:05:38.792] <TB0> INFO: buffer corruption: 0
[15:05:40.264] <TB0> INFO: ######################################################################
[15:05:40.264] <TB0> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[15:05:40.264] <TB0> INFO: ######################################################################
[15:05:40.682] <TB0> INFO: Expecting 41600 events.
[15:05:45.255] <TB0> INFO: 41600 events read in total (3856ms).
[15:05:45.264] <TB0> INFO: Test took 4993ms.
[15:05:45.283] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:05:46.012] <TB0> INFO: Expecting 41600 events.
[15:05:50.893] <TB0> INFO: 41600 events read in total (4159ms).
[15:05:50.904] <TB0> INFO: Test took 5302ms.
[15:05:50.930] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:05:51.453] <TB0> INFO: Expecting 41600 events.
[15:05:56.038] <TB0> INFO: 41600 events read in total (3862ms).
[15:05:56.041] <TB0> INFO: Test took 5070ms.
[15:05:56.062] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:05:56.408] <TB0> INFO: Expecting 2560 events.
[15:05:57.377] <TB0> INFO: 2560 events read in total (249ms).
[15:05:57.377] <TB0> INFO: Test took 1291ms.
[15:05:57.890] <TB0> INFO: Expecting 2560 events.
[15:05:58.850] <TB0> INFO: 2560 events read in total (244ms).
[15:05:58.851] <TB0> INFO: Test took 1473ms.
[15:05:59.359] <TB0> INFO: Expecting 2560 events.
[15:06:00.325] <TB0> INFO: 2560 events read in total (251ms).
[15:06:00.325] <TB0> INFO: Test took 1466ms.
[15:06:00.834] <TB0> INFO: Expecting 2560 events.
[15:06:01.795] <TB0> INFO: 2560 events read in total (245ms).
[15:06:01.796] <TB0> INFO: Test took 1470ms.
[15:06:02.307] <TB0> INFO: Expecting 2560 events.
[15:06:03.271] <TB0> INFO: 2560 events read in total (248ms).
[15:06:03.272] <TB0> INFO: Test took 1466ms.
[15:06:03.784] <TB0> INFO: Expecting 2560 events.
[15:06:04.747] <TB0> INFO: 2560 events read in total (247ms).
[15:06:04.747] <TB0> INFO: Test took 1475ms.
[15:06:05.258] <TB0> INFO: Expecting 2560 events.
[15:06:06.224] <TB0> INFO: 2560 events read in total (250ms).
[15:06:06.224] <TB0> INFO: Test took 1477ms.
[15:06:06.733] <TB0> INFO: Expecting 2560 events.
[15:06:07.695] <TB0> INFO: 2560 events read in total (246ms).
[15:06:07.696] <TB0> INFO: Test took 1467ms.
[15:06:08.205] <TB0> INFO: Expecting 2560 events.
[15:06:09.168] <TB0> INFO: 2560 events read in total (248ms).
[15:06:09.169] <TB0> INFO: Test took 1468ms.
[15:06:09.682] <TB0> INFO: Expecting 2560 events.
[15:06:10.647] <TB0> INFO: 2560 events read in total (250ms).
[15:06:10.648] <TB0> INFO: Test took 1479ms.
[15:06:11.156] <TB0> INFO: Expecting 2560 events.
[15:06:12.122] <TB0> INFO: 2560 events read in total (248ms).
[15:06:12.122] <TB0> INFO: Test took 1474ms.
[15:06:12.632] <TB0> INFO: Expecting 2560 events.
[15:06:13.600] <TB0> INFO: 2560 events read in total (251ms).
[15:06:13.600] <TB0> INFO: Test took 1477ms.
[15:06:14.110] <TB0> INFO: Expecting 2560 events.
[15:06:15.078] <TB0> INFO: 2560 events read in total (250ms).
[15:06:15.078] <TB0> INFO: Test took 1477ms.
[15:06:15.591] <TB0> INFO: Expecting 2560 events.
[15:06:16.552] <TB0> INFO: 2560 events read in total (246ms).
[15:06:16.553] <TB0> INFO: Test took 1474ms.
[15:06:17.066] <TB0> INFO: Expecting 2560 events.
[15:06:18.030] <TB0> INFO: 2560 events read in total (247ms).
[15:06:18.030] <TB0> INFO: Test took 1477ms.
[15:06:18.541] <TB0> INFO: Expecting 2560 events.
[15:06:19.504] <TB0> INFO: 2560 events read in total (247ms).
[15:06:19.504] <TB0> INFO: Test took 1473ms.
[15:06:19.510] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:06:20.017] <TB0> INFO: Expecting 655360 events.
[15:06:34.304] <TB0> INFO: 655360 events read in total (13571ms).
[15:06:34.324] <TB0> INFO: Expecting 655360 events.
[15:06:48.031] <TB0> INFO: 655360 events read in total (13181ms).
[15:06:48.053] <TB0> INFO: Expecting 655360 events.
[15:07:01.703] <TB0> INFO: 655360 events read in total (13123ms).
[15:07:01.748] <TB0> INFO: Expecting 655360 events.
[15:07:15.460] <TB0> INFO: 655360 events read in total (13185ms).
[15:07:15.507] <TB0> INFO: Expecting 655360 events.
[15:07:30.298] <TB0> INFO: 655360 events read in total (14264ms).
[15:07:30.350] <TB0> INFO: Expecting 655360 events.
[15:07:44.573] <TB0> INFO: 655360 events read in total (13696ms).
[15:07:44.635] <TB0> INFO: Expecting 655360 events.
[15:07:58.687] <TB0> INFO: 655360 events read in total (13526ms).
[15:07:58.798] <TB0> INFO: Expecting 655360 events.
[15:08:12.445] <TB0> INFO: 655360 events read in total (13120ms).
[15:08:12.506] <TB0> INFO: Expecting 655360 events.
[15:08:26.146] <TB0> INFO: 655360 events read in total (13114ms).
[15:08:26.228] <TB0> INFO: Expecting 655360 events.
[15:08:39.797] <TB0> INFO: 655360 events read in total (13042ms).
[15:08:39.874] <TB0> INFO: Expecting 655360 events.
[15:08:53.422] <TB0> INFO: 655360 events read in total (13021ms).
[15:08:53.520] <TB0> INFO: Expecting 655360 events.
[15:09:06.991] <TB0> INFO: 655360 events read in total (12942ms).
[15:09:07.090] <TB0> INFO: Expecting 655360 events.
[15:09:20.576] <TB0> INFO: 655360 events read in total (12960ms).
[15:09:20.671] <TB0> INFO: Expecting 655360 events.
[15:09:34.094] <TB0> INFO: 655360 events read in total (12897ms).
[15:09:34.220] <TB0> INFO: Expecting 655360 events.
[15:09:47.695] <TB0> INFO: 655360 events read in total (12947ms).
[15:09:47.808] <TB0> INFO: Expecting 655360 events.
[15:10:01.526] <TB0> INFO: 655360 events read in total (13191ms).
[15:10:01.665] <TB0> INFO: Test took 222155ms.
[15:10:01.839] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:10:02.140] <TB0> INFO: Expecting 655360 events.
[15:10:15.580] <TB0> INFO: 655360 events read in total (12724ms).
[15:10:15.603] <TB0> INFO: Expecting 655360 events.
[15:10:28.717] <TB0> INFO: 655360 events read in total (12587ms).
[15:10:28.747] <TB0> INFO: Expecting 655360 events.
[15:10:41.860] <TB0> INFO: 655360 events read in total (12587ms).
[15:10:41.898] <TB0> INFO: Expecting 655360 events.
[15:10:55.035] <TB0> INFO: 655360 events read in total (12610ms).
[15:10:55.076] <TB0> INFO: Expecting 655360 events.
[15:11:07.922] <TB0> INFO: 655360 events read in total (12320ms).
[15:11:07.968] <TB0> INFO: Expecting 655360 events.
[15:11:20.995] <TB0> INFO: 655360 events read in total (12500ms).
[15:11:21.055] <TB0> INFO: Expecting 655360 events.
[15:11:34.181] <TB0> INFO: 655360 events read in total (12600ms).
[15:11:34.234] <TB0> INFO: Expecting 655360 events.
[15:11:47.349] <TB0> INFO: 655360 events read in total (12588ms).
[15:11:47.415] <TB0> INFO: Expecting 655360 events.
[15:12:00.608] <TB0> INFO: 655360 events read in total (12666ms).
[15:12:00.678] <TB0> INFO: Expecting 655360 events.
[15:12:13.825] <TB0> INFO: 655360 events read in total (12621ms).
[15:12:13.913] <TB0> INFO: Expecting 655360 events.
[15:12:26.994] <TB0> INFO: 655360 events read in total (12555ms).
[15:12:27.077] <TB0> INFO: Expecting 655360 events.
[15:12:40.461] <TB0> INFO: 655360 events read in total (12857ms).
[15:12:40.545] <TB0> INFO: Expecting 655360 events.
[15:12:53.732] <TB0> INFO: 655360 events read in total (12661ms).
[15:12:53.824] <TB0> INFO: Expecting 655360 events.
[15:13:07.036] <TB0> INFO: 655360 events read in total (12685ms).
[15:13:07.163] <TB0> INFO: Expecting 655360 events.
[15:13:20.289] <TB0> INFO: 655360 events read in total (12599ms).
[15:13:20.415] <TB0> INFO: Expecting 655360 events.
[15:13:33.607] <TB0> INFO: 655360 events read in total (12665ms).
[15:13:33.739] <TB0> INFO: Test took 211900ms.
[15:13:34.080] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.097] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.113] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.128] <TB0> INFO: For ROC 2: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[15:13:34.133] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[15:13:34.147] <TB0> INFO: For ROC 2: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[15:13:34.151] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[15:13:34.166] <TB0> INFO: For ROC 2: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[15:13:34.171] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[15:13:34.186] <TB0> INFO: For ROC 2: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[15:13:34.190] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[15:13:34.205] <TB0> INFO: For ROC 2: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[15:13:34.209] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[15:13:34.224] <TB0> INFO: For ROC 2: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[15:13:34.228] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[15:13:34.243] <TB0> INFO: For ROC 2: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[15:13:34.247] <TB0> INFO: safety margin for low PH: adding 7, margin is now 27
[15:13:34.263] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.280] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.297] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.313] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.331] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.347] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.364] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.381] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.397] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.415] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.431] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.448] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.466] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:13:34.514] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C0.dat
[15:13:34.514] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C1.dat
[15:13:34.514] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C2.dat
[15:13:34.515] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C3.dat
[15:13:34.515] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C4.dat
[15:13:34.515] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C5.dat
[15:13:34.515] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C6.dat
[15:13:34.515] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C7.dat
[15:13:34.515] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C8.dat
[15:13:34.516] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C9.dat
[15:13:34.516] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C10.dat
[15:13:34.516] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C11.dat
[15:13:34.516] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C12.dat
[15:13:34.517] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C13.dat
[15:13:34.517] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C14.dat
[15:13:34.517] <TB0> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//dacParameters35_C15.dat
[15:13:34.866] <TB0> INFO: Expecting 41600 events.
[15:13:38.945] <TB0> INFO: 41600 events read in total (3363ms).
[15:13:38.947] <TB0> INFO: Test took 4423ms.
[15:13:39.581] <TB0> INFO: Expecting 41600 events.
[15:13:43.584] <TB0> INFO: 41600 events read in total (3288ms).
[15:13:43.586] <TB0> INFO: Test took 4363ms.
[15:13:44.248] <TB0> INFO: Expecting 41600 events.
[15:13:48.296] <TB0> INFO: 41600 events read in total (3333ms).
[15:13:48.297] <TB0> INFO: Test took 4414ms.
[15:13:48.579] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:48.713] <TB0> INFO: Expecting 2560 events.
[15:13:49.679] <TB0> INFO: 2560 events read in total (244ms).
[15:13:49.680] <TB0> INFO: Test took 1101ms.
[15:13:49.687] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:50.190] <TB0> INFO: Expecting 2560 events.
[15:13:51.149] <TB0> INFO: 2560 events read in total (244ms).
[15:13:51.153] <TB0> INFO: Test took 1466ms.
[15:13:51.156] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:51.659] <TB0> INFO: Expecting 2560 events.
[15:13:52.628] <TB0> INFO: 2560 events read in total (246ms).
[15:13:52.628] <TB0> INFO: Test took 1472ms.
[15:13:52.635] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:53.139] <TB0> INFO: Expecting 2560 events.
[15:13:54.099] <TB0> INFO: 2560 events read in total (245ms).
[15:13:54.100] <TB0> INFO: Test took 1465ms.
[15:13:54.104] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:54.609] <TB0> INFO: Expecting 2560 events.
[15:13:55.570] <TB0> INFO: 2560 events read in total (246ms).
[15:13:55.570] <TB0> INFO: Test took 1466ms.
[15:13:55.574] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:56.080] <TB0> INFO: Expecting 2560 events.
[15:13:57.040] <TB0> INFO: 2560 events read in total (244ms).
[15:13:57.041] <TB0> INFO: Test took 1467ms.
[15:13:57.045] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:57.551] <TB0> INFO: Expecting 2560 events.
[15:13:58.510] <TB0> INFO: 2560 events read in total (244ms).
[15:13:58.513] <TB0> INFO: Test took 1468ms.
[15:13:58.515] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:59.020] <TB0> INFO: Expecting 2560 events.
[15:13:59.980] <TB0> INFO: 2560 events read in total (244ms).
[15:13:59.980] <TB0> INFO: Test took 1465ms.
[15:13:59.986] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:00.490] <TB0> INFO: Expecting 2560 events.
[15:14:01.449] <TB0> INFO: 2560 events read in total (244ms).
[15:14:01.449] <TB0> INFO: Test took 1463ms.
[15:14:01.452] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:01.959] <TB0> INFO: Expecting 2560 events.
[15:14:02.919] <TB0> INFO: 2560 events read in total (245ms).
[15:14:02.923] <TB0> INFO: Test took 1471ms.
[15:14:02.926] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:03.429] <TB0> INFO: Expecting 2560 events.
[15:14:04.389] <TB0> INFO: 2560 events read in total (245ms).
[15:14:04.389] <TB0> INFO: Test took 1463ms.
[15:14:04.392] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:04.899] <TB0> INFO: Expecting 2560 events.
[15:14:05.859] <TB0> INFO: 2560 events read in total (245ms).
[15:14:05.860] <TB0> INFO: Test took 1468ms.
[15:14:05.866] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:06.369] <TB0> INFO: Expecting 2560 events.
[15:14:07.337] <TB0> INFO: 2560 events read in total (253ms).
[15:14:07.339] <TB0> INFO: Test took 1473ms.
[15:14:07.344] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:07.848] <TB0> INFO: Expecting 2560 events.
[15:14:08.808] <TB0> INFO: 2560 events read in total (244ms).
[15:14:08.808] <TB0> INFO: Test took 1464ms.
[15:14:08.812] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:09.318] <TB0> INFO: Expecting 2560 events.
[15:14:10.277] <TB0> INFO: 2560 events read in total (244ms).
[15:14:10.278] <TB0> INFO: Test took 1466ms.
[15:14:10.284] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:10.798] <TB0> INFO: Expecting 2560 events.
[15:14:11.759] <TB0> INFO: 2560 events read in total (245ms).
[15:14:11.759] <TB0> INFO: Test took 1475ms.
[15:14:11.764] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:12.269] <TB0> INFO: Expecting 2560 events.
[15:14:13.228] <TB0> INFO: 2560 events read in total (244ms).
[15:14:13.229] <TB0> INFO: Test took 1466ms.
[15:14:13.234] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:13.738] <TB0> INFO: Expecting 2560 events.
[15:14:14.699] <TB0> INFO: 2560 events read in total (245ms).
[15:14:14.700] <TB0> INFO: Test took 1466ms.
[15:14:14.702] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:15.209] <TB0> INFO: Expecting 2560 events.
[15:14:16.170] <TB0> INFO: 2560 events read in total (246ms).
[15:14:16.171] <TB0> INFO: Test took 1469ms.
[15:14:16.174] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:16.680] <TB0> INFO: Expecting 2560 events.
[15:14:17.643] <TB0> INFO: 2560 events read in total (245ms).
[15:14:17.643] <TB0> INFO: Test took 1469ms.
[15:14:17.649] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:18.153] <TB0> INFO: Expecting 2560 events.
[15:14:19.116] <TB0> INFO: 2560 events read in total (247ms).
[15:14:19.117] <TB0> INFO: Test took 1469ms.
[15:14:19.123] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:19.627] <TB0> INFO: Expecting 2560 events.
[15:14:20.588] <TB0> INFO: 2560 events read in total (245ms).
[15:14:20.588] <TB0> INFO: Test took 1465ms.
[15:14:20.594] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:21.098] <TB0> INFO: Expecting 2560 events.
[15:14:22.061] <TB0> INFO: 2560 events read in total (247ms).
[15:14:22.062] <TB0> INFO: Test took 1468ms.
[15:14:22.066] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:22.571] <TB0> INFO: Expecting 2560 events.
[15:14:23.535] <TB0> INFO: 2560 events read in total (249ms).
[15:14:23.536] <TB0> INFO: Test took 1470ms.
[15:14:23.539] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:24.046] <TB0> INFO: Expecting 2560 events.
[15:14:25.006] <TB0> INFO: 2560 events read in total (245ms).
[15:14:25.007] <TB0> INFO: Test took 1468ms.
[15:14:25.011] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:25.527] <TB0> INFO: Expecting 2560 events.
[15:14:26.487] <TB0> INFO: 2560 events read in total (245ms).
[15:14:26.487] <TB0> INFO: Test took 1476ms.
[15:14:26.492] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:26.997] <TB0> INFO: Expecting 2560 events.
[15:14:27.958] <TB0> INFO: 2560 events read in total (246ms).
[15:14:27.958] <TB0> INFO: Test took 1466ms.
[15:14:27.965] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:28.470] <TB0> INFO: Expecting 2560 events.
[15:14:29.432] <TB0> INFO: 2560 events read in total (246ms).
[15:14:29.433] <TB0> INFO: Test took 1469ms.
[15:14:29.438] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:29.943] <TB0> INFO: Expecting 2560 events.
[15:14:30.905] <TB0> INFO: 2560 events read in total (247ms).
[15:14:30.910] <TB0> INFO: Test took 1472ms.
[15:14:30.913] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:31.416] <TB0> INFO: Expecting 2560 events.
[15:14:32.378] <TB0> INFO: 2560 events read in total (246ms).
[15:14:32.378] <TB0> INFO: Test took 1465ms.
[15:14:32.381] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:32.889] <TB0> INFO: Expecting 2560 events.
[15:14:33.850] <TB0> INFO: 2560 events read in total (245ms).
[15:14:33.856] <TB0> INFO: Test took 1475ms.
[15:14:33.859] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:34.360] <TB0> INFO: Expecting 2560 events.
[15:14:35.321] <TB0> INFO: 2560 events read in total (245ms).
[15:14:35.321] <TB0> INFO: Test took 1462ms.
[15:14:36.033] <TB0> INFO: PixTestPhOptimization::doTest() done, duration: 535 seconds
[15:14:36.033] <TB0> INFO: PH scale (per ROC): 80 80 74 74 73 89 82 78 75 76 74 76 75 73 67 69
[15:14:36.033] <TB0> INFO: PH offset (per ROC): 156 159 176 174 159 165 162 153 173 156 163 182 173 162 167 164
[15:14:36.041] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:14:36.041] <TB0> INFO: Decoding statistics:
[15:14:36.041] <TB0> INFO: General information:
[15:14:36.041] <TB0> INFO: 16bit words read: 66388
[15:14:36.041] <TB0> INFO: valid events total: 5120
[15:14:36.041] <TB0> INFO: empty events: 2646
[15:14:36.041] <TB0> INFO: valid events with pixels: 2474
[15:14:36.041] <TB0> INFO: valid pixel hits: 2474
[15:14:36.041] <TB0> INFO: Event errors: 0
[15:14:36.041] <TB0> INFO: start marker: 0
[15:14:36.041] <TB0> INFO: stop marker: 0
[15:14:36.041] <TB0> INFO: overflow: 0
[15:14:36.041] <TB0> INFO: invalid 5bit words: 0
[15:14:36.041] <TB0> INFO: invalid XOR eye diagram: 0
[15:14:36.041] <TB0> INFO: TBM errors: 0
[15:14:36.041] <TB0> INFO: flawed TBM headers: 0
[15:14:36.041] <TB0> INFO: flawed TBM trailers: 0
[15:14:36.041] <TB0> INFO: event ID mismatches: 0
[15:14:36.041] <TB0> INFO: ROC errors: 0
[15:14:36.041] <TB0> INFO: missing ROC header(s): 0
[15:14:36.041] <TB0> INFO: misplaced readback start: 0
[15:14:36.041] <TB0> INFO: Pixel decoding errors: 0
[15:14:36.041] <TB0> INFO: pixel data incomplete: 0
[15:14:36.041] <TB0> INFO: pixel address: 0
[15:14:36.041] <TB0> INFO: pulse height fill bit: 0
[15:14:36.042] <TB0> INFO: buffer corruption: 0
[15:14:36.341] <TB0> INFO: ######################################################################
[15:14:36.341] <TB0> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:14:36.341] <TB0> INFO: ######################################################################
[15:14:36.363] <TB0> INFO: scanning low vcal = 10
[15:14:36.694] <TB0> INFO: Expecting 41600 events.
[15:14:39.848] <TB0> INFO: 41600 events read in total (2437ms).
[15:14:39.853] <TB0> INFO: Test took 3490ms.
[15:14:39.858] <TB0> INFO: scanning low vcal = 20
[15:14:40.358] <TB0> INFO: Expecting 41600 events.
[15:14:43.523] <TB0> INFO: 41600 events read in total (2450ms).
[15:14:43.524] <TB0> INFO: Test took 3666ms.
[15:14:43.529] <TB0> INFO: scanning low vcal = 30
[15:14:44.033] <TB0> INFO: Expecting 41600 events.
[15:14:47.233] <TB0> INFO: 41600 events read in total (2485ms).
[15:14:47.235] <TB0> INFO: Test took 3706ms.
[15:14:47.239] <TB0> INFO: scanning low vcal = 40
[15:14:47.727] <TB0> INFO: Expecting 41600 events.
[15:14:51.421] <TB0> INFO: 41600 events read in total (2979ms).
[15:14:51.423] <TB0> INFO: Test took 4183ms.
[15:14:51.429] <TB0> INFO: scanning low vcal = 50
[15:14:51.821] <TB0> INFO: Expecting 41600 events.
[15:14:55.581] <TB0> INFO: 41600 events read in total (3045ms).
[15:14:55.582] <TB0> INFO: Test took 4153ms.
[15:14:55.588] <TB0> INFO: scanning low vcal = 60
[15:14:55.975] <TB0> INFO: Expecting 41600 events.
[15:14:59.816] <TB0> INFO: 41600 events read in total (3126ms).
[15:14:59.818] <TB0> INFO: Test took 4230ms.
[15:14:59.823] <TB0> INFO: scanning low vcal = 70
[15:15:00.249] <TB0> INFO: Expecting 41600 events.
[15:15:04.018] <TB0> INFO: 41600 events read in total (3054ms).
[15:15:04.020] <TB0> INFO: Test took 4197ms.
[15:15:04.027] <TB0> INFO: scanning low vcal = 80
[15:15:04.422] <TB0> INFO: Expecting 41600 events.
[15:15:08.293] <TB0> INFO: 41600 events read in total (3155ms).
[15:15:08.295] <TB0> INFO: Test took 4268ms.
[15:15:08.299] <TB0> INFO: scanning low vcal = 90
[15:15:08.723] <TB0> INFO: Expecting 41600 events.
[15:15:12.697] <TB0> INFO: 41600 events read in total (3253ms).
[15:15:12.698] <TB0> INFO: Test took 4399ms.
[15:15:12.706] <TB0> INFO: scanning low vcal = 100
[15:15:13.138] <TB0> INFO: Expecting 41600 events.
[15:15:16.889] <TB0> INFO: 41600 events read in total (3035ms).
[15:15:16.890] <TB0> INFO: Test took 4184ms.
[15:15:16.895] <TB0> INFO: scanning low vcal = 110
[15:15:17.309] <TB0> INFO: Expecting 41600 events.
[15:15:21.096] <TB0> INFO: 41600 events read in total (3071ms).
[15:15:21.098] <TB0> INFO: Test took 4203ms.
[15:15:21.106] <TB0> INFO: scanning low vcal = 120
[15:15:21.506] <TB0> INFO: Expecting 41600 events.
[15:15:25.290] <TB0> INFO: 41600 events read in total (3069ms).
[15:15:25.291] <TB0> INFO: Test took 4185ms.
[15:15:25.297] <TB0> INFO: scanning low vcal = 130
[15:15:25.681] <TB0> INFO: Expecting 41600 events.
[15:15:29.448] <TB0> INFO: 41600 events read in total (3052ms).
[15:15:29.450] <TB0> INFO: Test took 4152ms.
[15:15:29.457] <TB0> INFO: scanning low vcal = 140
[15:15:29.885] <TB0> INFO: Expecting 41600 events.
[15:15:33.662] <TB0> INFO: 41600 events read in total (3061ms).
[15:15:33.662] <TB0> INFO: Test took 4205ms.
[15:15:33.668] <TB0> INFO: scanning low vcal = 150
[15:15:34.080] <TB0> INFO: Expecting 41600 events.
[15:15:37.898] <TB0> INFO: 41600 events read in total (3103ms).
[15:15:37.899] <TB0> INFO: Test took 4231ms.
[15:15:37.905] <TB0> INFO: scanning low vcal = 160
[15:15:38.288] <TB0> INFO: Expecting 41600 events.
[15:15:42.112] <TB0> INFO: 41600 events read in total (3109ms).
[15:15:42.114] <TB0> INFO: Test took 4209ms.
[15:15:42.120] <TB0> INFO: scanning low vcal = 170
[15:15:42.541] <TB0> INFO: Expecting 41600 events.
[15:15:46.298] <TB0> INFO: 41600 events read in total (3042ms).
[15:15:46.299] <TB0> INFO: Test took 4179ms.
[15:15:46.313] <TB0> INFO: scanning low vcal = 180
[15:15:46.703] <TB0> INFO: Expecting 41600 events.
[15:15:50.491] <TB0> INFO: 41600 events read in total (3073ms).
[15:15:50.494] <TB0> INFO: Test took 4181ms.
[15:15:50.501] <TB0> INFO: scanning low vcal = 190
[15:15:50.895] <TB0> INFO: Expecting 41600 events.
[15:15:54.744] <TB0> INFO: 41600 events read in total (3133ms).
[15:15:54.747] <TB0> INFO: Test took 4245ms.
[15:15:54.757] <TB0> INFO: scanning low vcal = 200
[15:15:55.185] <TB0> INFO: Expecting 41600 events.
[15:15:58.978] <TB0> INFO: 41600 events read in total (3072ms).
[15:15:58.980] <TB0> INFO: Test took 4220ms.
[15:15:58.987] <TB0> INFO: scanning low vcal = 210
[15:15:59.384] <TB0> INFO: Expecting 41600 events.
[15:16:03.212] <TB0> INFO: 41600 events read in total (3113ms).
[15:16:03.214] <TB0> INFO: Test took 4226ms.
[15:16:03.223] <TB0> INFO: scanning low vcal = 220
[15:16:03.632] <TB0> INFO: Expecting 41600 events.
[15:16:07.567] <TB0> INFO: 41600 events read in total (3220ms).
[15:16:07.578] <TB0> INFO: Test took 4351ms.
[15:16:07.591] <TB0> INFO: scanning low vcal = 230
[15:16:08.042] <TB0> INFO: Expecting 41600 events.
[15:16:11.852] <TB0> INFO: 41600 events read in total (3095ms).
[15:16:11.854] <TB0> INFO: Test took 4256ms.
[15:16:11.867] <TB0> INFO: scanning low vcal = 240
[15:16:12.266] <TB0> INFO: Expecting 41600 events.
[15:16:16.055] <TB0> INFO: 41600 events read in total (3074ms).
[15:16:16.058] <TB0> INFO: Test took 4189ms.
[15:16:16.069] <TB0> INFO: scanning low vcal = 250
[15:16:16.446] <TB0> INFO: Expecting 41600 events.
[15:16:20.561] <TB0> INFO: 41600 events read in total (3399ms).
[15:16:20.564] <TB0> INFO: Test took 4495ms.
[15:16:20.576] <TB0> INFO: scanning high vcal = 30 (= 210 in low range)
[15:16:21.115] <TB0> INFO: Expecting 41600 events.
[15:16:25.041] <TB0> INFO: 41600 events read in total (3206ms).
[15:16:25.042] <TB0> INFO: Test took 4463ms.
[15:16:25.048] <TB0> INFO: scanning high vcal = 50 (= 350 in low range)
[15:16:25.459] <TB0> INFO: Expecting 41600 events.
[15:16:29.341] <TB0> INFO: 41600 events read in total (3167ms).
[15:16:29.345] <TB0> INFO: Test took 4297ms.
[15:16:29.352] <TB0> INFO: scanning high vcal = 70 (= 490 in low range)
[15:16:29.834] <TB0> INFO: Expecting 41600 events.
[15:16:33.629] <TB0> INFO: 41600 events read in total (3080ms).
[15:16:33.631] <TB0> INFO: Test took 4279ms.
[15:16:33.638] <TB0> INFO: scanning high vcal = 90 (= 630 in low range)
[15:16:34.043] <TB0> INFO: Expecting 41600 events.
[15:16:37.962] <TB0> INFO: 41600 events read in total (3204ms).
[15:16:37.963] <TB0> INFO: Test took 4324ms.
[15:16:37.969] <TB0> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:16:38.374] <TB0> INFO: Expecting 41600 events.
[15:16:42.224] <TB0> INFO: 41600 events read in total (3134ms).
[15:16:42.226] <TB0> INFO: Test took 4257ms.
[15:16:43.521] <TB0> INFO: PixTestGainPedestal::measure() done
[15:18:12.693] <TB0> INFO: PixTestGainPedestal::fit() done
[15:18:12.693] <TB0> INFO: non-linearity mean: 0.957 0.959 0.961 0.952 0.962 0.956 0.964 0.958 0.951 0.956 0.958 0.955 0.960 0.959 0.957 0.961
[15:18:12.693] <TB0> INFO: non-linearity RMS: 0.007 0.005 0.005 0.007 0.005 0.006 0.005 0.006 0.007 0.005 0.006 0.006 0.006 0.007 0.006 0.006
[15:18:12.693] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[15:18:12.728] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[15:18:12.764] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[15:18:12.800] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[15:18:12.835] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[15:18:12.870] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[15:18:12.905] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[15:18:12.939] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[15:18:12.974] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[15:18:13.008] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[15:18:13.044] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[15:18:13.078] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[15:18:13.114] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[15:18:13.149] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[15:18:13.184] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[15:18:13.219] <TB0> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[15:18:13.254] <TB0> INFO: PixTestGainPedestal::doTest() done, duration: 216 seconds
[15:18:13.254] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:18:13.254] <TB0> INFO: Decoding statistics:
[15:18:13.254] <TB0> INFO: General information:
[15:18:13.254] <TB0> INFO: 16bit words read: 2329348
[15:18:13.254] <TB0> INFO: valid events total: 83200
[15:18:13.254] <TB0> INFO: empty events: 0
[15:18:13.254] <TB0> INFO: valid events with pixels: 83200
[15:18:13.254] <TB0> INFO: valid pixel hits: 665474
[15:18:13.254] <TB0> INFO: Event errors: 0
[15:18:13.254] <TB0> INFO: start marker: 0
[15:18:13.254] <TB0> INFO: stop marker: 0
[15:18:13.254] <TB0> INFO: overflow: 0
[15:18:13.254] <TB0> INFO: invalid 5bit words: 0
[15:18:13.254] <TB0> INFO: invalid XOR eye diagram: 0
[15:18:13.254] <TB0> INFO: TBM errors: 0
[15:18:13.254] <TB0> INFO: flawed TBM headers: 0
[15:18:13.254] <TB0> INFO: flawed TBM trailers: 0
[15:18:13.254] <TB0> INFO: event ID mismatches: 0
[15:18:13.254] <TB0> INFO: ROC errors: 0
[15:18:13.254] <TB0> INFO: missing ROC header(s): 0
[15:18:13.254] <TB0> INFO: misplaced readback start: 0
[15:18:13.254] <TB0> INFO: Pixel decoding errors: 0
[15:18:13.254] <TB0> INFO: pixel data incomplete: 0
[15:18:13.254] <TB0> INFO: pixel address: 0
[15:18:13.254] <TB0> INFO: pulse height fill bit: 0
[15:18:13.255] <TB0> INFO: buffer corruption: 0
[15:18:13.266] <TB0> INFO: readReadbackCal: /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C0.dat .. /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C15.dat
[15:18:13.269] <TB0> INFO: ######################################################################
[15:18:13.269] <TB0> INFO: PixTestTrim::doTest()
[15:18:13.269] <TB0> INFO: ######################################################################
[15:18:13.273] <TB0> INFO: PixTestReadback::RES sent once
[15:18:24.742] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C0.dat
[15:18:24.742] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C1.dat
[15:18:24.742] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C2.dat
[15:18:24.742] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C3.dat
[15:18:24.743] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C4.dat
[15:18:24.743] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C5.dat
[15:18:24.743] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C6.dat
[15:18:24.743] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C7.dat
[15:18:24.743] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C8.dat
[15:18:24.743] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C9.dat
[15:18:24.743] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C10.dat
[15:18:24.744] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C11.dat
[15:18:24.744] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C12.dat
[15:18:24.744] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C13.dat
[15:18:24.744] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C14.dat
[15:18:24.744] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C15.dat
[15:18:24.792] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[15:18:24.794] <TB0> INFO: PixTestReadback::RES sent once
[15:18:36.184] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C0.dat
[15:18:36.185] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C1.dat
[15:18:36.187] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C2.dat
[15:18:36.191] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C3.dat
[15:18:36.191] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C4.dat
[15:18:36.191] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C5.dat
[15:18:36.191] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C6.dat
[15:18:36.191] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C7.dat
[15:18:36.191] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C8.dat
[15:18:36.192] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C9.dat
[15:18:36.192] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C10.dat
[15:18:36.192] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C11.dat
[15:18:36.192] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C12.dat
[15:18:36.192] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C13.dat
[15:18:36.192] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C14.dat
[15:18:36.192] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C15.dat
[15:18:36.232] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[15:18:36.235] <TB0> INFO: PixTestReadback::RES sent once
[15:18:44.922] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[15:18:44.922] <TB0> INFO: Vbg will be calibrated using Vd calibration
[15:18:44.922] <TB0> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 153.6calibrated Vbg = 1.18862 :::*/*/*/*/
[15:18:44.922] <TB0> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 160calibrated Vbg = 1.1846 :::*/*/*/*/
[15:18:44.922] <TB0> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 150.7calibrated Vbg = 1.1933 :::*/*/*/*/
[15:18:44.922] <TB0> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 161.4calibrated Vbg = 1.20224 :::*/*/*/*/
[15:18:44.922] <TB0> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 144.4calibrated Vbg = 1.199 :::*/*/*/*/
[15:18:44.923] <TB0> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 166.2calibrated Vbg = 1.20739 :::*/*/*/*/
[15:18:44.923] <TB0> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 151.2calibrated Vbg = 1.19679 :::*/*/*/*/
[15:18:44.923] <TB0> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 145calibrated Vbg = 1.20623 :::*/*/*/*/
[15:18:44.923] <TB0> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 151.3calibrated Vbg = 1.20743 :::*/*/*/*/
[15:18:44.923] <TB0> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 151.7calibrated Vbg = 1.20386 :::*/*/*/*/
[15:18:44.923] <TB0> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 149.5calibrated Vbg = 1.21372 :::*/*/*/*/
[15:18:44.923] <TB0> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 155.7calibrated Vbg = 1.20231 :::*/*/*/*/
[15:18:44.923] <TB0> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 147.9calibrated Vbg = 1.19837 :::*/*/*/*/
[15:18:44.923] <TB0> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 145.4calibrated Vbg = 1.18857 :::*/*/*/*/
[15:18:44.923] <TB0> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 155.3calibrated Vbg = 1.18963 :::*/*/*/*/
[15:18:44.923] <TB0> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 168.4calibrated Vbg = 1.18876 :::*/*/*/*/
[15:18:44.927] <TB0> INFO: PixTestReadback::RES sent once
[15:18:45.733] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (6) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (6) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (6) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (6) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (6) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (6) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (6) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.735] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.736] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:18:45.736] <TB0> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (7) != Token Chain Length (8)
[15:21:40.926] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C0.dat
[15:21:40.927] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C1.dat
[15:21:40.927] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C2.dat
[15:21:40.927] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C3.dat
[15:21:40.927] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C4.dat
[15:21:40.927] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C5.dat
[15:21:40.928] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C6.dat
[15:21:40.928] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C7.dat
[15:21:40.929] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C8.dat
[15:21:40.929] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C9.dat
[15:21:40.929] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C10.dat
[15:21:40.929] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C11.dat
[15:21:40.930] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C12.dat
[15:21:40.931] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C13.dat
[15:21:40.932] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C14.dat
[15:21:40.934] <TB0> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3512_FullQualification_2015-10-29_13h38m_1446122315//001_Fulltest_m20//readbackCal_C15.dat
[15:21:40.976] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[15:21:40.978] <TB0> INFO: PixTestReadback::doTest() done
[15:21:40.978] <TB0> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:21:40.978] <TB0> INFO: Decoding statistics:
[15:21:40.978] <TB0> INFO: General information:
[15:21:40.978] <TB0> INFO: 16bit words read: 768
[15:21:40.978] <TB0> INFO: valid events total: 64
[15:21:40.978] <TB0> INFO: empty events: 64
[15:21:40.978] <TB0> INFO: valid events with pixels: 0
[15:21:40.978] <TB0> INFO: valid pixel hits: 0
[15:21:40.978] <TB0> INFO: Event errors: 0
[15:21:40.978] <TB0> INFO: start marker: 0
[15:21:40.978] <TB0> INFO: stop marker: 0
[15:21:40.978] <TB0> INFO: overflow: 0
[15:21:40.978] <TB0> INFO: invalid 5bit words: 0
[15:21:40.978] <TB0> INFO: invalid XOR eye diagram: 0
[15:21:40.978] <TB0> INFO: TBM errors: 0
[15:21:40.978] <TB0> INFO: flawed TBM headers: 0
[15:21:40.978] <TB0> INFO: flawed TBM trailers: 0
[15:21:40.978] <TB0> INFO: event ID mismatches: 0
[15:21:40.978] <TB0> INFO: ROC errors: 0
[15:21:40.978] <TB0> INFO: missing ROC header(s): 0
[15:21:40.979] <TB0> INFO: misplaced readback start: 0
[15:21:40.979] <TB0> INFO: Pixel decoding errors: 0
[15:21:40.979] <TB0> INFO: pixel data incomplete: 0
[15:21:40.979] <TB0> INFO: pixel address: 0
[15:21:40.979] <TB0> INFO: pulse height fill bit: 0
[15:21:40.979] <TB0> INFO: buffer corruption: 0
[15:21:41.007] <TB0> INFO: Decoding statistics:
[15:21:41.007] <TB0> INFO: General information:
[15:21:41.007] <TB0> INFO: 16bit words read: 9581238
[15:21:41.007] <TB0> INFO: valid events total: 551744
[15:21:41.007] <TB0> INFO: empty events: 264646
[15:21:41.007] <TB0> INFO: valid events with pixels: 287098
[15:21:41.007] <TB0> INFO: valid pixel hits: 1480155
[15:21:41.007] <TB0> INFO: Event errors: 0
[15:21:41.007] <TB0> INFO: start marker: 0
[15:21:41.007] <TB0> INFO: stop marker: 0
[15:21:41.007] <TB0> INFO: overflow: 0
[15:21:41.007] <TB0> INFO: invalid 5bit words: 0
[15:21:41.007] <TB0> INFO: invalid XOR eye diagram: 0
[15:21:41.007] <TB0> INFO: TBM errors: 0
[15:21:41.007] <TB0> INFO: flawed TBM headers: 0
[15:21:41.007] <TB0> INFO: flawed TBM trailers: 0
[15:21:41.007] <TB0> INFO: event ID mismatches: 0
[15:21:41.007] <TB0> INFO: ROC errors: 0
[15:21:41.007] <TB0> INFO: missing ROC header(s): 0
[15:21:41.007] <TB0> INFO: misplaced readback start: 0
[15:21:41.008] <TB0> INFO: Pixel decoding errors: 0
[15:21:41.008] <TB0> INFO: pixel data incomplete: 0
[15:21:41.008] <TB0> INFO: pixel address: 0
[15:21:41.008] <TB0> INFO: pulse height fill bit: 0
[15:21:41.008] <TB0> INFO: buffer corruption: 0
[15:21:41.008] <TB0> INFO: enter test to run
[15:21:41.008] <TB0> INFO: test: no parameter change
[15:21:41.422] <TB0> QUIET: Connection to board 127 closed.
[15:21:41.427] <TB0> INFO: pXar: this is the end, my friend