[13:29:02.805] INFO: === Welcome to pxar ===
[13:29:02.805] INFO: === Today: 2015/09/11
[13:29:02.805] INFO: readRocDacs: M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C0.dat .. M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C15.dat
[13:29:02.805] INFO: readTbmDacs: M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/tbmParameters_C0a.dat .. M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/tbmParameters_C0b.dat
[13:29:02.805] INFO: readMaskFile: M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/defaultMaskFile.dat
[13:29:02.805] INFO: readTrimFile: M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters_C0.dat .. M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters_C15.dat
[13:29:02.875] INFO: clk: 4
[13:29:02.875] INFO: ctr: 4
[13:29:02.875] INFO: sda: 19
[13:29:02.875] INFO: tin: 9
[13:29:02.875] INFO: level: 15
[13:29:02.875] INFO: triggerdelay: 0
[13:29:02.875] QUIET: Instanciating API for pxar prod-10+20~g6580e80
[13:29:02.875] INFO: Log level: INFO
[13:29:02.885] INFO: Found DTB DTB_WS6C22
[13:29:02.903] QUIET: Connection to board DTB_WS6C22 opened.
[13:29:02.906] INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 74
HW version: DTB1.2
FW version: 4.2
SW version: 4.4
USB id: DTB_WS6C22
MAC address: 40D85511804A
Hostname: pixelDTB074
Comment:
------------------------------------------------------
[13:29:02.909] INFO: RPC call hashes of host and DTB match: 397073690
[13:29:04.518] INFO: DUT info:
[13:29:04.518] INFO: The DUT currently contains the following objects:
[13:29:04.518] INFO: 2 TBM Cores tbm08c (2 ON)
[13:29:04.518] INFO: TBM Core alpha (0): 7 registers set
[13:29:04.518] INFO: TBM Core beta (1): 7 registers set
[13:29:04.518] INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[13:29:04.518] INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.518] INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.518] INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.518] INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.518] INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.518] INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.518] INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.518] INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.518] INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.518] INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.518] INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.519] INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.519] INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.519] INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.519] INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.519] INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:29:04.920] INFO: enter 'restricted' command line mode
[13:29:04.920] INFO: enter test to run
[13:29:04.920] INFO: test: Pretest no parameter change
[13:29:04.920] INFO: running: pretest
[13:29:04.927] INFO: ######################################################################
[13:29:04.927] INFO: PixTestPretest::doTest()
[13:29:04.927] INFO: ######################################################################
[13:29:04.929] INFO: ----------------------------------------------------------------------
[13:29:04.929] INFO: PixTestPretest::programROC()
[13:29:04.929] INFO: ----------------------------------------------------------------------
[13:29:22.953] INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:29:22.953] INFO: IA differences per ROC: 16.1 20.9 17.7 17.7 20.1 20.1 19.3 17.7 20.1 19.3 18.5 17.7 17.7 19.3 19.3 17.7
[13:29:23.030] INFO: ----------------------------------------------------------------------
[13:29:23.030] INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:29:23.030] INFO: ----------------------------------------------------------------------
[13:29:27.533] INFO: PixTestPretest::setVana() done, Module Ia 384.3 mA = 24.0187 mA/ROC
[13:29:27.535] INFO: ----------------------------------------------------------------------
[13:29:27.535] INFO: PixTestPretest::findTiming()
[13:29:27.535] INFO: ----------------------------------------------------------------------
[13:29:27.535] INFO: PixTestCmd::init()
[13:29:28.169] WARNING: Not unmasking DUT, not setting Calibrate bits!
[13:31:07.307] INFO: TBM phases: 160MHz: 7, 400MHz: 6, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[13:31:07.307] INFO: (success/tries = 100/100), width = 4
[13:31:07.309] INFO: ----------------------------------------------------------------------
[13:31:07.309] INFO: PixTestPretest::findWorkingPixel()
[13:31:07.309] INFO: ----------------------------------------------------------------------
[13:31:07.451] INFO: Expecting 231680 events.
[13:31:12.641] ERROR: <datapipe.cc/CheckEventValidity:L480> Channel 0 Number of ROCs (1) != Token Chain Length (8)
[13:31:12.644] ERROR: <datapipe.cc/CheckEventID:L453> Channel 0 Event ID mismatch: local ID (21) != TBM ID (2)
[13:31:15.330] INFO: 231680 events read in total (7100ms).
[13:31:15.335] INFO: Test took 8023ms.
[13:31:15.811] INFO: Found working pixel in all ROCs: col/row = 12/22
[13:31:15.861] INFO: ----------------------------------------------------------------------
[13:31:15.861] INFO: PixTestPretest::setVthrCompCalDel()
[13:31:15.861] INFO: ----------------------------------------------------------------------
[13:31:15.000] INFO: Expecting 231680 events.
[13:31:23.782] INFO: 231680 events read in total (7003ms).
[13:31:23.786] INFO: Test took 7919ms.
[13:31:24.291] INFO: PixTestPretest::setVthrCompCalDel() done
[13:31:24.291] INFO: CalDel: 150 143 140 142 163 149 154 148 138 141 146 134 132 169 129 133
[13:31:24.291] INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[13:31:24.294] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C0.dat
[13:31:24.294] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C1.dat
[13:31:24.294] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C2.dat
[13:31:24.295] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C3.dat
[13:31:24.295] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C4.dat
[13:31:24.295] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C5.dat
[13:31:24.295] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C6.dat
[13:31:24.295] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C7.dat
[13:31:24.296] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C8.dat
[13:31:24.296] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C9.dat
[13:31:24.296] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C10.dat
[13:31:24.296] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C11.dat
[13:31:24.296] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C12.dat
[13:31:24.296] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C13.dat
[13:31:24.297] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C14.dat
[13:31:24.297] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters_C15.dat
[13:31:24.297] INFO: write tbm parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/tbmParameters_C0a.dat
[13:31:24.297] INFO: write tbm parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/tbmParameters_C0b.dat
[13:31:24.297] INFO: PixTestPretest::doTest() done, duration: 139 seconds
[13:31:24.360] INFO: enter test to run
[13:31:24.360] INFO: test: FullTest no parameter change
[13:31:24.360] INFO: running: fulltest
[13:31:24.360] INFO: ######################################################################
[13:31:24.360] INFO: PixTestFullTest::doTest()
[13:31:24.360] INFO: ######################################################################
[13:31:24.362] INFO: ######################################################################
[13:31:24.362] INFO: PixTestAlive::doTest()
[13:31:24.362] INFO: ######################################################################
[13:31:24.364] INFO: ----------------------------------------------------------------------
[13:31:24.364] INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:31:24.364] INFO: ----------------------------------------------------------------------
[13:31:24.720] INFO: Expecting 41600 events.
[13:31:28.875] INFO: 41600 events read in total (3376ms).
[13:31:28.876] INFO: Test took 4510ms.
[13:31:28.882] INFO: Fetched DAQ statistics. Counters are being reset now.
[13:31:29.342] INFO: PixTestAlive::aliveTest() done
[13:31:29.342] INFO: number of dead pixels per ROC: 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0
[13:31:29.344] INFO: ----------------------------------------------------------------------
[13:31:29.344] INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:31:29.344] INFO: ----------------------------------------------------------------------
[13:31:29.700] INFO: Expecting 41600 events.
[13:31:32.595] INFO: 41600 events read in total (2116ms).
[13:31:32.595] INFO: Test took 3249ms.
[13:31:32.595] INFO: Fetched DAQ statistics. Counters are being reset now.
[13:31:32.596] INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[13:31:33.081] INFO: PixTestAlive::maskTest() done
[13:31:33.081] INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:31:33.083] INFO: ----------------------------------------------------------------------
[13:31:33.083] INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:31:33.083] INFO: ----------------------------------------------------------------------
[13:31:33.442] INFO: Expecting 41600 events.
[13:31:37.597] INFO: 41600 events read in total (3376ms).
[13:31:37.598] INFO: Test took 4513ms.
[13:31:37.604] INFO: Fetched DAQ statistics. Counters are being reset now.
[13:31:38.060] INFO: PixTestAlive::addressDecodingTest() done
[13:31:38.060] INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:31:38.060] INFO: PixTestAlive::doTest() done, duration: 13 seconds
[13:31:38.071] INFO: ######################################################################
[13:31:38.071] INFO: PixTestBBMap::doTest() Ntrig = 16, VcalS = 250 (high range)
[13:31:38.071] INFO: ######################################################################
[13:31:38.075] INFO: ---> dac: VthrComp name: calSMap ntrig: 16 dacrange: 0 .. 149 (-1/-1) hits flags = 2 (plus default)
[13:31:38.103] INFO: dacScan split into 1 runs with ntrig = 16
[13:31:38.104] INFO: run 1 of 1
[13:31:38.457] INFO: Expecting 9984000 events.
[13:32:06.850] INFO: 1213280 events read in total (27614ms).
[13:32:34.390] INFO: 2414544 events read in total (55155ms).
[13:33:01.932] INFO: 3608848 events read in total (82697ms).
[13:33:29.389] INFO: 4798208 events read in total (110153ms).
[13:33:56.902] INFO: 5990336 events read in total (137666ms).
[13:34:24.391] INFO: 7190624 events read in total (165155ms).
[13:34:52.011] INFO: 8397536 events read in total (192775ms).
[13:35:19.334] INFO: 9613424 events read in total (220099ms).
[13:35:27.334] INFO: 9984000 events read in total (228098ms).
[13:35:27.374] INFO: Test took 229270ms.
[13:35:27.465] INFO: Fetched DAQ statistics. Counters are being reset now.
[13:35:47.642] INFO: PixTestBBMap::doTest() done, duration: 249 seconds
[13:35:47.642] INFO: number of dead bumps (per ROC): 0 3 2 0 1 1 0 0 0 0 1 0 2 0 0 0
[13:35:47.642] INFO: separation cut (per ROC): 102 124 130 119 112 113 110 123 116 126 106 105 103 105 117 105
[13:35:47.710] INFO: ######################################################################
[13:35:47.710] INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:35:47.710] INFO: ######################################################################
[13:35:47.710] INFO: ----------------------------------------------------------------------
[13:35:47.710] INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:35:47.710] INFO: ----------------------------------------------------------------------
[13:35:47.710] INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 0 .. 149 (-1/-1) hits flags = 16 (plus default)
[13:35:47.720] INFO: dacScan split into 1 runs with ntrig = 50
[13:35:47.720] INFO: run 1 of 1
[13:35:48.070] INFO: Expecting 31200000 events.
[13:36:12.753] INFO: 1183300 events read in total (23904ms).
[13:36:36.524] INFO: 2344850 events read in total (47675ms).
[13:37:00.286] INFO: 3501850 events read in total (71437ms).
[13:37:23.931] INFO: 4656700 events read in total (95083ms).
[13:37:47.573] INFO: 5811000 events read in total (118724ms).
[13:38:11.193] INFO: 6959800 events read in total (142344ms).
[13:38:34.232] INFO: 8109050 events read in total (165383ms).
[13:38:57.927] INFO: 9255350 events read in total (189078ms).
[13:39:21.653] INFO: 10401150 events read in total (212804ms).
[13:39:45.403] INFO: 11546750 events read in total (236554ms).
[13:40:09.177] INFO: 12687750 events read in total (260328ms).
[13:40:32.892] INFO: 13827900 events read in total (284043ms).
[13:40:56.599] INFO: 14964750 events read in total (307750ms).
[13:41:20.208] INFO: 16093450 events read in total (331359ms).
[13:41:43.841] INFO: 17217950 events read in total (354992ms).
[13:42:07.385] INFO: 18339400 events read in total (378536ms).
[13:42:30.934] INFO: 19457450 events read in total (402085ms).
[13:42:54.439] INFO: 20573700 events read in total (425590ms).
[13:43:17.922] INFO: 21689550 events read in total (449073ms).
[13:43:41.371] INFO: 22803050 events read in total (472522ms).
[13:44:04.820] INFO: 23913050 events read in total (495972ms).
[13:44:28.242] INFO: 25023700 events read in total (519393ms).
[13:44:51.641] INFO: 26134300 events read in total (542792ms).
[13:45:15.032] INFO: 27243350 events read in total (566183ms).
[13:45:38.345] INFO: 28354850 events read in total (589496ms).
[13:46:01.697] INFO: 29465150 events read in total (612848ms).
[13:46:24.670] INFO: 30574200 events read in total (635821ms).
[13:46:37.413] INFO: 31200000 events read in total (648564ms).
[13:46:37.460] INFO: Test took 649740ms.
[13:46:37.571] INFO: Fetched DAQ statistics. Counters are being reset now.
[13:46:37.808] INFO: dumping ASCII scurve output file: SCurveData
[13:46:39.354] INFO: dumping ASCII scurve output file: SCurveData
[13:46:40.835] INFO: dumping ASCII scurve output file: SCurveData
[13:46:42.265] INFO: dumping ASCII scurve output file: SCurveData
[13:46:43.700] INFO: dumping ASCII scurve output file: SCurveData
[13:46:45.184] INFO: dumping ASCII scurve output file: SCurveData
[13:46:46.647] INFO: dumping ASCII scurve output file: SCurveData
[13:46:48.115] INFO: dumping ASCII scurve output file: SCurveData
[13:46:49.568] INFO: dumping ASCII scurve output file: SCurveData
[13:46:51.024] INFO: dumping ASCII scurve output file: SCurveData
[13:46:52.458] INFO: dumping ASCII scurve output file: SCurveData
[13:46:53.938] INFO: dumping ASCII scurve output file: SCurveData
[13:46:55.415] INFO: dumping ASCII scurve output file: SCurveData
[13:46:56.921] INFO: dumping ASCII scurve output file: SCurveData
[13:46:58.434] INFO: dumping ASCII scurve output file: SCurveData
[13:46:59.912] INFO: dumping ASCII scurve output file: SCurveData
[13:47:01.454] INFO: PixTestScurves::scurves() done
[13:47:01.454] INFO: Vcal mean: 72.59 92.77 112.07 102.48 84.40 85.86 83.85 89.02 87.54 100.76 82.78 82.90 72.02 77.98 92.28 88.75
[13:47:01.455] INFO: Vcal RMS: 4.62 5.13 5.31 6.10 4.75 5.20 4.89 6.32 5.09 6.23 4.88 5.46 5.21 4.54 8.56 5.69
[13:47:01.455] INFO: PixTestScurves::fullTest() done, duration: 673 seconds
[13:47:01.530] INFO: ######################################################################
[13:47:01.530] INFO: PixTestTrim::doTest()
[13:47:01.530] INFO: ######################################################################
[13:47:01.531] INFO: ----------------------------------------------------------------------
[13:47:01.531] INFO: PixTestTrim::trimTest() ntrig = 20, vcal = 35
[13:47:01.531] INFO: ----------------------------------------------------------------------
[13:47:01.611] INFO: ---> VthrComp thr map (minimal VthrComp)
[13:47:01.611] INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[13:47:01.621] INFO: dacScan split into 1 runs with ntrig = 20
[13:47:01.621] INFO: run 1 of 1
[13:47:01.970] INFO: Expecting 13312000 events.
[13:47:31.605] INFO: 1446320 events read in total (28850ms).
[13:48:00.463] INFO: 2886340 events read in total (57708ms).
[13:48:29.377] INFO: 4322520 events read in total (86622ms).
[13:48:58.199] INFO: 5749740 events read in total (115444ms).
[13:49:27.108] INFO: 7177900 events read in total (144353ms).
[13:49:56.135] INFO: 8614780 events read in total (173380ms).
[13:50:25.050] INFO: 10053500 events read in total (202295ms).
[13:50:54.154] INFO: 11496320 events read in total (231399ms).
[13:51:22.714] INFO: 12939600 events read in total (259959ms).
[13:51:29.975] INFO: 13312000 events read in total (267220ms).
[13:51:30.018] INFO: Test took 268397ms.
[13:51:30.081] INFO: Fetched DAQ statistics. Counters are being reset now.
[13:51:48.600] INFO: ROC 0 VthrComp = 75
[13:51:48.601] INFO: ROC 1 VthrComp = 98
[13:51:48.601] INFO: ROC 2 VthrComp = 107
[13:51:48.601] INFO: ROC 3 VthrComp = 99
[13:51:48.601] INFO: ROC 4 VthrComp = 87
[13:51:48.601] INFO: ROC 5 VthrComp = 87
[13:51:48.602] INFO: ROC 6 VthrComp = 86
[13:51:48.602] INFO: ROC 7 VthrComp = 92
[13:51:48.602] INFO: ROC 8 VthrComp = 92
[13:51:48.602] INFO: ROC 9 VthrComp = 100
[13:51:48.602] INFO: ROC 10 VthrComp = 85
[13:51:48.603] INFO: ROC 11 VthrComp = 85
[13:51:48.603] INFO: ROC 12 VthrComp = 78
[13:51:48.603] INFO: ROC 13 VthrComp = 80
[13:51:48.603] INFO: ROC 14 VthrComp = 88
[13:51:48.604] INFO: ROC 15 VthrComp = 88
[13:51:48.604] INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:51:48.604] INFO: ---> dac: vcal name: TrimThr1 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[13:51:48.617] INFO: dacScan split into 1 runs with ntrig = 20
[13:51:48.617] INFO: run 1 of 1
[13:51:48.966] INFO: Expecting 13312000 events.
[13:52:13.787] INFO: 920800 events read in total (24042ms).
[13:52:37.693] INFO: 1839140 events read in total (47948ms).
[13:53:01.773] INFO: 2755060 events read in total (72028ms).
[13:53:25.866] INFO: 3672840 events read in total (96121ms).
[13:53:49.995] INFO: 4590420 events read in total (120250ms).
[13:54:14.142] INFO: 5508660 events read in total (144397ms).
[13:54:38.210] INFO: 6427920 events read in total (168465ms).
[13:55:02.185] INFO: 7339880 events read in total (192440ms).
[13:55:26.177] INFO: 8249020 events read in total (216432ms).
[13:55:50.119] INFO: 9154980 events read in total (240374ms).
[13:56:14.084] INFO: 10059460 events read in total (264339ms).
[13:56:38.033] INFO: 10962300 events read in total (288288ms).
[13:57:01.931] INFO: 11864280 events read in total (312186ms).
[13:57:25.482] INFO: 12766100 events read in total (335737ms).
[13:57:39.683] INFO: 13312000 events read in total (349938ms).
[13:57:39.735] INFO: Test took 351118ms.
[13:57:39.903] INFO: Fetched DAQ statistics. Counters are being reset now.
[13:58:03.852] INFO: roc 0 with ID = 0 has maximal Vcal 58.3294 for pixel 0/36 mean/min/max = 46.3346/34.2853/58.3839
[13:58:03.852] INFO: roc 1 with ID = 1 has maximal Vcal 57.0019 for pixel 51/56 mean/min/max = 44.4428/31.8783/57.0073
[13:58:03.852] INFO: roc 2 with ID = 2 has maximal Vcal 64.7078 for pixel 14/77 mean/min/max = 49.4801/34.1258/64.8345
[13:58:03.853] INFO: roc 3 with ID = 3 has maximal Vcal 61.6499 for pixel 11/2 mean/min/max = 46.6775/31.6532/61.7017
[13:58:03.853] INFO: roc 4 with ID = 4 has maximal Vcal 57.6573 for pixel 15/74 mean/min/max = 45.017/32.3665/57.6675
[13:58:03.853] INFO: roc 5 with ID = 5 has maximal Vcal 58.6885 for pixel 18/79 mean/min/max = 45.5414/32.3906/58.6923
[13:58:03.854] INFO: roc 6 with ID = 6 has maximal Vcal 58.095 for pixel 0/74 mean/min/max = 45.442/32.6289/58.255
[13:58:03.854] INFO: roc 7 with ID = 7 has maximal Vcal 62.0784 for pixel 16/79 mean/min/max = 46.6169/30.8964/62.3373
[13:58:03.854] INFO: roc 8 with ID = 8 has maximal Vcal 57.6063 for pixel 51/11 mean/min/max = 45.2193/32.7922/57.6464
[13:58:03.854] INFO: roc 9 with ID = 9 has maximal Vcal 62.7698 for pixel 15/62 mean/min/max = 47.0701/31.3396/62.8006
[13:58:03.855] INFO: roc 10 with ID = 10 has maximal Vcal 57.4092 for pixel 10/66 mean/min/max = 45.1287/32.6054/57.6519
[13:58:03.855] INFO: roc 11 with ID = 11 has maximal Vcal 59.7795 for pixel 8/2 mean/min/max = 45.7581/31.6646/59.8516
[13:58:03.855] INFO: roc 12 with ID = 12 has maximal Vcal 59.1882 for pixel 1/10 mean/min/max = 46.3817/33.5407/59.2227
[13:58:03.856] INFO: roc 13 with ID = 13 has maximal Vcal 58.0649 for pixel 0/74 mean/min/max = 45.4317/32.6376/58.2258
[13:58:03.856] INFO: roc 14 with ID = 14 has maximal Vcal 68.8067 for pixel 3/49 mean/min/max = 49.7314/30.0888/69.3741
[13:58:03.856] INFO: roc 15 with ID = 15 has maximal Vcal 61.1618 for pixel 3/1 mean/min/max = 46.9569/32.3254/61.5884
[13:58:03.857] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:58:03.990] INFO: Expecting 1029120 events.
[13:58:22.949] INFO: 1029120 events read in total (18180ms).
[13:58:22.957] INFO: Expecting 1029120 events.
[13:58:41.751] INFO: 1029120 events read in total (18182ms).
[13:58:41.761] INFO: Expecting 1029120 events.
[13:59:00.634] INFO: 1029120 events read in total (18265ms).
[13:59:00.646] INFO: Expecting 1029120 events.
[13:59:19.250] INFO: 1029120 events read in total (17997ms).
[13:59:19.263] INFO: Expecting 1029120 events.
[13:59:37.919] INFO: 1029120 events read in total (18041ms).
[13:59:37.938] INFO: Expecting 1029120 events.
[13:59:56.680] INFO: 1029120 events read in total (18132ms).
[13:59:56.701] INFO: Expecting 1029120 events.
[14:00:15.379] INFO: 1029120 events read in total (18071ms).
[14:00:15.401] INFO: Expecting 1029120 events.
[14:00:34.217] INFO: 1029120 events read in total (18199ms).
[14:00:34.244] INFO: Expecting 1029120 events.
[14:00:53.053] INFO: 1029120 events read in total (18211ms).
[14:00:53.079] INFO: Expecting 1029120 events.
[14:01:11.964] INFO: 1029120 events read in total (18275ms).
[14:01:11.994] INFO: Expecting 1029120 events.
[14:01:30.839] INFO: 1029120 events read in total (18252ms).
[14:01:30.872] INFO: Expecting 1029120 events.
[14:01:49.776] INFO: 1029120 events read in total (18304ms).
[14:01:49.808] INFO: Expecting 1029120 events.
[14:02:08.684] INFO: 1029120 events read in total (18283ms).
[14:02:08.722] INFO: Expecting 1029120 events.
[14:02:27.424] INFO: 1029120 events read in total (18111ms).
[14:02:27.459] INFO: Expecting 1029120 events.
[14:02:46.293] INFO: 1029120 events read in total (18223ms).
[14:02:46.335] INFO: Expecting 1029120 events.
[14:03:04.991] INFO: 1029120 events read in total (18061ms).
[14:03:05.036] INFO: Test took 301179ms.
[14:03:06.060] INFO: ---> dac: vcal name: TrimThr2 ntrig: 20 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[14:03:06.071] INFO: dacScan split into 1 runs with ntrig = 20
[14:03:06.071] INFO: run 1 of 1
[14:03:06.425] INFO: Expecting 16640000 events.
[14:03:30.430] INFO: 843160 events read in total (23226ms).
[14:03:53.593] INFO: 1684760 events read in total (46389ms).
[14:04:16.788] INFO: 2525420 events read in total (69584ms).
[14:04:39.968] INFO: 3365500 events read in total (92764ms).
[14:05:03.168] INFO: 4206280 events read in total (115964ms).
[14:05:26.390] INFO: 5046300 events read in total (139186ms).
[14:05:49.588] INFO: 5887900 events read in total (162384ms).
[14:06:12.729] INFO: 6728960 events read in total (185525ms).
[14:06:35.929] INFO: 7569280 events read in total (208725ms).
[14:06:59.127] INFO: 8408220 events read in total (231923ms).
[14:07:22.206] INFO: 9241940 events read in total (255002ms).
[14:07:45.292] INFO: 10074720 events read in total (278088ms).
[14:08:08.425] INFO: 10906800 events read in total (301221ms).
[14:08:30.812] INFO: 11738640 events read in total (323608ms).
[14:08:54.038] INFO: 12569240 events read in total (346834ms).
[14:09:17.228] INFO: 13397940 events read in total (370024ms).
[14:09:40.414] INFO: 14226940 events read in total (393210ms).
[14:10:03.608] INFO: 15056740 events read in total (416404ms).
[14:10:26.585] INFO: 15886560 events read in total (439381ms).
[14:10:46.937] INFO: 16640000 events read in total (459733ms).
[14:10:47.022] INFO: Test took 460951ms.
[14:10:47.304] INFO: Fetched DAQ statistics. Counters are being reset now.
[14:11:14.189] INFO: ---> TrimStepCorr4 extremal thresholds: 0.043869 .. 255.000000
[14:11:14.257] INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 20 dacrange: 0 .. 255 (-1/-1) hits flags = 16 (plus default)
[14:11:14.267] INFO: dacScan split into 1 runs with ntrig = 20
[14:11:14.267] INFO: run 1 of 1
[14:11:14.616] INFO: Expecting 21299200 events.
[14:11:38.418] INFO: 825660 events read in total (23023ms).
[14:12:01.474] INFO: 1651400 events read in total (46079ms).
[14:12:24.405] INFO: 2477340 events read in total (69010ms).
[14:12:45.295] INFO: 3303640 events read in total (89900ms).
[14:13:08.287] INFO: 4129560 events read in total (112892ms).
[14:13:30.349] INFO: 4955540 events read in total (134954ms).
[14:13:52.907] INFO: 5782000 events read in total (157512ms).
[14:14:15.844] INFO: 6608280 events read in total (180449ms).
[14:14:36.965] INFO: 7434360 events read in total (201570ms).
[14:15:00.233] INFO: 8260900 events read in total (224838ms).
[14:15:23.205] INFO: 9087360 events read in total (247810ms).
[14:15:44.422] INFO: 9914020 events read in total (269027ms).
[14:16:07.496] INFO: 10740600 events read in total (292101ms).
[14:16:30.095] INFO: 11567300 events read in total (314700ms).
[14:16:53.153] INFO: 12393700 events read in total (337758ms).
[14:17:14.950] INFO: 13219340 events read in total (359555ms).
[14:17:38.081] INFO: 14045260 events read in total (382686ms).
[14:17:59.360] INFO: 14870700 events read in total (403965ms).
[14:18:22.249] INFO: 15695300 events read in total (426854ms).
[14:18:44.680] INFO: 16519980 events read in total (449285ms).
[14:19:07.700] INFO: 17344760 events read in total (472305ms).
[14:19:28.954] INFO: 18169060 events read in total (493559ms).
[14:19:51.911] INFO: 18993060 events read in total (516516ms).
[14:20:13.925] INFO: 19817360 events read in total (538530ms).
[14:20:34.934] INFO: 20640900 events read in total (559539ms).
[14:20:53.531] INFO: 21299200 events read in total (578136ms).
[14:20:53.651] INFO: Test took 579385ms.
[14:20:53.980] INFO: Fetched DAQ statistics. Counters are being reset now.
[14:21:23.145] INFO: ---> TrimStepCorr2 extremal thresholds: 11.061843 .. 52.816732
[14:21:23.213] INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 20 dacrange: 1 .. 62 (-1/-1) hits flags = 16 (plus default)
[14:21:23.223] INFO: dacScan split into 1 runs with ntrig = 20
[14:21:23.223] INFO: run 1 of 1
[14:21:23.572] INFO: Expecting 5158400 events.
[14:21:50.626] INFO: 1121080 events read in total (26268ms).
[14:22:16.968] INFO: 2241820 events read in total (52610ms).
[14:22:41.904] INFO: 3362340 events read in total (77546ms).
[14:23:06.003] INFO: 4480200 events read in total (102645ms).
[14:23:21.512] INFO: 5158400 events read in total (117154ms).
[14:23:21.529] INFO: Test took 118306ms.
[14:23:21.576] INFO: Fetched DAQ statistics. Counters are being reset now.
[14:23:36.072] INFO: ---> TrimStepCorr1a extremal thresholds: 18.418567 .. 47.470604
[14:23:36.141] INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 20 dacrange: 8 .. 57 (-1/-1) hits flags = 16 (plus default)
[14:23:36.151] INFO: dacScan split into 1 runs with ntrig = 20
[14:23:36.151] INFO: run 1 of 1
[14:23:36.505] INFO: Expecting 4160000 events.
[14:24:01.961] INFO: 1117000 events read in total (24678ms).
[14:24:26.851] INFO: 2233600 events read in total (49568ms).
[14:24:52.878] INFO: 3349280 events read in total (75595ms).
[14:25:11.823] INFO: 4160000 events read in total (94540ms).
[14:25:11.848] INFO: Test took 95697ms.
[14:25:11.899] INFO: Fetched DAQ statistics. Counters are being reset now.
[14:25:25.821] INFO: ---> TrimStepCorr1b extremal thresholds: 8.500000 .. 47.470604
[14:25:25.891] INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 20 dacrange: 8 .. 57 (-1/-1) hits flags = 16 (plus default)
[14:25:25.900] INFO: dacScan split into 1 runs with ntrig = 20
[14:25:25.900] INFO: run 1 of 1
[14:25:26.250] INFO: Expecting 4160000 events.
[14:25:51.412] INFO: 1118440 events read in total (24383ms).
[14:26:17.625] INFO: 2236740 events read in total (50596ms).
[14:26:41.929] INFO: 3353720 events read in total (74900ms).
[14:27:00.847] INFO: 4160000 events read in total (93818ms).
[14:27:00.872] INFO: Test took 94972ms.
[14:27:00.914] INFO: Fetched DAQ statistics. Counters are being reset now.
[14:27:14.841] INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:27:14.841] INFO: ---> dac: vcal name: TrimThrFinal ntrig: 20 dacrange: 15 .. 55 (-1/-1) hits flags = 16 (plus default)
[14:27:14.851] INFO: dacScan split into 1 runs with ntrig = 20
[14:27:14.851] INFO: run 1 of 1
[14:27:15.199] INFO: Expecting 3411200 events.
[14:27:40.038] INFO: 1074040 events read in total (24060ms).
[14:28:05.669] INFO: 2147960 events read in total (49691ms).
[14:28:31.349] INFO: 3221160 events read in total (75371ms).
[14:28:36.236] INFO: 3411200 events read in total (80258ms).
[14:28:36.252] INFO: Test took 81402ms.
[14:28:36.291] INFO: Fetched DAQ statistics. Counters are being reset now.
[14:28:49.480] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C0.dat
[14:28:49.480] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C1.dat
[14:28:49.480] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C2.dat
[14:28:49.480] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C3.dat
[14:28:49.480] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C4.dat
[14:28:49.481] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C5.dat
[14:28:49.481] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C6.dat
[14:28:49.481] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C7.dat
[14:28:49.481] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C8.dat
[14:28:49.481] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C9.dat
[14:28:49.481] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C10.dat
[14:28:49.481] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C11.dat
[14:28:49.482] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C12.dat
[14:28:49.482] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C13.dat
[14:28:49.482] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C14.dat
[14:28:49.482] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C15.dat
[14:28:49.482] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C0.dat
[14:28:49.492] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C1.dat
[14:28:49.498] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C2.dat
[14:28:49.504] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C3.dat
[14:28:49.510] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C4.dat
[14:28:49.515] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C5.dat
[14:28:49.521] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C6.dat
[14:28:49.527] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C7.dat
[14:28:49.533] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C8.dat
[14:28:49.539] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C9.dat
[14:28:49.545] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C10.dat
[14:28:49.550] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C11.dat
[14:28:49.556] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C12.dat
[14:28:49.562] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C13.dat
[14:28:49.568] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C14.dat
[14:28:49.574] INFO: write trim parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/trimParameters35_C15.dat
[14:28:49.579] INFO: PixTestTrim::trimTest() done
[14:28:49.579] INFO: vtrim: 92 91 118 92 91 96 94 106 83 110 87 96 91 84 113 93
[14:28:49.579] INFO: vthrcomp: 75 98 107 99 87 87 86 92 92 100 85 85 78 80 88 88
[14:28:49.579] INFO: vcal mean: 34.99 34.97 34.97 34.93 35.01 35.00 34.96 35.01 34.96 34.97 34.98 34.96 35.02 34.97 34.97 35.01
[14:28:49.579] INFO: vcal RMS: 0.69 0.70 0.85 1.13 0.71 0.77 0.76 0.97 0.65 0.90 0.75 0.76 0.69 0.75 1.00 0.76
[14:28:49.579] INFO: bits mean: 8.36 9.29 8.76 9.14 9.59 8.76 9.12 9.06 8.80 9.21 9.31 9.79 9.01 8.98 9.06 8.76
[14:28:49.579] INFO: bits RMS: 2.81 2.87 2.48 2.79 2.69 2.96 2.84 2.93 2.92 2.74 2.72 2.57 2.67 2.85 2.72 2.81
[14:28:49.589] INFO: ----------------------------------------------------------------------
[14:28:49.589] INFO: PixTestTrim::trimBitTest() ntrig = 10, vtrims = 254 126 63 32
[14:28:49.589] INFO: ----------------------------------------------------------------------
[14:28:49.593] INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 10 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[14:28:49.605] INFO: dacScan split into 1 runs with ntrig = 10
[14:28:49.605] INFO: run 1 of 1
[14:28:49.955] INFO: Expecting 8320000 events.
[14:29:20.206] INFO: 1146060 events read in total (29472ms).
[14:29:47.232] INFO: 2277930 events read in total (56498ms).
[14:30:15.926] INFO: 3403230 events read in total (85192ms).
[14:30:43.912] INFO: 4519420 events read in total (113178ms).
[14:31:10.682] INFO: 5624930 events read in total (139948ms).
[14:31:39.572] INFO: 6725550 events read in total (168838ms).
[14:32:08.499] INFO: 7825210 events read in total (197765ms).
[14:32:21.547] INFO: 8320000 events read in total (210813ms).
[14:32:21.599] INFO: Test took 211994ms.
[14:32:21.727] INFO: Fetched DAQ statistics. Counters are being reset now.
[14:32:49.403] INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 10 dacrange: 0 .. 181 (-1/-1) hits flags = 16 (plus default)
[14:32:49.413] INFO: dacScan split into 1 runs with ntrig = 10
[14:32:49.413] INFO: run 1 of 1
[14:32:49.762] INFO: Expecting 7571200 events.
[14:33:18.345] INFO: 1146930 events read in total (27804ms).
[14:33:47.840] INFO: 2279630 events read in total (57299ms).
[14:34:17.295] INFO: 3405120 events read in total (86754ms).
[14:34:44.068] INFO: 4518510 events read in total (113527ms).
[14:35:13.108] INFO: 5621310 events read in total (142567ms).
[14:35:41.029] INFO: 6722330 events read in total (170488ms).
[14:36:01.918] INFO: 7571200 events read in total (191377ms).
[14:36:01.976] INFO: Test took 192563ms.
[14:36:02.096] INFO: Fetched DAQ statistics. Counters are being reset now.
[14:36:28.126] INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 10 dacrange: 0 .. 166 (-1/-1) hits flags = 16 (plus default)
[14:36:28.142] INFO: dacScan split into 1 runs with ntrig = 10
[14:36:28.142] INFO: run 1 of 1
[14:36:28.493] INFO: Expecting 6947200 events.
[14:36:59.613] INFO: 1200380 events read in total (30341ms).
[14:37:29.764] INFO: 2382590 events read in total (60492ms).
[14:37:57.997] INFO: 3554170 events read in total (88726ms).
[14:38:26.818] INFO: 4708700 events read in total (117546ms).
[14:38:56.269] INFO: 5855250 events read in total (146997ms).
[14:39:24.245] INFO: 6947200 events read in total (174973ms).
[14:39:24.292] INFO: Test took 176150ms.
[14:39:24.388] INFO: Fetched DAQ statistics. Counters are being reset now.
[14:39:48.855] INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 10 dacrange: 0 .. 165 (-1/-1) hits flags = 16 (plus default)
[14:39:48.868] INFO: dacScan split into 1 runs with ntrig = 10
[14:39:48.868] INFO: run 1 of 1
[14:39:49.221] INFO: Expecting 6905600 events.
[14:40:20.337] INFO: 1203090 events read in total (30328ms).
[14:40:50.412] INFO: 2388030 events read in total (60403ms).
[14:41:19.674] INFO: 3561170 events read in total (89666ms).
[14:41:48.399] INFO: 4717240 events read in total (118390ms).
[14:42:18.071] INFO: 5866420 events read in total (148062ms).
[14:42:44.648] INFO: 6905600 events read in total (174639ms).
[14:42:44.693] INFO: Test took 175825ms.
[14:42:44.788] INFO: Fetched DAQ statistics. Counters are being reset now.
[14:43:09.476] INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 10 dacrange: 0 .. 165 (-1/-1) hits flags = 16 (plus default)
[14:43:09.490] INFO: dacScan split into 1 runs with ntrig = 10
[14:43:09.490] INFO: run 1 of 1
[14:43:09.844] INFO: Expecting 6905600 events.
[14:43:40.907] INFO: 1201700 events read in total (30275ms).
[14:44:11.054] INFO: 2385220 events read in total (60423ms).
[14:44:40.843] INFO: 3557350 events read in total (90212ms).
[14:45:08.607] INFO: 4712390 events read in total (117975ms).
[14:45:38.186] INFO: 5860870 events read in total (147554ms).
[14:46:04.725] INFO: 6905600 events read in total (174093ms).
[14:46:04.784] INFO: Test took 175294ms.
[14:46:04.880] INFO: Fetched DAQ statistics. Counters are being reset now.
[14:46:29.159] INFO: PixTestTrim::trimBitTest() done
[14:46:29.161] INFO: PixTestTrim::doTest() done, duration: 3567 seconds
[14:46:29.818] INFO: ######################################################################
[14:46:29.819] INFO: PixTestPhOptimization::doTest() Ntrig = 16
[14:46:29.819] INFO: ######################################################################
[14:46:30.170] INFO: Expecting 41600 events.
[14:46:34.230] INFO: 41600 events read in total (3274ms).
[14:46:34.231] INFO: Test took 4411ms.
[14:46:34.237] INFO: Fetched DAQ statistics. Counters are being reset now.
[14:46:35.008] INFO: Expecting 41600 events.
[14:46:39.098] INFO: 41600 events read in total (3311ms).
[14:46:39.098] INFO: Test took 4440ms.
[14:46:39.104] INFO: Fetched DAQ statistics. Counters are being reset now.
[14:46:39.609] INFO: Expecting 41600 events.
[14:46:43.748] INFO: 41600 events read in total (3360ms).
[14:46:43.749] INFO: Test took 4529ms.
[14:46:43.755] INFO: Fetched DAQ statistics. Counters are being reset now.
[14:46:43.763] INFO: The DUT currently contains the following objects:
[14:46:43.763] INFO: 2 TBM Cores tbm08c (2 ON)
[14:46:43.763] INFO: TBM Core alpha (0): 7 registers set
[14:46:43.763] INFO: TBM Core beta (1): 7 registers set
[14:46:43.763] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:46:43.763] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:43.763] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:44.258] INFO: Expecting 2560 events.
[14:46:45.286] INFO: 2560 events read in total (249ms).
[14:46:45.286] INFO: Test took 1523ms.
[14:46:45.286] INFO: The DUT currently contains the following objects:
[14:46:45.286] INFO: 2 TBM Cores tbm08c (2 ON)
[14:46:45.286] INFO: TBM Core alpha (0): 7 registers set
[14:46:45.286] INFO: TBM Core beta (1): 7 registers set
[14:46:45.286] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:46:45.286] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.286] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.286] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.287] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.287] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.287] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.287] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.287] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.287] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.287] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.287] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.287] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.287] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.287] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.287] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.287] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:45.859] INFO: Expecting 2560 events.
[14:46:46.883] INFO: 2560 events read in total (245ms).
[14:46:46.883] INFO: Test took 1596ms.
[14:46:46.883] INFO: The DUT currently contains the following objects:
[14:46:46.883] INFO: 2 TBM Cores tbm08c (2 ON)
[14:46:46.883] INFO: TBM Core alpha (0): 7 registers set
[14:46:46.883] INFO: TBM Core beta (1): 7 registers set
[14:46:46.883] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:46:46.883] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.883] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.883] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.883] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.883] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.883] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.883] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.883] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.883] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.883] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.884] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.884] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.884] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.884] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.884] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:46.884] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:47.456] INFO: Expecting 2560 events.
[14:46:48.480] INFO: 2560 events read in total (245ms).
[14:46:48.480] INFO: Test took 1596ms.
[14:46:48.480] INFO: The DUT currently contains the following objects:
[14:46:48.480] INFO: 2 TBM Cores tbm08c (2 ON)
[14:46:48.480] INFO: TBM Core alpha (0): 7 registers set
[14:46:48.481] INFO: TBM Core beta (1): 7 registers set
[14:46:48.481] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:46:48.481] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:48.481] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:49.053] INFO: Expecting 2560 events.
[14:46:50.076] INFO: 2560 events read in total (244ms).
[14:46:50.076] INFO: Test took 1595ms.
[14:46:50.077] INFO: The DUT currently contains the following objects:
[14:46:50.077] INFO: 2 TBM Cores tbm08c (2 ON)
[14:46:50.077] INFO: TBM Core alpha (0): 7 registers set
[14:46:50.077] INFO: TBM Core beta (1): 7 registers set
[14:46:50.077] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:46:50.077] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.077] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:50.649] INFO: Expecting 2560 events.
[14:46:51.672] INFO: 2560 events read in total (244ms).
[14:46:51.672] INFO: Test took 1595ms.
[14:46:51.673] INFO: The DUT currently contains the following objects:
[14:46:51.673] INFO: 2 TBM Cores tbm08c (2 ON)
[14:46:51.673] INFO: TBM Core alpha (0): 7 registers set
[14:46:51.673] INFO: TBM Core beta (1): 7 registers set
[14:46:51.673] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:46:51.673] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:51.673] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:52.246] INFO: Expecting 2560 events.
[14:46:53.269] INFO: 2560 events read in total (244ms).
[14:46:53.269] INFO: Test took 1596ms.
[14:46:53.269] INFO: The DUT currently contains the following objects:
[14:46:53.269] INFO: 2 TBM Cores tbm08c (2 ON)
[14:46:53.269] INFO: TBM Core alpha (0): 7 registers set
[14:46:53.269] INFO: TBM Core beta (1): 7 registers set
[14:46:53.269] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:46:53.269] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.269] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:53.842] INFO: Expecting 2560 events.
[14:46:54.866] INFO: 2560 events read in total (246ms).
[14:46:54.866] INFO: Test took 1597ms.
[14:46:54.866] INFO: The DUT currently contains the following objects:
[14:46:54.866] INFO: 2 TBM Cores tbm08c (2 ON)
[14:46:54.866] INFO: TBM Core alpha (0): 7 registers set
[14:46:54.866] INFO: TBM Core beta (1): 7 registers set
[14:46:54.866] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:46:54.866] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:54.866] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:55.439] INFO: Expecting 2560 events.
[14:46:56.461] INFO: 2560 events read in total (243ms).
[14:46:56.461] INFO: Test took 1595ms.
[14:46:56.462] INFO: The DUT currently contains the following objects:
[14:46:56.462] INFO: 2 TBM Cores tbm08c (2 ON)
[14:46:56.462] INFO: TBM Core alpha (0): 7 registers set
[14:46:56.462] INFO: TBM Core beta (1): 7 registers set
[14:46:56.462] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:46:56.462] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:56.462] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:57.034] INFO: Expecting 2560 events.
[14:46:58.059] INFO: 2560 events read in total (246ms).
[14:46:58.059] INFO: Test took 1597ms.
[14:46:58.060] INFO: The DUT currently contains the following objects:
[14:46:58.060] INFO: 2 TBM Cores tbm08c (2 ON)
[14:46:58.060] INFO: TBM Core alpha (0): 7 registers set
[14:46:58.060] INFO: TBM Core beta (1): 7 registers set
[14:46:58.060] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:46:58.060] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.060] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:58.632] INFO: Expecting 2560 events.
[14:46:59.656] INFO: 2560 events read in total (245ms).
[14:46:59.657] INFO: Test took 1597ms.
[14:46:59.657] INFO: The DUT currently contains the following objects:
[14:46:59.657] INFO: 2 TBM Cores tbm08c (2 ON)
[14:46:59.657] INFO: TBM Core alpha (0): 7 registers set
[14:46:59.657] INFO: TBM Core beta (1): 7 registers set
[14:46:59.657] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:46:59.657] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:46:59.657] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:00.230] INFO: Expecting 2560 events.
[14:47:01.253] INFO: 2560 events read in total (244ms).
[14:47:01.253] INFO: Test took 1596ms.
[14:47:01.253] INFO: The DUT currently contains the following objects:
[14:47:01.254] INFO: 2 TBM Cores tbm08c (2 ON)
[14:47:01.254] INFO: TBM Core alpha (0): 7 registers set
[14:47:01.254] INFO: TBM Core beta (1): 7 registers set
[14:47:01.254] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:47:01.254] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.254] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:01.826] INFO: Expecting 2560 events.
[14:47:02.848] INFO: 2560 events read in total (243ms).
[14:47:02.848] INFO: Test took 1594ms.
[14:47:02.849] INFO: The DUT currently contains the following objects:
[14:47:02.849] INFO: 2 TBM Cores tbm08c (2 ON)
[14:47:02.849] INFO: TBM Core alpha (0): 7 registers set
[14:47:02.849] INFO: TBM Core beta (1): 7 registers set
[14:47:02.849] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:47:02.849] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:02.849] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:03.422] INFO: Expecting 2560 events.
[14:47:04.450] INFO: 2560 events read in total (250ms).
[14:47:04.450] INFO: Test took 1601ms.
[14:47:04.450] INFO: The DUT currently contains the following objects:
[14:47:04.450] INFO: 2 TBM Cores tbm08c (2 ON)
[14:47:04.451] INFO: TBM Core alpha (0): 7 registers set
[14:47:04.451] INFO: TBM Core beta (1): 7 registers set
[14:47:04.451] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:47:04.451] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:04.451] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:05.024] INFO: Expecting 2560 events.
[14:47:06.051] INFO: 2560 events read in total (248ms).
[14:47:06.051] INFO: Test took 1600ms.
[14:47:06.052] INFO: The DUT currently contains the following objects:
[14:47:06.052] INFO: 2 TBM Cores tbm08c (2 ON)
[14:47:06.052] INFO: TBM Core alpha (0): 7 registers set
[14:47:06.052] INFO: TBM Core beta (1): 7 registers set
[14:47:06.052] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:47:06.052] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.052] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:06.624] INFO: Expecting 2560 events.
[14:47:07.651] INFO: 2560 events read in total (248ms).
[14:47:07.652] INFO: Test took 1600ms.
[14:47:07.652] INFO: The DUT currently contains the following objects:
[14:47:07.652] INFO: 2 TBM Cores tbm08c (2 ON)
[14:47:07.652] INFO: TBM Core alpha (0): 7 registers set
[14:47:07.652] INFO: TBM Core beta (1): 7 registers set
[14:47:07.652] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:47:07.652] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.652] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.652] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.652] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.652] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.652] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.652] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.652] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.652] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.652] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.652] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.652] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.652] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.653] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.653] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:07.653] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:47:08.225] INFO: Expecting 2560 events.
[14:47:09.254] INFO: 2560 events read in total (250ms).
[14:47:09.254] INFO: Test took 1601ms.
[14:47:09.259] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:47:09.829] INFO: Expecting 655360 events.
[14:47:23.178] INFO: 655360 events read in total (12571ms).
[14:47:23.189] INFO: Expecting 655360 events.
[14:47:36.378] INFO: 655360 events read in total (12610ms).
[14:47:36.394] INFO: Expecting 655360 events.
[14:47:49.545] INFO: 655360 events read in total (12574ms).
[14:47:49.570] INFO: Expecting 655360 events.
[14:48:02.741] INFO: 655360 events read in total (12611ms).
[14:48:02.766] INFO: Expecting 655360 events.
[14:48:15.908] INFO: 655360 events read in total (12577ms).
[14:48:15.935] INFO: Expecting 655360 events.
[14:48:29.098] INFO: 655360 events read in total (12597ms).
[14:48:29.129] INFO: Expecting 655360 events.
[14:48:42.278] INFO: 655360 events read in total (12588ms).
[14:48:42.325] INFO: Expecting 655360 events.
[14:48:55.446] INFO: 655360 events read in total (12579ms).
[14:48:55.491] INFO: Expecting 655360 events.
[14:49:08.672] INFO: 655360 events read in total (12641ms).
[14:49:08.719] INFO: Expecting 655360 events.
[14:49:21.906] INFO: 655360 events read in total (12641ms).
[14:49:21.955] INFO: Expecting 655360 events.
[14:49:35.139] INFO: 655360 events read in total (12648ms).
[14:49:35.191] INFO: Expecting 655360 events.
[14:49:48.387] INFO: 655360 events read in total (12659ms).
[14:49:48.452] INFO: Expecting 655360 events.
[14:50:01.619] INFO: 655360 events read in total (12640ms).
[14:50:01.680] INFO: Expecting 655360 events.
[14:50:14.844] INFO: 655360 events read in total (12637ms).
[14:50:14.910] INFO: Expecting 655360 events.
[14:50:28.051] INFO: 655360 events read in total (12613ms).
[14:50:28.122] INFO: Expecting 655360 events.
[14:50:41.337] INFO: 655360 events read in total (12688ms).
[14:50:41.416] INFO: Test took 212157ms.
[14:50:41.521] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:50:41.887] INFO: Expecting 655360 events.
[14:50:54.987] INFO: 655360 events read in total (12321ms).
[14:50:54.999] INFO: Expecting 655360 events.
[14:51:07.000] INFO: 655360 events read in total (12417ms).
[14:51:08.014] INFO: Expecting 655360 events.
[14:51:20.916] INFO: 655360 events read in total (12322ms).
[14:51:20.935] INFO: Expecting 655360 events.
[14:51:33.980] INFO: 655360 events read in total (12462ms).
[14:51:34.011] INFO: Expecting 655360 events.
[14:51:46.952] INFO: 655360 events read in total (12376ms).
[14:51:46.987] INFO: Expecting 655360 events.
[14:52:00.124] INFO: 655360 events read in total (12580ms).
[14:52:00.158] INFO: Expecting 655360 events.
[14:52:13.040] INFO: 655360 events read in total (12321ms).
[14:52:13.076] INFO: Expecting 655360 events.
[14:52:26.122] INFO: 655360 events read in total (12485ms).
[14:52:26.166] INFO: Expecting 655360 events.
[14:52:39.179] INFO: 655360 events read in total (12463ms).
[14:52:39.228] INFO: Expecting 655360 events.
[14:52:52.190] INFO: 655360 events read in total (12424ms).
[14:52:52.242] INFO: Expecting 655360 events.
[14:53:05.135] INFO: 655360 events read in total (12352ms).
[14:53:05.192] INFO: Expecting 655360 events.
[14:53:18.173] INFO: 655360 events read in total (12434ms).
[14:53:18.231] INFO: Expecting 655360 events.
[14:53:31.188] INFO: 655360 events read in total (12429ms).
[14:53:31.253] INFO: Expecting 655360 events.
[14:53:44.116] INFO: 655360 events read in total (12336ms).
[14:53:44.183] INFO: Expecting 655360 events.
[14:53:57.044] INFO: 655360 events read in total (12334ms).
[14:53:57.113] INFO: Expecting 655360 events.
[14:54:10.185] INFO: 655360 events read in total (12539ms).
[14:54:10.257] INFO: Test took 208736ms.
[14:54:10.453] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.459] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.466] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.472] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.479] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.485] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.492] INFO: safety margin for low PH: adding 1, margin is now 21
[14:54:10.498] INFO: safety margin for low PH: adding 2, margin is now 22
[14:54:10.505] INFO: safety margin for low PH: adding 3, margin is now 23
[14:54:10.511] INFO: safety margin for low PH: adding 4, margin is now 24
[14:54:10.518] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.524] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.531] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.537] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.544] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.550] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.556] INFO: safety margin for low PH: adding 1, margin is now 21
[14:54:10.563] INFO: safety margin for low PH: adding 2, margin is now 22
[14:54:10.569] INFO: safety margin for low PH: adding 3, margin is now 23
[14:54:10.576] INFO: safety margin for low PH: adding 4, margin is now 24
[14:54:10.582] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.589] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.595] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.602] INFO: safety margin for low PH: adding 0, margin is now 20
[14:54:10.658] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C0.dat
[14:54:10.658] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C1.dat
[14:54:10.659] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C2.dat
[14:54:10.659] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C3.dat
[14:54:10.659] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C4.dat
[14:54:10.659] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C5.dat
[14:54:10.659] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C6.dat
[14:54:10.659] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C7.dat
[14:54:10.660] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C8.dat
[14:54:10.660] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C9.dat
[14:54:10.660] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C10.dat
[14:54:10.660] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C11.dat
[14:54:10.660] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C12.dat
[14:54:10.661] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C13.dat
[14:54:10.661] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C14.dat
[14:54:10.661] INFO: write dac parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/dacParameters35_C15.dat
[14:54:11.022] INFO: Expecting 41600 events.
[14:54:15.288] INFO: 41600 events read in total (3487ms).
[14:54:15.289] INFO: Test took 4624ms.
[14:54:16.041] INFO: Expecting 41600 events.
[14:54:20.246] INFO: 41600 events read in total (3426ms).
[14:54:20.247] INFO: Test took 4565ms.
[14:54:20.999] INFO: Expecting 41600 events.
[14:54:25.261] INFO: 41600 events read in total (3483ms).
[14:54:25.262] INFO: Test took 4619ms.
[14:54:25.656] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:25.789] INFO: Expecting 2560 events.
[14:54:26.818] INFO: 2560 events read in total (250ms).
[14:54:26.818] INFO: Test took 1162ms.
[14:54:26.823] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:27.392] INFO: Expecting 2560 events.
[14:54:28.420] INFO: 2560 events read in total (249ms).
[14:54:28.421] INFO: Test took 1598ms.
[14:54:28.424] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:28.994] INFO: Expecting 2560 events.
[14:54:30.023] INFO: 2560 events read in total (250ms).
[14:54:30.024] INFO: Test took 1600ms.
[14:54:30.026] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:30.597] INFO: Expecting 2560 events.
[14:54:31.627] INFO: 2560 events read in total (251ms).
[14:54:31.627] INFO: Test took 1601ms.
[14:54:31.630] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:32.200] INFO: Expecting 2560 events.
[14:54:33.229] INFO: 2560 events read in total (250ms).
[14:54:33.230] INFO: Test took 1600ms.
[14:54:33.234] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:33.803] INFO: Expecting 2560 events.
[14:54:34.832] INFO: 2560 events read in total (250ms).
[14:54:34.833] INFO: Test took 1599ms.
[14:54:34.835] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:35.406] INFO: Expecting 2560 events.
[14:54:36.436] INFO: 2560 events read in total (251ms).
[14:54:36.436] INFO: Test took 1601ms.
[14:54:36.440] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:37.010] INFO: Expecting 2560 events.
[14:54:38.039] INFO: 2560 events read in total (250ms).
[14:54:38.039] INFO: Test took 1599ms.
[14:54:38.044] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:38.613] INFO: Expecting 2560 events.
[14:54:39.642] INFO: 2560 events read in total (250ms).
[14:54:39.642] INFO: Test took 1598ms.
[14:54:39.645] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:40.216] INFO: Expecting 2560 events.
[14:54:41.246] INFO: 2560 events read in total (251ms).
[14:54:41.246] INFO: Test took 1601ms.
[14:54:41.249] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:41.820] INFO: Expecting 2560 events.
[14:54:42.849] INFO: 2560 events read in total (250ms).
[14:54:42.849] INFO: Test took 1600ms.
[14:54:42.853] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:43.423] INFO: Expecting 2560 events.
[14:54:44.452] INFO: 2560 events read in total (250ms).
[14:54:44.453] INFO: Test took 1600ms.
[14:54:44.456] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:45.026] INFO: Expecting 2560 events.
[14:54:46.056] INFO: 2560 events read in total (251ms).
[14:54:46.056] INFO: Test took 1600ms.
[14:54:46.059] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:46.630] INFO: Expecting 2560 events.
[14:54:47.659] INFO: 2560 events read in total (250ms).
[14:54:47.659] INFO: Test took 1600ms.
[14:54:47.662] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:48.233] INFO: Expecting 2560 events.
[14:54:49.261] INFO: 2560 events read in total (249ms).
[14:54:49.262] INFO: Test took 1600ms.
[14:54:49.266] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:49.836] INFO: Expecting 2560 events.
[14:54:50.865] INFO: 2560 events read in total (250ms).
[14:54:50.866] INFO: Test took 1600ms.
[14:54:50.869] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:51.439] INFO: Expecting 2560 events.
[14:54:52.470] INFO: 2560 events read in total (252ms).
[14:54:52.470] INFO: Test took 1602ms.
[14:54:52.474] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:53.044] INFO: Expecting 2560 events.
[14:54:54.073] INFO: 2560 events read in total (250ms).
[14:54:54.074] INFO: Test took 1600ms.
[14:54:54.077] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:54.648] INFO: Expecting 2560 events.
[14:54:55.677] INFO: 2560 events read in total (250ms).
[14:54:55.677] INFO: Test took 1600ms.
[14:54:55.680] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:56.251] INFO: Expecting 2560 events.
[14:54:57.280] INFO: 2560 events read in total (250ms).
[14:54:57.281] INFO: Test took 1601ms.
[14:54:57.284] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:57.855] INFO: Expecting 2560 events.
[14:54:58.884] INFO: 2560 events read in total (250ms).
[14:54:58.884] INFO: Test took 1600ms.
[14:54:58.888] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:59.458] INFO: Expecting 2560 events.
[14:55:00.488] INFO: 2560 events read in total (251ms).
[14:55:00.488] INFO: Test took 1600ms.
[14:55:00.492] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:55:01.062] INFO: Expecting 2560 events.
[14:55:02.092] INFO: 2560 events read in total (251ms).
[14:55:02.092] INFO: Test took 1601ms.
[14:55:02.095] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:55:02.666] INFO: Expecting 2560 events.
[14:55:03.696] INFO: 2560 events read in total (251ms).
[14:55:03.696] INFO: Test took 1601ms.
[14:55:03.700] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:55:04.270] INFO: Expecting 2560 events.
[14:55:05.300] INFO: 2560 events read in total (251ms).
[14:55:05.300] INFO: Test took 1601ms.
[14:55:05.304] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:55:05.874] INFO: Expecting 2560 events.
[14:55:06.904] INFO: 2560 events read in total (251ms).
[14:55:06.904] INFO: Test took 1600ms.
[14:55:06.908] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:55:07.478] INFO: Expecting 2560 events.
[14:55:08.508] INFO: 2560 events read in total (251ms).
[14:55:08.508] INFO: Test took 1600ms.
[14:55:08.511] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:55:09.082] INFO: Expecting 2560 events.
[14:55:10.112] INFO: 2560 events read in total (251ms).
[14:55:10.113] INFO: Test took 1602ms.
[14:55:10.116] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:55:10.686] INFO: Expecting 2560 events.
[14:55:11.716] INFO: 2560 events read in total (251ms).
[14:55:11.716] INFO: Test took 1600ms.
[14:55:11.719] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:55:12.290] INFO: Expecting 2560 events.
[14:55:13.319] INFO: 2560 events read in total (250ms).
[14:55:13.320] INFO: Test took 1601ms.
[14:55:13.323] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:55:13.894] INFO: Expecting 2560 events.
[14:55:14.923] INFO: 2560 events read in total (250ms).
[14:55:14.924] INFO: Test took 1602ms.
[14:55:14.928] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:55:15.498] INFO: Expecting 2560 events.
[14:55:16.527] INFO: 2560 events read in total (250ms).
[14:55:16.528] INFO: Test took 1600ms.
[14:55:17.346] INFO: PixTestPhOptimization::doTest() done, duration: 527 seconds
[14:55:17.346] INFO: PH scale (per ROC): 85 81 73 74 81 83 85 84 80 82 83 80 100 83 71 80
[14:55:17.346] INFO: PH offset (per ROC): 158 153 182 165 156 144 157 153 146 160 139 137 129 147 158 150
[14:55:17.516] INFO: ######################################################################
[14:55:17.516] INFO: PixTestGainPedestal::fullTest() ntrig = 1
[14:55:17.516] INFO: ######################################################################
[14:55:17.528] INFO: scanning low vcal = 10
[14:55:17.878] INFO: Expecting 4160 events.
[14:55:20.751] INFO: 4160 events read in total (2094ms).
[14:55:20.751] INFO: Test took 3223ms.
[14:55:20.753] INFO: scanning low vcal = 20
[14:55:21.324] INFO: Expecting 4160 events.
[14:55:24.197] INFO: 4160 events read in total (2093ms).
[14:55:24.197] INFO: Test took 3444ms.
[14:55:24.200] INFO: scanning low vcal = 30
[14:55:24.772] INFO: Expecting 4160 events.
[14:55:27.647] INFO: 4160 events read in total (2096ms).
[14:55:27.648] INFO: Test took 3448ms.
[14:55:27.650] INFO: scanning low vcal = 40
[14:55:28.220] INFO: Expecting 4160 events.
[14:55:31.150] INFO: 4160 events read in total (2151ms).
[14:55:31.151] INFO: Test took 3501ms.
[14:55:31.154] INFO: scanning low vcal = 50
[14:55:31.706] INFO: Expecting 4160 events.
[14:55:34.643] INFO: 4160 events read in total (2158ms).
[14:55:34.644] INFO: Test took 3490ms.
[14:55:34.647] INFO: scanning low vcal = 60
[14:55:35.197] INFO: Expecting 4160 events.
[14:55:38.134] INFO: 4160 events read in total (2158ms).
[14:55:38.135] INFO: Test took 3488ms.
[14:55:38.138] INFO: scanning low vcal = 70
[14:55:38.688] INFO: Expecting 4160 events.
[14:55:41.632] INFO: 4160 events read in total (2165ms).
[14:55:41.632] INFO: Test took 3494ms.
[14:55:41.636] INFO: scanning low vcal = 80
[14:55:42.186] INFO: Expecting 4160 events.
[14:55:45.130] INFO: 4160 events read in total (2165ms).
[14:55:45.131] INFO: Test took 3495ms.
[14:55:45.134] INFO: scanning low vcal = 90
[14:55:45.684] INFO: Expecting 4160 events.
[14:55:48.701] INFO: 4160 events read in total (2238ms).
[14:55:48.702] INFO: Test took 3568ms.
[14:55:48.707] INFO: scanning low vcal = 100
[14:55:49.256] INFO: Expecting 4160 events.
[14:55:52.206] INFO: 4160 events read in total (2171ms).
[14:55:52.206] INFO: Test took 3499ms.
[14:55:52.210] INFO: scanning low vcal = 110
[14:55:52.759] INFO: Expecting 4160 events.
[14:55:55.711] INFO: 4160 events read in total (2173ms).
[14:55:55.712] INFO: Test took 3502ms.
[14:55:55.716] INFO: scanning low vcal = 120
[14:55:56.262] INFO: Expecting 4160 events.
[14:55:59.214] INFO: 4160 events read in total (2172ms).
[14:55:59.215] INFO: Test took 3499ms.
[14:55:59.220] INFO: scanning low vcal = 130
[14:55:59.764] INFO: Expecting 4160 events.
[14:56:02.717] INFO: 4160 events read in total (2174ms).
[14:56:02.718] INFO: Test took 3498ms.
[14:56:02.721] INFO: scanning low vcal = 140
[14:56:03.267] INFO: Expecting 4160 events.
[14:56:06.220] INFO: 4160 events read in total (2175ms).
[14:56:06.221] INFO: Test took 3500ms.
[14:56:06.224] INFO: scanning low vcal = 150
[14:56:06.769] INFO: Expecting 4160 events.
[14:56:09.724] INFO: 4160 events read in total (2176ms).
[14:56:09.724] INFO: Test took 3500ms.
[14:56:09.728] INFO: scanning low vcal = 160
[14:56:10.272] INFO: Expecting 4160 events.
[14:56:13.227] INFO: 4160 events read in total (2176ms).
[14:56:13.228] INFO: Test took 3500ms.
[14:56:13.232] INFO: scanning low vcal = 170
[14:56:13.773] INFO: Expecting 4160 events.
[14:56:16.724] INFO: 4160 events read in total (2172ms).
[14:56:16.724] INFO: Test took 3492ms.
[14:56:16.729] INFO: scanning low vcal = 180
[14:56:17.275] INFO: Expecting 4160 events.
[14:56:20.227] INFO: 4160 events read in total (2173ms).
[14:56:20.228] INFO: Test took 3499ms.
[14:56:20.232] INFO: scanning low vcal = 190
[14:56:20.778] INFO: Expecting 4160 events.
[14:56:23.730] INFO: 4160 events read in total (2173ms).
[14:56:23.731] INFO: Test took 3499ms.
[14:56:23.735] INFO: scanning low vcal = 200
[14:56:24.280] INFO: Expecting 4160 events.
[14:56:27.234] INFO: 4160 events read in total (2175ms).
[14:56:27.234] INFO: Test took 3499ms.
[14:56:27.238] INFO: scanning low vcal = 210
[14:56:27.784] INFO: Expecting 4160 events.
[14:56:30.737] INFO: 4160 events read in total (2174ms).
[14:56:30.738] INFO: Test took 3500ms.
[14:56:30.743] INFO: scanning low vcal = 220
[14:56:31.285] INFO: Expecting 4160 events.
[14:56:34.240] INFO: 4160 events read in total (2176ms).
[14:56:34.240] INFO: Test took 3497ms.
[14:56:34.244] INFO: scanning low vcal = 230
[14:56:34.787] INFO: Expecting 4160 events.
[14:56:37.743] INFO: 4160 events read in total (2177ms).
[14:56:37.743] INFO: Test took 3499ms.
[14:56:37.747] INFO: scanning low vcal = 240
[14:56:38.289] INFO: Expecting 4160 events.
[14:56:41.239] INFO: 4160 events read in total (2171ms).
[14:56:41.240] INFO: Test took 3493ms.
[14:56:41.244] INFO: scanning low vcal = 250
[14:56:41.792] INFO: Expecting 4160 events.
[14:56:44.744] INFO: 4160 events read in total (2174ms).
[14:56:44.745] INFO: Test took 3501ms.
[14:56:44.750] INFO: scanning high vcal = 30 (= 210 in low range)
[14:56:45.296] INFO: Expecting 4160 events.
[14:56:48.253] INFO: 4160 events read in total (2178ms).
[14:56:48.254] INFO: Test took 3503ms.
[14:56:48.259] INFO: scanning high vcal = 50 (= 350 in low range)
[14:56:48.797] INFO: Expecting 4160 events.
[14:56:51.749] INFO: 4160 events read in total (2173ms).
[14:56:51.750] INFO: Test took 3491ms.
[14:56:51.754] INFO: scanning high vcal = 70 (= 490 in low range)
[14:56:52.298] INFO: Expecting 4160 events.
[14:56:55.256] INFO: 4160 events read in total (2179ms).
[14:56:55.256] INFO: Test took 3502ms.
[14:56:55.260] INFO: scanning high vcal = 90 (= 630 in low range)
[14:56:55.807] INFO: Expecting 4160 events.
[14:56:58.841] INFO: 4160 events read in total (2254ms).
[14:56:58.842] INFO: Test took 3582ms.
[14:56:58.846] INFO: scanning high vcal = 200 (= 1400 in low range)
[14:56:59.390] INFO: Expecting 4160 events.
[14:57:02.333] INFO: 4160 events read in total (2165ms).
[14:57:02.334] INFO: Test took 3488ms.
[14:57:02.836] INFO: PixTestGainPedestal::measure() done
[14:57:35.839] INFO: PixTestGainPedestal::fit() done
[14:57:35.839] INFO: non-linearity mean: 0.952 0.957 0.945 0.956 0.956 0.960 0.955 0.957 0.952 0.957 0.953 0.959 0.955 0.954 0.954 0.956
[14:57:35.840] INFO: non-linearity RMS: 0.007 0.006 0.007 0.008 0.006 0.005 0.005 0.006 0.006 0.005 0.005 0.005 0.005 0.005 0.005 0.006
[14:57:35.840] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C0.dat
[14:57:35.868] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C1.dat
[14:57:35.888] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C2.dat
[14:57:35.907] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C3.dat
[14:57:35.927] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C4.dat
[14:57:35.947] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C5.dat
[14:57:35.966] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C6.dat
[14:57:35.985] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C7.dat
[14:57:35.004] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C8.dat
[14:57:36.023] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C9.dat
[14:57:36.042] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C10.dat
[14:57:36.061] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C11.dat
[14:57:36.080] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C12.dat
[14:57:36.099] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C13.dat
[14:57:36.118] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C14.dat
[14:57:36.137] INFO: write gain/ped parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/phCalibrationFitErr35_C15.dat
[14:57:36.156] INFO: PixTestGainPedestal::doTest() done, duration: 138 seconds
[14:57:36.162] INFO: readReadbackCal: M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C0.dat .. M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C15.dat
[14:57:36.163] INFO: PixTestReadback::doTest() start.
[14:57:36.164] INFO: PixTestReadback::RES sent once
[14:57:48.798] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C0.dat
[14:57:48.798] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C1.dat
[14:57:48.798] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C2.dat
[14:57:48.798] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C3.dat
[14:57:48.798] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C4.dat
[14:57:48.798] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C5.dat
[14:57:48.798] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C6.dat
[14:57:48.798] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C7.dat
[14:57:48.798] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C8.dat
[14:57:48.798] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C9.dat
[14:57:48.799] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C10.dat
[14:57:48.799] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C11.dat
[14:57:48.799] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C12.dat
[14:57:48.799] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C13.dat
[14:57:48.799] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C14.dat
[14:57:48.799] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C15.dat
[14:57:48.846] INFO: PixTestPattern:: pg_setup set to default.
[14:57:48.846] INFO: PixTestReadback::RES sent once
[14:58:01.444] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C0.dat
[14:58:01.444] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C1.dat
[14:58:01.444] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C2.dat
[14:58:01.444] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C3.dat
[14:58:01.444] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C4.dat
[14:58:01.444] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C5.dat
[14:58:01.444] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C6.dat
[14:58:01.444] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C7.dat
[14:58:01.444] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C8.dat
[14:58:01.444] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C9.dat
[14:58:01.444] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C10.dat
[14:58:01.444] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C11.dat
[14:58:01.444] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C12.dat
[14:58:01.445] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C13.dat
[14:58:01.445] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C14.dat
[14:58:01.445] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C15.dat
[14:58:01.494] INFO: PixTestPattern:: pg_setup set to default.
[14:58:01.494] INFO: PixTestReadback::RES sent once
[14:58:11.206] INFO: PixTestPattern:: pg_setup set to default.
[14:58:11.206] INFO: Vbg will be calibrated using Vd calibration
[14:58:11.206] INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 150.6calibrated Vbg = 1.21523 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 149.9calibrated Vbg = 1.21445 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 146.4calibrated Vbg = 1.21696 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 148.2calibrated Vbg = 1.22342 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 156.2calibrated Vbg = 1.22394 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 150.6calibrated Vbg = 1.22814 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 153.2calibrated Vbg = 1.22197 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 148.1calibrated Vbg = 1.22555 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 151.4calibrated Vbg = 1.23232 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 156calibrated Vbg = 1.23458 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 151.2calibrated Vbg = 1.23759 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 154.2calibrated Vbg = 1.22999 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 148.4calibrated Vbg = 1.22576 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 147.5calibrated Vbg = 1.21517 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 157.1calibrated Vbg = 1.22142 :::*/*/*/*/
[14:58:11.206] INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 159.2calibrated Vbg = 1.22011 :::*/*/*/*/
[14:58:11.210] INFO: PixTestReadback::RES sent once
[15:01:21.632] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C0.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C1.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C2.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C3.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C4.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C5.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C6.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C7.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C8.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C9.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C10.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C11.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C12.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C13.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C14.dat
[15:01:21.633] INFO: write readback calibration parameters into M4080_FullQualification_2015-09-11_11h43m_1441964587/003_Fulltest_m20/readbackCal_C15.dat
[15:01:21.679] INFO: PixTestPattern:: pg_setup set to default.
[15:01:21.681] INFO: PixTestReadback::doTest() done
[15:01:21.697] INFO: enter test to run
[15:01:21.697] INFO: test: BB2 no parameter change
[15:01:21.697] INFO: running: bb2
[15:01:21.699] INFO: ######################################################################
[15:01:21.699] INFO: PixTestBB2Map::doTest() Ntrig = 16, VcalS = 255, PlWidth = 35
[15:01:21.699] INFO: ######################################################################
[15:01:21.701] INFO: ----------------------------------------------------------------------
[15:01:21.701] INFO: PixTestBB2Map::setVana() target Ia = 30 mA/ROC
[15:01:21.701] INFO: ----------------------------------------------------------------------
[15:01:41.305] INFO: PixTestBB2Map::setVana() done, Module Ia 484.8 mA = 30.3 mA/ROC
[15:01:41.307] INFO: ----------------------------------------------------------------------
[15:01:41.307] INFO: PixTestBB2Map::setVthrCompCalDel()
[15:01:41.307] INFO: ----------------------------------------------------------------------
[15:01:41.452] INFO: Expecting 1048576 events.
[15:01:52.662] ERROR: <datapipe.cc/CheckEventValidity:L480> Channel 0 Number of ROCs (1) != Token Chain Length (8)
[15:01:52.665] ERROR: <datapipe.cc/CheckEventID:L453> Channel 0 Event ID mismatch: local ID (21) != TBM ID (130)
[15:02:02.973] INFO: 1048576 events read in total (20742ms).
[15:02:02.978] INFO: Test took 21663ms.
[15:02:03.423] INFO: PixTestBB2Map::setVthrCompCalDel() done
[15:02:03.423] INFO: CalDel: 146 141 141 145 163 147 147 152 139 141 145 133 129 168 132 131
[15:02:03.423] INFO: VthrComp: 94 123 127 123 112 114 109 120 121 125 107 107 100 110 109 111
[15:02:03.793] INFO: Expecting 8519680 events.
[15:02:34.258] INFO: 1336384 events read in total (29686ms).
[15:03:03.684] INFO: 2661360 events read in total (59112ms).
[15:03:33.331] INFO: 3980640 events read in total (88759ms).
[15:04:03.075] INFO: 5305328 events read in total (118503ms).
[15:04:32.822] INFO: 6636816 events read in total (148250ms).
[15:05:02.591] INFO: 7977808 events read in total (178019ms).
[15:05:14.822] INFO: 8519680 events read in total (190250ms).
[15:05:14.853] INFO: Test took 191411ms.
[15:05:15.467] INFO: Missing Bumps: 1 4 3 0 1 1 1 0 0 0 1 0 2 2 2 0
[15:05:15.467] INFO: Separation Cut: 45.00 25.08 45.00 26.97 35.14 37.78 39.87 35.70 40.29 40.62 37.81 41.87 37.56 35.60 37.16 37.75
[15:05:15.467] INFO: PixTestBB2Map::doTest() done,233 seconds
[15:05:15.772] INFO: enter test to run
[15:05:15.772] INFO: test: q no parameter change
[15:05:16.455] QUIET: Connection to board 74 closed.
[15:05:16.457] INFO: pXar: this is the end, my friend