[22:30:42.121] <TB1> INFO: *** Welcome to pxar ***
[22:30:42.122] <TB1> INFO: *** Today: 2016/11/07
[22:30:42.128] <TB1> INFO: *** Version: c8ba-dirty
[22:30:42.128] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C15.dat
[22:30:42.129] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[22:30:42.129] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//defaultMaskFile.dat
[22:30:42.129] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters_C15.dat
[22:30:42.183] <TB1> INFO: clk: 4
[22:30:42.183] <TB1> INFO: ctr: 4
[22:30:42.183] <TB1> INFO: sda: 19
[22:30:42.183] <TB1> INFO: tin: 9
[22:30:42.183] <TB1> INFO: level: 15
[22:30:42.183] <TB1> INFO: triggerdelay: 0
[22:30:42.183] <TB1> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[22:30:42.183] <TB1> INFO: Log level: INFO
[22:30:42.191] <TB1> INFO: Found DTB DTB_WXBYFL
[22:30:42.201] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[22:30:42.203] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
------------------------------------------------------
[22:30:42.205] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[22:30:43.763] <TB1> INFO: DUT info:
[22:30:43.763] <TB1> INFO: The DUT currently contains the following objects:
[22:30:43.763] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[22:30:43.763] <TB1> INFO: TBM Core alpha (0): 7 registers set
[22:30:43.763] <TB1> INFO: TBM Core beta (1): 7 registers set
[22:30:43.763] <TB1> INFO: TBM Core alpha (2): 7 registers set
[22:30:43.763] <TB1> INFO: TBM Core beta (3): 7 registers set
[22:30:43.763] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[22:30:43.763] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:43.763] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[22:30:44.164] <TB1> INFO: enter 'restricted' command line mode
[22:30:44.164] <TB1> INFO: enter test to run
[22:30:44.164] <TB1> INFO: test: pretest no parameter change
[22:30:44.164] <TB1> INFO: running: pretest
[22:30:44.702] <TB1> INFO: ######################################################################
[22:30:44.702] <TB1> INFO: PixTestPretest::doTest()
[22:30:44.702] <TB1> INFO: ######################################################################
[22:30:44.703] <TB1> INFO: ----------------------------------------------------------------------
[22:30:44.703] <TB1> INFO: PixTestPretest::programROC()
[22:30:44.703] <TB1> INFO: ----------------------------------------------------------------------
[22:31:02.716] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[22:31:02.716] <TB1> INFO: IA differences per ROC: 16.9 18.5 17.7 18.5 18.5 20.9 18.5 19.3 18.5 17.7 20.1 20.9 20.1 20.1 20.1 19.3
[22:31:02.751] <TB1> INFO: ----------------------------------------------------------------------
[22:31:02.751] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[22:31:02.751] <TB1> INFO: ----------------------------------------------------------------------
[22:31:10.030] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 395.5 mA = 24.7188 mA/ROC
[22:31:10.030] <TB1> INFO: i(loss) [mA/ROC]: 19.3 19.3 20.9 19.3 20.1 19.3 19.3 19.3 19.3 20.1 19.3 19.3 19.3 19.3 19.3 19.3
[22:31:10.058] <TB1> INFO: ----------------------------------------------------------------------
[22:31:10.058] <TB1> INFO: PixTestPretest::findTiming()
[22:31:10.058] <TB1> INFO: ----------------------------------------------------------------------
[22:31:10.058] <TB1> INFO: PixTestCmd::init()

[22:31:41.225] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[22:31:41.225] <TB1> INFO: (success/tries = 100/100), width = 4
[22:31:42.733] <TB1> INFO: ----------------------------------------------------------------------
[22:31:42.733] <TB1> INFO: PixTestPretest::findWorkingPixel()
[22:31:42.733] <TB1> INFO: ----------------------------------------------------------------------
[22:31:42.824] <TB1> INFO: Expecting 231680 events.
[22:31:52.498] <TB1> INFO: 231680 events read in total (9082ms).
[22:31:52.504] <TB1> INFO: Test took 9769ms.
[22:31:52.749] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[22:31:52.779] <TB1> INFO: ----------------------------------------------------------------------
[22:31:52.779] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[22:31:52.779] <TB1> INFO: ----------------------------------------------------------------------
[22:31:52.871] <TB1> INFO: Expecting 231680 events.
[22:32:02.533] <TB1> INFO: 231680 events read in total (9070ms).
[22:32:02.541] <TB1> INFO: Test took 9758ms.
[22:32:02.796] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[22:32:02.796] <TB1> INFO: CalDel: 95 83 97 90 92 91 109 110 100 85 78 86 111 100 94 86
[22:32:02.796] <TB1> INFO: VthrComp: 52 51 53 52 51 51 51 51 51 55 52 51 51 51 52 52
[22:32:02.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C0.dat
[22:32:02.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C1.dat
[22:32:02.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C2.dat
[22:32:02.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C3.dat
[22:32:02.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C4.dat
[22:32:02.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C5.dat
[22:32:02.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C6.dat
[22:32:02.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C7.dat
[22:32:02.800] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C8.dat
[22:32:02.800] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C9.dat
[22:32:02.800] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C10.dat
[22:32:02.800] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C11.dat
[22:32:02.800] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C12.dat
[22:32:02.800] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C13.dat
[22:32:02.800] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C14.dat
[22:32:02.800] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters_C15.dat
[22:32:02.800] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[22:32:02.801] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[22:32:02.801] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[22:32:02.801] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[22:32:02.801] <TB1> INFO: PixTestPretest::doTest() done, duration: 78 seconds
[22:32:02.904] <TB1> INFO: enter test to run
[22:32:02.904] <TB1> INFO: test: fulltest no parameter change
[22:32:02.904] <TB1> INFO: running: fulltest
[22:32:02.904] <TB1> INFO: ######################################################################
[22:32:02.904] <TB1> INFO: PixTestFullTest::doTest()
[22:32:02.904] <TB1> INFO: ######################################################################
[22:32:02.905] <TB1> INFO: ######################################################################
[22:32:02.906] <TB1> INFO: PixTestAlive::doTest()
[22:32:02.906] <TB1> INFO: ######################################################################
[22:32:02.907] <TB1> INFO: ----------------------------------------------------------------------
[22:32:02.907] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[22:32:02.907] <TB1> INFO: ----------------------------------------------------------------------
[22:32:03.185] <TB1> INFO: Expecting 41600 events.
[22:32:06.621] <TB1> INFO: 41600 events read in total (2845ms).
[22:32:06.622] <TB1> INFO: Test took 3714ms.
[22:32:06.849] <TB1> INFO: PixTestAlive::aliveTest() done
[22:32:06.849] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[22:32:06.850] <TB1> INFO: ----------------------------------------------------------------------
[22:32:06.850] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[22:32:06.850] <TB1> INFO: ----------------------------------------------------------------------
[22:32:07.085] <TB1> INFO: Expecting 41600 events.
[22:32:10.123] <TB1> INFO: 41600 events read in total (2446ms).
[22:32:10.123] <TB1> INFO: Test took 3272ms.
[22:32:10.123] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[22:32:10.363] <TB1> INFO: PixTestAlive::maskTest() done
[22:32:10.363] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[22:32:10.364] <TB1> INFO: ----------------------------------------------------------------------
[22:32:10.364] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[22:32:10.364] <TB1> INFO: ----------------------------------------------------------------------
[22:32:10.616] <TB1> INFO: Expecting 41600 events.
[22:32:14.054] <TB1> INFO: 41600 events read in total (2847ms).
[22:32:14.055] <TB1> INFO: Test took 3689ms.
[22:32:14.284] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[22:32:14.284] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[22:32:14.284] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[22:32:14.284] <TB1> INFO: Decoding statistics:
[22:32:14.284] <TB1> INFO: General information:
[22:32:14.284] <TB1> INFO: 16bit words read: 0
[22:32:14.284] <TB1> INFO: valid events total: 0
[22:32:14.284] <TB1> INFO: empty events: 0
[22:32:14.284] <TB1> INFO: valid events with pixels: 0
[22:32:14.284] <TB1> INFO: valid pixel hits: 0
[22:32:14.284] <TB1> INFO: Event errors: 0
[22:32:14.284] <TB1> INFO: start marker: 0
[22:32:14.284] <TB1> INFO: stop marker: 0
[22:32:14.284] <TB1> INFO: overflow: 0
[22:32:14.284] <TB1> INFO: invalid 5bit words: 0
[22:32:14.284] <TB1> INFO: invalid XOR eye diagram: 0
[22:32:14.284] <TB1> INFO: frame (failed synchr.): 0
[22:32:14.284] <TB1> INFO: idle data (no TBM trl): 0
[22:32:14.284] <TB1> INFO: no data (only TBM hdr): 0
[22:32:14.284] <TB1> INFO: TBM errors: 0
[22:32:14.284] <TB1> INFO: flawed TBM headers: 0
[22:32:14.284] <TB1> INFO: flawed TBM trailers: 0
[22:32:14.284] <TB1> INFO: event ID mismatches: 0
[22:32:14.284] <TB1> INFO: ROC errors: 0
[22:32:14.284] <TB1> INFO: missing ROC header(s): 0
[22:32:14.284] <TB1> INFO: misplaced readback start: 0
[22:32:14.284] <TB1> INFO: Pixel decoding errors: 0
[22:32:14.284] <TB1> INFO: pixel data incomplete: 0
[22:32:14.284] <TB1> INFO: pixel address: 0
[22:32:14.284] <TB1> INFO: pulse height fill bit: 0
[22:32:14.284] <TB1> INFO: buffer corruption: 0
[22:32:14.292] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C15.dat
[22:32:14.292] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[22:32:14.292] <TB1> INFO: ######################################################################
[22:32:14.292] <TB1> INFO: PixTestReadback::doTest()
[22:32:14.292] <TB1> INFO: ######################################################################
[22:32:14.292] <TB1> INFO: ----------------------------------------------------------------------
[22:32:14.292] <TB1> INFO: PixTestReadback::CalibrateVd()
[22:32:14.292] <TB1> INFO: ----------------------------------------------------------------------
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C0.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C1.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C2.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C3.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C4.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C5.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C6.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C7.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C8.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C9.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C10.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C11.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C12.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C13.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C14.dat
[22:32:24.249] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C15.dat
[22:32:24.277] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[22:32:24.277] <TB1> INFO: ----------------------------------------------------------------------
[22:32:24.277] <TB1> INFO: PixTestReadback::CalibrateVa()
[22:32:24.277] <TB1> INFO: ----------------------------------------------------------------------
[22:32:34.167] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C0.dat
[22:32:34.167] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C1.dat
[22:32:34.167] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C2.dat
[22:32:34.168] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C3.dat
[22:32:34.168] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C4.dat
[22:32:34.168] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C5.dat
[22:32:34.168] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C6.dat
[22:32:34.168] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C7.dat
[22:32:34.168] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C8.dat
[22:32:34.168] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C9.dat
[22:32:34.168] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C10.dat
[22:32:34.168] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C11.dat
[22:32:34.168] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C12.dat
[22:32:34.168] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C13.dat
[22:32:34.168] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C14.dat
[22:32:34.168] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C15.dat
[22:32:34.196] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[22:32:34.196] <TB1> INFO: ----------------------------------------------------------------------
[22:32:34.196] <TB1> INFO: PixTestReadback::readbackVbg()
[22:32:34.196] <TB1> INFO: ----------------------------------------------------------------------
[22:32:41.839] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[22:32:41.839] <TB1> INFO: ----------------------------------------------------------------------
[22:32:41.839] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[22:32:41.839] <TB1> INFO: ----------------------------------------------------------------------
[22:32:41.839] <TB1> INFO: Vbg will be calibrated using Vd calibration
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 152.7calibrated Vbg = 1.16488 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 147.9calibrated Vbg = 1.15845 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 159.1calibrated Vbg = 1.15119 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 160calibrated Vbg = 1.145 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 153.9calibrated Vbg = 1.15674 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 157.3calibrated Vbg = 1.16085 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 155.6calibrated Vbg = 1.16126 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 146.8calibrated Vbg = 1.1653 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 146calibrated Vbg = 1.15638 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 162.4calibrated Vbg = 1.15003 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 149.8calibrated Vbg = 1.14327 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 156calibrated Vbg = 1.1456 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 153.2calibrated Vbg = 1.14862 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 155.1calibrated Vbg = 1.1606 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 156.1calibrated Vbg = 1.15522 :::*/*/*/*/
[22:32:41.839] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 152.5calibrated Vbg = 1.15786 :::*/*/*/*/
[22:32:41.841] <TB1> INFO: ----------------------------------------------------------------------
[22:32:41.841] <TB1> INFO: PixTestReadback::CalibrateIa()
[22:32:41.841] <TB1> INFO: ----------------------------------------------------------------------
[22:35:22.117] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C0.dat
[22:35:22.118] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C1.dat
[22:35:22.118] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C2.dat
[22:35:22.118] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C3.dat
[22:35:22.118] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C4.dat
[22:35:22.118] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C5.dat
[22:35:22.118] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C6.dat
[22:35:22.118] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C7.dat
[22:35:22.118] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C8.dat
[22:35:22.118] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C9.dat
[22:35:22.118] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C10.dat
[22:35:22.118] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C11.dat
[22:35:22.118] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C12.dat
[22:35:22.118] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C13.dat
[22:35:22.118] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C14.dat
[22:35:22.119] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//readbackCal_C15.dat
[22:35:22.146] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[22:35:22.147] <TB1> INFO: PixTestReadback::doTest() done
[22:35:22.147] <TB1> INFO: Decoding statistics:
[22:35:22.147] <TB1> INFO: General information:
[22:35:22.147] <TB1> INFO: 16bit words read: 1536
[22:35:22.147] <TB1> INFO: valid events total: 256
[22:35:22.147] <TB1> INFO: empty events: 256
[22:35:22.147] <TB1> INFO: valid events with pixels: 0
[22:35:22.147] <TB1> INFO: valid pixel hits: 0
[22:35:22.147] <TB1> INFO: Event errors: 0
[22:35:22.147] <TB1> INFO: start marker: 0
[22:35:22.147] <TB1> INFO: stop marker: 0
[22:35:22.147] <TB1> INFO: overflow: 0
[22:35:22.147] <TB1> INFO: invalid 5bit words: 0
[22:35:22.147] <TB1> INFO: invalid XOR eye diagram: 0
[22:35:22.147] <TB1> INFO: frame (failed synchr.): 0
[22:35:22.147] <TB1> INFO: idle data (no TBM trl): 0
[22:35:22.147] <TB1> INFO: no data (only TBM hdr): 0
[22:35:22.147] <TB1> INFO: TBM errors: 0
[22:35:22.147] <TB1> INFO: flawed TBM headers: 0
[22:35:22.147] <TB1> INFO: flawed TBM trailers: 0
[22:35:22.147] <TB1> INFO: event ID mismatches: 0
[22:35:22.147] <TB1> INFO: ROC errors: 0
[22:35:22.147] <TB1> INFO: missing ROC header(s): 0
[22:35:22.147] <TB1> INFO: misplaced readback start: 0
[22:35:22.147] <TB1> INFO: Pixel decoding errors: 0
[22:35:22.147] <TB1> INFO: pixel data incomplete: 0
[22:35:22.147] <TB1> INFO: pixel address: 0
[22:35:22.147] <TB1> INFO: pulse height fill bit: 0
[22:35:22.147] <TB1> INFO: buffer corruption: 0
[22:35:22.182] <TB1> INFO: ######################################################################
[22:35:22.182] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[22:35:22.182] <TB1> INFO: ######################################################################
[22:35:22.184] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[22:35:22.195] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[22:35:22.195] <TB1> INFO: run 1 of 1
[22:35:22.442] <TB1> INFO: Expecting 3120000 events.
[22:35:53.065] <TB1> INFO: 688905 events read in total (30031ms).











[22:36:23.092] <TB1> INFO: 1371400 events read in total (60058ms).











[22:36:53.084] <TB1> INFO: 2048825 events read in total (90050ms).











[22:37:23.048] <TB1> INFO: 2724315 events read in total (120014ms).











[22:37:41.233] <TB1> INFO: 3120000 events read in total (138199ms).
[22:37:41.283] <TB1> INFO: Test took 139088ms.
[22:38:05.604] <TB1> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 163 seconds
[22:38:05.604] <TB1> INFO: number of dead bumps (per ROC): 2 0 0 0 0 0 0 0 1 0 0 0 0 1 0 2
[22:38:05.604] <TB1> INFO: separation cut (per ROC): 104 124 119 122 106 116 123 106 113 125 119 124 130 116 112 119
[22:38:05.604] <TB1> INFO: Decoding statistics:
[22:38:05.604] <TB1> INFO: General information:
[22:38:05.604] <TB1> INFO: 16bit words read: 0
[22:38:05.604] <TB1> INFO: valid events total: 0
[22:38:05.604] <TB1> INFO: empty events: 0
[22:38:05.604] <TB1> INFO: valid events with pixels: 0
[22:38:05.604] <TB1> INFO: valid pixel hits: 0
[22:38:05.604] <TB1> INFO: Event errors: 0
[22:38:05.604] <TB1> INFO: start marker: 0
[22:38:05.604] <TB1> INFO: stop marker: 0
[22:38:05.604] <TB1> INFO: overflow: 0
[22:38:05.604] <TB1> INFO: invalid 5bit words: 0
[22:38:05.604] <TB1> INFO: invalid XOR eye diagram: 0
[22:38:05.604] <TB1> INFO: frame (failed synchr.): 0
[22:38:05.604] <TB1> INFO: idle data (no TBM trl): 0
[22:38:05.604] <TB1> INFO: no data (only TBM hdr): 0
[22:38:05.604] <TB1> INFO: TBM errors: 0
[22:38:05.604] <TB1> INFO: flawed TBM headers: 0
[22:38:05.604] <TB1> INFO: flawed TBM trailers: 0
[22:38:05.604] <TB1> INFO: event ID mismatches: 0
[22:38:05.604] <TB1> INFO: ROC errors: 0
[22:38:05.604] <TB1> INFO: missing ROC header(s): 0
[22:38:05.604] <TB1> INFO: misplaced readback start: 0
[22:38:05.604] <TB1> INFO: Pixel decoding errors: 0
[22:38:05.604] <TB1> INFO: pixel data incomplete: 0
[22:38:05.604] <TB1> INFO: pixel address: 0
[22:38:05.604] <TB1> INFO: pulse height fill bit: 0
[22:38:05.604] <TB1> INFO: buffer corruption: 0
[22:38:05.656] <TB1> INFO: ######################################################################
[22:38:05.656] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[22:38:05.657] <TB1> INFO: ######################################################################
[22:38:05.657] <TB1> INFO: ----------------------------------------------------------------------
[22:38:05.657] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[22:38:05.657] <TB1> INFO: ----------------------------------------------------------------------
[22:38:05.657] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[22:38:05.671] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[22:38:05.671] <TB1> INFO: run 1 of 1
[22:38:05.938] <TB1> INFO: Expecting 36608000 events.
[22:38:29.885] <TB1> INFO: 712000 events read in total (23355ms).
[22:38:52.724] <TB1> INFO: 1408450 events read in total (46194ms).
[22:39:15.742] <TB1> INFO: 2106450 events read in total (69212ms).
[22:39:38.730] <TB1> INFO: 2801000 events read in total (92200ms).
[22:40:01.596] <TB1> INFO: 3491800 events read in total (115066ms).
[22:40:24.222] <TB1> INFO: 4181950 events read in total (137692ms).
[22:40:46.774] <TB1> INFO: 4872050 events read in total (160244ms).
[22:41:09.784] <TB1> INFO: 5559650 events read in total (183254ms).
[22:41:32.247] <TB1> INFO: 6247550 events read in total (205717ms).
[22:41:54.986] <TB1> INFO: 6935600 events read in total (228456ms).
[22:42:17.582] <TB1> INFO: 7622350 events read in total (251052ms).
[22:42:40.651] <TB1> INFO: 8309050 events read in total (274121ms).
[22:43:03.426] <TB1> INFO: 8996000 events read in total (296896ms).
[22:43:25.949] <TB1> INFO: 9681500 events read in total (319419ms).
[22:43:48.642] <TB1> INFO: 10366200 events read in total (342112ms).
[22:44:11.483] <TB1> INFO: 11051700 events read in total (364953ms).
[22:44:33.795] <TB1> INFO: 11736300 events read in total (387265ms).
[22:44:56.350] <TB1> INFO: 12419000 events read in total (409820ms).
[22:45:18.953] <TB1> INFO: 13103050 events read in total (432423ms).
[22:45:41.444] <TB1> INFO: 13788050 events read in total (454914ms).
[22:46:04.095] <TB1> INFO: 14470700 events read in total (477565ms).
[22:46:26.777] <TB1> INFO: 15151300 events read in total (500247ms).
[22:46:49.381] <TB1> INFO: 15832750 events read in total (522851ms).
[22:47:12.095] <TB1> INFO: 16514600 events read in total (545565ms).
[22:47:34.746] <TB1> INFO: 17196700 events read in total (568216ms).
[22:47:57.421] <TB1> INFO: 17875750 events read in total (590891ms).
[22:48:20.189] <TB1> INFO: 18555000 events read in total (613659ms).
[22:48:42.610] <TB1> INFO: 19233150 events read in total (636080ms).
[22:49:05.263] <TB1> INFO: 19910850 events read in total (658733ms).
[22:49:27.855] <TB1> INFO: 20588250 events read in total (681325ms).
[22:49:50.481] <TB1> INFO: 21264700 events read in total (703951ms).
[22:50:12.698] <TB1> INFO: 21939600 events read in total (726168ms).
[22:50:35.206] <TB1> INFO: 22613900 events read in total (748676ms).
[22:50:57.727] <TB1> INFO: 23291000 events read in total (771197ms).
[22:51:20.298] <TB1> INFO: 23967100 events read in total (793768ms).
[22:51:42.816] <TB1> INFO: 24642700 events read in total (816286ms).
[22:52:05.586] <TB1> INFO: 25318600 events read in total (839056ms).
[22:52:28.113] <TB1> INFO: 25994850 events read in total (861583ms).
[22:52:51.112] <TB1> INFO: 26670150 events read in total (884582ms).
[22:53:13.690] <TB1> INFO: 27345550 events read in total (907160ms).
[22:53:36.371] <TB1> INFO: 28020100 events read in total (929841ms).
[22:53:58.959] <TB1> INFO: 28695250 events read in total (952429ms).
[22:54:21.554] <TB1> INFO: 29370550 events read in total (975024ms).
[22:54:44.119] <TB1> INFO: 30043200 events read in total (997589ms).
[22:55:06.864] <TB1> INFO: 30717350 events read in total (1020334ms).
[22:55:29.171] <TB1> INFO: 31389100 events read in total (1042641ms).
[22:55:51.839] <TB1> INFO: 32064950 events read in total (1065309ms).
[22:56:14.511] <TB1> INFO: 32742250 events read in total (1087981ms).
[22:56:37.302] <TB1> INFO: 33421700 events read in total (1110772ms).
[22:56:59.805] <TB1> INFO: 34101550 events read in total (1133276ms).
[22:57:22.536] <TB1> INFO: 34781550 events read in total (1156006ms).
[22:57:45.263] <TB1> INFO: 35460550 events read in total (1178733ms).
[22:58:08.056] <TB1> INFO: 36146650 events read in total (1201526ms).
[22:58:23.262] <TB1> INFO: 36608000 events read in total (1216732ms).
[22:58:23.327] <TB1> INFO: Test took 1217656ms.
[22:58:23.641] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:25.512] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:27.531] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:29.456] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:31.364] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:33.304] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:35.220] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:36.839] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:38.668] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:40.518] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:42.348] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:44.582] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:46.424] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:48.459] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:50.116] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:52.075] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[22:58:54.029] <TB1> INFO: PixTestScurves::scurves() done
[22:58:54.029] <TB1> INFO: Vcal mean: 126.63 134.41 132.93 129.07 127.21 131.18 125.79 116.84 122.16 133.55 125.55 133.06 132.12 120.55 126.05 127.81
[22:58:54.029] <TB1> INFO: Vcal RMS: 6.20 5.79 6.28 5.79 6.82 6.46 6.34 6.22 6.11 6.78 6.41 6.57 6.23 6.12 6.46 6.55
[22:58:54.029] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1248 seconds
[22:58:54.029] <TB1> INFO: Decoding statistics:
[22:58:54.029] <TB1> INFO: General information:
[22:58:54.029] <TB1> INFO: 16bit words read: 0
[22:58:54.029] <TB1> INFO: valid events total: 0
[22:58:54.029] <TB1> INFO: empty events: 0
[22:58:54.029] <TB1> INFO: valid events with pixels: 0
[22:58:54.030] <TB1> INFO: valid pixel hits: 0
[22:58:54.030] <TB1> INFO: Event errors: 0
[22:58:54.030] <TB1> INFO: start marker: 0
[22:58:54.030] <TB1> INFO: stop marker: 0
[22:58:54.030] <TB1> INFO: overflow: 0
[22:58:54.030] <TB1> INFO: invalid 5bit words: 0
[22:58:54.030] <TB1> INFO: invalid XOR eye diagram: 0
[22:58:54.030] <TB1> INFO: frame (failed synchr.): 0
[22:58:54.030] <TB1> INFO: idle data (no TBM trl): 0
[22:58:54.030] <TB1> INFO: no data (only TBM hdr): 0
[22:58:54.030] <TB1> INFO: TBM errors: 0
[22:58:54.030] <TB1> INFO: flawed TBM headers: 0
[22:58:54.030] <TB1> INFO: flawed TBM trailers: 0
[22:58:54.030] <TB1> INFO: event ID mismatches: 0
[22:58:54.030] <TB1> INFO: ROC errors: 0
[22:58:54.030] <TB1> INFO: missing ROC header(s): 0
[22:58:54.030] <TB1> INFO: misplaced readback start: 0
[22:58:54.030] <TB1> INFO: Pixel decoding errors: 0
[22:58:54.030] <TB1> INFO: pixel data incomplete: 0
[22:58:54.030] <TB1> INFO: pixel address: 0
[22:58:54.030] <TB1> INFO: pulse height fill bit: 0
[22:58:54.030] <TB1> INFO: buffer corruption: 0
[22:58:54.118] <TB1> INFO: ######################################################################
[22:58:54.118] <TB1> INFO: PixTestTrim::doTest()
[22:58:54.118] <TB1> INFO: ######################################################################
[22:58:54.119] <TB1> INFO: ----------------------------------------------------------------------
[22:58:54.119] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[22:58:54.119] <TB1> INFO: ----------------------------------------------------------------------
[22:58:54.186] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[22:58:54.186] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[22:58:54.198] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[22:58:54.198] <TB1> INFO: run 1 of 1
[22:58:54.517] <TB1> INFO: Expecting 5025280 events.
[22:59:25.206] <TB1> INFO: 836176 events read in total (30092ms).
[22:59:55.109] <TB1> INFO: 1669312 events read in total (59995ms).
[23:00:24.695] <TB1> INFO: 2499640 events read in total (89582ms).
[23:00:54.530] <TB1> INFO: 3325952 events read in total (119416ms).
[23:01:24.187] <TB1> INFO: 4149088 events read in total (149073ms).
[23:01:53.883] <TB1> INFO: 4971264 events read in total (178769ms).
[23:01:56.323] <TB1> INFO: 5025280 events read in total (181209ms).
[23:01:56.365] <TB1> INFO: Test took 182167ms.
[23:02:12.782] <TB1> INFO: ROC 0 VthrComp = 127
[23:02:12.782] <TB1> INFO: ROC 1 VthrComp = 134
[23:02:12.782] <TB1> INFO: ROC 2 VthrComp = 134
[23:02:12.782] <TB1> INFO: ROC 3 VthrComp = 130
[23:02:12.782] <TB1> INFO: ROC 4 VthrComp = 127
[23:02:12.782] <TB1> INFO: ROC 5 VthrComp = 128
[23:02:12.782] <TB1> INFO: ROC 6 VthrComp = 128
[23:02:12.783] <TB1> INFO: ROC 7 VthrComp = 113
[23:02:12.783] <TB1> INFO: ROC 8 VthrComp = 117
[23:02:12.783] <TB1> INFO: ROC 9 VthrComp = 133
[23:02:12.783] <TB1> INFO: ROC 10 VthrComp = 133
[23:02:12.783] <TB1> INFO: ROC 11 VthrComp = 135
[23:02:12.783] <TB1> INFO: ROC 12 VthrComp = 132
[23:02:12.783] <TB1> INFO: ROC 13 VthrComp = 123
[23:02:12.784] <TB1> INFO: ROC 14 VthrComp = 127
[23:02:12.784] <TB1> INFO: ROC 15 VthrComp = 128
[23:02:13.018] <TB1> INFO: Expecting 41600 events.
[23:02:16.487] <TB1> INFO: 41600 events read in total (2878ms).
[23:02:16.488] <TB1> INFO: Test took 3703ms.
[23:02:16.500] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[23:02:16.500] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[23:02:16.510] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[23:02:16.510] <TB1> INFO: run 1 of 1
[23:02:16.788] <TB1> INFO: Expecting 5025280 events.
[23:02:43.414] <TB1> INFO: 592168 events read in total (26034ms).
[23:03:08.465] <TB1> INFO: 1182960 events read in total (51085ms).
[23:03:33.727] <TB1> INFO: 1773112 events read in total (76347ms).
[23:03:59.016] <TB1> INFO: 2362944 events read in total (101636ms).
[23:04:24.119] <TB1> INFO: 2950936 events read in total (126739ms).
[23:04:49.182] <TB1> INFO: 3537040 events read in total (151802ms).
[23:05:14.173] <TB1> INFO: 4122104 events read in total (176793ms).
[23:05:39.345] <TB1> INFO: 4708136 events read in total (201965ms).
[23:05:53.322] <TB1> INFO: 5025280 events read in total (215942ms).
[23:05:53.387] <TB1> INFO: Test took 216876ms.
[23:06:20.985] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 59.9793 for pixel 16/3 mean/min/max = 45.678/31.3446/60.0114
[23:06:20.985] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 63.0297 for pixel 4/19 mean/min/max = 49.105/35.1086/63.1015
[23:06:20.986] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 62.3521 for pixel 9/9 mean/min/max = 48.2897/34.2227/62.3568
[23:06:20.986] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 60.8997 for pixel 0/1 mean/min/max = 47.0219/33.0333/61.0106
[23:06:20.986] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 62.855 for pixel 2/18 mean/min/max = 47.0649/31.2081/62.9218
[23:06:20.987] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 64.1639 for pixel 2/61 mean/min/max = 49.5131/34.7951/64.231
[23:06:20.987] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 59.803 for pixel 22/7 mean/min/max = 45.5964/31.3571/59.8358
[23:06:20.987] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 61.8352 for pixel 15/2 mean/min/max = 47.1312/32.354/61.9084
[23:06:20.988] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 61.5311 for pixel 5/78 mean/min/max = 46.7514/31.8869/61.616
[23:06:20.988] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 63.9472 for pixel 1/14 mean/min/max = 48.6813/33.2602/64.1023
[23:06:20.988] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 59.4514 for pixel 28/12 mean/min/max = 46.02/32.4685/59.5715
[23:06:20.989] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 59.4108 for pixel 5/41 mean/min/max = 45.9609/32.3573/59.5646
[23:06:20.989] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 59.3855 for pixel 16/1 mean/min/max = 46.1798/32.8466/59.5129
[23:06:20.989] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 60.7701 for pixel 5/2 mean/min/max = 45.9394/30.9875/60.8913
[23:06:20.990] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 60.9069 for pixel 23/2 mean/min/max = 46.5075/31.8748/61.1402
[23:06:20.990] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 62.4729 for pixel 20/24 mean/min/max = 47.5024/32.465/62.5399
[23:06:20.990] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:06:21.079] <TB1> INFO: Expecting 411648 events.
[23:06:30.597] <TB1> INFO: 411648 events read in total (8925ms).
[23:06:30.604] <TB1> INFO: Expecting 411648 events.
[23:06:39.819] <TB1> INFO: 411648 events read in total (8812ms).
[23:06:39.834] <TB1> INFO: Expecting 411648 events.
[23:06:49.237] <TB1> INFO: 411648 events read in total (9000ms).
[23:06:49.249] <TB1> INFO: Expecting 411648 events.
[23:06:58.337] <TB1> INFO: 411648 events read in total (8684ms).
[23:06:58.351] <TB1> INFO: Expecting 411648 events.
[23:07:07.394] <TB1> INFO: 411648 events read in total (8640ms).
[23:07:07.414] <TB1> INFO: Expecting 411648 events.
[23:07:16.456] <TB1> INFO: 411648 events read in total (8639ms).
[23:07:16.477] <TB1> INFO: Expecting 411648 events.
[23:07:25.541] <TB1> INFO: 411648 events read in total (8661ms).
[23:07:25.566] <TB1> INFO: Expecting 411648 events.
[23:07:34.626] <TB1> INFO: 411648 events read in total (8657ms).
[23:07:34.650] <TB1> INFO: Expecting 411648 events.
[23:07:43.669] <TB1> INFO: 411648 events read in total (8616ms).
[23:07:43.697] <TB1> INFO: Expecting 411648 events.
[23:07:52.725] <TB1> INFO: 411648 events read in total (8625ms).
[23:07:52.755] <TB1> INFO: Expecting 411648 events.
[23:08:01.811] <TB1> INFO: 411648 events read in total (8645ms).
[23:08:01.856] <TB1> INFO: Expecting 411648 events.
[23:08:10.910] <TB1> INFO: 411648 events read in total (8651ms).
[23:08:10.955] <TB1> INFO: Expecting 411648 events.
[23:08:19.963] <TB1> INFO: 411648 events read in total (8605ms).
[23:08:20.014] <TB1> INFO: Expecting 411648 events.
[23:08:29.018] <TB1> INFO: 411648 events read in total (8601ms).
[23:08:29.060] <TB1> INFO: Expecting 411648 events.
[23:08:38.130] <TB1> INFO: 411648 events read in total (8668ms).
[23:08:38.176] <TB1> INFO: Expecting 411648 events.
[23:08:47.177] <TB1> INFO: 411648 events read in total (8598ms).
[23:08:47.225] <TB1> INFO: Test took 146235ms.
[23:08:47.845] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[23:08:47.855] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[23:08:47.855] <TB1> INFO: run 1 of 1
[23:08:48.092] <TB1> INFO: Expecting 5025280 events.
[23:09:14.033] <TB1> INFO: 592416 events read in total (25350ms).
[23:09:39.390] <TB1> INFO: 1184880 events read in total (50707ms).
[23:10:05.373] <TB1> INFO: 1774256 events read in total (76690ms).
[23:10:31.133] <TB1> INFO: 2364208 events read in total (102450ms).
[23:10:56.817] <TB1> INFO: 2953200 events read in total (128134ms).
[23:11:22.734] <TB1> INFO: 3547064 events read in total (154051ms).
[23:11:48.581] <TB1> INFO: 4140592 events read in total (179898ms).
[23:12:13.984] <TB1> INFO: 4730472 events read in total (205301ms).
[23:12:27.004] <TB1> INFO: 5025280 events read in total (218321ms).
[23:12:27.162] <TB1> INFO: Test took 219308ms.
[23:12:51.703] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 8.557190 .. 146.276118
[23:12:51.943] <TB1> INFO: Expecting 208000 events.
[23:13:01.643] <TB1> INFO: 208000 events read in total (9109ms).
[23:13:01.644] <TB1> INFO: Test took 9940ms.
[23:13:01.692] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 8 .. 156 (-1/-1) hits flags = 528 (plus default)
[23:13:01.702] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[23:13:01.702] <TB1> INFO: run 1 of 1
[23:13:01.980] <TB1> INFO: Expecting 4958720 events.
[23:13:27.806] <TB1> INFO: 575960 events read in total (25234ms).
[23:13:52.652] <TB1> INFO: 1151920 events read in total (50080ms).
[23:14:17.673] <TB1> INFO: 1727592 events read in total (75101ms).
[23:14:43.019] <TB1> INFO: 2303184 events read in total (100447ms).
[23:15:08.460] <TB1> INFO: 2878456 events read in total (125888ms).
[23:15:33.672] <TB1> INFO: 3452608 events read in total (151100ms).
[23:15:59.033] <TB1> INFO: 4026336 events read in total (176461ms).
[23:16:24.268] <TB1> INFO: 4599696 events read in total (201696ms).
[23:16:39.742] <TB1> INFO: 4958720 events read in total (217170ms).
[23:16:39.835] <TB1> INFO: Test took 218132ms.
[23:17:07.627] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.904820 .. 47.023699
[23:17:07.871] <TB1> INFO: Expecting 208000 events.
[23:17:17.790] <TB1> INFO: 208000 events read in total (9328ms).
[23:17:17.790] <TB1> INFO: Test took 10161ms.
[23:17:17.842] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 57 (-1/-1) hits flags = 528 (plus default)
[23:17:17.851] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[23:17:17.851] <TB1> INFO: run 1 of 1
[23:17:18.129] <TB1> INFO: Expecting 1364480 events.
[23:17:45.936] <TB1> INFO: 654560 events read in total (27215ms).
[23:18:12.850] <TB1> INFO: 1306128 events read in total (54129ms).
[23:18:15.648] <TB1> INFO: 1364480 events read in total (56928ms).
[23:18:15.674] <TB1> INFO: Test took 57824ms.
[23:18:29.934] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 28.438555 .. 47.132981
[23:18:30.211] <TB1> INFO: Expecting 208000 events.
[23:18:39.774] <TB1> INFO: 208000 events read in total (8971ms).
[23:18:39.775] <TB1> INFO: Test took 9839ms.
[23:18:39.822] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 18 .. 57 (-1/-1) hits flags = 528 (plus default)
[23:18:39.833] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[23:18:39.833] <TB1> INFO: run 1 of 1
[23:18:40.111] <TB1> INFO: Expecting 1331200 events.
[23:19:07.916] <TB1> INFO: 649384 events read in total (27214ms).
[23:19:35.178] <TB1> INFO: 1296968 events read in total (54476ms).
[23:19:37.090] <TB1> INFO: 1331200 events read in total (56388ms).
[23:19:37.120] <TB1> INFO: Test took 57287ms.
[23:19:50.923] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 26.160059 .. 46.134666
[23:19:51.162] <TB1> INFO: Expecting 208000 events.
[23:20:00.830] <TB1> INFO: 208000 events read in total (9076ms).
[23:20:00.831] <TB1> INFO: Test took 9906ms.
[23:20:00.897] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 56 (-1/-1) hits flags = 528 (plus default)
[23:20:00.909] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[23:20:00.909] <TB1> INFO: run 1 of 1
[23:20:01.187] <TB1> INFO: Expecting 1364480 events.
[23:20:29.372] <TB1> INFO: 660200 events read in total (27593ms).
[23:20:56.841] <TB1> INFO: 1320136 events read in total (55062ms).
[23:20:59.027] <TB1> INFO: 1364480 events read in total (57248ms).
[23:20:59.049] <TB1> INFO: Test took 58140ms.
[23:21:13.133] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[23:21:13.133] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[23:21:13.143] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[23:21:13.143] <TB1> INFO: run 1 of 1
[23:21:13.375] <TB1> INFO: Expecting 1364480 events.
[23:21:41.932] <TB1> INFO: 668336 events read in total (27965ms).
[23:22:09.549] <TB1> INFO: 1335984 events read in total (55582ms).
[23:22:11.172] <TB1> INFO: 1364480 events read in total (57205ms).
[23:22:11.195] <TB1> INFO: Test took 58052ms.
[23:22:23.002] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C0.dat
[23:22:23.002] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C1.dat
[23:22:23.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C2.dat
[23:22:23.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C3.dat
[23:22:23.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C4.dat
[23:22:23.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C5.dat
[23:22:24.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C6.dat
[23:22:24.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C7.dat
[23:22:24.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C8.dat
[23:22:24.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C9.dat
[23:22:24.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C10.dat
[23:22:24.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C11.dat
[23:22:24.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C12.dat
[23:22:24.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C13.dat
[23:22:24.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C14.dat
[23:22:24.004] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C15.dat
[23:22:24.004] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C0.dat
[23:22:24.009] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C1.dat
[23:22:24.015] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C2.dat
[23:22:24.021] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C3.dat
[23:22:24.026] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C4.dat
[23:22:24.032] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C5.dat
[23:22:24.037] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C6.dat
[23:22:24.043] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C7.dat
[23:22:24.049] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C8.dat
[23:22:24.054] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C9.dat
[23:22:24.060] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C10.dat
[23:22:24.065] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C11.dat
[23:22:24.071] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C12.dat
[23:22:24.077] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C13.dat
[23:22:24.082] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C14.dat
[23:22:24.088] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters35_C15.dat
[23:22:24.093] <TB1> INFO: PixTestTrim::trimTest() done
[23:22:24.093] <TB1> INFO: vtrim: 132 151 144 148 152 150 149 140 114 141 142 134 141 142 132 155
[23:22:24.093] <TB1> INFO: vthrcomp: 127 134 134 130 127 128 128 113 117 133 133 135 132 123 127 128
[23:22:24.093] <TB1> INFO: vcal mean: 34.96 35.11 35.10 35.05 35.03 35.07 34.98 34.95 34.96 35.21 35.00 35.04 35.01 34.93 35.01 35.05
[23:22:24.093] <TB1> INFO: vcal RMS: 1.16 1.19 1.15 1.14 1.21 1.14 1.03 1.12 1.11 1.26 1.07 1.08 1.03 1.11 1.04 1.13
[23:22:24.093] <TB1> INFO: bits mean: 10.05 9.02 9.10 9.57 9.92 8.60 10.42 9.51 9.47 9.16 9.80 10.08 10.07 10.35 9.40 9.67
[23:22:24.093] <TB1> INFO: bits RMS: 2.57 2.34 2.47 2.57 2.56 2.47 2.36 2.59 2.71 2.54 2.51 2.39 2.37 2.40 2.80 2.47
[23:22:24.100] <TB1> INFO: ----------------------------------------------------------------------
[23:22:24.100] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[23:22:24.100] <TB1> INFO: ----------------------------------------------------------------------
[23:22:24.103] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[23:22:24.113] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[23:22:24.113] <TB1> INFO: run 1 of 1
[23:22:24.376] <TB1> INFO: Expecting 4160000 events.
[23:22:57.990] <TB1> INFO: 786115 events read in total (33022ms).
[23:23:30.107] <TB1> INFO: 1560025 events read in total (65139ms).
[23:24:02.254] <TB1> INFO: 2326330 events read in total (97286ms).
[23:24:34.189] <TB1> INFO: 3087360 events read in total (129221ms).
[23:25:06.010] <TB1> INFO: 3847740 events read in total (161042ms).
[23:25:19.128] <TB1> INFO: 4160000 events read in total (174160ms).
[23:25:19.182] <TB1> INFO: Test took 175069ms.
[23:25:44.863] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[23:25:44.873] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[23:25:44.873] <TB1> INFO: run 1 of 1
[23:25:45.112] <TB1> INFO: Expecting 4326400 events.
[23:26:18.146] <TB1> INFO: 746520 events read in total (32442ms).
[23:26:49.478] <TB1> INFO: 1483745 events read in total (63774ms).
[23:27:20.712] <TB1> INFO: 2216645 events read in total (95008ms).
[23:27:51.819] <TB1> INFO: 2944425 events read in total (126115ms).
[23:28:22.976] <TB1> INFO: 3670240 events read in total (157272ms).
[23:28:50.851] <TB1> INFO: 4326400 events read in total (185147ms).
[23:28:50.908] <TB1> INFO: Test took 186035ms.
[23:29:18.543] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[23:29:18.554] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[23:29:18.554] <TB1> INFO: run 1 of 1
[23:29:18.836] <TB1> INFO: Expecting 4430400 events.
[23:29:51.997] <TB1> INFO: 740180 events read in total (32569ms).
[23:30:22.804] <TB1> INFO: 1472210 events read in total (63376ms).
[23:30:54.017] <TB1> INFO: 2199245 events read in total (94589ms).
[23:31:25.258] <TB1> INFO: 2921890 events read in total (125830ms).
[23:31:56.075] <TB1> INFO: 3642530 events read in total (156647ms).
[23:32:27.023] <TB1> INFO: 4365985 events read in total (187595ms).
[23:32:30.180] <TB1> INFO: 4430400 events read in total (190752ms).
[23:32:30.246] <TB1> INFO: Test took 191692ms.
[23:33:00.528] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 217 (-1/-1) hits flags = 528 (plus default)
[23:33:00.540] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[23:33:00.540] <TB1> INFO: run 1 of 1
[23:33:00.820] <TB1> INFO: Expecting 4534400 events.
[23:33:33.441] <TB1> INFO: 734400 events read in total (32029ms).
[23:34:04.583] <TB1> INFO: 1460260 events read in total (63171ms).
[23:34:35.595] <TB1> INFO: 2182110 events read in total (94183ms).
[23:35:06.902] <TB1> INFO: 2899165 events read in total (125490ms).
[23:35:37.765] <TB1> INFO: 3614725 events read in total (156353ms).
[23:36:08.810] <TB1> INFO: 4330715 events read in total (187398ms).
[23:36:18.018] <TB1> INFO: 4534400 events read in total (196606ms).
[23:36:18.084] <TB1> INFO: Test took 197543ms.
[23:36:50.128] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 218 (-1/-1) hits flags = 528 (plus default)
[23:36:50.138] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[23:36:50.138] <TB1> INFO: run 1 of 1
[23:36:50.370] <TB1> INFO: Expecting 4555200 events.
[23:37:22.438] <TB1> INFO: 733355 events read in total (31476ms).
[23:37:53.420] <TB1> INFO: 1458020 events read in total (62458ms).
[23:38:24.519] <TB1> INFO: 2178840 events read in total (93557ms).
[23:38:55.615] <TB1> INFO: 2895025 events read in total (124653ms).
[23:39:26.411] <TB1> INFO: 3609795 events read in total (155449ms).
[23:39:57.850] <TB1> INFO: 4324735 events read in total (186888ms).
[23:40:08.146] <TB1> INFO: 4555200 events read in total (197184ms).
[23:40:08.206] <TB1> INFO: Test took 198067ms.
[23:40:36.695] <TB1> INFO: PixTestTrim::trimBitTest() done
[23:40:36.696] <TB1> INFO: PixTestTrim::doTest() done, duration: 2502 seconds
[23:40:36.696] <TB1> INFO: Decoding statistics:
[23:40:36.696] <TB1> INFO: General information:
[23:40:36.696] <TB1> INFO: 16bit words read: 0
[23:40:36.696] <TB1> INFO: valid events total: 0
[23:40:36.696] <TB1> INFO: empty events: 0
[23:40:36.696] <TB1> INFO: valid events with pixels: 0
[23:40:36.696] <TB1> INFO: valid pixel hits: 0
[23:40:36.696] <TB1> INFO: Event errors: 0
[23:40:36.696] <TB1> INFO: start marker: 0
[23:40:36.696] <TB1> INFO: stop marker: 0
[23:40:36.696] <TB1> INFO: overflow: 0
[23:40:36.696] <TB1> INFO: invalid 5bit words: 0
[23:40:36.696] <TB1> INFO: invalid XOR eye diagram: 0
[23:40:36.696] <TB1> INFO: frame (failed synchr.): 0
[23:40:36.696] <TB1> INFO: idle data (no TBM trl): 0
[23:40:36.696] <TB1> INFO: no data (only TBM hdr): 0
[23:40:36.696] <TB1> INFO: TBM errors: 0
[23:40:36.696] <TB1> INFO: flawed TBM headers: 0
[23:40:36.696] <TB1> INFO: flawed TBM trailers: 0
[23:40:36.696] <TB1> INFO: event ID mismatches: 0
[23:40:36.696] <TB1> INFO: ROC errors: 0
[23:40:36.696] <TB1> INFO: missing ROC header(s): 0
[23:40:36.696] <TB1> INFO: misplaced readback start: 0
[23:40:36.696] <TB1> INFO: Pixel decoding errors: 0
[23:40:36.696] <TB1> INFO: pixel data incomplete: 0
[23:40:36.696] <TB1> INFO: pixel address: 0
[23:40:36.696] <TB1> INFO: pulse height fill bit: 0
[23:40:36.696] <TB1> INFO: buffer corruption: 0
[23:40:37.329] <TB1> INFO: ######################################################################
[23:40:37.330] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[23:40:37.330] <TB1> INFO: ######################################################################
[23:40:37.605] <TB1> INFO: Expecting 41600 events.
[23:40:41.196] <TB1> INFO: 41600 events read in total (2999ms).
[23:40:41.197] <TB1> INFO: Test took 3866ms.
[23:40:41.673] <TB1> INFO: Expecting 41600 events.
[23:40:45.121] <TB1> INFO: 41600 events read in total (2857ms).
[23:40:45.122] <TB1> INFO: Test took 3724ms.
[23:40:45.410] <TB1> INFO: Expecting 41600 events.
[23:40:48.944] <TB1> INFO: 41600 events read in total (2942ms).
[23:40:48.945] <TB1> INFO: Test took 3799ms.
[23:40:49.234] <TB1> INFO: Expecting 41600 events.
[23:40:52.772] <TB1> INFO: 41600 events read in total (2947ms).
[23:40:52.772] <TB1> INFO: Test took 3803ms.
[23:40:53.074] <TB1> INFO: Expecting 41600 events.
[23:40:56.603] <TB1> INFO: 41600 events read in total (2937ms).
[23:40:56.604] <TB1> INFO: Test took 3805ms.
[23:40:56.895] <TB1> INFO: Expecting 41600 events.
[23:41:00.414] <TB1> INFO: 41600 events read in total (2928ms).
[23:41:00.415] <TB1> INFO: Test took 3788ms.
[23:41:00.703] <TB1> INFO: Expecting 41600 events.
[23:41:04.310] <TB1> INFO: 41600 events read in total (3016ms).
[23:41:04.311] <TB1> INFO: Test took 3873ms.
[23:41:04.599] <TB1> INFO: Expecting 41600 events.
[23:41:08.082] <TB1> INFO: 41600 events read in total (2892ms).
[23:41:08.083] <TB1> INFO: Test took 3749ms.
[23:41:08.374] <TB1> INFO: Expecting 41600 events.
[23:41:11.920] <TB1> INFO: 41600 events read in total (2955ms).
[23:41:11.921] <TB1> INFO: Test took 3812ms.
[23:41:12.209] <TB1> INFO: Expecting 41600 events.
[23:41:15.774] <TB1> INFO: 41600 events read in total (2974ms).
[23:41:15.775] <TB1> INFO: Test took 3831ms.
[23:41:16.063] <TB1> INFO: Expecting 41600 events.
[23:41:19.598] <TB1> INFO: 41600 events read in total (2943ms).
[23:41:19.599] <TB1> INFO: Test took 3801ms.
[23:41:19.887] <TB1> INFO: Expecting 41600 events.
[23:41:23.470] <TB1> INFO: 41600 events read in total (2991ms).
[23:41:23.471] <TB1> INFO: Test took 3849ms.
[23:41:23.759] <TB1> INFO: Expecting 41600 events.
[23:41:27.461] <TB1> INFO: 41600 events read in total (3110ms).
[23:41:27.462] <TB1> INFO: Test took 3968ms.
[23:41:27.754] <TB1> INFO: Expecting 41600 events.
[23:41:31.299] <TB1> INFO: 41600 events read in total (2954ms).
[23:41:31.300] <TB1> INFO: Test took 3811ms.
[23:41:31.590] <TB1> INFO: Expecting 41600 events.
[23:41:35.054] <TB1> INFO: 41600 events read in total (2873ms).
[23:41:35.055] <TB1> INFO: Test took 3730ms.
[23:41:35.346] <TB1> INFO: Expecting 41600 events.
[23:41:38.808] <TB1> INFO: 41600 events read in total (2870ms).
[23:41:38.809] <TB1> INFO: Test took 3727ms.
[23:41:39.151] <TB1> INFO: Expecting 41600 events.
[23:41:42.670] <TB1> INFO: 41600 events read in total (2928ms).
[23:41:42.671] <TB1> INFO: Test took 3838ms.
[23:41:43.015] <TB1> INFO: Expecting 41600 events.
[23:41:46.557] <TB1> INFO: 41600 events read in total (2950ms).
[23:41:46.558] <TB1> INFO: Test took 3862ms.
[23:41:46.847] <TB1> INFO: Expecting 41600 events.
[23:41:50.296] <TB1> INFO: 41600 events read in total (2858ms).
[23:41:50.297] <TB1> INFO: Test took 3715ms.
[23:41:50.587] <TB1> INFO: Expecting 41600 events.
[23:41:54.039] <TB1> INFO: 41600 events read in total (2860ms).
[23:41:54.040] <TB1> INFO: Test took 3717ms.
[23:41:54.332] <TB1> INFO: Expecting 41600 events.
[23:41:57.780] <TB1> INFO: 41600 events read in total (2857ms).
[23:41:57.781] <TB1> INFO: Test took 3717ms.
[23:41:58.069] <TB1> INFO: Expecting 41600 events.
[23:42:01.549] <TB1> INFO: 41600 events read in total (2889ms).
[23:42:01.550] <TB1> INFO: Test took 3746ms.
[23:42:01.841] <TB1> INFO: Expecting 41600 events.
[23:42:05.421] <TB1> INFO: 41600 events read in total (2988ms).
[23:42:05.421] <TB1> INFO: Test took 3844ms.
[23:42:05.710] <TB1> INFO: Expecting 41600 events.
[23:42:09.168] <TB1> INFO: 41600 events read in total (2867ms).
[23:42:09.169] <TB1> INFO: Test took 3724ms.
[23:42:09.457] <TB1> INFO: Expecting 41600 events.
[23:42:12.988] <TB1> INFO: 41600 events read in total (2940ms).
[23:42:12.989] <TB1> INFO: Test took 3797ms.
[23:42:13.277] <TB1> INFO: Expecting 41600 events.
[23:42:16.713] <TB1> INFO: 41600 events read in total (2845ms).
[23:42:16.713] <TB1> INFO: Test took 3701ms.
[23:42:16.001] <TB1> INFO: Expecting 41600 events.
[23:42:20.485] <TB1> INFO: 41600 events read in total (2892ms).
[23:42:20.485] <TB1> INFO: Test took 3748ms.
[23:42:20.776] <TB1> INFO: Expecting 41600 events.
[23:42:24.237] <TB1> INFO: 41600 events read in total (2869ms).
[23:42:24.237] <TB1> INFO: Test took 3726ms.
[23:42:24.527] <TB1> INFO: Expecting 41600 events.
[23:42:27.980] <TB1> INFO: 41600 events read in total (2862ms).
[23:42:27.981] <TB1> INFO: Test took 3719ms.
[23:42:28.269] <TB1> INFO: Expecting 2560 events.
[23:42:29.154] <TB1> INFO: 2560 events read in total (293ms).
[23:42:29.155] <TB1> INFO: Test took 1162ms.
[23:42:29.462] <TB1> INFO: Expecting 2560 events.
[23:42:30.343] <TB1> INFO: 2560 events read in total (289ms).
[23:42:30.344] <TB1> INFO: Test took 1189ms.
[23:42:30.652] <TB1> INFO: Expecting 2560 events.
[23:42:31.535] <TB1> INFO: 2560 events read in total (292ms).
[23:42:31.535] <TB1> INFO: Test took 1191ms.
[23:42:31.843] <TB1> INFO: Expecting 2560 events.
[23:42:32.725] <TB1> INFO: 2560 events read in total (290ms).
[23:42:32.725] <TB1> INFO: Test took 1189ms.
[23:42:33.033] <TB1> INFO: Expecting 2560 events.
[23:42:33.913] <TB1> INFO: 2560 events read in total (289ms).
[23:42:33.913] <TB1> INFO: Test took 1188ms.
[23:42:34.221] <TB1> INFO: Expecting 2560 events.
[23:42:35.101] <TB1> INFO: 2560 events read in total (288ms).
[23:42:35.101] <TB1> INFO: Test took 1187ms.
[23:42:35.409] <TB1> INFO: Expecting 2560 events.
[23:42:36.291] <TB1> INFO: 2560 events read in total (290ms).
[23:42:36.291] <TB1> INFO: Test took 1190ms.
[23:42:36.599] <TB1> INFO: Expecting 2560 events.
[23:42:37.477] <TB1> INFO: 2560 events read in total (287ms).
[23:42:37.477] <TB1> INFO: Test took 1186ms.
[23:42:37.785] <TB1> INFO: Expecting 2560 events.
[23:42:38.664] <TB1> INFO: 2560 events read in total (287ms).
[23:42:38.664] <TB1> INFO: Test took 1186ms.
[23:42:38.972] <TB1> INFO: Expecting 2560 events.
[23:42:39.852] <TB1> INFO: 2560 events read in total (288ms).
[23:42:39.852] <TB1> INFO: Test took 1187ms.
[23:42:40.159] <TB1> INFO: Expecting 2560 events.
[23:42:41.037] <TB1> INFO: 2560 events read in total (286ms).
[23:42:41.037] <TB1> INFO: Test took 1185ms.
[23:42:41.346] <TB1> INFO: Expecting 2560 events.
[23:42:42.224] <TB1> INFO: 2560 events read in total (287ms).
[23:42:42.224] <TB1> INFO: Test took 1186ms.
[23:42:42.532] <TB1> INFO: Expecting 2560 events.
[23:42:43.414] <TB1> INFO: 2560 events read in total (291ms).
[23:42:43.414] <TB1> INFO: Test took 1190ms.
[23:42:43.722] <TB1> INFO: Expecting 2560 events.
[23:42:44.604] <TB1> INFO: 2560 events read in total (290ms).
[23:42:44.605] <TB1> INFO: Test took 1191ms.
[23:42:44.912] <TB1> INFO: Expecting 2560 events.
[23:42:45.795] <TB1> INFO: 2560 events read in total (291ms).
[23:42:45.795] <TB1> INFO: Test took 1190ms.
[23:42:46.103] <TB1> INFO: Expecting 2560 events.
[23:42:46.986] <TB1> INFO: 2560 events read in total (292ms).
[23:42:46.987] <TB1> INFO: Test took 1192ms.
[23:42:46.990] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:42:47.295] <TB1> INFO: Expecting 655360 events.
[23:43:01.446] <TB1> INFO: 655360 events read in total (13560ms).
[23:43:01.462] <TB1> INFO: Expecting 655360 events.
[23:43:15.422] <TB1> INFO: 655360 events read in total (13557ms).
[23:43:15.436] <TB1> INFO: Expecting 655360 events.
[23:43:29.445] <TB1> INFO: 655360 events read in total (13606ms).
[23:43:29.465] <TB1> INFO: Expecting 655360 events.
[23:43:43.457] <TB1> INFO: 655360 events read in total (13589ms).
[23:43:43.481] <TB1> INFO: Expecting 655360 events.
[23:43:57.509] <TB1> INFO: 655360 events read in total (13625ms).
[23:43:57.537] <TB1> INFO: Expecting 655360 events.
[23:44:11.554] <TB1> INFO: 655360 events read in total (13614ms).
[23:44:11.589] <TB1> INFO: Expecting 655360 events.
[23:44:25.617] <TB1> INFO: 655360 events read in total (13625ms).
[23:44:25.659] <TB1> INFO: Expecting 655360 events.
[23:44:39.670] <TB1> INFO: 655360 events read in total (13608ms).
[23:44:39.711] <TB1> INFO: Expecting 655360 events.
[23:44:53.714] <TB1> INFO: 655360 events read in total (13600ms).
[23:44:53.777] <TB1> INFO: Expecting 655360 events.
[23:45:07.812] <TB1> INFO: 655360 events read in total (13632ms).
[23:45:07.863] <TB1> INFO: Expecting 655360 events.
[23:45:21.882] <TB1> INFO: 655360 events read in total (13616ms).
[23:45:21.956] <TB1> INFO: Expecting 655360 events.
[23:45:36.068] <TB1> INFO: 655360 events read in total (13709ms).
[23:45:36.136] <TB1> INFO: Expecting 655360 events.
[23:45:50.344] <TB1> INFO: 655360 events read in total (13805ms).
[23:45:50.430] <TB1> INFO: Expecting 655360 events.
[23:46:04.427] <TB1> INFO: 655360 events read in total (13594ms).
[23:46:04.503] <TB1> INFO: Expecting 655360 events.
[23:46:18.544] <TB1> INFO: 655360 events read in total (13638ms).
[23:46:18.640] <TB1> INFO: Expecting 655360 events.
[23:46:32.630] <TB1> INFO: 655360 events read in total (13588ms).
[23:46:32.706] <TB1> INFO: Test took 225716ms.
[23:46:32.783] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:46:33.048] <TB1> INFO: Expecting 655360 events.
[23:46:47.148] <TB1> INFO: 655360 events read in total (13507ms).
[23:46:47.162] <TB1> INFO: Expecting 655360 events.
[23:47:00.937] <TB1> INFO: 655360 events read in total (13372ms).
[23:47:00.957] <TB1> INFO: Expecting 655360 events.
[23:47:14.927] <TB1> INFO: 655360 events read in total (13566ms).
[23:47:14.954] <TB1> INFO: Expecting 655360 events.
[23:47:28.982] <TB1> INFO: 655360 events read in total (13625ms).
[23:47:29.016] <TB1> INFO: Expecting 655360 events.
[23:47:42.953] <TB1> INFO: 655360 events read in total (13534ms).
[23:47:42.992] <TB1> INFO: Expecting 655360 events.
[23:47:56.903] <TB1> INFO: 655360 events read in total (13508ms).
[23:47:56.937] <TB1> INFO: Expecting 655360 events.
[23:48:10.905] <TB1> INFO: 655360 events read in total (13565ms).
[23:48:10.945] <TB1> INFO: Expecting 655360 events.
[23:48:24.799] <TB1> INFO: 655360 events read in total (13451ms).
[23:48:24.838] <TB1> INFO: Expecting 655360 events.
[23:48:38.744] <TB1> INFO: 655360 events read in total (13503ms).
[23:48:38.793] <TB1> INFO: Expecting 655360 events.
[23:48:52.791] <TB1> INFO: 655360 events read in total (13595ms).
[23:48:52.842] <TB1> INFO: Expecting 655360 events.
[23:49:06.723] <TB1> INFO: 655360 events read in total (13479ms).
[23:49:06.777] <TB1> INFO: Expecting 655360 events.
[23:49:20.797] <TB1> INFO: 655360 events read in total (13617ms).
[23:49:20.854] <TB1> INFO: Expecting 655360 events.
[23:49:34.832] <TB1> INFO: 655360 events read in total (13575ms).
[23:49:34.893] <TB1> INFO: Expecting 655360 events.
[23:49:48.957] <TB1> INFO: 655360 events read in total (13661ms).
[23:49:49.048] <TB1> INFO: Expecting 655360 events.
[23:50:03.149] <TB1> INFO: 655360 events read in total (13698ms).
[23:50:03.244] <TB1> INFO: Expecting 655360 events.
[23:50:17.489] <TB1> INFO: 655360 events read in total (13842ms).
[23:50:17.564] <TB1> INFO: Test took 224781ms.
[23:50:17.787] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.793] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.800] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.806] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.813] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[23:50:17.819] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[23:50:17.825] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[23:50:17.832] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.839] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.845] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.851] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.858] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.864] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[23:50:17.871] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[23:50:17.877] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[23:50:17.883] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[23:50:17.890] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[23:50:17.896] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[23:50:17.903] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.909] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.915] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.922] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.928] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.935] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[23:50:17.941] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[23:50:17.947] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.954] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[23:50:17.960] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[23:50:17.967] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[23:50:17.973] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[23:50:18.009] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C0.dat
[23:50:18.010] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C1.dat
[23:50:18.010] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C2.dat
[23:50:18.010] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C3.dat
[23:50:18.010] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C4.dat
[23:50:18.010] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C5.dat
[23:50:18.010] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C6.dat
[23:50:18.010] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C7.dat
[23:50:18.010] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C8.dat
[23:50:18.010] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C9.dat
[23:50:18.010] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C10.dat
[23:50:18.010] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C11.dat
[23:50:18.010] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C12.dat
[23:50:18.011] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C13.dat
[23:50:18.011] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C14.dat
[23:50:18.011] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters35_C15.dat
[23:50:18.244] <TB1> INFO: Expecting 41600 events.
[23:50:21.397] <TB1> INFO: 41600 events read in total (2561ms).
[23:50:21.398] <TB1> INFO: Test took 3385ms.
[23:50:21.842] <TB1> INFO: Expecting 41600 events.
[23:50:24.904] <TB1> INFO: 41600 events read in total (2471ms).
[23:50:24.905] <TB1> INFO: Test took 3295ms.
[23:50:25.353] <TB1> INFO: Expecting 41600 events.
[23:50:28.464] <TB1> INFO: 41600 events read in total (2520ms).
[23:50:28.465] <TB1> INFO: Test took 3349ms.
[23:50:28.684] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:28.772] <TB1> INFO: Expecting 2560 events.
[23:50:29.659] <TB1> INFO: 2560 events read in total (295ms).
[23:50:29.659] <TB1> INFO: Test took 975ms.
[23:50:29.661] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:29.967] <TB1> INFO: Expecting 2560 events.
[23:50:30.854] <TB1> INFO: 2560 events read in total (295ms).
[23:50:30.854] <TB1> INFO: Test took 1193ms.
[23:50:30.856] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:31.162] <TB1> INFO: Expecting 2560 events.
[23:50:32.045] <TB1> INFO: 2560 events read in total (291ms).
[23:50:32.045] <TB1> INFO: Test took 1189ms.
[23:50:32.047] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:32.353] <TB1> INFO: Expecting 2560 events.
[23:50:33.236] <TB1> INFO: 2560 events read in total (291ms).
[23:50:33.236] <TB1> INFO: Test took 1189ms.
[23:50:33.238] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:33.544] <TB1> INFO: Expecting 2560 events.
[23:50:34.428] <TB1> INFO: 2560 events read in total (292ms).
[23:50:34.428] <TB1> INFO: Test took 1190ms.
[23:50:34.430] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:34.737] <TB1> INFO: Expecting 2560 events.
[23:50:35.619] <TB1> INFO: 2560 events read in total (291ms).
[23:50:35.620] <TB1> INFO: Test took 1190ms.
[23:50:35.622] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:35.928] <TB1> INFO: Expecting 2560 events.
[23:50:36.814] <TB1> INFO: 2560 events read in total (294ms).
[23:50:36.814] <TB1> INFO: Test took 1193ms.
[23:50:36.816] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:37.122] <TB1> INFO: Expecting 2560 events.
[23:50:38.007] <TB1> INFO: 2560 events read in total (293ms).
[23:50:38.007] <TB1> INFO: Test took 1191ms.
[23:50:38.009] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:38.315] <TB1> INFO: Expecting 2560 events.
[23:50:39.197] <TB1> INFO: 2560 events read in total (290ms).
[23:50:39.197] <TB1> INFO: Test took 1188ms.
[23:50:39.199] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:39.505] <TB1> INFO: Expecting 2560 events.
[23:50:40.388] <TB1> INFO: 2560 events read in total (291ms).
[23:50:40.388] <TB1> INFO: Test took 1189ms.
[23:50:40.390] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:40.697] <TB1> INFO: Expecting 2560 events.
[23:50:41.575] <TB1> INFO: 2560 events read in total (287ms).
[23:50:41.575] <TB1> INFO: Test took 1185ms.
[23:50:41.577] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:41.884] <TB1> INFO: Expecting 2560 events.
[23:50:42.763] <TB1> INFO: 2560 events read in total (287ms).
[23:50:42.763] <TB1> INFO: Test took 1186ms.
[23:50:42.765] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:43.072] <TB1> INFO: Expecting 2560 events.
[23:50:43.954] <TB1> INFO: 2560 events read in total (291ms).
[23:50:43.954] <TB1> INFO: Test took 1189ms.
[23:50:43.956] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:44.262] <TB1> INFO: Expecting 2560 events.
[23:50:45.141] <TB1> INFO: 2560 events read in total (287ms).
[23:50:45.141] <TB1> INFO: Test took 1185ms.
[23:50:45.143] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:45.449] <TB1> INFO: Expecting 2560 events.
[23:50:46.327] <TB1> INFO: 2560 events read in total (286ms).
[23:50:46.327] <TB1> INFO: Test took 1184ms.
[23:50:46.329] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:46.635] <TB1> INFO: Expecting 2560 events.
[23:50:47.517] <TB1> INFO: 2560 events read in total (290ms).
[23:50:47.517] <TB1> INFO: Test took 1188ms.
[23:50:47.519] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:47.826] <TB1> INFO: Expecting 2560 events.
[23:50:48.708] <TB1> INFO: 2560 events read in total (291ms).
[23:50:48.709] <TB1> INFO: Test took 1190ms.
[23:50:48.710] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:49.017] <TB1> INFO: Expecting 2560 events.
[23:50:49.900] <TB1> INFO: 2560 events read in total (291ms).
[23:50:49.900] <TB1> INFO: Test took 1190ms.
[23:50:49.902] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:50.208] <TB1> INFO: Expecting 2560 events.
[23:50:51.087] <TB1> INFO: 2560 events read in total (287ms).
[23:50:51.087] <TB1> INFO: Test took 1185ms.
[23:50:51.089] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:51.396] <TB1> INFO: Expecting 2560 events.
[23:50:52.279] <TB1> INFO: 2560 events read in total (292ms).
[23:50:52.279] <TB1> INFO: Test took 1190ms.
[23:50:52.281] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:52.587] <TB1> INFO: Expecting 2560 events.
[23:50:53.466] <TB1> INFO: 2560 events read in total (287ms).
[23:50:53.466] <TB1> INFO: Test took 1185ms.
[23:50:53.468] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:53.774] <TB1> INFO: Expecting 2560 events.
[23:50:54.653] <TB1> INFO: 2560 events read in total (287ms).
[23:50:54.653] <TB1> INFO: Test took 1185ms.
[23:50:54.655] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:54.962] <TB1> INFO: Expecting 2560 events.
[23:50:55.840] <TB1> INFO: 2560 events read in total (287ms).
[23:50:55.840] <TB1> INFO: Test took 1186ms.
[23:50:55.842] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:56.149] <TB1> INFO: Expecting 2560 events.
[23:50:57.029] <TB1> INFO: 2560 events read in total (289ms).
[23:50:57.029] <TB1> INFO: Test took 1188ms.
[23:50:57.031] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:57.337] <TB1> INFO: Expecting 2560 events.
[23:50:58.220] <TB1> INFO: 2560 events read in total (291ms).
[23:50:58.220] <TB1> INFO: Test took 1189ms.
[23:50:58.223] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:58.529] <TB1> INFO: Expecting 2560 events.
[23:50:59.411] <TB1> INFO: 2560 events read in total (290ms).
[23:50:59.411] <TB1> INFO: Test took 1188ms.
[23:50:59.413] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:50:59.720] <TB1> INFO: Expecting 2560 events.
[23:51:00.604] <TB1> INFO: 2560 events read in total (293ms).
[23:51:00.605] <TB1> INFO: Test took 1192ms.
[23:51:00.607] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:51:00.913] <TB1> INFO: Expecting 2560 events.
[23:51:01.796] <TB1> INFO: 2560 events read in total (292ms).
[23:51:01.796] <TB1> INFO: Test took 1189ms.
[23:51:01.798] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:51:02.104] <TB1> INFO: Expecting 2560 events.
[23:51:02.990] <TB1> INFO: 2560 events read in total (294ms).
[23:51:02.990] <TB1> INFO: Test took 1192ms.
[23:51:02.992] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:51:03.299] <TB1> INFO: Expecting 2560 events.
[23:51:04.185] <TB1> INFO: 2560 events read in total (295ms).
[23:51:04.186] <TB1> INFO: Test took 1194ms.
[23:51:04.187] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:51:04.494] <TB1> INFO: Expecting 2560 events.
[23:51:05.380] <TB1> INFO: 2560 events read in total (294ms).
[23:51:05.380] <TB1> INFO: Test took 1193ms.
[23:51:05.382] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[23:51:05.689] <TB1> INFO: Expecting 2560 events.
[23:51:06.572] <TB1> INFO: 2560 events read in total (292ms).
[23:51:06.572] <TB1> INFO: Test took 1190ms.
[23:51:07.034] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 629 seconds
[23:51:07.035] <TB1> INFO: PH scale (per ROC): 43 45 49 53 54 46 44 37 38 39 47 36 55 38 39 43
[23:51:07.035] <TB1> INFO: PH offset (per ROC): 106 113 126 127 123 107 115 109 112 97 92 106 124 97 105 101
[23:51:07.040] <TB1> INFO: Decoding statistics:
[23:51:07.040] <TB1> INFO: General information:
[23:51:07.040] <TB1> INFO: 16bit words read: 127880
[23:51:07.040] <TB1> INFO: valid events total: 20480
[23:51:07.040] <TB1> INFO: empty events: 17980
[23:51:07.040] <TB1> INFO: valid events with pixels: 2500
[23:51:07.040] <TB1> INFO: valid pixel hits: 2500
[23:51:07.040] <TB1> INFO: Event errors: 0
[23:51:07.041] <TB1> INFO: start marker: 0
[23:51:07.041] <TB1> INFO: stop marker: 0
[23:51:07.041] <TB1> INFO: overflow: 0
[23:51:07.041] <TB1> INFO: invalid 5bit words: 0
[23:51:07.041] <TB1> INFO: invalid XOR eye diagram: 0
[23:51:07.041] <TB1> INFO: frame (failed synchr.): 0
[23:51:07.041] <TB1> INFO: idle data (no TBM trl): 0
[23:51:07.041] <TB1> INFO: no data (only TBM hdr): 0
[23:51:07.041] <TB1> INFO: TBM errors: 0
[23:51:07.041] <TB1> INFO: flawed TBM headers: 0
[23:51:07.041] <TB1> INFO: flawed TBM trailers: 0
[23:51:07.041] <TB1> INFO: event ID mismatches: 0
[23:51:07.041] <TB1> INFO: ROC errors: 0
[23:51:07.041] <TB1> INFO: missing ROC header(s): 0
[23:51:07.041] <TB1> INFO: misplaced readback start: 0
[23:51:07.041] <TB1> INFO: Pixel decoding errors: 0
[23:51:07.041] <TB1> INFO: pixel data incomplete: 0
[23:51:07.041] <TB1> INFO: pixel address: 0
[23:51:07.041] <TB1> INFO: pulse height fill bit: 0
[23:51:07.041] <TB1> INFO: buffer corruption: 0
[23:51:07.391] <TB1> INFO: ######################################################################
[23:51:07.391] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[23:51:07.391] <TB1> INFO: ######################################################################
[23:51:07.403] <TB1> INFO: scanning low vcal = 10
[23:51:07.634] <TB1> INFO: Expecting 41600 events.
[23:51:11.204] <TB1> INFO: 41600 events read in total (2978ms).
[23:51:11.204] <TB1> INFO: Test took 3801ms.
[23:51:11.206] <TB1> INFO: scanning low vcal = 20
[23:51:11.505] <TB1> INFO: Expecting 41600 events.
[23:51:15.067] <TB1> INFO: 41600 events read in total (2970ms).
[23:51:15.067] <TB1> INFO: Test took 3861ms.
[23:51:15.069] <TB1> INFO: scanning low vcal = 30
[23:51:15.368] <TB1> INFO: Expecting 41600 events.
[23:51:18.997] <TB1> INFO: 41600 events read in total (3038ms).
[23:51:18.998] <TB1> INFO: Test took 3929ms.
[23:51:18.001] <TB1> INFO: scanning low vcal = 40
[23:51:19.278] <TB1> INFO: Expecting 41600 events.
[23:51:23.241] <TB1> INFO: 41600 events read in total (3372ms).
[23:51:23.243] <TB1> INFO: Test took 4242ms.
[23:51:23.246] <TB1> INFO: scanning low vcal = 50
[23:51:23.522] <TB1> INFO: Expecting 41600 events.
[23:51:27.496] <TB1> INFO: 41600 events read in total (3383ms).
[23:51:27.497] <TB1> INFO: Test took 4251ms.
[23:51:27.500] <TB1> INFO: scanning low vcal = 60
[23:51:27.776] <TB1> INFO: Expecting 41600 events.
[23:51:31.750] <TB1> INFO: 41600 events read in total (3382ms).
[23:51:31.751] <TB1> INFO: Test took 4251ms.
[23:51:31.754] <TB1> INFO: scanning low vcal = 70
[23:51:32.031] <TB1> INFO: Expecting 41600 events.
[23:51:35.991] <TB1> INFO: 41600 events read in total (3369ms).
[23:51:35.992] <TB1> INFO: Test took 4238ms.
[23:51:35.995] <TB1> INFO: scanning low vcal = 80
[23:51:36.272] <TB1> INFO: Expecting 41600 events.
[23:51:40.277] <TB1> INFO: 41600 events read in total (3414ms).
[23:51:40.278] <TB1> INFO: Test took 4283ms.
[23:51:40.281] <TB1> INFO: scanning low vcal = 90
[23:51:40.558] <TB1> INFO: Expecting 41600 events.
[23:51:44.491] <TB1> INFO: 41600 events read in total (3342ms).
[23:51:44.492] <TB1> INFO: Test took 4211ms.
[23:51:44.495] <TB1> INFO: scanning low vcal = 100
[23:51:44.771] <TB1> INFO: Expecting 41600 events.
[23:51:48.758] <TB1> INFO: 41600 events read in total (3395ms).
[23:51:48.759] <TB1> INFO: Test took 4264ms.
[23:51:48.762] <TB1> INFO: scanning low vcal = 110
[23:51:49.038] <TB1> INFO: Expecting 41600 events.
[23:51:53.003] <TB1> INFO: 41600 events read in total (3373ms).
[23:51:53.004] <TB1> INFO: Test took 4242ms.
[23:51:53.007] <TB1> INFO: scanning low vcal = 120
[23:51:53.283] <TB1> INFO: Expecting 41600 events.
[23:51:57.257] <TB1> INFO: 41600 events read in total (3382ms).
[23:51:57.257] <TB1> INFO: Test took 4250ms.
[23:51:57.260] <TB1> INFO: scanning low vcal = 130
[23:51:57.537] <TB1> INFO: Expecting 41600 events.
[23:52:01.525] <TB1> INFO: 41600 events read in total (3397ms).
[23:52:01.526] <TB1> INFO: Test took 4266ms.
[23:52:01.528] <TB1> INFO: scanning low vcal = 140
[23:52:01.805] <TB1> INFO: Expecting 41600 events.
[23:52:05.737] <TB1> INFO: 41600 events read in total (3340ms).
[23:52:05.738] <TB1> INFO: Test took 4209ms.
[23:52:05.740] <TB1> INFO: scanning low vcal = 150
[23:52:06.018] <TB1> INFO: Expecting 41600 events.
[23:52:09.952] <TB1> INFO: 41600 events read in total (3342ms).
[23:52:09.953] <TB1> INFO: Test took 4213ms.
[23:52:09.956] <TB1> INFO: scanning low vcal = 160
[23:52:10.232] <TB1> INFO: Expecting 41600 events.
[23:52:14.179] <TB1> INFO: 41600 events read in total (3355ms).
[23:52:14.180] <TB1> INFO: Test took 4224ms.
[23:52:14.183] <TB1> INFO: scanning low vcal = 170
[23:52:14.459] <TB1> INFO: Expecting 41600 events.
[23:52:18.431] <TB1> INFO: 41600 events read in total (3380ms).
[23:52:18.432] <TB1> INFO: Test took 4249ms.
[23:52:18.435] <TB1> INFO: scanning low vcal = 180
[23:52:18.711] <TB1> INFO: Expecting 41600 events.
[23:52:22.683] <TB1> INFO: 41600 events read in total (3380ms).
[23:52:22.684] <TB1> INFO: Test took 4249ms.
[23:52:22.687] <TB1> INFO: scanning low vcal = 190
[23:52:22.964] <TB1> INFO: Expecting 41600 events.
[23:52:26.920] <TB1> INFO: 41600 events read in total (3365ms).
[23:52:26.921] <TB1> INFO: Test took 4234ms.
[23:52:26.924] <TB1> INFO: scanning low vcal = 200
[23:52:27.200] <TB1> INFO: Expecting 41600 events.
[23:52:31.154] <TB1> INFO: 41600 events read in total (3362ms).
[23:52:31.155] <TB1> INFO: Test took 4231ms.
[23:52:31.158] <TB1> INFO: scanning low vcal = 210
[23:52:31.434] <TB1> INFO: Expecting 41600 events.
[23:52:35.365] <TB1> INFO: 41600 events read in total (3339ms).
[23:52:35.366] <TB1> INFO: Test took 4208ms.
[23:52:35.369] <TB1> INFO: scanning low vcal = 220
[23:52:35.645] <TB1> INFO: Expecting 41600 events.
[23:52:39.589] <TB1> INFO: 41600 events read in total (3352ms).
[23:52:39.590] <TB1> INFO: Test took 4221ms.
[23:52:39.592] <TB1> INFO: scanning low vcal = 230
[23:52:39.869] <TB1> INFO: Expecting 41600 events.
[23:52:43.806] <TB1> INFO: 41600 events read in total (3345ms).
[23:52:43.807] <TB1> INFO: Test took 4215ms.
[23:52:43.809] <TB1> INFO: scanning low vcal = 240
[23:52:44.086] <TB1> INFO: Expecting 41600 events.
[23:52:48.018] <TB1> INFO: 41600 events read in total (3340ms).
[23:52:48.019] <TB1> INFO: Test took 4210ms.
[23:52:48.022] <TB1> INFO: scanning low vcal = 250
[23:52:48.298] <TB1> INFO: Expecting 41600 events.
[23:52:52.245] <TB1> INFO: 41600 events read in total (3355ms).
[23:52:52.246] <TB1> INFO: Test took 4224ms.
[23:52:52.250] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[23:52:52.526] <TB1> INFO: Expecting 41600 events.
[23:52:56.469] <TB1> INFO: 41600 events read in total (3352ms).
[23:52:56.469] <TB1> INFO: Test took 4219ms.
[23:52:56.473] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[23:52:56.749] <TB1> INFO: Expecting 41600 events.
[23:53:00.763] <TB1> INFO: 41600 events read in total (3422ms).
[23:53:00.764] <TB1> INFO: Test took 4291ms.
[23:53:00.766] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[23:53:01.043] <TB1> INFO: Expecting 41600 events.
[23:53:05.069] <TB1> INFO: 41600 events read in total (3435ms).
[23:53:05.070] <TB1> INFO: Test took 4304ms.
[23:53:05.074] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[23:53:05.392] <TB1> INFO: Expecting 41600 events.
[23:53:09.383] <TB1> INFO: 41600 events read in total (3399ms).
[23:53:09.384] <TB1> INFO: Test took 4310ms.
[23:53:09.387] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[23:53:09.690] <TB1> INFO: Expecting 41600 events.
[23:53:13.734] <TB1> INFO: 41600 events read in total (3452ms).
[23:53:13.736] <TB1> INFO: Test took 4349ms.
[23:53:14.305] <TB1> INFO: PixTestGainPedestal::measure() done
[23:53:53.185] <TB1> INFO: PixTestGainPedestal::fit() done
[23:53:53.185] <TB1> INFO: non-linearity mean: 0.966 0.955 0.980 0.983 0.982 0.958 0.940 0.939 0.937 0.943 0.929 0.938 0.984 0.933 0.928 0.945
[23:53:53.185] <TB1> INFO: non-linearity RMS: 0.032 0.044 0.004 0.004 0.004 0.035 0.044 0.080 0.076 0.088 0.113 0.162 0.003 0.079 0.074 0.140
[23:53:53.185] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[23:53:53.208] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[23:53:53.230] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[23:53:53.252] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[23:53:53.274] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[23:53:53.296] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[23:53:53.318] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[23:53:53.340] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[23:53:53.364] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[23:53:53.388] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[23:53:53.412] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[23:53:53.436] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[23:53:53.460] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[23:53:53.482] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[23:53:53.504] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[23:53:53.528] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[23:53:53.552] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 166 seconds
[23:53:53.552] <TB1> INFO: Decoding statistics:
[23:53:53.552] <TB1> INFO: General information:
[23:53:53.552] <TB1> INFO: 16bit words read: 3309282
[23:53:53.552] <TB1> INFO: valid events total: 332800
[23:53:53.552] <TB1> INFO: empty events: 572
[23:53:53.552] <TB1> INFO: valid events with pixels: 332228
[23:53:53.552] <TB1> INFO: valid pixel hits: 656241
[23:53:53.552] <TB1> INFO: Event errors: 0
[23:53:53.552] <TB1> INFO: start marker: 0
[23:53:53.552] <TB1> INFO: stop marker: 0
[23:53:53.552] <TB1> INFO: overflow: 0
[23:53:53.552] <TB1> INFO: invalid 5bit words: 0
[23:53:53.552] <TB1> INFO: invalid XOR eye diagram: 0
[23:53:53.552] <TB1> INFO: frame (failed synchr.): 0
[23:53:53.552] <TB1> INFO: idle data (no TBM trl): 0
[23:53:53.552] <TB1> INFO: no data (only TBM hdr): 0
[23:53:53.552] <TB1> INFO: TBM errors: 0
[23:53:53.552] <TB1> INFO: flawed TBM headers: 0
[23:53:53.552] <TB1> INFO: flawed TBM trailers: 0
[23:53:53.552] <TB1> INFO: event ID mismatches: 0
[23:53:53.552] <TB1> INFO: ROC errors: 0
[23:53:53.552] <TB1> INFO: missing ROC header(s): 0
[23:53:53.552] <TB1> INFO: misplaced readback start: 0
[23:53:53.552] <TB1> INFO: Pixel decoding errors: 0
[23:53:53.552] <TB1> INFO: pixel data incomplete: 0
[23:53:53.552] <TB1> INFO: pixel address: 0
[23:53:53.552] <TB1> INFO: pulse height fill bit: 0
[23:53:53.552] <TB1> INFO: buffer corruption: 0
[23:53:53.574] <TB1> INFO: Decoding statistics:
[23:53:53.574] <TB1> INFO: General information:
[23:53:53.574] <TB1> INFO: 16bit words read: 3438698
[23:53:53.574] <TB1> INFO: valid events total: 353536
[23:53:53.574] <TB1> INFO: empty events: 18808
[23:53:53.574] <TB1> INFO: valid events with pixels: 334728
[23:53:53.574] <TB1> INFO: valid pixel hits: 658741
[23:53:53.574] <TB1> INFO: Event errors: 0
[23:53:53.574] <TB1> INFO: start marker: 0
[23:53:53.574] <TB1> INFO: stop marker: 0
[23:53:53.574] <TB1> INFO: overflow: 0
[23:53:53.574] <TB1> INFO: invalid 5bit words: 0
[23:53:53.574] <TB1> INFO: invalid XOR eye diagram: 0
[23:53:53.574] <TB1> INFO: frame (failed synchr.): 0
[23:53:53.574] <TB1> INFO: idle data (no TBM trl): 0
[23:53:53.574] <TB1> INFO: no data (only TBM hdr): 0
[23:53:53.574] <TB1> INFO: TBM errors: 0
[23:53:53.574] <TB1> INFO: flawed TBM headers: 0
[23:53:53.574] <TB1> INFO: flawed TBM trailers: 0
[23:53:53.574] <TB1> INFO: event ID mismatches: 0
[23:53:53.574] <TB1> INFO: ROC errors: 0
[23:53:53.574] <TB1> INFO: missing ROC header(s): 0
[23:53:53.574] <TB1> INFO: misplaced readback start: 0
[23:53:53.574] <TB1> INFO: Pixel decoding errors: 0
[23:53:53.574] <TB1> INFO: pixel data incomplete: 0
[23:53:53.574] <TB1> INFO: pixel address: 0
[23:53:53.574] <TB1> INFO: pulse height fill bit: 0
[23:53:53.574] <TB1> INFO: buffer corruption: 0
[23:53:53.574] <TB1> INFO: enter test to run
[23:53:53.574] <TB1> INFO: test: Trim80 no parameter change
[23:53:53.574] <TB1> INFO: running: trim80
[23:53:53.597] <TB1> INFO: ######################################################################
[23:53:53.597] <TB1> INFO: PixTestTrim80::doTest()
[23:53:53.597] <TB1> INFO: ######################################################################
[23:53:53.598] <TB1> INFO: ----------------------------------------------------------------------
[23:53:53.598] <TB1> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[23:53:53.598] <TB1> INFO: ----------------------------------------------------------------------
[23:53:53.639] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[23:53:53.639] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[23:53:53.649] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[23:53:53.649] <TB1> INFO: run 1 of 1
[23:53:53.923] <TB1> INFO: Expecting 5025280 events.
[23:54:22.079] <TB1> INFO: 687776 events read in total (27564ms).
[23:54:49.352] <TB1> INFO: 1370568 events read in total (54838ms).
[23:55:16.463] <TB1> INFO: 2052256 events read in total (81948ms).
[23:55:43.691] <TB1> INFO: 2732280 events read in total (109176ms).
[23:56:10.847] <TB1> INFO: 3410768 events read in total (136332ms).
[23:56:38.065] <TB1> INFO: 4087496 events read in total (163550ms).
[23:57:05.653] <TB1> INFO: 4765632 events read in total (191138ms).
[23:57:16.230] <TB1> INFO: 5025280 events read in total (201715ms).
[23:57:16.300] <TB1> INFO: Test took 202651ms.
[23:57:37.666] <TB1> INFO: ROC 0 VthrComp = 77
[23:57:37.666] <TB1> INFO: ROC 1 VthrComp = 85
[23:57:37.666] <TB1> INFO: ROC 2 VthrComp = 85
[23:57:37.666] <TB1> INFO: ROC 3 VthrComp = 81
[23:57:37.666] <TB1> INFO: ROC 4 VthrComp = 76
[23:57:37.666] <TB1> INFO: ROC 5 VthrComp = 80
[23:57:37.666] <TB1> INFO: ROC 6 VthrComp = 77
[23:57:37.666] <TB1> INFO: ROC 7 VthrComp = 70
[23:57:37.667] <TB1> INFO: ROC 8 VthrComp = 73
[23:57:37.667] <TB1> INFO: ROC 9 VthrComp = 86
[23:57:37.667] <TB1> INFO: ROC 10 VthrComp = 79
[23:57:37.667] <TB1> INFO: ROC 11 VthrComp = 83
[23:57:37.667] <TB1> INFO: ROC 12 VthrComp = 82
[23:57:37.667] <TB1> INFO: ROC 13 VthrComp = 73
[23:57:37.667] <TB1> INFO: ROC 14 VthrComp = 77
[23:57:37.668] <TB1> INFO: ROC 15 VthrComp = 78
[23:57:37.948] <TB1> INFO: Expecting 41600 events.
[23:57:41.404] <TB1> INFO: 41600 events read in total (2864ms).
[23:57:41.405] <TB1> INFO: Test took 3736ms.
[23:57:41.417] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[23:57:41.417] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[23:57:41.427] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[23:57:41.427] <TB1> INFO: run 1 of 1
[23:57:41.706] <TB1> INFO: Expecting 5025280 events.
[23:58:09.709] <TB1> INFO: 686128 events read in total (27411ms).
[23:58:37.161] <TB1> INFO: 1368992 events read in total (54864ms).
[23:59:04.223] <TB1> INFO: 2050336 events read in total (81925ms).
[23:59:31.243] <TB1> INFO: 2728368 events read in total (108945ms).
[23:59:58.265] <TB1> INFO: 3402296 events read in total (135967ms).
[00:00:25.143] <TB1> INFO: 4075664 events read in total (162845ms).
[00:00:52.207] <TB1> INFO: 4750264 events read in total (189909ms).
[00:01:03.798] <TB1> INFO: 5025280 events read in total (201500ms).
[00:01:03.845] <TB1> INFO: Test took 202417ms.
[00:01:29.550] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 111.953 for pixel 0/20 mean/min/max = 95.2544/78.39/112.119
[00:01:29.550] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 106.644 for pixel 16/2 mean/min/max = 90.7593/74.6749/106.844
[00:01:29.551] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 107.198 for pixel 17/3 mean/min/max = 90.9478/74.6089/107.287
[00:01:29.551] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 107.484 for pixel 4/1 mean/min/max = 91.218/74.8401/107.596
[00:01:29.551] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 114.576 for pixel 0/17 mean/min/max = 96.6134/78.5061/114.721
[00:01:29.552] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 109.055 for pixel 47/79 mean/min/max = 92.2522/75.3001/109.204
[00:01:29.552] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 110.98 for pixel 51/0 mean/min/max = 94.6212/78.2594/110.983
[00:01:29.552] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 109.764 for pixel 0/8 mean/min/max = 92.2294/74.5484/109.91
[00:01:29.553] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 111.255 for pixel 0/72 mean/min/max = 94.3427/77.416/111.269
[00:01:29.553] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 109.304 for pixel 0/49 mean/min/max = 91.8859/74.3501/109.422
[00:01:29.553] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 109.949 for pixel 2/15 mean/min/max = 93.6378/77.292/109.984
[00:01:29.554] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 107.334 for pixel 50/79 mean/min/max = 90.8306/74.2864/107.375
[00:01:29.554] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 105.761 for pixel 17/7 mean/min/max = 90.3798/74.9756/105.784
[00:01:29.554] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 111.661 for pixel 8/1 mean/min/max = 93.9627/76.2104/111.715
[00:01:29.555] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 111.941 for pixel 0/2 mean/min/max = 94.8807/77.7661/111.995
[00:01:29.555] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 112.025 for pixel 3/7 mean/min/max = 95.1977/78.1465/112.249
[00:01:29.555] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[00:01:29.644] <TB1> INFO: Expecting 411648 events.
[00:01:38.889] <TB1> INFO: 411648 events read in total (8654ms).
[00:01:38.896] <TB1> INFO: Expecting 411648 events.
[00:01:47.940] <TB1> INFO: 411648 events read in total (8641ms).
[00:01:47.950] <TB1> INFO: Expecting 411648 events.
[00:01:57.017] <TB1> INFO: 411648 events read in total (8664ms).
[00:01:57.029] <TB1> INFO: Expecting 411648 events.
[00:02:06.083] <TB1> INFO: 411648 events read in total (8651ms).
[00:02:06.101] <TB1> INFO: Expecting 411648 events.
[00:02:15.215] <TB1> INFO: 411648 events read in total (8711ms).
[00:02:15.232] <TB1> INFO: Expecting 411648 events.
[00:02:24.347] <TB1> INFO: 411648 events read in total (8712ms).
[00:02:24.373] <TB1> INFO: Expecting 411648 events.
[00:02:33.384] <TB1> INFO: 411648 events read in total (8608ms).
[00:02:33.406] <TB1> INFO: Expecting 411648 events.
[00:02:42.555] <TB1> INFO: 411648 events read in total (8746ms).
[00:02:42.580] <TB1> INFO: Expecting 411648 events.
[00:02:51.612] <TB1> INFO: 411648 events read in total (8629ms).
[00:02:51.639] <TB1> INFO: Expecting 411648 events.
[00:03:00.717] <TB1> INFO: 411648 events read in total (8675ms).
[00:03:00.749] <TB1> INFO: Expecting 411648 events.
[00:03:09.886] <TB1> INFO: 411648 events read in total (8734ms).
[00:03:09.920] <TB1> INFO: Expecting 411648 events.
[00:03:18.996] <TB1> INFO: 411648 events read in total (8673ms).
[00:03:19.037] <TB1> INFO: Expecting 411648 events.
[00:03:28.119] <TB1> INFO: 411648 events read in total (8679ms).
[00:03:28.158] <TB1> INFO: Expecting 411648 events.
[00:03:37.195] <TB1> INFO: 411648 events read in total (8634ms).
[00:03:37.251] <TB1> INFO: Expecting 411648 events.
[00:03:46.534] <TB1> INFO: 411648 events read in total (8880ms).
[00:03:46.594] <TB1> INFO: Expecting 411648 events.
[00:03:55.769] <TB1> INFO: 411648 events read in total (8772ms).
[00:03:55.817] <TB1> INFO: Test took 146262ms.
[00:03:57.525] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[00:03:57.537] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[00:03:57.537] <TB1> INFO: run 1 of 1
[00:03:57.830] <TB1> INFO: Expecting 5025280 events.
[00:04:25.106] <TB1> INFO: 665496 events read in total (26684ms).
[00:04:51.830] <TB1> INFO: 1329248 events read in total (53408ms).
[00:05:18.758] <TB1> INFO: 1991944 events read in total (80336ms).
[00:05:45.311] <TB1> INFO: 2652464 events read in total (106889ms).
[00:06:11.634] <TB1> INFO: 3309144 events read in total (133212ms).
[00:06:38.487] <TB1> INFO: 3964896 events read in total (160065ms).
[00:07:05.228] <TB1> INFO: 4621464 events read in total (186806ms).
[00:07:21.724] <TB1> INFO: 5025280 events read in total (203302ms).
[00:07:21.772] <TB1> INFO: Test took 204234ms.
[00:07:46.213] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 49.212191 .. 102.496557
[00:07:46.468] <TB1> INFO: Expecting 208000 events.
[00:07:56.099] <TB1> INFO: 208000 events read in total (9039ms).
[00:07:56.099] <TB1> INFO: Test took 9885ms.
[00:07:56.178] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 39 .. 112 (-1/-1) hits flags = 528 (plus default)
[00:07:56.190] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[00:07:56.190] <TB1> INFO: run 1 of 1
[00:07:56.468] <TB1> INFO: Expecting 2462720 events.
[00:08:25.018] <TB1> INFO: 694408 events read in total (27959ms).
[00:08:52.651] <TB1> INFO: 1384536 events read in total (55592ms).
[00:09:20.539] <TB1> INFO: 2066400 events read in total (83480ms).
[00:09:36.771] <TB1> INFO: 2462720 events read in total (99712ms).
[00:09:36.807] <TB1> INFO: Test took 100617ms.
[00:09:54.262] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 60.152500 .. 90.618028
[00:09:54.496] <TB1> INFO: Expecting 208000 events.
[00:10:04.807] <TB1> INFO: 208000 events read in total (9719ms).
[00:10:04.808] <TB1> INFO: Test took 10545ms.
[00:10:04.892] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 50 .. 100 (-1/-1) hits flags = 528 (plus default)
[00:10:04.904] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[00:10:04.904] <TB1> INFO: run 1 of 1
[00:10:05.184] <TB1> INFO: Expecting 1697280 events.
[00:10:34.133] <TB1> INFO: 703416 events read in total (28358ms).
[00:11:02.212] <TB1> INFO: 1406128 events read in total (56437ms).
[00:11:14.026] <TB1> INFO: 1697280 events read in total (68251ms).
[00:11:14.064] <TB1> INFO: Test took 69160ms.
[00:11:29.650] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 64.058509 .. 82.933213
[00:11:29.881] <TB1> INFO: Expecting 208000 events.
[00:11:39.625] <TB1> INFO: 208000 events read in total (9152ms).
[00:11:39.626] <TB1> INFO: Test took 9975ms.
[00:11:39.674] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 54 .. 92 (-1/-1) hits flags = 528 (plus default)
[00:11:39.686] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[00:11:39.686] <TB1> INFO: run 1 of 1
[00:11:39.964] <TB1> INFO: Expecting 1297920 events.
[00:12:09.828] <TB1> INFO: 735264 events read in total (29273ms).
[00:12:31.872] <TB1> INFO: 1297920 events read in total (51317ms).
[00:12:31.893] <TB1> INFO: Test took 52208ms.
[00:12:46.934] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 65.098977 .. 82.933213
[00:12:47.255] <TB1> INFO: Expecting 208000 events.
[00:12:57.058] <TB1> INFO: 208000 events read in total (9212ms).
[00:12:57.059] <TB1> INFO: Test took 10122ms.
[00:12:57.124] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 55 .. 92 (-1/-1) hits flags = 528 (plus default)
[00:12:57.136] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[00:12:57.136] <TB1> INFO: run 1 of 1
[00:12:57.414] <TB1> INFO: Expecting 1264640 events.
[00:13:27.008] <TB1> INFO: 733960 events read in total (29002ms).
[00:13:47.801] <TB1> INFO: 1264640 events read in total (49796ms).
[00:13:47.830] <TB1> INFO: Test took 50694ms.
[00:14:03.615] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[00:14:03.615] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[00:14:03.625] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[00:14:03.625] <TB1> INFO: run 1 of 1
[00:14:03.858] <TB1> INFO: Expecting 1364480 events.
[00:14:32.319] <TB1> INFO: 668360 events read in total (27869ms).
[00:15:00.095] <TB1> INFO: 1336256 events read in total (55645ms).
[00:15:01.625] <TB1> INFO: 1364480 events read in total (57175ms).
[00:15:01.651] <TB1> INFO: Test took 58026ms.
[00:15:18.086] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C0.dat
[00:15:18.086] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C1.dat
[00:15:18.086] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C2.dat
[00:15:18.086] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C3.dat
[00:15:18.086] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C4.dat
[00:15:18.087] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C5.dat
[00:15:18.087] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C6.dat
[00:15:18.087] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C7.dat
[00:15:18.087] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C8.dat
[00:15:18.087] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C9.dat
[00:15:18.087] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C10.dat
[00:15:18.087] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C11.dat
[00:15:18.087] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C12.dat
[00:15:18.087] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C13.dat
[00:15:18.088] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C14.dat
[00:15:18.088] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//dacParameters80_C15.dat
[00:15:18.088] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C0.dat
[00:15:18.097] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C1.dat
[00:15:18.105] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C2.dat
[00:15:18.114] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C3.dat
[00:15:18.123] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C4.dat
[00:15:18.132] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C5.dat
[00:15:18.140] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C6.dat
[00:15:18.149] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C7.dat
[00:15:18.158] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C8.dat
[00:15:18.167] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C9.dat
[00:15:18.176] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C10.dat
[00:15:18.185] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C11.dat
[00:15:18.193] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C12.dat
[00:15:18.202] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C13.dat
[00:15:18.211] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C14.dat
[00:15:18.219] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1138_FullQualification_2016-11-07_19h53m_1478544796//003_FulltestTrim80_p17//trimParameters80_C15.dat
[00:15:18.227] <TB1> INFO: PixTestTrim80::trimTest() done
[00:15:18.227] <TB1> INFO: vtrim: 108 106 113 118 128 111 117 105 100 107 114 101 100 107 120 132
[00:15:18.227] <TB1> INFO: vthrcomp: 77 85 85 81 76 80 77 70 73 86 79 83 82 73 77 78
[00:15:18.227] <TB1> INFO: vcal mean: 79.99 79.96 79.99 79.99 79.97 80.03 80.00 80.01 80.00 79.96 79.98 79.99 79.99 79.96 79.96 80.02
[00:15:18.227] <TB1> INFO: vcal RMS: 0.75 0.75 0.79 0.72 0.79 0.78 0.77 0.72 0.78 0.80 0.78 0.76 0.75 0.73 0.77 0.82
[00:15:18.227] <TB1> INFO: bits mean: 9.16 10.52 10.71 10.64 9.39 10.05 9.59 10.00 9.60 10.24 9.96 10.50 10.50 9.87 9.71 9.88
[00:15:18.227] <TB1> INFO: bits RMS: 2.22 2.21 2.11 2.12 2.10 2.32 2.10 2.46 2.22 2.37 2.09 2.26 2.25 2.18 2.08 2.01
[00:15:18.233] <TB1> INFO: ----------------------------------------------------------------------
[00:15:18.233] <TB1> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[00:15:18.233] <TB1> INFO: ----------------------------------------------------------------------
[00:15:18.236] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[00:15:18.244] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[00:15:18.244] <TB1> INFO: run 1 of 1
[00:15:18.477] <TB1> INFO: Expecting 4160000 events.
[00:15:51.254] <TB1> INFO: 786490 events read in total (32185ms).
[00:16:23.223] <TB1> INFO: 1560825 events read in total (64154ms).
[00:16:54.978] <TB1> INFO: 2327545 events read in total (95910ms).
[00:17:26.682] <TB1> INFO: 3089010 events read in total (127613ms).
[00:17:58.673] <TB1> INFO: 3849810 events read in total (159604ms).
[00:18:11.623] <TB1> INFO: 4160000 events read in total (172554ms).
[00:18:11.666] <TB1> INFO: Test took 173421ms.
[00:18:37.037] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 209 (-1/-1) hits flags = 528 (plus default)
[00:18:37.050] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[00:18:37.050] <TB1> INFO: run 1 of 1
[00:18:37.312] <TB1> INFO: Expecting 4368000 events.
[00:19:08.859] <TB1> INFO: 743920 events read in total (30956ms).
[00:19:39.706] <TB1> INFO: 1478935 events read in total (61803ms).
[00:20:10.383] <TB1> INFO: 2209575 events read in total (92480ms).
[00:20:41.266] <TB1> INFO: 2935095 events read in total (123363ms).
[00:21:12.550] <TB1> INFO: 3658720 events read in total (154647ms).
[00:21:42.738] <TB1> INFO: 4368000 events read in total (184835ms).
[00:21:42.790] <TB1> INFO: Test took 185740ms.
[00:22:12.568] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 201 (-1/-1) hits flags = 528 (plus default)
[00:22:12.578] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[00:22:12.578] <TB1> INFO: run 1 of 1
[00:22:12.844] <TB1> INFO: Expecting 4201600 events.
[00:22:45.317] <TB1> INFO: 756270 events read in total (31881ms).
[00:23:16.689] <TB1> INFO: 1502695 events read in total (63253ms).
[00:23:47.946] <TB1> INFO: 2243935 events read in total (94510ms).
[00:24:19.031] <TB1> INFO: 2980505 events read in total (125595ms).
[00:24:50.167] <TB1> INFO: 3714990 events read in total (156731ms).
[00:25:10.618] <TB1> INFO: 4201600 events read in total (177182ms).
[00:25:10.666] <TB1> INFO: Test took 178088ms.
[00:25:37.806] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 201 (-1/-1) hits flags = 528 (plus default)
[00:25:37.818] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[00:25:37.818] <TB1> INFO: run 1 of 1
[00:25:38.075] <TB1> INFO: Expecting 4201600 events.
[00:26:09.970] <TB1> INFO: 756775 events read in total (31303ms).
[00:26:41.301] <TB1> INFO: 1503485 events read in total (62634ms).
[00:27:12.658] <TB1> INFO: 2244975 events read in total (93991ms).
[00:27:43.892] <TB1> INFO: 2981670 events read in total (125225ms).
[00:28:15.405] <TB1> INFO: 3716485 events read in total (156738ms).
[00:28:35.843] <TB1> INFO: 4201600 events read in total (177176ms).
[00:28:35.902] <TB1> INFO: Test took 178084ms.
[00:29:02.456] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 201 (-1/-1) hits flags = 528 (plus default)
[00:29:02.467] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[00:29:02.467] <TB1> INFO: run 1 of 1
[00:29:02.741] <TB1> INFO: Expecting 4201600 events.
[00:29:35.145] <TB1> INFO: 757260 events read in total (31812ms).
[00:30:06.518] <TB1> INFO: 1504070 events read in total (63185ms).
[00:30:37.546] <TB1> INFO: 2245915 events read in total (94214ms).
[00:31:08.751] <TB1> INFO: 2982795 events read in total (125418ms).
[00:31:39.696] <TB1> INFO: 3717700 events read in total (156363ms).
[00:32:01.422] <TB1> INFO: 4201600 events read in total (178089ms).
[00:32:01.469] <TB1> INFO: Test took 179002ms.
[00:32:33.916] <TB1> INFO: PixTestTrim80::trimBitTest() done
[00:32:33.917] <TB1> INFO: PixTestTrim80::doTest() done, duration: 2320 seconds
[00:32:34.843] <TB1> INFO: enter test to run
[00:32:34.843] <TB1> INFO: test: exit no parameter change
[00:32:34.963] <TB1> QUIET: Connection to board 153 closed.
[00:32:34.963] <TB1> INFO: pXar: this is the end, my friend