[11:12:43.321] <TB1> INFO: *** Welcome to pxar ***
[11:12:43.321] <TB1> INFO: *** Today: 2016/11/15
[11:12:43.326] <TB1> INFO: *** Version: c8ba-dirty
[11:12:43.327] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C15.dat
[11:12:43.327] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//tbmParameters_C1b.dat
[11:12:43.327] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//defaultMaskFile.dat
[11:12:43.327] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters_C15.dat
[11:12:43.381] <TB1> INFO: clk: 4
[11:12:43.381] <TB1> INFO: ctr: 4
[11:12:43.381] <TB1> INFO: sda: 19
[11:12:43.382] <TB1> INFO: tin: 9
[11:12:43.382] <TB1> INFO: level: 15
[11:12:43.382] <TB1> INFO: triggerdelay: 0
[11:12:43.382] <TB1> QUIET: Instanciating API for pxar v2.1.0+875~gda35c4c
[11:12:43.382] <TB1> INFO: Log level: INFO
[11:12:43.390] <TB1> INFO: Found DTB DTB_WXBYFL
[11:12:43.400] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[11:12:43.402] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
------------------------------------------------------
[11:12:43.403] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[11:12:44.888] <TB1> INFO: DUT info:
[11:12:44.888] <TB1> INFO: The DUT currently contains the following objects:
[11:12:44.888] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[11:12:44.888] <TB1> INFO: TBM Core alpha (0): 7 registers set
[11:12:44.888] <TB1> INFO: TBM Core beta (1): 7 registers set
[11:12:44.888] <TB1> INFO: TBM Core alpha (2): 7 registers set
[11:12:44.888] <TB1> INFO: TBM Core beta (3): 7 registers set
[11:12:44.888] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:12:44.888] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.888] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.888] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.888] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.888] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.888] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.888] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.888] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.888] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.888] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.888] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.888] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.889] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.889] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.889] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:44.889] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:12:45.289] <TB1> INFO: enter 'restricted' command line mode
[11:12:45.289] <TB1> INFO: enter test to run
[11:12:45.289] <TB1> INFO: test: pretest no parameter change
[11:12:45.289] <TB1> INFO: running: pretest
[11:12:45.843] <TB1> INFO: ######################################################################
[11:12:45.843] <TB1> INFO: PixTestPretest::doTest()
[11:12:45.843] <TB1> INFO: ######################################################################
[11:12:45.844] <TB1> INFO: ----------------------------------------------------------------------
[11:12:45.844] <TB1> INFO: PixTestPretest::programROC()
[11:12:45.844] <TB1> INFO: ----------------------------------------------------------------------
[11:13:03.857] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:13:03.857] <TB1> INFO: IA differences per ROC: 18.5 18.5 18.5 17.7 16.9 20.9 17.7 20.9 16.9 16.9 18.5 17.7 21.7 18.5 18.5 20.9
[11:13:03.894] <TB1> INFO: ----------------------------------------------------------------------
[11:13:03.894] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:13:03.894] <TB1> INFO: ----------------------------------------------------------------------
[11:13:25.124] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 389.1 mA = 24.3188 mA/ROC
[11:13:25.124] <TB1> INFO: i(loss) [mA/ROC]: 20.9 20.9 20.1 19.3 19.3 19.3 20.9 20.1 20.1 20.1 19.3 20.1 19.3 20.1 20.1 19.3
[11:13:25.150] <TB1> INFO: ----------------------------------------------------------------------
[11:13:25.150] <TB1> INFO: PixTestPretest::findTiming()
[11:13:25.150] <TB1> INFO: ----------------------------------------------------------------------
[11:13:25.150] <TB1> INFO: PixTestCmd::init()

[11:13:55.185] <TB1> INFO: TBM phases: 160MHz: 4, 400MHz: 6, TBM delays: ROC(0/1):3, header/trailer: 1, token: 0
[11:13:55.185] <TB1> INFO: (success/tries = 100/100), width = 5
[11:13:56.691] <TB1> INFO: ----------------------------------------------------------------------
[11:13:56.691] <TB1> INFO: PixTestPretest::findWorkingPixel()
[11:13:56.691] <TB1> INFO: ----------------------------------------------------------------------
[11:13:56.782] <TB1> INFO: Expecting 231680 events.
[11:14:06.678] <TB1> INFO: 231680 events read in total (9304ms).
[11:14:06.684] <TB1> INFO: Test took 9991ms.
[11:14:06.924] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:14:06.953] <TB1> INFO: ----------------------------------------------------------------------
[11:14:06.953] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[11:14:06.953] <TB1> INFO: ----------------------------------------------------------------------
[11:14:07.046] <TB1> INFO: Expecting 231680 events.
[11:14:16.882] <TB1> INFO: 231680 events read in total (9244ms).
[11:14:16.892] <TB1> INFO: Test took 9935ms.
[11:14:17.148] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[11:14:17.148] <TB1> INFO: CalDel: 114 119 99 86 113 110 101 103 104 95 115 128 96 101 113 110
[11:14:17.148] <TB1> INFO: VthrComp: 52 51 51 51 57 51 51 51 51 51 51 52 51 54 51 54
[11:14:17.150] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C0.dat
[11:14:17.150] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C1.dat
[11:14:17.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C2.dat
[11:14:17.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C3.dat
[11:14:17.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C4.dat
[11:14:17.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C5.dat
[11:14:17.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C6.dat
[11:14:17.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C7.dat
[11:14:17.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C8.dat
[11:14:17.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C9.dat
[11:14:17.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C10.dat
[11:14:17.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C11.dat
[11:14:17.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C12.dat
[11:14:17.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C13.dat
[11:14:17.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C14.dat
[11:14:17.152] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters_C15.dat
[11:14:17.152] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//tbmParameters_C0a.dat
[11:14:17.152] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//tbmParameters_C0b.dat
[11:14:17.152] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//tbmParameters_C1a.dat
[11:14:17.152] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//tbmParameters_C1b.dat
[11:14:17.152] <TB1> INFO: PixTestPretest::doTest() done, duration: 91 seconds
[11:14:17.247] <TB1> INFO: enter test to run
[11:14:17.247] <TB1> INFO: test: FullTest no parameter change
[11:14:17.247] <TB1> INFO: running: fulltest
[11:14:17.247] <TB1> INFO: ######################################################################
[11:14:17.247] <TB1> INFO: PixTestFullTest::doTest()
[11:14:17.247] <TB1> INFO: ######################################################################
[11:14:17.248] <TB1> INFO: ######################################################################
[11:14:17.248] <TB1> INFO: PixTestAlive::doTest()
[11:14:17.248] <TB1> INFO: ######################################################################
[11:14:17.250] <TB1> INFO: ----------------------------------------------------------------------
[11:14:17.250] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:14:17.250] <TB1> INFO: ----------------------------------------------------------------------
[11:14:17.483] <TB1> INFO: Expecting 41600 events.
[11:14:21.068] <TB1> INFO: 41600 events read in total (2993ms).
[11:14:21.069] <TB1> INFO: Test took 3818ms.
[11:14:21.295] <TB1> INFO: PixTestAlive::aliveTest() done
[11:14:21.295] <TB1> INFO: number of dead pixels (per ROC): 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
[11:14:21.296] <TB1> INFO: ----------------------------------------------------------------------
[11:14:21.296] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:14:21.296] <TB1> INFO: ----------------------------------------------------------------------
[11:14:21.529] <TB1> INFO: Expecting 41600 events.
[11:14:24.658] <TB1> INFO: 41600 events read in total (2538ms).
[11:14:24.658] <TB1> INFO: Test took 3361ms.
[11:14:24.658] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:14:24.897] <TB1> INFO: PixTestAlive::maskTest() done
[11:14:24.897] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:14:24.898] <TB1> INFO: ----------------------------------------------------------------------
[11:14:24.898] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:14:24.898] <TB1> INFO: ----------------------------------------------------------------------
[11:14:25.210] <TB1> INFO: Expecting 41600 events.
[11:14:28.678] <TB1> INFO: 41600 events read in total (2877ms).
[11:14:28.678] <TB1> INFO: Test took 3778ms.
[11:14:28.905] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[11:14:28.905] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:14:28.905] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:14:28.905] <TB1> INFO: Decoding statistics:
[11:14:28.905] <TB1> INFO: General information:
[11:14:28.905] <TB1> INFO: 16bit words read: 0
[11:14:28.905] <TB1> INFO: valid events total: 0
[11:14:28.905] <TB1> INFO: empty events: 0
[11:14:28.905] <TB1> INFO: valid events with pixels: 0
[11:14:28.905] <TB1> INFO: valid pixel hits: 0
[11:14:28.905] <TB1> INFO: Event errors: 0
[11:14:28.905] <TB1> INFO: start marker: 0
[11:14:28.905] <TB1> INFO: stop marker: 0
[11:14:28.905] <TB1> INFO: overflow: 0
[11:14:28.905] <TB1> INFO: invalid 5bit words: 0
[11:14:28.905] <TB1> INFO: invalid XOR eye diagram: 0
[11:14:28.905] <TB1> INFO: frame (failed synchr.): 0
[11:14:28.905] <TB1> INFO: idle data (no TBM trl): 0
[11:14:28.905] <TB1> INFO: no data (only TBM hdr): 0
[11:14:28.905] <TB1> INFO: TBM errors: 0
[11:14:28.905] <TB1> INFO: flawed TBM headers: 0
[11:14:28.905] <TB1> INFO: flawed TBM trailers: 0
[11:14:28.905] <TB1> INFO: event ID mismatches: 0
[11:14:28.905] <TB1> INFO: ROC errors: 0
[11:14:28.905] <TB1> INFO: missing ROC header(s): 0
[11:14:28.905] <TB1> INFO: misplaced readback start: 0
[11:14:28.905] <TB1> INFO: Pixel decoding errors: 0
[11:14:28.905] <TB1> INFO: pixel data incomplete: 0
[11:14:28.905] <TB1> INFO: pixel address: 0
[11:14:28.905] <TB1> INFO: pulse height fill bit: 0
[11:14:28.905] <TB1> INFO: buffer corruption: 0
[11:14:28.912] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C15.dat
[11:14:28.912] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr_C15.dat

[11:14:28.912] <TB1> INFO: ######################################################################
[11:14:28.912] <TB1> INFO: PixTestReadback::doTest()
[11:14:28.912] <TB1> INFO: ######################################################################
[11:14:28.912] <TB1> INFO: ----------------------------------------------------------------------
[11:14:28.912] <TB1> INFO: PixTestReadback::CalibrateVd()
[11:14:28.912] <TB1> INFO: ----------------------------------------------------------------------
[11:14:38.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C0.dat
[11:14:38.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C1.dat
[11:14:38.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C2.dat
[11:14:38.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C3.dat
[11:14:38.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C4.dat
[11:14:38.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C5.dat
[11:14:38.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C6.dat
[11:14:38.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C7.dat
[11:14:38.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C8.dat
[11:14:38.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C9.dat
[11:14:38.877] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C10.dat
[11:14:38.877] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C11.dat
[11:14:38.877] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C12.dat
[11:14:38.877] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C13.dat
[11:14:38.877] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C14.dat
[11:14:38.877] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C15.dat
[11:14:38.903] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:14:38.904] <TB1> INFO: ----------------------------------------------------------------------
[11:14:38.904] <TB1> INFO: PixTestReadback::CalibrateVa()
[11:14:38.904] <TB1> INFO: ----------------------------------------------------------------------
[11:14:48.792] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C0.dat
[11:14:48.792] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C1.dat
[11:14:48.792] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C2.dat
[11:14:48.792] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C3.dat
[11:14:48.792] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C4.dat
[11:14:48.792] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C5.dat
[11:14:48.792] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C6.dat
[11:14:48.793] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C7.dat
[11:14:48.793] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C8.dat
[11:14:48.793] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C9.dat
[11:14:48.793] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C10.dat
[11:14:48.793] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C11.dat
[11:14:48.793] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C12.dat
[11:14:48.793] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C13.dat
[11:14:48.793] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C14.dat
[11:14:48.793] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C15.dat
[11:14:48.822] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:14:48.822] <TB1> INFO: ----------------------------------------------------------------------
[11:14:48.822] <TB1> INFO: PixTestReadback::readbackVbg()
[11:14:48.822] <TB1> INFO: ----------------------------------------------------------------------
[11:14:56.462] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:14:56.463] <TB1> INFO: ----------------------------------------------------------------------
[11:14:56.463] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[11:14:56.463] <TB1> INFO: ----------------------------------------------------------------------
[11:14:56.463] <TB1> INFO: Vbg will be calibrated using Vd calibration
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 161.4calibrated Vbg = 1.1479 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 155calibrated Vbg = 1.14516 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 158.1calibrated Vbg = 1.13519 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 154calibrated Vbg = 1.13949 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 160.2calibrated Vbg = 1.14314 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 151calibrated Vbg = 1.1367 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 159.8calibrated Vbg = 1.14834 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 153.3calibrated Vbg = 1.15085 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 159calibrated Vbg = 1.14241 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 153.3calibrated Vbg = 1.1343 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 159calibrated Vbg = 1.1362 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 159.8calibrated Vbg = 1.12888 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 153.3calibrated Vbg = 1.14144 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 156.2calibrated Vbg = 1.14419 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 136.4calibrated Vbg = 1.13968 :::*/*/*/*/
[11:14:56.463] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 158.1calibrated Vbg = 1.14241 :::*/*/*/*/
[11:14:56.464] <TB1> INFO: ----------------------------------------------------------------------
[11:14:56.464] <TB1> INFO: PixTestReadback::CalibrateIa()
[11:14:56.464] <TB1> INFO: ----------------------------------------------------------------------
[11:17:36.704] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C0.dat
[11:17:36.704] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C1.dat
[11:17:36.705] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C2.dat
[11:17:36.705] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C3.dat
[11:17:36.705] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C4.dat
[11:17:36.705] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C5.dat
[11:17:36.705] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C6.dat
[11:17:36.705] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C7.dat
[11:17:36.705] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C8.dat
[11:17:36.705] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C9.dat
[11:17:36.705] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C10.dat
[11:17:36.705] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C11.dat
[11:17:36.705] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C12.dat
[11:17:36.705] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C13.dat
[11:17:36.706] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C14.dat
[11:17:36.706] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//readbackCal_C15.dat
[11:17:36.733] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:17:36.734] <TB1> INFO: PixTestReadback::doTest() done
[11:17:36.734] <TB1> INFO: Decoding statistics:
[11:17:36.734] <TB1> INFO: General information:
[11:17:36.734] <TB1> INFO: 16bit words read: 1536
[11:17:36.734] <TB1> INFO: valid events total: 256
[11:17:36.734] <TB1> INFO: empty events: 256
[11:17:36.734] <TB1> INFO: valid events with pixels: 0
[11:17:36.734] <TB1> INFO: valid pixel hits: 0
[11:17:36.734] <TB1> INFO: Event errors: 0
[11:17:36.734] <TB1> INFO: start marker: 0
[11:17:36.734] <TB1> INFO: stop marker: 0
[11:17:36.734] <TB1> INFO: overflow: 0
[11:17:36.734] <TB1> INFO: invalid 5bit words: 0
[11:17:36.734] <TB1> INFO: invalid XOR eye diagram: 0
[11:17:36.734] <TB1> INFO: frame (failed synchr.): 0
[11:17:36.734] <TB1> INFO: idle data (no TBM trl): 0
[11:17:36.734] <TB1> INFO: no data (only TBM hdr): 0
[11:17:36.734] <TB1> INFO: TBM errors: 0
[11:17:36.734] <TB1> INFO: flawed TBM headers: 0
[11:17:36.734] <TB1> INFO: flawed TBM trailers: 0
[11:17:36.734] <TB1> INFO: event ID mismatches: 0
[11:17:36.734] <TB1> INFO: ROC errors: 0
[11:17:36.734] <TB1> INFO: missing ROC header(s): 0
[11:17:36.734] <TB1> INFO: misplaced readback start: 0
[11:17:36.734] <TB1> INFO: Pixel decoding errors: 0
[11:17:36.734] <TB1> INFO: pixel data incomplete: 0
[11:17:36.734] <TB1> INFO: pixel address: 0
[11:17:36.734] <TB1> INFO: pulse height fill bit: 0
[11:17:36.734] <TB1> INFO: buffer corruption: 0
[11:17:36.767] <TB1> INFO: ######################################################################
[11:17:36.767] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:17:36.767] <TB1> INFO: ######################################################################
[11:17:36.769] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:17:36.785] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:17:36.785] <TB1> INFO: run 1 of 1
[11:17:37.089] <TB1> INFO: Expecting 3120000 events.
[11:18:08.892] <TB1> INFO: 655335 events read in total (31210ms).











[11:18:39.766] <TB1> INFO: 1304870 events read in total (62084ms).











[11:19:10.258] <TB1> INFO: 1951845 events read in total (92576ms).











[11:19:40.616] <TB1> INFO: 2598315 events read in total (122934ms).











[11:20:05.566] <TB1> INFO: 3120000 events read in total (147884ms).
[11:20:05.620] <TB1> INFO: Test took 148836ms.
[11:20:35.136] <TB1> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 178 seconds
[11:20:35.136] <TB1> INFO: number of dead bumps (per ROC): 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
[11:20:35.136] <TB1> INFO: separation cut (per ROC): 107 104 104 108 117 105 107 96 107 91 100 99 109 108 98 106
[11:20:35.136] <TB1> INFO: Decoding statistics:
[11:20:35.136] <TB1> INFO: General information:
[11:20:35.136] <TB1> INFO: 16bit words read: 0
[11:20:35.136] <TB1> INFO: valid events total: 0
[11:20:35.136] <TB1> INFO: empty events: 0
[11:20:35.136] <TB1> INFO: valid events with pixels: 0
[11:20:35.136] <TB1> INFO: valid pixel hits: 0
[11:20:35.136] <TB1> INFO: Event errors: 0
[11:20:35.136] <TB1> INFO: start marker: 0
[11:20:35.136] <TB1> INFO: stop marker: 0
[11:20:35.136] <TB1> INFO: overflow: 0
[11:20:35.136] <TB1> INFO: invalid 5bit words: 0
[11:20:35.136] <TB1> INFO: invalid XOR eye diagram: 0
[11:20:35.136] <TB1> INFO: frame (failed synchr.): 0
[11:20:35.136] <TB1> INFO: idle data (no TBM trl): 0
[11:20:35.136] <TB1> INFO: no data (only TBM hdr): 0
[11:20:35.136] <TB1> INFO: TBM errors: 0
[11:20:35.136] <TB1> INFO: flawed TBM headers: 0
[11:20:35.136] <TB1> INFO: flawed TBM trailers: 0
[11:20:35.136] <TB1> INFO: event ID mismatches: 0
[11:20:35.136] <TB1> INFO: ROC errors: 0
[11:20:35.136] <TB1> INFO: missing ROC header(s): 0
[11:20:35.136] <TB1> INFO: misplaced readback start: 0
[11:20:35.136] <TB1> INFO: Pixel decoding errors: 0
[11:20:35.136] <TB1> INFO: pixel data incomplete: 0
[11:20:35.136] <TB1> INFO: pixel address: 0
[11:20:35.136] <TB1> INFO: pulse height fill bit: 0
[11:20:35.136] <TB1> INFO: buffer corruption: 0
[11:20:35.170] <TB1> INFO: ######################################################################
[11:20:35.171] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:20:35.171] <TB1> INFO: ######################################################################
[11:20:35.171] <TB1> INFO: ----------------------------------------------------------------------
[11:20:35.171] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:20:35.171] <TB1> INFO: ----------------------------------------------------------------------
[11:20:35.171] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[11:20:35.180] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[11:20:35.180] <TB1> INFO: run 1 of 1
[11:20:35.413] <TB1> INFO: Expecting 36608000 events.
[11:21:00.335] <TB1> INFO: 681950 events read in total (24331ms).
[11:21:24.512] <TB1> INFO: 1353600 events read in total (48508ms).
[11:21:48.155] <TB1> INFO: 2020550 events read in total (72151ms).
[11:22:11.736] <TB1> INFO: 2689350 events read in total (95732ms).
[11:22:35.088] <TB1> INFO: 3355250 events read in total (119084ms).
[11:22:58.150] <TB1> INFO: 4020600 events read in total (142146ms).
[11:23:21.824] <TB1> INFO: 4687250 events read in total (165820ms).
[11:23:45.309] <TB1> INFO: 5353550 events read in total (189305ms).
[11:24:08.867] <TB1> INFO: 6018200 events read in total (212863ms).
[11:24:32.945] <TB1> INFO: 6685100 events read in total (236941ms).
[11:24:56.419] <TB1> INFO: 7353050 events read in total (260415ms).
[11:25:20.491] <TB1> INFO: 8021750 events read in total (284487ms).
[11:25:43.469] <TB1> INFO: 8691150 events read in total (307465ms).
[11:26:07.079] <TB1> INFO: 9359550 events read in total (331075ms).
[11:26:30.853] <TB1> INFO: 10028200 events read in total (354849ms).
[11:26:55.057] <TB1> INFO: 10693450 events read in total (379053ms).
[11:27:18.480] <TB1> INFO: 11360650 events read in total (402476ms).
[11:27:42.570] <TB1> INFO: 12025750 events read in total (426566ms).
[11:28:06.876] <TB1> INFO: 12692750 events read in total (450872ms).
[11:28:31.188] <TB1> INFO: 13357750 events read in total (475184ms).
[11:28:55.211] <TB1> INFO: 14024450 events read in total (499207ms).
[11:29:18.920] <TB1> INFO: 14687600 events read in total (522916ms).
[11:29:42.366] <TB1> INFO: 15352300 events read in total (546362ms).
[11:30:06.076] <TB1> INFO: 16015200 events read in total (570072ms).
[11:30:29.805] <TB1> INFO: 16681300 events read in total (593801ms).
[11:30:53.452] <TB1> INFO: 17343700 events read in total (617448ms).
[11:31:16.968] <TB1> INFO: 18008600 events read in total (640964ms).
[11:31:40.986] <TB1> INFO: 18670500 events read in total (664982ms).
[11:32:03.940] <TB1> INFO: 19332000 events read in total (687936ms).
[11:32:28.323] <TB1> INFO: 19991950 events read in total (712319ms).
[11:32:52.233] <TB1> INFO: 20650850 events read in total (736229ms).
[11:33:15.779] <TB1> INFO: 21311950 events read in total (759775ms).
[11:33:39.390] <TB1> INFO: 21971600 events read in total (783386ms).
[11:34:03.514] <TB1> INFO: 22631850 events read in total (807510ms).
[11:34:26.800] <TB1> INFO: 23291400 events read in total (830796ms).
[11:34:50.824] <TB1> INFO: 23953200 events read in total (854820ms).
[11:35:14.515] <TB1> INFO: 24614750 events read in total (878511ms).
[11:35:38.384] <TB1> INFO: 25277750 events read in total (902380ms).
[11:36:01.491] <TB1> INFO: 25937000 events read in total (925487ms).
[11:36:25.524] <TB1> INFO: 26597400 events read in total (949520ms).
[11:36:49.506] <TB1> INFO: 27256450 events read in total (973502ms).
[11:37:11.924] <TB1> INFO: 27913350 events read in total (995920ms).
[11:37:36.019] <TB1> INFO: 28572600 events read in total (1020015ms).
[11:37:59.781] <TB1> INFO: 29232900 events read in total (1043777ms).
[11:38:23.491] <TB1> INFO: 29893550 events read in total (1067487ms).
[11:38:47.535] <TB1> INFO: 30551850 events read in total (1091531ms).
[11:39:11.481] <TB1> INFO: 31211300 events read in total (1115477ms).
[11:39:35.184] <TB1> INFO: 31871050 events read in total (1139180ms).
[11:39:58.984] <TB1> INFO: 32531800 events read in total (1162980ms).
[11:40:22.871] <TB1> INFO: 33189350 events read in total (1186867ms).
[11:40:46.420] <TB1> INFO: 33850750 events read in total (1210416ms).
[11:41:10.465] <TB1> INFO: 34510600 events read in total (1234461ms).
[11:41:33.739] <TB1> INFO: 35171500 events read in total (1257735ms).
[11:41:57.494] <TB1> INFO: 35831950 events read in total (1281490ms).
[11:42:22.088] <TB1> INFO: 36508250 events read in total (1306084ms).
[11:42:25.954] <TB1> INFO: 36608000 events read in total (1309950ms).
[11:42:26.006] <TB1> INFO: Test took 1310826ms.
[11:42:26.350] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:27.867] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:29.393] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:30.843] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:32.330] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:33.786] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:35.265] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:36.742] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:38.210] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:39.666] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:41.124] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:42.576] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:44.025] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:45.489] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:46.963] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:48.403] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:42:49.902] <TB1> INFO: PixTestScurves::scurves() done
[11:42:49.902] <TB1> INFO: Vcal mean: 122.51 110.90 120.46 118.23 131.33 118.13 125.92 97.84 124.96 110.28 111.58 123.37 118.01 119.58 128.23 128.40
[11:42:49.902] <TB1> INFO: Vcal RMS: 7.90 4.97 6.25 5.91 6.81 5.54 5.77 5.33 6.13 4.94 5.54 6.08 5.69 5.73 6.56 6.63
[11:42:49.902] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1334 seconds
[11:42:49.902] <TB1> INFO: Decoding statistics:
[11:42:49.902] <TB1> INFO: General information:
[11:42:49.902] <TB1> INFO: 16bit words read: 0
[11:42:49.902] <TB1> INFO: valid events total: 0
[11:42:49.902] <TB1> INFO: empty events: 0
[11:42:49.902] <TB1> INFO: valid events with pixels: 0
[11:42:49.902] <TB1> INFO: valid pixel hits: 0
[11:42:49.902] <TB1> INFO: Event errors: 0
[11:42:49.902] <TB1> INFO: start marker: 0
[11:42:49.902] <TB1> INFO: stop marker: 0
[11:42:49.902] <TB1> INFO: overflow: 0
[11:42:49.902] <TB1> INFO: invalid 5bit words: 0
[11:42:49.902] <TB1> INFO: invalid XOR eye diagram: 0
[11:42:49.902] <TB1> INFO: frame (failed synchr.): 0
[11:42:49.902] <TB1> INFO: idle data (no TBM trl): 0
[11:42:49.902] <TB1> INFO: no data (only TBM hdr): 0
[11:42:49.902] <TB1> INFO: TBM errors: 0
[11:42:49.902] <TB1> INFO: flawed TBM headers: 0
[11:42:49.902] <TB1> INFO: flawed TBM trailers: 0
[11:42:49.902] <TB1> INFO: event ID mismatches: 0
[11:42:49.902] <TB1> INFO: ROC errors: 0
[11:42:49.902] <TB1> INFO: missing ROC header(s): 0
[11:42:49.902] <TB1> INFO: misplaced readback start: 0
[11:42:49.902] <TB1> INFO: Pixel decoding errors: 0
[11:42:49.902] <TB1> INFO: pixel data incomplete: 0
[11:42:49.902] <TB1> INFO: pixel address: 0
[11:42:49.902] <TB1> INFO: pulse height fill bit: 0
[11:42:49.902] <TB1> INFO: buffer corruption: 0
[11:42:49.966] <TB1> INFO: ######################################################################
[11:42:49.966] <TB1> INFO: PixTestTrim::doTest()
[11:42:49.966] <TB1> INFO: ######################################################################
[11:42:49.967] <TB1> INFO: ----------------------------------------------------------------------
[11:42:49.967] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[11:42:49.967] <TB1> INFO: ----------------------------------------------------------------------
[11:42:50.006] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[11:42:50.006] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:42:50.016] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:42:50.016] <TB1> INFO: run 1 of 1
[11:42:50.248] <TB1> INFO: Expecting 5025280 events.
[11:43:22.551] <TB1> INFO: 829168 events read in total (31710ms).
[11:43:53.874] <TB1> INFO: 1656592 events read in total (63033ms).
[11:44:25.167] <TB1> INFO: 2481192 events read in total (94326ms).
[11:44:56.580] <TB1> INFO: 3302320 events read in total (125739ms).
[11:45:27.510] <TB1> INFO: 4117848 events read in total (156670ms).
[11:45:58.847] <TB1> INFO: 4933032 events read in total (188006ms).
[11:46:02.521] <TB1> INFO: 5025280 events read in total (191680ms).
[11:46:02.578] <TB1> INFO: Test took 192562ms.
[11:46:17.808] <TB1> INFO: ROC 0 VthrComp = 122
[11:46:17.808] <TB1> INFO: ROC 1 VthrComp = 117
[11:46:17.808] <TB1> INFO: ROC 2 VthrComp = 126
[11:46:17.808] <TB1> INFO: ROC 3 VthrComp = 121
[11:46:17.809] <TB1> INFO: ROC 4 VthrComp = 129
[11:46:17.809] <TB1> INFO: ROC 5 VthrComp = 126
[11:46:17.809] <TB1> INFO: ROC 6 VthrComp = 128
[11:46:17.809] <TB1> INFO: ROC 7 VthrComp = 103
[11:46:17.809] <TB1> INFO: ROC 8 VthrComp = 124
[11:46:17.809] <TB1> INFO: ROC 9 VthrComp = 112
[11:46:17.809] <TB1> INFO: ROC 10 VthrComp = 116
[11:46:17.809] <TB1> INFO: ROC 11 VthrComp = 117
[11:46:17.809] <TB1> INFO: ROC 12 VthrComp = 126
[11:46:17.809] <TB1> INFO: ROC 13 VthrComp = 123
[11:46:17.809] <TB1> INFO: ROC 14 VthrComp = 124
[11:46:17.810] <TB1> INFO: ROC 15 VthrComp = 132
[11:46:18.042] <TB1> INFO: Expecting 41600 events.
[11:46:21.495] <TB1> INFO: 41600 events read in total (2861ms).
[11:46:21.495] <TB1> INFO: Test took 3684ms.
[11:46:21.504] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[11:46:21.504] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:46:21.513] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:46:21.513] <TB1> INFO: run 1 of 1
[11:46:21.792] <TB1> INFO: Expecting 5025280 events.
[11:46:49.699] <TB1> INFO: 590592 events read in total (27316ms).
[11:47:17.070] <TB1> INFO: 1180184 events read in total (54687ms).
[11:47:44.005] <TB1> INFO: 1770608 events read in total (81622ms).
[11:48:11.050] <TB1> INFO: 2361008 events read in total (108667ms).
[11:48:37.265] <TB1> INFO: 2949440 events read in total (134882ms).
[11:49:03.381] <TB1> INFO: 3535944 events read in total (160998ms).
[11:49:30.335] <TB1> INFO: 4121640 events read in total (187952ms).
[11:49:57.170] <TB1> INFO: 4707216 events read in total (214787ms).
[11:50:11.604] <TB1> INFO: 5025280 events read in total (229221ms).
[11:50:11.664] <TB1> INFO: Test took 230150ms.
[11:50:33.357] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 62.4162 for pixel 9/24 mean/min/max = 46.7866/30.9932/62.58
[11:50:33.357] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 59.2746 for pixel 14/14 mean/min/max = 45.5441/31.592/59.4961
[11:50:33.358] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 61.3211 for pixel 5/9 mean/min/max = 46.1584/30.7272/61.5896
[11:50:33.358] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 61.5547 for pixel 23/0 mean/min/max = 46.6221/31.6876/61.5566
[11:50:33.358] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 67.1526 for pixel 51/67 mean/min/max = 49.5213/31.4284/67.6142
[11:50:33.359] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 59.2585 for pixel 0/3 mean/min/max = 45.3992/31.5387/59.2597
[11:50:33.359] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 64.3093 for pixel 25/18 mean/min/max = 47.3933/30.2538/64.5328
[11:50:33.359] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 58.5107 for pixel 4/21 mean/min/max = 45.8775/33.224/58.531
[11:50:33.360] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 63.4032 for pixel 8/12 mean/min/max = 47.3885/31.2056/63.5714
[11:50:33.360] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 60.5455 for pixel 5/43 mean/min/max = 46.5715/32.5839/60.5591
[11:50:33.360] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 60.4783 for pixel 2/4 mean/min/max = 46.1667/31.6516/60.6818
[11:50:33.361] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 65.561 for pixel 18/0 mean/min/max = 48.3695/31.0293/65.7097
[11:50:33.361] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 59.1977 for pixel 14/1 mean/min/max = 45.3883/31.3412/59.4354
[11:50:33.361] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 63.5784 for pixel 19/0 mean/min/max = 47.1861/30.7406/63.6315
[11:50:33.361] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 64.891 for pixel 43/3 mean/min/max = 48.1515/30.9016/65.4014
[11:50:33.362] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 64.1021 for pixel 47/8 mean/min/max = 48.5047/32.8486/64.1607
[11:50:33.362] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:33.451] <TB1> INFO: Expecting 411648 events.
[11:50:43.213] <TB1> INFO: 411648 events read in total (9170ms).
[11:50:43.223] <TB1> INFO: Expecting 411648 events.
[11:50:52.622] <TB1> INFO: 411648 events read in total (8996ms).
[11:50:52.631] <TB1> INFO: Expecting 411648 events.
[11:51:02.232] <TB1> INFO: 411648 events read in total (9198ms).
[11:51:02.244] <TB1> INFO: Expecting 411648 events.
[11:51:11.804] <TB1> INFO: 411648 events read in total (9157ms).
[11:51:11.820] <TB1> INFO: Expecting 411648 events.
[11:51:21.265] <TB1> INFO: 411648 events read in total (9042ms).
[11:51:21.281] <TB1> INFO: Expecting 411648 events.
[11:51:30.641] <TB1> INFO: 411648 events read in total (8957ms).
[11:51:30.659] <TB1> INFO: Expecting 411648 events.
[11:51:40.012] <TB1> INFO: 411648 events read in total (8950ms).
[11:51:40.033] <TB1> INFO: Expecting 411648 events.
[11:51:49.420] <TB1> INFO: 411648 events read in total (8984ms).
[11:51:49.448] <TB1> INFO: Expecting 411648 events.
[11:51:59.058] <TB1> INFO: 411648 events read in total (9207ms).
[11:51:59.084] <TB1> INFO: Expecting 411648 events.
[11:52:08.687] <TB1> INFO: 411648 events read in total (9200ms).
[11:52:08.718] <TB1> INFO: Expecting 411648 events.
[11:52:18.214] <TB1> INFO: 411648 events read in total (9093ms).
[11:52:18.261] <TB1> INFO: Expecting 411648 events.
[11:52:27.687] <TB1> INFO: 411648 events read in total (9023ms).
[11:52:27.723] <TB1> INFO: Expecting 411648 events.
[11:52:37.195] <TB1> INFO: 411648 events read in total (9069ms).
[11:52:37.256] <TB1> INFO: Expecting 411648 events.
[11:52:46.677] <TB1> INFO: 411648 events read in total (9018ms).
[11:52:46.742] <TB1> INFO: Expecting 411648 events.
[11:52:56.395] <TB1> INFO: 411648 events read in total (9250ms).
[11:52:56.440] <TB1> INFO: Expecting 411648 events.
[11:53:05.978] <TB1> INFO: 411648 events read in total (9135ms).
[11:53:06.025] <TB1> INFO: Test took 152663ms.
[11:53:06.847] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[11:53:06.856] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:53:06.856] <TB1> INFO: run 1 of 1
[11:53:07.090] <TB1> INFO: Expecting 5025280 events.
[11:53:34.123] <TB1> INFO: 594696 events read in total (26441ms).
[11:54:01.412] <TB1> INFO: 1187888 events read in total (53730ms).
[11:54:28.602] <TB1> INFO: 1784872 events read in total (80920ms).
[11:54:55.633] <TB1> INFO: 2378328 events read in total (107952ms).
[11:55:22.498] <TB1> INFO: 2977248 events read in total (134816ms).
[11:55:49.583] <TB1> INFO: 3575984 events read in total (161901ms).
[11:56:16.633] <TB1> INFO: 4172048 events read in total (188951ms).
[11:56:43.838] <TB1> INFO: 4764656 events read in total (216156ms).
[11:56:55.742] <TB1> INFO: 5025280 events read in total (228060ms).
[11:56:55.905] <TB1> INFO: Test took 229050ms.
[11:57:14.836] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 1.500000 .. 147.747596
[11:57:15.071] <TB1> INFO: Expecting 208000 events.
[11:57:25.094] <TB1> INFO: 208000 events read in total (9432ms).
[11:57:25.094] <TB1> INFO: Test took 10256ms.
[11:57:25.142] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 157 (-1/-1) hits flags = 528 (plus default)
[11:57:25.151] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:57:25.151] <TB1> INFO: run 1 of 1
[11:57:25.384] <TB1> INFO: Expecting 5224960 events.
[11:57:53.721] <TB1> INFO: 584904 events read in total (27745ms).
[11:58:20.366] <TB1> INFO: 1169928 events read in total (54390ms).
[11:58:47.024] <TB1> INFO: 1754088 events read in total (81049ms).
[11:59:13.671] <TB1> INFO: 2338256 events read in total (107695ms).
[11:59:40.264] <TB1> INFO: 2922176 events read in total (134288ms).
[12:00:07.333] <TB1> INFO: 3505584 events read in total (161357ms).
[12:00:33.426] <TB1> INFO: 4088696 events read in total (187450ms).
[12:00:59.669] <TB1> INFO: 4671432 events read in total (213693ms).
[12:01:24.479] <TB1> INFO: 5224960 events read in total (238503ms).
[12:01:24.581] <TB1> INFO: Test took 239430ms.
[12:01:45.976] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.340174 .. 46.653755
[12:01:46.218] <TB1> INFO: Expecting 208000 events.
[12:01:56.483] <TB1> INFO: 208000 events read in total (9673ms).
[12:01:56.484] <TB1> INFO: Test took 10505ms.
[12:01:56.531] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[12:01:56.541] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:01:56.542] <TB1> INFO: run 1 of 1
[12:01:56.773] <TB1> INFO: Expecting 1331200 events.
[12:02:26.160] <TB1> INFO: 653768 events read in total (28796ms).
[12:02:54.296] <TB1> INFO: 1307272 events read in total (56932ms).
[12:02:55.706] <TB1> INFO: 1331200 events read in total (58343ms).
[12:02:55.741] <TB1> INFO: Test took 59200ms.
[12:03:13.307] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 24.152131 .. 45.918830
[12:03:13.554] <TB1> INFO: Expecting 208000 events.
[12:03:24.071] <TB1> INFO: 208000 events read in total (9926ms).
[12:03:24.071] <TB1> INFO: Test took 10762ms.
[12:03:24.119] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 14 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:03:24.129] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:03:24.129] <TB1> INFO: run 1 of 1
[12:03:24.361] <TB1> INFO: Expecting 1397760 events.
[12:03:54.654] <TB1> INFO: 671192 events read in total (29702ms).
[12:04:23.288] <TB1> INFO: 1341952 events read in total (58336ms).
[12:04:26.200] <TB1> INFO: 1397760 events read in total (61248ms).
[12:04:26.232] <TB1> INFO: Test took 62104ms.
[12:04:37.415] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 21.894511 .. 42.580601
[12:04:37.651] <TB1> INFO: Expecting 208000 events.
[12:04:47.523] <TB1> INFO: 208000 events read in total (9280ms).
[12:04:47.524] <TB1> INFO: Test took 10107ms.
[12:04:47.573] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 11 .. 52 (-1/-1) hits flags = 528 (plus default)
[12:04:47.584] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:04:47.584] <TB1> INFO: run 1 of 1
[12:04:47.814] <TB1> INFO: Expecting 1397760 events.
[12:05:17.660] <TB1> INFO: 697016 events read in total (29254ms).
[12:05:48.441] <TB1> INFO: 1392592 events read in total (60035ms).
[12:05:49.081] <TB1> INFO: 1397760 events read in total (60676ms).
[12:05:49.102] <TB1> INFO: Test took 61519ms.
[12:05:59.500] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:05:59.500] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:05:59.510] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:05:59.510] <TB1> INFO: run 1 of 1
[12:05:59.742] <TB1> INFO: Expecting 1364480 events.
[12:06:29.289] <TB1> INFO: 667408 events read in total (28956ms).
[12:06:58.277] <TB1> INFO: 1334544 events read in total (57944ms).
[12:07:00.038] <TB1> INFO: 1364480 events read in total (59706ms).
[12:07:00.068] <TB1> INFO: Test took 60559ms.
[12:07:11.240] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C0.dat
[12:07:11.240] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C1.dat
[12:07:11.240] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C2.dat
[12:07:11.240] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C3.dat
[12:07:11.240] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C4.dat
[12:07:11.240] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C5.dat
[12:07:11.240] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C6.dat
[12:07:11.241] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C7.dat
[12:07:11.241] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C8.dat
[12:07:11.241] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C9.dat
[12:07:11.241] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C10.dat
[12:07:11.241] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C11.dat
[12:07:11.241] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C12.dat
[12:07:11.241] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C13.dat
[12:07:11.241] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C14.dat
[12:07:11.241] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C15.dat
[12:07:11.241] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C0.dat
[12:07:11.249] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C1.dat
[12:07:11.258] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C2.dat
[12:07:11.266] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C3.dat
[12:07:11.274] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C4.dat
[12:07:11.282] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C5.dat
[12:07:11.290] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C6.dat
[12:07:11.298] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C7.dat
[12:07:11.305] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C8.dat
[12:07:11.313] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C9.dat
[12:07:11.322] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C10.dat
[12:07:11.330] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C11.dat
[12:07:11.338] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C12.dat
[12:07:11.346] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C13.dat
[12:07:11.354] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C14.dat
[12:07:11.362] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//trimParameters35_C15.dat
[12:07:11.370] <TB1> INFO: PixTestTrim::trimTest() done
[12:07:11.370] <TB1> INFO: vtrim: 144 141 136 150 143 130 153 131 143 152 130 153 138 133 138 135
[12:07:11.370] <TB1> INFO: vthrcomp: 122 117 126 121 129 126 128 103 124 112 116 117 126 123 124 132
[12:07:11.370] <TB1> INFO: vcal mean: 34.92 34.96 34.93 34.93 34.93 34.90 35.00 34.97 34.91 34.97 34.97 34.97 34.98 34.93 34.93 34.99
[12:07:11.370] <TB1> INFO: vcal RMS: 1.59 1.05 1.10 1.15 1.28 1.06 1.22 0.96 1.17 1.05 1.00 1.32 1.06 1.17 1.29 1.09
[12:07:11.370] <TB1> INFO: bits mean: 9.75 10.30 9.80 10.44 9.28 9.91 9.85 10.00 9.72 10.23 9.70 9.94 10.25 9.72 9.50 9.02
[12:07:11.370] <TB1> INFO: bits RMS: 2.61 2.38 2.70 2.22 2.63 2.63 2.65 2.30 2.54 2.21 2.57 2.45 2.42 2.66 2.68 2.63
[12:07:11.376] <TB1> INFO: ----------------------------------------------------------------------
[12:07:11.376] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:07:11.376] <TB1> INFO: ----------------------------------------------------------------------
[12:07:11.378] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:07:11.387] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:07:11.387] <TB1> INFO: run 1 of 1
[12:07:11.620] <TB1> INFO: Expecting 4160000 events.
[12:07:44.631] <TB1> INFO: 749975 events read in total (32419ms).
[12:08:17.006] <TB1> INFO: 1497860 events read in total (64794ms).
[12:08:49.364] <TB1> INFO: 2240095 events read in total (97152ms).
[12:09:21.874] <TB1> INFO: 2977470 events read in total (129662ms).
[12:09:54.408] <TB1> INFO: 3712490 events read in total (162196ms).
[12:10:14.773] <TB1> INFO: 4160000 events read in total (182561ms).
[12:10:14.824] <TB1> INFO: Test took 183437ms.
[12:10:36.907] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 221 (-1/-1) hits flags = 528 (plus default)
[12:10:36.916] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:10:36.916] <TB1> INFO: run 1 of 1
[12:10:37.149] <TB1> INFO: Expecting 4617600 events.
[12:11:09.602] <TB1> INFO: 699945 events read in total (31861ms).
[12:11:41.786] <TB1> INFO: 1397900 events read in total (64045ms).
[12:12:12.936] <TB1> INFO: 2093330 events read in total (95195ms).
[12:12:45.225] <TB1> INFO: 2785490 events read in total (127484ms).
[12:13:17.423] <TB1> INFO: 3476840 events read in total (159682ms).
[12:13:49.425] <TB1> INFO: 4166810 events read in total (191684ms).
[12:14:10.425] <TB1> INFO: 4617600 events read in total (212684ms).
[12:14:10.521] <TB1> INFO: Test took 213604ms.
[12:14:35.110] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[12:14:35.121] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:14:35.121] <TB1> INFO: run 1 of 1
[12:14:35.355] <TB1> INFO: Expecting 4243200 events.
[12:15:08.381] <TB1> INFO: 719645 events read in total (32434ms).
[12:15:40.534] <TB1> INFO: 1437820 events read in total (64587ms).
[12:16:12.432] <TB1> INFO: 2152200 events read in total (96485ms).
[12:16:44.131] <TB1> INFO: 2862910 events read in total (128184ms).
[12:17:15.909] <TB1> INFO: 3572035 events read in total (159962ms).
[12:17:45.457] <TB1> INFO: 4243200 events read in total (189510ms).
[12:17:45.515] <TB1> INFO: Test took 190394ms.
[12:18:08.905] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[12:18:08.915] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:18:08.915] <TB1> INFO: run 1 of 1
[12:18:09.147] <TB1> INFO: Expecting 4284800 events.
[12:18:41.198] <TB1> INFO: 717325 events read in total (31459ms).
[12:19:12.916] <TB1> INFO: 1433150 events read in total (63177ms).
[12:19:44.601] <TB1> INFO: 2145455 events read in total (94862ms).
[12:20:16.950] <TB1> INFO: 2853730 events read in total (127211ms).
[12:20:49.870] <TB1> INFO: 3560900 events read in total (160131ms).
[12:21:21.805] <TB1> INFO: 4270175 events read in total (192066ms).
[12:21:22.855] <TB1> INFO: 4284800 events read in total (193116ms).
[12:21:22.911] <TB1> INFO: Test took 193996ms.
[12:21:48.969] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[12:21:48.982] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:21:48.982] <TB1> INFO: run 1 of 1
[12:21:49.267] <TB1> INFO: Expecting 4326400 events.
[12:22:21.514] <TB1> INFO: 714920 events read in total (31655ms).
[12:22:52.930] <TB1> INFO: 1428090 events read in total (63071ms).
[12:23:24.327] <TB1> INFO: 2138075 events read in total (94469ms).
[12:23:55.407] <TB1> INFO: 2844175 events read in total (125548ms).
[12:24:27.532] <TB1> INFO: 3549165 events read in total (157673ms).
[12:24:58.656] <TB1> INFO: 4254510 events read in total (188797ms).
[12:25:02.220] <TB1> INFO: 4326400 events read in total (192361ms).
[12:25:02.277] <TB1> INFO: Test took 193295ms.
[12:25:26.017] <TB1> INFO: PixTestTrim::trimBitTest() done
[12:25:26.018] <TB1> INFO: PixTestTrim::doTest() done, duration: 2556 seconds
[12:25:26.018] <TB1> INFO: Decoding statistics:
[12:25:26.018] <TB1> INFO: General information:
[12:25:26.018] <TB1> INFO: 16bit words read: 0
[12:25:26.018] <TB1> INFO: valid events total: 0
[12:25:26.018] <TB1> INFO: empty events: 0
[12:25:26.018] <TB1> INFO: valid events with pixels: 0
[12:25:26.018] <TB1> INFO: valid pixel hits: 0
[12:25:26.018] <TB1> INFO: Event errors: 0
[12:25:26.018] <TB1> INFO: start marker: 0
[12:25:26.018] <TB1> INFO: stop marker: 0
[12:25:26.018] <TB1> INFO: overflow: 0
[12:25:26.018] <TB1> INFO: invalid 5bit words: 0
[12:25:26.018] <TB1> INFO: invalid XOR eye diagram: 0
[12:25:26.018] <TB1> INFO: frame (failed synchr.): 0
[12:25:26.018] <TB1> INFO: idle data (no TBM trl): 0
[12:25:26.018] <TB1> INFO: no data (only TBM hdr): 0
[12:25:26.018] <TB1> INFO: TBM errors: 0
[12:25:26.018] <TB1> INFO: flawed TBM headers: 0
[12:25:26.018] <TB1> INFO: flawed TBM trailers: 0
[12:25:26.018] <TB1> INFO: event ID mismatches: 0
[12:25:26.018] <TB1> INFO: ROC errors: 0
[12:25:26.018] <TB1> INFO: missing ROC header(s): 0
[12:25:26.018] <TB1> INFO: misplaced readback start: 0
[12:25:26.018] <TB1> INFO: Pixel decoding errors: 0
[12:25:26.018] <TB1> INFO: pixel data incomplete: 0
[12:25:26.018] <TB1> INFO: pixel address: 0
[12:25:26.018] <TB1> INFO: pulse height fill bit: 0
[12:25:26.018] <TB1> INFO: buffer corruption: 0
[12:25:26.628] <TB1> INFO: ######################################################################
[12:25:26.628] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:25:26.628] <TB1> INFO: ######################################################################
[12:25:26.861] <TB1> INFO: Expecting 41600 events.
[12:25:30.292] <TB1> INFO: 41600 events read in total (2840ms).
[12:25:30.293] <TB1> INFO: Test took 3664ms.
[12:25:30.730] <TB1> INFO: Expecting 41600 events.
[12:25:34.248] <TB1> INFO: 41600 events read in total (2926ms).
[12:25:34.249] <TB1> INFO: Test took 3749ms.
[12:25:34.262] <TB1> INFO: Max pixel from chip 0 is [8 ,12] phvalue 58
[12:25:34.262] <TB1> INFO: Max pixel from chip 1 is [7 ,8] phvalue 64
[12:25:34.262] <TB1> INFO: Max pixel from chip 2 is [4 ,33] phvalue 63
[12:25:34.262] <TB1> INFO: Max pixel from chip 3 is [18 ,7] phvalue 164
[12:25:34.263] <TB1> INFO: Max pixel from chip 4 is [4 ,18] phvalue 68
[12:25:34.263] <TB1> INFO: Max pixel from chip 5 is [17 ,12] phvalue 61
[12:25:34.263] <TB1> INFO: Max pixel from chip 6 is [9 ,16] phvalue 190
[12:25:34.263] <TB1> INFO: Max pixel from chip 7 is [14 ,21] phvalue 79
[12:25:34.263] <TB1> INFO: Max pixel from chip 8 is [40 ,21] phvalue 128
[12:25:34.263] <TB1> INFO: Max pixel from chip 9 is [8 ,17] phvalue 96
[12:25:34.264] <TB1> INFO: Max pixel from chip 10 is [16 ,7] phvalue 129
[12:25:34.264] <TB1> INFO: Max pixel from chip 11 is [6 ,9] phvalue 135
[12:25:34.264] <TB1> INFO: Max pixel from chip 12 is [30 ,35] phvalue 150
[12:25:34.264] <TB1> INFO: Max pixel from chip 13 is [12 ,12] phvalue 140
[12:25:34.264] <TB1> INFO: Max pixel from chip 14 is [24 ,50] phvalue 62
[12:25:34.265] <TB1> INFO: Max pixel from chip 15 is [8 ,14] phvalue 96
[12:25:34.544] <TB1> INFO: Expecting 41600 events.
[12:25:38.050] <TB1> INFO: 41600 events read in total (2915ms).
[12:25:38.051] <TB1> INFO: Test took 3772ms.
[12:25:38.059] <TB1> INFO: Min pixel from chip 0 is [3 ,17] phvalue 246
[12:25:38.060] <TB1> INFO: Min pixel from chip 1 is [39 ,62] phvalue 240
[12:25:38.060] <TB1> INFO: Min pixel from chip 2 is [9 ,59] phvalue 245
[12:25:38.060] <TB1> INFO: Min pixel from chip 3 is [3 ,5] phvalue 255
[12:25:38.060] <TB1> INFO: Min pixel from chip 4 is [16 ,58] phvalue 252
[12:25:38.060] <TB1> INFO: Min pixel from chip 5 is [10 ,6] phvalue 237
[12:25:38.060] <TB1> INFO: Min pixel from chip 6 is [3 ,5] phvalue 255
[12:25:38.060] <TB1> INFO: Min pixel from chip 7 is [12 ,49] phvalue 253
[12:25:38.061] <TB1> INFO: Min pixel from chip 8 is [3 ,5] phvalue 255
[12:25:38.061] <TB1> INFO: Min pixel from chip 9 is [3 ,5] phvalue 255
[12:25:38.061] <TB1> INFO: Min pixel from chip 10 is [3 ,5] phvalue 255
[12:25:38.061] <TB1> INFO: Min pixel from chip 11 is [3 ,5] phvalue 255
[12:25:38.061] <TB1> INFO: Min pixel from chip 12 is [3 ,5] phvalue 255
[12:25:38.061] <TB1> INFO: Min pixel from chip 13 is [3 ,5] phvalue 255
[12:25:38.061] <TB1> INFO: Min pixel from chip 14 is [11 ,52] phvalue 249
[12:25:38.061] <TB1> INFO: Min pixel from chip 15 is [3 ,5] phvalue 255
[12:25:38.340] <TB1> INFO: Expecting 2560 events.
[12:25:39.225] <TB1> INFO: 2560 events read in total (294ms).
[12:25:39.225] <TB1> INFO: Test took 1162ms.
[12:25:39.532] <TB1> INFO: Expecting 2560 events.
[12:25:40.416] <TB1> INFO: 2560 events read in total (292ms).
[12:25:40.416] <TB1> INFO: Test took 1191ms.
[12:25:40.724] <TB1> INFO: Expecting 2560 events.
[12:25:41.613] <TB1> INFO: 2560 events read in total (297ms).
[12:25:41.613] <TB1> INFO: Test took 1197ms.
[12:25:41.921] <TB1> INFO: Expecting 2560 events.
[12:25:42.805] <TB1> INFO: 2560 events read in total (292ms).
[12:25:42.805] <TB1> INFO: Test took 1192ms.
[12:25:43.113] <TB1> INFO: Expecting 2560 events.
[12:25:43.999] <TB1> INFO: 2560 events read in total (294ms).
[12:25:43.000] <TB1> INFO: Test took 1194ms.
[12:25:44.307] <TB1> INFO: Expecting 2560 events.
[12:25:45.187] <TB1> INFO: 2560 events read in total (288ms).
[12:25:45.187] <TB1> INFO: Test took 1187ms.
[12:25:45.495] <TB1> INFO: Expecting 2560 events.
[12:25:46.375] <TB1> INFO: 2560 events read in total (288ms).
[12:25:46.375] <TB1> INFO: Test took 1188ms.
[12:25:46.684] <TB1> INFO: Expecting 2560 events.
[12:25:47.563] <TB1> INFO: 2560 events read in total (288ms).
[12:25:47.563] <TB1> INFO: Test took 1187ms.
[12:25:47.871] <TB1> INFO: Expecting 2560 events.
[12:25:48.752] <TB1> INFO: 2560 events read in total (289ms).
[12:25:48.752] <TB1> INFO: Test took 1188ms.
[12:25:49.060] <TB1> INFO: Expecting 2560 events.
[12:25:49.940] <TB1> INFO: 2560 events read in total (289ms).
[12:25:49.940] <TB1> INFO: Test took 1188ms.
[12:25:50.247] <TB1> INFO: Expecting 2560 events.
[12:25:51.132] <TB1> INFO: 2560 events read in total (293ms).
[12:25:51.132] <TB1> INFO: Test took 1192ms.
[12:25:51.440] <TB1> INFO: Expecting 2560 events.
[12:25:52.321] <TB1> INFO: 2560 events read in total (290ms).
[12:25:52.321] <TB1> INFO: Test took 1189ms.
[12:25:52.628] <TB1> INFO: Expecting 2560 events.
[12:25:53.519] <TB1> INFO: 2560 events read in total (299ms).
[12:25:53.519] <TB1> INFO: Test took 1198ms.
[12:25:53.826] <TB1> INFO: Expecting 2560 events.
[12:25:54.710] <TB1> INFO: 2560 events read in total (292ms).
[12:25:54.710] <TB1> INFO: Test took 1189ms.
[12:25:55.018] <TB1> INFO: Expecting 2560 events.
[12:25:55.903] <TB1> INFO: 2560 events read in total (293ms).
[12:25:55.903] <TB1> INFO: Test took 1192ms.
[12:25:56.211] <TB1> INFO: Expecting 2560 events.
[12:25:57.095] <TB1> INFO: 2560 events read in total (293ms).
[12:25:57.095] <TB1> INFO: Test took 1191ms.
[12:25:57.098] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:25:57.404] <TB1> INFO: Expecting 655360 events.
[12:26:12.414] <TB1> INFO: 655360 events read in total (14418ms).
[12:26:12.425] <TB1> INFO: Expecting 655360 events.
[12:26:27.110] <TB1> INFO: 655360 events read in total (14282ms).
[12:26:27.132] <TB1> INFO: Expecting 655360 events.
[12:26:41.722] <TB1> INFO: 655360 events read in total (14187ms).
[12:26:41.740] <TB1> INFO: Expecting 655360 events.
[12:26:56.275] <TB1> INFO: 655360 events read in total (14132ms).
[12:26:56.297] <TB1> INFO: Expecting 655360 events.
[12:27:10.917] <TB1> INFO: 655360 events read in total (14217ms).
[12:27:10.943] <TB1> INFO: Expecting 655360 events.
[12:27:25.726] <TB1> INFO: 655360 events read in total (14379ms).
[12:27:25.757] <TB1> INFO: Expecting 655360 events.
[12:27:40.379] <TB1> INFO: 655360 events read in total (14219ms).
[12:27:40.414] <TB1> INFO: Expecting 655360 events.
[12:27:55.185] <TB1> INFO: 655360 events read in total (14368ms).
[12:27:55.225] <TB1> INFO: Expecting 655360 events.
[12:28:09.888] <TB1> INFO: 655360 events read in total (14260ms).
[12:28:09.929] <TB1> INFO: Expecting 655360 events.
[12:28:24.604] <TB1> INFO: 655360 events read in total (14272ms).
[12:28:24.653] <TB1> INFO: Expecting 655360 events.
[12:28:39.401] <TB1> INFO: 655360 events read in total (14345ms).
[12:28:39.454] <TB1> INFO: Expecting 655360 events.
[12:28:54.235] <TB1> INFO: 655360 events read in total (14378ms).
[12:28:54.294] <TB1> INFO: Expecting 655360 events.
[12:29:09.314] <TB1> INFO: 655360 events read in total (14617ms).
[12:29:09.412] <TB1> INFO: Expecting 655360 events.
[12:29:24.321] <TB1> INFO: 655360 events read in total (14505ms).
[12:29:24.424] <TB1> INFO: Expecting 655360 events.
[12:29:39.180] <TB1> INFO: 655360 events read in total (14353ms).
[12:29:39.249] <TB1> INFO: Expecting 655360 events.
[12:29:53.820] <TB1> INFO: 655360 events read in total (14168ms).
[12:29:53.894] <TB1> INFO: Test took 236796ms.
[12:29:53.975] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:29:54.240] <TB1> INFO: Expecting 655360 events.
[12:30:09.150] <TB1> INFO: 655360 events read in total (14319ms).
[12:30:09.160] <TB1> INFO: Expecting 655360 events.
[12:30:23.816] <TB1> INFO: 655360 events read in total (14253ms).
[12:30:23.830] <TB1> INFO: Expecting 655360 events.
[12:30:38.490] <TB1> INFO: 655360 events read in total (14257ms).
[12:30:38.508] <TB1> INFO: Expecting 655360 events.
[12:30:53.157] <TB1> INFO: 655360 events read in total (14246ms).
[12:30:53.180] <TB1> INFO: Expecting 655360 events.
[12:31:07.967] <TB1> INFO: 655360 events read in total (14384ms).
[12:31:07.994] <TB1> INFO: Expecting 655360 events.
[12:31:22.679] <TB1> INFO: 655360 events read in total (14282ms).
[12:31:22.709] <TB1> INFO: Expecting 655360 events.
[12:31:37.084] <TB1> INFO: 655360 events read in total (13972ms).
[12:31:37.117] <TB1> INFO: Expecting 655360 events.
[12:31:51.945] <TB1> INFO: 655360 events read in total (14425ms).
[12:31:52.004] <TB1> INFO: Expecting 655360 events.
[12:32:06.559] <TB1> INFO: 655360 events read in total (14152ms).
[12:32:06.624] <TB1> INFO: Expecting 655360 events.
[12:32:21.018] <TB1> INFO: 655360 events read in total (13991ms).
[12:32:21.066] <TB1> INFO: Expecting 655360 events.
[12:32:35.551] <TB1> INFO: 655360 events read in total (14082ms).
[12:32:35.604] <TB1> INFO: Expecting 655360 events.
[12:32:50.051] <TB1> INFO: 655360 events read in total (14044ms).
[12:32:50.108] <TB1> INFO: Expecting 655360 events.
[12:33:04.843] <TB1> INFO: 655360 events read in total (14332ms).
[12:33:04.905] <TB1> INFO: Expecting 655360 events.
[12:33:19.862] <TB1> INFO: 655360 events read in total (14554ms).
[12:33:19.927] <TB1> INFO: Expecting 655360 events.
[12:33:34.604] <TB1> INFO: 655360 events read in total (14274ms).
[12:33:34.673] <TB1> INFO: Expecting 655360 events.
[12:33:49.359] <TB1> INFO: 655360 events read in total (14283ms).
[12:33:49.431] <TB1> INFO: Test took 235456ms.
[12:33:49.590] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.595] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.600] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.605] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.610] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:33:49.615] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:33:49.620] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:33:49.624] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[12:33:49.629] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[12:33:49.634] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[12:33:49.638] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[12:33:49.643] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[12:33:49.648] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[12:33:49.652] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.657] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.662] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.666] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.671] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.676] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:33:49.680] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:33:49.685] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:33:49.689] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.694] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.699] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.703] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.708] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.712] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:33:49.717] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:33:49.721] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:33:49.726] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[12:33:49.730] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[12:33:49.734] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[12:33:49.739] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.744] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:33:49.776] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C0.dat
[12:33:49.776] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C1.dat
[12:33:49.776] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C2.dat
[12:33:49.777] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C3.dat
[12:33:49.777] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C4.dat
[12:33:49.777] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C5.dat
[12:33:49.777] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C6.dat
[12:33:49.777] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C7.dat
[12:33:49.777] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C8.dat
[12:33:49.777] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C9.dat
[12:33:49.777] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C10.dat
[12:33:49.777] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C11.dat
[12:33:49.777] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C12.dat
[12:33:49.777] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C13.dat
[12:33:49.777] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C14.dat
[12:33:49.777] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//dacParameters35_C15.dat
[12:33:50.012] <TB1> INFO: Expecting 41600 events.
[12:33:53.239] <TB1> INFO: 41600 events read in total (2635ms).
[12:33:53.240] <TB1> INFO: Test took 3460ms.
[12:33:53.763] <TB1> INFO: Expecting 41600 events.
[12:33:56.801] <TB1> INFO: 41600 events read in total (2446ms).
[12:33:56.802] <TB1> INFO: Test took 3348ms.
[12:33:57.248] <TB1> INFO: Expecting 41600 events.
[12:34:00.370] <TB1> INFO: 41600 events read in total (2530ms).
[12:34:00.370] <TB1> INFO: Test took 3354ms.
[12:34:00.584] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:00.672] <TB1> INFO: Expecting 2560 events.
[12:34:01.556] <TB1> INFO: 2560 events read in total (292ms).
[12:34:01.556] <TB1> INFO: Test took 972ms.
[12:34:01.558] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:01.865] <TB1> INFO: Expecting 2560 events.
[12:34:02.750] <TB1> INFO: 2560 events read in total (294ms).
[12:34:02.750] <TB1> INFO: Test took 1192ms.
[12:34:02.752] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:03.058] <TB1> INFO: Expecting 2560 events.
[12:34:03.942] <TB1> INFO: 2560 events read in total (292ms).
[12:34:03.942] <TB1> INFO: Test took 1190ms.
[12:34:03.944] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:04.251] <TB1> INFO: Expecting 2560 events.
[12:34:05.135] <TB1> INFO: 2560 events read in total (293ms).
[12:34:05.135] <TB1> INFO: Test took 1191ms.
[12:34:05.137] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:05.444] <TB1> INFO: Expecting 2560 events.
[12:34:06.327] <TB1> INFO: 2560 events read in total (292ms).
[12:34:06.327] <TB1> INFO: Test took 1190ms.
[12:34:06.329] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:06.636] <TB1> INFO: Expecting 2560 events.
[12:34:07.520] <TB1> INFO: 2560 events read in total (292ms).
[12:34:07.521] <TB1> INFO: Test took 1192ms.
[12:34:07.522] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:07.829] <TB1> INFO: Expecting 2560 events.
[12:34:08.717] <TB1> INFO: 2560 events read in total (296ms).
[12:34:08.717] <TB1> INFO: Test took 1195ms.
[12:34:08.719] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:09.026] <TB1> INFO: Expecting 2560 events.
[12:34:09.915] <TB1> INFO: 2560 events read in total (298ms).
[12:34:09.915] <TB1> INFO: Test took 1196ms.
[12:34:09.917] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:10.223] <TB1> INFO: Expecting 2560 events.
[12:34:11.103] <TB1> INFO: 2560 events read in total (288ms).
[12:34:11.103] <TB1> INFO: Test took 1186ms.
[12:34:11.105] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:11.412] <TB1> INFO: Expecting 2560 events.
[12:34:12.297] <TB1> INFO: 2560 events read in total (294ms).
[12:34:12.297] <TB1> INFO: Test took 1192ms.
[12:34:12.299] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:12.605] <TB1> INFO: Expecting 2560 events.
[12:34:13.485] <TB1> INFO: 2560 events read in total (288ms).
[12:34:13.485] <TB1> INFO: Test took 1186ms.
[12:34:13.487] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:13.793] <TB1> INFO: Expecting 2560 events.
[12:34:14.673] <TB1> INFO: 2560 events read in total (288ms).
[12:34:14.673] <TB1> INFO: Test took 1186ms.
[12:34:14.675] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:14.982] <TB1> INFO: Expecting 2560 events.
[12:34:15.861] <TB1> INFO: 2560 events read in total (288ms).
[12:34:15.861] <TB1> INFO: Test took 1186ms.
[12:34:15.863] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:16.170] <TB1> INFO: Expecting 2560 events.
[12:34:17.055] <TB1> INFO: 2560 events read in total (293ms).
[12:34:17.055] <TB1> INFO: Test took 1192ms.
[12:34:17.057] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:17.363] <TB1> INFO: Expecting 2560 events.
[12:34:18.248] <TB1> INFO: 2560 events read in total (293ms).
[12:34:18.248] <TB1> INFO: Test took 1191ms.
[12:34:18.250] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:18.557] <TB1> INFO: Expecting 2560 events.
[12:34:19.437] <TB1> INFO: 2560 events read in total (288ms).
[12:34:19.438] <TB1> INFO: Test took 1188ms.
[12:34:19.439] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:19.746] <TB1> INFO: Expecting 2560 events.
[12:34:20.626] <TB1> INFO: 2560 events read in total (288ms).
[12:34:20.627] <TB1> INFO: Test took 1188ms.
[12:34:20.628] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:20.935] <TB1> INFO: Expecting 2560 events.
[12:34:21.815] <TB1> INFO: 2560 events read in total (289ms).
[12:34:21.815] <TB1> INFO: Test took 1187ms.
[12:34:21.817] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:22.123] <TB1> INFO: Expecting 2560 events.
[12:34:23.008] <TB1> INFO: 2560 events read in total (293ms).
[12:34:23.008] <TB1> INFO: Test took 1191ms.
[12:34:23.010] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:23.316] <TB1> INFO: Expecting 2560 events.
[12:34:24.201] <TB1> INFO: 2560 events read in total (294ms).
[12:34:24.201] <TB1> INFO: Test took 1191ms.
[12:34:24.203] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:24.509] <TB1> INFO: Expecting 2560 events.
[12:34:25.389] <TB1> INFO: 2560 events read in total (289ms).
[12:34:25.389] <TB1> INFO: Test took 1186ms.
[12:34:25.391] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:25.697] <TB1> INFO: Expecting 2560 events.
[12:34:26.582] <TB1> INFO: 2560 events read in total (293ms).
[12:34:26.582] <TB1> INFO: Test took 1191ms.
[12:34:26.584] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:26.891] <TB1> INFO: Expecting 2560 events.
[12:34:27.770] <TB1> INFO: 2560 events read in total (288ms).
[12:34:27.770] <TB1> INFO: Test took 1186ms.
[12:34:27.772] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:28.079] <TB1> INFO: Expecting 2560 events.
[12:34:28.959] <TB1> INFO: 2560 events read in total (288ms).
[12:34:28.959] <TB1> INFO: Test took 1187ms.
[12:34:28.961] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:29.268] <TB1> INFO: Expecting 2560 events.
[12:34:30.151] <TB1> INFO: 2560 events read in total (292ms).
[12:34:30.152] <TB1> INFO: Test took 1191ms.
[12:34:30.154] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:30.460] <TB1> INFO: Expecting 2560 events.
[12:34:31.349] <TB1> INFO: 2560 events read in total (297ms).
[12:34:31.349] <TB1> INFO: Test took 1196ms.
[12:34:31.351] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:31.658] <TB1> INFO: Expecting 2560 events.
[12:34:32.542] <TB1> INFO: 2560 events read in total (292ms).
[12:34:32.542] <TB1> INFO: Test took 1191ms.
[12:34:32.544] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:32.851] <TB1> INFO: Expecting 2560 events.
[12:34:33.736] <TB1> INFO: 2560 events read in total (293ms).
[12:34:33.737] <TB1> INFO: Test took 1193ms.
[12:34:33.739] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:34.045] <TB1> INFO: Expecting 2560 events.
[12:34:34.933] <TB1> INFO: 2560 events read in total (296ms).
[12:34:34.933] <TB1> INFO: Test took 1195ms.
[12:34:34.935] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:35.242] <TB1> INFO: Expecting 2560 events.
[12:34:36.131] <TB1> INFO: 2560 events read in total (297ms).
[12:34:36.132] <TB1> INFO: Test took 1197ms.
[12:34:36.134] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:36.440] <TB1> INFO: Expecting 2560 events.
[12:34:37.329] <TB1> INFO: 2560 events read in total (298ms).
[12:34:37.329] <TB1> INFO: Test took 1195ms.
[12:34:37.331] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:34:37.638] <TB1> INFO: Expecting 2560 events.
[12:34:38.527] <TB1> INFO: 2560 events read in total (297ms).
[12:34:38.527] <TB1> INFO: Test took 1196ms.
[12:34:38.989] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 552 seconds
[12:34:38.989] <TB1> INFO: PH scale (per ROC): 55 58 57 48 58 55 57 64 47 46 58 44 65 48 61 46
[12:34:38.989] <TB1> INFO: PH offset (per ROC): 126 126 124 93 124 127 89 123 102 108 108 99 105 96 127 107
[12:34:38.995] <TB1> INFO: Decoding statistics:
[12:34:38.995] <TB1> INFO: General information:
[12:34:38.995] <TB1> INFO: 16bit words read: 127880
[12:34:38.995] <TB1> INFO: valid events total: 20480
[12:34:38.995] <TB1> INFO: empty events: 17980
[12:34:38.995] <TB1> INFO: valid events with pixels: 2500
[12:34:38.995] <TB1> INFO: valid pixel hits: 2500
[12:34:38.995] <TB1> INFO: Event errors: 0
[12:34:38.995] <TB1> INFO: start marker: 0
[12:34:38.995] <TB1> INFO: stop marker: 0
[12:34:38.995] <TB1> INFO: overflow: 0
[12:34:38.995] <TB1> INFO: invalid 5bit words: 0
[12:34:38.995] <TB1> INFO: invalid XOR eye diagram: 0
[12:34:38.995] <TB1> INFO: frame (failed synchr.): 0
[12:34:38.995] <TB1> INFO: idle data (no TBM trl): 0
[12:34:38.995] <TB1> INFO: no data (only TBM hdr): 0
[12:34:38.995] <TB1> INFO: TBM errors: 0
[12:34:38.995] <TB1> INFO: flawed TBM headers: 0
[12:34:38.995] <TB1> INFO: flawed TBM trailers: 0
[12:34:38.995] <TB1> INFO: event ID mismatches: 0
[12:34:38.995] <TB1> INFO: ROC errors: 0
[12:34:38.995] <TB1> INFO: missing ROC header(s): 0
[12:34:38.995] <TB1> INFO: misplaced readback start: 0
[12:34:38.995] <TB1> INFO: Pixel decoding errors: 0
[12:34:38.995] <TB1> INFO: pixel data incomplete: 0
[12:34:38.995] <TB1> INFO: pixel address: 0
[12:34:38.995] <TB1> INFO: pulse height fill bit: 0
[12:34:38.995] <TB1> INFO: buffer corruption: 0
[12:34:39.257] <TB1> INFO: ######################################################################
[12:34:39.257] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[12:34:39.257] <TB1> INFO: ######################################################################
[12:34:39.269] <TB1> INFO: scanning low vcal = 10
[12:34:39.506] <TB1> INFO: Expecting 41600 events.
[12:34:43.117] <TB1> INFO: 41600 events read in total (3020ms).
[12:34:43.117] <TB1> INFO: Test took 3848ms.
[12:34:43.119] <TB1> INFO: scanning low vcal = 20
[12:34:43.433] <TB1> INFO: Expecting 41600 events.
[12:34:47.047] <TB1> INFO: 41600 events read in total (3023ms).
[12:34:47.047] <TB1> INFO: Test took 3928ms.
[12:34:47.049] <TB1> INFO: scanning low vcal = 30
[12:34:47.348] <TB1> INFO: Expecting 41600 events.
[12:34:51.025] <TB1> INFO: 41600 events read in total (3085ms).
[12:34:51.026] <TB1> INFO: Test took 3977ms.
[12:34:51.028] <TB1> INFO: scanning low vcal = 40
[12:34:51.341] <TB1> INFO: Expecting 41600 events.
[12:34:55.322] <TB1> INFO: 41600 events read in total (3389ms).
[12:34:55.323] <TB1> INFO: Test took 4295ms.
[12:34:55.326] <TB1> INFO: scanning low vcal = 50
[12:34:55.634] <TB1> INFO: Expecting 41600 events.
[12:34:59.623] <TB1> INFO: 41600 events read in total (3397ms).
[12:34:59.623] <TB1> INFO: Test took 4297ms.
[12:34:59.626] <TB1> INFO: scanning low vcal = 60
[12:34:59.934] <TB1> INFO: Expecting 41600 events.
[12:35:03.955] <TB1> INFO: 41600 events read in total (3429ms).
[12:35:03.956] <TB1> INFO: Test took 4330ms.
[12:35:03.959] <TB1> INFO: scanning low vcal = 70
[12:35:04.236] <TB1> INFO: Expecting 41600 events.
[12:35:08.220] <TB1> INFO: 41600 events read in total (3393ms).
[12:35:08.221] <TB1> INFO: Test took 4262ms.
[12:35:08.223] <TB1> INFO: scanning low vcal = 80
[12:35:08.532] <TB1> INFO: Expecting 41600 events.
[12:35:12.510] <TB1> INFO: 41600 events read in total (3386ms).
[12:35:12.511] <TB1> INFO: Test took 4288ms.
[12:35:12.513] <TB1> INFO: scanning low vcal = 90
[12:35:12.790] <TB1> INFO: Expecting 41600 events.
[12:35:16.813] <TB1> INFO: 41600 events read in total (3431ms).
[12:35:16.813] <TB1> INFO: Test took 4300ms.
[12:35:16.816] <TB1> INFO: scanning low vcal = 100
[12:35:17.093] <TB1> INFO: Expecting 41600 events.
[12:35:21.107] <TB1> INFO: 41600 events read in total (3422ms).
[12:35:21.108] <TB1> INFO: Test took 4292ms.
[12:35:21.110] <TB1> INFO: scanning low vcal = 110
[12:35:21.387] <TB1> INFO: Expecting 41600 events.
[12:35:25.375] <TB1> INFO: 41600 events read in total (3397ms).
[12:35:25.376] <TB1> INFO: Test took 4266ms.
[12:35:25.378] <TB1> INFO: scanning low vcal = 120
[12:35:25.655] <TB1> INFO: Expecting 41600 events.
[12:35:29.642] <TB1> INFO: 41600 events read in total (3396ms).
[12:35:29.643] <TB1> INFO: Test took 4265ms.
[12:35:29.645] <TB1> INFO: scanning low vcal = 130
[12:35:29.922] <TB1> INFO: Expecting 41600 events.
[12:35:33.885] <TB1> INFO: 41600 events read in total (3371ms).
[12:35:33.886] <TB1> INFO: Test took 4240ms.
[12:35:33.888] <TB1> INFO: scanning low vcal = 140
[12:35:34.165] <TB1> INFO: Expecting 41600 events.
[12:35:38.180] <TB1> INFO: 41600 events read in total (3424ms).
[12:35:38.181] <TB1> INFO: Test took 4293ms.
[12:35:38.184] <TB1> INFO: scanning low vcal = 150
[12:35:38.494] <TB1> INFO: Expecting 41600 events.
[12:35:42.535] <TB1> INFO: 41600 events read in total (3449ms).
[12:35:42.536] <TB1> INFO: Test took 4352ms.
[12:35:42.539] <TB1> INFO: scanning low vcal = 160
[12:35:42.850] <TB1> INFO: Expecting 41600 events.
[12:35:46.838] <TB1> INFO: 41600 events read in total (3396ms).
[12:35:46.838] <TB1> INFO: Test took 4299ms.
[12:35:46.841] <TB1> INFO: scanning low vcal = 170
[12:35:47.118] <TB1> INFO: Expecting 41600 events.
[12:35:51.158] <TB1> INFO: 41600 events read in total (3449ms).
[12:35:51.160] <TB1> INFO: Test took 4319ms.
[12:35:51.162] <TB1> INFO: scanning low vcal = 180
[12:35:51.473] <TB1> INFO: Expecting 41600 events.
[12:35:55.466] <TB1> INFO: 41600 events read in total (3401ms).
[12:35:55.467] <TB1> INFO: Test took 4304ms.
[12:35:55.470] <TB1> INFO: scanning low vcal = 190
[12:35:55.780] <TB1> INFO: Expecting 41600 events.
[12:35:59.775] <TB1> INFO: 41600 events read in total (3403ms).
[12:35:59.776] <TB1> INFO: Test took 4306ms.
[12:35:59.779] <TB1> INFO: scanning low vcal = 200
[12:36:00.055] <TB1> INFO: Expecting 41600 events.
[12:36:04.014] <TB1> INFO: 41600 events read in total (3367ms).
[12:36:04.015] <TB1> INFO: Test took 4236ms.
[12:36:04.018] <TB1> INFO: scanning low vcal = 210
[12:36:04.294] <TB1> INFO: Expecting 41600 events.
[12:36:08.253] <TB1> INFO: 41600 events read in total (3367ms).
[12:36:08.254] <TB1> INFO: Test took 4236ms.
[12:36:08.256] <TB1> INFO: scanning low vcal = 220
[12:36:08.533] <TB1> INFO: Expecting 41600 events.
[12:36:12.568] <TB1> INFO: 41600 events read in total (3442ms).
[12:36:12.569] <TB1> INFO: Test took 4313ms.
[12:36:12.572] <TB1> INFO: scanning low vcal = 230
[12:36:12.848] <TB1> INFO: Expecting 41600 events.
[12:36:16.931] <TB1> INFO: 41600 events read in total (3491ms).
[12:36:16.932] <TB1> INFO: Test took 4360ms.
[12:36:16.935] <TB1> INFO: scanning low vcal = 240
[12:36:17.265] <TB1> INFO: Expecting 41600 events.
[12:36:21.280] <TB1> INFO: 41600 events read in total (3424ms).
[12:36:21.280] <TB1> INFO: Test took 4344ms.
[12:36:21.283] <TB1> INFO: scanning low vcal = 250
[12:36:21.559] <TB1> INFO: Expecting 41600 events.
[12:36:25.500] <TB1> INFO: 41600 events read in total (3349ms).
[12:36:25.501] <TB1> INFO: Test took 4218ms.
[12:36:25.505] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[12:36:25.781] <TB1> INFO: Expecting 41600 events.
[12:36:29.761] <TB1> INFO: 41600 events read in total (3389ms).
[12:36:29.761] <TB1> INFO: Test took 4256ms.
[12:36:29.764] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[12:36:30.041] <TB1> INFO: Expecting 41600 events.
[12:36:33.989] <TB1> INFO: 41600 events read in total (3356ms).
[12:36:33.990] <TB1> INFO: Test took 4226ms.
[12:36:33.993] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[12:36:34.270] <TB1> INFO: Expecting 41600 events.
[12:36:38.217] <TB1> INFO: 41600 events read in total (3355ms).
[12:36:38.218] <TB1> INFO: Test took 4225ms.
[12:36:38.221] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[12:36:38.497] <TB1> INFO: Expecting 41600 events.
[12:36:42.444] <TB1> INFO: 41600 events read in total (3355ms).
[12:36:42.444] <TB1> INFO: Test took 4223ms.
[12:36:42.447] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:36:42.724] <TB1> INFO: Expecting 41600 events.
[12:36:46.679] <TB1> INFO: 41600 events read in total (3363ms).
[12:36:46.680] <TB1> INFO: Test took 4233ms.
[12:36:47.043] <TB1> INFO: PixTestGainPedestal::measure() done
[12:37:19.265] <TB1> INFO: PixTestGainPedestal::fit() done
[12:37:19.265] <TB1> INFO: non-linearity mean: 0.982 0.982 0.980 0.954 0.983 0.981 0.962 0.984 0.944 0.930 0.976 0.938 0.977 0.937 0.984 0.941
[12:37:19.265] <TB1> INFO: non-linearity RMS: 0.004 0.004 0.006 0.060 0.003 0.006 0.031 0.004 0.101 0.120 0.007 0.116 0.008 0.098 0.004 0.150
[12:37:19.265] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C0.dat
[12:37:19.279] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C1.dat
[12:37:19.293] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C2.dat
[12:37:19.307] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C3.dat
[12:37:19.320] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C4.dat
[12:37:19.334] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C5.dat
[12:37:19.348] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C6.dat
[12:37:19.362] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C7.dat
[12:37:19.376] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C8.dat
[12:37:19.390] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C9.dat
[12:37:19.404] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C10.dat
[12:37:19.418] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C11.dat
[12:37:19.432] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C12.dat
[12:37:19.446] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C13.dat
[12:37:19.460] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C14.dat
[12:37:19.474] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-15_11h07m_1479204422//000_Fulltest_m20//phCalibrationFitErr35_C15.dat
[12:37:19.488] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 160 seconds
[12:37:19.488] <TB1> INFO: Decoding statistics:
[12:37:19.488] <TB1> INFO: General information:
[12:37:19.488] <TB1> INFO: 16bit words read: 3327512
[12:37:19.488] <TB1> INFO: valid events total: 332800
[12:37:19.488] <TB1> INFO: empty events: 0
[12:37:19.488] <TB1> INFO: valid events with pixels: 332800
[12:37:19.488] <TB1> INFO: valid pixel hits: 665356
[12:37:19.488] <TB1> INFO: Event errors: 0
[12:37:19.488] <TB1> INFO: start marker: 0
[12:37:19.488] <TB1> INFO: stop marker: 0
[12:37:19.488] <TB1> INFO: overflow: 0
[12:37:19.488] <TB1> INFO: invalid 5bit words: 0
[12:37:19.488] <TB1> INFO: invalid XOR eye diagram: 0
[12:37:19.488] <TB1> INFO: frame (failed synchr.): 0
[12:37:19.488] <TB1> INFO: idle data (no TBM trl): 0
[12:37:19.488] <TB1> INFO: no data (only TBM hdr): 0
[12:37:19.488] <TB1> INFO: TBM errors: 0
[12:37:19.488] <TB1> INFO: flawed TBM headers: 0
[12:37:19.488] <TB1> INFO: flawed TBM trailers: 0
[12:37:19.488] <TB1> INFO: event ID mismatches: 0
[12:37:19.488] <TB1> INFO: ROC errors: 0
[12:37:19.488] <TB1> INFO: missing ROC header(s): 0
[12:37:19.488] <TB1> INFO: misplaced readback start: 0
[12:37:19.488] <TB1> INFO: Pixel decoding errors: 0
[12:37:19.488] <TB1> INFO: pixel data incomplete: 0
[12:37:19.488] <TB1> INFO: pixel address: 0
[12:37:19.488] <TB1> INFO: pulse height fill bit: 0
[12:37:19.488] <TB1> INFO: buffer corruption: 0
[12:37:19.502] <TB1> INFO: Decoding statistics:
[12:37:19.502] <TB1> INFO: General information:
[12:37:19.502] <TB1> INFO: 16bit words read: 3456928
[12:37:19.502] <TB1> INFO: valid events total: 353536
[12:37:19.502] <TB1> INFO: empty events: 18236
[12:37:19.502] <TB1> INFO: valid events with pixels: 335300
[12:37:19.502] <TB1> INFO: valid pixel hits: 667856
[12:37:19.502] <TB1> INFO: Event errors: 0
[12:37:19.502] <TB1> INFO: start marker: 0
[12:37:19.502] <TB1> INFO: stop marker: 0
[12:37:19.502] <TB1> INFO: overflow: 0
[12:37:19.502] <TB1> INFO: invalid 5bit words: 0
[12:37:19.502] <TB1> INFO: invalid XOR eye diagram: 0
[12:37:19.502] <TB1> INFO: frame (failed synchr.): 0
[12:37:19.502] <TB1> INFO: idle data (no TBM trl): 0
[12:37:19.502] <TB1> INFO: no data (only TBM hdr): 0
[12:37:19.502] <TB1> INFO: TBM errors: 0
[12:37:19.502] <TB1> INFO: flawed TBM headers: 0
[12:37:19.502] <TB1> INFO: flawed TBM trailers: 0
[12:37:19.502] <TB1> INFO: event ID mismatches: 0
[12:37:19.502] <TB1> INFO: ROC errors: 0
[12:37:19.502] <TB1> INFO: missing ROC header(s): 0
[12:37:19.502] <TB1> INFO: misplaced readback start: 0
[12:37:19.502] <TB1> INFO: Pixel decoding errors: 0
[12:37:19.502] <TB1> INFO: pixel data incomplete: 0
[12:37:19.502] <TB1> INFO: pixel address: 0
[12:37:19.502] <TB1> INFO: pulse height fill bit: 0
[12:37:19.502] <TB1> INFO: buffer corruption: 0
[12:37:19.502] <TB1> INFO: enter test to run
[12:37:19.502] <TB1> INFO: test: exit no parameter change
[12:37:19.527] <TB1> QUIET: Connection to board 153 closed.
[12:37:19.528] <TB1> INFO: pXar: this is the end, my friend