[13:58:51.908] <TB2> INFO: *** Welcome to pxar ***
[13:58:51.908] <TB2> INFO: *** Today: 2016/11/07
[13:58:51.914] <TB2> INFO: *** Version: c8ba-dirty
[13:58:51.914] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C15.dat
[13:58:51.915] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[13:58:51.915] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//defaultMaskFile.dat
[13:58:51.915] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters_C15.dat
[13:58:51.969] <TB2> INFO: clk: 4
[13:58:51.969] <TB2> INFO: ctr: 4
[13:58:51.969] <TB2> INFO: sda: 19
[13:58:51.969] <TB2> INFO: tin: 9
[13:58:51.969] <TB2> INFO: level: 15
[13:58:51.969] <TB2> INFO: triggerdelay: 0
[13:58:51.969] <TB2> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[13:58:51.969] <TB2> INFO: Log level: INFO
[13:58:51.977] <TB2> INFO: Found DTB DTB_WXC55Z
[13:58:51.989] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[13:58:51.991] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
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[13:58:51.992] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[13:58:53.533] <TB2> INFO: DUT info:
[13:58:53.533] <TB2> INFO: The DUT currently contains the following objects:
[13:58:53.533] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[13:58:53.533] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:58:53.533] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:58:53.533] <TB2> INFO: TBM Core alpha (2): 7 registers set
[13:58:53.533] <TB2> INFO: TBM Core beta (3): 7 registers set
[13:58:53.533] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[13:58:53.533] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.533] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:53.934] <TB2> INFO: enter 'restricted' command line mode
[13:58:53.934] <TB2> INFO: enter test to run
[13:58:53.934] <TB2> INFO: test: pretest no parameter change
[13:58:53.934] <TB2> INFO: running: pretest
[13:58:54.504] <TB2> INFO: ######################################################################
[13:58:54.504] <TB2> INFO: PixTestPretest::doTest()
[13:58:54.504] <TB2> INFO: ######################################################################
[13:58:54.505] <TB2> INFO: ----------------------------------------------------------------------
[13:58:54.505] <TB2> INFO: PixTestPretest::programROC()
[13:58:54.505] <TB2> INFO: ----------------------------------------------------------------------
[13:59:12.518] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:59:12.518] <TB2> INFO: IA differences per ROC: 18.5 17.7 18.5 17.7 17.7 20.1 17.7 20.1 16.9 17.7 17.7 17.7 20.9 18.5 18.5 20.1
[13:59:12.552] <TB2> INFO: ----------------------------------------------------------------------
[13:59:12.552] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:59:12.552] <TB2> INFO: ----------------------------------------------------------------------
[13:59:33.798] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 388.3 mA = 24.2687 mA/ROC
[13:59:33.798] <TB2> INFO: i(loss) [mA/ROC]: 20.1 20.1 20.1 19.3 19.3 19.3 18.5 18.5 19.3 19.3 18.5 18.5 18.5 17.7 20.1 18.5
[13:59:33.826] <TB2> INFO: ----------------------------------------------------------------------
[13:59:33.826] <TB2> INFO: PixTestPretest::findTiming()
[13:59:33.826] <TB2> INFO: ----------------------------------------------------------------------
[13:59:33.826] <TB2> INFO: PixTestCmd::init()

[14:00:05.211] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[14:00:05.211] <TB2> INFO: (success/tries = 100/100), width = 3
[14:00:06.714] <TB2> INFO: ----------------------------------------------------------------------
[14:00:06.714] <TB2> INFO: PixTestPretest::findWorkingPixel()
[14:00:06.714] <TB2> INFO: ----------------------------------------------------------------------
[14:00:06.806] <TB2> INFO: Expecting 231680 events.
[14:00:16.497] <TB2> INFO: 231680 events read in total (9099ms).
[14:00:16.504] <TB2> INFO: Test took 9787ms.
[14:00:16.749] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[14:00:16.777] <TB2> INFO: ----------------------------------------------------------------------
[14:00:16.778] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[14:00:16.778] <TB2> INFO: ----------------------------------------------------------------------
[14:00:16.869] <TB2> INFO: Expecting 231680 events.
[14:00:26.584] <TB2> INFO: 231680 events read in total (9123ms).
[14:00:26.593] <TB2> INFO: Test took 9812ms.
[14:00:26.852] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[14:00:26.852] <TB2> INFO: CalDel: 107 109 90 79 104 100 92 94 95 87 106 118 87 90 105 100
[14:00:26.852] <TB2> INFO: VthrComp: 54 51 51 52 59 51 51 51 53 51 51 51 51 54 53 55
[14:00:26.854] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C0.dat
[14:00:26.855] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C1.dat
[14:00:26.855] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C2.dat
[14:00:26.855] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C3.dat
[14:00:26.855] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C4.dat
[14:00:26.855] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C5.dat
[14:00:26.855] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C6.dat
[14:00:26.855] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C7.dat
[14:00:26.855] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C8.dat
[14:00:26.855] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C9.dat
[14:00:26.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C10.dat
[14:00:26.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C11.dat
[14:00:26.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C12.dat
[14:00:26.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C13.dat
[14:00:26.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C14.dat
[14:00:26.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C15.dat
[14:00:26.856] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[14:00:26.856] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[14:00:26.856] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[14:00:26.856] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[14:00:26.857] <TB2> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[14:00:26.954] <TB2> INFO: enter test to run
[14:00:26.954] <TB2> INFO: test: fulltest no parameter change
[14:00:26.954] <TB2> INFO: running: fulltest
[14:00:26.954] <TB2> INFO: ######################################################################
[14:00:26.954] <TB2> INFO: PixTestFullTest::doTest()
[14:00:26.954] <TB2> INFO: ######################################################################
[14:00:26.955] <TB2> INFO: ######################################################################
[14:00:26.955] <TB2> INFO: PixTestAlive::doTest()
[14:00:26.955] <TB2> INFO: ######################################################################
[14:00:26.956] <TB2> INFO: ----------------------------------------------------------------------
[14:00:26.956] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:00:26.956] <TB2> INFO: ----------------------------------------------------------------------
[14:00:27.189] <TB2> INFO: Expecting 41600 events.
[14:00:30.704] <TB2> INFO: 41600 events read in total (2923ms).
[14:00:30.704] <TB2> INFO: Test took 3746ms.
[14:00:30.930] <TB2> INFO: PixTestAlive::aliveTest() done
[14:00:30.930] <TB2> INFO: number of dead pixels (per ROC): 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
[14:00:30.932] <TB2> INFO: ----------------------------------------------------------------------
[14:00:30.932] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:00:30.932] <TB2> INFO: ----------------------------------------------------------------------
[14:00:31.166] <TB2> INFO: Expecting 41600 events.
[14:00:34.145] <TB2> INFO: 41600 events read in total (2388ms).
[14:00:34.145] <TB2> INFO: Test took 3211ms.
[14:00:34.146] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[14:00:34.385] <TB2> INFO: PixTestAlive::maskTest() done
[14:00:34.385] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:00:34.387] <TB2> INFO: ----------------------------------------------------------------------
[14:00:34.387] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:00:34.387] <TB2> INFO: ----------------------------------------------------------------------
[14:00:34.619] <TB2> INFO: Expecting 41600 events.
[14:00:38.078] <TB2> INFO: 41600 events read in total (2867ms).
[14:00:38.078] <TB2> INFO: Test took 3690ms.
[14:00:38.306] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[14:00:38.306] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:00:38.306] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[14:00:38.306] <TB2> INFO: Decoding statistics:
[14:00:38.306] <TB2> INFO: General information:
[14:00:38.306] <TB2> INFO: 16bit words read: 0
[14:00:38.306] <TB2> INFO: valid events total: 0
[14:00:38.306] <TB2> INFO: empty events: 0
[14:00:38.306] <TB2> INFO: valid events with pixels: 0
[14:00:38.306] <TB2> INFO: valid pixel hits: 0
[14:00:38.306] <TB2> INFO: Event errors: 0
[14:00:38.306] <TB2> INFO: start marker: 0
[14:00:38.306] <TB2> INFO: stop marker: 0
[14:00:38.306] <TB2> INFO: overflow: 0
[14:00:38.306] <TB2> INFO: invalid 5bit words: 0
[14:00:38.306] <TB2> INFO: invalid XOR eye diagram: 0
[14:00:38.306] <TB2> INFO: frame (failed synchr.): 0
[14:00:38.306] <TB2> INFO: idle data (no TBM trl): 0
[14:00:38.306] <TB2> INFO: no data (only TBM hdr): 0
[14:00:38.306] <TB2> INFO: TBM errors: 0
[14:00:38.306] <TB2> INFO: flawed TBM headers: 0
[14:00:38.306] <TB2> INFO: flawed TBM trailers: 0
[14:00:38.306] <TB2> INFO: event ID mismatches: 0
[14:00:38.306] <TB2> INFO: ROC errors: 0
[14:00:38.306] <TB2> INFO: missing ROC header(s): 0
[14:00:38.306] <TB2> INFO: misplaced readback start: 0
[14:00:38.306] <TB2> INFO: Pixel decoding errors: 0
[14:00:38.306] <TB2> INFO: pixel data incomplete: 0
[14:00:38.306] <TB2> INFO: pixel address: 0
[14:00:38.306] <TB2> INFO: pulse height fill bit: 0
[14:00:38.306] <TB2> INFO: buffer corruption: 0
[14:00:38.313] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C15.dat
[14:00:38.314] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[14:00:38.314] <TB2> INFO: ######################################################################
[14:00:38.314] <TB2> INFO: PixTestReadback::doTest()
[14:00:38.314] <TB2> INFO: ######################################################################
[14:00:38.314] <TB2> INFO: ----------------------------------------------------------------------
[14:00:38.314] <TB2> INFO: PixTestReadback::CalibrateVd()
[14:00:38.314] <TB2> INFO: ----------------------------------------------------------------------
[14:00:48.281] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C0.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C1.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C2.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C3.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C4.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C5.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C6.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C7.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C8.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C9.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C10.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C11.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C12.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C13.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C14.dat
[14:00:48.282] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C15.dat
[14:00:48.310] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:00:48.310] <TB2> INFO: ----------------------------------------------------------------------
[14:00:48.310] <TB2> INFO: PixTestReadback::CalibrateVa()
[14:00:48.310] <TB2> INFO: ----------------------------------------------------------------------
[14:00:58.197] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C0.dat
[14:00:58.197] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C1.dat
[14:00:58.197] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C2.dat
[14:00:58.197] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C3.dat
[14:00:58.197] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C4.dat
[14:00:58.197] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C5.dat
[14:00:58.197] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C6.dat
[14:00:58.197] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C7.dat
[14:00:58.197] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C8.dat
[14:00:58.197] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C9.dat
[14:00:58.198] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C10.dat
[14:00:58.198] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C11.dat
[14:00:58.198] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C12.dat
[14:00:58.198] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C13.dat
[14:00:58.198] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C14.dat
[14:00:58.198] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C15.dat
[14:00:58.227] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:00:58.227] <TB2> INFO: ----------------------------------------------------------------------
[14:00:58.227] <TB2> INFO: PixTestReadback::readbackVbg()
[14:00:58.227] <TB2> INFO: ----------------------------------------------------------------------
[14:01:05.867] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:01:05.867] <TB2> INFO: ----------------------------------------------------------------------
[14:01:05.867] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[14:01:05.867] <TB2> INFO: ----------------------------------------------------------------------
[14:01:05.868] <TB2> INFO: Vbg will be calibrated using Vd calibration
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 160.8calibrated Vbg = 1.18181 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 155calibrated Vbg = 1.17257 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 157.9calibrated Vbg = 1.17125 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 153.7calibrated Vbg = 1.16905 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 160.3calibrated Vbg = 1.17538 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 152calibrated Vbg = 1.17172 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 159.9calibrated Vbg = 1.17548 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 153.9calibrated Vbg = 1.18498 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 159calibrated Vbg = 1.17457 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154calibrated Vbg = 1.1651 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 158.8calibrated Vbg = 1.16745 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 159calibrated Vbg = 1.16041 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 154.8calibrated Vbg = 1.16911 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 157.1calibrated Vbg = 1.17588 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 138.2calibrated Vbg = 1.17042 :::*/*/*/*/
[14:01:05.868] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 159.1calibrated Vbg = 1.17478 :::*/*/*/*/
[14:01:05.869] <TB2> INFO: ----------------------------------------------------------------------
[14:01:05.869] <TB2> INFO: PixTestReadback::CalibrateIa()
[14:01:05.869] <TB2> INFO: ----------------------------------------------------------------------
[14:03:46.174] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C0.dat
[14:03:46.174] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C1.dat
[14:03:46.174] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C2.dat
[14:03:46.174] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C3.dat
[14:03:46.174] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C4.dat
[14:03:46.174] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C5.dat
[14:03:46.174] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C6.dat
[14:03:46.174] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C7.dat
[14:03:46.175] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C8.dat
[14:03:46.175] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C9.dat
[14:03:46.175] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C10.dat
[14:03:46.175] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C11.dat
[14:03:46.175] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C12.dat
[14:03:46.175] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C13.dat
[14:03:46.175] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C14.dat
[14:03:46.175] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C15.dat
[14:03:46.201] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:03:46.202] <TB2> INFO: PixTestReadback::doTest() done
[14:03:46.203] <TB2> INFO: Decoding statistics:
[14:03:46.203] <TB2> INFO: General information:
[14:03:46.203] <TB2> INFO: 16bit words read: 1536
[14:03:46.203] <TB2> INFO: valid events total: 256
[14:03:46.203] <TB2> INFO: empty events: 256
[14:03:46.203] <TB2> INFO: valid events with pixels: 0
[14:03:46.203] <TB2> INFO: valid pixel hits: 0
[14:03:46.203] <TB2> INFO: Event errors: 0
[14:03:46.203] <TB2> INFO: start marker: 0
[14:03:46.203] <TB2> INFO: stop marker: 0
[14:03:46.203] <TB2> INFO: overflow: 0
[14:03:46.203] <TB2> INFO: invalid 5bit words: 0
[14:03:46.203] <TB2> INFO: invalid XOR eye diagram: 0
[14:03:46.203] <TB2> INFO: frame (failed synchr.): 0
[14:03:46.203] <TB2> INFO: idle data (no TBM trl): 0
[14:03:46.203] <TB2> INFO: no data (only TBM hdr): 0
[14:03:46.203] <TB2> INFO: TBM errors: 0
[14:03:46.203] <TB2> INFO: flawed TBM headers: 0
[14:03:46.203] <TB2> INFO: flawed TBM trailers: 0
[14:03:46.203] <TB2> INFO: event ID mismatches: 0
[14:03:46.203] <TB2> INFO: ROC errors: 0
[14:03:46.203] <TB2> INFO: missing ROC header(s): 0
[14:03:46.203] <TB2> INFO: misplaced readback start: 0
[14:03:46.203] <TB2> INFO: Pixel decoding errors: 0
[14:03:46.203] <TB2> INFO: pixel data incomplete: 0
[14:03:46.203] <TB2> INFO: pixel address: 0
[14:03:46.203] <TB2> INFO: pulse height fill bit: 0
[14:03:46.203] <TB2> INFO: buffer corruption: 0
[14:03:46.237] <TB2> INFO: ######################################################################
[14:03:46.237] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[14:03:46.237] <TB2> INFO: ######################################################################
[14:03:46.239] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[14:03:46.251] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:03:46.251] <TB2> INFO: run 1 of 1
[14:03:46.483] <TB2> INFO: Expecting 3120000 events.
[14:04:17.134] <TB2> INFO: 666370 events read in total (30059ms).











[14:04:47.100] <TB2> INFO: 1326765 events read in total (60025ms).











[14:05:16.598] <TB2> INFO: 1983715 events read in total (89524ms).











[14:05:46.132] <TB2> INFO: 2639270 events read in total (119057ms).











[14:06:08.090] <TB2> INFO: 3120000 events read in total (141015ms).
[14:06:08.145] <TB2> INFO: Test took 141895ms.
[14:06:33.140] <TB2> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 166 seconds
[14:06:33.140] <TB2> INFO: number of dead bumps (per ROC): 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
[14:06:33.140] <TB2> INFO: separation cut (per ROC): 107 104 104 111 127 109 103 100 108 101 102 99 110 106 103 105
[14:06:33.140] <TB2> INFO: Decoding statistics:
[14:06:33.140] <TB2> INFO: General information:
[14:06:33.140] <TB2> INFO: 16bit words read: 0
[14:06:33.140] <TB2> INFO: valid events total: 0
[14:06:33.140] <TB2> INFO: empty events: 0
[14:06:33.140] <TB2> INFO: valid events with pixels: 0
[14:06:33.140] <TB2> INFO: valid pixel hits: 0
[14:06:33.140] <TB2> INFO: Event errors: 0
[14:06:33.140] <TB2> INFO: start marker: 0
[14:06:33.140] <TB2> INFO: stop marker: 0
[14:06:33.140] <TB2> INFO: overflow: 0
[14:06:33.140] <TB2> INFO: invalid 5bit words: 0
[14:06:33.140] <TB2> INFO: invalid XOR eye diagram: 0
[14:06:33.140] <TB2> INFO: frame (failed synchr.): 0
[14:06:33.140] <TB2> INFO: idle data (no TBM trl): 0
[14:06:33.140] <TB2> INFO: no data (only TBM hdr): 0
[14:06:33.140] <TB2> INFO: TBM errors: 0
[14:06:33.140] <TB2> INFO: flawed TBM headers: 0
[14:06:33.140] <TB2> INFO: flawed TBM trailers: 0
[14:06:33.140] <TB2> INFO: event ID mismatches: 0
[14:06:33.140] <TB2> INFO: ROC errors: 0
[14:06:33.140] <TB2> INFO: missing ROC header(s): 0
[14:06:33.140] <TB2> INFO: misplaced readback start: 0
[14:06:33.140] <TB2> INFO: Pixel decoding errors: 0
[14:06:33.140] <TB2> INFO: pixel data incomplete: 0
[14:06:33.140] <TB2> INFO: pixel address: 0
[14:06:33.140] <TB2> INFO: pulse height fill bit: 0
[14:06:33.140] <TB2> INFO: buffer corruption: 0
[14:06:33.177] <TB2> INFO: ######################################################################
[14:06:33.177] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:06:33.177] <TB2> INFO: ######################################################################
[14:06:33.177] <TB2> INFO: ----------------------------------------------------------------------
[14:06:33.177] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:06:33.177] <TB2> INFO: ----------------------------------------------------------------------
[14:06:33.177] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[14:06:33.187] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[14:06:33.187] <TB2> INFO: run 1 of 1
[14:06:33.419] <TB2> INFO: Expecting 36608000 events.
[14:06:57.184] <TB2> INFO: 691050 events read in total (23174ms).
[14:07:20.062] <TB2> INFO: 1371350 events read in total (46052ms).
[14:07:42.553] <TB2> INFO: 2047350 events read in total (68543ms).
[14:08:05.280] <TB2> INFO: 2725050 events read in total (91270ms).
[14:08:28.165] <TB2> INFO: 3399050 events read in total (114155ms).
[14:08:50.894] <TB2> INFO: 4073700 events read in total (136884ms).
[14:09:13.866] <TB2> INFO: 4749050 events read in total (159856ms).
[14:09:36.366] <TB2> INFO: 5423800 events read in total (182356ms).
[14:09:59.033] <TB2> INFO: 6097050 events read in total (205023ms).
[14:10:21.755] <TB2> INFO: 6772700 events read in total (227745ms).
[14:10:44.395] <TB2> INFO: 7449100 events read in total (250385ms).
[14:11:07.381] <TB2> INFO: 8126550 events read in total (273371ms).
[14:11:30.276] <TB2> INFO: 8802800 events read in total (296266ms).
[14:11:53.294] <TB2> INFO: 9479600 events read in total (319284ms).
[14:12:15.845] <TB2> INFO: 10155700 events read in total (341835ms).
[14:12:38.858] <TB2> INFO: 10830600 events read in total (364848ms).
[14:13:01.768] <TB2> INFO: 11506150 events read in total (387758ms).
[14:13:24.524] <TB2> INFO: 12179050 events read in total (410514ms).
[14:13:47.114] <TB2> INFO: 12854200 events read in total (433104ms).
[14:14:09.736] <TB2> INFO: 13527800 events read in total (455726ms).
[14:14:32.564] <TB2> INFO: 14202900 events read in total (478554ms).
[14:14:55.369] <TB2> INFO: 14873600 events read in total (501359ms).
[14:15:17.915] <TB2> INFO: 15546500 events read in total (523905ms).
[14:15:40.736] <TB2> INFO: 16217250 events read in total (546726ms).
[14:16:03.492] <TB2> INFO: 16890900 events read in total (569482ms).
[14:16:26.191] <TB2> INFO: 17561250 events read in total (592181ms).
[14:16:49.059] <TB2> INFO: 18232150 events read in total (615049ms).
[14:17:11.534] <TB2> INFO: 18901000 events read in total (637524ms).
[14:17:34.130] <TB2> INFO: 19570050 events read in total (660120ms).
[14:17:56.465] <TB2> INFO: 20235800 events read in total (682455ms).
[14:18:19.240] <TB2> INFO: 20904200 events read in total (705230ms).
[14:18:41.749] <TB2> INFO: 21570750 events read in total (727739ms).
[14:19:04.793] <TB2> INFO: 22238200 events read in total (750784ms).
[14:19:27.310] <TB2> INFO: 22906050 events read in total (773301ms).
[14:19:49.918] <TB2> INFO: 23574400 events read in total (795908ms).
[14:20:12.330] <TB2> INFO: 24244600 events read in total (818320ms).
[14:20:34.972] <TB2> INFO: 24913600 events read in total (840962ms).
[14:20:57.887] <TB2> INFO: 25583000 events read in total (863877ms).
[14:21:20.349] <TB2> INFO: 26249600 events read in total (886339ms).
[14:21:42.832] <TB2> INFO: 26917100 events read in total (908822ms).
[14:22:05.304] <TB2> INFO: 27582150 events read in total (931295ms).
[14:22:27.645] <TB2> INFO: 28246850 events read in total (953635ms).
[14:22:50.509] <TB2> INFO: 28912300 events read in total (976499ms).
[14:23:13.386] <TB2> INFO: 29581500 events read in total (999376ms).
[14:23:35.956] <TB2> INFO: 30244300 events read in total (1021946ms).
[14:23:58.396] <TB2> INFO: 30910500 events read in total (1044386ms).
[14:24:20.874] <TB2> INFO: 31574650 events read in total (1066864ms).
[14:24:43.463] <TB2> INFO: 32242800 events read in total (1089453ms).
[14:25:06.224] <TB2> INFO: 32908250 events read in total (1112214ms).
[14:25:28.811] <TB2> INFO: 33575450 events read in total (1134801ms).
[14:25:51.589] <TB2> INFO: 34244150 events read in total (1157579ms).
[14:26:14.143] <TB2> INFO: 34911100 events read in total (1180133ms).
[14:26:36.722] <TB2> INFO: 35578800 events read in total (1202712ms).
[14:26:59.177] <TB2> INFO: 36254650 events read in total (1225167ms).
[14:27:10.994] <TB2> INFO: 36608000 events read in total (1236985ms).
[14:27:11.062] <TB2> INFO: Test took 1237875ms.
[14:27:11.463] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:13.452] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:15.347] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:17.241] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:19.160] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:20.994] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:22.951] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:24.412] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:25.876] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:27.314] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:28.744] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:30.190] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:31.606] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:33.014] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:34.439] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:35.901] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:27:37.712] <TB2> INFO: PixTestScurves::scurves() done
[14:27:37.712] <TB2> INFO: Vcal mean: 129.51 121.08 131.60 129.30 137.19 128.07 126.11 105.68 131.49 122.65 118.26 129.20 128.19 122.91 134.85 134.15
[14:27:37.712] <TB2> INFO: Vcal RMS: 8.19 5.90 6.39 6.21 6.54 5.91 5.76 5.26 6.14 5.76 6.20 5.97 6.17 5.77 6.39 6.35
[14:27:37.712] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1264 seconds
[14:27:37.712] <TB2> INFO: Decoding statistics:
[14:27:37.712] <TB2> INFO: General information:
[14:27:37.712] <TB2> INFO: 16bit words read: 0
[14:27:37.712] <TB2> INFO: valid events total: 0
[14:27:37.712] <TB2> INFO: empty events: 0
[14:27:37.712] <TB2> INFO: valid events with pixels: 0
[14:27:37.712] <TB2> INFO: valid pixel hits: 0
[14:27:37.713] <TB2> INFO: Event errors: 0
[14:27:37.713] <TB2> INFO: start marker: 0
[14:27:37.713] <TB2> INFO: stop marker: 0
[14:27:37.713] <TB2> INFO: overflow: 0
[14:27:37.713] <TB2> INFO: invalid 5bit words: 0
[14:27:37.713] <TB2> INFO: invalid XOR eye diagram: 0
[14:27:37.713] <TB2> INFO: frame (failed synchr.): 0
[14:27:37.713] <TB2> INFO: idle data (no TBM trl): 0
[14:27:37.713] <TB2> INFO: no data (only TBM hdr): 0
[14:27:37.713] <TB2> INFO: TBM errors: 0
[14:27:37.713] <TB2> INFO: flawed TBM headers: 0
[14:27:37.713] <TB2> INFO: flawed TBM trailers: 0
[14:27:37.713] <TB2> INFO: event ID mismatches: 0
[14:27:37.713] <TB2> INFO: ROC errors: 0
[14:27:37.713] <TB2> INFO: missing ROC header(s): 0
[14:27:37.713] <TB2> INFO: misplaced readback start: 0
[14:27:37.713] <TB2> INFO: Pixel decoding errors: 0
[14:27:37.713] <TB2> INFO: pixel data incomplete: 0
[14:27:37.713] <TB2> INFO: pixel address: 0
[14:27:37.713] <TB2> INFO: pulse height fill bit: 0
[14:27:37.713] <TB2> INFO: buffer corruption: 0
[14:27:37.783] <TB2> INFO: ######################################################################
[14:27:37.783] <TB2> INFO: PixTestTrim::doTest()
[14:27:37.783] <TB2> INFO: ######################################################################
[14:27:37.784] <TB2> INFO: ----------------------------------------------------------------------
[14:27:37.784] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[14:27:37.784] <TB2> INFO: ----------------------------------------------------------------------
[14:27:37.825] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:27:37.825] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:27:37.835] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:27:37.835] <TB2> INFO: run 1 of 1
[14:27:38.088] <TB2> INFO: Expecting 5025280 events.
[14:28:08.340] <TB2> INFO: 831448 events read in total (29660ms).
[14:28:38.336] <TB2> INFO: 1661384 events read in total (59656ms).
[14:29:08.176] <TB2> INFO: 2488616 events read in total (89497ms).
[14:29:37.896] <TB2> INFO: 3313176 events read in total (119216ms).
[14:30:07.531] <TB2> INFO: 4133512 events read in total (148851ms).
[14:30:36.002] <TB2> INFO: 4952520 events read in total (178322ms).
[14:30:40.018] <TB2> INFO: 5025280 events read in total (181338ms).
[14:30:40.058] <TB2> INFO: Test took 182224ms.
[14:30:54.865] <TB2> INFO: ROC 0 VthrComp = 128
[14:30:54.865] <TB2> INFO: ROC 1 VthrComp = 126
[14:30:54.865] <TB2> INFO: ROC 2 VthrComp = 131
[14:30:54.865] <TB2> INFO: ROC 3 VthrComp = 132
[14:30:54.865] <TB2> INFO: ROC 4 VthrComp = 133
[14:30:54.865] <TB2> INFO: ROC 5 VthrComp = 132
[14:30:54.866] <TB2> INFO: ROC 6 VthrComp = 119
[14:30:54.866] <TB2> INFO: ROC 7 VthrComp = 106
[14:30:54.867] <TB2> INFO: ROC 8 VthrComp = 129
[14:30:54.867] <TB2> INFO: ROC 9 VthrComp = 123
[14:30:54.867] <TB2> INFO: ROC 10 VthrComp = 117
[14:30:54.868] <TB2> INFO: ROC 11 VthrComp = 115
[14:30:54.868] <TB2> INFO: ROC 12 VthrComp = 130
[14:30:54.868] <TB2> INFO: ROC 13 VthrComp = 118
[14:30:54.868] <TB2> INFO: ROC 14 VthrComp = 129
[14:30:54.868] <TB2> INFO: ROC 15 VthrComp = 132
[14:30:55.135] <TB2> INFO: Expecting 41600 events.
[14:30:58.817] <TB2> INFO: 41600 events read in total (3090ms).
[14:30:58.818] <TB2> INFO: Test took 3948ms.
[14:30:58.826] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:30:58.826] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:30:58.835] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:30:58.835] <TB2> INFO: run 1 of 1
[14:30:59.113] <TB2> INFO: Expecting 5025280 events.
[14:31:25.176] <TB2> INFO: 592640 events read in total (25471ms).
[14:31:50.857] <TB2> INFO: 1184096 events read in total (51152ms).
[14:32:16.060] <TB2> INFO: 1775792 events read in total (76355ms).
[14:32:41.683] <TB2> INFO: 2366848 events read in total (101978ms).
[14:33:06.779] <TB2> INFO: 2955424 events read in total (127074ms).
[14:33:31.728] <TB2> INFO: 3542064 events read in total (152023ms).
[14:33:57.203] <TB2> INFO: 4127760 events read in total (177498ms).
[14:34:22.573] <TB2> INFO: 4713296 events read in total (202868ms).
[14:34:35.931] <TB2> INFO: 5025280 events read in total (216226ms).
[14:34:36.004] <TB2> INFO: Test took 217169ms.
[14:35:02.317] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 62.9892 for pixel 8/2 mean/min/max = 46.7266/30.1494/63.3037
[14:35:02.317] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 59.648 for pixel 13/19 mean/min/max = 45.9083/32.1051/59.7116
[14:35:02.317] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 62.7913 for pixel 2/6 mean/min/max = 47.6393/32.4576/62.8211
[14:35:02.318] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.9922 for pixel 15/74 mean/min/max = 46.5519/31.9423/61.1616
[14:35:02.318] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 68.9539 for pixel 1/9 mean/min/max = 51.1499/33.2762/69.0237
[14:35:02.319] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 59.7321 for pixel 0/26 mean/min/max = 46.0279/32.2673/59.7886
[14:35:02.319] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 65.0243 for pixel 25/18 mean/min/max = 47.9444/30.361/65.5278
[14:35:02.319] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 60.6366 for pixel 0/19 mean/min/max = 48.0108/35.3223/60.6993
[14:35:02.320] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 63.0752 for pixel 9/13 mean/min/max = 46.7359/30.2949/63.1769
[14:35:02.320] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 60.2553 for pixel 3/18 mean/min/max = 46.1595/32.0319/60.2871
[14:35:02.320] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 60.9971 for pixel 9/4 mean/min/max = 46.5846/32.1512/61.0181
[14:35:02.321] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 66.0693 for pixel 23/2 mean/min/max = 48.4868/30.8829/66.0907
[14:35:02.321] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 59.6492 for pixel 18/10 mean/min/max = 45.7422/31.5575/59.9269
[14:35:02.321] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 65.1149 for pixel 48/9 mean/min/max = 48.2487/31.3707/65.1268
[14:35:02.322] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 66.5118 for pixel 51/4 mean/min/max = 49.5086/32.2183/66.7989
[14:35:02.322] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 66.5022 for pixel 0/8 mean/min/max = 50.3309/34.0741/66.5876
[14:35:02.322] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:35:02.411] <TB2> INFO: Expecting 411648 events.
[14:35:11.563] <TB2> INFO: 411648 events read in total (8561ms).
[14:35:11.571] <TB2> INFO: Expecting 411648 events.
[14:35:20.582] <TB2> INFO: 411648 events read in total (8608ms).
[14:35:20.592] <TB2> INFO: Expecting 411648 events.
[14:35:29.592] <TB2> INFO: 411648 events read in total (8597ms).
[14:35:29.604] <TB2> INFO: Expecting 411648 events.
[14:35:38.671] <TB2> INFO: 411648 events read in total (8664ms).
[14:35:38.685] <TB2> INFO: Expecting 411648 events.
[14:35:47.723] <TB2> INFO: 411648 events read in total (8635ms).
[14:35:47.740] <TB2> INFO: Expecting 411648 events.
[14:35:56.731] <TB2> INFO: 411648 events read in total (8588ms).
[14:35:56.752] <TB2> INFO: Expecting 411648 events.
[14:36:05.837] <TB2> INFO: 411648 events read in total (8682ms).
[14:36:05.859] <TB2> INFO: Expecting 411648 events.
[14:36:14.856] <TB2> INFO: 411648 events read in total (8594ms).
[14:36:14.879] <TB2> INFO: Expecting 411648 events.
[14:36:23.930] <TB2> INFO: 411648 events read in total (8648ms).
[14:36:23.956] <TB2> INFO: Expecting 411648 events.
[14:36:33.034] <TB2> INFO: 411648 events read in total (8675ms).
[14:36:33.064] <TB2> INFO: Expecting 411648 events.
[14:36:42.015] <TB2> INFO: 411648 events read in total (8549ms).
[14:36:42.046] <TB2> INFO: Expecting 411648 events.
[14:36:51.095] <TB2> INFO: 411648 events read in total (8646ms).
[14:36:51.138] <TB2> INFO: Expecting 411648 events.
[14:37:00.191] <TB2> INFO: 411648 events read in total (8650ms).
[14:37:00.239] <TB2> INFO: Expecting 411648 events.
[14:37:09.337] <TB2> INFO: 411648 events read in total (8695ms).
[14:37:09.378] <TB2> INFO: Expecting 411648 events.
[14:37:18.511] <TB2> INFO: 411648 events read in total (8730ms).
[14:37:18.556] <TB2> INFO: Expecting 411648 events.
[14:37:27.627] <TB2> INFO: 411648 events read in total (8668ms).
[14:37:27.673] <TB2> INFO: Test took 145351ms.
[14:37:28.384] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:37:28.394] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:37:28.394] <TB2> INFO: run 1 of 1
[14:37:28.640] <TB2> INFO: Expecting 5025280 events.
[14:37:55.013] <TB2> INFO: 599632 events read in total (25781ms).
[14:38:20.600] <TB2> INFO: 1198216 events read in total (51368ms).
[14:38:46.281] <TB2> INFO: 1794936 events read in total (77049ms).
[14:39:11.794] <TB2> INFO: 2390016 events read in total (102562ms).
[14:39:37.576] <TB2> INFO: 2985624 events read in total (128344ms).
[14:40:03.279] <TB2> INFO: 3582832 events read in total (154047ms).
[14:40:29.199] <TB2> INFO: 4181968 events read in total (179967ms).
[14:40:55.207] <TB2> INFO: 4781728 events read in total (205975ms).
[14:41:05.984] <TB2> INFO: 5025280 events read in total (216752ms).
[14:41:06.109] <TB2> INFO: Test took 217715ms.
[14:41:27.841] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 3.521463 .. 147.464889
[14:41:28.120] <TB2> INFO: Expecting 208000 events.
[14:41:37.549] <TB2> INFO: 208000 events read in total (8837ms).
[14:41:37.550] <TB2> INFO: Test took 9707ms.
[14:41:37.603] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 3 .. 157 (-1/-1) hits flags = 528 (plus default)
[14:41:37.614] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:41:37.614] <TB2> INFO: run 1 of 1
[14:41:37.891] <TB2> INFO: Expecting 5158400 events.
[14:42:03.821] <TB2> INFO: 583328 events read in total (25338ms).
[14:42:29.197] <TB2> INFO: 1166408 events read in total (50715ms).
[14:42:54.356] <TB2> INFO: 1748656 events read in total (75874ms).
[14:43:19.630] <TB2> INFO: 2331096 events read in total (101147ms).
[14:43:44.725] <TB2> INFO: 2914104 events read in total (126242ms).
[14:44:09.793] <TB2> INFO: 3496024 events read in total (151310ms).
[14:44:35.155] <TB2> INFO: 4077328 events read in total (176672ms).
[14:45:01.184] <TB2> INFO: 4658232 events read in total (202701ms).
[14:45:22.981] <TB2> INFO: 5158400 events read in total (224498ms).
[14:45:23.087] <TB2> INFO: Test took 225473ms.
[14:45:48.623] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.470166 .. 47.350444
[14:45:48.879] <TB2> INFO: Expecting 208000 events.
[14:45:58.572] <TB2> INFO: 208000 events read in total (9101ms).
[14:45:58.573] <TB2> INFO: Test took 9949ms.
[14:45:58.640] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 57 (-1/-1) hits flags = 528 (plus default)
[14:45:58.651] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:45:58.651] <TB2> INFO: run 1 of 1
[14:45:58.929] <TB2> INFO: Expecting 1364480 events.
[14:46:27.117] <TB2> INFO: 661160 events read in total (27596ms).
[14:46:54.048] <TB2> INFO: 1316872 events read in total (54528ms).
[14:46:56.355] <TB2> INFO: 1364480 events read in total (56834ms).
[14:46:56.381] <TB2> INFO: Test took 57730ms.
[14:47:10.148] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 28.263111 .. 50.620156
[14:47:10.383] <TB2> INFO: Expecting 208000 events.
[14:47:20.208] <TB2> INFO: 208000 events read in total (9234ms).
[14:47:20.209] <TB2> INFO: Test took 10059ms.
[14:47:20.255] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 18 .. 60 (-1/-1) hits flags = 528 (plus default)
[14:47:20.266] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:47:20.266] <TB2> INFO: run 1 of 1
[14:47:20.544] <TB2> INFO: Expecting 1431040 events.
[14:47:47.002] <TB2> INFO: 642864 events read in total (26867ms).
[14:48:14.719] <TB2> INFO: 1283112 events read in total (53584ms).
[14:48:21.099] <TB2> INFO: 1431040 events read in total (59964ms).
[14:48:21.125] <TB2> INFO: Test took 60860ms.
[14:48:34.513] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 27.271792 .. 54.585830
[14:48:34.816] <TB2> INFO: Expecting 208000 events.
[14:48:44.580] <TB2> INFO: 208000 events read in total (9172ms).
[14:48:44.581] <TB2> INFO: Test took 10067ms.
[14:48:44.626] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 17 .. 64 (-1/-1) hits flags = 528 (plus default)
[14:48:44.635] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:48:44.635] <TB2> INFO: run 1 of 1
[14:48:44.938] <TB2> INFO: Expecting 1597440 events.
[14:49:12.306] <TB2> INFO: 632920 events read in total (26777ms).
[14:49:38.877] <TB2> INFO: 1264256 events read in total (53348ms).
[14:49:52.967] <TB2> INFO: 1597440 events read in total (67439ms).
[14:49:52.995] <TB2> INFO: Test took 68360ms.
[14:50:06.830] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:50:06.830] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:50:06.841] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:50:06.842] <TB2> INFO: run 1 of 1
[14:50:07.085] <TB2> INFO: Expecting 1364480 events.
[14:50:35.496] <TB2> INFO: 669776 events read in total (27820ms).
[14:51:02.813] <TB2> INFO: 1338280 events read in total (55137ms).
[14:51:04.327] <TB2> INFO: 1364480 events read in total (56652ms).
[14:51:04.356] <TB2> INFO: Test took 57514ms.
[14:51:16.627] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C0.dat
[14:51:16.627] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C1.dat
[14:51:16.627] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C2.dat
[14:51:16.627] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C3.dat
[14:51:16.627] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C4.dat
[14:51:16.627] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C5.dat
[14:51:16.627] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C6.dat
[14:51:16.627] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C7.dat
[14:51:16.627] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C8.dat
[14:51:16.627] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C9.dat
[14:51:16.627] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C10.dat
[14:51:16.628] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C11.dat
[14:51:16.628] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C12.dat
[14:51:16.628] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C13.dat
[14:51:16.628] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C14.dat
[14:51:16.628] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C15.dat
[14:51:16.628] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C0.dat
[14:51:16.634] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C1.dat
[14:51:16.639] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C2.dat
[14:51:16.644] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C3.dat
[14:51:16.650] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C4.dat
[14:51:16.655] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C5.dat
[14:51:16.661] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C6.dat
[14:51:16.666] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C7.dat
[14:51:16.671] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C8.dat
[14:51:16.677] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C9.dat
[14:51:16.682] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C10.dat
[14:51:16.688] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C11.dat
[14:51:16.693] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C12.dat
[14:51:16.698] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C13.dat
[14:51:16.704] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C14.dat
[14:51:16.709] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C15.dat
[14:51:16.715] <TB2> INFO: PixTestTrim::trimTest() done
[14:51:16.715] <TB2> INFO: vtrim: 151 140 155 131 154 128 144 117 146 134 123 147 134 140 138 139
[14:51:16.715] <TB2> INFO: vthrcomp: 128 126 131 132 133 132 119 106 129 123 117 115 130 118 129 132
[14:51:16.715] <TB2> INFO: vcal mean: 35.27 34.99 35.24 35.01 36.28 34.93 35.56 35.02 35.72 35.04 35.04 35.70 34.94 35.86 35.19 35.49
[14:51:16.715] <TB2> INFO: vcal RMS: 1.80 1.02 1.43 1.21 2.42 1.01 1.90 0.94 2.03 1.07 1.11 1.99 1.10 2.01 1.51 1.64
[14:51:16.715] <TB2> INFO: bits mean: 10.29 9.97 9.99 9.61 9.49 9.49 10.22 8.43 10.58 9.78 9.53 10.22 10.09 10.23 8.90 8.72
[14:51:16.715] <TB2> INFO: bits RMS: 2.50 2.46 2.38 2.63 2.57 2.71 2.57 2.52 2.43 2.55 2.62 2.44 2.46 2.48 2.79 2.65
[14:51:16.721] <TB2> INFO: ----------------------------------------------------------------------
[14:51:16.721] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:51:16.721] <TB2> INFO: ----------------------------------------------------------------------
[14:51:16.723] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:51:16.734] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:51:16.734] <TB2> INFO: run 1 of 1
[14:51:16.965] <TB2> INFO: Expecting 4160000 events.
[14:51:48.640] <TB2> INFO: 764180 events read in total (31083ms).
[14:52:19.986] <TB2> INFO: 1525910 events read in total (62429ms).
[14:52:51.348] <TB2> INFO: 2280880 events read in total (93791ms).
[14:53:22.649] <TB2> INFO: 3031645 events read in total (125092ms).
[14:53:54.063] <TB2> INFO: 3778725 events read in total (156507ms).
[14:54:10.305] <TB2> INFO: 4160000 events read in total (172748ms).
[14:54:10.355] <TB2> INFO: Test took 173621ms.
[14:54:41.403] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 231 (-1/-1) hits flags = 528 (plus default)
[14:54:41.412] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:54:41.412] <TB2> INFO: run 1 of 1
[14:54:41.676] <TB2> INFO: Expecting 4825600 events.
[14:55:12.433] <TB2> INFO: 700445 events read in total (30165ms).
[14:55:42.039] <TB2> INFO: 1398855 events read in total (59771ms).
[14:56:11.925] <TB2> INFO: 2094705 events read in total (89657ms).
[14:56:41.892] <TB2> INFO: 2787225 events read in total (119624ms).
[14:57:12.326] <TB2> INFO: 3477850 events read in total (150058ms).
[14:57:42.346] <TB2> INFO: 4166395 events read in total (180078ms).
[14:58:11.010] <TB2> INFO: 4825600 events read in total (208742ms).
[14:58:11.080] <TB2> INFO: Test took 209668ms.
[14:58:42.830] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 215 (-1/-1) hits flags = 528 (plus default)
[14:58:42.842] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:58:42.842] <TB2> INFO: run 1 of 1
[14:58:43.121] <TB2> INFO: Expecting 4492800 events.
[14:59:14.172] <TB2> INFO: 718005 events read in total (30460ms).
[14:59:44.313] <TB2> INFO: 1433120 events read in total (60601ms).
[15:00:14.518] <TB2> INFO: 2145040 events read in total (90806ms).
[15:00:44.592] <TB2> INFO: 2852245 events read in total (120880ms).
[15:01:14.762] <TB2> INFO: 3558335 events read in total (151050ms).
[15:01:45.080] <TB2> INFO: 4263480 events read in total (181368ms).
[15:01:55.288] <TB2> INFO: 4492800 events read in total (191576ms).
[15:01:55.367] <TB2> INFO: Test took 192525ms.
[15:02:24.137] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 217 (-1/-1) hits flags = 528 (plus default)
[15:02:24.148] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:02:24.148] <TB2> INFO: run 1 of 1
[15:02:24.389] <TB2> INFO: Expecting 4534400 events.
[15:02:55.313] <TB2> INFO: 715985 events read in total (30333ms).
[15:03:25.690] <TB2> INFO: 1429415 events read in total (60710ms).
[15:03:56.199] <TB2> INFO: 2139370 events read in total (91219ms).
[15:04:26.700] <TB2> INFO: 2844580 events read in total (121720ms).
[15:04:56.901] <TB2> INFO: 3548390 events read in total (151921ms).
[15:05:27.861] <TB2> INFO: 4251340 events read in total (182881ms).
[15:05:40.039] <TB2> INFO: 4534400 events read in total (195059ms).
[15:05:40.109] <TB2> INFO: Test took 195961ms.
[15:06:08.294] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 216 (-1/-1) hits flags = 528 (plus default)
[15:06:08.305] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:06:08.305] <TB2> INFO: run 1 of 1
[15:06:08.563] <TB2> INFO: Expecting 4513600 events.
[15:06:39.572] <TB2> INFO: 717135 events read in total (30418ms).
[15:07:10.242] <TB2> INFO: 1431805 events read in total (61088ms).
[15:07:40.601] <TB2> INFO: 2142645 events read in total (91447ms).
[15:08:10.873] <TB2> INFO: 2848965 events read in total (121719ms).
[15:08:41.464] <TB2> INFO: 3554045 events read in total (152310ms).
[15:09:12.024] <TB2> INFO: 4258105 events read in total (182870ms).
[15:09:23.056] <TB2> INFO: 4513600 events read in total (193902ms).
[15:09:23.113] <TB2> INFO: Test took 194808ms.
[15:09:52.634] <TB2> INFO: PixTestTrim::trimBitTest() done
[15:09:52.635] <TB2> INFO: PixTestTrim::doTest() done, duration: 2534 seconds
[15:09:52.635] <TB2> INFO: Decoding statistics:
[15:09:52.635] <TB2> INFO: General information:
[15:09:52.635] <TB2> INFO: 16bit words read: 0
[15:09:52.635] <TB2> INFO: valid events total: 0
[15:09:52.635] <TB2> INFO: empty events: 0
[15:09:52.635] <TB2> INFO: valid events with pixels: 0
[15:09:52.635] <TB2> INFO: valid pixel hits: 0
[15:09:52.635] <TB2> INFO: Event errors: 0
[15:09:52.635] <TB2> INFO: start marker: 0
[15:09:52.635] <TB2> INFO: stop marker: 0
[15:09:52.635] <TB2> INFO: overflow: 0
[15:09:52.635] <TB2> INFO: invalid 5bit words: 0
[15:09:52.635] <TB2> INFO: invalid XOR eye diagram: 0
[15:09:52.635] <TB2> INFO: frame (failed synchr.): 0
[15:09:52.635] <TB2> INFO: idle data (no TBM trl): 0
[15:09:52.635] <TB2> INFO: no data (only TBM hdr): 0
[15:09:52.635] <TB2> INFO: TBM errors: 0
[15:09:52.636] <TB2> INFO: flawed TBM headers: 0
[15:09:52.636] <TB2> INFO: flawed TBM trailers: 0
[15:09:52.636] <TB2> INFO: event ID mismatches: 0
[15:09:52.636] <TB2> INFO: ROC errors: 0
[15:09:52.636] <TB2> INFO: missing ROC header(s): 0
[15:09:52.636] <TB2> INFO: misplaced readback start: 0
[15:09:52.636] <TB2> INFO: Pixel decoding errors: 0
[15:09:52.636] <TB2> INFO: pixel data incomplete: 0
[15:09:52.636] <TB2> INFO: pixel address: 0
[15:09:52.636] <TB2> INFO: pulse height fill bit: 0
[15:09:52.636] <TB2> INFO: buffer corruption: 0
[15:09:53.246] <TB2> INFO: ######################################################################
[15:09:53.246] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[15:09:53.246] <TB2> INFO: ######################################################################
[15:09:53.478] <TB2> INFO: Expecting 41600 events.
[15:09:56.969] <TB2> INFO: 41600 events read in total (2899ms).
[15:09:56.970] <TB2> INFO: Test took 3722ms.
[15:09:57.404] <TB2> INFO: Expecting 41600 events.
[15:10:00.933] <TB2> INFO: 41600 events read in total (2937ms).
[15:10:00.934] <TB2> INFO: Test took 3762ms.
[15:10:01.222] <TB2> INFO: Expecting 41600 events.
[15:10:04.761] <TB2> INFO: 41600 events read in total (2947ms).
[15:10:04.762] <TB2> INFO: Test took 3805ms.
[15:10:05.050] <TB2> INFO: Expecting 41600 events.
[15:10:08.486] <TB2> INFO: 41600 events read in total (2844ms).
[15:10:08.487] <TB2> INFO: Test took 3701ms.
[15:10:08.778] <TB2> INFO: Expecting 41600 events.
[15:10:12.304] <TB2> INFO: 41600 events read in total (2935ms).
[15:10:12.305] <TB2> INFO: Test took 3792ms.
[15:10:12.599] <TB2> INFO: Expecting 41600 events.
[15:10:16.127] <TB2> INFO: 41600 events read in total (2935ms).
[15:10:16.127] <TB2> INFO: Test took 3799ms.
[15:10:16.424] <TB2> INFO: Expecting 41600 events.
[15:10:19.936] <TB2> INFO: 41600 events read in total (2920ms).
[15:10:19.936] <TB2> INFO: Test took 3785ms.
[15:10:20.225] <TB2> INFO: Expecting 41600 events.
[15:10:23.667] <TB2> INFO: 41600 events read in total (2851ms).
[15:10:23.668] <TB2> INFO: Test took 3708ms.
[15:10:23.957] <TB2> INFO: Expecting 41600 events.
[15:10:27.486] <TB2> INFO: 41600 events read in total (2938ms).
[15:10:27.487] <TB2> INFO: Test took 3795ms.
[15:10:27.777] <TB2> INFO: Expecting 41600 events.
[15:10:31.433] <TB2> INFO: 41600 events read in total (3064ms).
[15:10:31.434] <TB2> INFO: Test took 3921ms.
[15:10:31.722] <TB2> INFO: Expecting 41600 events.
[15:10:35.249] <TB2> INFO: 41600 events read in total (2936ms).
[15:10:35.250] <TB2> INFO: Test took 3793ms.
[15:10:35.541] <TB2> INFO: Expecting 41600 events.
[15:10:38.977] <TB2> INFO: 41600 events read in total (2845ms).
[15:10:38.978] <TB2> INFO: Test took 3702ms.
[15:10:39.276] <TB2> INFO: Expecting 41600 events.
[15:10:42.770] <TB2> INFO: 41600 events read in total (2902ms).
[15:10:42.771] <TB2> INFO: Test took 3770ms.
[15:10:43.059] <TB2> INFO: Expecting 41600 events.
[15:10:46.575] <TB2> INFO: 41600 events read in total (2924ms).
[15:10:46.576] <TB2> INFO: Test took 3782ms.
[15:10:46.864] <TB2> INFO: Expecting 41600 events.
[15:10:50.456] <TB2> INFO: 41600 events read in total (3000ms).
[15:10:50.457] <TB2> INFO: Test took 3857ms.
[15:10:50.745] <TB2> INFO: Expecting 41600 events.
[15:10:54.188] <TB2> INFO: 41600 events read in total (2852ms).
[15:10:54.189] <TB2> INFO: Test took 3709ms.
[15:10:54.480] <TB2> INFO: Expecting 41600 events.
[15:10:57.968] <TB2> INFO: 41600 events read in total (2897ms).
[15:10:57.969] <TB2> INFO: Test took 3754ms.
[15:10:58.259] <TB2> INFO: Expecting 41600 events.
[15:11:01.745] <TB2> INFO: 41600 events read in total (2894ms).
[15:11:01.745] <TB2> INFO: Test took 3751ms.
[15:11:02.033] <TB2> INFO: Expecting 41600 events.
[15:11:05.572] <TB2> INFO: 41600 events read in total (2947ms).
[15:11:05.573] <TB2> INFO: Test took 3804ms.
[15:11:05.861] <TB2> INFO: Expecting 41600 events.
[15:11:09.379] <TB2> INFO: 41600 events read in total (2926ms).
[15:11:09.380] <TB2> INFO: Test took 3783ms.
[15:11:09.668] <TB2> INFO: Expecting 41600 events.
[15:11:13.173] <TB2> INFO: 41600 events read in total (2914ms).
[15:11:13.173] <TB2> INFO: Test took 3770ms.
[15:11:13.461] <TB2> INFO: Expecting 41600 events.
[15:11:17.065] <TB2> INFO: 41600 events read in total (3012ms).
[15:11:17.066] <TB2> INFO: Test took 3869ms.
[15:11:17.354] <TB2> INFO: Expecting 41600 events.
[15:11:20.872] <TB2> INFO: 41600 events read in total (2927ms).
[15:11:20.873] <TB2> INFO: Test took 3784ms.
[15:11:21.162] <TB2> INFO: Expecting 41600 events.
[15:11:24.700] <TB2> INFO: 41600 events read in total (2947ms).
[15:11:24.701] <TB2> INFO: Test took 3804ms.
[15:11:24.992] <TB2> INFO: Expecting 41600 events.
[15:11:28.441] <TB2> INFO: 41600 events read in total (2857ms).
[15:11:28.442] <TB2> INFO: Test took 3715ms.
[15:11:28.733] <TB2> INFO: Expecting 41600 events.
[15:11:32.267] <TB2> INFO: 41600 events read in total (2942ms).
[15:11:32.268] <TB2> INFO: Test took 3800ms.
[15:11:32.556] <TB2> INFO: Expecting 41600 events.
[15:11:36.096] <TB2> INFO: 41600 events read in total (2948ms).
[15:11:36.096] <TB2> INFO: Test took 3804ms.
[15:11:36.385] <TB2> INFO: Expecting 41600 events.
[15:11:39.840] <TB2> INFO: 41600 events read in total (2864ms).
[15:11:39.841] <TB2> INFO: Test took 3721ms.
[15:11:40.129] <TB2> INFO: Expecting 41600 events.
[15:11:43.650] <TB2> INFO: 41600 events read in total (2930ms).
[15:11:43.651] <TB2> INFO: Test took 3787ms.
[15:11:43.941] <TB2> INFO: Expecting 41600 events.
[15:11:47.462] <TB2> INFO: 41600 events read in total (2930ms).
[15:11:47.463] <TB2> INFO: Test took 3787ms.
[15:11:47.751] <TB2> INFO: Expecting 2560 events.
[15:11:48.636] <TB2> INFO: 2560 events read in total (293ms).
[15:11:48.636] <TB2> INFO: Test took 1161ms.
[15:11:48.945] <TB2> INFO: Expecting 2560 events.
[15:11:49.826] <TB2> INFO: 2560 events read in total (290ms).
[15:11:49.826] <TB2> INFO: Test took 1189ms.
[15:11:50.135] <TB2> INFO: Expecting 2560 events.
[15:11:51.016] <TB2> INFO: 2560 events read in total (290ms).
[15:11:51.017] <TB2> INFO: Test took 1190ms.
[15:11:51.325] <TB2> INFO: Expecting 2560 events.
[15:11:52.207] <TB2> INFO: 2560 events read in total (291ms).
[15:11:52.207] <TB2> INFO: Test took 1190ms.
[15:11:52.515] <TB2> INFO: Expecting 2560 events.
[15:11:53.393] <TB2> INFO: 2560 events read in total (286ms).
[15:11:53.393] <TB2> INFO: Test took 1185ms.
[15:11:53.701] <TB2> INFO: Expecting 2560 events.
[15:11:54.579] <TB2> INFO: 2560 events read in total (286ms).
[15:11:54.579] <TB2> INFO: Test took 1185ms.
[15:11:54.886] <TB2> INFO: Expecting 2560 events.
[15:11:55.764] <TB2> INFO: 2560 events read in total (286ms).
[15:11:55.765] <TB2> INFO: Test took 1186ms.
[15:11:56.072] <TB2> INFO: Expecting 2560 events.
[15:11:56.950] <TB2> INFO: 2560 events read in total (286ms).
[15:11:56.950] <TB2> INFO: Test took 1185ms.
[15:11:57.258] <TB2> INFO: Expecting 2560 events.
[15:11:58.139] <TB2> INFO: 2560 events read in total (290ms).
[15:11:58.139] <TB2> INFO: Test took 1188ms.
[15:11:58.447] <TB2> INFO: Expecting 2560 events.
[15:11:59.326] <TB2> INFO: 2560 events read in total (287ms).
[15:11:59.326] <TB2> INFO: Test took 1186ms.
[15:11:59.634] <TB2> INFO: Expecting 2560 events.
[15:12:00.515] <TB2> INFO: 2560 events read in total (289ms).
[15:12:00.515] <TB2> INFO: Test took 1189ms.
[15:12:00.823] <TB2> INFO: Expecting 2560 events.
[15:12:01.700] <TB2> INFO: 2560 events read in total (285ms).
[15:12:01.701] <TB2> INFO: Test took 1185ms.
[15:12:02.009] <TB2> INFO: Expecting 2560 events.
[15:12:02.893] <TB2> INFO: 2560 events read in total (293ms).
[15:12:02.893] <TB2> INFO: Test took 1192ms.
[15:12:03.201] <TB2> INFO: Expecting 2560 events.
[15:12:04.086] <TB2> INFO: 2560 events read in total (293ms).
[15:12:04.086] <TB2> INFO: Test took 1192ms.
[15:12:04.395] <TB2> INFO: Expecting 2560 events.
[15:12:05.277] <TB2> INFO: 2560 events read in total (291ms).
[15:12:05.277] <TB2> INFO: Test took 1190ms.
[15:12:05.585] <TB2> INFO: Expecting 2560 events.
[15:12:06.466] <TB2> INFO: 2560 events read in total (289ms).
[15:12:06.466] <TB2> INFO: Test took 1188ms.
[15:12:06.470] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:12:06.775] <TB2> INFO: Expecting 655360 events.
[15:12:21.007] <TB2> INFO: 655360 events read in total (13640ms).
[15:12:21.022] <TB2> INFO: Expecting 655360 events.
[15:12:35.063] <TB2> INFO: 655360 events read in total (13638ms).
[15:12:35.078] <TB2> INFO: Expecting 655360 events.
[15:12:49.234] <TB2> INFO: 655360 events read in total (13753ms).
[15:12:49.262] <TB2> INFO: Expecting 655360 events.
[15:13:03.359] <TB2> INFO: 655360 events read in total (13694ms).
[15:13:03.392] <TB2> INFO: Expecting 655360 events.
[15:13:17.481] <TB2> INFO: 655360 events read in total (13687ms).
[15:13:17.510] <TB2> INFO: Expecting 655360 events.
[15:13:31.542] <TB2> INFO: 655360 events read in total (13627ms).
[15:13:31.586] <TB2> INFO: Expecting 655360 events.
[15:13:45.678] <TB2> INFO: 655360 events read in total (13689ms).
[15:13:45.725] <TB2> INFO: Expecting 655360 events.
[15:13:59.832] <TB2> INFO: 655360 events read in total (13704ms).
[15:13:59.923] <TB2> INFO: Expecting 655360 events.
[15:14:14.015] <TB2> INFO: 655360 events read in total (13689ms).
[15:14:14.076] <TB2> INFO: Expecting 655360 events.
[15:14:28.314] <TB2> INFO: 655360 events read in total (13835ms).
[15:14:28.409] <TB2> INFO: Expecting 655360 events.
[15:14:42.623] <TB2> INFO: 655360 events read in total (13811ms).
[15:14:42.737] <TB2> INFO: Expecting 655360 events.
[15:14:56.908] <TB2> INFO: 655360 events read in total (13768ms).
[15:14:56.000] <TB2> INFO: Expecting 655360 events.
[15:15:11.211] <TB2> INFO: 655360 events read in total (13808ms).
[15:15:11.278] <TB2> INFO: Expecting 655360 events.
[15:15:25.388] <TB2> INFO: 655360 events read in total (13707ms).
[15:15:25.488] <TB2> INFO: Expecting 655360 events.
[15:15:39.597] <TB2> INFO: 655360 events read in total (13706ms).
[15:15:39.716] <TB2> INFO: Expecting 655360 events.
[15:15:53.832] <TB2> INFO: 655360 events read in total (13713ms).
[15:15:53.936] <TB2> INFO: Test took 227466ms.
[15:15:54.016] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:15:54.280] <TB2> INFO: Expecting 655360 events.
[15:16:08.344] <TB2> INFO: 655360 events read in total (13472ms).
[15:16:08.360] <TB2> INFO: Expecting 655360 events.
[15:16:22.322] <TB2> INFO: 655360 events read in total (13559ms).
[15:16:22.340] <TB2> INFO: Expecting 655360 events.
[15:16:36.155] <TB2> INFO: 655360 events read in total (13412ms).
[15:16:36.181] <TB2> INFO: Expecting 655360 events.
[15:16:50.187] <TB2> INFO: 655360 events read in total (13603ms).
[15:16:50.212] <TB2> INFO: Expecting 655360 events.
[15:17:04.151] <TB2> INFO: 655360 events read in total (13536ms).
[15:17:04.181] <TB2> INFO: Expecting 655360 events.
[15:17:18.060] <TB2> INFO: 655360 events read in total (13476ms).
[15:17:18.092] <TB2> INFO: Expecting 655360 events.
[15:17:31.970] <TB2> INFO: 655360 events read in total (13475ms).
[15:17:32.006] <TB2> INFO: Expecting 655360 events.
[15:17:46.157] <TB2> INFO: 655360 events read in total (13748ms).
[15:17:46.228] <TB2> INFO: Expecting 655360 events.
[15:18:00.273] <TB2> INFO: 655360 events read in total (13642ms).
[15:18:00.338] <TB2> INFO: Expecting 655360 events.
[15:18:14.318] <TB2> INFO: 655360 events read in total (13576ms).
[15:18:14.378] <TB2> INFO: Expecting 655360 events.
[15:18:28.458] <TB2> INFO: 655360 events read in total (13677ms).
[15:18:28.526] <TB2> INFO: Expecting 655360 events.
[15:18:42.437] <TB2> INFO: 655360 events read in total (13508ms).
[15:18:42.568] <TB2> INFO: Expecting 655360 events.
[15:18:56.622] <TB2> INFO: 655360 events read in total (13651ms).
[15:18:56.715] <TB2> INFO: Expecting 655360 events.
[15:19:10.722] <TB2> INFO: 655360 events read in total (13604ms).
[15:19:10.798] <TB2> INFO: Expecting 655360 events.
[15:19:24.820] <TB2> INFO: 655360 events read in total (13619ms).
[15:19:24.902] <TB2> INFO: Expecting 655360 events.
[15:19:39.041] <TB2> INFO: 655360 events read in total (13736ms).
[15:19:39.130] <TB2> INFO: Test took 225115ms.
[15:19:39.287] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.292] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:19:39.297] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:19:39.301] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:19:39.306] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:19:39.310] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:19:39.315] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[15:19:39.320] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[15:19:39.324] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[15:19:39.329] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[15:19:39.333] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.338] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.343] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.347] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.352] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.356] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.361] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:19:39.366] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:19:39.370] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:19:39.375] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.380] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:19:39.384] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:19:39.389] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:19:39.393] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:19:39.398] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:19:39.403] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[15:19:39.408] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[15:19:39.412] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[15:19:39.417] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.422] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.427] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.432] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:19:39.437] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:19:39.442] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:19:39.447] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:19:39.451] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:19:39.456] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[15:19:39.461] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.467] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:19:39.471] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.476] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.481] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.486] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:19:39.519] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C0.dat
[15:19:39.519] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C1.dat
[15:19:39.520] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C2.dat
[15:19:39.520] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C3.dat
[15:19:39.520] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C4.dat
[15:19:39.520] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C5.dat
[15:19:39.520] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C6.dat
[15:19:39.520] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C7.dat
[15:19:39.520] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C8.dat
[15:19:39.520] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C9.dat
[15:19:39.520] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C10.dat
[15:19:39.520] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C11.dat
[15:19:39.521] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C12.dat
[15:19:39.521] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C13.dat
[15:19:39.521] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C14.dat
[15:19:39.521] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C15.dat
[15:19:39.781] <TB2> INFO: Expecting 41600 events.
[15:19:42.899] <TB2> INFO: 41600 events read in total (2526ms).
[15:19:42.900] <TB2> INFO: Test took 3376ms.
[15:19:43.345] <TB2> INFO: Expecting 41600 events.
[15:19:46.396] <TB2> INFO: 41600 events read in total (2460ms).
[15:19:46.396] <TB2> INFO: Test took 3283ms.
[15:19:46.842] <TB2> INFO: Expecting 41600 events.
[15:19:49.915] <TB2> INFO: 41600 events read in total (2482ms).
[15:19:49.916] <TB2> INFO: Test took 3306ms.
[15:19:50.133] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:50.221] <TB2> INFO: Expecting 2560 events.
[15:19:51.105] <TB2> INFO: 2560 events read in total (292ms).
[15:19:51.105] <TB2> INFO: Test took 972ms.
[15:19:51.107] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:51.413] <TB2> INFO: Expecting 2560 events.
[15:19:52.296] <TB2> INFO: 2560 events read in total (291ms).
[15:19:52.297] <TB2> INFO: Test took 1190ms.
[15:19:52.298] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:52.605] <TB2> INFO: Expecting 2560 events.
[15:19:53.488] <TB2> INFO: 2560 events read in total (291ms).
[15:19:53.488] <TB2> INFO: Test took 1190ms.
[15:19:53.490] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:53.797] <TB2> INFO: Expecting 2560 events.
[15:19:54.682] <TB2> INFO: 2560 events read in total (294ms).
[15:19:54.682] <TB2> INFO: Test took 1193ms.
[15:19:54.684] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:54.991] <TB2> INFO: Expecting 2560 events.
[15:19:55.874] <TB2> INFO: 2560 events read in total (292ms).
[15:19:55.875] <TB2> INFO: Test took 1191ms.
[15:19:55.876] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:56.183] <TB2> INFO: Expecting 2560 events.
[15:19:57.067] <TB2> INFO: 2560 events read in total (292ms).
[15:19:57.067] <TB2> INFO: Test took 1191ms.
[15:19:57.069] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:57.376] <TB2> INFO: Expecting 2560 events.
[15:19:58.259] <TB2> INFO: 2560 events read in total (292ms).
[15:19:58.259] <TB2> INFO: Test took 1190ms.
[15:19:58.262] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:58.568] <TB2> INFO: Expecting 2560 events.
[15:19:59.453] <TB2> INFO: 2560 events read in total (295ms).
[15:19:59.454] <TB2> INFO: Test took 1192ms.
[15:19:59.456] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:59.762] <TB2> INFO: Expecting 2560 events.
[15:20:00.642] <TB2> INFO: 2560 events read in total (288ms).
[15:20:00.642] <TB2> INFO: Test took 1186ms.
[15:20:00.644] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:00.951] <TB2> INFO: Expecting 2560 events.
[15:20:01.829] <TB2> INFO: 2560 events read in total (287ms).
[15:20:01.829] <TB2> INFO: Test took 1185ms.
[15:20:01.831] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:02.138] <TB2> INFO: Expecting 2560 events.
[15:20:03.023] <TB2> INFO: 2560 events read in total (293ms).
[15:20:03.023] <TB2> INFO: Test took 1192ms.
[15:20:03.026] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:03.331] <TB2> INFO: Expecting 2560 events.
[15:20:04.209] <TB2> INFO: 2560 events read in total (286ms).
[15:20:04.209] <TB2> INFO: Test took 1183ms.
[15:20:04.211] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:04.518] <TB2> INFO: Expecting 2560 events.
[15:20:05.399] <TB2> INFO: 2560 events read in total (290ms).
[15:20:05.400] <TB2> INFO: Test took 1189ms.
[15:20:05.401] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:05.708] <TB2> INFO: Expecting 2560 events.
[15:20:06.586] <TB2> INFO: 2560 events read in total (287ms).
[15:20:06.586] <TB2> INFO: Test took 1185ms.
[15:20:06.589] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:06.894] <TB2> INFO: Expecting 2560 events.
[15:20:07.772] <TB2> INFO: 2560 events read in total (286ms).
[15:20:07.772] <TB2> INFO: Test took 1183ms.
[15:20:07.774] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:08.080] <TB2> INFO: Expecting 2560 events.
[15:20:08.959] <TB2> INFO: 2560 events read in total (287ms).
[15:20:08.959] <TB2> INFO: Test took 1185ms.
[15:20:08.961] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:09.268] <TB2> INFO: Expecting 2560 events.
[15:20:10.146] <TB2> INFO: 2560 events read in total (286ms).
[15:20:10.147] <TB2> INFO: Test took 1186ms.
[15:20:10.148] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:10.455] <TB2> INFO: Expecting 2560 events.
[15:20:11.340] <TB2> INFO: 2560 events read in total (293ms).
[15:20:11.340] <TB2> INFO: Test took 1192ms.
[15:20:11.342] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:11.648] <TB2> INFO: Expecting 2560 events.
[15:20:12.530] <TB2> INFO: 2560 events read in total (290ms).
[15:20:12.530] <TB2> INFO: Test took 1188ms.
[15:20:12.532] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:12.839] <TB2> INFO: Expecting 2560 events.
[15:20:13.721] <TB2> INFO: 2560 events read in total (291ms).
[15:20:13.721] <TB2> INFO: Test took 1189ms.
[15:20:13.723] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:14.029] <TB2> INFO: Expecting 2560 events.
[15:20:14.906] <TB2> INFO: 2560 events read in total (285ms).
[15:20:14.907] <TB2> INFO: Test took 1184ms.
[15:20:14.909] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:15.215] <TB2> INFO: Expecting 2560 events.
[15:20:16.094] <TB2> INFO: 2560 events read in total (287ms).
[15:20:16.094] <TB2> INFO: Test took 1185ms.
[15:20:16.096] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:16.403] <TB2> INFO: Expecting 2560 events.
[15:20:17.284] <TB2> INFO: 2560 events read in total (290ms).
[15:20:17.285] <TB2> INFO: Test took 1189ms.
[15:20:17.287] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:17.593] <TB2> INFO: Expecting 2560 events.
[15:20:18.472] <TB2> INFO: 2560 events read in total (288ms).
[15:20:18.472] <TB2> INFO: Test took 1185ms.
[15:20:18.474] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:18.780] <TB2> INFO: Expecting 2560 events.
[15:20:19.664] <TB2> INFO: 2560 events read in total (292ms).
[15:20:19.664] <TB2> INFO: Test took 1191ms.
[15:20:19.670] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:19.972] <TB2> INFO: Expecting 2560 events.
[15:20:20.856] <TB2> INFO: 2560 events read in total (292ms).
[15:20:20.856] <TB2> INFO: Test took 1186ms.
[15:20:20.858] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:21.164] <TB2> INFO: Expecting 2560 events.
[15:20:22.047] <TB2> INFO: 2560 events read in total (291ms).
[15:20:22.048] <TB2> INFO: Test took 1190ms.
[15:20:22.050] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:22.356] <TB2> INFO: Expecting 2560 events.
[15:20:23.238] <TB2> INFO: 2560 events read in total (290ms).
[15:20:23.238] <TB2> INFO: Test took 1189ms.
[15:20:23.240] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:23.547] <TB2> INFO: Expecting 2560 events.
[15:20:24.430] <TB2> INFO: 2560 events read in total (291ms).
[15:20:24.431] <TB2> INFO: Test took 1191ms.
[15:20:24.433] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:24.739] <TB2> INFO: Expecting 2560 events.
[15:20:25.622] <TB2> INFO: 2560 events read in total (292ms).
[15:20:25.623] <TB2> INFO: Test took 1190ms.
[15:20:25.625] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:25.931] <TB2> INFO: Expecting 2560 events.
[15:20:26.814] <TB2> INFO: 2560 events read in total (291ms).
[15:20:26.814] <TB2> INFO: Test took 1189ms.
[15:20:26.816] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:27.122] <TB2> INFO: Expecting 2560 events.
[15:20:28.006] <TB2> INFO: 2560 events read in total (292ms).
[15:20:28.006] <TB2> INFO: Test took 1190ms.
[15:20:28.470] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 635 seconds
[15:20:28.470] <TB2> INFO: PH scale (per ROC): 48 51 51 42 37 47 48 39 38 33 48 34 51 36 38 36
[15:20:28.470] <TB2> INFO: PH offset (per ROC): 121 123 121 88 112 117 87 111 98 107 107 97 103 95 111 105
[15:20:28.475] <TB2> INFO: Decoding statistics:
[15:20:28.475] <TB2> INFO: General information:
[15:20:28.475] <TB2> INFO: 16bit words read: 127704
[15:20:28.475] <TB2> INFO: valid events total: 20480
[15:20:28.475] <TB2> INFO: empty events: 18068
[15:20:28.475] <TB2> INFO: valid events with pixels: 2412
[15:20:28.475] <TB2> INFO: valid pixel hits: 2412
[15:20:28.475] <TB2> INFO: Event errors: 0
[15:20:28.475] <TB2> INFO: start marker: 0
[15:20:28.475] <TB2> INFO: stop marker: 0
[15:20:28.475] <TB2> INFO: overflow: 0
[15:20:28.475] <TB2> INFO: invalid 5bit words: 0
[15:20:28.475] <TB2> INFO: invalid XOR eye diagram: 0
[15:20:28.475] <TB2> INFO: frame (failed synchr.): 0
[15:20:28.475] <TB2> INFO: idle data (no TBM trl): 0
[15:20:28.475] <TB2> INFO: no data (only TBM hdr): 0
[15:20:28.475] <TB2> INFO: TBM errors: 0
[15:20:28.475] <TB2> INFO: flawed TBM headers: 0
[15:20:28.475] <TB2> INFO: flawed TBM trailers: 0
[15:20:28.475] <TB2> INFO: event ID mismatches: 0
[15:20:28.475] <TB2> INFO: ROC errors: 0
[15:20:28.475] <TB2> INFO: missing ROC header(s): 0
[15:20:28.475] <TB2> INFO: misplaced readback start: 0
[15:20:28.475] <TB2> INFO: Pixel decoding errors: 0
[15:20:28.475] <TB2> INFO: pixel data incomplete: 0
[15:20:28.475] <TB2> INFO: pixel address: 0
[15:20:28.475] <TB2> INFO: pulse height fill bit: 0
[15:20:28.475] <TB2> INFO: buffer corruption: 0
[15:20:28.743] <TB2> INFO: ######################################################################
[15:20:28.743] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:20:28.743] <TB2> INFO: ######################################################################
[15:20:28.755] <TB2> INFO: scanning low vcal = 10
[15:20:28.995] <TB2> INFO: Expecting 41600 events.
[15:20:32.576] <TB2> INFO: 41600 events read in total (2989ms).
[15:20:32.576] <TB2> INFO: Test took 3821ms.
[15:20:32.578] <TB2> INFO: scanning low vcal = 20
[15:20:32.875] <TB2> INFO: Expecting 41600 events.
[15:20:36.427] <TB2> INFO: 41600 events read in total (2960ms).
[15:20:36.427] <TB2> INFO: Test took 3849ms.
[15:20:36.429] <TB2> INFO: scanning low vcal = 30
[15:20:36.727] <TB2> INFO: Expecting 41600 events.
[15:20:40.335] <TB2> INFO: 41600 events read in total (3016ms).
[15:20:40.336] <TB2> INFO: Test took 3907ms.
[15:20:40.338] <TB2> INFO: scanning low vcal = 40
[15:20:40.618] <TB2> INFO: Expecting 41600 events.
[15:20:44.532] <TB2> INFO: 41600 events read in total (3322ms).
[15:20:44.533] <TB2> INFO: Test took 4194ms.
[15:20:44.536] <TB2> INFO: scanning low vcal = 50
[15:20:44.814] <TB2> INFO: Expecting 41600 events.
[15:20:48.756] <TB2> INFO: 41600 events read in total (3350ms).
[15:20:48.757] <TB2> INFO: Test took 4221ms.
[15:20:48.760] <TB2> INFO: scanning low vcal = 60
[15:20:49.037] <TB2> INFO: Expecting 41600 events.
[15:20:52.986] <TB2> INFO: 41600 events read in total (3358ms).
[15:20:52.987] <TB2> INFO: Test took 4227ms.
[15:20:52.989] <TB2> INFO: scanning low vcal = 70
[15:20:53.266] <TB2> INFO: Expecting 41600 events.
[15:20:57.198] <TB2> INFO: 41600 events read in total (3340ms).
[15:20:57.199] <TB2> INFO: Test took 4210ms.
[15:20:57.202] <TB2> INFO: scanning low vcal = 80
[15:20:57.479] <TB2> INFO: Expecting 41600 events.
[15:21:01.449] <TB2> INFO: 41600 events read in total (3379ms).
[15:21:01.450] <TB2> INFO: Test took 4248ms.
[15:21:01.452] <TB2> INFO: scanning low vcal = 90
[15:21:01.729] <TB2> INFO: Expecting 41600 events.
[15:21:05.644] <TB2> INFO: 41600 events read in total (3323ms).
[15:21:05.645] <TB2> INFO: Test took 4193ms.
[15:21:05.648] <TB2> INFO: scanning low vcal = 100
[15:21:05.925] <TB2> INFO: Expecting 41600 events.
[15:21:09.851] <TB2> INFO: 41600 events read in total (3335ms).
[15:21:09.851] <TB2> INFO: Test took 4203ms.
[15:21:09.854] <TB2> INFO: scanning low vcal = 110
[15:21:10.131] <TB2> INFO: Expecting 41600 events.
[15:21:14.043] <TB2> INFO: 41600 events read in total (3321ms).
[15:21:14.044] <TB2> INFO: Test took 4190ms.
[15:21:14.046] <TB2> INFO: scanning low vcal = 120
[15:21:14.323] <TB2> INFO: Expecting 41600 events.
[15:21:18.259] <TB2> INFO: 41600 events read in total (3344ms).
[15:21:18.260] <TB2> INFO: Test took 4213ms.
[15:21:18.263] <TB2> INFO: scanning low vcal = 130
[15:21:18.539] <TB2> INFO: Expecting 41600 events.
[15:21:22.499] <TB2> INFO: 41600 events read in total (3368ms).
[15:21:22.500] <TB2> INFO: Test took 4237ms.
[15:21:22.503] <TB2> INFO: scanning low vcal = 140
[15:21:22.780] <TB2> INFO: Expecting 41600 events.
[15:21:26.691] <TB2> INFO: 41600 events read in total (3320ms).
[15:21:26.692] <TB2> INFO: Test took 4189ms.
[15:21:26.694] <TB2> INFO: scanning low vcal = 150
[15:21:26.971] <TB2> INFO: Expecting 41600 events.
[15:21:30.914] <TB2> INFO: 41600 events read in total (3351ms).
[15:21:30.915] <TB2> INFO: Test took 4220ms.
[15:21:30.918] <TB2> INFO: scanning low vcal = 160
[15:21:31.194] <TB2> INFO: Expecting 41600 events.
[15:21:35.132] <TB2> INFO: 41600 events read in total (3347ms).
[15:21:35.133] <TB2> INFO: Test took 4215ms.
[15:21:35.136] <TB2> INFO: scanning low vcal = 170
[15:21:35.413] <TB2> INFO: Expecting 41600 events.
[15:21:39.341] <TB2> INFO: 41600 events read in total (3336ms).
[15:21:39.342] <TB2> INFO: Test took 4206ms.
[15:21:39.345] <TB2> INFO: scanning low vcal = 180
[15:21:39.622] <TB2> INFO: Expecting 41600 events.
[15:21:43.572] <TB2> INFO: 41600 events read in total (3358ms).
[15:21:43.573] <TB2> INFO: Test took 4228ms.
[15:21:43.576] <TB2> INFO: scanning low vcal = 190
[15:21:43.852] <TB2> INFO: Expecting 41600 events.
[15:21:47.865] <TB2> INFO: 41600 events read in total (3421ms).
[15:21:47.866] <TB2> INFO: Test took 4290ms.
[15:21:47.869] <TB2> INFO: scanning low vcal = 200
[15:21:48.146] <TB2> INFO: Expecting 41600 events.
[15:21:52.118] <TB2> INFO: 41600 events read in total (3381ms).
[15:21:52.119] <TB2> INFO: Test took 4250ms.
[15:21:52.122] <TB2> INFO: scanning low vcal = 210
[15:21:52.398] <TB2> INFO: Expecting 41600 events.
[15:21:56.360] <TB2> INFO: 41600 events read in total (3370ms).
[15:21:56.361] <TB2> INFO: Test took 4239ms.
[15:21:56.364] <TB2> INFO: scanning low vcal = 220
[15:21:56.641] <TB2> INFO: Expecting 41600 events.
[15:22:00.588] <TB2> INFO: 41600 events read in total (3356ms).
[15:22:00.589] <TB2> INFO: Test took 4225ms.
[15:22:00.592] <TB2> INFO: scanning low vcal = 230
[15:22:00.869] <TB2> INFO: Expecting 41600 events.
[15:22:04.839] <TB2> INFO: 41600 events read in total (3379ms).
[15:22:04.840] <TB2> INFO: Test took 4248ms.
[15:22:04.843] <TB2> INFO: scanning low vcal = 240
[15:22:05.119] <TB2> INFO: Expecting 41600 events.
[15:22:09.071] <TB2> INFO: 41600 events read in total (3360ms).
[15:22:09.072] <TB2> INFO: Test took 4229ms.
[15:22:09.075] <TB2> INFO: scanning low vcal = 250
[15:22:09.352] <TB2> INFO: Expecting 41600 events.
[15:22:13.318] <TB2> INFO: 41600 events read in total (3375ms).
[15:22:13.319] <TB2> INFO: Test took 4244ms.
[15:22:13.323] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[15:22:13.599] <TB2> INFO: Expecting 41600 events.
[15:22:17.593] <TB2> INFO: 41600 events read in total (3403ms).
[15:22:17.594] <TB2> INFO: Test took 4271ms.
[15:22:17.597] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[15:22:17.873] <TB2> INFO: Expecting 41600 events.
[15:22:21.792] <TB2> INFO: 41600 events read in total (3328ms).
[15:22:21.792] <TB2> INFO: Test took 4195ms.
[15:22:21.795] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[15:22:22.071] <TB2> INFO: Expecting 41600 events.
[15:22:26.067] <TB2> INFO: 41600 events read in total (3404ms).
[15:22:26.068] <TB2> INFO: Test took 4273ms.
[15:22:26.070] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[15:22:26.347] <TB2> INFO: Expecting 41600 events.
[15:22:30.320] <TB2> INFO: 41600 events read in total (3381ms).
[15:22:30.321] <TB2> INFO: Test took 4250ms.
[15:22:30.325] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:22:30.605] <TB2> INFO: Expecting 41600 events.
[15:22:34.562] <TB2> INFO: 41600 events read in total (3366ms).
[15:22:34.563] <TB2> INFO: Test took 4238ms.
[15:22:35.031] <TB2> INFO: PixTestGainPedestal::measure() done
[15:23:14.543] <TB2> INFO: PixTestGainPedestal::fit() done
[15:23:14.543] <TB2> INFO: non-linearity mean: 0.982 0.979 0.982 0.933 0.930 0.961 0.969 0.917 0.933 0.929 0.976 0.933 0.975 0.941 0.943 0.956
[15:23:14.543] <TB2> INFO: non-linearity RMS: 0.004 0.004 0.004 0.089 0.083 0.028 0.023 0.115 0.124 0.138 0.005 0.114 0.010 0.143 0.137 0.165
[15:23:14.543] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[15:23:14.558] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[15:23:14.572] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[15:23:14.585] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[15:23:14.599] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[15:23:14.613] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[15:23:14.627] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[15:23:14.640] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[15:23:14.659] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[15:23:14.680] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[15:23:14.696] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[15:23:14.711] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[15:23:14.728] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[15:23:14.743] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[15:23:14.757] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[15:23:14.771] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[15:23:14.785] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 166 seconds
[15:23:14.785] <TB2> INFO: Decoding statistics:
[15:23:14.785] <TB2> INFO: General information:
[15:23:14.785] <TB2> INFO: 16bit words read: 3265094
[15:23:14.785] <TB2> INFO: valid events total: 332800
[15:23:14.785] <TB2> INFO: empty events: 3281
[15:23:14.785] <TB2> INFO: valid events with pixels: 329519
[15:23:14.785] <TB2> INFO: valid pixel hits: 634147
[15:23:14.785] <TB2> INFO: Event errors: 0
[15:23:14.785] <TB2> INFO: start marker: 0
[15:23:14.785] <TB2> INFO: stop marker: 0
[15:23:14.785] <TB2> INFO: overflow: 0
[15:23:14.785] <TB2> INFO: invalid 5bit words: 0
[15:23:14.785] <TB2> INFO: invalid XOR eye diagram: 0
[15:23:14.785] <TB2> INFO: frame (failed synchr.): 0
[15:23:14.785] <TB2> INFO: idle data (no TBM trl): 0
[15:23:14.785] <TB2> INFO: no data (only TBM hdr): 0
[15:23:14.785] <TB2> INFO: TBM errors: 0
[15:23:14.785] <TB2> INFO: flawed TBM headers: 0
[15:23:14.785] <TB2> INFO: flawed TBM trailers: 0
[15:23:14.785] <TB2> INFO: event ID mismatches: 0
[15:23:14.785] <TB2> INFO: ROC errors: 0
[15:23:14.785] <TB2> INFO: missing ROC header(s): 0
[15:23:14.785] <TB2> INFO: misplaced readback start: 0
[15:23:14.785] <TB2> INFO: Pixel decoding errors: 0
[15:23:14.785] <TB2> INFO: pixel data incomplete: 0
[15:23:14.785] <TB2> INFO: pixel address: 0
[15:23:14.785] <TB2> INFO: pulse height fill bit: 0
[15:23:14.785] <TB2> INFO: buffer corruption: 0
[15:23:14.804] <TB2> INFO: Decoding statistics:
[15:23:14.804] <TB2> INFO: General information:
[15:23:14.804] <TB2> INFO: 16bit words read: 3394334
[15:23:14.804] <TB2> INFO: valid events total: 353536
[15:23:14.804] <TB2> INFO: empty events: 21605
[15:23:14.804] <TB2> INFO: valid events with pixels: 331931
[15:23:14.804] <TB2> INFO: valid pixel hits: 636559
[15:23:14.804] <TB2> INFO: Event errors: 0
[15:23:14.804] <TB2> INFO: start marker: 0
[15:23:14.804] <TB2> INFO: stop marker: 0
[15:23:14.804] <TB2> INFO: overflow: 0
[15:23:14.804] <TB2> INFO: invalid 5bit words: 0
[15:23:14.804] <TB2> INFO: invalid XOR eye diagram: 0
[15:23:14.804] <TB2> INFO: frame (failed synchr.): 0
[15:23:14.804] <TB2> INFO: idle data (no TBM trl): 0
[15:23:14.804] <TB2> INFO: no data (only TBM hdr): 0
[15:23:14.804] <TB2> INFO: TBM errors: 0
[15:23:14.804] <TB2> INFO: flawed TBM headers: 0
[15:23:14.804] <TB2> INFO: flawed TBM trailers: 0
[15:23:14.804] <TB2> INFO: event ID mismatches: 0
[15:23:14.804] <TB2> INFO: ROC errors: 0
[15:23:14.804] <TB2> INFO: missing ROC header(s): 0
[15:23:14.804] <TB2> INFO: misplaced readback start: 0
[15:23:14.804] <TB2> INFO: Pixel decoding errors: 0
[15:23:14.804] <TB2> INFO: pixel data incomplete: 0
[15:23:14.804] <TB2> INFO: pixel address: 0
[15:23:14.804] <TB2> INFO: pulse height fill bit: 0
[15:23:14.804] <TB2> INFO: buffer corruption: 0
[15:23:14.805] <TB2> INFO: enter test to run
[15:23:14.805] <TB2> INFO: test: Trim80 no parameter change
[15:23:14.805] <TB2> INFO: running: trim80
[15:23:14.828] <TB2> INFO: ######################################################################
[15:23:14.828] <TB2> INFO: PixTestTrim80::doTest()
[15:23:14.828] <TB2> INFO: ######################################################################
[15:23:14.829] <TB2> INFO: ----------------------------------------------------------------------
[15:23:14.829] <TB2> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[15:23:14.829] <TB2> INFO: ----------------------------------------------------------------------
[15:23:14.869] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[15:23:14.869] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:23:14.878] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:23:14.878] <TB2> INFO: run 1 of 1
[15:23:15.111] <TB2> INFO: Expecting 5025280 events.
[15:23:43.283] <TB2> INFO: 691864 events read in total (27580ms).
[15:24:10.919] <TB2> INFO: 1379544 events read in total (55216ms).
[15:24:38.418] <TB2> INFO: 2064936 events read in total (82715ms).
[15:25:05.811] <TB2> INFO: 2748152 events read in total (110108ms).
[15:25:33.310] <TB2> INFO: 3429192 events read in total (137607ms).
[15:26:01.047] <TB2> INFO: 4107976 events read in total (165344ms).
[15:26:27.995] <TB2> INFO: 4787168 events read in total (192292ms).
[15:26:37.644] <TB2> INFO: 5025280 events read in total (201941ms).
[15:26:37.729] <TB2> INFO: Test took 202851ms.
[15:26:58.666] <TB2> INFO: ROC 0 VthrComp = 80
[15:26:58.666] <TB2> INFO: ROC 1 VthrComp = 75
[15:26:58.666] <TB2> INFO: ROC 2 VthrComp = 81
[15:26:58.667] <TB2> INFO: ROC 3 VthrComp = 82
[15:26:58.667] <TB2> INFO: ROC 4 VthrComp = 90
[15:26:58.667] <TB2> INFO: ROC 5 VthrComp = 79
[15:26:58.667] <TB2> INFO: ROC 6 VthrComp = 76
[15:26:58.667] <TB2> INFO: ROC 7 VthrComp = 63
[15:26:58.667] <TB2> INFO: ROC 8 VthrComp = 83
[15:26:58.667] <TB2> INFO: ROC 9 VthrComp = 75
[15:26:58.667] <TB2> INFO: ROC 10 VthrComp = 72
[15:26:58.668] <TB2> INFO: ROC 11 VthrComp = 75
[15:26:58.668] <TB2> INFO: ROC 12 VthrComp = 79
[15:26:58.668] <TB2> INFO: ROC 13 VthrComp = 76
[15:26:58.668] <TB2> INFO: ROC 14 VthrComp = 85
[15:26:58.668] <TB2> INFO: ROC 15 VthrComp = 87
[15:26:58.910] <TB2> INFO: Expecting 41600 events.
[15:27:02.486] <TB2> INFO: 41600 events read in total (2984ms).
[15:27:02.486] <TB2> INFO: Test took 3817ms.
[15:27:02.495] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[15:27:02.495] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:27:02.505] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:27:02.505] <TB2> INFO: run 1 of 1
[15:27:02.812] <TB2> INFO: Expecting 5025280 events.
[15:27:30.789] <TB2> INFO: 685776 events read in total (27385ms).
[15:27:58.063] <TB2> INFO: 1368080 events read in total (54659ms).
[15:28:25.291] <TB2> INFO: 2049424 events read in total (81887ms).
[15:28:52.567] <TB2> INFO: 2728560 events read in total (109163ms).
[15:29:20.192] <TB2> INFO: 3402880 events read in total (136788ms).
[15:29:47.616] <TB2> INFO: 4076632 events read in total (164212ms).
[15:30:15.313] <TB2> INFO: 4750904 events read in total (191909ms).
[15:30:26.490] <TB2> INFO: 5025280 events read in total (203086ms).
[15:30:26.556] <TB2> INFO: Test took 204050ms.
[15:30:47.370] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 111.635 for pixel 12/76 mean/min/max = 93.1532/74.4732/111.833
[15:30:47.370] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 108.505 for pixel 0/10 mean/min/max = 93.2563/77.9086/108.604
[15:30:47.370] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 108.224 for pixel 20/2 mean/min/max = 91.7596/75.2729/108.246
[15:30:47.371] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 106.399 for pixel 2/16 mean/min/max = 90.482/74.4223/106.542
[15:30:47.371] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 111.701 for pixel 51/77 mean/min/max = 93.8172/75.8633/111.771
[15:30:47.372] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 110.33 for pixel 0/67 mean/min/max = 94.1947/78.0047/110.385
[15:30:47.372] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 112.604 for pixel 49/14 mean/min/max = 95.4694/78.172/112.767
[15:30:47.373] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 105.34 for pixel 18/79 mean/min/max = 90.0819/74.4978/105.666
[15:30:47.373] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 108.695 for pixel 10/18 mean/min/max = 91.6126/74.3907/108.835
[15:30:47.373] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 108.396 for pixel 0/47 mean/min/max = 93.0576/77.7093/108.406
[15:30:47.374] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 109.607 for pixel 0/6 mean/min/max = 93.0395/76.2654/109.813
[15:30:47.374] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 111.81 for pixel 51/29 mean/min/max = 94.3334/76.8422/111.825
[15:30:47.375] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 108.353 for pixel 2/14 mean/min/max = 93.0291/77.6029/108.455
[15:30:47.375] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 112.452 for pixel 47/5 mean/min/max = 95.2652/77.9031/112.627
[15:30:47.376] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 108.672 for pixel 51/15 mean/min/max = 91.6642/74.5288/108.8
[15:30:47.376] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 108.125 for pixel 0/71 mean/min/max = 91.2678/74.2057/108.33
[15:30:47.376] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:30:47.465] <TB2> INFO: Expecting 411648 events.
[15:30:56.679] <TB2> INFO: 411648 events read in total (8623ms).
[15:30:56.686] <TB2> INFO: Expecting 411648 events.
[15:31:05.693] <TB2> INFO: 411648 events read in total (8604ms).
[15:31:05.703] <TB2> INFO: Expecting 411648 events.
[15:31:14.775] <TB2> INFO: 411648 events read in total (8669ms).
[15:31:14.787] <TB2> INFO: Expecting 411648 events.
[15:31:23.776] <TB2> INFO: 411648 events read in total (8586ms).
[15:31:23.792] <TB2> INFO: Expecting 411648 events.
[15:31:32.818] <TB2> INFO: 411648 events read in total (8624ms).
[15:31:32.836] <TB2> INFO: Expecting 411648 events.
[15:31:41.852] <TB2> INFO: 411648 events read in total (8613ms).
[15:31:41.871] <TB2> INFO: Expecting 411648 events.
[15:31:50.892] <TB2> INFO: 411648 events read in total (8618ms).
[15:31:50.913] <TB2> INFO: Expecting 411648 events.
[15:31:59.901] <TB2> INFO: 411648 events read in total (8585ms).
[15:31:59.927] <TB2> INFO: Expecting 411648 events.
[15:32:08.959] <TB2> INFO: 411648 events read in total (8629ms).
[15:32:08.986] <TB2> INFO: Expecting 411648 events.
[15:32:18.047] <TB2> INFO: 411648 events read in total (8658ms).
[15:32:18.101] <TB2> INFO: Expecting 411648 events.
[15:32:27.245] <TB2> INFO: 411648 events read in total (8741ms).
[15:32:27.279] <TB2> INFO: Expecting 411648 events.
[15:32:36.390] <TB2> INFO: 411648 events read in total (8708ms).
[15:32:36.449] <TB2> INFO: Expecting 411648 events.
[15:32:45.530] <TB2> INFO: 411648 events read in total (8678ms).
[15:32:45.588] <TB2> INFO: Expecting 411648 events.
[15:32:54.680] <TB2> INFO: 411648 events read in total (8689ms).
[15:32:54.748] <TB2> INFO: Expecting 411648 events.
[15:33:04.017] <TB2> INFO: 411648 events read in total (8866ms).
[15:33:04.123] <TB2> INFO: Expecting 411648 events.
[15:33:13.204] <TB2> INFO: 411648 events read in total (8679ms).
[15:33:13.317] <TB2> INFO: Test took 145941ms.
[15:33:15.108] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[15:33:15.119] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:33:15.119] <TB2> INFO: run 1 of 1
[15:33:15.365] <TB2> INFO: Expecting 5025280 events.
[15:33:42.719] <TB2> INFO: 664200 events read in total (26763ms).
[15:34:09.696] <TB2> INFO: 1325656 events read in total (53740ms).
[15:34:36.534] <TB2> INFO: 1986952 events read in total (80578ms).
[15:35:03.344] <TB2> INFO: 2646400 events read in total (107388ms).
[15:35:30.136] <TB2> INFO: 3302064 events read in total (134180ms).
[15:35:56.833] <TB2> INFO: 3955880 events read in total (160877ms).
[15:36:23.719] <TB2> INFO: 4610824 events read in total (187763ms).
[15:36:40.672] <TB2> INFO: 5025280 events read in total (204716ms).
[15:36:40.741] <TB2> INFO: Test took 205622ms.
[15:37:04.634] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 48.909483 .. 97.693355
[15:37:04.868] <TB2> INFO: Expecting 208000 events.
[15:37:14.609] <TB2> INFO: 208000 events read in total (9150ms).
[15:37:14.609] <TB2> INFO: Test took 9973ms.
[15:37:14.659] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 38 .. 107 (-1/-1) hits flags = 528 (plus default)
[15:37:14.670] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:37:14.670] <TB2> INFO: run 1 of 1
[15:37:14.948] <TB2> INFO: Expecting 2329600 events.
[15:37:43.607] <TB2> INFO: 708760 events read in total (28067ms).
[15:38:11.792] <TB2> INFO: 1414248 events read in total (56252ms).
[15:38:39.614] <TB2> INFO: 2111752 events read in total (84074ms).
[15:38:48.346] <TB2> INFO: 2329600 events read in total (92806ms).
[15:38:48.379] <TB2> INFO: Test took 93708ms.
[15:39:07.388] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 59.520665 .. 88.931600
[15:39:07.621] <TB2> INFO: Expecting 208000 events.
[15:39:17.245] <TB2> INFO: 208000 events read in total (9032ms).
[15:39:17.246] <TB2> INFO: Test took 9856ms.
[15:39:17.312] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 49 .. 98 (-1/-1) hits flags = 528 (plus default)
[15:39:17.323] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:39:17.323] <TB2> INFO: run 1 of 1
[15:39:17.601] <TB2> INFO: Expecting 1664000 events.
[15:39:46.378] <TB2> INFO: 714792 events read in total (28185ms).
[15:40:14.446] <TB2> INFO: 1428840 events read in total (56254ms).
[15:40:23.867] <TB2> INFO: 1664000 events read in total (65674ms).
[15:40:23.893] <TB2> INFO: Test took 66570ms.
[15:40:39.627] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 65.049640 .. 83.756623
[15:40:39.900] <TB2> INFO: Expecting 208000 events.
[15:40:49.597] <TB2> INFO: 208000 events read in total (9105ms).
[15:40:49.598] <TB2> INFO: Test took 9969ms.
[15:40:49.665] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 55 .. 93 (-1/-1) hits flags = 528 (plus default)
[15:40:49.676] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:40:49.676] <TB2> INFO: run 1 of 1
[15:40:49.954] <TB2> INFO: Expecting 1297920 events.
[15:41:19.023] <TB2> INFO: 725320 events read in total (28477ms).
[15:41:41.840] <TB2> INFO: 1297920 events read in total (51295ms).
[15:41:41.862] <TB2> INFO: Test took 52186ms.
[15:41:58.683] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 67.172074 .. 88.186050
[15:41:58.917] <TB2> INFO: Expecting 208000 events.
[15:42:08.570] <TB2> INFO: 208000 events read in total (9061ms).
[15:42:08.571] <TB2> INFO: Test took 9886ms.
[15:42:08.623] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 57 .. 98 (-1/-1) hits flags = 528 (plus default)
[15:42:08.633] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:42:08.633] <TB2> INFO: run 1 of 1
[15:42:08.911] <TB2> INFO: Expecting 1397760 events.
[15:42:37.895] <TB2> INFO: 690552 events read in total (28393ms).
[15:43:06.686] <TB2> INFO: 1380880 events read in total (57184ms).
[15:43:07.814] <TB2> INFO: 1397760 events read in total (58313ms).
[15:43:07.849] <TB2> INFO: Test took 59216ms.
[15:43:26.771] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[15:43:26.771] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[15:43:26.781] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:43:26.782] <TB2> INFO: run 1 of 1
[15:43:27.013] <TB2> INFO: Expecting 1364480 events.
[15:43:55.258] <TB2> INFO: 668232 events read in total (27653ms).
[15:44:23.122] <TB2> INFO: 1335808 events read in total (55517ms).
[15:44:24.813] <TB2> INFO: 1364480 events read in total (57208ms).
[15:44:24.839] <TB2> INFO: Test took 58057ms.
[15:44:42.292] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C0.dat
[15:44:42.292] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C1.dat
[15:44:42.292] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C2.dat
[15:44:42.292] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C3.dat
[15:44:42.292] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C4.dat
[15:44:42.293] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C5.dat
[15:44:42.293] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C6.dat
[15:44:42.293] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C7.dat
[15:44:42.293] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C8.dat
[15:44:42.293] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C9.dat
[15:44:42.293] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C10.dat
[15:44:42.293] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C11.dat
[15:44:42.293] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C12.dat
[15:44:42.293] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C13.dat
[15:44:42.293] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C14.dat
[15:44:42.293] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C15.dat
[15:44:42.293] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C0.dat
[15:44:42.299] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C1.dat
[15:44:42.305] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C2.dat
[15:44:42.310] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C3.dat
[15:44:42.316] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C4.dat
[15:44:42.321] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C5.dat
[15:44:42.327] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C6.dat
[15:44:42.333] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C7.dat
[15:44:42.338] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C8.dat
[15:44:42.344] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C9.dat
[15:44:42.349] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C10.dat
[15:44:42.355] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C11.dat
[15:44:42.360] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C12.dat
[15:44:42.366] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C13.dat
[15:44:42.371] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C14.dat
[15:44:42.379] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1133_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C15.dat
[15:44:42.386] <TB2> INFO: PixTestTrim80::trimTest() done
[15:44:42.386] <TB2> INFO: vtrim: 127 105 119 107 112 111 126 85 109 98 93 105 108 104 102 94
[15:44:42.386] <TB2> INFO: vthrcomp: 80 75 81 82 90 79 76 63 83 75 72 75 79 76 85 87
[15:44:42.386] <TB2> INFO: vcal mean: 79.87 79.98 79.94 79.93 79.99 79.96 79.95 79.89 79.95 80.00 79.97 79.93 79.95 80.00 79.95 79.95
[15:44:42.386] <TB2> INFO: vcal RMS: 2.61 0.74 0.79 0.82 0.92 0.72 0.93 0.71 0.84 0.73 0.76 0.86 0.78 0.83 1.50 0.79
[15:44:42.386] <TB2> INFO: bits mean: 10.35 9.58 10.76 10.76 9.82 9.63 10.15 10.43 10.42 9.29 9.48 9.63 9.87 9.49 10.11 10.07
[15:44:42.386] <TB2> INFO: bits RMS: 2.23 2.18 2.02 2.18 2.35 2.11 1.90 2.34 2.30 2.36 2.42 2.26 2.11 2.17 2.45 2.54
[15:44:42.393] <TB2> INFO: ----------------------------------------------------------------------
[15:44:42.393] <TB2> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[15:44:42.393] <TB2> INFO: ----------------------------------------------------------------------
[15:44:42.395] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[15:44:42.405] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:44:42.405] <TB2> INFO: run 1 of 1
[15:44:42.637] <TB2> INFO: Expecting 4160000 events.
[15:45:14.675] <TB2> INFO: 764225 events read in total (31447ms).
[15:45:46.370] <TB2> INFO: 1525935 events read in total (63142ms).
[15:46:17.851] <TB2> INFO: 2280745 events read in total (94623ms).
[15:46:49.145] <TB2> INFO: 3030975 events read in total (125917ms).
[15:47:20.739] <TB2> INFO: 3778120 events read in total (157511ms).
[15:47:37.018] <TB2> INFO: 4160000 events read in total (173790ms).
[15:47:37.069] <TB2> INFO: Test took 174664ms.
[15:48:01.114] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[15:48:01.124] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:48:01.124] <TB2> INFO: run 1 of 1
[15:48:01.357] <TB2> INFO: Expecting 5324800 events.
[15:48:31.883] <TB2> INFO: 680785 events read in total (29935ms).
[15:49:01.520] <TB2> INFO: 1359335 events read in total (59572ms).
[15:49:31.489] <TB2> INFO: 2036720 events read in total (89541ms).
[15:50:01.185] <TB2> INFO: 2711545 events read in total (119237ms).
[15:50:30.798] <TB2> INFO: 3382990 events read in total (148850ms).
[15:51:00.119] <TB2> INFO: 4054520 events read in total (178171ms).
[15:51:29.715] <TB2> INFO: 4724810 events read in total (207767ms).
[15:51:56.203] <TB2> INFO: 5324800 events read in total (234255ms).
[15:51:56.280] <TB2> INFO: Test took 235156ms.
[15:52:30.351] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 215 (-1/-1) hits flags = 528 (plus default)
[15:52:30.361] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:52:30.361] <TB2> INFO: run 1 of 1
[15:52:30.621] <TB2> INFO: Expecting 4492800 events.
[15:53:01.906] <TB2> INFO: 717775 events read in total (30693ms).
[15:53:32.402] <TB2> INFO: 1432940 events read in total (61189ms).
[15:54:02.900] <TB2> INFO: 2144930 events read in total (91687ms).
[15:54:33.065] <TB2> INFO: 2852245 events read in total (121852ms).
[15:55:03.468] <TB2> INFO: 3558330 events read in total (152255ms).
[15:55:34.078] <TB2> INFO: 4263380 events read in total (182865ms).
[15:55:44.352] <TB2> INFO: 4492800 events read in total (193139ms).
[15:55:44.431] <TB2> INFO: Test took 194070ms.
[15:56:14.943] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 217 (-1/-1) hits flags = 528 (plus default)
[15:56:14.956] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:56:14.956] <TB2> INFO: run 1 of 1
[15:56:15.243] <TB2> INFO: Expecting 4534400 events.
[15:56:46.333] <TB2> INFO: 715930 events read in total (30499ms).
[15:57:16.735] <TB2> INFO: 1429415 events read in total (60901ms).
[15:57:47.207] <TB2> INFO: 2139435 events read in total (91373ms).
[15:58:17.479] <TB2> INFO: 2844760 events read in total (121645ms).
[15:58:47.921] <TB2> INFO: 3548810 events read in total (152087ms).
[15:59:18.370] <TB2> INFO: 4251885 events read in total (182536ms).
[15:59:30.696] <TB2> INFO: 4534400 events read in total (194862ms).
[15:59:30.761] <TB2> INFO: Test took 195805ms.
[16:00:01.252] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 217 (-1/-1) hits flags = 528 (plus default)
[16:00:01.262] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:00:01.262] <TB2> INFO: run 1 of 1
[16:00:01.496] <TB2> INFO: Expecting 4534400 events.
[16:00:32.667] <TB2> INFO: 715975 events read in total (30580ms).
[16:01:03.275] <TB2> INFO: 1429350 events read in total (61188ms).
[16:01:33.499] <TB2> INFO: 2139350 events read in total (91412ms).
[16:02:03.653] <TB2> INFO: 2844710 events read in total (121566ms).
[16:02:34.697] <TB2> INFO: 3548760 events read in total (152610ms).
[16:03:05.537] <TB2> INFO: 4251875 events read in total (183450ms).
[16:03:18.236] <TB2> INFO: 4534400 events read in total (196149ms).
[16:03:18.295] <TB2> INFO: Test took 197032ms.
[16:03:45.814] <TB2> INFO: PixTestTrim80::trimBitTest() done
[16:03:45.815] <TB2> INFO: PixTestTrim80::doTest() done, duration: 2431 seconds
[16:03:46.450] <TB2> INFO: enter test to run
[16:03:46.450] <TB2> INFO: test: exit no parameter change
[16:03:46.548] <TB2> QUIET: Connection to board 156 closed.
[16:03:46.549] <TB2> INFO: pXar: this is the end, my friend