[13:58:31.943] <TB0> INFO: *** Welcome to pxar ***
[13:58:31.943] <TB0> INFO: *** Today: 2016/11/07
[13:58:31.949] <TB0> INFO: *** Version: c8ba-dirty
[13:58:31.949] <TB0> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C15.dat
[13:58:31.949] <TB0> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[13:58:31.949] <TB0> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//defaultMaskFile.dat
[13:58:31.949] <TB0> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters_C15.dat
[13:58:31.002] <TB0> INFO: clk: 4
[13:58:31.002] <TB0> INFO: ctr: 4
[13:58:31.002] <TB0> INFO: sda: 19
[13:58:31.002] <TB0> INFO: tin: 9
[13:58:31.002] <TB0> INFO: level: 15
[13:58:31.002] <TB0> INFO: triggerdelay: 0
[13:58:31.002] <TB0> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[13:58:31.002] <TB0> INFO: Log level: INFO
[13:58:32.010] <TB0> INFO: Found DTB DTB_WS6AYH
[13:58:32.017] <TB0> QUIET: Connection to board DTB_WS6AYH opened.
[13:58:32.019] <TB0> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 73
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WS6AYH
MAC address: 40D855118049
Hostname: pixelDTB073
Comment:
------------------------------------------------------
[13:58:32.021] <TB0> INFO: RPC call hashes of host and DTB match: 486171790
[13:58:33.500] <TB0> INFO: DUT info:
[13:58:33.500] <TB0> INFO: The DUT currently contains the following objects:
[13:58:33.500] <TB0> INFO: 4 TBM Cores tbm10c (4 ON)
[13:58:33.500] <TB0> INFO: TBM Core alpha (0): 7 registers set
[13:58:33.500] <TB0> INFO: TBM Core beta (1): 7 registers set
[13:58:33.500] <TB0> INFO: TBM Core alpha (2): 7 registers set
[13:58:33.500] <TB0> INFO: TBM Core beta (3): 7 registers set
[13:58:33.500] <TB0> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[13:58:33.500] <TB0> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.500] <TB0> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:58:33.901] <TB0> INFO: enter 'restricted' command line mode
[13:58:33.901] <TB0> INFO: enter test to run
[13:58:33.901] <TB0> INFO: test: pretest no parameter change
[13:58:33.901] <TB0> INFO: running: pretest
[13:58:34.432] <TB0> INFO: ######################################################################
[13:58:34.432] <TB0> INFO: PixTestPretest::doTest()
[13:58:34.432] <TB0> INFO: ######################################################################
[13:58:34.433] <TB0> INFO: ----------------------------------------------------------------------
[13:58:34.433] <TB0> INFO: PixTestPretest::programROC()
[13:58:34.433] <TB0> INFO: ----------------------------------------------------------------------
[13:58:52.446] <TB0> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:58:52.446] <TB0> INFO: IA differences per ROC: 17.7 20.1 17.7 16.9 18.5 19.3 18.5 21.7 21.7 20.1 17.7 20.1 18.5 19.3 16.9 21.7
[13:58:52.480] <TB0> INFO: ----------------------------------------------------------------------
[13:58:52.480] <TB0> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:58:52.480] <TB0> INFO: ----------------------------------------------------------------------
[13:58:58.653] <TB0> INFO: PixTestPretest::setVana() done, Module Ia 385.1 mA = 24.0688 mA/ROC
[13:58:58.653] <TB0> INFO: i(loss) [mA/ROC]: 19.3 18.5 19.3 19.3 18.5 19.3 19.3 19.3 19.3 18.5 18.5 19.3 18.5 18.5 19.3 18.5
[13:58:58.679] <TB0> INFO: ----------------------------------------------------------------------
[13:58:58.679] <TB0> INFO: PixTestPretest::findTiming()
[13:58:58.680] <TB0> INFO: ----------------------------------------------------------------------
[13:58:58.680] <TB0> INFO: PixTestCmd::init()

[13:59:30.007] <TB0> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[13:59:30.007] <TB0> INFO: (success/tries = 100/100), width = 4
[13:59:31.521] <TB0> INFO: ----------------------------------------------------------------------
[13:59:31.521] <TB0> INFO: PixTestPretest::findWorkingPixel()
[13:59:31.521] <TB0> INFO: ----------------------------------------------------------------------
[13:59:31.613] <TB0> INFO: Expecting 231680 events.
[13:59:41.328] <TB0> INFO: 231680 events read in total (9124ms).
[13:59:41.335] <TB0> INFO: Test took 9812ms.
[13:59:41.580] <TB0> INFO: Found working pixel in all ROCs: col/row = 12/22
[13:59:41.611] <TB0> INFO: ----------------------------------------------------------------------
[13:59:41.611] <TB0> INFO: PixTestPretest::setVthrCompCalDel()
[13:59:41.611] <TB0> INFO: ----------------------------------------------------------------------
[13:59:41.703] <TB0> INFO: Expecting 231680 events.
[13:59:51.380] <TB0> INFO: 231680 events read in total (9085ms).
[13:59:51.390] <TB0> INFO: Test took 9776ms.
[13:59:51.650] <TB0> INFO: PixTestPretest::setVthrCompCalDel() done
[13:59:51.650] <TB0> INFO: CalDel: 76 83 93 88 82 100 79 84 88 88 83 101 91 73 82 112
[13:59:51.650] <TB0> INFO: VthrComp: 51 51 51 51 54 51 51 53 51 51 57 51 51 51 55 51
[13:59:51.652] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C0.dat
[13:59:51.652] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C1.dat
[13:59:51.652] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C2.dat
[13:59:51.652] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C3.dat
[13:59:51.652] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C4.dat
[13:59:51.652] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C5.dat
[13:59:51.652] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C6.dat
[13:59:51.652] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C7.dat
[13:59:51.652] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C8.dat
[13:59:51.652] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C9.dat
[13:59:51.653] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C10.dat
[13:59:51.653] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C11.dat
[13:59:51.653] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C12.dat
[13:59:51.653] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C13.dat
[13:59:51.653] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C14.dat
[13:59:51.653] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters_C15.dat
[13:59:51.653] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[13:59:51.653] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[13:59:51.653] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[13:59:51.653] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[13:59:51.653] <TB0> INFO: PixTestPretest::doTest() done, duration: 77 seconds
[13:59:51.760] <TB0> INFO: enter test to run
[13:59:51.760] <TB0> INFO: test: fulltest no parameter change
[13:59:51.760] <TB0> INFO: running: fulltest
[13:59:51.760] <TB0> INFO: ######################################################################
[13:59:51.760] <TB0> INFO: PixTestFullTest::doTest()
[13:59:51.760] <TB0> INFO: ######################################################################
[13:59:51.761] <TB0> INFO: ######################################################################
[13:59:51.761] <TB0> INFO: PixTestAlive::doTest()
[13:59:51.761] <TB0> INFO: ######################################################################
[13:59:51.763] <TB0> INFO: ----------------------------------------------------------------------
[13:59:51.763] <TB0> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:59:51.763] <TB0> INFO: ----------------------------------------------------------------------
[13:59:51.996] <TB0> INFO: Expecting 41600 events.
[13:59:55.451] <TB0> INFO: 41600 events read in total (2863ms).
[13:59:55.452] <TB0> INFO: Test took 3688ms.
[13:59:55.682] <TB0> INFO: PixTestAlive::aliveTest() done
[13:59:55.682] <TB0> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 16 0 0 0 0 0 0
[13:59:55.683] <TB0> INFO: ----------------------------------------------------------------------
[13:59:55.683] <TB0> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:59:55.683] <TB0> INFO: ----------------------------------------------------------------------
[13:59:55.934] <TB0> INFO: Expecting 41600 events.
[13:59:58.853] <TB0> INFO: 41600 events read in total (2327ms).
[13:59:58.853] <TB0> INFO: Test took 3169ms.
[13:59:58.853] <TB0> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[13:59:59.091] <TB0> INFO: PixTestAlive::maskTest() done
[13:59:59.091] <TB0> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:59:59.092] <TB0> INFO: ----------------------------------------------------------------------
[13:59:59.092] <TB0> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:59:59.092] <TB0> INFO: ----------------------------------------------------------------------
[13:59:59.327] <TB0> INFO: Expecting 41600 events.
[14:00:02.811] <TB0> INFO: 41600 events read in total (2893ms).
[14:00:02.812] <TB0> INFO: Test took 3718ms.
[14:00:03.038] <TB0> INFO: PixTestAlive::addressDecodingTest() done
[14:00:03.038] <TB0> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:00:03.038] <TB0> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[14:00:03.038] <TB0> INFO: Decoding statistics:
[14:00:03.038] <TB0> INFO: General information:
[14:00:03.038] <TB0> INFO: 16bit words read: 0
[14:00:03.038] <TB0> INFO: valid events total: 0
[14:00:03.038] <TB0> INFO: empty events: 0
[14:00:03.038] <TB0> INFO: valid events with pixels: 0
[14:00:03.038] <TB0> INFO: valid pixel hits: 0
[14:00:03.038] <TB0> INFO: Event errors: 0
[14:00:03.038] <TB0> INFO: start marker: 0
[14:00:03.038] <TB0> INFO: stop marker: 0
[14:00:03.038] <TB0> INFO: overflow: 0
[14:00:03.038] <TB0> INFO: invalid 5bit words: 0
[14:00:03.038] <TB0> INFO: invalid XOR eye diagram: 0
[14:00:03.038] <TB0> INFO: frame (failed synchr.): 0
[14:00:03.038] <TB0> INFO: idle data (no TBM trl): 0
[14:00:03.038] <TB0> INFO: no data (only TBM hdr): 0
[14:00:03.038] <TB0> INFO: TBM errors: 0
[14:00:03.039] <TB0> INFO: flawed TBM headers: 0
[14:00:03.039] <TB0> INFO: flawed TBM trailers: 0
[14:00:03.039] <TB0> INFO: event ID mismatches: 0
[14:00:03.039] <TB0> INFO: ROC errors: 0
[14:00:03.039] <TB0> INFO: missing ROC header(s): 0
[14:00:03.039] <TB0> INFO: misplaced readback start: 0
[14:00:03.039] <TB0> INFO: Pixel decoding errors: 0
[14:00:03.039] <TB0> INFO: pixel data incomplete: 0
[14:00:03.039] <TB0> INFO: pixel address: 0
[14:00:03.039] <TB0> INFO: pulse height fill bit: 0
[14:00:03.039] <TB0> INFO: buffer corruption: 0
[14:00:03.045] <TB0> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C15.dat
[14:00:03.046] <TB0> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[14:00:03.046] <TB0> INFO: ######################################################################
[14:00:03.046] <TB0> INFO: PixTestReadback::doTest()
[14:00:03.046] <TB0> INFO: ######################################################################
[14:00:03.046] <TB0> INFO: ----------------------------------------------------------------------
[14:00:03.046] <TB0> INFO: PixTestReadback::CalibrateVd()
[14:00:03.046] <TB0> INFO: ----------------------------------------------------------------------
[14:00:12.000] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C0.dat
[14:00:12.000] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C1.dat
[14:00:12.000] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C2.dat
[14:00:12.001] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C3.dat
[14:00:12.001] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C4.dat
[14:00:12.001] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C5.dat
[14:00:12.001] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C6.dat
[14:00:12.001] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C7.dat
[14:00:12.001] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C8.dat
[14:00:12.001] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C9.dat
[14:00:12.001] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C10.dat
[14:00:12.001] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C11.dat
[14:00:12.001] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C12.dat
[14:00:12.001] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C13.dat
[14:00:12.001] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C14.dat
[14:00:12.002] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C15.dat
[14:00:13.028] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[14:00:13.028] <TB0> INFO: ----------------------------------------------------------------------
[14:00:13.028] <TB0> INFO: PixTestReadback::CalibrateVa()
[14:00:13.028] <TB0> INFO: ----------------------------------------------------------------------
[14:00:22.920] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C0.dat
[14:00:22.920] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C1.dat
[14:00:22.920] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C2.dat
[14:00:22.920] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C3.dat
[14:00:22.920] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C4.dat
[14:00:22.921] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C5.dat
[14:00:22.921] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C6.dat
[14:00:22.921] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C7.dat
[14:00:22.921] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C8.dat
[14:00:22.921] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C9.dat
[14:00:22.921] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C10.dat
[14:00:22.921] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C11.dat
[14:00:22.921] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C12.dat
[14:00:22.921] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C13.dat
[14:00:22.921] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C14.dat
[14:00:22.921] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C15.dat
[14:00:22.948] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[14:00:22.948] <TB0> INFO: ----------------------------------------------------------------------
[14:00:22.948] <TB0> INFO: PixTestReadback::readbackVbg()
[14:00:22.948] <TB0> INFO: ----------------------------------------------------------------------
[14:00:30.586] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[14:00:30.586] <TB0> INFO: ----------------------------------------------------------------------
[14:00:30.586] <TB0> INFO: PixTestReadback::getCalibratedVbg()
[14:00:30.586] <TB0> INFO: ----------------------------------------------------------------------
[14:00:30.586] <TB0> INFO: Vbg will be calibrated using Vd calibration
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 164.9calibrated Vbg = 1.20123 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 157calibrated Vbg = 1.20097 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 154.9calibrated Vbg = 1.18651 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 155.8calibrated Vbg = 1.18954 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 149calibrated Vbg = 1.19374 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 147.2calibrated Vbg = 1.19561 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 160.1calibrated Vbg = 1.19495 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 162.8calibrated Vbg = 1.19528 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 151.6calibrated Vbg = 1.19709 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 155.2calibrated Vbg = 1.19503 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 160calibrated Vbg = 1.18242 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 157.6calibrated Vbg = 1.18705 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 156.8calibrated Vbg = 1.19266 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 162.2calibrated Vbg = 1.19017 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 159.5calibrated Vbg = 1.19806 :::*/*/*/*/
[14:00:30.586] <TB0> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 157.8calibrated Vbg = 1.19704 :::*/*/*/*/
[14:00:30.589] <TB0> INFO: ----------------------------------------------------------------------
[14:00:30.589] <TB0> INFO: PixTestReadback::CalibrateIa()
[14:00:30.589] <TB0> INFO: ----------------------------------------------------------------------
[14:03:10.884] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C0.dat
[14:03:10.884] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C1.dat
[14:03:10.884] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C2.dat
[14:03:10.884] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C3.dat
[14:03:10.884] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C4.dat
[14:03:10.884] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C5.dat
[14:03:10.884] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C6.dat
[14:03:10.884] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C7.dat
[14:03:10.885] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C8.dat
[14:03:10.885] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C9.dat
[14:03:10.885] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C10.dat
[14:03:10.885] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C11.dat
[14:03:10.885] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C12.dat
[14:03:10.885] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C13.dat
[14:03:10.885] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C14.dat
[14:03:10.885] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//readbackCal_C15.dat
[14:03:10.912] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[14:03:10.913] <TB0> INFO: PixTestReadback::doTest() done
[14:03:10.914] <TB0> INFO: Decoding statistics:
[14:03:10.914] <TB0> INFO: General information:
[14:03:10.914] <TB0> INFO: 16bit words read: 1536
[14:03:10.914] <TB0> INFO: valid events total: 256
[14:03:10.914] <TB0> INFO: empty events: 256
[14:03:10.914] <TB0> INFO: valid events with pixels: 0
[14:03:10.914] <TB0> INFO: valid pixel hits: 0
[14:03:10.914] <TB0> INFO: Event errors: 0
[14:03:10.914] <TB0> INFO: start marker: 0
[14:03:10.914] <TB0> INFO: stop marker: 0
[14:03:10.914] <TB0> INFO: overflow: 0
[14:03:10.914] <TB0> INFO: invalid 5bit words: 0
[14:03:10.914] <TB0> INFO: invalid XOR eye diagram: 0
[14:03:10.914] <TB0> INFO: frame (failed synchr.): 0
[14:03:10.914] <TB0> INFO: idle data (no TBM trl): 0
[14:03:10.914] <TB0> INFO: no data (only TBM hdr): 0
[14:03:10.914] <TB0> INFO: TBM errors: 0
[14:03:10.914] <TB0> INFO: flawed TBM headers: 0
[14:03:10.914] <TB0> INFO: flawed TBM trailers: 0
[14:03:10.914] <TB0> INFO: event ID mismatches: 0
[14:03:10.914] <TB0> INFO: ROC errors: 0
[14:03:10.914] <TB0> INFO: missing ROC header(s): 0
[14:03:10.914] <TB0> INFO: misplaced readback start: 0
[14:03:10.914] <TB0> INFO: Pixel decoding errors: 0
[14:03:10.914] <TB0> INFO: pixel data incomplete: 0
[14:03:10.914] <TB0> INFO: pixel address: 0
[14:03:10.914] <TB0> INFO: pulse height fill bit: 0
[14:03:10.914] <TB0> INFO: buffer corruption: 0
[14:03:10.962] <TB0> INFO: ######################################################################
[14:03:10.962] <TB0> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[14:03:10.962] <TB0> INFO: ######################################################################
[14:03:10.965] <TB0> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[14:03:10.976] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:03:10.976] <TB0> INFO: run 1 of 1
[14:03:11.253] <TB0> INFO: Expecting 3120000 events.
[14:03:41.680] <TB0> INFO: 673755 events read in total (29836ms).











[14:04:11.578] <TB0> INFO: 1342050 events read in total (59734ms).











[14:04:41.297] <TB0> INFO: 2007875 events read in total (89453ms).











[14:05:11.156] <TB0> INFO: 2671895 events read in total (119312ms).











[14:05:31.445] <TB0> INFO: 3120000 events read in total (139601ms).
[14:05:31.519] <TB0> INFO: Test took 140544ms.
[14:05:58.131] <TB0> INFO: PixTestBBMap::doTest() done, duration: 167 seconds
[14:05:58.131] <TB0> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 0 10 0 0 1 0 0 0
[14:05:58.131] <TB0> INFO: separation cut (per ROC): 106 102 106 102 123 111 108 126 106 105 104 111 108 108 105 104
[14:05:58.131] <TB0> INFO: Decoding statistics:
[14:05:58.131] <TB0> INFO: General information:
[14:05:58.131] <TB0> INFO: 16bit words read: 0
[14:05:58.131] <TB0> INFO: valid events total: 0
[14:05:58.131] <TB0> INFO: empty events: 0
[14:05:58.131] <TB0> INFO: valid events with pixels: 0
[14:05:58.131] <TB0> INFO: valid pixel hits: 0
[14:05:58.131] <TB0> INFO: Event errors: 0
[14:05:58.131] <TB0> INFO: start marker: 0
[14:05:58.131] <TB0> INFO: stop marker: 0
[14:05:58.131] <TB0> INFO: overflow: 0
[14:05:58.131] <TB0> INFO: invalid 5bit words: 0
[14:05:58.131] <TB0> INFO: invalid XOR eye diagram: 0
[14:05:58.131] <TB0> INFO: frame (failed synchr.): 0
[14:05:58.131] <TB0> INFO: idle data (no TBM trl): 0
[14:05:58.131] <TB0> INFO: no data (only TBM hdr): 0
[14:05:58.131] <TB0> INFO: TBM errors: 0
[14:05:58.131] <TB0> INFO: flawed TBM headers: 0
[14:05:58.131] <TB0> INFO: flawed TBM trailers: 0
[14:05:58.131] <TB0> INFO: event ID mismatches: 0
[14:05:58.131] <TB0> INFO: ROC errors: 0
[14:05:58.131] <TB0> INFO: missing ROC header(s): 0
[14:05:58.131] <TB0> INFO: misplaced readback start: 0
[14:05:58.131] <TB0> INFO: Pixel decoding errors: 0
[14:05:58.131] <TB0> INFO: pixel data incomplete: 0
[14:05:58.131] <TB0> INFO: pixel address: 0
[14:05:58.131] <TB0> INFO: pulse height fill bit: 0
[14:05:58.131] <TB0> INFO: buffer corruption: 0
[14:05:58.172] <TB0> INFO: ######################################################################
[14:05:58.172] <TB0> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:05:58.172] <TB0> INFO: ######################################################################
[14:05:58.172] <TB0> INFO: ----------------------------------------------------------------------
[14:05:58.172] <TB0> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:05:58.172] <TB0> INFO: ----------------------------------------------------------------------
[14:05:58.172] <TB0> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[14:05:58.181] <TB0> INFO: dacScan split into 1 runs with ntrig = 50
[14:05:58.181] <TB0> INFO: run 1 of 1
[14:05:58.451] <TB0> INFO: Expecting 36608000 events.
[14:06:22.030] <TB0> INFO: 702450 events read in total (22988ms).
[14:06:44.204] <TB0> INFO: 1382250 events read in total (45162ms).
[14:07:06.842] <TB0> INFO: 2066900 events read in total (67800ms).
[14:07:29.120] <TB0> INFO: 2744900 events read in total (90078ms).
[14:07:51.871] <TB0> INFO: 3426650 events read in total (112829ms).
[14:08:14.429] <TB0> INFO: 4105200 events read in total (135387ms).
[14:08:36.001] <TB0> INFO: 4786250 events read in total (157959ms).
[14:08:59.483] <TB0> INFO: 5466850 events read in total (180441ms).
[14:09:22.053] <TB0> INFO: 6148400 events read in total (203011ms).
[14:09:44.430] <TB0> INFO: 6827050 events read in total (225388ms).
[14:10:06.738] <TB0> INFO: 7506600 events read in total (247696ms).
[14:10:29.387] <TB0> INFO: 8184300 events read in total (270345ms).
[14:10:52.282] <TB0> INFO: 8864100 events read in total (293240ms).
[14:11:14.849] <TB0> INFO: 9540050 events read in total (315807ms).
[14:11:37.472] <TB0> INFO: 10218050 events read in total (338430ms).
[14:11:59.794] <TB0> INFO: 10893250 events read in total (360752ms).
[14:12:22.515] <TB0> INFO: 11571000 events read in total (383473ms).
[14:12:44.899] <TB0> INFO: 12249600 events read in total (405857ms).
[14:13:07.416] <TB0> INFO: 12926950 events read in total (428374ms).
[14:13:30.006] <TB0> INFO: 13604800 events read in total (450964ms).
[14:13:52.391] <TB0> INFO: 14280750 events read in total (473349ms).
[14:14:15.095] <TB0> INFO: 14957700 events read in total (496053ms).
[14:14:37.496] <TB0> INFO: 15632350 events read in total (518454ms).
[14:15:00.078] <TB0> INFO: 16307300 events read in total (541036ms).
[14:15:22.777] <TB0> INFO: 16981850 events read in total (563735ms).
[14:15:45.337] <TB0> INFO: 17656850 events read in total (586295ms).
[14:16:07.877] <TB0> INFO: 18328350 events read in total (608835ms).
[14:16:30.407] <TB0> INFO: 19003200 events read in total (631365ms).
[14:16:53.291] <TB0> INFO: 19674200 events read in total (654250ms).
[14:17:16.091] <TB0> INFO: 20345650 events read in total (677049ms).
[14:17:38.550] <TB0> INFO: 21014400 events read in total (699508ms).
[14:18:01.229] <TB0> INFO: 21687850 events read in total (722187ms).
[14:18:23.558] <TB0> INFO: 22357950 events read in total (744516ms).
[14:18:46.025] <TB0> INFO: 23028900 events read in total (766983ms).
[14:19:08.580] <TB0> INFO: 23697550 events read in total (789538ms).
[14:19:31.315] <TB0> INFO: 24366350 events read in total (812273ms).
[14:19:53.827] <TB0> INFO: 25035650 events read in total (834785ms).
[14:20:16.394] <TB0> INFO: 25706750 events read in total (857352ms).
[14:20:39.006] <TB0> INFO: 26378350 events read in total (879964ms).
[14:21:01.474] <TB0> INFO: 27047250 events read in total (902432ms).
[14:21:23.942] <TB0> INFO: 27716600 events read in total (924900ms).
[14:21:46.354] <TB0> INFO: 28384450 events read in total (947312ms).
[14:22:08.785] <TB0> INFO: 29054050 events read in total (969743ms).
[14:22:31.260] <TB0> INFO: 29722000 events read in total (992218ms).
[14:22:54.323] <TB0> INFO: 30392150 events read in total (1015281ms).
[14:23:17.004] <TB0> INFO: 31058550 events read in total (1037962ms).
[14:23:39.457] <TB0> INFO: 31727100 events read in total (1060415ms).
[14:24:01.921] <TB0> INFO: 32396450 events read in total (1082879ms).
[14:24:24.472] <TB0> INFO: 33066400 events read in total (1105430ms).
[14:24:46.948] <TB0> INFO: 33734000 events read in total (1127906ms).
[14:25:09.600] <TB0> INFO: 34405750 events read in total (1150558ms).
[14:25:32.069] <TB0> INFO: 35075450 events read in total (1173027ms).
[14:25:54.602] <TB0> INFO: 35745000 events read in total (1195560ms).
[14:26:17.411] <TB0> INFO: 36425650 events read in total (1218369ms).
[14:26:23.618] <TB0> INFO: 36608000 events read in total (1224576ms).
[14:26:23.674] <TB0> INFO: Test took 1225492ms.
[14:26:24.105] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:25.998] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:27.848] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:29.751] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:31.732] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:33.511] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:35.206] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:37.255] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:39.092] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:40.669] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:42.181] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:44.153] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:45.919] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:47.813] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:49.687] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:51.530] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[14:26:53.441] <TB0> INFO: PixTestScurves::scurves() done
[14:26:53.441] <TB0> INFO: Vcal mean: 126.50 120.25 120.11 114.86 132.79 124.72 132.06 138.33 129.60 123.08 122.25 125.63 129.24 122.46 125.04 117.60
[14:26:53.441] <TB0> INFO: Vcal RMS: 5.95 6.32 6.10 5.26 7.22 5.47 5.86 5.82 6.31 9.79 6.72 7.49 6.25 5.61 6.48 5.33
[14:26:53.441] <TB0> INFO: PixTestScurves::fullTest() done, duration: 1255 seconds
[14:26:53.441] <TB0> INFO: Decoding statistics:
[14:26:53.442] <TB0> INFO: General information:
[14:26:53.442] <TB0> INFO: 16bit words read: 0
[14:26:53.442] <TB0> INFO: valid events total: 0
[14:26:53.442] <TB0> INFO: empty events: 0
[14:26:53.442] <TB0> INFO: valid events with pixels: 0
[14:26:53.442] <TB0> INFO: valid pixel hits: 0
[14:26:53.442] <TB0> INFO: Event errors: 0
[14:26:53.442] <TB0> INFO: start marker: 0
[14:26:53.442] <TB0> INFO: stop marker: 0
[14:26:53.442] <TB0> INFO: overflow: 0
[14:26:53.442] <TB0> INFO: invalid 5bit words: 0
[14:26:53.442] <TB0> INFO: invalid XOR eye diagram: 0
[14:26:53.442] <TB0> INFO: frame (failed synchr.): 0
[14:26:53.442] <TB0> INFO: idle data (no TBM trl): 0
[14:26:53.442] <TB0> INFO: no data (only TBM hdr): 0
[14:26:53.442] <TB0> INFO: TBM errors: 0
[14:26:53.442] <TB0> INFO: flawed TBM headers: 0
[14:26:53.442] <TB0> INFO: flawed TBM trailers: 0
[14:26:53.442] <TB0> INFO: event ID mismatches: 0
[14:26:53.442] <TB0> INFO: ROC errors: 0
[14:26:53.442] <TB0> INFO: missing ROC header(s): 0
[14:26:53.442] <TB0> INFO: misplaced readback start: 0
[14:26:53.442] <TB0> INFO: Pixel decoding errors: 0
[14:26:53.442] <TB0> INFO: pixel data incomplete: 0
[14:26:53.442] <TB0> INFO: pixel address: 0
[14:26:53.442] <TB0> INFO: pulse height fill bit: 0
[14:26:53.442] <TB0> INFO: buffer corruption: 0
[14:26:53.506] <TB0> INFO: ######################################################################
[14:26:53.506] <TB0> INFO: PixTestTrim::doTest()
[14:26:53.506] <TB0> INFO: ######################################################################
[14:26:53.507] <TB0> INFO: ----------------------------------------------------------------------
[14:26:53.507] <TB0> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[14:26:53.507] <TB0> INFO: ----------------------------------------------------------------------
[14:26:53.557] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:26:53.557] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:26:53.569] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:26:53.569] <TB0> INFO: run 1 of 1
[14:26:53.844] <TB0> INFO: Expecting 5025280 events.
[14:27:24.448] <TB0> INFO: 832120 events read in total (30009ms).
[14:27:54.394] <TB0> INFO: 1661848 events read in total (59955ms).
[14:28:24.197] <TB0> INFO: 2488736 events read in total (89758ms).
[14:28:54.021] <TB0> INFO: 3311496 events read in total (119582ms).
[14:29:23.773] <TB0> INFO: 4130336 events read in total (149334ms).
[14:29:53.197] <TB0> INFO: 4946616 events read in total (178758ms).
[14:29:56.353] <TB0> INFO: 5025280 events read in total (181914ms).
[14:29:56.402] <TB0> INFO: Test took 182832ms.
[14:30:14.113] <TB0> INFO: ROC 0 VthrComp = 124
[14:30:14.113] <TB0> INFO: ROC 1 VthrComp = 122
[14:30:14.113] <TB0> INFO: ROC 2 VthrComp = 123
[14:30:14.113] <TB0> INFO: ROC 3 VthrComp = 114
[14:30:14.113] <TB0> INFO: ROC 4 VthrComp = 133
[14:30:14.113] <TB0> INFO: ROC 5 VthrComp = 130
[14:30:14.114] <TB0> INFO: ROC 6 VthrComp = 131
[14:30:14.114] <TB0> INFO: ROC 7 VthrComp = 132
[14:30:14.114] <TB0> INFO: ROC 8 VthrComp = 133
[14:30:14.114] <TB0> INFO: ROC 9 VthrComp = 125
[14:30:14.115] <TB0> INFO: ROC 10 VthrComp = 119
[14:30:14.115] <TB0> INFO: ROC 11 VthrComp = 123
[14:30:14.115] <TB0> INFO: ROC 12 VthrComp = 128
[14:30:14.115] <TB0> INFO: ROC 13 VthrComp = 126
[14:30:14.115] <TB0> INFO: ROC 14 VthrComp = 123
[14:30:14.115] <TB0> INFO: ROC 15 VthrComp = 116
[14:30:14.393] <TB0> INFO: Expecting 41600 events.
[14:30:17.882] <TB0> INFO: 41600 events read in total (2898ms).
[14:30:17.882] <TB0> INFO: Test took 3765ms.
[14:30:17.891] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:30:17.891] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:30:17.900] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:30:17.900] <TB0> INFO: run 1 of 1
[14:30:18.178] <TB0> INFO: Expecting 5025280 events.
[14:30:44.396] <TB0> INFO: 592496 events read in total (25626ms).
[14:31:09.723] <TB0> INFO: 1184416 events read in total (50953ms).
[14:31:35.548] <TB0> INFO: 1776048 events read in total (76778ms).
[14:32:01.171] <TB0> INFO: 2367136 events read in total (102401ms).
[14:32:26.491] <TB0> INFO: 2956360 events read in total (127721ms).
[14:32:51.786] <TB0> INFO: 3543912 events read in total (153016ms).
[14:33:17.152] <TB0> INFO: 4130712 events read in total (178382ms).
[14:33:42.775] <TB0> INFO: 4717104 events read in total (204005ms).
[14:33:56.420] <TB0> INFO: 5025280 events read in total (217650ms).
[14:33:56.482] <TB0> INFO: Test took 218582ms.
[14:34:24.441] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 64.353 for pixel 20/8 mean/min/max = 48.5002/32.5576/64.4427
[14:34:24.442] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 61.1409 for pixel 9/18 mean/min/max = 46.9477/32.7432/61.1522
[14:34:24.442] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 60.5033 for pixel 11/2 mean/min/max = 46.506/32.4913/60.5208
[14:34:24.442] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 60.0784 for pixel 21/26 mean/min/max = 46.5061/32.8872/60.125
[14:34:24.442] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 62.9358 for pixel 4/75 mean/min/max = 48.3724/33.7139/63.0308
[14:34:24.443] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 58.7673 for pixel 33/7 mean/min/max = 45.2932/31.7883/58.7981
[14:34:24.443] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 62.8685 for pixel 25/7 mean/min/max = 48.2733/33.5303/63.0163
[14:34:24.443] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 73.0837 for pixel 9/20 mean/min/max = 56.2874/39.4527/73.1221
[14:34:24.444] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 63.5996 for pixel 21/9 mean/min/max = 48.5559/33.2388/63.8731
[14:34:24.444] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 64.7658 for pixel 23/4 mean/min/max = 47.3665/29.1356/65.5974
[14:34:24.444] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 64.7294 for pixel 34/0 mean/min/max = 48.2635/31.1344/65.3927
[14:34:24.444] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 62.8148 for pixel 0/15 mean/min/max = 46.9335/31.0302/62.8369
[14:34:24.445] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 63.0517 for pixel 35/8 mean/min/max = 46.9879/30.914/63.0617
[14:34:24.445] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 60.5085 for pixel 20/8 mean/min/max = 46.4409/32.3722/60.5096
[14:34:24.445] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 64.9132 for pixel 3/9 mean/min/max = 48.7204/32.52/64.9208
[14:34:24.446] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 62.1497 for pixel 43/0 mean/min/max = 47.1785/32.0835/62.2735
[14:34:24.446] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:34:24.534] <TB0> INFO: Expecting 411648 events.
[14:34:33.895] <TB0> INFO: 411648 events read in total (8769ms).
[14:34:33.903] <TB0> INFO: Expecting 411648 events.
[14:34:43.108] <TB0> INFO: 411648 events read in total (8802ms).
[14:34:43.118] <TB0> INFO: Expecting 411648 events.
[14:34:52.252] <TB0> INFO: 411648 events read in total (8731ms).
[14:34:52.269] <TB0> INFO: Expecting 411648 events.
[14:35:01.392] <TB0> INFO: 411648 events read in total (8720ms).
[14:35:01.411] <TB0> INFO: Expecting 411648 events.
[14:35:10.435] <TB0> INFO: 411648 events read in total (8622ms).
[14:35:10.457] <TB0> INFO: Expecting 411648 events.
[14:35:19.479] <TB0> INFO: 411648 events read in total (8619ms).
[14:35:19.499] <TB0> INFO: Expecting 411648 events.
[14:35:28.582] <TB0> INFO: 411648 events read in total (8680ms).
[14:35:28.604] <TB0> INFO: Expecting 411648 events.
[14:35:37.716] <TB0> INFO: 411648 events read in total (8709ms).
[14:35:37.741] <TB0> INFO: Expecting 411648 events.
[14:35:46.846] <TB0> INFO: 411648 events read in total (8700ms).
[14:35:46.873] <TB0> INFO: Expecting 411648 events.
[14:35:55.882] <TB0> INFO: 411648 events read in total (8606ms).
[14:35:55.927] <TB0> INFO: Expecting 411648 events.
[14:36:04.915] <TB0> INFO: 411648 events read in total (8585ms).
[14:36:04.949] <TB0> INFO: Expecting 411648 events.
[14:36:13.000] <TB0> INFO: 411648 events read in total (8648ms).
[14:36:14.050] <TB0> INFO: Expecting 411648 events.
[14:36:23.106] <TB0> INFO: 411648 events read in total (8653ms).
[14:36:23.144] <TB0> INFO: Expecting 411648 events.
[14:36:32.197] <TB0> INFO: 411648 events read in total (8649ms).
[14:36:32.239] <TB0> INFO: Expecting 411648 events.
[14:36:41.231] <TB0> INFO: 411648 events read in total (8589ms).
[14:36:41.277] <TB0> INFO: Expecting 411648 events.
[14:36:50.290] <TB0> INFO: 411648 events read in total (8610ms).
[14:36:50.353] <TB0> INFO: Test took 145907ms.
[14:36:51.014] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:36:51.027] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:36:51.027] <TB0> INFO: run 1 of 1
[14:36:51.261] <TB0> INFO: Expecting 5025280 events.
[14:37:17.244] <TB0> INFO: 595136 events read in total (25392ms).
[14:37:42.922] <TB0> INFO: 1187352 events read in total (51070ms).
[14:38:08.552] <TB0> INFO: 1778480 events read in total (76700ms).
[14:38:34.189] <TB0> INFO: 2371656 events read in total (102337ms).
[14:38:59.670] <TB0> INFO: 2964824 events read in total (127818ms).
[14:39:25.312] <TB0> INFO: 3559384 events read in total (153460ms).
[14:39:50.901] <TB0> INFO: 4148896 events read in total (179049ms).
[14:40:16.345] <TB0> INFO: 4739496 events read in total (204493ms).
[14:40:29.097] <TB0> INFO: 5025280 events read in total (217245ms).
[14:40:29.207] <TB0> INFO: Test took 218181ms.
[14:40:52.945] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 0.869256 .. 147.989647
[14:40:53.180] <TB0> INFO: Expecting 208000 events.
[14:41:02.571] <TB0> INFO: 208000 events read in total (8799ms).
[14:41:02.573] <TB0> INFO: Test took 9626ms.
[14:41:02.621] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 157 (-1/-1) hits flags = 528 (plus default)
[14:41:02.629] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:41:02.629] <TB0> INFO: run 1 of 1
[14:41:02.907] <TB0> INFO: Expecting 5258240 events.
[14:41:29.235] <TB0> INFO: 586304 events read in total (25736ms).
[14:41:54.720] <TB0> INFO: 1172776 events read in total (51221ms).
[14:42:19.827] <TB0> INFO: 1758344 events read in total (76328ms).
[14:42:45.285] <TB0> INFO: 2344152 events read in total (101786ms).
[14:43:10.314] <TB0> INFO: 2929720 events read in total (126815ms).
[14:43:35.484] <TB0> INFO: 3514840 events read in total (151985ms).
[14:44:00.903] <TB0> INFO: 4099720 events read in total (177404ms).
[14:44:25.769] <TB0> INFO: 4684456 events read in total (202270ms).
[14:44:51.287] <TB0> INFO: 5258240 events read in total (227788ms).
[14:44:51.372] <TB0> INFO: Test took 228743ms.
[14:45:17.319] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 27.415075 .. 46.530641
[14:45:17.555] <TB0> INFO: Expecting 208000 events.
[14:45:27.508] <TB0> INFO: 208000 events read in total (9362ms).
[14:45:27.509] <TB0> INFO: Test took 10188ms.
[14:45:27.559] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[14:45:27.570] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:45:27.570] <TB0> INFO: run 1 of 1
[14:45:27.857] <TB0> INFO: Expecting 1331200 events.
[14:45:55.983] <TB0> INFO: 663184 events read in total (27535ms).
[14:46:23.750] <TB0> INFO: 1322688 events read in total (55303ms).
[14:46:24.614] <TB0> INFO: 1331200 events read in total (56167ms).
[14:46:24.645] <TB0> INFO: Test took 57076ms.
[14:46:37.221] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 28.812518 .. 52.997234
[14:46:37.484] <TB0> INFO: Expecting 208000 events.
[14:46:47.135] <TB0> INFO: 208000 events read in total (9059ms).
[14:46:47.137] <TB0> INFO: Test took 9915ms.
[14:46:47.202] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 18 .. 62 (-1/-1) hits flags = 528 (plus default)
[14:46:47.214] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:46:47.214] <TB0> INFO: run 1 of 1
[14:46:47.492] <TB0> INFO: Expecting 1497600 events.
[14:47:16.881] <TB0> INFO: 635784 events read in total (28797ms).
[14:47:43.496] <TB0> INFO: 1270344 events read in total (55412ms).
[14:47:53.336] <TB0> INFO: 1497600 events read in total (65252ms).
[14:47:53.375] <TB0> INFO: Test took 66162ms.
[14:48:06.998] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 26.183251 .. 55.695918
[14:48:07.275] <TB0> INFO: Expecting 208000 events.
[14:48:17.120] <TB0> INFO: 208000 events read in total (9253ms).
[14:48:17.121] <TB0> INFO: Test took 10122ms.
[14:48:17.167] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 65 (-1/-1) hits flags = 528 (plus default)
[14:48:17.177] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:48:17.177] <TB0> INFO: run 1 of 1
[14:48:17.455] <TB0> INFO: Expecting 1664000 events.
[14:48:44.976] <TB0> INFO: 633424 events read in total (26929ms).
[14:49:11.848] <TB0> INFO: 1266360 events read in total (53801ms).
[14:49:28.908] <TB0> INFO: 1664000 events read in total (70861ms).
[14:49:28.938] <TB0> INFO: Test took 71761ms.
[14:49:42.827] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:49:42.827] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:49:42.836] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:49:42.836] <TB0> INFO: run 1 of 1
[14:49:43.108] <TB0> INFO: Expecting 1364480 events.
[14:50:11.551] <TB0> INFO: 670128 events read in total (27852ms).
[14:50:38.904] <TB0> INFO: 1338912 events read in total (55205ms).
[14:50:40.331] <TB0> INFO: 1364480 events read in total (56633ms).
[14:50:40.355] <TB0> INFO: Test took 57519ms.
[14:50:53.114] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C0.dat
[14:50:53.114] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C1.dat
[14:50:53.115] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C2.dat
[14:50:53.115] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C3.dat
[14:50:53.115] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C4.dat
[14:50:53.115] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C5.dat
[14:50:53.115] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C6.dat
[14:50:53.115] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C7.dat
[14:50:53.115] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C8.dat
[14:50:53.115] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C9.dat
[14:50:53.115] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C10.dat
[14:50:53.115] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C11.dat
[14:50:53.115] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C12.dat
[14:50:53.115] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C13.dat
[14:50:53.115] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C14.dat
[14:50:53.116] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C15.dat
[14:50:53.116] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C0.dat
[14:50:53.122] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C1.dat
[14:50:53.128] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C2.dat
[14:50:53.134] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C3.dat
[14:50:53.142] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C4.dat
[14:50:53.149] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C5.dat
[14:50:53.157] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C6.dat
[14:50:53.164] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C7.dat
[14:50:53.173] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C8.dat
[14:50:53.180] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C9.dat
[14:50:53.186] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C10.dat
[14:50:53.192] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C11.dat
[14:50:53.198] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C12.dat
[14:50:53.204] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C13.dat
[14:50:53.210] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C14.dat
[14:50:53.216] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters35_C15.dat
[14:50:53.224] <TB0> INFO: PixTestTrim::trimTest() done
[14:50:53.224] <TB0> INFO: vtrim: 150 143 147 142 142 130 150 209 168 145 123 118 153 150 143 143
[14:50:53.224] <TB0> INFO: vthrcomp: 124 122 123 114 133 130 131 132 133 125 119 123 128 126 123 116
[14:50:53.224] <TB0> INFO: vcal mean: 35.34 35.03 35.61 35.03 35.25 35.02 35.43 35.85 35.19 35.33 35.75 35.04 35.48 35.01 35.31 35.00
[14:50:53.224] <TB0> INFO: vcal RMS: 1.45 1.13 1.82 1.16 1.38 1.05 1.59 2.25 1.45 1.92 1.97 1.29 1.80 1.12 1.43 1.14
[14:50:53.224] <TB0> INFO: bits mean: 9.48 9.52 10.37 9.86 9.00 10.07 9.66 8.54 9.61 10.18 10.16 9.64 10.51 10.37 9.36 9.74
[14:50:53.224] <TB0> INFO: bits RMS: 2.61 2.54 2.32 2.45 2.60 2.53 2.45 2.11 2.37 2.25 2.50 2.67 2.37 2.25 2.62 2.54
[14:50:53.232] <TB0> INFO: ----------------------------------------------------------------------
[14:50:53.232] <TB0> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:50:53.232] <TB0> INFO: ----------------------------------------------------------------------
[14:50:53.234] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:50:53.243] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:50:53.243] <TB0> INFO: run 1 of 1
[14:50:53.483] <TB0> INFO: Expecting 4160000 events.
[14:51:25.905] <TB0> INFO: 770190 events read in total (31830ms).
[14:51:57.324] <TB0> INFO: 1533315 events read in total (63249ms).
[14:52:28.875] <TB0> INFO: 2291390 events read in total (94800ms).
[14:53:00.436] <TB0> INFO: 3044185 events read in total (126361ms).
[14:53:31.737] <TB0> INFO: 3795160 events read in total (157662ms).
[14:53:47.361] <TB0> INFO: 4160000 events read in total (173286ms).
[14:53:47.433] <TB0> INFO: Test took 174190ms.
[14:54:13.580] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[14:54:13.591] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:54:13.591] <TB0> INFO: run 1 of 1
[14:54:13.823] <TB0> INFO: Expecting 4430400 events.
[14:54:44.974] <TB0> INFO: 727720 events read in total (30559ms).
[14:55:15.588] <TB0> INFO: 1450250 events read in total (61173ms).
[14:55:46.319] <TB0> INFO: 2170270 events read in total (91904ms).
[14:56:16.740] <TB0> INFO: 2885875 events read in total (122325ms).
[14:56:47.164] <TB0> INFO: 3599400 events read in total (152749ms).
[14:57:17.764] <TB0> INFO: 4312450 events read in total (183349ms).
[14:57:22.990] <TB0> INFO: 4430400 events read in total (188575ms).
[14:57:23.043] <TB0> INFO: Test took 189452ms.
[14:57:51.853] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 216 (-1/-1) hits flags = 528 (plus default)
[14:57:51.861] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:57:51.862] <TB0> INFO: run 1 of 1
[14:57:52.095] <TB0> INFO: Expecting 4513600 events.
[14:58:23.661] <TB0> INFO: 723280 events read in total (30975ms).
[14:58:54.359] <TB0> INFO: 1441435 events read in total (61673ms).
[14:59:25.093] <TB0> INFO: 2157835 events read in total (92407ms).
[14:59:55.662] <TB0> INFO: 2869730 events read in total (122976ms).
[15:00:26.193] <TB0> INFO: 3579160 events read in total (153507ms).
[15:00:56.921] <TB0> INFO: 4288075 events read in total (184235ms).
[15:01:07.184] <TB0> INFO: 4513600 events read in total (194498ms).
[15:01:07.248] <TB0> INFO: Test took 195386ms.
[15:01:39.140] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 216 (-1/-1) hits flags = 528 (plus default)
[15:01:39.151] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[15:01:39.151] <TB0> INFO: run 1 of 1
[15:01:39.432] <TB0> INFO: Expecting 4513600 events.
[15:02:10.625] <TB0> INFO: 723530 events read in total (30601ms).
[15:02:41.239] <TB0> INFO: 1441875 events read in total (61215ms).
[15:03:11.910] <TB0> INFO: 2158685 events read in total (91886ms).
[15:03:42.078] <TB0> INFO: 2870855 events read in total (122054ms).
[15:04:12.418] <TB0> INFO: 3580445 events read in total (152394ms).
[15:04:43.010] <TB0> INFO: 4289770 events read in total (182986ms).
[15:04:53.288] <TB0> INFO: 4513600 events read in total (193264ms).
[15:04:53.366] <TB0> INFO: Test took 194215ms.
[15:05:22.696] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 217 (-1/-1) hits flags = 528 (plus default)
[15:05:22.707] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[15:05:22.707] <TB0> INFO: run 1 of 1
[15:05:22.947] <TB0> INFO: Expecting 4534400 events.
[15:05:53.002] <TB0> INFO: 722500 events read in total (30464ms).
[15:06:24.473] <TB0> INFO: 1440020 events read in total (60935ms).
[15:06:54.826] <TB0> INFO: 2155855 events read in total (91288ms).
[15:07:25.156] <TB0> INFO: 2867455 events read in total (121618ms).
[15:07:55.403] <TB0> INFO: 3576175 events read in total (151865ms).
[15:08:25.904] <TB0> INFO: 4284665 events read in total (182366ms).
[15:08:37.176] <TB0> INFO: 4534400 events read in total (193639ms).
[15:08:37.273] <TB0> INFO: Test took 194565ms.
[15:09:08.168] <TB0> INFO: PixTestTrim::trimBitTest() done
[15:09:08.170] <TB0> INFO: PixTestTrim::doTest() done, duration: 2534 seconds
[15:09:08.170] <TB0> INFO: Decoding statistics:
[15:09:08.170] <TB0> INFO: General information:
[15:09:08.170] <TB0> INFO: 16bit words read: 0
[15:09:08.170] <TB0> INFO: valid events total: 0
[15:09:08.170] <TB0> INFO: empty events: 0
[15:09:08.170] <TB0> INFO: valid events with pixels: 0
[15:09:08.170] <TB0> INFO: valid pixel hits: 0
[15:09:08.170] <TB0> INFO: Event errors: 0
[15:09:08.170] <TB0> INFO: start marker: 0
[15:09:08.170] <TB0> INFO: stop marker: 0
[15:09:08.170] <TB0> INFO: overflow: 0
[15:09:08.170] <TB0> INFO: invalid 5bit words: 0
[15:09:08.170] <TB0> INFO: invalid XOR eye diagram: 0
[15:09:08.170] <TB0> INFO: frame (failed synchr.): 0
[15:09:08.170] <TB0> INFO: idle data (no TBM trl): 0
[15:09:08.170] <TB0> INFO: no data (only TBM hdr): 0
[15:09:08.170] <TB0> INFO: TBM errors: 0
[15:09:08.170] <TB0> INFO: flawed TBM headers: 0
[15:09:08.170] <TB0> INFO: flawed TBM trailers: 0
[15:09:08.170] <TB0> INFO: event ID mismatches: 0
[15:09:08.170] <TB0> INFO: ROC errors: 0
[15:09:08.170] <TB0> INFO: missing ROC header(s): 0
[15:09:08.170] <TB0> INFO: misplaced readback start: 0
[15:09:08.170] <TB0> INFO: Pixel decoding errors: 0
[15:09:08.170] <TB0> INFO: pixel data incomplete: 0
[15:09:08.170] <TB0> INFO: pixel address: 0
[15:09:08.170] <TB0> INFO: pulse height fill bit: 0
[15:09:08.170] <TB0> INFO: buffer corruption: 0
[15:09:08.843] <TB0> INFO: ######################################################################
[15:09:08.843] <TB0> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[15:09:08.843] <TB0> INFO: ######################################################################
[15:09:09.078] <TB0> INFO: Expecting 41600 events.
[15:09:12.568] <TB0> INFO: 41600 events read in total (2899ms).
[15:09:12.569] <TB0> INFO: Test took 3724ms.
[15:09:13.029] <TB0> INFO: Expecting 41600 events.
[15:09:16.969] <TB0> INFO: 41600 events read in total (3348ms).
[15:09:16.970] <TB0> INFO: Test took 4199ms.
[15:09:17.319] <TB0> INFO: Expecting 41600 events.
[15:09:20.896] <TB0> INFO: 41600 events read in total (2986ms).
[15:09:20.897] <TB0> INFO: Test took 3899ms.
[15:09:21.189] <TB0> INFO: Expecting 41600 events.
[15:09:24.908] <TB0> INFO: 41600 events read in total (3128ms).
[15:09:24.909] <TB0> INFO: Test took 3985ms.
[15:09:25.199] <TB0> INFO: Expecting 41600 events.
[15:09:28.721] <TB0> INFO: 41600 events read in total (2930ms).
[15:09:28.722] <TB0> INFO: Test took 3788ms.
[15:09:29.013] <TB0> INFO: Expecting 41600 events.
[15:09:32.537] <TB0> INFO: 41600 events read in total (2933ms).
[15:09:32.538] <TB0> INFO: Test took 3790ms.
[15:09:32.828] <TB0> INFO: Expecting 41600 events.
[15:09:36.350] <TB0> INFO: 41600 events read in total (2930ms).
[15:09:36.351] <TB0> INFO: Test took 3788ms.
[15:09:36.639] <TB0> INFO: Expecting 41600 events.
[15:09:40.097] <TB0> INFO: 41600 events read in total (2866ms).
[15:09:40.098] <TB0> INFO: Test took 3724ms.
[15:09:40.395] <TB0> INFO: Expecting 41600 events.
[15:09:43.843] <TB0> INFO: 41600 events read in total (2856ms).
[15:09:43.844] <TB0> INFO: Test took 3720ms.
[15:09:44.131] <TB0> INFO: Expecting 41600 events.
[15:09:47.570] <TB0> INFO: 41600 events read in total (2847ms).
[15:09:47.571] <TB0> INFO: Test took 3705ms.
[15:09:47.860] <TB0> INFO: Expecting 41600 events.
[15:09:51.356] <TB0> INFO: 41600 events read in total (2905ms).
[15:09:51.357] <TB0> INFO: Test took 3762ms.
[15:09:51.646] <TB0> INFO: Expecting 41600 events.
[15:09:55.074] <TB0> INFO: 41600 events read in total (2837ms).
[15:09:55.075] <TB0> INFO: Test took 3694ms.
[15:09:55.363] <TB0> INFO: Expecting 41600 events.
[15:09:58.792] <TB0> INFO: 41600 events read in total (2837ms).
[15:09:58.793] <TB0> INFO: Test took 3694ms.
[15:09:59.081] <TB0> INFO: Expecting 41600 events.
[15:10:02.610] <TB0> INFO: 41600 events read in total (2937ms).
[15:10:02.611] <TB0> INFO: Test took 3794ms.
[15:10:02.899] <TB0> INFO: Expecting 41600 events.
[15:10:06.364] <TB0> INFO: 41600 events read in total (2874ms).
[15:10:06.364] <TB0> INFO: Test took 3730ms.
[15:10:06.653] <TB0> INFO: Expecting 41600 events.
[15:10:10.082] <TB0> INFO: 41600 events read in total (2838ms).
[15:10:10.083] <TB0> INFO: Test took 3695ms.
[15:10:10.381] <TB0> INFO: Expecting 41600 events.
[15:10:13.894] <TB0> INFO: 41600 events read in total (2922ms).
[15:10:13.894] <TB0> INFO: Test took 3788ms.
[15:10:14.183] <TB0> INFO: Expecting 41600 events.
[15:10:17.632] <TB0> INFO: 41600 events read in total (2858ms).
[15:10:17.632] <TB0> INFO: Test took 3714ms.
[15:10:17.920] <TB0> INFO: Expecting 41600 events.
[15:10:21.444] <TB0> INFO: 41600 events read in total (2932ms).
[15:10:21.445] <TB0> INFO: Test took 3789ms.
[15:10:21.733] <TB0> INFO: Expecting 41600 events.
[15:10:25.213] <TB0> INFO: 41600 events read in total (2888ms).
[15:10:25.214] <TB0> INFO: Test took 3745ms.
[15:10:25.502] <TB0> INFO: Expecting 41600 events.
[15:10:29.025] <TB0> INFO: 41600 events read in total (2931ms).
[15:10:29.026] <TB0> INFO: Test took 3788ms.
[15:10:29.314] <TB0> INFO: Expecting 41600 events.
[15:10:32.797] <TB0> INFO: 41600 events read in total (2892ms).
[15:10:32.798] <TB0> INFO: Test took 3749ms.
[15:10:33.092] <TB0> INFO: Expecting 41600 events.
[15:10:36.590] <TB0> INFO: 41600 events read in total (2906ms).
[15:10:36.591] <TB0> INFO: Test took 3768ms.
[15:10:36.879] <TB0> INFO: Expecting 41600 events.
[15:10:40.317] <TB0> INFO: 41600 events read in total (2846ms).
[15:10:40.318] <TB0> INFO: Test took 3704ms.
[15:10:40.619] <TB0> INFO: Expecting 41600 events.
[15:10:44.052] <TB0> INFO: 41600 events read in total (2841ms).
[15:10:44.053] <TB0> INFO: Test took 3709ms.
[15:10:44.341] <TB0> INFO: Expecting 41600 events.
[15:10:47.802] <TB0> INFO: 41600 events read in total (2869ms).
[15:10:47.803] <TB0> INFO: Test took 3727ms.
[15:10:48.103] <TB0> INFO: Expecting 41600 events.
[15:10:51.656] <TB0> INFO: 41600 events read in total (2962ms).
[15:10:51.656] <TB0> INFO: Test took 3830ms.
[15:10:51.949] <TB0> INFO: Expecting 41600 events.
[15:10:55.535] <TB0> INFO: 41600 events read in total (2995ms).
[15:10:55.536] <TB0> INFO: Test took 3852ms.
[15:10:55.825] <TB0> INFO: Expecting 2560 events.
[15:10:56.707] <TB0> INFO: 2560 events read in total (290ms).
[15:10:56.708] <TB0> INFO: Test took 1160ms.
[15:10:57.015] <TB0> INFO: Expecting 2560 events.
[15:10:57.901] <TB0> INFO: 2560 events read in total (294ms).
[15:10:57.901] <TB0> INFO: Test took 1193ms.
[15:10:58.209] <TB0> INFO: Expecting 2560 events.
[15:10:59.092] <TB0> INFO: 2560 events read in total (292ms).
[15:10:59.092] <TB0> INFO: Test took 1191ms.
[15:10:59.401] <TB0> INFO: Expecting 2560 events.
[15:11:00.285] <TB0> INFO: 2560 events read in total (293ms).
[15:11:00.285] <TB0> INFO: Test took 1192ms.
[15:11:00.593] <TB0> INFO: Expecting 2560 events.
[15:11:01.471] <TB0> INFO: 2560 events read in total (287ms).
[15:11:01.472] <TB0> INFO: Test took 1187ms.
[15:11:01.779] <TB0> INFO: Expecting 2560 events.
[15:11:02.657] <TB0> INFO: 2560 events read in total (286ms).
[15:11:02.657] <TB0> INFO: Test took 1185ms.
[15:11:02.965] <TB0> INFO: Expecting 2560 events.
[15:11:03.847] <TB0> INFO: 2560 events read in total (290ms).
[15:11:03.847] <TB0> INFO: Test took 1189ms.
[15:11:04.155] <TB0> INFO: Expecting 2560 events.
[15:11:05.034] <TB0> INFO: 2560 events read in total (288ms).
[15:11:05.034] <TB0> INFO: Test took 1187ms.
[15:11:05.342] <TB0> INFO: Expecting 2560 events.
[15:11:06.220] <TB0> INFO: 2560 events read in total (287ms).
[15:11:06.220] <TB0> INFO: Test took 1186ms.
[15:11:06.528] <TB0> INFO: Expecting 2560 events.
[15:11:07.406] <TB0> INFO: 2560 events read in total (287ms).
[15:11:07.406] <TB0> INFO: Test took 1186ms.
[15:11:07.714] <TB0> INFO: Expecting 2560 events.
[15:11:08.597] <TB0> INFO: 2560 events read in total (291ms).
[15:11:08.597] <TB0> INFO: Test took 1190ms.
[15:11:08.905] <TB0> INFO: Expecting 2560 events.
[15:11:09.790] <TB0> INFO: 2560 events read in total (293ms).
[15:11:09.791] <TB0> INFO: Test took 1193ms.
[15:11:10.098] <TB0> INFO: Expecting 2560 events.
[15:11:10.980] <TB0> INFO: 2560 events read in total (291ms).
[15:11:10.980] <TB0> INFO: Test took 1188ms.
[15:11:11.288] <TB0> INFO: Expecting 2560 events.
[15:11:12.171] <TB0> INFO: 2560 events read in total (291ms).
[15:11:12.171] <TB0> INFO: Test took 1191ms.
[15:11:12.479] <TB0> INFO: Expecting 2560 events.
[15:11:13.368] <TB0> INFO: 2560 events read in total (298ms).
[15:11:13.368] <TB0> INFO: Test took 1197ms.
[15:11:13.676] <TB0> INFO: Expecting 2560 events.
[15:11:14.558] <TB0> INFO: 2560 events read in total (290ms).
[15:11:14.558] <TB0> INFO: Test took 1190ms.
[15:11:14.561] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:14.867] <TB0> INFO: Expecting 655360 events.
[15:11:29.129] <TB0> INFO: 655360 events read in total (13671ms).
[15:11:29.139] <TB0> INFO: Expecting 655360 events.
[15:11:43.253] <TB0> INFO: 655360 events read in total (13711ms).
[15:11:43.268] <TB0> INFO: Expecting 655360 events.
[15:11:57.268] <TB0> INFO: 655360 events read in total (13597ms).
[15:11:57.286] <TB0> INFO: Expecting 655360 events.
[15:12:11.310] <TB0> INFO: 655360 events read in total (13621ms).
[15:12:11.341] <TB0> INFO: Expecting 655360 events.
[15:12:25.334] <TB0> INFO: 655360 events read in total (13590ms).
[15:12:25.373] <TB0> INFO: Expecting 655360 events.
[15:12:39.407] <TB0> INFO: 655360 events read in total (13631ms).
[15:12:39.451] <TB0> INFO: Expecting 655360 events.
[15:12:53.520] <TB0> INFO: 655360 events read in total (13666ms).
[15:12:53.567] <TB0> INFO: Expecting 655360 events.
[15:13:07.584] <TB0> INFO: 655360 events read in total (13614ms).
[15:13:07.624] <TB0> INFO: Expecting 655360 events.
[15:13:21.574] <TB0> INFO: 655360 events read in total (13547ms).
[15:13:21.620] <TB0> INFO: Expecting 655360 events.
[15:13:35.737] <TB0> INFO: 655360 events read in total (13714ms).
[15:13:35.793] <TB0> INFO: Expecting 655360 events.
[15:13:49.844] <TB0> INFO: 655360 events read in total (13648ms).
[15:13:49.917] <TB0> INFO: Expecting 655360 events.
[15:14:03.954] <TB0> INFO: 655360 events read in total (13634ms).
[15:14:04.034] <TB0> INFO: Expecting 655360 events.
[15:14:18.067] <TB0> INFO: 655360 events read in total (13630ms).
[15:14:18.165] <TB0> INFO: Expecting 655360 events.
[15:14:32.280] <TB0> INFO: 655360 events read in total (13712ms).
[15:14:32.372] <TB0> INFO: Expecting 655360 events.
[15:14:46.350] <TB0> INFO: 655360 events read in total (13575ms).
[15:14:46.437] <TB0> INFO: Expecting 655360 events.
[15:15:00.578] <TB0> INFO: 655360 events read in total (13738ms).
[15:15:00.678] <TB0> INFO: Test took 226117ms.
[15:15:00.757] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:15:01.022] <TB0> INFO: Expecting 655360 events.
[15:15:15.092] <TB0> INFO: 655360 events read in total (13479ms).
[15:15:15.104] <TB0> INFO: Expecting 655360 events.
[15:15:29.074] <TB0> INFO: 655360 events read in total (13567ms).
[15:15:29.087] <TB0> INFO: Expecting 655360 events.
[15:15:43.026] <TB0> INFO: 655360 events read in total (13536ms).
[15:15:43.045] <TB0> INFO: Expecting 655360 events.
[15:15:56.917] <TB0> INFO: 655360 events read in total (13469ms).
[15:15:56.942] <TB0> INFO: Expecting 655360 events.
[15:16:10.605] <TB0> INFO: 655360 events read in total (13260ms).
[15:16:10.640] <TB0> INFO: Expecting 655360 events.
[15:16:24.579] <TB0> INFO: 655360 events read in total (13536ms).
[15:16:24.610] <TB0> INFO: Expecting 655360 events.
[15:16:38.576] <TB0> INFO: 655360 events read in total (13563ms).
[15:16:38.610] <TB0> INFO: Expecting 655360 events.
[15:16:52.583] <TB0> INFO: 655360 events read in total (13570ms).
[15:16:52.625] <TB0> INFO: Expecting 655360 events.
[15:17:06.692] <TB0> INFO: 655360 events read in total (13664ms).
[15:17:06.750] <TB0> INFO: Expecting 655360 events.
[15:17:20.650] <TB0> INFO: 655360 events read in total (13497ms).
[15:17:20.708] <TB0> INFO: Expecting 655360 events.
[15:17:34.507] <TB0> INFO: 655360 events read in total (13396ms).
[15:17:34.567] <TB0> INFO: Expecting 655360 events.
[15:17:48.323] <TB0> INFO: 655360 events read in total (13353ms).
[15:17:48.409] <TB0> INFO: Expecting 655360 events.
[15:18:02.446] <TB0> INFO: 655360 events read in total (13634ms).
[15:18:02.531] <TB0> INFO: Expecting 655360 events.
[15:18:16.560] <TB0> INFO: 655360 events read in total (13626ms).
[15:18:16.651] <TB0> INFO: Expecting 655360 events.
[15:18:30.444] <TB0> INFO: 655360 events read in total (13390ms).
[15:18:30.535] <TB0> INFO: Expecting 655360 events.
[15:18:44.399] <TB0> INFO: 655360 events read in total (13461ms).
[15:18:44.499] <TB0> INFO: Test took 223742ms.
[15:18:44.655] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.660] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[15:18:44.664] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[15:18:44.669] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[15:18:44.673] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.678] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[15:18:44.682] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[15:18:44.687] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[15:18:44.691] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.696] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.700] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[15:18:44.705] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[15:18:44.709] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.714] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[15:18:44.718] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[15:18:44.723] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[15:18:44.727] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.732] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.737] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.741] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.746] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.750] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[15:18:44.755] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[15:18:44.759] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[15:18:44.764] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[15:18:44.769] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[15:18:44.773] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[15:18:44.778] <TB0> INFO: safety margin for low PH: adding 7, margin is now 27
[15:18:44.782] <TB0> INFO: safety margin for low PH: adding 8, margin is now 28
[15:18:44.787] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.792] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[15:18:44.796] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[15:18:44.801] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[15:18:44.805] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[15:18:44.810] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[15:18:44.814] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[15:18:44.819] <TB0> INFO: safety margin for low PH: adding 7, margin is now 27
[15:18:44.824] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.828] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[15:18:44.833] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[15:18:44.838] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[15:18:44.842] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.847] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.851] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.856] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[15:18:44.861] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[15:18:44.865] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[15:18:44.870] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[15:18:44.875] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[15:18:44.879] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[15:18:44.884] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[15:18:44.917] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C0.dat
[15:18:44.917] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C1.dat
[15:18:44.917] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C2.dat
[15:18:44.917] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C3.dat
[15:18:44.917] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C4.dat
[15:18:44.917] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C5.dat
[15:18:44.917] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C6.dat
[15:18:44.917] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C7.dat
[15:18:44.918] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C8.dat
[15:18:44.918] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C9.dat
[15:18:44.918] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C10.dat
[15:18:44.918] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C11.dat
[15:18:44.918] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C12.dat
[15:18:44.918] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C13.dat
[15:18:44.918] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C14.dat
[15:18:44.918] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters35_C15.dat
[15:18:45.196] <TB0> INFO: Expecting 41600 events.
[15:18:48.298] <TB0> INFO: 41600 events read in total (2510ms).
[15:18:48.298] <TB0> INFO: Test took 3377ms.
[15:18:48.743] <TB0> INFO: Expecting 41600 events.
[15:18:51.746] <TB0> INFO: 41600 events read in total (2411ms).
[15:18:51.747] <TB0> INFO: Test took 3237ms.
[15:18:52.191] <TB0> INFO: Expecting 41600 events.
[15:18:55.301] <TB0> INFO: 41600 events read in total (2519ms).
[15:18:55.302] <TB0> INFO: Test took 3343ms.
[15:18:55.516] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:18:55.605] <TB0> INFO: Expecting 2560 events.
[15:18:56.488] <TB0> INFO: 2560 events read in total (292ms).
[15:18:56.488] <TB0> INFO: Test took 972ms.
[15:18:56.490] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:18:56.796] <TB0> INFO: Expecting 2560 events.
[15:18:57.679] <TB0> INFO: 2560 events read in total (291ms).
[15:18:57.679] <TB0> INFO: Test took 1189ms.
[15:18:57.681] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:18:57.987] <TB0> INFO: Expecting 2560 events.
[15:18:58.874] <TB0> INFO: 2560 events read in total (295ms).
[15:18:58.874] <TB0> INFO: Test took 1193ms.
[15:18:58.876] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:18:59.182] <TB0> INFO: Expecting 2560 events.
[15:19:00.066] <TB0> INFO: 2560 events read in total (292ms).
[15:19:00.067] <TB0> INFO: Test took 1191ms.
[15:19:00.068] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:00.375] <TB0> INFO: Expecting 2560 events.
[15:19:01.259] <TB0> INFO: 2560 events read in total (293ms).
[15:19:01.259] <TB0> INFO: Test took 1191ms.
[15:19:01.261] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:01.567] <TB0> INFO: Expecting 2560 events.
[15:19:02.453] <TB0> INFO: 2560 events read in total (294ms).
[15:19:02.453] <TB0> INFO: Test took 1192ms.
[15:19:02.455] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:02.762] <TB0> INFO: Expecting 2560 events.
[15:19:03.644] <TB0> INFO: 2560 events read in total (291ms).
[15:19:03.645] <TB0> INFO: Test took 1190ms.
[15:19:03.646] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:03.953] <TB0> INFO: Expecting 2560 events.
[15:19:04.836] <TB0> INFO: 2560 events read in total (292ms).
[15:19:04.836] <TB0> INFO: Test took 1190ms.
[15:19:04.838] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:05.144] <TB0> INFO: Expecting 2560 events.
[15:19:06.023] <TB0> INFO: 2560 events read in total (287ms).
[15:19:06.024] <TB0> INFO: Test took 1186ms.
[15:19:06.025] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:06.331] <TB0> INFO: Expecting 2560 events.
[15:19:07.211] <TB0> INFO: 2560 events read in total (288ms).
[15:19:07.212] <TB0> INFO: Test took 1187ms.
[15:19:07.214] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:07.520] <TB0> INFO: Expecting 2560 events.
[15:19:08.399] <TB0> INFO: 2560 events read in total (288ms).
[15:19:08.400] <TB0> INFO: Test took 1186ms.
[15:19:08.402] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:08.708] <TB0> INFO: Expecting 2560 events.
[15:19:09.586] <TB0> INFO: 2560 events read in total (286ms).
[15:19:09.586] <TB0> INFO: Test took 1184ms.
[15:19:09.589] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:09.895] <TB0> INFO: Expecting 2560 events.
[15:19:10.779] <TB0> INFO: 2560 events read in total (292ms).
[15:19:10.780] <TB0> INFO: Test took 1191ms.
[15:19:10.783] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:11.088] <TB0> INFO: Expecting 2560 events.
[15:19:11.966] <TB0> INFO: 2560 events read in total (286ms).
[15:19:11.966] <TB0> INFO: Test took 1183ms.
[15:19:11.968] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:12.275] <TB0> INFO: Expecting 2560 events.
[15:19:13.157] <TB0> INFO: 2560 events read in total (291ms).
[15:19:13.157] <TB0> INFO: Test took 1189ms.
[15:19:13.159] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:13.465] <TB0> INFO: Expecting 2560 events.
[15:19:14.344] <TB0> INFO: 2560 events read in total (287ms).
[15:19:14.345] <TB0> INFO: Test took 1186ms.
[15:19:14.347] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:14.653] <TB0> INFO: Expecting 2560 events.
[15:19:15.532] <TB0> INFO: 2560 events read in total (287ms).
[15:19:15.532] <TB0> INFO: Test took 1186ms.
[15:19:15.534] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:15.841] <TB0> INFO: Expecting 2560 events.
[15:19:16.720] <TB0> INFO: 2560 events read in total (288ms).
[15:19:16.721] <TB0> INFO: Test took 1187ms.
[15:19:16.723] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:17.029] <TB0> INFO: Expecting 2560 events.
[15:19:17.911] <TB0> INFO: 2560 events read in total (290ms).
[15:19:17.911] <TB0> INFO: Test took 1188ms.
[15:19:17.913] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:18.219] <TB0> INFO: Expecting 2560 events.
[15:19:19.098] <TB0> INFO: 2560 events read in total (287ms).
[15:19:19.099] <TB0> INFO: Test took 1186ms.
[15:19:19.101] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:19.407] <TB0> INFO: Expecting 2560 events.
[15:19:20.285] <TB0> INFO: 2560 events read in total (286ms).
[15:19:20.285] <TB0> INFO: Test took 1184ms.
[15:19:20.287] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:20.594] <TB0> INFO: Expecting 2560 events.
[15:19:21.472] <TB0> INFO: 2560 events read in total (287ms).
[15:19:21.473] <TB0> INFO: Test took 1186ms.
[15:19:21.475] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:21.781] <TB0> INFO: Expecting 2560 events.
[15:19:22.663] <TB0> INFO: 2560 events read in total (291ms).
[15:19:22.663] <TB0> INFO: Test took 1188ms.
[15:19:22.666] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:22.972] <TB0> INFO: Expecting 2560 events.
[15:19:23.853] <TB0> INFO: 2560 events read in total (290ms).
[15:19:23.853] <TB0> INFO: Test took 1187ms.
[15:19:23.855] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:24.161] <TB0> INFO: Expecting 2560 events.
[15:19:25.047] <TB0> INFO: 2560 events read in total (294ms).
[15:19:25.048] <TB0> INFO: Test took 1193ms.
[15:19:25.050] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:25.356] <TB0> INFO: Expecting 2560 events.
[15:19:26.240] <TB0> INFO: 2560 events read in total (292ms).
[15:19:26.240] <TB0> INFO: Test took 1190ms.
[15:19:26.242] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:26.549] <TB0> INFO: Expecting 2560 events.
[15:19:27.432] <TB0> INFO: 2560 events read in total (291ms).
[15:19:27.432] <TB0> INFO: Test took 1190ms.
[15:19:27.434] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:27.741] <TB0> INFO: Expecting 2560 events.
[15:19:28.624] <TB0> INFO: 2560 events read in total (292ms).
[15:19:28.625] <TB0> INFO: Test took 1191ms.
[15:19:28.626] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:28.933] <TB0> INFO: Expecting 2560 events.
[15:19:29.817] <TB0> INFO: 2560 events read in total (292ms).
[15:19:29.817] <TB0> INFO: Test took 1191ms.
[15:19:29.819] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:30.125] <TB0> INFO: Expecting 2560 events.
[15:19:31.011] <TB0> INFO: 2560 events read in total (294ms).
[15:19:31.011] <TB0> INFO: Test took 1192ms.
[15:19:31.013] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:31.319] <TB0> INFO: Expecting 2560 events.
[15:19:32.202] <TB0> INFO: 2560 events read in total (292ms).
[15:19:32.203] <TB0> INFO: Test took 1190ms.
[15:19:32.205] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:19:32.511] <TB0> INFO: Expecting 2560 events.
[15:19:33.397] <TB0> INFO: 2560 events read in total (294ms).
[15:19:33.397] <TB0> INFO: Test took 1192ms.
[15:19:33.859] <TB0> INFO: PixTestPhOptimization::doTest() done, duration: 625 seconds
[15:19:33.859] <TB0> INFO: PH scale (per ROC): 37 35 45 60 34 43 49 45 42 48 31 41 38 45 45 31
[15:19:33.859] <TB0> INFO: PH offset (per ROC): 112 101 109 129 91 105 117 114 109 106 94 104 106 103 108 95
[15:19:33.865] <TB0> INFO: Decoding statistics:
[15:19:33.865] <TB0> INFO: General information:
[15:19:33.865] <TB0> INFO: 16bit words read: 127888
[15:19:33.865] <TB0> INFO: valid events total: 20480
[15:19:33.865] <TB0> INFO: empty events: 17976
[15:19:33.865] <TB0> INFO: valid events with pixels: 2504
[15:19:33.865] <TB0> INFO: valid pixel hits: 2504
[15:19:33.865] <TB0> INFO: Event errors: 0
[15:19:33.865] <TB0> INFO: start marker: 0
[15:19:33.865] <TB0> INFO: stop marker: 0
[15:19:33.865] <TB0> INFO: overflow: 0
[15:19:33.865] <TB0> INFO: invalid 5bit words: 0
[15:19:33.865] <TB0> INFO: invalid XOR eye diagram: 0
[15:19:33.865] <TB0> INFO: frame (failed synchr.): 0
[15:19:33.865] <TB0> INFO: idle data (no TBM trl): 0
[15:19:33.865] <TB0> INFO: no data (only TBM hdr): 0
[15:19:33.865] <TB0> INFO: TBM errors: 0
[15:19:33.865] <TB0> INFO: flawed TBM headers: 0
[15:19:33.865] <TB0> INFO: flawed TBM trailers: 0
[15:19:33.865] <TB0> INFO: event ID mismatches: 0
[15:19:33.865] <TB0> INFO: ROC errors: 0
[15:19:33.865] <TB0> INFO: missing ROC header(s): 0
[15:19:33.865] <TB0> INFO: misplaced readback start: 0
[15:19:33.865] <TB0> INFO: Pixel decoding errors: 0
[15:19:33.865] <TB0> INFO: pixel data incomplete: 0
[15:19:33.865] <TB0> INFO: pixel address: 0
[15:19:33.865] <TB0> INFO: pulse height fill bit: 0
[15:19:33.865] <TB0> INFO: buffer corruption: 0
[15:19:34.148] <TB0> INFO: ######################################################################
[15:19:34.148] <TB0> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:19:34.148] <TB0> INFO: ######################################################################
[15:19:34.159] <TB0> INFO: scanning low vcal = 10
[15:19:34.422] <TB0> INFO: Expecting 41600 events.
[15:19:37.976] <TB0> INFO: 41600 events read in total (2962ms).
[15:19:37.976] <TB0> INFO: Test took 3817ms.
[15:19:37.978] <TB0> INFO: scanning low vcal = 20
[15:19:38.277] <TB0> INFO: Expecting 41600 events.
[15:19:41.846] <TB0> INFO: 41600 events read in total (2978ms).
[15:19:41.847] <TB0> INFO: Test took 3869ms.
[15:19:41.849] <TB0> INFO: scanning low vcal = 30
[15:19:42.147] <TB0> INFO: Expecting 41600 events.
[15:19:45.795] <TB0> INFO: 41600 events read in total (3057ms).
[15:19:45.796] <TB0> INFO: Test took 3947ms.
[15:19:45.799] <TB0> INFO: scanning low vcal = 40
[15:19:46.075] <TB0> INFO: Expecting 41600 events.
[15:19:49.990] <TB0> INFO: 41600 events read in total (3323ms).
[15:19:49.991] <TB0> INFO: Test took 4192ms.
[15:19:49.994] <TB0> INFO: scanning low vcal = 50
[15:19:50.271] <TB0> INFO: Expecting 41600 events.
[15:19:54.247] <TB0> INFO: 41600 events read in total (3384ms).
[15:19:54.248] <TB0> INFO: Test took 4254ms.
[15:19:54.251] <TB0> INFO: scanning low vcal = 60
[15:19:54.527] <TB0> INFO: Expecting 41600 events.
[15:19:58.507] <TB0> INFO: 41600 events read in total (3388ms).
[15:19:58.507] <TB0> INFO: Test took 4256ms.
[15:19:58.510] <TB0> INFO: scanning low vcal = 70
[15:19:58.787] <TB0> INFO: Expecting 41600 events.
[15:20:02.723] <TB0> INFO: 41600 events read in total (3345ms).
[15:20:02.724] <TB0> INFO: Test took 4214ms.
[15:20:02.727] <TB0> INFO: scanning low vcal = 80
[15:20:03.003] <TB0> INFO: Expecting 41600 events.
[15:20:06.930] <TB0> INFO: 41600 events read in total (3335ms).
[15:20:06.931] <TB0> INFO: Test took 4204ms.
[15:20:06.934] <TB0> INFO: scanning low vcal = 90
[15:20:07.211] <TB0> INFO: Expecting 41600 events.
[15:20:11.152] <TB0> INFO: 41600 events read in total (3350ms).
[15:20:11.152] <TB0> INFO: Test took 4218ms.
[15:20:11.155] <TB0> INFO: scanning low vcal = 100
[15:20:11.432] <TB0> INFO: Expecting 41600 events.
[15:20:15.341] <TB0> INFO: 41600 events read in total (3318ms).
[15:20:15.342] <TB0> INFO: Test took 4187ms.
[15:20:15.345] <TB0> INFO: scanning low vcal = 110
[15:20:15.621] <TB0> INFO: Expecting 41600 events.
[15:20:19.564] <TB0> INFO: 41600 events read in total (3351ms).
[15:20:19.565] <TB0> INFO: Test took 4220ms.
[15:20:19.568] <TB0> INFO: scanning low vcal = 120
[15:20:19.844] <TB0> INFO: Expecting 41600 events.
[15:20:23.807] <TB0> INFO: 41600 events read in total (3371ms).
[15:20:23.807] <TB0> INFO: Test took 4239ms.
[15:20:23.811] <TB0> INFO: scanning low vcal = 130
[15:20:24.088] <TB0> INFO: Expecting 41600 events.
[15:20:28.030] <TB0> INFO: 41600 events read in total (3350ms).
[15:20:28.031] <TB0> INFO: Test took 4220ms.
[15:20:28.033] <TB0> INFO: scanning low vcal = 140
[15:20:28.310] <TB0> INFO: Expecting 41600 events.
[15:20:32.211] <TB0> INFO: 41600 events read in total (3309ms).
[15:20:32.212] <TB0> INFO: Test took 4178ms.
[15:20:32.214] <TB0> INFO: scanning low vcal = 150
[15:20:32.491] <TB0> INFO: Expecting 41600 events.
[15:20:36.482] <TB0> INFO: 41600 events read in total (3400ms).
[15:20:36.483] <TB0> INFO: Test took 4269ms.
[15:20:36.486] <TB0> INFO: scanning low vcal = 160
[15:20:36.763] <TB0> INFO: Expecting 41600 events.
[15:20:40.676] <TB0> INFO: 41600 events read in total (3321ms).
[15:20:40.677] <TB0> INFO: Test took 4191ms.
[15:20:40.680] <TB0> INFO: scanning low vcal = 170
[15:20:40.956] <TB0> INFO: Expecting 41600 events.
[15:20:44.867] <TB0> INFO: 41600 events read in total (3319ms).
[15:20:44.868] <TB0> INFO: Test took 4188ms.
[15:20:44.871] <TB0> INFO: scanning low vcal = 180
[15:20:45.148] <TB0> INFO: Expecting 41600 events.
[15:20:49.076] <TB0> INFO: 41600 events read in total (3337ms).
[15:20:49.076] <TB0> INFO: Test took 4205ms.
[15:20:49.079] <TB0> INFO: scanning low vcal = 190
[15:20:49.356] <TB0> INFO: Expecting 41600 events.
[15:20:53.268] <TB0> INFO: 41600 events read in total (3321ms).
[15:20:53.269] <TB0> INFO: Test took 4190ms.
[15:20:53.271] <TB0> INFO: scanning low vcal = 200
[15:20:53.549] <TB0> INFO: Expecting 41600 events.
[15:20:57.499] <TB0> INFO: 41600 events read in total (3358ms).
[15:20:57.500] <TB0> INFO: Test took 4229ms.
[15:20:57.503] <TB0> INFO: scanning low vcal = 210
[15:20:57.780] <TB0> INFO: Expecting 41600 events.
[15:21:01.731] <TB0> INFO: 41600 events read in total (3360ms).
[15:21:01.732] <TB0> INFO: Test took 4229ms.
[15:21:01.735] <TB0> INFO: scanning low vcal = 220
[15:21:02.011] <TB0> INFO: Expecting 41600 events.
[15:21:05.939] <TB0> INFO: 41600 events read in total (3336ms).
[15:21:05.940] <TB0> INFO: Test took 4205ms.
[15:21:05.942] <TB0> INFO: scanning low vcal = 230
[15:21:06.219] <TB0> INFO: Expecting 41600 events.
[15:21:10.176] <TB0> INFO: 41600 events read in total (3365ms).
[15:21:10.176] <TB0> INFO: Test took 4235ms.
[15:21:10.180] <TB0> INFO: scanning low vcal = 240
[15:21:10.456] <TB0> INFO: Expecting 41600 events.
[15:21:14.400] <TB0> INFO: 41600 events read in total (3352ms).
[15:21:14.401] <TB0> INFO: Test took 4221ms.
[15:21:14.404] <TB0> INFO: scanning low vcal = 250
[15:21:14.681] <TB0> INFO: Expecting 41600 events.
[15:21:18.615] <TB0> INFO: 41600 events read in total (3342ms).
[15:21:18.616] <TB0> INFO: Test took 4211ms.
[15:21:18.620] <TB0> INFO: scanning high vcal = 30 (= 210 in low range)
[15:21:18.895] <TB0> INFO: Expecting 41600 events.
[15:21:22.901] <TB0> INFO: 41600 events read in total (3414ms).
[15:21:22.902] <TB0> INFO: Test took 4282ms.
[15:21:22.905] <TB0> INFO: scanning high vcal = 50 (= 350 in low range)
[15:21:23.182] <TB0> INFO: Expecting 41600 events.
[15:21:27.109] <TB0> INFO: 41600 events read in total (3335ms).
[15:21:27.110] <TB0> INFO: Test took 4205ms.
[15:21:27.113] <TB0> INFO: scanning high vcal = 70 (= 490 in low range)
[15:21:27.390] <TB0> INFO: Expecting 41600 events.
[15:21:31.322] <TB0> INFO: 41600 events read in total (3340ms).
[15:21:31.323] <TB0> INFO: Test took 4210ms.
[15:21:31.325] <TB0> INFO: scanning high vcal = 90 (= 630 in low range)
[15:21:31.602] <TB0> INFO: Expecting 41600 events.
[15:21:35.539] <TB0> INFO: 41600 events read in total (3345ms).
[15:21:35.540] <TB0> INFO: Test took 4214ms.
[15:21:35.543] <TB0> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:21:35.819] <TB0> INFO: Expecting 41600 events.
[15:21:39.726] <TB0> INFO: 41600 events read in total (3315ms).
[15:21:39.727] <TB0> INFO: Test took 4184ms.
[15:21:40.198] <TB0> INFO: PixTestGainPedestal::measure() done
[15:22:18.641] <TB0> INFO: PixTestGainPedestal::fit() done
[15:22:18.641] <TB0> INFO: non-linearity mean: 0.937 0.931 0.934 0.986 0.924 0.935 0.983 0.967 0.933 0.952 0.924 0.948 0.927 0.959 0.958 1.054
[15:22:18.641] <TB0> INFO: non-linearity RMS: 0.077 0.129 0.070 0.002 0.121 0.086 0.003 0.018 0.068 0.041 0.144 0.065 0.113 0.026 0.043 0.140
[15:22:18.641] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[15:22:18.661] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[15:22:18.680] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[15:22:18.697] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[15:22:18.714] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[15:22:18.729] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[15:22:18.742] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[15:22:18.756] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[15:22:18.770] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[15:22:18.783] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[15:22:18.797] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[15:22:18.811] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[15:22:18.824] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[15:22:18.838] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[15:22:18.852] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[15:22:18.866] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[15:22:18.880] <TB0> INFO: PixTestGainPedestal::fullTest() done, duration: 164 seconds
[15:22:18.880] <TB0> INFO: Decoding statistics:
[15:22:18.880] <TB0> INFO: General information:
[15:22:18.880] <TB0> INFO: 16bit words read: 3215686
[15:22:18.880] <TB0> INFO: valid events total: 332800
[15:22:18.880] <TB0> INFO: empty events: 7146
[15:22:18.880] <TB0> INFO: valid events with pixels: 325654
[15:22:18.880] <TB0> INFO: valid pixel hits: 609443
[15:22:18.880] <TB0> INFO: Event errors: 0
[15:22:18.880] <TB0> INFO: start marker: 0
[15:22:18.880] <TB0> INFO: stop marker: 0
[15:22:18.880] <TB0> INFO: overflow: 0
[15:22:18.880] <TB0> INFO: invalid 5bit words: 0
[15:22:18.880] <TB0> INFO: invalid XOR eye diagram: 0
[15:22:18.880] <TB0> INFO: frame (failed synchr.): 0
[15:22:18.880] <TB0> INFO: idle data (no TBM trl): 0
[15:22:18.880] <TB0> INFO: no data (only TBM hdr): 0
[15:22:18.880] <TB0> INFO: TBM errors: 0
[15:22:18.880] <TB0> INFO: flawed TBM headers: 0
[15:22:18.880] <TB0> INFO: flawed TBM trailers: 0
[15:22:18.880] <TB0> INFO: event ID mismatches: 0
[15:22:18.880] <TB0> INFO: ROC errors: 0
[15:22:18.880] <TB0> INFO: missing ROC header(s): 0
[15:22:18.880] <TB0> INFO: misplaced readback start: 0
[15:22:18.880] <TB0> INFO: Pixel decoding errors: 0
[15:22:18.880] <TB0> INFO: pixel data incomplete: 0
[15:22:18.880] <TB0> INFO: pixel address: 0
[15:22:18.880] <TB0> INFO: pulse height fill bit: 0
[15:22:18.880] <TB0> INFO: buffer corruption: 0
[15:22:18.894] <TB0> INFO: Decoding statistics:
[15:22:18.894] <TB0> INFO: General information:
[15:22:18.894] <TB0> INFO: 16bit words read: 3345110
[15:22:18.894] <TB0> INFO: valid events total: 353536
[15:22:18.894] <TB0> INFO: empty events: 25378
[15:22:18.894] <TB0> INFO: valid events with pixels: 328158
[15:22:18.894] <TB0> INFO: valid pixel hits: 611947
[15:22:18.894] <TB0> INFO: Event errors: 0
[15:22:18.894] <TB0> INFO: start marker: 0
[15:22:18.894] <TB0> INFO: stop marker: 0
[15:22:18.894] <TB0> INFO: overflow: 0
[15:22:18.894] <TB0> INFO: invalid 5bit words: 0
[15:22:18.894] <TB0> INFO: invalid XOR eye diagram: 0
[15:22:18.894] <TB0> INFO: frame (failed synchr.): 0
[15:22:18.894] <TB0> INFO: idle data (no TBM trl): 0
[15:22:18.894] <TB0> INFO: no data (only TBM hdr): 0
[15:22:18.894] <TB0> INFO: TBM errors: 0
[15:22:18.894] <TB0> INFO: flawed TBM headers: 0
[15:22:18.894] <TB0> INFO: flawed TBM trailers: 0
[15:22:18.894] <TB0> INFO: event ID mismatches: 0
[15:22:18.894] <TB0> INFO: ROC errors: 0
[15:22:18.894] <TB0> INFO: missing ROC header(s): 0
[15:22:18.894] <TB0> INFO: misplaced readback start: 0
[15:22:18.894] <TB0> INFO: Pixel decoding errors: 0
[15:22:18.894] <TB0> INFO: pixel data incomplete: 0
[15:22:18.894] <TB0> INFO: pixel address: 0
[15:22:18.894] <TB0> INFO: pulse height fill bit: 0
[15:22:18.894] <TB0> INFO: buffer corruption: 0
[15:22:18.894] <TB0> INFO: enter test to run
[15:22:18.894] <TB0> INFO: test: Trim80 no parameter change
[15:22:18.894] <TB0> INFO: running: trim80
[15:22:18.910] <TB0> INFO: ######################################################################
[15:22:18.910] <TB0> INFO: PixTestTrim80::doTest()
[15:22:18.910] <TB0> INFO: ######################################################################
[15:22:18.911] <TB0> INFO: ----------------------------------------------------------------------
[15:22:18.911] <TB0> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[15:22:18.911] <TB0> INFO: ----------------------------------------------------------------------
[15:22:18.953] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[15:22:18.953] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:22:18.962] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[15:22:18.962] <TB0> INFO: run 1 of 1
[15:22:19.196] <TB0> INFO: Expecting 5025280 events.
[15:22:47.046] <TB0> INFO: 686848 events read in total (27258ms).
[15:23:14.421] <TB0> INFO: 1369504 events read in total (54633ms).
[15:23:41.784] <TB0> INFO: 2049864 events read in total (81996ms).
[15:24:08.960] <TB0> INFO: 2728624 events read in total (109172ms).
[15:24:36.474] <TB0> INFO: 3406664 events read in total (136686ms).
[15:25:03.729] <TB0> INFO: 4083600 events read in total (163941ms).
[15:25:30.000] <TB0> INFO: 4759256 events read in total (191212ms).
[15:25:41.808] <TB0> INFO: 5025280 events read in total (202020ms).
[15:25:41.926] <TB0> INFO: Test took 202964ms.
[15:26:04.711] <TB0> INFO: ROC 0 VthrComp = 76
[15:26:04.712] <TB0> INFO: ROC 1 VthrComp = 73
[15:26:04.712] <TB0> INFO: ROC 2 VthrComp = 74
[15:26:04.712] <TB0> INFO: ROC 3 VthrComp = 69
[15:26:04.712] <TB0> INFO: ROC 4 VthrComp = 85
[15:26:04.712] <TB0> INFO: ROC 5 VthrComp = 78
[15:26:04.712] <TB0> INFO: ROC 6 VthrComp = 82
[15:26:04.712] <TB0> INFO: ROC 7 VthrComp = 91
[15:26:04.712] <TB0> INFO: ROC 8 VthrComp = 81
[15:26:04.712] <TB0> INFO: ROC 9 VthrComp = 74
[15:26:04.713] <TB0> INFO: ROC 10 VthrComp = 76
[15:26:04.713] <TB0> INFO: ROC 11 VthrComp = 75
[15:26:04.713] <TB0> INFO: ROC 12 VthrComp = 78
[15:26:04.713] <TB0> INFO: ROC 13 VthrComp = 75
[15:26:04.713] <TB0> INFO: ROC 14 VthrComp = 78
[15:26:04.713] <TB0> INFO: ROC 15 VthrComp = 72
[15:26:04.990] <TB0> INFO: Expecting 41600 events.
[15:26:08.393] <TB0> INFO: 41600 events read in total (2812ms).
[15:26:08.394] <TB0> INFO: Test took 3679ms.
[15:26:08.403] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[15:26:08.403] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:26:08.412] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[15:26:08.412] <TB0> INFO: run 1 of 1
[15:26:08.690] <TB0> INFO: Expecting 5025280 events.
[15:26:35.921] <TB0> INFO: 684768 events read in total (26639ms).
[15:27:03.073] <TB0> INFO: 1366768 events read in total (53791ms).
[15:27:30.707] <TB0> INFO: 2049824 events read in total (81425ms).
[15:27:57.890] <TB0> INFO: 2730408 events read in total (108608ms).
[15:28:24.760] <TB0> INFO: 3406992 events read in total (135478ms).
[15:28:51.950] <TB0> INFO: 4082184 events read in total (162668ms).
[15:29:19.101] <TB0> INFO: 4757704 events read in total (189819ms).
[15:29:30.028] <TB0> INFO: 5025280 events read in total (200746ms).
[15:29:30.104] <TB0> INFO: Test took 201692ms.
[15:29:53.713] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 113.129 for pixel 0/15 mean/min/max = 95.9352/78.5353/113.335
[15:29:53.713] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 110.123 for pixel 0/44 mean/min/max = 94.0258/77.8682/110.183
[15:29:53.714] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 109.104 for pixel 6/62 mean/min/max = 93.1067/77.0354/109.178
[15:29:53.714] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 106.628 for pixel 7/48 mean/min/max = 90.6353/74.5875/106.683
[15:29:53.715] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 109.36 for pixel 0/9 mean/min/max = 91.5201/73.421/109.619
[15:29:53.715] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 107.743 for pixel 20/1 mean/min/max = 93.3/78.7384/107.862
[15:29:53.715] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 106.926 for pixel 22/72 mean/min/max = 91.1281/75.2965/106.96
[15:29:53.716] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 108.346 for pixel 0/26 mean/min/max = 92.3755/76.1547/108.596
[15:29:53.716] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 108.921 for pixel 0/0 mean/min/max = 92.1829/75.2356/109.13
[15:29:53.717] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 112.409 for pixel 18/7 mean/min/max = 95.8266/79.1457/112.507
[15:29:53.717] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 114.665 for pixel 0/76 mean/min/max = 96.59/78.1218/115.058
[15:29:53.717] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 114.164 for pixel 0/69 mean/min/max = 95.8518/76.5681/115.136
[15:29:53.718] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 113.313 for pixel 9/2 mean/min/max = 95.8551/78.1941/113.516
[15:29:53.718] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 109.932 for pixel 2/16 mean/min/max = 94.0099/77.9018/110.118
[15:29:53.718] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 113.039 for pixel 14/12 mean/min/max = 95.3938/77.6898/113.098
[15:29:53.719] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 108.535 for pixel 0/8 mean/min/max = 93.0409/77.1023/108.98
[15:29:53.719] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:29:53.808] <TB0> INFO: Expecting 411648 events.
[15:30:03.222] <TB0> INFO: 411648 events read in total (8823ms).
[15:30:03.231] <TB0> INFO: Expecting 411648 events.
[15:30:12.454] <TB0> INFO: 411648 events read in total (8820ms).
[15:30:12.467] <TB0> INFO: Expecting 411648 events.
[15:30:21.625] <TB0> INFO: 411648 events read in total (8755ms).
[15:30:21.640] <TB0> INFO: Expecting 411648 events.
[15:30:30.821] <TB0> INFO: 411648 events read in total (8778ms).
[15:30:30.837] <TB0> INFO: Expecting 411648 events.
[15:30:40.009] <TB0> INFO: 411648 events read in total (8769ms).
[15:30:40.033] <TB0> INFO: Expecting 411648 events.
[15:30:49.321] <TB0> INFO: 411648 events read in total (8885ms).
[15:30:49.341] <TB0> INFO: Expecting 411648 events.
[15:30:58.358] <TB0> INFO: 411648 events read in total (8614ms).
[15:30:58.380] <TB0> INFO: Expecting 411648 events.
[15:31:07.449] <TB0> INFO: 411648 events read in total (8666ms).
[15:31:07.480] <TB0> INFO: Expecting 411648 events.
[15:31:16.563] <TB0> INFO: 411648 events read in total (8680ms).
[15:31:16.590] <TB0> INFO: Expecting 411648 events.
[15:31:25.705] <TB0> INFO: 411648 events read in total (8712ms).
[15:31:25.782] <TB0> INFO: Expecting 411648 events.
[15:31:34.823] <TB0> INFO: 411648 events read in total (8638ms).
[15:31:34.887] <TB0> INFO: Expecting 411648 events.
[15:31:43.949] <TB0> INFO: 411648 events read in total (8659ms).
[15:31:44.009] <TB0> INFO: Expecting 411648 events.
[15:31:53.101] <TB0> INFO: 411648 events read in total (8689ms).
[15:31:53.168] <TB0> INFO: Expecting 411648 events.
[15:32:02.298] <TB0> INFO: 411648 events read in total (8727ms).
[15:32:02.369] <TB0> INFO: Expecting 411648 events.
[15:32:11.466] <TB0> INFO: 411648 events read in total (8694ms).
[15:32:11.542] <TB0> INFO: Expecting 411648 events.
[15:32:20.670] <TB0> INFO: 411648 events read in total (8725ms).
[15:32:20.756] <TB0> INFO: Test took 147037ms.
[15:32:22.341] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[15:32:22.353] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[15:32:22.353] <TB0> INFO: run 1 of 1
[15:32:22.589] <TB0> INFO: Expecting 5025280 events.
[15:32:50.179] <TB0> INFO: 666424 events read in total (26999ms).
[15:33:16.913] <TB0> INFO: 1330304 events read in total (53733ms).
[15:33:43.953] <TB0> INFO: 1993880 events read in total (80773ms).
[15:34:10.911] <TB0> INFO: 2655080 events read in total (107731ms).
[15:34:37.732] <TB0> INFO: 3312320 events read in total (134552ms).
[15:35:04.440] <TB0> INFO: 3968072 events read in total (161260ms).
[15:35:31.210] <TB0> INFO: 4622848 events read in total (188030ms).
[15:35:47.815] <TB0> INFO: 5025280 events read in total (204635ms).
[15:35:47.870] <TB0> INFO: Test took 205517ms.
[15:36:11.686] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 48.746595 .. 106.501466
[15:36:11.960] <TB0> INFO: Expecting 208000 events.
[15:36:21.786] <TB0> INFO: 208000 events read in total (9235ms).
[15:36:21.787] <TB0> INFO: Test took 10099ms.
[15:36:21.833] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 38 .. 116 (-1/-1) hits flags = 528 (plus default)
[15:36:21.844] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[15:36:21.844] <TB0> INFO: run 1 of 1
[15:36:22.122] <TB0> INFO: Expecting 2629120 events.
[15:36:50.171] <TB0> INFO: 684368 events read in total (27458ms).
[15:37:17.319] <TB0> INFO: 1367368 events read in total (54606ms).
[15:37:44.739] <TB0> INFO: 2046880 events read in total (82026ms).
[15:38:08.979] <TB0> INFO: 2629120 events read in total (106266ms).
[15:38:09.019] <TB0> INFO: Test took 107176ms.
[15:38:27.767] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 60.060304 .. 95.746038
[15:38:28.004] <TB0> INFO: Expecting 208000 events.
[15:38:37.993] <TB0> INFO: 208000 events read in total (9397ms).
[15:38:37.994] <TB0> INFO: Test took 10225ms.
[15:38:38.074] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 50 .. 105 (-1/-1) hits flags = 528 (plus default)
[15:38:38.087] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[15:38:38.087] <TB0> INFO: run 1 of 1
[15:38:38.364] <TB0> INFO: Expecting 1863680 events.
[15:39:06.580] <TB0> INFO: 683640 events read in total (27624ms).
[15:39:34.250] <TB0> INFO: 1367080 events read in total (55294ms).
[15:39:53.849] <TB0> INFO: 1863680 events read in total (74893ms).
[15:39:53.879] <TB0> INFO: Test took 75793ms.
[15:40:10.006] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 66.280688 .. 92.098427
[15:40:10.246] <TB0> INFO: Expecting 208000 events.
[15:40:19.795] <TB0> INFO: 208000 events read in total (8957ms).
[15:40:19.796] <TB0> INFO: Test took 9789ms.
[15:40:19.842] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 56 .. 102 (-1/-1) hits flags = 528 (plus default)
[15:40:19.852] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[15:40:19.852] <TB0> INFO: run 1 of 1
[15:40:20.130] <TB0> INFO: Expecting 1564160 events.
[15:40:48.684] <TB0> INFO: 675904 events read in total (27962ms).
[15:41:16.195] <TB0> INFO: 1350824 events read in total (55474ms).
[15:41:25.107] <TB0> INFO: 1564160 events read in total (64385ms).
[15:41:25.131] <TB0> INFO: Test took 65280ms.
[15:41:43.398] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 69.007922 .. 92.098427
[15:41:43.632] <TB0> INFO: Expecting 208000 events.
[15:41:53.584] <TB0> INFO: 208000 events read in total (9360ms).
[15:41:53.585] <TB0> INFO: Test took 10185ms.
[15:41:53.639] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 59 .. 102 (-1/-1) hits flags = 528 (plus default)
[15:41:53.649] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[15:41:53.649] <TB0> INFO: run 1 of 1
[15:41:53.927] <TB0> INFO: Expecting 1464320 events.
[15:42:21.627] <TB0> INFO: 665624 events read in total (27108ms).
[15:42:49.154] <TB0> INFO: 1330504 events read in total (54636ms).
[15:42:55.140] <TB0> INFO: 1464320 events read in total (60621ms).
[15:42:55.164] <TB0> INFO: Test took 61514ms.
[15:43:13.678] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[15:43:13.678] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[15:43:13.690] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[15:43:13.690] <TB0> INFO: run 1 of 1
[15:43:13.962] <TB0> INFO: Expecting 1364480 events.
[15:43:41.665] <TB0> INFO: 667656 events read in total (27111ms).
[15:44:08.799] <TB0> INFO: 1334936 events read in total (54245ms).
[15:44:10.458] <TB0> INFO: 1364480 events read in total (55904ms).
[15:44:10.487] <TB0> INFO: Test took 56796ms.
[15:44:27.968] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C0.dat
[15:44:27.968] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C1.dat
[15:44:27.968] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C2.dat
[15:44:27.968] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C3.dat
[15:44:27.968] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C4.dat
[15:44:27.968] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C5.dat
[15:44:27.969] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C6.dat
[15:44:27.969] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C7.dat
[15:44:27.969] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C8.dat
[15:44:27.969] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C9.dat
[15:44:27.969] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C10.dat
[15:44:27.969] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C11.dat
[15:44:27.969] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C12.dat
[15:44:27.969] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C13.dat
[15:44:27.969] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C14.dat
[15:44:27.969] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//dacParameters80_C15.dat
[15:44:27.969] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C0.dat
[15:44:27.976] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C1.dat
[15:44:27.982] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C2.dat
[15:44:27.990] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C3.dat
[15:44:27.998] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C4.dat
[15:44:28.008] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C5.dat
[15:44:28.017] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C6.dat
[15:44:28.026] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C7.dat
[15:44:28.033] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C8.dat
[15:44:28.039] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C9.dat
[15:44:28.045] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C10.dat
[15:44:28.051] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C11.dat
[15:44:28.057] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C12.dat
[15:44:28.065] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C13.dat
[15:44:28.075] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C14.dat
[15:44:28.084] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1131_FullQualification_2016-11-07_11h20m_1478514052//003_FulltestTrim80_p17//trimParameters80_C15.dat
[15:44:28.093] <TB0> INFO: PixTestTrim80::trimTest() done
[15:44:28.093] <TB0> INFO: vtrim: 123 111 103 101 100 107 109 112 113 118 94 117 127 119 126 105
[15:44:28.093] <TB0> INFO: vthrcomp: 76 73 74 69 85 78 82 91 81 74 76 75 78 75 78 72
[15:44:28.093] <TB0> INFO: vcal mean: 79.98 79.96 79.96 79.95 79.96 79.97 79.94 79.90 79.94 79.65 80.00 79.94 79.94 79.99 79.98 79.99
[15:44:28.093] <TB0> INFO: vcal RMS: 0.77 0.74 0.74 0.73 0.79 0.72 0.76 0.79 0.76 5.02 0.84 0.85 0.82 0.78 0.82 0.78
[15:44:28.093] <TB0> INFO: bits mean: 9.55 9.46 9.52 10.58 9.80 9.67 10.40 9.79 10.23 9.87 9.04 10.03 9.95 10.25 9.95 9.75
[15:44:28.093] <TB0> INFO: bits RMS: 2.06 2.19 2.31 2.20 2.67 2.07 2.23 2.39 2.26 1.90 2.30 2.05 1.94 1.88 2.00 2.23
[15:44:28.100] <TB0> INFO: ----------------------------------------------------------------------
[15:44:28.100] <TB0> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[15:44:28.100] <TB0> INFO: ----------------------------------------------------------------------
[15:44:28.103] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[15:44:28.113] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[15:44:28.113] <TB0> INFO: run 1 of 1
[15:44:28.434] <TB0> INFO: Expecting 4160000 events.
[15:45:00.736] <TB0> INFO: 769840 events read in total (31710ms).
[15:45:32.562] <TB0> INFO: 1532725 events read in total (63536ms).
[15:46:03.852] <TB0> INFO: 2290500 events read in total (94827ms).
[15:46:35.533] <TB0> INFO: 3042925 events read in total (126507ms).
[15:47:06.586] <TB0> INFO: 3793625 events read in total (157560ms).
[15:47:22.437] <TB0> INFO: 4160000 events read in total (173411ms).
[15:47:22.495] <TB0> INFO: Test took 174382ms.
[15:47:49.534] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[15:47:49.544] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[15:47:49.544] <TB0> INFO: run 1 of 1
[15:47:49.787] <TB0> INFO: Expecting 5324800 events.
[15:48:20.221] <TB0> INFO: 685420 events read in total (29843ms).
[15:48:50.052] <TB0> INFO: 1367805 events read in total (59674ms).
[15:49:19.626] <TB0> INFO: 2048000 events read in total (89248ms).
[15:49:49.203] <TB0> INFO: 2726740 events read in total (118825ms).
[15:50:18.774] <TB0> INFO: 3402835 events read in total (148396ms).
[15:50:48.087] <TB0> INFO: 4076970 events read in total (177709ms).
[15:51:17.389] <TB0> INFO: 4751060 events read in total (207011ms).
[15:51:42.539] <TB0> INFO: 5324800 events read in total (232161ms).
[15:51:42.620] <TB0> INFO: Test took 233076ms.
[15:52:17.812] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 217 (-1/-1) hits flags = 528 (plus default)
[15:52:17.824] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[15:52:17.824] <TB0> INFO: run 1 of 1
[15:52:18.091] <TB0> INFO: Expecting 4534400 events.
[15:52:49.624] <TB0> INFO: 721750 events read in total (30941ms).
[15:53:20.298] <TB0> INFO: 1438575 events read in total (61615ms).
[15:53:50.981] <TB0> INFO: 2153680 events read in total (92298ms).
[15:54:21.464] <TB0> INFO: 2864445 events read in total (122781ms).
[15:54:51.740] <TB0> INFO: 3572780 events read in total (153057ms).
[15:55:21.844] <TB0> INFO: 4280505 events read in total (183161ms).
[15:55:33.029] <TB0> INFO: 4534400 events read in total (194346ms).
[15:55:33.085] <TB0> INFO: Test took 195261ms.
[15:56:03.360] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 216 (-1/-1) hits flags = 528 (plus default)
[15:56:03.371] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[15:56:03.371] <TB0> INFO: run 1 of 1
[15:56:03.632] <TB0> INFO: Expecting 4513600 events.
[15:56:34.825] <TB0> INFO: 723420 events read in total (30601ms).
[15:57:05.493] <TB0> INFO: 1441695 events read in total (61269ms).
[15:57:35.925] <TB0> INFO: 2158065 events read in total (91701ms).
[15:58:06.512] <TB0> INFO: 2870280 events read in total (122288ms).
[15:58:36.897] <TB0> INFO: 3579715 events read in total (152673ms).
[15:59:07.139] <TB0> INFO: 4288820 events read in total (182915ms).
[15:59:17.047] <TB0> INFO: 4513600 events read in total (192823ms).
[15:59:17.130] <TB0> INFO: Test took 193759ms.
[15:59:47.583] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 216 (-1/-1) hits flags = 528 (plus default)
[15:59:47.595] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[15:59:47.595] <TB0> INFO: run 1 of 1
[15:59:47.855] <TB0> INFO: Expecting 4513600 events.
[16:00:18.840] <TB0> INFO: 723530 events read in total (30393ms).
[16:00:49.429] <TB0> INFO: 1441950 events read in total (60982ms).
[16:01:19.901] <TB0> INFO: 2158625 events read in total (91454ms).
[16:01:50.278] <TB0> INFO: 2870830 events read in total (121831ms).
[16:02:21.714] <TB0> INFO: 3580525 events read in total (153267ms).
[16:02:53.078] <TB0> INFO: 4289940 events read in total (184631ms).
[16:03:03.266] <TB0> INFO: 4513600 events read in total (194819ms).
[16:03:03.322] <TB0> INFO: Test took 195727ms.
[16:03:31.419] <TB0> INFO: PixTestTrim80::trimBitTest() done
[16:03:31.420] <TB0> INFO: PixTestTrim80::doTest() done, duration: 2472 seconds
[16:03:32.283] <TB0> INFO: enter test to run
[16:03:32.283] <TB0> INFO: test: exit no parameter change
[16:03:32.403] <TB0> QUIET: Connection to board 73 closed.
[16:03:32.405] <TB0> INFO: pXar: this is the end, my friend