[14:20:06.592] <TB3> INFO: *** Welcome to pxar ***
[14:20:06.592] <TB3> INFO: *** Today: 2016/11/07
[14:20:06.598] <TB3> INFO: *** Version: c8ba-dirty
[14:20:06.598] <TB3> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C15.dat
[14:20:06.599] <TB3> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C1b.dat
[14:20:06.599] <TB3> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//defaultMaskFile.dat
[14:20:06.599] <TB3> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters_C15.dat
[14:20:06.685] <TB3> INFO: clk: 4
[14:20:06.685] <TB3> INFO: ctr: 4
[14:20:06.685] <TB3> INFO: sda: 19
[14:20:06.685] <TB3> INFO: tin: 9
[14:20:06.685] <TB3> INFO: level: 15
[14:20:06.685] <TB3> INFO: triggerdelay: 0
[14:20:06.685] <TB3> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[14:20:06.685] <TB3> INFO: Log level: INFO
[14:20:06.695] <TB3> INFO: Found DTB DTB_WWVASW
[14:20:06.704] <TB3> QUIET: Connection to board DTB_WWVASW opened.
[14:20:06.706] <TB3> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 126
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWVASW
MAC address: 40D85511807E
Hostname: pixelDTB126
Comment:
------------------------------------------------------
[14:20:06.708] <TB3> INFO: RPC call hashes of host and DTB match: 486171790
[14:20:08.208] <TB3> INFO: DUT info:
[14:20:08.209] <TB3> INFO: The DUT currently contains the following objects:
[14:20:08.209] <TB3> INFO: 4 TBM Cores tbm10c (4 ON)
[14:20:08.209] <TB3> INFO: TBM Core alpha (0): 7 registers set
[14:20:08.209] <TB3> INFO: TBM Core beta (1): 7 registers set
[14:20:08.209] <TB3> INFO: TBM Core alpha (2): 7 registers set
[14:20:08.209] <TB3> INFO: TBM Core beta (3): 7 registers set
[14:20:08.209] <TB3> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[14:20:08.209] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.209] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.209] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.209] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.209] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.209] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.209] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.209] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.209] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.209] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.209] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.209] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.209] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.210] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.210] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.210] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[14:20:08.612] <TB3> INFO: enter 'restricted' command line mode
[14:20:08.612] <TB3> INFO: enter test to run
[14:20:08.612] <TB3> INFO: test: pretest no parameter change
[14:20:08.612] <TB3> INFO: running: pretest
[14:20:08.619] <TB3> INFO: ######################################################################
[14:20:08.619] <TB3> INFO: PixTestPretest::doTest()
[14:20:08.619] <TB3> INFO: ######################################################################
[14:20:08.620] <TB3> INFO: ----------------------------------------------------------------------
[14:20:08.620] <TB3> INFO: PixTestPretest::programROC()
[14:20:08.620] <TB3> INFO: ----------------------------------------------------------------------
[14:20:26.635] <TB3> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[14:20:26.635] <TB3> INFO: IA differences per ROC: 16.9 19.3 15.3 16.1 15.3 18.5 20.1 19.3 19.3 17.7 21.7 18.5 18.5 18.5 19.3 17.7
[14:20:26.697] <TB3> INFO: ----------------------------------------------------------------------
[14:20:26.697] <TB3> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[14:20:26.697] <TB3> INFO: ----------------------------------------------------------------------
[14:20:47.997] <TB3> INFO: PixTestPretest::setVana() done, Module Ia 375.4 mA = 23.4625 mA/ROC
[14:20:47.997] <TB3> INFO: i(loss) [mA/ROC]: 20.1 20.1 19.3 19.3 18.5 20.1 18.5 19.3 19.3 20.1 16.9 17.7 20.1 18.5 18.5 19.3
[14:20:48.030] <TB3> INFO: ----------------------------------------------------------------------
[14:20:48.030] <TB3> INFO: PixTestPretest::findTiming()
[14:20:48.030] <TB3> INFO: ----------------------------------------------------------------------
[14:20:48.030] <TB3> INFO: PixTestCmd::init()

[14:21:20.103] <TB3> INFO: TBM phases: 160MHz: 7, 400MHz: 6, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[14:21:20.103] <TB3> INFO: (success/tries = 100/100), width = 3
[14:21:21.608] <TB3> INFO: ----------------------------------------------------------------------
[14:21:21.608] <TB3> INFO: PixTestPretest::findWorkingPixel()
[14:21:21.608] <TB3> INFO: ----------------------------------------------------------------------
[14:21:21.700] <TB3> INFO: Expecting 231680 events.
[14:21:31.552] <TB3> INFO: 231680 events read in total (9260ms).
[14:21:31.561] <TB3> INFO: Test took 9951ms.
[14:21:31.802] <TB3> INFO: Found working pixel in all ROCs: col/row = 12/22
[14:21:31.835] <TB3> INFO: ----------------------------------------------------------------------
[14:21:31.835] <TB3> INFO: PixTestPretest::setVthrCompCalDel()
[14:21:31.835] <TB3> INFO: ----------------------------------------------------------------------
[14:21:31.930] <TB3> INFO: Expecting 231680 events.
[14:21:41.942] <TB3> INFO: 231680 events read in total (9420ms).
[14:21:41.956] <TB3> INFO: Test took 10115ms.
[14:21:42.210] <TB3> INFO: PixTestPretest::setVthrCompCalDel() done
[14:21:42.210] <TB3> INFO: CalDel: 77 92 97 107 105 109 95 95 85 82 97 81 97 84 97 93
[14:21:42.210] <TB3> INFO: VthrComp: 51 52 51 51 51 51 51 57 51 51 51 51 51 51 51 51
[14:21:42.213] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C0.dat
[14:21:42.214] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C1.dat
[14:21:42.214] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C2.dat
[14:21:42.214] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C3.dat
[14:21:42.214] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C4.dat
[14:21:42.214] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C5.dat
[14:21:42.214] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C6.dat
[14:21:42.214] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C7.dat
[14:21:42.214] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C8.dat
[14:21:42.214] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C9.dat
[14:21:42.215] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C10.dat
[14:21:42.215] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C11.dat
[14:21:42.215] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C12.dat
[14:21:42.215] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C13.dat
[14:21:42.215] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C14.dat
[14:21:42.215] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C15.dat
[14:21:42.215] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C0a.dat
[14:21:42.215] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C0b.dat
[14:21:42.215] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C1a.dat
[14:21:42.215] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C1b.dat
[14:21:42.215] <TB3> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[14:21:42.266] <TB3> INFO: enter test to run
[14:21:42.266] <TB3> INFO: test: FullTest no parameter change
[14:21:42.266] <TB3> INFO: running: fulltest
[14:21:42.266] <TB3> INFO: ######################################################################
[14:21:42.267] <TB3> INFO: PixTestFullTest::doTest()
[14:21:42.267] <TB3> INFO: ######################################################################
[14:21:42.268] <TB3> INFO: ######################################################################
[14:21:42.268] <TB3> INFO: PixTestAlive::doTest()
[14:21:42.268] <TB3> INFO: ######################################################################
[14:21:42.269] <TB3> INFO: ----------------------------------------------------------------------
[14:21:42.269] <TB3> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:21:42.269] <TB3> INFO: ----------------------------------------------------------------------
[14:21:42.512] <TB3> INFO: Expecting 41600 events.
[14:21:46.068] <TB3> INFO: 41600 events read in total (2965ms).
[14:21:46.069] <TB3> INFO: Test took 3799ms.
[14:21:46.302] <TB3> INFO: PixTestAlive::aliveTest() done
[14:21:46.302] <TB3> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
[14:21:46.303] <TB3> INFO: ----------------------------------------------------------------------
[14:21:46.303] <TB3> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:21:46.303] <TB3> INFO: ----------------------------------------------------------------------
[14:21:46.547] <TB3> INFO: Expecting 41600 events.
[14:21:49.557] <TB3> INFO: 41600 events read in total (2418ms).
[14:21:49.557] <TB3> INFO: Test took 3252ms.
[14:21:49.558] <TB3> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[14:21:49.796] <TB3> INFO: PixTestAlive::maskTest() done
[14:21:49.796] <TB3> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:21:49.798] <TB3> INFO: ----------------------------------------------------------------------
[14:21:49.798] <TB3> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:21:49.798] <TB3> INFO: ----------------------------------------------------------------------
[14:21:50.047] <TB3> INFO: Expecting 41600 events.
[14:21:53.606] <TB3> INFO: 41600 events read in total (2967ms).
[14:21:53.608] <TB3> INFO: Test took 3809ms.
[14:21:53.836] <TB3> INFO: PixTestAlive::addressDecodingTest() done
[14:21:53.836] <TB3> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:21:53.837] <TB3> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[14:21:53.837] <TB3> INFO: Decoding statistics:
[14:21:53.837] <TB3> INFO: General information:
[14:21:53.837] <TB3> INFO: 16bit words read: 0
[14:21:53.837] <TB3> INFO: valid events total: 0
[14:21:53.837] <TB3> INFO: empty events: 0
[14:21:53.837] <TB3> INFO: valid events with pixels: 0
[14:21:53.837] <TB3> INFO: valid pixel hits: 0
[14:21:53.837] <TB3> INFO: Event errors: 0
[14:21:53.837] <TB3> INFO: start marker: 0
[14:21:53.837] <TB3> INFO: stop marker: 0
[14:21:53.837] <TB3> INFO: overflow: 0
[14:21:53.837] <TB3> INFO: invalid 5bit words: 0
[14:21:53.837] <TB3> INFO: invalid XOR eye diagram: 0
[14:21:53.837] <TB3> INFO: frame (failed synchr.): 0
[14:21:53.837] <TB3> INFO: idle data (no TBM trl): 0
[14:21:53.837] <TB3> INFO: no data (only TBM hdr): 0
[14:21:53.837] <TB3> INFO: TBM errors: 0
[14:21:53.837] <TB3> INFO: flawed TBM headers: 0
[14:21:53.837] <TB3> INFO: flawed TBM trailers: 0
[14:21:53.837] <TB3> INFO: event ID mismatches: 0
[14:21:53.837] <TB3> INFO: ROC errors: 0
[14:21:53.837] <TB3> INFO: missing ROC header(s): 0
[14:21:53.837] <TB3> INFO: misplaced readback start: 0
[14:21:53.837] <TB3> INFO: Pixel decoding errors: 0
[14:21:53.837] <TB3> INFO: pixel data incomplete: 0
[14:21:53.837] <TB3> INFO: pixel address: 0
[14:21:53.837] <TB3> INFO: pulse height fill bit: 0
[14:21:53.837] <TB3> INFO: buffer corruption: 0
[14:21:53.843] <TB3> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C15.dat
[14:21:53.843] <TB3> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[14:21:53.843] <TB3> INFO: ######################################################################
[14:21:53.843] <TB3> INFO: PixTestReadback::doTest()
[14:21:53.843] <TB3> INFO: ######################################################################
[14:21:53.843] <TB3> INFO: ----------------------------------------------------------------------
[14:21:53.843] <TB3> INFO: PixTestReadback::CalibrateVd()
[14:21:53.843] <TB3> INFO: ----------------------------------------------------------------------
[14:22:03.829] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C0.dat
[14:22:03.829] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C1.dat
[14:22:03.829] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C2.dat
[14:22:03.829] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C3.dat
[14:22:03.829] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C4.dat
[14:22:03.829] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C5.dat
[14:22:03.829] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C6.dat
[14:22:03.829] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C7.dat
[14:22:03.829] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C8.dat
[14:22:03.829] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C9.dat
[14:22:03.829] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C10.dat
[14:22:03.830] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C11.dat
[14:22:03.830] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C12.dat
[14:22:03.830] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C13.dat
[14:22:03.830] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C14.dat
[14:22:03.830] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C15.dat
[14:22:03.863] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[14:22:03.863] <TB3> INFO: ----------------------------------------------------------------------
[14:22:03.863] <TB3> INFO: PixTestReadback::CalibrateVa()
[14:22:03.863] <TB3> INFO: ----------------------------------------------------------------------
[14:22:13.805] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C0.dat
[14:22:13.805] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C1.dat
[14:22:13.805] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C2.dat
[14:22:13.805] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C3.dat
[14:22:13.805] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C4.dat
[14:22:13.805] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C5.dat
[14:22:13.805] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C6.dat
[14:22:13.805] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C7.dat
[14:22:13.805] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C8.dat
[14:22:13.805] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C9.dat
[14:22:13.805] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C10.dat
[14:22:13.805] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C11.dat
[14:22:13.805] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C12.dat
[14:22:13.806] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C13.dat
[14:22:13.806] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C14.dat
[14:22:13.806] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C15.dat
[14:22:13.838] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[14:22:13.838] <TB3> INFO: ----------------------------------------------------------------------
[14:22:13.838] <TB3> INFO: PixTestReadback::readbackVbg()
[14:22:13.838] <TB3> INFO: ----------------------------------------------------------------------
[14:22:21.508] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[14:22:21.508] <TB3> INFO: ----------------------------------------------------------------------
[14:22:21.508] <TB3> INFO: PixTestReadback::getCalibratedVbg()
[14:22:21.508] <TB3> INFO: ----------------------------------------------------------------------
[14:22:21.508] <TB3> INFO: Vbg will be calibrated using Vd calibration
[14:22:21.508] <TB3> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 159calibrated Vbg = 1.18996 :::*/*/*/*/
[14:22:21.508] <TB3> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 155calibrated Vbg = 1.20197 :::*/*/*/*/
[14:22:21.508] <TB3> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 158.7calibrated Vbg = 1.19363 :::*/*/*/*/
[14:22:21.508] <TB3> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 150.1calibrated Vbg = 1.18684 :::*/*/*/*/
[14:22:21.508] <TB3> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 145.7calibrated Vbg = 1.18972 :::*/*/*/*/
[14:22:21.508] <TB3> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 155.4calibrated Vbg = 1.19085 :::*/*/*/*/
[14:22:21.508] <TB3> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 160.9calibrated Vbg = 1.19476 :::*/*/*/*/
[14:22:21.509] <TB3> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 158.3calibrated Vbg = 1.19436 :::*/*/*/*/
[14:22:21.509] <TB3> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 154.5calibrated Vbg = 1.19298 :::*/*/*/*/
[14:22:21.509] <TB3> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 161.4calibrated Vbg = 1.18725 :::*/*/*/*/
[14:22:21.509] <TB3> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 152.8calibrated Vbg = 1.19168 :::*/*/*/*/
[14:22:21.509] <TB3> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 157.8calibrated Vbg = 1.17648 :::*/*/*/*/
[14:22:21.509] <TB3> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 153.7calibrated Vbg = 1.19115 :::*/*/*/*/
[14:22:21.509] <TB3> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 154.6calibrated Vbg = 1.19474 :::*/*/*/*/
[14:22:21.509] <TB3> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 151.5calibrated Vbg = 1.19754 :::*/*/*/*/
[14:22:21.509] <TB3> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 160.8calibrated Vbg = 1.19577 :::*/*/*/*/
[14:22:21.512] <TB3> INFO: ----------------------------------------------------------------------
[14:22:21.512] <TB3> INFO: PixTestReadback::CalibrateIa()
[14:22:21.512] <TB3> INFO: ----------------------------------------------------------------------
[14:25:02.336] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C0.dat
[14:25:02.336] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C1.dat
[14:25:02.336] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C2.dat
[14:25:02.336] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C3.dat
[14:25:02.336] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C4.dat
[14:25:02.336] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C5.dat
[14:25:02.336] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C6.dat
[14:25:02.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C7.dat
[14:25:02.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C8.dat
[14:25:02.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C9.dat
[14:25:02.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C10.dat
[14:25:02.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C11.dat
[14:25:02.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C12.dat
[14:25:02.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C13.dat
[14:25:02.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C14.dat
[14:25:02.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C15.dat
[14:25:02.365] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[14:25:02.368] <TB3> INFO: PixTestReadback::doTest() done
[14:25:02.368] <TB3> INFO: Decoding statistics:
[14:25:02.368] <TB3> INFO: General information:
[14:25:02.368] <TB3> INFO: 16bit words read: 1536
[14:25:02.368] <TB3> INFO: valid events total: 256
[14:25:02.368] <TB3> INFO: empty events: 256
[14:25:02.368] <TB3> INFO: valid events with pixels: 0
[14:25:02.368] <TB3> INFO: valid pixel hits: 0
[14:25:02.368] <TB3> INFO: Event errors: 0
[14:25:02.368] <TB3> INFO: start marker: 0
[14:25:02.368] <TB3> INFO: stop marker: 0
[14:25:02.368] <TB3> INFO: overflow: 0
[14:25:02.368] <TB3> INFO: invalid 5bit words: 0
[14:25:02.369] <TB3> INFO: invalid XOR eye diagram: 0
[14:25:02.369] <TB3> INFO: frame (failed synchr.): 0
[14:25:02.369] <TB3> INFO: idle data (no TBM trl): 0
[14:25:02.369] <TB3> INFO: no data (only TBM hdr): 0
[14:25:02.369] <TB3> INFO: TBM errors: 0
[14:25:02.369] <TB3> INFO: flawed TBM headers: 0
[14:25:02.369] <TB3> INFO: flawed TBM trailers: 0
[14:25:02.369] <TB3> INFO: event ID mismatches: 0
[14:25:02.369] <TB3> INFO: ROC errors: 0
[14:25:02.369] <TB3> INFO: missing ROC header(s): 0
[14:25:02.369] <TB3> INFO: misplaced readback start: 0
[14:25:02.369] <TB3> INFO: Pixel decoding errors: 0
[14:25:02.369] <TB3> INFO: pixel data incomplete: 0
[14:25:02.369] <TB3> INFO: pixel address: 0
[14:25:02.369] <TB3> INFO: pulse height fill bit: 0
[14:25:02.369] <TB3> INFO: buffer corruption: 0
[14:25:02.423] <TB3> INFO: ######################################################################
[14:25:02.423] <TB3> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[14:25:02.423] <TB3> INFO: ######################################################################
[14:25:02.426] <TB3> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[14:25:02.451] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[14:25:02.451] <TB3> INFO: run 1 of 1
[14:25:02.687] <TB3> INFO: Expecting 3120000 events.
[14:25:33.991] <TB3> INFO: 661245 events read in total (30712ms).











[14:26:04.714] <TB3> INFO: 1317335 events read in total (61436ms).











[14:26:34.825] <TB3> INFO: 1968710 events read in total (91546ms).











[14:27:05.459] <TB3> INFO: 2621845 events read in total (122180ms).











[14:27:28.672] <TB3> INFO: 3120000 events read in total (145393ms).
[14:27:28.744] <TB3> INFO: Test took 146294ms.
[14:27:55.208] <TB3> INFO: PixTestBBMap::doTest() done with 4 decoding errors: , duration: 172 seconds
[14:27:55.208] <TB3> INFO: number of dead bumps (per ROC): 1 0 3 0 0 0 0 0 1 0 1 0 0 0 0 0
[14:27:55.208] <TB3> INFO: separation cut (per ROC): 107 116 96 106 96 105 102 125 119 114 113 108 117 110 115 115
[14:27:55.208] <TB3> INFO: Decoding statistics:
[14:27:55.208] <TB3> INFO: General information:
[14:27:55.208] <TB3> INFO: 16bit words read: 0
[14:27:55.208] <TB3> INFO: valid events total: 0
[14:27:55.208] <TB3> INFO: empty events: 0
[14:27:55.208] <TB3> INFO: valid events with pixels: 0
[14:27:55.208] <TB3> INFO: valid pixel hits: 0
[14:27:55.208] <TB3> INFO: Event errors: 0
[14:27:55.208] <TB3> INFO: start marker: 0
[14:27:55.208] <TB3> INFO: stop marker: 0
[14:27:55.208] <TB3> INFO: overflow: 0
[14:27:55.208] <TB3> INFO: invalid 5bit words: 0
[14:27:55.208] <TB3> INFO: invalid XOR eye diagram: 0
[14:27:55.208] <TB3> INFO: frame (failed synchr.): 0
[14:27:55.208] <TB3> INFO: idle data (no TBM trl): 0
[14:27:55.208] <TB3> INFO: no data (only TBM hdr): 0
[14:27:55.208] <TB3> INFO: TBM errors: 0
[14:27:55.208] <TB3> INFO: flawed TBM headers: 0
[14:27:55.208] <TB3> INFO: flawed TBM trailers: 0
[14:27:55.208] <TB3> INFO: event ID mismatches: 0
[14:27:55.208] <TB3> INFO: ROC errors: 0
[14:27:55.209] <TB3> INFO: missing ROC header(s): 0
[14:27:55.209] <TB3> INFO: misplaced readback start: 0
[14:27:55.209] <TB3> INFO: Pixel decoding errors: 0
[14:27:55.209] <TB3> INFO: pixel data incomplete: 0
[14:27:55.209] <TB3> INFO: pixel address: 0
[14:27:55.209] <TB3> INFO: pulse height fill bit: 0
[14:27:55.209] <TB3> INFO: buffer corruption: 0
[14:27:55.253] <TB3> INFO: ######################################################################
[14:27:55.253] <TB3> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:27:55.253] <TB3> INFO: ######################################################################
[14:27:55.253] <TB3> INFO: ----------------------------------------------------------------------
[14:27:55.253] <TB3> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:27:55.253] <TB3> INFO: ----------------------------------------------------------------------
[14:27:55.253] <TB3> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[14:27:55.269] <TB3> INFO: dacScan split into 1 runs with ntrig = 50
[14:27:55.269] <TB3> INFO: run 1 of 1
[14:27:55.554] <TB3> INFO: Expecting 36608000 events.
[14:28:20.225] <TB3> INFO: 674650 events read in total (24079ms).
[14:28:43.252] <TB3> INFO: 1335450 events read in total (47106ms).
[14:29:07.302] <TB3> INFO: 1996450 events read in total (71156ms).
[14:29:31.539] <TB3> INFO: 2657200 events read in total (95393ms).
[14:29:54.509] <TB3> INFO: 3316350 events read in total (118363ms).
[14:30:17.815] <TB3> INFO: 3973950 events read in total (141669ms).
[14:30:40.670] <TB3> INFO: 4631400 events read in total (164524ms).
[14:31:03.533] <TB3> INFO: 5290000 events read in total (187387ms).
[14:31:26.719] <TB3> INFO: 5948400 events read in total (210573ms).
[14:31:49.607] <TB3> INFO: 6607900 events read in total (233461ms).
[14:32:12.456] <TB3> INFO: 7266650 events read in total (256310ms).
[14:32:35.360] <TB3> INFO: 7924800 events read in total (279214ms).
[14:32:58.668] <TB3> INFO: 8581000 events read in total (302522ms).
[14:33:21.648] <TB3> INFO: 9237900 events read in total (325502ms).
[14:33:44.495] <TB3> INFO: 9892800 events read in total (348349ms).
[14:34:07.246] <TB3> INFO: 10548650 events read in total (371100ms).
[14:34:30.248] <TB3> INFO: 11203800 events read in total (394102ms).
[14:34:53.360] <TB3> INFO: 11860200 events read in total (417214ms).
[14:35:15.966] <TB3> INFO: 12514550 events read in total (439820ms).
[14:35:38.642] <TB3> INFO: 13171450 events read in total (462496ms).
[14:36:01.608] <TB3> INFO: 13829000 events read in total (485462ms).
[14:36:24.404] <TB3> INFO: 14483950 events read in total (508258ms).
[14:36:47.240] <TB3> INFO: 15139750 events read in total (531094ms).
[14:37:09.889] <TB3> INFO: 15794100 events read in total (553743ms).
[14:37:32.566] <TB3> INFO: 16449800 events read in total (576420ms).
[14:37:55.388] <TB3> INFO: 17104350 events read in total (599242ms).
[14:38:17.755] <TB3> INFO: 17755850 events read in total (621609ms).
[14:38:40.700] <TB3> INFO: 18406800 events read in total (644554ms).
[14:39:03.315] <TB3> INFO: 19058450 events read in total (667169ms).
[14:39:25.740] <TB3> INFO: 19710300 events read in total (689594ms).
[14:39:48.391] <TB3> INFO: 20362700 events read in total (712246ms).
[14:40:11.326] <TB3> INFO: 21014750 events read in total (735180ms).
[14:40:33.949] <TB3> INFO: 21669250 events read in total (757803ms).
[14:40:56.489] <TB3> INFO: 22321650 events read in total (780343ms).
[14:41:19.148] <TB3> INFO: 22973250 events read in total (803002ms).
[14:41:41.489] <TB3> INFO: 23623250 events read in total (825343ms).
[14:42:04.096] <TB3> INFO: 24274050 events read in total (847950ms).
[14:42:26.738] <TB3> INFO: 24926850 events read in total (870592ms).
[14:42:49.547] <TB3> INFO: 25578650 events read in total (893401ms).
[14:43:12.236] <TB3> INFO: 26232950 events read in total (916091ms).
[14:43:34.909] <TB3> INFO: 26887500 events read in total (938763ms).
[14:43:57.631] <TB3> INFO: 27539500 events read in total (961485ms).
[14:44:20.366] <TB3> INFO: 28191200 events read in total (984220ms).
[14:44:43.038] <TB3> INFO: 28841000 events read in total (1006892ms).
[14:45:05.605] <TB3> INFO: 29488400 events read in total (1029459ms).
[14:45:28.480] <TB3> INFO: 30138700 events read in total (1052334ms).
[14:45:51.210] <TB3> INFO: 30788350 events read in total (1075064ms).
[14:46:13.712] <TB3> INFO: 31436500 events read in total (1097566ms).
[14:46:36.457] <TB3> INFO: 32084800 events read in total (1120311ms).
[14:46:59.240] <TB3> INFO: 32733200 events read in total (1143094ms).
[14:47:21.796] <TB3> INFO: 33383950 events read in total (1165650ms).
[14:47:44.827] <TB3> INFO: 34034850 events read in total (1188681ms).
[14:48:07.830] <TB3> INFO: 34686050 events read in total (1211684ms).
[14:48:30.467] <TB3> INFO: 35336950 events read in total (1234321ms).
[14:48:53.413] <TB3> INFO: 35989700 events read in total (1257267ms).
[14:49:15.435] <TB3> INFO: 36608000 events read in total (1279289ms).
[14:49:15.522] <TB3> INFO: Test took 1280253ms.
[14:49:16.026] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:18.013] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:20.248] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:21.826] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:23.305] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:24.832] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:26.316] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:27.867] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:29.396] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:30.874] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:32.424] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:33.930] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:35.439] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:36.966] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:38.461] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:39.941] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:49:41.437] <TB3> INFO: PixTestScurves::scurves() done
[14:49:41.437] <TB3> INFO: Vcal mean: 113.40 117.70 109.24 115.46 111.82 106.83 110.22 126.57 113.36 114.33 108.74 112.69 120.28 104.31 99.94 113.69
[14:49:41.437] <TB3> INFO: Vcal RMS: 5.15 6.72 5.56 5.76 5.39 4.55 5.10 6.07 4.91 5.39 5.67 4.88 5.81 5.05 5.46 6.26
[14:49:41.438] <TB3> INFO: PixTestScurves::fullTest() done, duration: 1306 seconds
[14:49:41.438] <TB3> INFO: Decoding statistics:
[14:49:41.438] <TB3> INFO: General information:
[14:49:41.438] <TB3> INFO: 16bit words read: 0
[14:49:41.438] <TB3> INFO: valid events total: 0
[14:49:41.438] <TB3> INFO: empty events: 0
[14:49:41.438] <TB3> INFO: valid events with pixels: 0
[14:49:41.438] <TB3> INFO: valid pixel hits: 0
[14:49:41.438] <TB3> INFO: Event errors: 0
[14:49:41.438] <TB3> INFO: start marker: 0
[14:49:41.438] <TB3> INFO: stop marker: 0
[14:49:41.438] <TB3> INFO: overflow: 0
[14:49:41.438] <TB3> INFO: invalid 5bit words: 0
[14:49:41.438] <TB3> INFO: invalid XOR eye diagram: 0
[14:49:41.438] <TB3> INFO: frame (failed synchr.): 0
[14:49:41.438] <TB3> INFO: idle data (no TBM trl): 0
[14:49:41.438] <TB3> INFO: no data (only TBM hdr): 0
[14:49:41.438] <TB3> INFO: TBM errors: 0
[14:49:41.438] <TB3> INFO: flawed TBM headers: 0
[14:49:41.438] <TB3> INFO: flawed TBM trailers: 0
[14:49:41.438] <TB3> INFO: event ID mismatches: 0
[14:49:41.438] <TB3> INFO: ROC errors: 0
[14:49:41.438] <TB3> INFO: missing ROC header(s): 0
[14:49:41.438] <TB3> INFO: misplaced readback start: 0
[14:49:41.439] <TB3> INFO: Pixel decoding errors: 0
[14:49:41.439] <TB3> INFO: pixel data incomplete: 0
[14:49:41.439] <TB3> INFO: pixel address: 0
[14:49:41.439] <TB3> INFO: pulse height fill bit: 0
[14:49:41.439] <TB3> INFO: buffer corruption: 0
[14:49:41.507] <TB3> INFO: ######################################################################
[14:49:41.507] <TB3> INFO: PixTestTrim::doTest()
[14:49:41.507] <TB3> INFO: ######################################################################
[14:49:41.508] <TB3> INFO: ----------------------------------------------------------------------
[14:49:41.508] <TB3> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[14:49:41.508] <TB3> INFO: ----------------------------------------------------------------------
[14:49:41.553] <TB3> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:49:41.554] <TB3> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:49:41.566] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:49:41.566] <TB3> INFO: run 1 of 1
[14:49:41.806] <TB3> INFO: Expecting 5025280 events.
[14:50:12.155] <TB3> INFO: 823880 events read in total (29749ms).
[14:50:42.257] <TB3> INFO: 1645152 events read in total (59851ms).
[14:51:12.282] <TB3> INFO: 2463248 events read in total (89877ms).
[14:51:42.543] <TB3> INFO: 3278088 events read in total (120137ms).
[14:52:12.627] <TB3> INFO: 4090568 events read in total (150222ms).
[14:52:42.696] <TB3> INFO: 4901192 events read in total (180290ms).
[14:52:47.448] <TB3> INFO: 5025280 events read in total (185042ms).
[14:52:47.512] <TB3> INFO: Test took 185946ms.
[14:53:04.004] <TB3> INFO: ROC 0 VthrComp = 118
[14:53:04.004] <TB3> INFO: ROC 1 VthrComp = 122
[14:53:04.005] <TB3> INFO: ROC 2 VthrComp = 108
[14:53:04.005] <TB3> INFO: ROC 3 VthrComp = 118
[14:53:04.005] <TB3> INFO: ROC 4 VthrComp = 108
[14:53:04.005] <TB3> INFO: ROC 5 VthrComp = 112
[14:53:04.005] <TB3> INFO: ROC 6 VthrComp = 111
[14:53:04.005] <TB3> INFO: ROC 7 VthrComp = 134
[14:53:04.005] <TB3> INFO: ROC 8 VthrComp = 118
[14:53:04.005] <TB3> INFO: ROC 9 VthrComp = 120
[14:53:04.005] <TB3> INFO: ROC 10 VthrComp = 105
[14:53:04.005] <TB3> INFO: ROC 11 VthrComp = 112
[14:53:04.006] <TB3> INFO: ROC 12 VthrComp = 127
[14:53:04.006] <TB3> INFO: ROC 13 VthrComp = 107
[14:53:04.006] <TB3> INFO: ROC 14 VthrComp = 102
[14:53:04.006] <TB3> INFO: ROC 15 VthrComp = 117
[14:53:04.246] <TB3> INFO: Expecting 41600 events.
[14:53:07.699] <TB3> INFO: 41600 events read in total (2861ms).
[14:53:07.700] <TB3> INFO: Test took 3693ms.
[14:53:07.709] <TB3> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:53:07.709] <TB3> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:53:07.720] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:53:07.720] <TB3> INFO: run 1 of 1
[14:53:07.998] <TB3> INFO: Expecting 5025280 events.
[14:53:34.299] <TB3> INFO: 590760 events read in total (25709ms).
[14:54:00.334] <TB3> INFO: 1181176 events read in total (51744ms).
[14:54:26.079] <TB3> INFO: 1772104 events read in total (77489ms).
[14:54:51.985] <TB3> INFO: 2362528 events read in total (103395ms).
[14:55:17.927] <TB3> INFO: 2950824 events read in total (129337ms).
[14:55:43.672] <TB3> INFO: 3537704 events read in total (155082ms).
[14:56:09.599] <TB3> INFO: 4123816 events read in total (181009ms).
[14:56:35.455] <TB3> INFO: 4709240 events read in total (206865ms).
[14:56:49.210] <TB3> INFO: 5025280 events read in total (220620ms).
[14:56:49.331] <TB3> INFO: Test took 221610ms.
[14:57:11.444] <TB3> INFO: roc 0 with ID = 0 has maximal Vcal 59.8742 for pixel 9/1 mean/min/max = 45.6681/31.0459/60.2904
[14:57:11.445] <TB3> INFO: roc 1 with ID = 1 has maximal Vcal 63.1616 for pixel 10/8 mean/min/max = 46.8693/30.5599/63.1786
[14:57:11.445] <TB3> INFO: roc 2 with ID = 2 has maximal Vcal 62.8354 for pixel 4/14 mean/min/max = 48.7989/34.1554/63.4423
[14:57:11.446] <TB3> INFO: roc 3 with ID = 3 has maximal Vcal 62.0105 for pixel 0/13 mean/min/max = 46.4539/30.8882/62.0196
[14:57:11.446] <TB3> INFO: roc 4 with ID = 4 has maximal Vcal 65.6072 for pixel 24/3 mean/min/max = 49.6022/33.5599/65.6445
[14:57:11.447] <TB3> INFO: roc 5 with ID = 5 has maximal Vcal 58.3374 for pixel 17/16 mean/min/max = 45.7949/33.1419/58.4479
[14:57:11.447] <TB3> INFO: roc 6 with ID = 6 has maximal Vcal 63.3142 for pixel 18/76 mean/min/max = 48.5072/33.5962/63.4181
[14:57:11.448] <TB3> INFO: roc 7 with ID = 7 has maximal Vcal 64.1038 for pixel 12/76 mean/min/max = 49.2783/34.1518/64.4049
[14:57:11.448] <TB3> INFO: roc 8 with ID = 8 has maximal Vcal 59.7661 for pixel 0/3 mean/min/max = 45.648/31.5278/59.7681
[14:57:11.448] <TB3> INFO: roc 9 with ID = 9 has maximal Vcal 61.6089 for pixel 0/15 mean/min/max = 46.4285/31.204/61.6529
[14:57:11.449] <TB3> INFO: roc 10 with ID = 10 has maximal Vcal 64.1919 for pixel 14/67 mean/min/max = 49.0268/33.2743/64.7792
[14:57:11.449] <TB3> INFO: roc 11 with ID = 11 has maximal Vcal 61.6806 for pixel 17/78 mean/min/max = 46.8837/31.883/61.8844
[14:57:11.449] <TB3> INFO: roc 12 with ID = 12 has maximal Vcal 58.851 for pixel 16/70 mean/min/max = 45.3105/31.7393/58.8817
[14:57:11.450] <TB3> INFO: roc 13 with ID = 13 has maximal Vcal 60.4527 for pixel 23/17 mean/min/max = 47.6803/34.8594/60.5013
[14:57:11.450] <TB3> INFO: roc 14 with ID = 14 has maximal Vcal 60.6705 for pixel 14/11 mean/min/max = 47.0275/33.3733/60.6817
[14:57:11.451] <TB3> INFO: roc 15 with ID = 15 has maximal Vcal 60.0543 for pixel 36/12 mean/min/max = 45.9551/31.664/60.2463
[14:57:11.451] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:57:11.540] <TB3> INFO: Expecting 411648 events.
[14:57:21.140] <TB3> INFO: 411648 events read in total (9008ms).
[14:57:21.148] <TB3> INFO: Expecting 411648 events.
[14:57:30.596] <TB3> INFO: 411648 events read in total (9045ms).
[14:57:30.611] <TB3> INFO: Expecting 411648 events.
[14:57:40.020] <TB3> INFO: 411648 events read in total (9006ms).
[14:57:40.035] <TB3> INFO: Expecting 411648 events.
[14:57:49.412] <TB3> INFO: 411648 events read in total (8974ms).
[14:57:49.432] <TB3> INFO: Expecting 411648 events.
[14:57:58.901] <TB3> INFO: 411648 events read in total (9066ms).
[14:57:58.920] <TB3> INFO: Expecting 411648 events.
[14:58:08.349] <TB3> INFO: 411648 events read in total (9026ms).
[14:58:08.370] <TB3> INFO: Expecting 411648 events.
[14:58:17.835] <TB3> INFO: 411648 events read in total (9061ms).
[14:58:17.859] <TB3> INFO: Expecting 411648 events.
[14:58:27.376] <TB3> INFO: 411648 events read in total (9114ms).
[14:58:27.404] <TB3> INFO: Expecting 411648 events.
[14:58:36.715] <TB3> INFO: 411648 events read in total (8908ms).
[14:58:36.745] <TB3> INFO: Expecting 411648 events.
[14:58:46.167] <TB3> INFO: 411648 events read in total (9019ms).
[14:58:46.199] <TB3> INFO: Expecting 411648 events.
[14:58:55.620] <TB3> INFO: 411648 events read in total (9018ms).
[14:58:55.655] <TB3> INFO: Expecting 411648 events.
[14:59:05.065] <TB3> INFO: 411648 events read in total (9007ms).
[14:59:05.112] <TB3> INFO: Expecting 411648 events.
[14:59:14.719] <TB3> INFO: 411648 events read in total (9204ms).
[14:59:14.761] <TB3> INFO: Expecting 411648 events.
[14:59:24.139] <TB3> INFO: 411648 events read in total (8975ms).
[14:59:24.183] <TB3> INFO: Expecting 411648 events.
[14:59:33.493] <TB3> INFO: 411648 events read in total (8907ms).
[14:59:33.537] <TB3> INFO: Expecting 411648 events.
[14:59:42.829] <TB3> INFO: 411648 events read in total (8888ms).
[14:59:42.920] <TB3> INFO: Test took 151469ms.
[14:59:43.638] <TB3> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:59:43.652] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:59:43.652] <TB3> INFO: run 1 of 1
[14:59:43.891] <TB3> INFO: Expecting 5025280 events.
[15:00:10.106] <TB3> INFO: 589064 events read in total (25623ms).
[15:00:36.396] <TB3> INFO: 1176432 events read in total (51913ms).
[15:01:02.446] <TB3> INFO: 1763712 events read in total (77963ms).
[15:01:28.443] <TB3> INFO: 2349696 events read in total (103960ms).
[15:01:54.490] <TB3> INFO: 2934592 events read in total (130007ms).
[15:02:20.554] <TB3> INFO: 3521888 events read in total (156071ms).
[15:02:46.638] <TB3> INFO: 4109544 events read in total (182155ms).
[15:03:13.038] <TB3> INFO: 4695456 events read in total (208555ms).
[15:03:27.689] <TB3> INFO: 5025280 events read in total (223206ms).
[15:03:27.863] <TB3> INFO: Test took 224212ms.
[15:03:50.072] <TB3> INFO: ---> TrimStepCorr4 extremal thresholds: 6.228706 .. 147.427068
[15:03:50.309] <TB3> INFO: Expecting 208000 events.
[15:03:59.998] <TB3> INFO: 208000 events read in total (9095ms).
[15:03:59.999] <TB3> INFO: Test took 9926ms.
[15:04:00.047] <TB3> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 6 .. 157 (-1/-1) hits flags = 528 (plus default)
[15:04:00.059] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[15:04:00.059] <TB3> INFO: run 1 of 1
[15:04:00.337] <TB3> INFO: Expecting 5058560 events.
[15:04:26.414] <TB3> INFO: 576920 events read in total (25485ms).
[15:04:52.027] <TB3> INFO: 1154288 events read in total (51098ms).
[15:05:17.572] <TB3> INFO: 1731160 events read in total (76643ms).
[15:05:43.509] <TB3> INFO: 2307944 events read in total (102580ms).
[15:06:08.849] <TB3> INFO: 2885104 events read in total (127920ms).
[15:06:34.555] <TB3> INFO: 3461488 events read in total (153626ms).
[15:07:00.394] <TB3> INFO: 4037792 events read in total (179465ms).
[15:07:25.708] <TB3> INFO: 4613280 events read in total (204779ms).
[15:07:46.120] <TB3> INFO: 5058560 events read in total (225191ms).
[15:07:46.206] <TB3> INFO: Test took 226147ms.
[15:08:12.204] <TB3> INFO: ---> TrimStepCorr2 extremal thresholds: 27.338371 .. 45.397690
[15:08:12.444] <TB3> INFO: Expecting 208000 events.
[15:08:22.032] <TB3> INFO: 208000 events read in total (8996ms).
[15:08:22.032] <TB3> INFO: Test took 9826ms.
[15:08:22.079] <TB3> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 55 (-1/-1) hits flags = 528 (plus default)
[15:08:22.093] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[15:08:22.093] <TB3> INFO: run 1 of 1
[15:08:22.371] <TB3> INFO: Expecting 1297920 events.
[15:08:50.457] <TB3> INFO: 658536 events read in total (27495ms).
[15:09:17.343] <TB3> INFO: 1297920 events read in total (54381ms).
[15:09:17.388] <TB3> INFO: Test took 55295ms.
[15:09:31.238] <TB3> INFO: ---> TrimStepCorr1a extremal thresholds: 25.632110 .. 48.140578
[15:09:31.479] <TB3> INFO: Expecting 208000 events.
[15:09:41.121] <TB3> INFO: 208000 events read in total (9050ms).
[15:09:41.122] <TB3> INFO: Test took 9883ms.
[15:09:41.169] <TB3> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 58 (-1/-1) hits flags = 528 (plus default)
[15:09:41.183] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[15:09:41.183] <TB3> INFO: run 1 of 1
[15:09:41.461] <TB3> INFO: Expecting 1464320 events.
[15:10:09.375] <TB3> INFO: 655840 events read in total (27322ms).
[15:10:36.779] <TB3> INFO: 1311448 events read in total (54726ms).
[15:10:43.770] <TB3> INFO: 1464320 events read in total (61717ms).
[15:10:43.810] <TB3> INFO: Test took 62628ms.
[15:10:57.391] <TB3> INFO: ---> TrimStepCorr1b extremal thresholds: 25.252438 .. 45.840711
[15:10:57.630] <TB3> INFO: Expecting 208000 events.
[15:11:07.275] <TB3> INFO: 208000 events read in total (9054ms).
[15:11:07.276] <TB3> INFO: Test took 9884ms.
[15:11:07.325] <TB3> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[15:11:07.337] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[15:11:07.337] <TB3> INFO: run 1 of 1
[15:11:07.616] <TB3> INFO: Expecting 1364480 events.
[15:11:36.436] <TB3> INFO: 667512 events read in total (28228ms).
[15:12:04.842] <TB3> INFO: 1334808 events read in total (56634ms).
[15:12:06.631] <TB3> INFO: 1364480 events read in total (58423ms).
[15:12:06.662] <TB3> INFO: Test took 59325ms.
[15:12:20.242] <TB3> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[15:12:20.243] <TB3> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[15:12:20.255] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[15:12:20.255] <TB3> INFO: run 1 of 1
[15:12:20.492] <TB3> INFO: Expecting 1364480 events.
[15:12:49.124] <TB3> INFO: 667408 events read in total (28040ms).
[15:13:17.046] <TB3> INFO: 1334136 events read in total (55962ms).
[15:13:18.792] <TB3> INFO: 1364480 events read in total (57709ms).
[15:13:18.829] <TB3> INFO: Test took 58574ms.
[15:13:32.083] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C0.dat
[15:13:32.083] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C1.dat
[15:13:32.083] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C2.dat
[15:13:32.084] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C3.dat
[15:13:32.084] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C4.dat
[15:13:32.084] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C5.dat
[15:13:32.084] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C6.dat
[15:13:32.084] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C7.dat
[15:13:32.084] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C8.dat
[15:13:32.085] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C9.dat
[15:13:32.085] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C10.dat
[15:13:32.085] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C11.dat
[15:13:32.085] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C12.dat
[15:13:32.085] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C13.dat
[15:13:32.086] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C14.dat
[15:13:32.086] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C15.dat
[15:13:32.086] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C0.dat
[15:13:32.098] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C1.dat
[15:13:32.104] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C2.dat
[15:13:32.110] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C3.dat
[15:13:32.116] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C4.dat
[15:13:32.122] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C5.dat
[15:13:32.127] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C6.dat
[15:13:32.132] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C7.dat
[15:13:32.136] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C8.dat
[15:13:32.141] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C9.dat
[15:13:32.146] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C10.dat
[15:13:32.150] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C11.dat
[15:13:32.155] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C12.dat
[15:13:32.160] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C13.dat
[15:13:32.164] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C14.dat
[15:13:32.169] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C15.dat
[15:13:32.174] <TB3> INFO: PixTestTrim::trimTest() done
[15:13:32.174] <TB3> INFO: vtrim: 128 135 127 124 127 137 141 155 95 124 127 126 125 126 134 132
[15:13:32.174] <TB3> INFO: vthrcomp: 118 122 108 118 108 112 111 134 118 120 105 112 127 107 102 117
[15:13:32.174] <TB3> INFO: vcal mean: 34.90 34.94 35.08 34.94 35.26 34.95 34.99 34.97 35.04 35.02 35.08 35.03 34.92 34.94 34.98 34.94
[15:13:32.174] <TB3> INFO: vcal RMS: 1.05 1.04 1.12 1.07 1.30 0.95 1.07 1.10 1.00 1.02 1.30 1.23 1.04 0.96 0.95 1.09
[15:13:32.174] <TB3> INFO: bits mean: 9.40 9.58 8.74 9.46 8.83 9.49 9.10 8.56 8.86 9.00 9.23 9.54 9.82 8.85 9.43 9.69
[15:13:32.174] <TB3> INFO: bits RMS: 2.86 2.68 2.53 2.79 2.63 2.59 2.46 2.52 3.10 3.04 2.48 2.65 2.60 2.50 2.48 2.66
[15:13:32.181] <TB3> INFO: ----------------------------------------------------------------------
[15:13:32.181] <TB3> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[15:13:32.181] <TB3> INFO: ----------------------------------------------------------------------
[15:13:32.184] <TB3> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[15:13:32.198] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[15:13:32.198] <TB3> INFO: run 1 of 1
[15:13:32.478] <TB3> INFO: Expecting 4160000 events.
[15:14:05.157] <TB3> INFO: 744020 events read in total (32087ms).
[15:14:37.097] <TB3> INFO: 1480905 events read in total (64027ms).
[15:15:09.340] <TB3> INFO: 2213975 events read in total (96270ms).
[15:15:41.436] <TB3> INFO: 2944785 events read in total (128366ms).
[15:16:13.291] <TB3> INFO: 3673130 events read in total (160221ms).
[15:16:34.689] <TB3> INFO: 4160000 events read in total (181619ms).
[15:16:34.772] <TB3> INFO: Test took 182574ms.
[15:17:06.723] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[15:17:06.736] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[15:17:06.736] <TB3> INFO: run 1 of 1
[15:17:06.980] <TB3> INFO: Expecting 4305600 events.
[15:17:38.846] <TB3> INFO: 711920 events read in total (31275ms).
[15:18:09.655] <TB3> INFO: 1418745 events read in total (62084ms).
[15:18:40.589] <TB3> INFO: 2122490 events read in total (93019ms).
[15:19:11.305] <TB3> INFO: 2823045 events read in total (123734ms).
[15:19:42.005] <TB3> INFO: 3523465 events read in total (154434ms).
[15:20:13.315] <TB3> INFO: 4221995 events read in total (185744ms).
[15:20:17.392] <TB3> INFO: 4305600 events read in total (189821ms).
[15:20:17.502] <TB3> INFO: Test took 190765ms.
[15:20:42.305] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 215 (-1/-1) hits flags = 528 (plus default)
[15:20:42.320] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[15:20:42.320] <TB3> INFO: run 1 of 1
[15:20:42.564] <TB3> INFO: Expecting 4492800 events.
[15:21:14.124] <TB3> INFO: 702305 events read in total (30969ms).
[15:21:45.122] <TB3> INFO: 1400270 events read in total (61967ms).
[15:22:16.330] <TB3> INFO: 2095895 events read in total (93175ms).
[15:22:46.681] <TB3> INFO: 2787800 events read in total (123526ms).
[15:23:17.288] <TB3> INFO: 3479735 events read in total (154133ms).
[15:23:48.915] <TB3> INFO: 4168795 events read in total (185760ms).
[15:24:03.505] <TB3> INFO: 4492800 events read in total (200350ms).
[15:24:03.618] <TB3> INFO: Test took 201298ms.
[15:24:31.528] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 219 (-1/-1) hits flags = 528 (plus default)
[15:24:31.541] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[15:24:31.542] <TB3> INFO: run 1 of 1
[15:24:31.785] <TB3> INFO: Expecting 4576000 events.
[15:25:03.455] <TB3> INFO: 698675 events read in total (31078ms).
[15:25:34.450] <TB3> INFO: 1393035 events read in total (62073ms).
[15:26:05.337] <TB3> INFO: 2085285 events read in total (92960ms).
[15:26:36.883] <TB3> INFO: 2774015 events read in total (124506ms).
[15:27:07.171] <TB3> INFO: 3462550 events read in total (154794ms).
[15:27:37.483] <TB3> INFO: 4148230 events read in total (185106ms).
[15:27:56.429] <TB3> INFO: 4576000 events read in total (204052ms).
[15:27:56.561] <TB3> INFO: Test took 205019ms.
[15:28:22.444] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 219 (-1/-1) hits flags = 528 (plus default)
[15:28:22.457] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[15:28:22.457] <TB3> INFO: run 1 of 1
[15:28:22.696] <TB3> INFO: Expecting 4576000 events.
[15:28:54.178] <TB3> INFO: 699150 events read in total (30890ms).
[15:29:24.850] <TB3> INFO: 1393760 events read in total (61562ms).
[15:29:56.343] <TB3> INFO: 2086455 events read in total (93055ms).
[15:30:26.818] <TB3> INFO: 2775480 events read in total (123530ms).
[15:30:57.689] <TB3> INFO: 3464360 events read in total (154401ms).
[15:31:28.332] <TB3> INFO: 4150390 events read in total (185044ms).
[15:31:47.224] <TB3> INFO: 4576000 events read in total (203936ms).
[15:31:47.347] <TB3> INFO: Test took 204889ms.
[15:32:12.950] <TB3> INFO: PixTestTrim::trimBitTest() done
[15:32:12.951] <TB3> INFO: PixTestTrim::doTest() done, duration: 2551 seconds
[15:32:12.951] <TB3> INFO: Decoding statistics:
[15:32:12.951] <TB3> INFO: General information:
[15:32:12.951] <TB3> INFO: 16bit words read: 0
[15:32:12.951] <TB3> INFO: valid events total: 0
[15:32:12.951] <TB3> INFO: empty events: 0
[15:32:12.951] <TB3> INFO: valid events with pixels: 0
[15:32:12.951] <TB3> INFO: valid pixel hits: 0
[15:32:12.951] <TB3> INFO: Event errors: 0
[15:32:12.951] <TB3> INFO: start marker: 0
[15:32:12.951] <TB3> INFO: stop marker: 0
[15:32:12.951] <TB3> INFO: overflow: 0
[15:32:12.951] <TB3> INFO: invalid 5bit words: 0
[15:32:12.951] <TB3> INFO: invalid XOR eye diagram: 0
[15:32:12.951] <TB3> INFO: frame (failed synchr.): 0
[15:32:12.951] <TB3> INFO: idle data (no TBM trl): 0
[15:32:12.951] <TB3> INFO: no data (only TBM hdr): 0
[15:32:12.951] <TB3> INFO: TBM errors: 0
[15:32:12.951] <TB3> INFO: flawed TBM headers: 0
[15:32:12.951] <TB3> INFO: flawed TBM trailers: 0
[15:32:12.951] <TB3> INFO: event ID mismatches: 0
[15:32:12.951] <TB3> INFO: ROC errors: 0
[15:32:12.951] <TB3> INFO: missing ROC header(s): 0
[15:32:12.951] <TB3> INFO: misplaced readback start: 0
[15:32:12.951] <TB3> INFO: Pixel decoding errors: 0
[15:32:12.951] <TB3> INFO: pixel data incomplete: 0
[15:32:12.951] <TB3> INFO: pixel address: 0
[15:32:12.951] <TB3> INFO: pulse height fill bit: 0
[15:32:12.951] <TB3> INFO: buffer corruption: 0
[15:32:13.564] <TB3> INFO: ######################################################################
[15:32:13.564] <TB3> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[15:32:13.564] <TB3> INFO: ######################################################################
[15:32:13.803] <TB3> INFO: Expecting 41600 events.
[15:32:17.350] <TB3> INFO: 41600 events read in total (2954ms).
[15:32:17.351] <TB3> INFO: Test took 3785ms.
[15:32:17.800] <TB3> INFO: Expecting 41600 events.
[15:32:21.459] <TB3> INFO: 41600 events read in total (3067ms).
[15:32:21.459] <TB3> INFO: Test took 3905ms.
[15:32:21.749] <TB3> INFO: Expecting 41600 events.
[15:32:25.305] <TB3> INFO: 41600 events read in total (2965ms).
[15:32:25.306] <TB3> INFO: Test took 3823ms.
[15:32:25.596] <TB3> INFO: Expecting 41600 events.
[15:32:29.134] <TB3> INFO: 41600 events read in total (2945ms).
[15:32:29.134] <TB3> INFO: Test took 3804ms.
[15:32:29.448] <TB3> INFO: Expecting 41600 events.
[15:32:32.975] <TB3> INFO: 41600 events read in total (2936ms).
[15:32:32.976] <TB3> INFO: Test took 3817ms.
[15:32:33.280] <TB3> INFO: Expecting 41600 events.
[15:32:36.798] <TB3> INFO: 41600 events read in total (2926ms).
[15:32:36.799] <TB3> INFO: Test took 3799ms.
[15:32:37.088] <TB3> INFO: Expecting 41600 events.
[15:32:40.619] <TB3> INFO: 41600 events read in total (2939ms).
[15:32:40.620] <TB3> INFO: Test took 3797ms.
[15:32:40.909] <TB3> INFO: Expecting 41600 events.
[15:32:44.472] <TB3> INFO: 41600 events read in total (2971ms).
[15:32:44.472] <TB3> INFO: Test took 3828ms.
[15:32:44.761] <TB3> INFO: Expecting 41600 events.
[15:32:48.370] <TB3> INFO: 41600 events read in total (3017ms).
[15:32:48.371] <TB3> INFO: Test took 3875ms.
[15:32:48.661] <TB3> INFO: Expecting 41600 events.
[15:32:52.298] <TB3> INFO: 41600 events read in total (3045ms).
[15:32:52.298] <TB3> INFO: Test took 3902ms.
[15:32:52.591] <TB3> INFO: Expecting 41600 events.
[15:32:56.174] <TB3> INFO: 41600 events read in total (2991ms).
[15:32:56.175] <TB3> INFO: Test took 3850ms.
[15:32:56.465] <TB3> INFO: Expecting 41600 events.
[15:33:00.033] <TB3> INFO: 41600 events read in total (2977ms).
[15:33:00.033] <TB3> INFO: Test took 3834ms.
[15:33:00.322] <TB3> INFO: Expecting 41600 events.
[15:33:03.829] <TB3> INFO: 41600 events read in total (2915ms).
[15:33:03.830] <TB3> INFO: Test took 3772ms.
[15:33:04.124] <TB3> INFO: Expecting 41600 events.
[15:33:07.636] <TB3> INFO: 41600 events read in total (2920ms).
[15:33:07.637] <TB3> INFO: Test took 3778ms.
[15:33:07.926] <TB3> INFO: Expecting 41600 events.
[15:33:11.423] <TB3> INFO: 41600 events read in total (2905ms).
[15:33:11.424] <TB3> INFO: Test took 3763ms.
[15:33:11.714] <TB3> INFO: Expecting 41600 events.
[15:33:15.270] <TB3> INFO: 41600 events read in total (2964ms).
[15:33:15.271] <TB3> INFO: Test took 3822ms.
[15:33:15.566] <TB3> INFO: Expecting 41600 events.
[15:33:19.072] <TB3> INFO: 41600 events read in total (2914ms).
[15:33:19.073] <TB3> INFO: Test took 3775ms.
[15:33:19.366] <TB3> INFO: Expecting 41600 events.
[15:33:22.967] <TB3> INFO: 41600 events read in total (3009ms).
[15:33:22.968] <TB3> INFO: Test took 3868ms.
[15:33:23.258] <TB3> INFO: Expecting 41600 events.
[15:33:26.767] <TB3> INFO: 41600 events read in total (2918ms).
[15:33:26.768] <TB3> INFO: Test took 3775ms.
[15:33:27.057] <TB3> INFO: Expecting 41600 events.
[15:33:30.585] <TB3> INFO: 41600 events read in total (2936ms).
[15:33:30.585] <TB3> INFO: Test took 3793ms.
[15:33:30.881] <TB3> INFO: Expecting 41600 events.
[15:33:34.495] <TB3> INFO: 41600 events read in total (3022ms).
[15:33:34.495] <TB3> INFO: Test took 3885ms.
[15:33:34.786] <TB3> INFO: Expecting 41600 events.
[15:33:38.286] <TB3> INFO: 41600 events read in total (2908ms).
[15:33:38.287] <TB3> INFO: Test took 3767ms.
[15:33:38.576] <TB3> INFO: Expecting 41600 events.
[15:33:42.107] <TB3> INFO: 41600 events read in total (2939ms).
[15:33:42.108] <TB3> INFO: Test took 3797ms.
[15:33:42.398] <TB3> INFO: Expecting 41600 events.
[15:33:45.921] <TB3> INFO: 41600 events read in total (2931ms).
[15:33:45.922] <TB3> INFO: Test took 3789ms.
[15:33:46.214] <TB3> INFO: Expecting 41600 events.
[15:33:49.746] <TB3> INFO: 41600 events read in total (2940ms).
[15:33:49.747] <TB3> INFO: Test took 3798ms.
[15:33:50.037] <TB3> INFO: Expecting 41600 events.
[15:33:53.582] <TB3> INFO: 41600 events read in total (2954ms).
[15:33:53.583] <TB3> INFO: Test took 3812ms.
[15:33:53.876] <TB3> INFO: Expecting 41600 events.
[15:33:57.562] <TB3> INFO: 41600 events read in total (3094ms).
[15:33:57.562] <TB3> INFO: Test took 3951ms.
[15:33:57.852] <TB3> INFO: Expecting 41600 events.
[15:34:01.443] <TB3> INFO: 41600 events read in total (2999ms).
[15:34:01.444] <TB3> INFO: Test took 3858ms.
[15:34:01.737] <TB3> INFO: Expecting 41600 events.
[15:34:05.285] <TB3> INFO: 41600 events read in total (2956ms).
[15:34:05.286] <TB3> INFO: Test took 3814ms.
[15:34:05.596] <TB3> INFO: Expecting 41600 events.
[15:34:09.217] <TB3> INFO: 41600 events read in total (3029ms).
[15:34:09.217] <TB3> INFO: Test took 3907ms.
[15:34:09.511] <TB3> INFO: Expecting 41600 events.
[15:34:13.053] <TB3> INFO: 41600 events read in total (2950ms).
[15:34:13.054] <TB3> INFO: Test took 3808ms.
[15:34:13.344] <TB3> INFO: Expecting 2560 events.
[15:34:14.230] <TB3> INFO: 2560 events read in total (294ms).
[15:34:14.231] <TB3> INFO: Test took 1164ms.
[15:34:14.539] <TB3> INFO: Expecting 2560 events.
[15:34:15.425] <TB3> INFO: 2560 events read in total (294ms).
[15:34:15.425] <TB3> INFO: Test took 1194ms.
[15:34:15.734] <TB3> INFO: Expecting 2560 events.
[15:34:16.625] <TB3> INFO: 2560 events read in total (299ms).
[15:34:16.625] <TB3> INFO: Test took 1199ms.
[15:34:16.934] <TB3> INFO: Expecting 2560 events.
[15:34:17.819] <TB3> INFO: 2560 events read in total (294ms).
[15:34:17.819] <TB3> INFO: Test took 1193ms.
[15:34:18.127] <TB3> INFO: Expecting 2560 events.
[15:34:19.008] <TB3> INFO: 2560 events read in total (289ms).
[15:34:19.009] <TB3> INFO: Test took 1190ms.
[15:34:19.316] <TB3> INFO: Expecting 2560 events.
[15:34:20.199] <TB3> INFO: 2560 events read in total (292ms).
[15:34:20.199] <TB3> INFO: Test took 1190ms.
[15:34:20.507] <TB3> INFO: Expecting 2560 events.
[15:34:21.392] <TB3> INFO: 2560 events read in total (293ms).
[15:34:21.392] <TB3> INFO: Test took 1192ms.
[15:34:21.700] <TB3> INFO: Expecting 2560 events.
[15:34:22.582] <TB3> INFO: 2560 events read in total (291ms).
[15:34:22.583] <TB3> INFO: Test took 1190ms.
[15:34:22.890] <TB3> INFO: Expecting 2560 events.
[15:34:23.785] <TB3> INFO: 2560 events read in total (304ms).
[15:34:23.785] <TB3> INFO: Test took 1201ms.
[15:34:24.092] <TB3> INFO: Expecting 2560 events.
[15:34:24.976] <TB3> INFO: 2560 events read in total (292ms).
[15:34:24.976] <TB3> INFO: Test took 1190ms.
[15:34:25.283] <TB3> INFO: Expecting 2560 events.
[15:34:26.163] <TB3> INFO: 2560 events read in total (288ms).
[15:34:26.163] <TB3> INFO: Test took 1186ms.
[15:34:26.471] <TB3> INFO: Expecting 2560 events.
[15:34:27.359] <TB3> INFO: 2560 events read in total (296ms).
[15:34:27.360] <TB3> INFO: Test took 1197ms.
[15:34:27.668] <TB3> INFO: Expecting 2560 events.
[15:34:28.556] <TB3> INFO: 2560 events read in total (296ms).
[15:34:28.557] <TB3> INFO: Test took 1197ms.
[15:34:28.866] <TB3> INFO: Expecting 2560 events.
[15:34:29.753] <TB3> INFO: 2560 events read in total (296ms).
[15:34:29.753] <TB3> INFO: Test took 1196ms.
[15:34:30.060] <TB3> INFO: Expecting 2560 events.
[15:34:30.952] <TB3> INFO: 2560 events read in total (300ms).
[15:34:30.953] <TB3> INFO: Test took 1199ms.
[15:34:31.260] <TB3> INFO: Expecting 2560 events.
[15:34:32.153] <TB3> INFO: 2560 events read in total (301ms).
[15:34:32.153] <TB3> INFO: Test took 1200ms.
[15:34:32.156] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:34:32.461] <TB3> INFO: Expecting 655360 events.
[15:34:47.185] <TB3> INFO: 655360 events read in total (14132ms).
[15:34:47.197] <TB3> INFO: Expecting 655360 events.
[15:35:01.701] <TB3> INFO: 655360 events read in total (14100ms).
[15:35:01.718] <TB3> INFO: Expecting 655360 events.
[15:35:16.321] <TB3> INFO: 655360 events read in total (14200ms).
[15:35:16.350] <TB3> INFO: Expecting 655360 events.
[15:35:30.844] <TB3> INFO: 655360 events read in total (14091ms).
[15:35:30.875] <TB3> INFO: Expecting 655360 events.
[15:35:45.487] <TB3> INFO: 655360 events read in total (14209ms).
[15:35:45.516] <TB3> INFO: Expecting 655360 events.
[15:36:00.047] <TB3> INFO: 655360 events read in total (14128ms).
[15:36:00.090] <TB3> INFO: Expecting 655360 events.
[15:36:14.542] <TB3> INFO: 655360 events read in total (14048ms).
[15:36:14.585] <TB3> INFO: Expecting 655360 events.
[15:36:29.147] <TB3> INFO: 655360 events read in total (14158ms).
[15:36:29.192] <TB3> INFO: Expecting 655360 events.
[15:36:43.656] <TB3> INFO: 655360 events read in total (14061ms).
[15:36:43.717] <TB3> INFO: Expecting 655360 events.
[15:36:58.316] <TB3> INFO: 655360 events read in total (14196ms).
[15:36:58.369] <TB3> INFO: Expecting 655360 events.
[15:37:12.983] <TB3> INFO: 655360 events read in total (14211ms).
[15:37:13.056] <TB3> INFO: Expecting 655360 events.
[15:37:27.654] <TB3> INFO: 655360 events read in total (14194ms).
[15:37:27.758] <TB3> INFO: Expecting 655360 events.
[15:37:42.456] <TB3> INFO: 655360 events read in total (14295ms).
[15:37:42.536] <TB3> INFO: Expecting 655360 events.
[15:37:57.242] <TB3> INFO: 655360 events read in total (14303ms).
[15:37:57.328] <TB3> INFO: Expecting 655360 events.
[15:38:11.841] <TB3> INFO: 655360 events read in total (14110ms).
[15:38:11.976] <TB3> INFO: Expecting 655360 events.
[15:38:26.690] <TB3> INFO: 655360 events read in total (14311ms).
[15:38:26.871] <TB3> INFO: Test took 234715ms.
[15:38:26.991] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:38:27.243] <TB3> INFO: Expecting 655360 events.
[15:38:42.212] <TB3> INFO: 655360 events read in total (14377ms).
[15:38:42.224] <TB3> INFO: Expecting 655360 events.
[15:38:56.808] <TB3> INFO: 655360 events read in total (14181ms).
[15:38:56.824] <TB3> INFO: Expecting 655360 events.
[15:39:11.541] <TB3> INFO: 655360 events read in total (14315ms).
[15:39:11.562] <TB3> INFO: Expecting 655360 events.
[15:39:26.019] <TB3> INFO: 655360 events read in total (14054ms).
[15:39:26.051] <TB3> INFO: Expecting 655360 events.
[15:39:40.576] <TB3> INFO: 655360 events read in total (14122ms).
[15:39:40.608] <TB3> INFO: Expecting 655360 events.
[15:39:55.394] <TB3> INFO: 655360 events read in total (14383ms).
[15:39:55.435] <TB3> INFO: Expecting 655360 events.
[15:40:10.206] <TB3> INFO: 655360 events read in total (14367ms).
[15:40:10.243] <TB3> INFO: Expecting 655360 events.
[15:40:24.872] <TB3> INFO: 655360 events read in total (14226ms).
[15:40:24.917] <TB3> INFO: Expecting 655360 events.
[15:40:40.022] <TB3> INFO: 655360 events read in total (14702ms).
[15:40:40.070] <TB3> INFO: Expecting 655360 events.
[15:40:55.213] <TB3> INFO: 655360 events read in total (14739ms).
[15:40:55.267] <TB3> INFO: Expecting 655360 events.
[15:41:09.879] <TB3> INFO: 655360 events read in total (14209ms).
[15:41:09.931] <TB3> INFO: Expecting 655360 events.
[15:41:24.899] <TB3> INFO: 655360 events read in total (14565ms).
[15:41:25.015] <TB3> INFO: Expecting 655360 events.
[15:41:39.783] <TB3> INFO: 655360 events read in total (14365ms).
[15:41:39.892] <TB3> INFO: Expecting 655360 events.
[15:41:54.432] <TB3> INFO: 655360 events read in total (14137ms).
[15:41:54.518] <TB3> INFO: Expecting 655360 events.
[15:42:09.484] <TB3> INFO: 655360 events read in total (14563ms).
[15:42:09.581] <TB3> INFO: Expecting 655360 events.
[15:42:24.304] <TB3> INFO: 655360 events read in total (14319ms).
[15:42:24.445] <TB3> INFO: Test took 237454ms.
[15:42:24.615] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.621] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.627] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.632] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.638] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.644] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.649] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.655] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[15:42:24.661] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[15:42:24.667] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.672] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.678] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.684] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.689] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[15:42:24.695] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[15:42:24.701] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[15:42:24.707] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.713] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.718] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.724] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[15:42:24.730] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.735] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:42:24.769] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C0.dat
[15:42:24.769] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C1.dat
[15:42:24.769] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C2.dat
[15:42:24.769] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C3.dat
[15:42:24.769] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C4.dat
[15:42:24.769] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C5.dat
[15:42:24.769] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C6.dat
[15:42:24.769] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C7.dat
[15:42:24.770] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C8.dat
[15:42:24.770] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C9.dat
[15:42:24.770] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C10.dat
[15:42:24.770] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C11.dat
[15:42:24.770] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C12.dat
[15:42:24.770] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C13.dat
[15:42:24.770] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C14.dat
[15:42:24.770] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C15.dat
[15:42:25.017] <TB3> INFO: Expecting 41600 events.
[15:42:28.197] <TB3> INFO: 41600 events read in total (2588ms).
[15:42:28.198] <TB3> INFO: Test took 3425ms.
[15:42:28.658] <TB3> INFO: Expecting 41600 events.
[15:42:31.747] <TB3> INFO: 41600 events read in total (2498ms).
[15:42:31.748] <TB3> INFO: Test took 3335ms.
[15:42:32.197] <TB3> INFO: Expecting 41600 events.
[15:42:35.390] <TB3> INFO: 41600 events read in total (2601ms).
[15:42:35.391] <TB3> INFO: Test took 3432ms.
[15:42:35.610] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:35.700] <TB3> INFO: Expecting 2560 events.
[15:42:36.588] <TB3> INFO: 2560 events read in total (296ms).
[15:42:36.588] <TB3> INFO: Test took 978ms.
[15:42:36.591] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:36.896] <TB3> INFO: Expecting 2560 events.
[15:42:37.784] <TB3> INFO: 2560 events read in total (296ms).
[15:42:37.785] <TB3> INFO: Test took 1194ms.
[15:42:37.787] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:38.094] <TB3> INFO: Expecting 2560 events.
[15:42:38.988] <TB3> INFO: 2560 events read in total (302ms).
[15:42:38.988] <TB3> INFO: Test took 1201ms.
[15:42:38.991] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:39.297] <TB3> INFO: Expecting 2560 events.
[15:42:40.187] <TB3> INFO: 2560 events read in total (299ms).
[15:42:40.188] <TB3> INFO: Test took 1197ms.
[15:42:40.192] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:40.496] <TB3> INFO: Expecting 2560 events.
[15:42:41.389] <TB3> INFO: 2560 events read in total (302ms).
[15:42:41.390] <TB3> INFO: Test took 1198ms.
[15:42:41.394] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:41.698] <TB3> INFO: Expecting 2560 events.
[15:42:42.592] <TB3> INFO: 2560 events read in total (300ms).
[15:42:42.592] <TB3> INFO: Test took 1198ms.
[15:42:42.595] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:42.901] <TB3> INFO: Expecting 2560 events.
[15:42:43.793] <TB3> INFO: 2560 events read in total (300ms).
[15:42:43.794] <TB3> INFO: Test took 1199ms.
[15:42:43.797] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:44.102] <TB3> INFO: Expecting 2560 events.
[15:42:44.998] <TB3> INFO: 2560 events read in total (304ms).
[15:42:44.999] <TB3> INFO: Test took 1203ms.
[15:42:44.002] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:45.308] <TB3> INFO: Expecting 2560 events.
[15:42:46.193] <TB3> INFO: 2560 events read in total (293ms).
[15:42:46.194] <TB3> INFO: Test took 1192ms.
[15:42:46.197] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:46.501] <TB3> INFO: Expecting 2560 events.
[15:42:47.393] <TB3> INFO: 2560 events read in total (300ms).
[15:42:47.394] <TB3> INFO: Test took 1197ms.
[15:42:47.397] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:47.701] <TB3> INFO: Expecting 2560 events.
[15:42:48.591] <TB3> INFO: 2560 events read in total (298ms).
[15:42:48.592] <TB3> INFO: Test took 1195ms.
[15:42:48.598] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:48.899] <TB3> INFO: Expecting 2560 events.
[15:42:49.791] <TB3> INFO: 2560 events read in total (300ms).
[15:42:49.791] <TB3> INFO: Test took 1193ms.
[15:42:49.795] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:50.098] <TB3> INFO: Expecting 2560 events.
[15:42:50.979] <TB3> INFO: 2560 events read in total (289ms).
[15:42:50.979] <TB3> INFO: Test took 1184ms.
[15:42:50.983] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:51.286] <TB3> INFO: Expecting 2560 events.
[15:42:52.177] <TB3> INFO: 2560 events read in total (299ms).
[15:42:52.178] <TB3> INFO: Test took 1196ms.
[15:42:52.181] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:52.487] <TB3> INFO: Expecting 2560 events.
[15:42:53.377] <TB3> INFO: 2560 events read in total (299ms).
[15:42:53.378] <TB3> INFO: Test took 1197ms.
[15:42:53.381] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:53.685] <TB3> INFO: Expecting 2560 events.
[15:42:54.572] <TB3> INFO: 2560 events read in total (295ms).
[15:42:54.572] <TB3> INFO: Test took 1192ms.
[15:42:54.575] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:54.880] <TB3> INFO: Expecting 2560 events.
[15:42:55.761] <TB3> INFO: 2560 events read in total (289ms).
[15:42:55.762] <TB3> INFO: Test took 1187ms.
[15:42:55.765] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:56.070] <TB3> INFO: Expecting 2560 events.
[15:42:56.958] <TB3> INFO: 2560 events read in total (296ms).
[15:42:56.959] <TB3> INFO: Test took 1194ms.
[15:42:56.964] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:57.267] <TB3> INFO: Expecting 2560 events.
[15:42:58.148] <TB3> INFO: 2560 events read in total (289ms).
[15:42:58.148] <TB3> INFO: Test took 1184ms.
[15:42:58.151] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:58.457] <TB3> INFO: Expecting 2560 events.
[15:42:59.337] <TB3> INFO: 2560 events read in total (288ms).
[15:42:59.338] <TB3> INFO: Test took 1187ms.
[15:42:59.340] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:42:59.647] <TB3> INFO: Expecting 2560 events.
[15:43:00.537] <TB3> INFO: 2560 events read in total (299ms).
[15:43:00.537] <TB3> INFO: Test took 1197ms.
[15:43:00.541] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:43:00.845] <TB3> INFO: Expecting 2560 events.
[15:43:01.733] <TB3> INFO: 2560 events read in total (296ms).
[15:43:01.733] <TB3> INFO: Test took 1193ms.
[15:43:01.737] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:43:02.041] <TB3> INFO: Expecting 2560 events.
[15:43:02.927] <TB3> INFO: 2560 events read in total (294ms).
[15:43:02.928] <TB3> INFO: Test took 1191ms.
[15:43:02.930] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:43:03.236] <TB3> INFO: Expecting 2560 events.
[15:43:04.118] <TB3> INFO: 2560 events read in total (290ms).
[15:43:04.118] <TB3> INFO: Test took 1189ms.
[15:43:04.120] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:43:04.426] <TB3> INFO: Expecting 2560 events.
[15:43:05.312] <TB3> INFO: 2560 events read in total (294ms).
[15:43:05.312] <TB3> INFO: Test took 1192ms.
[15:43:05.314] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:43:05.621] <TB3> INFO: Expecting 2560 events.
[15:43:06.504] <TB3> INFO: 2560 events read in total (292ms).
[15:43:06.504] <TB3> INFO: Test took 1190ms.
[15:43:06.506] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:43:06.813] <TB3> INFO: Expecting 2560 events.
[15:43:07.695] <TB3> INFO: 2560 events read in total (291ms).
[15:43:07.696] <TB3> INFO: Test took 1190ms.
[15:43:07.697] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:43:08.004] <TB3> INFO: Expecting 2560 events.
[15:43:08.888] <TB3> INFO: 2560 events read in total (292ms).
[15:43:08.888] <TB3> INFO: Test took 1191ms.
[15:43:08.890] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:43:09.197] <TB3> INFO: Expecting 2560 events.
[15:43:10.079] <TB3> INFO: 2560 events read in total (291ms).
[15:43:10.080] <TB3> INFO: Test took 1190ms.
[15:43:10.083] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:43:10.389] <TB3> INFO: Expecting 2560 events.
[15:43:11.271] <TB3> INFO: 2560 events read in total (291ms).
[15:43:11.271] <TB3> INFO: Test took 1188ms.
[15:43:11.273] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:43:11.580] <TB3> INFO: Expecting 2560 events.
[15:43:12.465] <TB3> INFO: 2560 events read in total (293ms).
[15:43:12.466] <TB3> INFO: Test took 1193ms.
[15:43:12.468] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:43:12.774] <TB3> INFO: Expecting 2560 events.
[15:43:13.657] <TB3> INFO: 2560 events read in total (292ms).
[15:43:13.657] <TB3> INFO: Test took 1189ms.
[15:43:14.123] <TB3> INFO: PixTestPhOptimization::doTest() done, duration: 660 seconds
[15:43:14.123] <TB3> INFO: PH scale (per ROC): 56 51 61 55 64 59 35 45 55 53 50 53 48 49 53 49
[15:43:14.123] <TB3> INFO: PH offset (per ROC): 123 117 130 135 129 112 97 98 124 111 104 119 108 125 133 111
[15:43:14.132] <TB3> INFO: Decoding statistics:
[15:43:14.132] <TB3> INFO: General information:
[15:43:14.132] <TB3> INFO: 16bit words read: 127890
[15:43:14.132] <TB3> INFO: valid events total: 20480
[15:43:14.132] <TB3> INFO: empty events: 17975
[15:43:14.132] <TB3> INFO: valid events with pixels: 2505
[15:43:14.132] <TB3> INFO: valid pixel hits: 2505
[15:43:14.132] <TB3> INFO: Event errors: 0
[15:43:14.132] <TB3> INFO: start marker: 0
[15:43:14.132] <TB3> INFO: stop marker: 0
[15:43:14.132] <TB3> INFO: overflow: 0
[15:43:14.132] <TB3> INFO: invalid 5bit words: 0
[15:43:14.132] <TB3> INFO: invalid XOR eye diagram: 0
[15:43:14.132] <TB3> INFO: frame (failed synchr.): 0
[15:43:14.132] <TB3> INFO: idle data (no TBM trl): 0
[15:43:14.132] <TB3> INFO: no data (only TBM hdr): 0
[15:43:14.132] <TB3> INFO: TBM errors: 0
[15:43:14.132] <TB3> INFO: flawed TBM headers: 0
[15:43:14.132] <TB3> INFO: flawed TBM trailers: 0
[15:43:14.132] <TB3> INFO: event ID mismatches: 0
[15:43:14.132] <TB3> INFO: ROC errors: 0
[15:43:14.132] <TB3> INFO: missing ROC header(s): 0
[15:43:14.132] <TB3> INFO: misplaced readback start: 0
[15:43:14.132] <TB3> INFO: Pixel decoding errors: 0
[15:43:14.132] <TB3> INFO: pixel data incomplete: 0
[15:43:14.132] <TB3> INFO: pixel address: 0
[15:43:14.132] <TB3> INFO: pulse height fill bit: 0
[15:43:14.132] <TB3> INFO: buffer corruption: 0
[15:43:14.296] <TB3> INFO: ######################################################################
[15:43:14.296] <TB3> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:43:14.296] <TB3> INFO: ######################################################################
[15:43:14.312] <TB3> INFO: scanning low vcal = 10
[15:43:14.548] <TB3> INFO: Expecting 41600 events.
[15:43:18.169] <TB3> INFO: 41600 events read in total (3029ms).
[15:43:18.169] <TB3> INFO: Test took 3857ms.
[15:43:18.174] <TB3> INFO: scanning low vcal = 20
[15:43:18.465] <TB3> INFO: Expecting 41600 events.
[15:43:22.072] <TB3> INFO: 41600 events read in total (3015ms).
[15:43:22.073] <TB3> INFO: Test took 3899ms.
[15:43:22.080] <TB3> INFO: scanning low vcal = 30
[15:43:22.396] <TB3> INFO: Expecting 41600 events.
[15:43:26.075] <TB3> INFO: 41600 events read in total (3087ms).
[15:43:26.077] <TB3> INFO: Test took 3999ms.
[15:43:26.084] <TB3> INFO: scanning low vcal = 40
[15:43:26.360] <TB3> INFO: Expecting 41600 events.
[15:43:30.367] <TB3> INFO: 41600 events read in total (3416ms).
[15:43:30.371] <TB3> INFO: Test took 4287ms.
[15:43:30.376] <TB3> INFO: scanning low vcal = 50
[15:43:30.651] <TB3> INFO: Expecting 41600 events.
[15:43:34.662] <TB3> INFO: 41600 events read in total (3419ms).
[15:43:34.663] <TB3> INFO: Test took 4287ms.
[15:43:34.666] <TB3> INFO: scanning low vcal = 60
[15:43:34.942] <TB3> INFO: Expecting 41600 events.
[15:43:38.944] <TB3> INFO: 41600 events read in total (3410ms).
[15:43:38.945] <TB3> INFO: Test took 4279ms.
[15:43:38.950] <TB3> INFO: scanning low vcal = 70
[15:43:39.224] <TB3> INFO: Expecting 41600 events.
[15:43:43.254] <TB3> INFO: 41600 events read in total (3438ms).
[15:43:43.255] <TB3> INFO: Test took 4305ms.
[15:43:43.258] <TB3> INFO: scanning low vcal = 80
[15:43:43.534] <TB3> INFO: Expecting 41600 events.
[15:43:47.601] <TB3> INFO: 41600 events read in total (3475ms).
[15:43:47.602] <TB3> INFO: Test took 4344ms.
[15:43:47.605] <TB3> INFO: scanning low vcal = 90
[15:43:47.881] <TB3> INFO: Expecting 41600 events.
[15:43:51.877] <TB3> INFO: 41600 events read in total (3404ms).
[15:43:51.877] <TB3> INFO: Test took 4272ms.
[15:43:51.883] <TB3> INFO: scanning low vcal = 100
[15:43:52.157] <TB3> INFO: Expecting 41600 events.
[15:43:56.238] <TB3> INFO: 41600 events read in total (3489ms).
[15:43:56.238] <TB3> INFO: Test took 4355ms.
[15:43:56.242] <TB3> INFO: scanning low vcal = 110
[15:43:56.561] <TB3> INFO: Expecting 41600 events.
[15:44:00.532] <TB3> INFO: 41600 events read in total (3379ms).
[15:44:00.533] <TB3> INFO: Test took 4291ms.
[15:44:00.536] <TB3> INFO: scanning low vcal = 120
[15:44:00.813] <TB3> INFO: Expecting 41600 events.
[15:44:04.763] <TB3> INFO: 41600 events read in total (3358ms).
[15:44:04.763] <TB3> INFO: Test took 4227ms.
[15:44:04.766] <TB3> INFO: scanning low vcal = 130
[15:44:05.043] <TB3> INFO: Expecting 41600 events.
[15:44:08.000] <TB3> INFO: 41600 events read in total (3365ms).
[15:44:08.001] <TB3> INFO: Test took 4234ms.
[15:44:09.004] <TB3> INFO: scanning low vcal = 140
[15:44:09.281] <TB3> INFO: Expecting 41600 events.
[15:44:13.240] <TB3> INFO: 41600 events read in total (3367ms).
[15:44:13.241] <TB3> INFO: Test took 4237ms.
[15:44:13.244] <TB3> INFO: scanning low vcal = 150
[15:44:13.521] <TB3> INFO: Expecting 41600 events.
[15:44:17.475] <TB3> INFO: 41600 events read in total (3362ms).
[15:44:17.476] <TB3> INFO: Test took 4232ms.
[15:44:17.479] <TB3> INFO: scanning low vcal = 160
[15:44:17.756] <TB3> INFO: Expecting 41600 events.
[15:44:21.715] <TB3> INFO: 41600 events read in total (3368ms).
[15:44:21.716] <TB3> INFO: Test took 4237ms.
[15:44:21.719] <TB3> INFO: scanning low vcal = 170
[15:44:21.996] <TB3> INFO: Expecting 41600 events.
[15:44:25.955] <TB3> INFO: 41600 events read in total (3367ms).
[15:44:25.955] <TB3> INFO: Test took 4235ms.
[15:44:25.961] <TB3> INFO: scanning low vcal = 180
[15:44:26.235] <TB3> INFO: Expecting 41600 events.
[15:44:30.189] <TB3> INFO: 41600 events read in total (3362ms).
[15:44:30.190] <TB3> INFO: Test took 4229ms.
[15:44:30.193] <TB3> INFO: scanning low vcal = 190
[15:44:30.470] <TB3> INFO: Expecting 41600 events.
[15:44:34.421] <TB3> INFO: 41600 events read in total (3360ms).
[15:44:34.422] <TB3> INFO: Test took 4229ms.
[15:44:34.425] <TB3> INFO: scanning low vcal = 200
[15:44:34.702] <TB3> INFO: Expecting 41600 events.
[15:44:38.654] <TB3> INFO: 41600 events read in total (3360ms).
[15:44:38.654] <TB3> INFO: Test took 4228ms.
[15:44:38.657] <TB3> INFO: scanning low vcal = 210
[15:44:38.934] <TB3> INFO: Expecting 41600 events.
[15:44:42.884] <TB3> INFO: 41600 events read in total (3358ms).
[15:44:42.885] <TB3> INFO: Test took 4228ms.
[15:44:42.888] <TB3> INFO: scanning low vcal = 220
[15:44:43.165] <TB3> INFO: Expecting 41600 events.
[15:44:47.122] <TB3> INFO: 41600 events read in total (3365ms).
[15:44:47.123] <TB3> INFO: Test took 4235ms.
[15:44:47.126] <TB3> INFO: scanning low vcal = 230
[15:44:47.403] <TB3> INFO: Expecting 41600 events.
[15:44:51.362] <TB3> INFO: 41600 events read in total (3367ms).
[15:44:51.363] <TB3> INFO: Test took 4237ms.
[15:44:51.366] <TB3> INFO: scanning low vcal = 240
[15:44:51.643] <TB3> INFO: Expecting 41600 events.
[15:44:55.600] <TB3> INFO: 41600 events read in total (3365ms).
[15:44:55.601] <TB3> INFO: Test took 4235ms.
[15:44:55.604] <TB3> INFO: scanning low vcal = 250
[15:44:55.881] <TB3> INFO: Expecting 41600 events.
[15:44:59.831] <TB3> INFO: 41600 events read in total (3358ms).
[15:44:59.832] <TB3> INFO: Test took 4228ms.
[15:44:59.836] <TB3> INFO: scanning high vcal = 30 (= 210 in low range)
[15:45:00.112] <TB3> INFO: Expecting 41600 events.
[15:45:04.069] <TB3> INFO: 41600 events read in total (3365ms).
[15:45:04.070] <TB3> INFO: Test took 4234ms.
[15:45:04.073] <TB3> INFO: scanning high vcal = 50 (= 350 in low range)
[15:45:04.350] <TB3> INFO: Expecting 41600 events.
[15:45:08.310] <TB3> INFO: 41600 events read in total (3369ms).
[15:45:08.311] <TB3> INFO: Test took 4238ms.
[15:45:08.314] <TB3> INFO: scanning high vcal = 70 (= 490 in low range)
[15:45:08.591] <TB3> INFO: Expecting 41600 events.
[15:45:12.550] <TB3> INFO: 41600 events read in total (3367ms).
[15:45:12.551] <TB3> INFO: Test took 4237ms.
[15:45:12.554] <TB3> INFO: scanning high vcal = 90 (= 630 in low range)
[15:45:12.831] <TB3> INFO: Expecting 41600 events.
[15:45:16.791] <TB3> INFO: 41600 events read in total (3368ms).
[15:45:16.792] <TB3> INFO: Test took 4238ms.
[15:45:16.795] <TB3> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:45:17.072] <TB3> INFO: Expecting 41600 events.
[15:45:21.029] <TB3> INFO: 41600 events read in total (3366ms).
[15:45:21.030] <TB3> INFO: Test took 4235ms.
[15:45:21.417] <TB3> INFO: PixTestGainPedestal::measure() done
[15:45:53.781] <TB3> INFO: PixTestGainPedestal::fit() done
[15:45:53.781] <TB3> INFO: non-linearity mean: 0.979 0.975 0.981 0.981 0.986 0.983 0.982 0.900 0.981 0.950 0.958 0.982 0.953 0.967 0.980 0.943
[15:45:53.781] <TB3> INFO: non-linearity RMS: 0.004 0.003 0.002 0.006 0.003 0.003 0.181 0.088 0.010 0.053 0.052 0.004 0.060 0.030 0.004 0.050
[15:45:53.781] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[15:45:53.796] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[15:45:53.811] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[15:45:53.825] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[15:45:53.839] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[15:45:53.853] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[15:45:53.866] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[15:45:53.881] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[15:45:53.894] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[15:45:53.908] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[15:45:53.922] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[15:45:53.936] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[15:45:53.950] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[15:45:53.963] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[15:45:53.978] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[15:45:53.992] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[15:45:54.006] <TB3> INFO: PixTestGainPedestal::fullTest() done, duration: 159 seconds
[15:45:54.006] <TB3> INFO: Decoding statistics:
[15:45:54.006] <TB3> INFO: General information:
[15:45:54.006] <TB3> INFO: 16bit words read: 3327828
[15:45:54.006] <TB3> INFO: valid events total: 332800
[15:45:54.006] <TB3> INFO: empty events: 0
[15:45:54.006] <TB3> INFO: valid events with pixels: 332800
[15:45:54.006] <TB3> INFO: valid pixel hits: 665514
[15:45:54.006] <TB3> INFO: Event errors: 0
[15:45:54.006] <TB3> INFO: start marker: 0
[15:45:54.006] <TB3> INFO: stop marker: 0
[15:45:54.006] <TB3> INFO: overflow: 0
[15:45:54.006] <TB3> INFO: invalid 5bit words: 0
[15:45:54.006] <TB3> INFO: invalid XOR eye diagram: 0
[15:45:54.006] <TB3> INFO: frame (failed synchr.): 0
[15:45:54.006] <TB3> INFO: idle data (no TBM trl): 0
[15:45:54.006] <TB3> INFO: no data (only TBM hdr): 0
[15:45:54.006] <TB3> INFO: TBM errors: 0
[15:45:54.006] <TB3> INFO: flawed TBM headers: 0
[15:45:54.006] <TB3> INFO: flawed TBM trailers: 0
[15:45:54.006] <TB3> INFO: event ID mismatches: 0
[15:45:54.006] <TB3> INFO: ROC errors: 0
[15:45:54.006] <TB3> INFO: missing ROC header(s): 0
[15:45:54.006] <TB3> INFO: misplaced readback start: 0
[15:45:54.006] <TB3> INFO: Pixel decoding errors: 0
[15:45:54.006] <TB3> INFO: pixel data incomplete: 0
[15:45:54.006] <TB3> INFO: pixel address: 0
[15:45:54.006] <TB3> INFO: pulse height fill bit: 0
[15:45:54.006] <TB3> INFO: buffer corruption: 0
[15:45:54.023] <TB3> INFO: Decoding statistics:
[15:45:54.024] <TB3> INFO: General information:
[15:45:54.024] <TB3> INFO: 16bit words read: 3457254
[15:45:54.024] <TB3> INFO: valid events total: 353536
[15:45:54.024] <TB3> INFO: empty events: 18231
[15:45:54.024] <TB3> INFO: valid events with pixels: 335305
[15:45:54.024] <TB3> INFO: valid pixel hits: 668019
[15:45:54.024] <TB3> INFO: Event errors: 0
[15:45:54.024] <TB3> INFO: start marker: 0
[15:45:54.024] <TB3> INFO: stop marker: 0
[15:45:54.024] <TB3> INFO: overflow: 0
[15:45:54.024] <TB3> INFO: invalid 5bit words: 0
[15:45:54.024] <TB3> INFO: invalid XOR eye diagram: 0
[15:45:54.024] <TB3> INFO: frame (failed synchr.): 0
[15:45:54.024] <TB3> INFO: idle data (no TBM trl): 0
[15:45:54.024] <TB3> INFO: no data (only TBM hdr): 0
[15:45:54.024] <TB3> INFO: TBM errors: 0
[15:45:54.024] <TB3> INFO: flawed TBM headers: 0
[15:45:54.024] <TB3> INFO: flawed TBM trailers: 0
[15:45:54.024] <TB3> INFO: event ID mismatches: 0
[15:45:54.024] <TB3> INFO: ROC errors: 0
[15:45:54.024] <TB3> INFO: missing ROC header(s): 0
[15:45:54.024] <TB3> INFO: misplaced readback start: 0
[15:45:54.024] <TB3> INFO: Pixel decoding errors: 0
[15:45:54.024] <TB3> INFO: pixel data incomplete: 0
[15:45:54.024] <TB3> INFO: pixel address: 0
[15:45:54.024] <TB3> INFO: pulse height fill bit: 0
[15:45:54.024] <TB3> INFO: buffer corruption: 0
[15:45:54.024] <TB3> INFO: enter test to run
[15:45:54.024] <TB3> INFO: test: exit no parameter change
[15:45:54.132] <TB3> QUIET: Connection to board 126 closed.
[15:45:54.133] <TB3> INFO: pXar: this is the end, my friend