[15:55:58.554] <TB3> INFO: *** Welcome to pxar ***
[15:55:58.554] <TB3> INFO: *** Today: 2016/11/07
[15:55:58.562] <TB3> INFO: *** Version: c8ba-dirty
[15:55:58.562] <TB3> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C15.dat
[15:55:58.563] <TB3> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[15:55:58.563] <TB3> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//defaultMaskFile.dat
[15:55:58.563] <TB3> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters_C15.dat
[15:55:58.630] <TB3> INFO: clk: 4
[15:55:58.630] <TB3> INFO: ctr: 4
[15:55:58.630] <TB3> INFO: sda: 19
[15:55:58.630] <TB3> INFO: tin: 9
[15:55:58.630] <TB3> INFO: level: 15
[15:55:58.630] <TB3> INFO: triggerdelay: 0
[15:55:58.630] <TB3> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[15:55:58.630] <TB3> INFO: Log level: INFO
[15:55:58.638] <TB3> INFO: Found DTB DTB_WWVASW
[15:55:58.648] <TB3> QUIET: Connection to board DTB_WWVASW opened.
[15:55:58.650] <TB3> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 126
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWVASW
MAC address: 40D85511807E
Hostname: pixelDTB126
Comment:
------------------------------------------------------
[15:55:58.652] <TB3> INFO: RPC call hashes of host and DTB match: 486171790
[15:56:00.144] <TB3> INFO: DUT info:
[15:56:00.144] <TB3> INFO: The DUT currently contains the following objects:
[15:56:00.144] <TB3> INFO: 4 TBM Cores tbm10c (4 ON)
[15:56:00.145] <TB3> INFO: TBM Core alpha (0): 7 registers set
[15:56:00.145] <TB3> INFO: TBM Core beta (1): 7 registers set
[15:56:00.145] <TB3> INFO: TBM Core alpha (2): 7 registers set
[15:56:00.145] <TB3> INFO: TBM Core beta (3): 7 registers set
[15:56:00.145] <TB3> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[15:56:00.145] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.145] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.145] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.145] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.145] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.145] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.145] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.145] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.145] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.145] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.145] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.145] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.146] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.146] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.146] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.146] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[15:56:00.547] <TB3> INFO: enter 'restricted' command line mode
[15:56:00.547] <TB3> INFO: enter test to run
[15:56:00.547] <TB3> INFO: test: pretest no parameter change
[15:56:00.547] <TB3> INFO: running: pretest
[15:56:00.554] <TB3> INFO: ######################################################################
[15:56:00.554] <TB3> INFO: PixTestPretest::doTest()
[15:56:00.554] <TB3> INFO: ######################################################################
[15:56:00.555] <TB3> INFO: ----------------------------------------------------------------------
[15:56:00.556] <TB3> INFO: PixTestPretest::programROC()
[15:56:00.556] <TB3> INFO: ----------------------------------------------------------------------
[15:56:18.570] <TB3> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[15:56:18.570] <TB3> INFO: IA differences per ROC: 16.9 19.3 16.1 16.9 15.3 18.5 20.9 18.5 18.5 17.7 20.9 17.7 18.5 18.5 19.3 17.7
[15:56:18.638] <TB3> INFO: ----------------------------------------------------------------------
[15:56:18.638] <TB3> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[15:56:18.638] <TB3> INFO: ----------------------------------------------------------------------
[15:56:39.935] <TB3> INFO: PixTestPretest::setVana() done, Module Ia 389.9 mA = 24.3688 mA/ROC
[15:56:39.935] <TB3> INFO: i(loss) [mA/ROC]: 20.1 20.1 20.1 20.1 20.1 21.7 20.1 20.9 20.1 20.9 19.3 20.1 20.1 19.3 19.3 20.1
[15:56:39.965] <TB3> INFO: ----------------------------------------------------------------------
[15:56:39.965] <TB3> INFO: PixTestPretest::findTiming()
[15:56:39.965] <TB3> INFO: ----------------------------------------------------------------------
[15:56:39.965] <TB3> INFO: PixTestCmd::init()

[15:57:12.301] <TB3> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[15:57:12.301] <TB3> INFO: (success/tries = 100/100), width = 3
[15:57:13.807] <TB3> INFO: ----------------------------------------------------------------------
[15:57:13.807] <TB3> INFO: PixTestPretest::findWorkingPixel()
[15:57:13.807] <TB3> INFO: ----------------------------------------------------------------------
[15:57:13.901] <TB3> INFO: Expecting 231680 events.
[15:57:23.876] <TB3> INFO: 231680 events read in total (9383ms).
[15:57:23.883] <TB3> INFO: Test took 10072ms.
[15:57:24.134] <TB3> INFO: Found working pixel in all ROCs: col/row = 12/22
[15:57:24.168] <TB3> INFO: ----------------------------------------------------------------------
[15:57:24.168] <TB3> INFO: PixTestPretest::setVthrCompCalDel()
[15:57:24.168] <TB3> INFO: ----------------------------------------------------------------------
[15:57:24.264] <TB3> INFO: Expecting 231680 events.
[15:57:34.429] <TB3> INFO: 231680 events read in total (9573ms).
[15:57:34.440] <TB3> INFO: Test took 10266ms.
[15:57:34.705] <TB3> INFO: PixTestPretest::setVthrCompCalDel() done
[15:57:34.705] <TB3> INFO: CalDel: 70 81 83 92 93 96 84 84 78 73 84 72 84 76 87 82
[15:57:34.705] <TB3> INFO: VthrComp: 53 53 51 51 51 51 52 61 51 51 51 51 53 51 51 51
[15:57:34.708] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C0.dat
[15:57:34.708] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C1.dat
[15:57:34.708] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C2.dat
[15:57:34.709] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C3.dat
[15:57:34.709] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C4.dat
[15:57:34.709] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C5.dat
[15:57:34.709] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C6.dat
[15:57:34.710] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C7.dat
[15:57:34.710] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C8.dat
[15:57:34.710] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C9.dat
[15:57:34.710] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C10.dat
[15:57:34.711] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C11.dat
[15:57:34.711] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C12.dat
[15:57:34.711] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C13.dat
[15:57:34.711] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C14.dat
[15:57:34.712] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C15.dat
[15:57:34.712] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[15:57:34.712] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[15:57:34.712] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[15:57:34.712] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[15:57:34.712] <TB3> INFO: PixTestPretest::doTest() done, duration: 94 seconds
[15:57:34.767] <TB3> INFO: enter test to run
[15:57:34.767] <TB3> INFO: test: fulltest no parameter change
[15:57:34.767] <TB3> INFO: running: fulltest
[15:57:34.767] <TB3> INFO: ######################################################################
[15:57:34.767] <TB3> INFO: PixTestFullTest::doTest()
[15:57:34.767] <TB3> INFO: ######################################################################
[15:57:34.768] <TB3> INFO: ######################################################################
[15:57:34.769] <TB3> INFO: PixTestAlive::doTest()
[15:57:34.769] <TB3> INFO: ######################################################################
[15:57:34.770] <TB3> INFO: ----------------------------------------------------------------------
[15:57:34.770] <TB3> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:57:34.770] <TB3> INFO: ----------------------------------------------------------------------
[15:57:35.013] <TB3> INFO: Expecting 41600 events.
[15:57:38.629] <TB3> INFO: 41600 events read in total (3024ms).
[15:57:38.630] <TB3> INFO: Test took 3859ms.
[15:57:38.864] <TB3> INFO: PixTestAlive::aliveTest() done
[15:57:38.864] <TB3> INFO: number of dead pixels (per ROC): 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 2
[15:57:38.866] <TB3> INFO: ----------------------------------------------------------------------
[15:57:38.866] <TB3> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:57:38.866] <TB3> INFO: ----------------------------------------------------------------------
[15:57:39.111] <TB3> INFO: Expecting 41600 events.
[15:57:42.104] <TB3> INFO: 41600 events read in total (2401ms).
[15:57:42.104] <TB3> INFO: Test took 3237ms.
[15:57:42.104] <TB3> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[15:57:42.345] <TB3> INFO: PixTestAlive::maskTest() done
[15:57:42.346] <TB3> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:57:42.347] <TB3> INFO: ----------------------------------------------------------------------
[15:57:42.347] <TB3> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:57:42.347] <TB3> INFO: ----------------------------------------------------------------------
[15:57:42.589] <TB3> INFO: Expecting 41600 events.
[15:57:46.128] <TB3> INFO: 41600 events read in total (2947ms).
[15:57:46.129] <TB3> INFO: Test took 3780ms.
[15:57:46.366] <TB3> INFO: PixTestAlive::addressDecodingTest() done
[15:57:46.366] <TB3> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:57:46.366] <TB3> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[15:57:46.366] <TB3> INFO: Decoding statistics:
[15:57:46.366] <TB3> INFO: General information:
[15:57:46.366] <TB3> INFO: 16bit words read: 0
[15:57:46.366] <TB3> INFO: valid events total: 0
[15:57:46.366] <TB3> INFO: empty events: 0
[15:57:46.366] <TB3> INFO: valid events with pixels: 0
[15:57:46.366] <TB3> INFO: valid pixel hits: 0
[15:57:46.366] <TB3> INFO: Event errors: 0
[15:57:46.366] <TB3> INFO: start marker: 0
[15:57:46.366] <TB3> INFO: stop marker: 0
[15:57:46.366] <TB3> INFO: overflow: 0
[15:57:46.366] <TB3> INFO: invalid 5bit words: 0
[15:57:46.366] <TB3> INFO: invalid XOR eye diagram: 0
[15:57:46.366] <TB3> INFO: frame (failed synchr.): 0
[15:57:46.367] <TB3> INFO: idle data (no TBM trl): 0
[15:57:46.367] <TB3> INFO: no data (only TBM hdr): 0
[15:57:46.367] <TB3> INFO: TBM errors: 0
[15:57:46.367] <TB3> INFO: flawed TBM headers: 0
[15:57:46.367] <TB3> INFO: flawed TBM trailers: 0
[15:57:46.367] <TB3> INFO: event ID mismatches: 0
[15:57:46.367] <TB3> INFO: ROC errors: 0
[15:57:46.367] <TB3> INFO: missing ROC header(s): 0
[15:57:46.367] <TB3> INFO: misplaced readback start: 0
[15:57:46.367] <TB3> INFO: Pixel decoding errors: 0
[15:57:46.367] <TB3> INFO: pixel data incomplete: 0
[15:57:46.367] <TB3> INFO: pixel address: 0
[15:57:46.367] <TB3> INFO: pulse height fill bit: 0
[15:57:46.367] <TB3> INFO: buffer corruption: 0
[15:57:46.375] <TB3> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[15:57:46.376] <TB3> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[15:57:46.376] <TB3> INFO: ######################################################################
[15:57:46.376] <TB3> INFO: PixTestReadback::doTest()
[15:57:46.376] <TB3> INFO: ######################################################################
[15:57:46.376] <TB3> INFO: ----------------------------------------------------------------------
[15:57:46.376] <TB3> INFO: PixTestReadback::CalibrateVd()
[15:57:46.376] <TB3> INFO: ----------------------------------------------------------------------
[15:57:56.365] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat
[15:57:56.365] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C1.dat
[15:57:56.365] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C2.dat
[15:57:56.365] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C3.dat
[15:57:56.365] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C4.dat
[15:57:56.365] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C5.dat
[15:57:56.365] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C6.dat
[15:57:56.365] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C7.dat
[15:57:56.365] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C8.dat
[15:57:56.365] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C9.dat
[15:57:56.365] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C10.dat
[15:57:56.366] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C11.dat
[15:57:56.366] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C12.dat
[15:57:56.366] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C13.dat
[15:57:56.366] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C14.dat
[15:57:56.366] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[15:57:56.401] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[15:57:56.401] <TB3> INFO: ----------------------------------------------------------------------
[15:57:56.401] <TB3> INFO: PixTestReadback::CalibrateVa()
[15:57:56.401] <TB3> INFO: ----------------------------------------------------------------------
[15:58:06.336] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C1.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C2.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C3.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C4.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C5.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C6.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C7.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C8.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C9.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C10.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C11.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C12.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C13.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C14.dat
[15:58:06.337] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[15:58:06.371] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[15:58:06.371] <TB3> INFO: ----------------------------------------------------------------------
[15:58:06.371] <TB3> INFO: PixTestReadback::readbackVbg()
[15:58:06.371] <TB3> INFO: ----------------------------------------------------------------------
[15:58:14.044] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[15:58:14.044] <TB3> INFO: ----------------------------------------------------------------------
[15:58:14.044] <TB3> INFO: PixTestReadback::getCalibratedVbg()
[15:58:14.044] <TB3> INFO: ----------------------------------------------------------------------
[15:58:14.044] <TB3> INFO: Vbg will be calibrated using Vd calibration
[15:58:14.044] <TB3> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 159.1calibrated Vbg = 1.20834 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 155.4calibrated Vbg = 1.22346 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 159.2calibrated Vbg = 1.20983 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 151.9calibrated Vbg = 1.20648 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 147.7calibrated Vbg = 1.20843 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 156calibrated Vbg = 1.21039 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 160.5calibrated Vbg = 1.21176 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 160calibrated Vbg = 1.21405 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 155.8calibrated Vbg = 1.20958 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 161.4calibrated Vbg = 1.2048 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 153.9calibrated Vbg = 1.20658 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 158.5calibrated Vbg = 1.19784 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 154.7calibrated Vbg = 1.21077 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 154.8calibrated Vbg = 1.214 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 152.5calibrated Vbg = 1.21548 :::*/*/*/*/
[15:58:14.045] <TB3> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 160.8calibrated Vbg = 1.21386 :::*/*/*/*/
[15:58:14.048] <TB3> INFO: ----------------------------------------------------------------------
[15:58:14.048] <TB3> INFO: PixTestReadback::CalibrateIa()
[15:58:14.048] <TB3> INFO: ----------------------------------------------------------------------
[16:00:54.847] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat
[16:00:54.847] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C1.dat
[16:00:54.847] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C2.dat
[16:00:54.847] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C3.dat
[16:00:54.847] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C4.dat
[16:00:54.847] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C5.dat
[16:00:54.847] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C6.dat
[16:00:54.847] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C7.dat
[16:00:54.847] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C8.dat
[16:00:54.847] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C9.dat
[16:00:54.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C10.dat
[16:00:54.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C11.dat
[16:00:54.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C12.dat
[16:00:54.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C13.dat
[16:00:54.849] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C14.dat
[16:00:54.849] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[16:00:54.879] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[16:00:54.881] <TB3> INFO: PixTestReadback::doTest() done
[16:00:54.881] <TB3> INFO: Decoding statistics:
[16:00:54.881] <TB3> INFO: General information:
[16:00:54.881] <TB3> INFO: 16bit words read: 1536
[16:00:54.881] <TB3> INFO: valid events total: 256
[16:00:54.881] <TB3> INFO: empty events: 256
[16:00:54.881] <TB3> INFO: valid events with pixels: 0
[16:00:54.882] <TB3> INFO: valid pixel hits: 0
[16:00:54.882] <TB3> INFO: Event errors: 0
[16:00:54.882] <TB3> INFO: start marker: 0
[16:00:54.882] <TB3> INFO: stop marker: 0
[16:00:54.882] <TB3> INFO: overflow: 0
[16:00:54.882] <TB3> INFO: invalid 5bit words: 0
[16:00:54.882] <TB3> INFO: invalid XOR eye diagram: 0
[16:00:54.882] <TB3> INFO: frame (failed synchr.): 0
[16:00:54.882] <TB3> INFO: idle data (no TBM trl): 0
[16:00:54.882] <TB3> INFO: no data (only TBM hdr): 0
[16:00:54.882] <TB3> INFO: TBM errors: 0
[16:00:54.882] <TB3> INFO: flawed TBM headers: 0
[16:00:54.882] <TB3> INFO: flawed TBM trailers: 0
[16:00:54.882] <TB3> INFO: event ID mismatches: 0
[16:00:54.882] <TB3> INFO: ROC errors: 0
[16:00:54.882] <TB3> INFO: missing ROC header(s): 0
[16:00:54.882] <TB3> INFO: misplaced readback start: 0
[16:00:54.882] <TB3> INFO: Pixel decoding errors: 0
[16:00:54.882] <TB3> INFO: pixel data incomplete: 0
[16:00:54.882] <TB3> INFO: pixel address: 0
[16:00:54.882] <TB3> INFO: pulse height fill bit: 0
[16:00:54.882] <TB3> INFO: buffer corruption: 0
[16:00:54.934] <TB3> INFO: ######################################################################
[16:00:54.934] <TB3> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[16:00:54.934] <TB3> INFO: ######################################################################
[16:00:54.936] <TB3> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[16:00:55.043] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[16:00:55.043] <TB3> INFO: run 1 of 1
[16:00:55.289] <TB3> INFO: Expecting 3120000 events.
[16:01:26.514] <TB3> INFO: 670830 events read in total (30633ms).




















[16:01:56.686] <TB3> INFO: 1336530 events read in total (60805ms).











[16:02:27.230] <TB3> INFO: 1997270 events read in total (91349ms).











[16:02:57.541] <TB3> INFO: 2661370 events read in total (121660ms).











[16:03:19.187] <TB3> INFO: 3120000 events read in total (143306ms).
[16:03:19.280] <TB3> INFO: Test took 144238ms.
[16:03:43.921] <TB3> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 168 seconds
[16:03:43.921] <TB3> INFO: number of dead bumps (per ROC): 1 0 2 0 0 0 0 0 1 0 0 0 0 0 1 0
[16:03:43.921] <TB3> INFO: separation cut (per ROC): 105 121 104 108 102 112 107 140 129 118 135 117 121 116 95 124
[16:03:43.921] <TB3> INFO: Decoding statistics:
[16:03:43.921] <TB3> INFO: General information:
[16:03:43.921] <TB3> INFO: 16bit words read: 0
[16:03:43.921] <TB3> INFO: valid events total: 0
[16:03:43.921] <TB3> INFO: empty events: 0
[16:03:43.921] <TB3> INFO: valid events with pixels: 0
[16:03:43.921] <TB3> INFO: valid pixel hits: 0
[16:03:43.921] <TB3> INFO: Event errors: 0
[16:03:43.921] <TB3> INFO: start marker: 0
[16:03:43.921] <TB3> INFO: stop marker: 0
[16:03:43.922] <TB3> INFO: overflow: 0
[16:03:43.922] <TB3> INFO: invalid 5bit words: 0
[16:03:43.922] <TB3> INFO: invalid XOR eye diagram: 0
[16:03:43.922] <TB3> INFO: frame (failed synchr.): 0
[16:03:43.922] <TB3> INFO: idle data (no TBM trl): 0
[16:03:43.922] <TB3> INFO: no data (only TBM hdr): 0
[16:03:43.922] <TB3> INFO: TBM errors: 0
[16:03:43.922] <TB3> INFO: flawed TBM headers: 0
[16:03:43.922] <TB3> INFO: flawed TBM trailers: 0
[16:03:43.922] <TB3> INFO: event ID mismatches: 0
[16:03:43.922] <TB3> INFO: ROC errors: 0
[16:03:43.922] <TB3> INFO: missing ROC header(s): 0
[16:03:43.922] <TB3> INFO: misplaced readback start: 0
[16:03:43.922] <TB3> INFO: Pixel decoding errors: 0
[16:03:43.922] <TB3> INFO: pixel data incomplete: 0
[16:03:43.922] <TB3> INFO: pixel address: 0
[16:03:43.922] <TB3> INFO: pulse height fill bit: 0
[16:03:43.922] <TB3> INFO: buffer corruption: 0
[16:03:43.977] <TB3> INFO: ######################################################################
[16:03:43.977] <TB3> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:03:43.977] <TB3> INFO: ######################################################################
[16:03:43.977] <TB3> INFO: ----------------------------------------------------------------------
[16:03:43.977] <TB3> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:03:43.977] <TB3> INFO: ----------------------------------------------------------------------
[16:03:43.977] <TB3> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[16:03:43.992] <TB3> INFO: dacScan split into 1 runs with ntrig = 50
[16:03:43.992] <TB3> INFO: run 1 of 1
[16:03:44.267] <TB3> INFO: Expecting 36608000 events.
[16:04:08.110] <TB3> INFO: 707600 events read in total (23251ms).
[16:04:31.259] <TB3> INFO: 1396300 events read in total (46400ms).
[16:04:54.474] <TB3> INFO: 2086350 events read in total (69615ms).
[16:05:17.663] <TB3> INFO: 2775700 events read in total (92804ms).
[16:05:41.264] <TB3> INFO: 3461850 events read in total (116405ms).
[16:06:04.524] <TB3> INFO: 4145300 events read in total (139665ms).
[16:06:27.790] <TB3> INFO: 4832500 events read in total (162931ms).
[16:06:51.158] <TB3> INFO: 5518400 events read in total (186299ms).
[16:07:14.308] <TB3> INFO: 6207350 events read in total (209449ms).
[16:07:37.654] <TB3> INFO: 6892800 events read in total (232795ms).
[16:08:01.136] <TB3> INFO: 7577750 events read in total (256277ms).
[16:08:24.126] <TB3> INFO: 8262750 events read in total (279267ms).
[16:08:47.404] <TB3> INFO: 8947650 events read in total (302545ms).
[16:09:10.380] <TB3> INFO: 9630600 events read in total (325521ms).
[16:09:33.521] <TB3> INFO: 10312950 events read in total (348662ms).
[16:09:56.673] <TB3> INFO: 10996500 events read in total (371815ms).
[16:10:19.575] <TB3> INFO: 11678250 events read in total (394716ms).
[16:10:42.797] <TB3> INFO: 12361700 events read in total (417938ms).
[16:11:05.001] <TB3> INFO: 13043900 events read in total (441142ms).
[16:11:29.248] <TB3> INFO: 13728950 events read in total (464389ms).
[16:11:52.259] <TB3> INFO: 14411250 events read in total (487400ms).
[16:12:15.549] <TB3> INFO: 15091900 events read in total (510690ms).
[16:12:38.494] <TB3> INFO: 15774150 events read in total (533635ms).
[16:13:01.322] <TB3> INFO: 16455300 events read in total (556463ms).
[16:13:24.532] <TB3> INFO: 17136650 events read in total (579673ms).
[16:13:47.408] <TB3> INFO: 17814250 events read in total (602549ms).
[16:14:10.309] <TB3> INFO: 18490350 events read in total (625450ms).
[16:14:33.253] <TB3> INFO: 19168350 events read in total (648394ms).
[16:14:56.320] <TB3> INFO: 19846150 events read in total (671461ms).
[16:15:19.282] <TB3> INFO: 20524550 events read in total (694423ms).
[16:15:42.359] <TB3> INFO: 21201300 events read in total (717500ms).
[16:16:05.514] <TB3> INFO: 21882000 events read in total (740655ms).
[16:16:28.541] <TB3> INFO: 22558950 events read in total (763683ms).
[16:16:51.530] <TB3> INFO: 23233250 events read in total (786671ms).
[16:17:14.426] <TB3> INFO: 23906850 events read in total (809567ms).
[16:17:37.651] <TB3> INFO: 24585150 events read in total (832792ms).
[16:18:00.717] <TB3> INFO: 25263800 events read in total (855858ms).
[16:18:23.766] <TB3> INFO: 25940550 events read in total (878907ms).
[16:18:46.899] <TB3> INFO: 26619300 events read in total (902040ms).
[16:19:09.912] <TB3> INFO: 27297900 events read in total (925053ms).
[16:19:33.085] <TB3> INFO: 27975950 events read in total (948226ms).
[16:19:56.135] <TB3> INFO: 28652900 events read in total (971276ms).
[16:20:19.040] <TB3> INFO: 29326650 events read in total (994181ms).
[16:20:41.971] <TB3> INFO: 29999200 events read in total (1017112ms).
[16:21:05.239] <TB3> INFO: 30674150 events read in total (1040380ms).
[16:21:28.107] <TB3> INFO: 31345750 events read in total (1063248ms).
[16:21:51.234] <TB3> INFO: 32019850 events read in total (1086375ms).
[16:22:14.124] <TB3> INFO: 32690900 events read in total (1109265ms).
[16:22:37.163] <TB3> INFO: 33366850 events read in total (1132304ms).
[16:23:00.068] <TB3> INFO: 34042700 events read in total (1155209ms).
[16:23:23.056] <TB3> INFO: 34718650 events read in total (1178197ms).
[16:23:46.040] <TB3> INFO: 35393700 events read in total (1201181ms).
[16:24:09.411] <TB3> INFO: 36075000 events read in total (1224552ms).
[16:24:27.817] <TB3> INFO: 36608000 events read in total (1242958ms).
[16:24:27.891] <TB3> INFO: Test took 1243900ms.
[16:24:28.237] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:29.719] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:31.192] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:32.655] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:34.117] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:35.569] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:37.089] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:39.480] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:41.651] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:43.086] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:44.735] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:46.335] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:48.186] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:50.187] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:51.925] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:53.968] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:24:55.831] <TB3> INFO: PixTestScurves::scurves() done
[16:24:55.831] <TB3> INFO: Vcal mean: 124.97 128.33 125.11 127.68 130.67 122.68 126.22 137.44 127.23 127.34 130.10 132.23 130.69 117.41 114.16 126.92
[16:24:55.831] <TB3> INFO: Vcal RMS: 6.06 7.05 6.79 6.43 6.45 5.38 5.69 5.99 5.36 5.99 6.23 5.66 5.95 5.23 5.35 6.60
[16:24:55.831] <TB3> INFO: PixTestScurves::fullTest() done, duration: 1271 seconds
[16:24:55.831] <TB3> INFO: Decoding statistics:
[16:24:55.831] <TB3> INFO: General information:
[16:24:55.831] <TB3> INFO: 16bit words read: 0
[16:24:55.831] <TB3> INFO: valid events total: 0
[16:24:55.831] <TB3> INFO: empty events: 0
[16:24:55.831] <TB3> INFO: valid events with pixels: 0
[16:24:55.831] <TB3> INFO: valid pixel hits: 0
[16:24:55.831] <TB3> INFO: Event errors: 0
[16:24:55.831] <TB3> INFO: start marker: 0
[16:24:55.831] <TB3> INFO: stop marker: 0
[16:24:55.831] <TB3> INFO: overflow: 0
[16:24:55.831] <TB3> INFO: invalid 5bit words: 0
[16:24:55.831] <TB3> INFO: invalid XOR eye diagram: 0
[16:24:55.831] <TB3> INFO: frame (failed synchr.): 0
[16:24:55.831] <TB3> INFO: idle data (no TBM trl): 0
[16:24:55.831] <TB3> INFO: no data (only TBM hdr): 0
[16:24:55.831] <TB3> INFO: TBM errors: 0
[16:24:55.831] <TB3> INFO: flawed TBM headers: 0
[16:24:55.831] <TB3> INFO: flawed TBM trailers: 0
[16:24:55.831] <TB3> INFO: event ID mismatches: 0
[16:24:55.831] <TB3> INFO: ROC errors: 0
[16:24:55.831] <TB3> INFO: missing ROC header(s): 0
[16:24:55.831] <TB3> INFO: misplaced readback start: 0
[16:24:55.831] <TB3> INFO: Pixel decoding errors: 0
[16:24:55.831] <TB3> INFO: pixel data incomplete: 0
[16:24:55.831] <TB3> INFO: pixel address: 0
[16:24:55.831] <TB3> INFO: pulse height fill bit: 0
[16:24:55.831] <TB3> INFO: buffer corruption: 0
[16:24:55.904] <TB3> INFO: ######################################################################
[16:24:55.904] <TB3> INFO: PixTestTrim::doTest()
[16:24:55.904] <TB3> INFO: ######################################################################
[16:24:55.905] <TB3> INFO: ----------------------------------------------------------------------
[16:24:55.905] <TB3> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[16:24:55.905] <TB3> INFO: ----------------------------------------------------------------------
[16:24:55.947] <TB3> INFO: ---> VthrComp thr map (minimal VthrComp)
[16:24:55.947] <TB3> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:24:55.960] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:24:55.960] <TB3> INFO: run 1 of 1
[16:24:56.196] <TB3> INFO: Expecting 5025280 events.
[16:25:27.309] <TB3> INFO: 834928 events read in total (30514ms).
[16:25:57.795] <TB3> INFO: 1666728 events read in total (61000ms).
[16:26:28.129] <TB3> INFO: 2495776 events read in total (91334ms).
[16:26:58.284] <TB3> INFO: 3320488 events read in total (121489ms).
[16:27:28.468] <TB3> INFO: 4142144 events read in total (151674ms).
[16:27:59.022] <TB3> INFO: 4962048 events read in total (182227ms).
[16:28:01.650] <TB3> INFO: 5025280 events read in total (184855ms).
[16:28:01.715] <TB3> INFO: Test took 185756ms.
[16:28:19.620] <TB3> INFO: ROC 0 VthrComp = 127
[16:28:19.620] <TB3> INFO: ROC 1 VthrComp = 129
[16:28:19.620] <TB3> INFO: ROC 2 VthrComp = 124
[16:28:19.620] <TB3> INFO: ROC 3 VthrComp = 126
[16:28:19.620] <TB3> INFO: ROC 4 VthrComp = 124
[16:28:19.620] <TB3> INFO: ROC 5 VthrComp = 129
[16:28:19.621] <TB3> INFO: ROC 6 VthrComp = 129
[16:28:19.621] <TB3> INFO: ROC 7 VthrComp = 140
[16:28:19.621] <TB3> INFO: ROC 8 VthrComp = 130
[16:28:19.621] <TB3> INFO: ROC 9 VthrComp = 130
[16:28:19.621] <TB3> INFO: ROC 10 VthrComp = 130
[16:28:19.621] <TB3> INFO: ROC 11 VthrComp = 132
[16:28:19.621] <TB3> INFO: ROC 12 VthrComp = 134
[16:28:19.621] <TB3> INFO: ROC 13 VthrComp = 118
[16:28:19.621] <TB3> INFO: ROC 14 VthrComp = 112
[16:28:19.621] <TB3> INFO: ROC 15 VthrComp = 127
[16:28:19.860] <TB3> INFO: Expecting 41600 events.
[16:28:23.336] <TB3> INFO: 41600 events read in total (2884ms).
[16:28:23.336] <TB3> INFO: Test took 3713ms.
[16:28:23.345] <TB3> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[16:28:23.345] <TB3> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:28:23.356] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:28:23.356] <TB3> INFO: run 1 of 1
[16:28:23.635] <TB3> INFO: Expecting 5025280 events.
[16:28:50.097] <TB3> INFO: 590424 events read in total (25870ms).
[16:29:15.887] <TB3> INFO: 1180248 events read in total (51660ms).
[16:29:41.752] <TB3> INFO: 1770632 events read in total (77525ms).
[16:30:07.645] <TB3> INFO: 2360832 events read in total (103418ms).
[16:30:33.787] <TB3> INFO: 2948768 events read in total (129560ms).
[16:30:59.713] <TB3> INFO: 3535208 events read in total (155486ms).
[16:31:25.598] <TB3> INFO: 4121576 events read in total (181371ms).
[16:31:51.420] <TB3> INFO: 4707064 events read in total (207193ms).
[16:32:05.569] <TB3> INFO: 5025280 events read in total (221342ms).
[16:32:05.652] <TB3> INFO: Test took 222296ms.
[16:32:31.557] <TB3> INFO: roc 0 with ID = 0 has maximal Vcal 60.676 for pixel 3/6 mean/min/max = 45.5989/30.3353/60.8625
[16:32:31.557] <TB3> INFO: roc 1 with ID = 1 has maximal Vcal 63.857 for pixel 0/22 mean/min/max = 47.4581/30.8574/64.0588
[16:32:31.558] <TB3> INFO: roc 2 with ID = 2 has maximal Vcal 60.7981 for pixel 49/63 mean/min/max = 46.4068/31.9981/60.8155
[16:32:31.558] <TB3> INFO: roc 3 with ID = 3 has maximal Vcal 62.5238 for pixel 1/4 mean/min/max = 47.1233/31.5879/62.6588
[16:32:31.559] <TB3> INFO: roc 4 with ID = 4 has maximal Vcal 64.1952 for pixel 36/0 mean/min/max = 48.2063/32.2047/64.2078
[16:32:31.559] <TB3> INFO: roc 5 with ID = 5 has maximal Vcal 58.0484 for pixel 14/3 mean/min/max = 45.1469/32.1643/58.1294
[16:32:31.560] <TB3> INFO: roc 6 with ID = 6 has maximal Vcal 61.4222 for pixel 18/76 mean/min/max = 46.6462/31.461/61.8314
[16:32:31.561] <TB3> INFO: roc 7 with ID = 7 has maximal Vcal 74.9457 for pixel 0/38 mean/min/max = 57.7906/40.604/74.9771
[16:32:31.561] <TB3> INFO: roc 8 with ID = 8 has maximal Vcal 60.0214 for pixel 23/16 mean/min/max = 46.1491/32.2359/60.0623
[16:32:31.562] <TB3> INFO: roc 9 with ID = 9 has maximal Vcal 62.6251 for pixel 0/15 mean/min/max = 47.3748/32.1046/62.645
[16:32:31.562] <TB3> INFO: roc 10 with ID = 10 has maximal Vcal 61.4602 for pixel 6/10 mean/min/max = 46.425/31.3855/61.4646
[16:32:31.563] <TB3> INFO: roc 11 with ID = 11 has maximal Vcal 60.8859 for pixel 23/9 mean/min/max = 46.785/32.524/61.0459
[16:32:31.563] <TB3> INFO: roc 12 with ID = 12 has maximal Vcal 59.3046 for pixel 16/70 mean/min/max = 46.0051/32.6431/59.3671
[16:32:31.564] <TB3> INFO: roc 13 with ID = 13 has maximal Vcal 58.8297 for pixel 21/2 mean/min/max = 45.6882/32.4919/58.8845
[16:32:31.564] <TB3> INFO: roc 14 with ID = 14 has maximal Vcal 60.7407 for pixel 14/79 mean/min/max = 46.7979/32.7138/60.8819
[16:32:31.565] <TB3> INFO: roc 15 with ID = 15 has maximal Vcal 60.3678 for pixel 10/3 mean/min/max = 45.7/31.0276/60.3724
[16:32:31.565] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:32:31.654] <TB3> INFO: Expecting 411648 events.
[16:32:41.221] <TB3> INFO: 411648 events read in total (8975ms).
[16:32:41.228] <TB3> INFO: Expecting 411648 events.
[16:32:50.593] <TB3> INFO: 411648 events read in total (8961ms).
[16:32:50.603] <TB3> INFO: Expecting 411648 events.
[16:32:59.001] <TB3> INFO: 411648 events read in total (8995ms).
[16:33:00.017] <TB3> INFO: Expecting 411648 events.
[16:33:09.359] <TB3> INFO: 411648 events read in total (8939ms).
[16:33:09.374] <TB3> INFO: Expecting 411648 events.
[16:33:18.621] <TB3> INFO: 411648 events read in total (8844ms).
[16:33:18.639] <TB3> INFO: Expecting 411648 events.
[16:33:28.102] <TB3> INFO: 411648 events read in total (9060ms).
[16:33:28.124] <TB3> INFO: Expecting 411648 events.
[16:33:37.526] <TB3> INFO: 411648 events read in total (8999ms).
[16:33:37.550] <TB3> INFO: Expecting 411648 events.
[16:33:46.988] <TB3> INFO: 411648 events read in total (9035ms).
[16:33:47.016] <TB3> INFO: Expecting 411648 events.
[16:33:56.330] <TB3> INFO: 411648 events read in total (8910ms).
[16:33:56.364] <TB3> INFO: Expecting 411648 events.
[16:34:05.707] <TB3> INFO: 411648 events read in total (8939ms).
[16:34:05.742] <TB3> INFO: Expecting 411648 events.
[16:34:15.045] <TB3> INFO: 411648 events read in total (8900ms).
[16:34:15.130] <TB3> INFO: Expecting 411648 events.
[16:34:24.412] <TB3> INFO: 411648 events read in total (8878ms).
[16:34:24.465] <TB3> INFO: Expecting 411648 events.
[16:34:33.832] <TB3> INFO: 411648 events read in total (8964ms).
[16:34:33.882] <TB3> INFO: Expecting 411648 events.
[16:34:43.124] <TB3> INFO: 411648 events read in total (8839ms).
[16:34:43.184] <TB3> INFO: Expecting 411648 events.
[16:34:52.374] <TB3> INFO: 411648 events read in total (8787ms).
[16:34:52.431] <TB3> INFO: Expecting 411648 events.
[16:35:01.735] <TB3> INFO: 411648 events read in total (8901ms).
[16:35:01.802] <TB3> INFO: Test took 150237ms.
[16:35:02.492] <TB3> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[16:35:02.505] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:35:02.505] <TB3> INFO: run 1 of 1
[16:35:02.742] <TB3> INFO: Expecting 5025280 events.
[16:35:28.001] <TB3> INFO: 591840 events read in total (25667ms).
[16:35:55.368] <TB3> INFO: 1181664 events read in total (52034ms).
[16:36:21.698] <TB3> INFO: 1769552 events read in total (78364ms).
[16:36:47.832] <TB3> INFO: 2356584 events read in total (104498ms).
[16:37:13.982] <TB3> INFO: 2943128 events read in total (130648ms).
[16:37:40.110] <TB3> INFO: 3531280 events read in total (156776ms).
[16:38:06.380] <TB3> INFO: 4121224 events read in total (183046ms).
[16:38:32.768] <TB3> INFO: 4708704 events read in total (209434ms).
[16:38:47.006] <TB3> INFO: 5025280 events read in total (223672ms).
[16:38:47.198] <TB3> INFO: Test took 224694ms.
[16:39:10.240] <TB3> INFO: ---> TrimStepCorr4 extremal thresholds: 2.748947 .. 144.320883
[16:39:10.486] <TB3> INFO: Expecting 208000 events.
[16:39:19.933] <TB3> INFO: 208000 events read in total (8856ms).
[16:39:19.934] <TB3> INFO: Test took 9693ms.
[16:39:19.983] <TB3> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 154 (-1/-1) hits flags = 528 (plus default)
[16:39:19.996] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:39:19.996] <TB3> INFO: run 1 of 1
[16:39:20.274] <TB3> INFO: Expecting 5091840 events.
[16:39:47.006] <TB3> INFO: 582608 events read in total (26140ms).
[16:40:12.275] <TB3> INFO: 1164792 events read in total (51409ms).
[16:40:38.609] <TB3> INFO: 1747280 events read in total (77743ms).
[16:41:04.169] <TB3> INFO: 2330304 events read in total (103304ms).
[16:41:30.232] <TB3> INFO: 2913624 events read in total (129366ms).
[16:41:56.181] <TB3> INFO: 3496976 events read in total (155315ms).
[16:42:22.242] <TB3> INFO: 4080464 events read in total (181376ms).
[16:42:48.101] <TB3> INFO: 4662960 events read in total (207235ms).
[16:43:07.563] <TB3> INFO: 5091840 events read in total (226697ms).
[16:43:07.756] <TB3> INFO: Test took 227761ms.
[16:43:32.427] <TB3> INFO: ---> TrimStepCorr2 extremal thresholds: 26.740596 .. 46.842192
[16:43:32.667] <TB3> INFO: Expecting 208000 events.
[16:43:42.702] <TB3> INFO: 208000 events read in total (9443ms).
[16:43:42.703] <TB3> INFO: Test took 10275ms.
[16:43:42.784] <TB3> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 56 (-1/-1) hits flags = 528 (plus default)
[16:43:42.799] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:43:42.799] <TB3> INFO: run 1 of 1
[16:43:43.105] <TB3> INFO: Expecting 1364480 events.
[16:44:11.640] <TB3> INFO: 661272 events read in total (27943ms).
[16:44:39.800] <TB3> INFO: 1320712 events read in total (56103ms).
[16:44:42.093] <TB3> INFO: 1364480 events read in total (58396ms).
[16:44:42.145] <TB3> INFO: Test took 59346ms.
[16:44:54.504] <TB3> INFO: ---> TrimStepCorr1a extremal thresholds: 27.202958 .. 52.558278
[16:44:54.750] <TB3> INFO: Expecting 208000 events.
[16:45:04.469] <TB3> INFO: 208000 events read in total (9128ms).
[16:45:04.470] <TB3> INFO: Test took 9965ms.
[16:45:04.519] <TB3> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 62 (-1/-1) hits flags = 528 (plus default)
[16:45:04.532] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:45:04.532] <TB3> INFO: run 1 of 1
[16:45:04.813] <TB3> INFO: Expecting 1530880 events.
[16:45:32.850] <TB3> INFO: 637552 events read in total (27445ms).
[16:46:00.401] <TB3> INFO: 1274416 events read in total (54996ms).
[16:46:11.747] <TB3> INFO: 1530880 events read in total (66343ms).
[16:46:11.783] <TB3> INFO: Test took 67250ms.
[16:46:27.194] <TB3> INFO: ---> TrimStepCorr1b extremal thresholds: 25.589187 .. 53.745169
[16:46:27.453] <TB3> INFO: Expecting 208000 events.
[16:46:37.174] <TB3> INFO: 208000 events read in total (9130ms).
[16:46:37.175] <TB3> INFO: Test took 9980ms.
[16:46:37.222] <TB3> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 63 (-1/-1) hits flags = 528 (plus default)
[16:46:37.236] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:46:37.236] <TB3> INFO: run 1 of 1
[16:46:37.514] <TB3> INFO: Expecting 1630720 events.
[16:47:05.434] <TB3> INFO: 641184 events read in total (27328ms).
[16:47:33.368] <TB3> INFO: 1282200 events read in total (55262ms).
[16:47:48.188] <TB3> INFO: 1630720 events read in total (70083ms).
[16:47:48.226] <TB3> INFO: Test took 70991ms.
[16:48:02.992] <TB3> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[16:48:02.992] <TB3> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[16:48:03.005] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:48:03.005] <TB3> INFO: run 1 of 1
[16:48:03.251] <TB3> INFO: Expecting 1364480 events.
[16:48:32.179] <TB3> INFO: 668192 events read in total (28336ms).
[16:48:59.998] <TB3> INFO: 1335632 events read in total (56155ms).
[16:49:01.605] <TB3> INFO: 1364480 events read in total (57762ms).
[16:49:01.642] <TB3> INFO: Test took 58637ms.
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C0.dat
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C1.dat
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C2.dat
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C3.dat
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C4.dat
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C5.dat
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C6.dat
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C7.dat
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C8.dat
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C9.dat
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C10.dat
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C11.dat
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C12.dat
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C13.dat
[16:49:16.933] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C14.dat
[16:49:16.934] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C15.dat
[16:49:16.934] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C0.dat
[16:49:16.938] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C1.dat
[16:49:16.943] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C2.dat
[16:49:16.948] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C3.dat
[16:49:16.952] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C4.dat
[16:49:16.957] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C5.dat
[16:49:16.963] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C6.dat
[16:49:16.970] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C7.dat
[16:49:16.977] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C8.dat
[16:49:16.983] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C9.dat
[16:49:16.989] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C10.dat
[16:49:16.996] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C11.dat
[16:49:16.002] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C12.dat
[16:49:17.008] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C13.dat
[16:49:17.014] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C14.dat
[16:49:17.020] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C15.dat
[16:49:17.026] <TB3> INFO: PixTestTrim::trimTest() done
[16:49:17.026] <TB3> INFO: vtrim: 137 123 129 130 148 129 138 184 114 140 130 136 126 118 114 124
[16:49:17.026] <TB3> INFO: vthrcomp: 127 129 124 126 124 129 129 140 130 130 130 132 134 118 112 127
[16:49:17.026] <TB3> INFO: vcal mean: 34.93 35.03 35.33 35.18 35.77 34.97 35.06 35.00 34.98 35.07 34.99 35.24 35.08 34.97 35.01 34.96
[16:49:17.026] <TB3> INFO: vcal RMS: 1.15 1.05 1.57 1.29 2.03 0.96 1.18 1.17 1.10 1.10 1.27 1.35 1.19 1.04 1.00 1.08
[16:49:17.026] <TB3> INFO: bits mean: 10.02 8.81 9.89 9.51 10.19 9.44 9.52 6.18 9.62 9.13 9.66 9.54 9.59 9.58 8.74 9.54
[16:49:17.026] <TB3> INFO: bits RMS: 2.70 2.96 2.60 2.72 2.37 2.84 2.73 2.22 2.66 2.82 2.67 2.68 2.60 2.69 2.93 2.88
[16:49:17.034] <TB3> INFO: ----------------------------------------------------------------------
[16:49:17.034] <TB3> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[16:49:17.034] <TB3> INFO: ----------------------------------------------------------------------
[16:49:17.036] <TB3> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[16:49:17.050] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[16:49:17.050] <TB3> INFO: run 1 of 1
[16:49:17.289] <TB3> INFO: Expecting 4160000 events.
[16:49:50.446] <TB3> INFO: 781990 events read in total (32565ms).
[16:50:22.967] <TB3> INFO: 1554710 events read in total (65086ms).
[16:50:55.411] <TB3> INFO: 2321160 events read in total (97530ms).
[16:51:27.770] <TB3> INFO: 3084970 events read in total (129889ms).
[16:52:00.556] <TB3> INFO: 3844575 events read in total (162675ms).
[16:52:14.140] <TB3> INFO: 4160000 events read in total (176259ms).
[16:52:14.210] <TB3> INFO: Test took 177161ms.
[16:52:37.555] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[16:52:37.568] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[16:52:37.568] <TB3> INFO: run 1 of 1
[16:52:37.804] <TB3> INFO: Expecting 5324800 events.
[16:53:09.123] <TB3> INFO: 691320 events read in total (30727ms).
[16:53:39.421] <TB3> INFO: 1378705 events read in total (61025ms).
[16:54:09.770] <TB3> INFO: 2063770 events read in total (91374ms).
[16:54:40.147] <TB3> INFO: 2746200 events read in total (121751ms).
[16:55:10.596] <TB3> INFO: 3427015 events read in total (152200ms).
[16:55:41.702] <TB3> INFO: 4108575 events read in total (183306ms).
[16:56:11.457] <TB3> INFO: 4786375 events read in total (213061ms).
[16:56:35.857] <TB3> INFO: 5324800 events read in total (237461ms).
[16:56:35.964] <TB3> INFO: Test took 238396ms.
[16:57:07.662] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 252 (-1/-1) hits flags = 528 (plus default)
[16:57:07.675] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[16:57:07.675] <TB3> INFO: run 1 of 1
[16:57:07.911] <TB3> INFO: Expecting 5262400 events.
[16:57:39.720] <TB3> INFO: 694290 events read in total (31217ms).
[16:58:10.623] <TB3> INFO: 1384555 events read in total (62120ms).
[16:58:41.550] <TB3> INFO: 2072380 events read in total (93047ms).
[16:59:12.649] <TB3> INFO: 2757380 events read in total (124146ms).
[16:59:43.031] <TB3> INFO: 3440655 events read in total (154528ms).
[17:00:14.507] <TB3> INFO: 4125040 events read in total (186004ms).
[17:00:45.414] <TB3> INFO: 4805440 events read in total (216911ms).
[17:01:06.008] <TB3> INFO: 5262400 events read in total (237505ms).
[17:01:06.171] <TB3> INFO: Test took 238496ms.
[17:01:37.067] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 248 (-1/-1) hits flags = 528 (plus default)
[17:01:37.080] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[17:01:37.080] <TB3> INFO: run 1 of 1
[17:01:37.319] <TB3> INFO: Expecting 5179200 events.
[17:02:09.163] <TB3> INFO: 698205 events read in total (31252ms).
[17:02:39.875] <TB3> INFO: 1391735 events read in total (61964ms).
[17:03:10.775] <TB3> INFO: 2083155 events read in total (92864ms).
[17:03:42.170] <TB3> INFO: 2771320 events read in total (124259ms).
[17:04:12.473] <TB3> INFO: 3458165 events read in total (154562ms).
[17:04:42.906] <TB3> INFO: 4145505 events read in total (184995ms).
[17:05:13.391] <TB3> INFO: 4829625 events read in total (215480ms).
[17:05:28.891] <TB3> INFO: 5179200 events read in total (230980ms).
[17:05:29.015] <TB3> INFO: Test took 231935ms.
[17:06:00.577] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 251 (-1/-1) hits flags = 528 (plus default)
[17:06:00.591] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[17:06:00.591] <TB3> INFO: run 1 of 1
[17:06:00.879] <TB3> INFO: Expecting 5241600 events.
[17:06:31.627] <TB3> INFO: 695930 events read in total (30156ms).
[17:07:01.801] <TB3> INFO: 1387255 events read in total (60330ms).
[17:07:32.833] <TB3> INFO: 2076680 events read in total (91362ms).
[17:08:03.910] <TB3> INFO: 2763175 events read in total (122439ms).
[17:08:34.778] <TB3> INFO: 3448095 events read in total (153307ms).
[17:09:06.136] <TB3> INFO: 4133615 events read in total (184665ms).
[17:09:36.714] <TB3> INFO: 4815155 events read in total (215243ms).
[17:09:55.787] <TB3> INFO: 5241600 events read in total (234316ms).
[17:09:55.892] <TB3> INFO: Test took 235300ms.
[17:10:24.807] <TB3> INFO: PixTestTrim::trimBitTest() done
[17:10:24.808] <TB3> INFO: PixTestTrim::doTest() done, duration: 2728 seconds
[17:10:24.808] <TB3> INFO: Decoding statistics:
[17:10:24.808] <TB3> INFO: General information:
[17:10:24.808] <TB3> INFO: 16bit words read: 0
[17:10:24.808] <TB3> INFO: valid events total: 0
[17:10:24.808] <TB3> INFO: empty events: 0
[17:10:24.808] <TB3> INFO: valid events with pixels: 0
[17:10:24.808] <TB3> INFO: valid pixel hits: 0
[17:10:24.808] <TB3> INFO: Event errors: 0
[17:10:24.808] <TB3> INFO: start marker: 0
[17:10:24.808] <TB3> INFO: stop marker: 0
[17:10:24.808] <TB3> INFO: overflow: 0
[17:10:24.808] <TB3> INFO: invalid 5bit words: 0
[17:10:24.808] <TB3> INFO: invalid XOR eye diagram: 0
[17:10:24.808] <TB3> INFO: frame (failed synchr.): 0
[17:10:24.808] <TB3> INFO: idle data (no TBM trl): 0
[17:10:24.808] <TB3> INFO: no data (only TBM hdr): 0
[17:10:24.808] <TB3> INFO: TBM errors: 0
[17:10:24.808] <TB3> INFO: flawed TBM headers: 0
[17:10:24.808] <TB3> INFO: flawed TBM trailers: 0
[17:10:24.808] <TB3> INFO: event ID mismatches: 0
[17:10:24.808] <TB3> INFO: ROC errors: 0
[17:10:24.808] <TB3> INFO: missing ROC header(s): 0
[17:10:24.808] <TB3> INFO: misplaced readback start: 0
[17:10:24.808] <TB3> INFO: Pixel decoding errors: 0
[17:10:24.808] <TB3> INFO: pixel data incomplete: 0
[17:10:24.809] <TB3> INFO: pixel address: 0
[17:10:24.809] <TB3> INFO: pulse height fill bit: 0
[17:10:24.809] <TB3> INFO: buffer corruption: 0
[17:10:25.422] <TB3> INFO: ######################################################################
[17:10:25.422] <TB3> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[17:10:25.422] <TB3> INFO: ######################################################################
[17:10:25.660] <TB3> INFO: Expecting 41600 events.
[17:10:29.198] <TB3> INFO: 41600 events read in total (2946ms).
[17:10:29.199] <TB3> INFO: Test took 3776ms.
[17:10:29.645] <TB3> INFO: Expecting 41600 events.
[17:10:33.198] <TB3> INFO: 41600 events read in total (2961ms).
[17:10:33.199] <TB3> INFO: Test took 3796ms.
[17:10:33.488] <TB3> INFO: Expecting 41600 events.
[17:10:37.130] <TB3> INFO: 41600 events read in total (3050ms).
[17:10:37.131] <TB3> INFO: Test took 3908ms.
[17:10:37.420] <TB3> INFO: Expecting 41600 events.
[17:10:40.932] <TB3> INFO: 41600 events read in total (2920ms).
[17:10:40.933] <TB3> INFO: Test took 3778ms.
[17:10:41.234] <TB3> INFO: Expecting 41600 events.
[17:10:44.813] <TB3> INFO: 41600 events read in total (2988ms).
[17:10:44.814] <TB3> INFO: Test took 3857ms.
[17:10:45.103] <TB3> INFO: Expecting 41600 events.
[17:10:48.680] <TB3> INFO: 41600 events read in total (2985ms).
[17:10:48.681] <TB3> INFO: Test took 3843ms.
[17:10:48.970] <TB3> INFO: Expecting 41600 events.
[17:10:52.517] <TB3> INFO: 41600 events read in total (2955ms).
[17:10:52.518] <TB3> INFO: Test took 3813ms.
[17:10:52.807] <TB3> INFO: Expecting 41600 events.
[17:10:56.398] <TB3> INFO: 41600 events read in total (2999ms).
[17:10:56.399] <TB3> INFO: Test took 3857ms.
[17:10:56.703] <TB3> INFO: Expecting 41600 events.
[17:11:00.279] <TB3> INFO: 41600 events read in total (2984ms).
[17:11:00.280] <TB3> INFO: Test took 3854ms.
[17:11:00.579] <TB3> INFO: Expecting 41600 events.
[17:11:04.151] <TB3> INFO: 41600 events read in total (2980ms).
[17:11:04.152] <TB3> INFO: Test took 3846ms.
[17:11:04.442] <TB3> INFO: Expecting 41600 events.
[17:11:08.024] <TB3> INFO: 41600 events read in total (2991ms).
[17:11:08.025] <TB3> INFO: Test took 3849ms.
[17:11:08.318] <TB3> INFO: Expecting 41600 events.
[17:11:11.842] <TB3> INFO: 41600 events read in total (2933ms).
[17:11:11.843] <TB3> INFO: Test took 3793ms.
[17:11:12.132] <TB3> INFO: Expecting 41600 events.
[17:11:15.697] <TB3> INFO: 41600 events read in total (2973ms).
[17:11:15.698] <TB3> INFO: Test took 3831ms.
[17:11:15.990] <TB3> INFO: Expecting 41600 events.
[17:11:19.510] <TB3> INFO: 41600 events read in total (2928ms).
[17:11:19.511] <TB3> INFO: Test took 3786ms.
[17:11:19.802] <TB3> INFO: Expecting 41600 events.
[17:11:23.301] <TB3> INFO: 41600 events read in total (2908ms).
[17:11:23.301] <TB3> INFO: Test took 3765ms.
[17:11:23.591] <TB3> INFO: Expecting 41600 events.
[17:11:27.081] <TB3> INFO: 41600 events read in total (2898ms).
[17:11:27.082] <TB3> INFO: Test took 3756ms.
[17:11:27.371] <TB3> INFO: Expecting 41600 events.
[17:11:31.011] <TB3> INFO: 41600 events read in total (3048ms).
[17:11:31.011] <TB3> INFO: Test took 3905ms.
[17:11:31.301] <TB3> INFO: Expecting 41600 events.
[17:11:34.820] <TB3> INFO: 41600 events read in total (2927ms).
[17:11:34.821] <TB3> INFO: Test took 3785ms.
[17:11:35.110] <TB3> INFO: Expecting 41600 events.
[17:11:38.632] <TB3> INFO: 41600 events read in total (2930ms).
[17:11:38.633] <TB3> INFO: Test took 3788ms.
[17:11:38.923] <TB3> INFO: Expecting 41600 events.
[17:11:42.529] <TB3> INFO: 41600 events read in total (3015ms).
[17:11:42.530] <TB3> INFO: Test took 3872ms.
[17:11:42.820] <TB3> INFO: Expecting 41600 events.
[17:11:46.554] <TB3> INFO: 41600 events read in total (3143ms).
[17:11:46.554] <TB3> INFO: Test took 3999ms.
[17:11:46.844] <TB3> INFO: Expecting 41600 events.
[17:11:50.464] <TB3> INFO: 41600 events read in total (3029ms).
[17:11:50.466] <TB3> INFO: Test took 3887ms.
[17:11:50.766] <TB3> INFO: Expecting 41600 events.
[17:11:54.281] <TB3> INFO: 41600 events read in total (2924ms).
[17:11:54.282] <TB3> INFO: Test took 3791ms.
[17:11:54.601] <TB3> INFO: Expecting 41600 events.
[17:11:58.145] <TB3> INFO: 41600 events read in total (2952ms).
[17:11:58.146] <TB3> INFO: Test took 3840ms.
[17:11:58.454] <TB3> INFO: Expecting 41600 events.
[17:12:01.966] <TB3> INFO: 41600 events read in total (2920ms).
[17:12:01.967] <TB3> INFO: Test took 3796ms.
[17:12:02.257] <TB3> INFO: Expecting 41600 events.
[17:12:05.768] <TB3> INFO: 41600 events read in total (2920ms).
[17:12:05.769] <TB3> INFO: Test took 3778ms.
[17:12:06.059] <TB3> INFO: Expecting 41600 events.
[17:12:09.583] <TB3> INFO: 41600 events read in total (2932ms).
[17:12:09.584] <TB3> INFO: Test took 3790ms.
[17:12:09.873] <TB3> INFO: Expecting 41600 events.
[17:12:13.377] <TB3> INFO: 41600 events read in total (2912ms).
[17:12:13.378] <TB3> INFO: Test took 3770ms.
[17:12:13.684] <TB3> INFO: Expecting 41600 events.
[17:12:17.218] <TB3> INFO: 41600 events read in total (2942ms).
[17:12:17.219] <TB3> INFO: Test took 3816ms.
[17:12:17.510] <TB3> INFO: Expecting 41600 events.
[17:12:21.032] <TB3> INFO: 41600 events read in total (2930ms).
[17:12:21.033] <TB3> INFO: Test took 3788ms.
[17:12:21.323] <TB3> INFO: Expecting 2560 events.
[17:12:22.211] <TB3> INFO: 2560 events read in total (296ms).
[17:12:22.212] <TB3> INFO: Test took 1166ms.
[17:12:22.520] <TB3> INFO: Expecting 2560 events.
[17:12:23.413] <TB3> INFO: 2560 events read in total (301ms).
[17:12:23.413] <TB3> INFO: Test took 1201ms.
[17:12:23.722] <TB3> INFO: Expecting 2560 events.
[17:12:24.615] <TB3> INFO: 2560 events read in total (302ms).
[17:12:24.615] <TB3> INFO: Test took 1201ms.
[17:12:24.923] <TB3> INFO: Expecting 2560 events.
[17:12:25.816] <TB3> INFO: 2560 events read in total (302ms).
[17:12:25.816] <TB3> INFO: Test took 1200ms.
[17:12:26.124] <TB3> INFO: Expecting 2560 events.
[17:12:27.014] <TB3> INFO: 2560 events read in total (298ms).
[17:12:27.014] <TB3> INFO: Test took 1197ms.
[17:12:27.322] <TB3> INFO: Expecting 2560 events.
[17:12:28.205] <TB3> INFO: 2560 events read in total (291ms).
[17:12:28.206] <TB3> INFO: Test took 1192ms.
[17:12:28.514] <TB3> INFO: Expecting 2560 events.
[17:12:29.396] <TB3> INFO: 2560 events read in total (290ms).
[17:12:29.396] <TB3> INFO: Test took 1190ms.
[17:12:29.704] <TB3> INFO: Expecting 2560 events.
[17:12:30.592] <TB3> INFO: 2560 events read in total (296ms).
[17:12:30.592] <TB3> INFO: Test took 1196ms.
[17:12:30.899] <TB3> INFO: Expecting 2560 events.
[17:12:31.789] <TB3> INFO: 2560 events read in total (298ms).
[17:12:31.789] <TB3> INFO: Test took 1196ms.
[17:12:32.097] <TB3> INFO: Expecting 2560 events.
[17:12:32.979] <TB3> INFO: 2560 events read in total (290ms).
[17:12:32.979] <TB3> INFO: Test took 1190ms.
[17:12:33.288] <TB3> INFO: Expecting 2560 events.
[17:12:34.177] <TB3> INFO: 2560 events read in total (297ms).
[17:12:34.178] <TB3> INFO: Test took 1198ms.
[17:12:34.485] <TB3> INFO: Expecting 2560 events.
[17:12:35.365] <TB3> INFO: 2560 events read in total (288ms).
[17:12:35.366] <TB3> INFO: Test took 1188ms.
[17:12:35.673] <TB3> INFO: Expecting 2560 events.
[17:12:36.563] <TB3> INFO: 2560 events read in total (298ms).
[17:12:36.563] <TB3> INFO: Test took 1197ms.
[17:12:36.871] <TB3> INFO: Expecting 2560 events.
[17:12:37.765] <TB3> INFO: 2560 events read in total (302ms).
[17:12:37.765] <TB3> INFO: Test took 1202ms.
[17:12:38.073] <TB3> INFO: Expecting 2560 events.
[17:12:38.965] <TB3> INFO: 2560 events read in total (300ms).
[17:12:38.965] <TB3> INFO: Test took 1199ms.
[17:12:39.273] <TB3> INFO: Expecting 2560 events.
[17:12:40.165] <TB3> INFO: 2560 events read in total (300ms).
[17:12:40.165] <TB3> INFO: Test took 1200ms.
[17:12:40.169] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:12:40.474] <TB3> INFO: Expecting 655360 events.
[17:12:55.268] <TB3> INFO: 655360 events read in total (14202ms).
[17:12:55.283] <TB3> INFO: Expecting 655360 events.
[17:13:09.948] <TB3> INFO: 655360 events read in total (14262ms).
[17:13:09.966] <TB3> INFO: Expecting 655360 events.
[17:13:24.595] <TB3> INFO: 655360 events read in total (14226ms).
[17:13:24.618] <TB3> INFO: Expecting 655360 events.
[17:13:39.148] <TB3> INFO: 655360 events read in total (14127ms).
[17:13:39.176] <TB3> INFO: Expecting 655360 events.
[17:13:53.736] <TB3> INFO: 655360 events read in total (14157ms).
[17:13:53.767] <TB3> INFO: Expecting 655360 events.
[17:14:08.339] <TB3> INFO: 655360 events read in total (14169ms).
[17:14:08.378] <TB3> INFO: Expecting 655360 events.
[17:14:22.969] <TB3> INFO: 655360 events read in total (14188ms).
[17:14:23.020] <TB3> INFO: Expecting 655360 events.
[17:14:37.466] <TB3> INFO: 655360 events read in total (14043ms).
[17:14:37.512] <TB3> INFO: Expecting 655360 events.
[17:14:51.905] <TB3> INFO: 655360 events read in total (13990ms).
[17:14:51.952] <TB3> INFO: Expecting 655360 events.
[17:15:06.640] <TB3> INFO: 655360 events read in total (14285ms).
[17:15:06.729] <TB3> INFO: Expecting 655360 events.
[17:15:21.228] <TB3> INFO: 655360 events read in total (14096ms).
[17:15:21.319] <TB3> INFO: Expecting 655360 events.
[17:15:35.999] <TB3> INFO: 655360 events read in total (14277ms).
[17:15:36.074] <TB3> INFO: Expecting 655360 events.
[17:15:50.722] <TB3> INFO: 655360 events read in total (14245ms).
[17:15:50.807] <TB3> INFO: Expecting 655360 events.
[17:16:05.400] <TB3> INFO: 655360 events read in total (14190ms).
[17:16:05.522] <TB3> INFO: Expecting 655360 events.
[17:16:20.065] <TB3> INFO: 655360 events read in total (14140ms).
[17:16:20.181] <TB3> INFO: Expecting 655360 events.
[17:16:34.872] <TB3> INFO: 655360 events read in total (14288ms).
[17:16:34.973] <TB3> INFO: Test took 234804ms.
[17:16:35.073] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:35.325] <TB3> INFO: Expecting 655360 events.
[17:16:50.367] <TB3> INFO: 655360 events read in total (14450ms).
[17:16:50.384] <TB3> INFO: Expecting 655360 events.
[17:17:05.238] <TB3> INFO: 655360 events read in total (14451ms).
[17:17:05.257] <TB3> INFO: Expecting 655360 events.
[17:17:20.330] <TB3> INFO: 655360 events read in total (14670ms).
[17:17:20.353] <TB3> INFO: Expecting 655360 events.
[17:17:34.980] <TB3> INFO: 655360 events read in total (14224ms).
[17:17:35.006] <TB3> INFO: Expecting 655360 events.
[17:17:49.907] <TB3> INFO: 655360 events read in total (14498ms).
[17:17:49.945] <TB3> INFO: Expecting 655360 events.
[17:18:04.437] <TB3> INFO: 655360 events read in total (14089ms).
[17:18:04.479] <TB3> INFO: Expecting 655360 events.
[17:18:19.193] <TB3> INFO: 655360 events read in total (14311ms).
[17:18:19.240] <TB3> INFO: Expecting 655360 events.
[17:18:33.965] <TB3> INFO: 655360 events read in total (14322ms).
[17:18:34.007] <TB3> INFO: Expecting 655360 events.
[17:18:48.801] <TB3> INFO: 655360 events read in total (14391ms).
[17:18:48.847] <TB3> INFO: Expecting 655360 events.
[17:19:03.306] <TB3> INFO: 655360 events read in total (14056ms).
[17:19:03.372] <TB3> INFO: Expecting 655360 events.
[17:19:17.608] <TB3> INFO: 655360 events read in total (13833ms).
[17:19:17.682] <TB3> INFO: Expecting 655360 events.
[17:19:31.993] <TB3> INFO: 655360 events read in total (13908ms).
[17:19:32.114] <TB3> INFO: Expecting 655360 events.
[17:19:46.399] <TB3> INFO: 655360 events read in total (13882ms).
[17:19:46.484] <TB3> INFO: Expecting 655360 events.
[17:20:00.976] <TB3> INFO: 655360 events read in total (14089ms).
[17:20:01.121] <TB3> INFO: Expecting 655360 events.
[17:20:15.501] <TB3> INFO: 655360 events read in total (13977ms).
[17:20:15.628] <TB3> INFO: Expecting 655360 events.
[17:20:29.761] <TB3> INFO: 655360 events read in total (13730ms).
[17:20:29.927] <TB3> INFO: Test took 234854ms.
[17:20:30.145] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.151] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.158] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[17:20:30.167] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[17:20:30.177] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.187] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.195] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.204] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[17:20:30.212] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[17:20:30.221] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[17:20:30.230] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[17:20:30.239] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.248] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.257] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[17:20:30.265] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[17:20:30.274] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[17:20:30.285] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.291] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.297] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.303] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.309] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[17:20:30.315] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[17:20:30.325] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[17:20:30.333] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[17:20:30.339] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[17:20:30.348] <TB3> INFO: safety margin for low PH: adding 6, margin is now 26
[17:20:30.358] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.367] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.375] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.383] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.391] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:20:30.430] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C0.dat
[17:20:30.430] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C1.dat
[17:20:30.430] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C2.dat
[17:20:30.431] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C3.dat
[17:20:30.431] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C4.dat
[17:20:30.431] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C5.dat
[17:20:30.431] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C6.dat
[17:20:30.431] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C7.dat
[17:20:30.431] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C8.dat
[17:20:30.431] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C9.dat
[17:20:30.431] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C10.dat
[17:20:30.431] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C11.dat
[17:20:30.431] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C12.dat
[17:20:30.431] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C13.dat
[17:20:30.431] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C14.dat
[17:20:30.431] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C15.dat
[17:20:30.706] <TB3> INFO: Expecting 41600 events.
[17:20:33.853] <TB3> INFO: 41600 events read in total (2555ms).
[17:20:33.854] <TB3> INFO: Test took 3420ms.
[17:20:34.338] <TB3> INFO: Expecting 41600 events.
[17:20:37.353] <TB3> INFO: 41600 events read in total (2423ms).
[17:20:37.355] <TB3> INFO: Test took 3289ms.
[17:20:37.892] <TB3> INFO: Expecting 41600 events.
[17:20:41.033] <TB3> INFO: 41600 events read in total (2550ms).
[17:20:41.034] <TB3> INFO: Test took 3467ms.
[17:20:41.253] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:41.343] <TB3> INFO: Expecting 2560 events.
[17:20:42.238] <TB3> INFO: 2560 events read in total (303ms).
[17:20:42.239] <TB3> INFO: Test took 986ms.
[17:20:42.244] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:42.546] <TB3> INFO: Expecting 2560 events.
[17:20:43.443] <TB3> INFO: 2560 events read in total (305ms).
[17:20:43.444] <TB3> INFO: Test took 1200ms.
[17:20:43.447] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:43.752] <TB3> INFO: Expecting 2560 events.
[17:20:44.638] <TB3> INFO: 2560 events read in total (293ms).
[17:20:44.639] <TB3> INFO: Test took 1192ms.
[17:20:44.641] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:44.945] <TB3> INFO: Expecting 2560 events.
[17:20:45.839] <TB3> INFO: 2560 events read in total (302ms).
[17:20:45.839] <TB3> INFO: Test took 1198ms.
[17:20:45.843] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:46.148] <TB3> INFO: Expecting 2560 events.
[17:20:47.037] <TB3> INFO: 2560 events read in total (297ms).
[17:20:47.037] <TB3> INFO: Test took 1194ms.
[17:20:47.042] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:47.345] <TB3> INFO: Expecting 2560 events.
[17:20:48.238] <TB3> INFO: 2560 events read in total (302ms).
[17:20:48.239] <TB3> INFO: Test took 1197ms.
[17:20:48.241] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:48.546] <TB3> INFO: Expecting 2560 events.
[17:20:49.430] <TB3> INFO: 2560 events read in total (293ms).
[17:20:49.430] <TB3> INFO: Test took 1189ms.
[17:20:49.433] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:49.738] <TB3> INFO: Expecting 2560 events.
[17:20:50.629] <TB3> INFO: 2560 events read in total (300ms).
[17:20:50.629] <TB3> INFO: Test took 1196ms.
[17:20:50.636] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:50.937] <TB3> INFO: Expecting 2560 events.
[17:20:51.820] <TB3> INFO: 2560 events read in total (292ms).
[17:20:51.820] <TB3> INFO: Test took 1184ms.
[17:20:51.822] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:52.128] <TB3> INFO: Expecting 2560 events.
[17:20:53.011] <TB3> INFO: 2560 events read in total (291ms).
[17:20:53.011] <TB3> INFO: Test took 1189ms.
[17:20:53.013] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:53.319] <TB3> INFO: Expecting 2560 events.
[17:20:54.199] <TB3> INFO: 2560 events read in total (288ms).
[17:20:54.199] <TB3> INFO: Test took 1186ms.
[17:20:54.201] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:54.508] <TB3> INFO: Expecting 2560 events.
[17:20:55.388] <TB3> INFO: 2560 events read in total (289ms).
[17:20:55.389] <TB3> INFO: Test took 1188ms.
[17:20:55.391] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:55.696] <TB3> INFO: Expecting 2560 events.
[17:20:56.579] <TB3> INFO: 2560 events read in total (291ms).
[17:20:56.579] <TB3> INFO: Test took 1189ms.
[17:20:56.581] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:56.888] <TB3> INFO: Expecting 2560 events.
[17:20:57.770] <TB3> INFO: 2560 events read in total (290ms).
[17:20:57.770] <TB3> INFO: Test took 1189ms.
[17:20:57.772] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:58.078] <TB3> INFO: Expecting 2560 events.
[17:20:58.961] <TB3> INFO: 2560 events read in total (290ms).
[17:20:58.961] <TB3> INFO: Test took 1189ms.
[17:20:58.963] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:59.269] <TB3> INFO: Expecting 2560 events.
[17:21:00.150] <TB3> INFO: 2560 events read in total (289ms).
[17:21:00.151] <TB3> INFO: Test took 1188ms.
[17:21:00.154] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:00.458] <TB3> INFO: Expecting 2560 events.
[17:21:01.340] <TB3> INFO: 2560 events read in total (290ms).
[17:21:01.340] <TB3> INFO: Test took 1186ms.
[17:21:01.342] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:01.649] <TB3> INFO: Expecting 2560 events.
[17:21:02.532] <TB3> INFO: 2560 events read in total (291ms).
[17:21:02.532] <TB3> INFO: Test took 1190ms.
[17:21:02.534] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:02.840] <TB3> INFO: Expecting 2560 events.
[17:21:03.723] <TB3> INFO: 2560 events read in total (291ms).
[17:21:03.723] <TB3> INFO: Test took 1189ms.
[17:21:03.725] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:04.031] <TB3> INFO: Expecting 2560 events.
[17:21:04.909] <TB3> INFO: 2560 events read in total (287ms).
[17:21:04.910] <TB3> INFO: Test took 1185ms.
[17:21:04.912] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:05.218] <TB3> INFO: Expecting 2560 events.
[17:21:06.105] <TB3> INFO: 2560 events read in total (295ms).
[17:21:06.105] <TB3> INFO: Test took 1193ms.
[17:21:06.107] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:06.413] <TB3> INFO: Expecting 2560 events.
[17:21:07.300] <TB3> INFO: 2560 events read in total (295ms).
[17:21:07.300] <TB3> INFO: Test took 1193ms.
[17:21:07.303] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:07.607] <TB3> INFO: Expecting 2560 events.
[17:21:08.490] <TB3> INFO: 2560 events read in total (291ms).
[17:21:08.491] <TB3> INFO: Test took 1188ms.
[17:21:08.493] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:08.799] <TB3> INFO: Expecting 2560 events.
[17:21:09.688] <TB3> INFO: 2560 events read in total (297ms).
[17:21:09.688] <TB3> INFO: Test took 1195ms.
[17:21:09.693] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:09.996] <TB3> INFO: Expecting 2560 events.
[17:21:10.890] <TB3> INFO: 2560 events read in total (302ms).
[17:21:10.890] <TB3> INFO: Test took 1197ms.
[17:21:10.895] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:11.199] <TB3> INFO: Expecting 2560 events.
[17:21:12.085] <TB3> INFO: 2560 events read in total (294ms).
[17:21:12.086] <TB3> INFO: Test took 1191ms.
[17:21:12.089] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:12.392] <TB3> INFO: Expecting 2560 events.
[17:21:13.276] <TB3> INFO: 2560 events read in total (292ms).
[17:21:13.276] <TB3> INFO: Test took 1188ms.
[17:21:13.279] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:13.586] <TB3> INFO: Expecting 2560 events.
[17:21:14.471] <TB3> INFO: 2560 events read in total (293ms).
[17:21:14.471] <TB3> INFO: Test took 1192ms.
[17:21:14.474] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:14.779] <TB3> INFO: Expecting 2560 events.
[17:21:15.674] <TB3> INFO: 2560 events read in total (303ms).
[17:21:15.674] <TB3> INFO: Test took 1200ms.
[17:21:15.677] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:15.982] <TB3> INFO: Expecting 2560 events.
[17:21:16.875] <TB3> INFO: 2560 events read in total (301ms).
[17:21:16.876] <TB3> INFO: Test took 1199ms.
[17:21:16.881] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:17.184] <TB3> INFO: Expecting 2560 events.
[17:21:18.074] <TB3> INFO: 2560 events read in total (299ms).
[17:21:18.074] <TB3> INFO: Test took 1193ms.
[17:21:18.077] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:21:18.383] <TB3> INFO: Expecting 2560 events.
[17:21:19.271] <TB3> INFO: 2560 events read in total (296ms).
[17:21:19.271] <TB3> INFO: Test took 1194ms.
[17:21:19.736] <TB3> INFO: PixTestPhOptimization::doTest() done, duration: 654 seconds
[17:21:19.736] <TB3> INFO: PH scale (per ROC): 37 34 28 51 48 35 30 38 52 48 46 48 41 36 47 44
[17:21:19.736] <TB3> INFO: PH offset (per ROC): 107 105 107 129 115 94 92 93 120 106 98 113 103 112 125 104
[17:21:19.744] <TB3> INFO: Decoding statistics:
[17:21:19.744] <TB3> INFO: General information:
[17:21:19.744] <TB3> INFO: 16bit words read: 127890
[17:21:19.744] <TB3> INFO: valid events total: 20480
[17:21:19.744] <TB3> INFO: empty events: 17975
[17:21:19.744] <TB3> INFO: valid events with pixels: 2505
[17:21:19.744] <TB3> INFO: valid pixel hits: 2505
[17:21:19.744] <TB3> INFO: Event errors: 0
[17:21:19.744] <TB3> INFO: start marker: 0
[17:21:19.744] <TB3> INFO: stop marker: 0
[17:21:19.744] <TB3> INFO: overflow: 0
[17:21:19.744] <TB3> INFO: invalid 5bit words: 0
[17:21:19.744] <TB3> INFO: invalid XOR eye diagram: 0
[17:21:19.744] <TB3> INFO: frame (failed synchr.): 0
[17:21:19.744] <TB3> INFO: idle data (no TBM trl): 0
[17:21:19.744] <TB3> INFO: no data (only TBM hdr): 0
[17:21:19.744] <TB3> INFO: TBM errors: 0
[17:21:19.744] <TB3> INFO: flawed TBM headers: 0
[17:21:19.744] <TB3> INFO: flawed TBM trailers: 0
[17:21:19.744] <TB3> INFO: event ID mismatches: 0
[17:21:19.744] <TB3> INFO: ROC errors: 0
[17:21:19.744] <TB3> INFO: missing ROC header(s): 0
[17:21:19.744] <TB3> INFO: misplaced readback start: 0
[17:21:19.744] <TB3> INFO: Pixel decoding errors: 0
[17:21:19.744] <TB3> INFO: pixel data incomplete: 0
[17:21:19.744] <TB3> INFO: pixel address: 0
[17:21:19.744] <TB3> INFO: pulse height fill bit: 0
[17:21:19.745] <TB3> INFO: buffer corruption: 0
[17:21:19.938] <TB3> INFO: ######################################################################
[17:21:19.938] <TB3> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[17:21:19.938] <TB3> INFO: ######################################################################
[17:21:19.954] <TB3> INFO: scanning low vcal = 10
[17:21:20.247] <TB3> INFO: Expecting 41600 events.
[17:21:23.815] <TB3> INFO: 41600 events read in total (2976ms).
[17:21:23.815] <TB3> INFO: Test took 3861ms.
[17:21:23.817] <TB3> INFO: scanning low vcal = 20
[17:21:24.113] <TB3> INFO: Expecting 41600 events.
[17:21:27.691] <TB3> INFO: 41600 events read in total (2987ms).
[17:21:27.691] <TB3> INFO: Test took 3874ms.
[17:21:27.694] <TB3> INFO: scanning low vcal = 30
[17:21:27.992] <TB3> INFO: Expecting 41600 events.
[17:21:31.635] <TB3> INFO: 41600 events read in total (3052ms).
[17:21:31.636] <TB3> INFO: Test took 3942ms.
[17:21:31.639] <TB3> INFO: scanning low vcal = 40
[17:21:31.920] <TB3> INFO: Expecting 41600 events.
[17:21:35.954] <TB3> INFO: 41600 events read in total (3442ms).
[17:21:35.955] <TB3> INFO: Test took 4316ms.
[17:21:35.959] <TB3> INFO: scanning low vcal = 50
[17:21:36.236] <TB3> INFO: Expecting 41600 events.
[17:21:40.244] <TB3> INFO: 41600 events read in total (3416ms).
[17:21:40.244] <TB3> INFO: Test took 4285ms.
[17:21:40.248] <TB3> INFO: scanning low vcal = 60
[17:21:40.524] <TB3> INFO: Expecting 41600 events.
[17:21:44.480] <TB3> INFO: 41600 events read in total (3364ms).
[17:21:44.481] <TB3> INFO: Test took 4233ms.
[17:21:44.484] <TB3> INFO: scanning low vcal = 70
[17:21:44.761] <TB3> INFO: Expecting 41600 events.
[17:21:48.740] <TB3> INFO: 41600 events read in total (3388ms).
[17:21:48.740] <TB3> INFO: Test took 4256ms.
[17:21:48.744] <TB3> INFO: scanning low vcal = 80
[17:21:49.023] <TB3> INFO: Expecting 41600 events.
[17:21:52.986] <TB3> INFO: 41600 events read in total (3371ms).
[17:21:52.987] <TB3> INFO: Test took 4243ms.
[17:21:52.990] <TB3> INFO: scanning low vcal = 90
[17:21:53.267] <TB3> INFO: Expecting 41600 events.
[17:21:57.240] <TB3> INFO: 41600 events read in total (3382ms).
[17:21:57.241] <TB3> INFO: Test took 4251ms.
[17:21:57.244] <TB3> INFO: scanning low vcal = 100
[17:21:57.520] <TB3> INFO: Expecting 41600 events.
[17:22:01.499] <TB3> INFO: 41600 events read in total (3387ms).
[17:22:01.500] <TB3> INFO: Test took 4255ms.
[17:22:01.503] <TB3> INFO: scanning low vcal = 110
[17:22:01.780] <TB3> INFO: Expecting 41600 events.
[17:22:05.840] <TB3> INFO: 41600 events read in total (3469ms).
[17:22:05.841] <TB3> INFO: Test took 4338ms.
[17:22:05.845] <TB3> INFO: scanning low vcal = 120
[17:22:06.122] <TB3> INFO: Expecting 41600 events.
[17:22:10.093] <TB3> INFO: 41600 events read in total (3380ms).
[17:22:10.093] <TB3> INFO: Test took 4248ms.
[17:22:10.096] <TB3> INFO: scanning low vcal = 130
[17:22:10.373] <TB3> INFO: Expecting 41600 events.
[17:22:14.314] <TB3> INFO: 41600 events read in total (3349ms).
[17:22:14.315] <TB3> INFO: Test took 4219ms.
[17:22:14.318] <TB3> INFO: scanning low vcal = 140
[17:22:14.595] <TB3> INFO: Expecting 41600 events.
[17:22:18.554] <TB3> INFO: 41600 events read in total (3368ms).
[17:22:18.555] <TB3> INFO: Test took 4237ms.
[17:22:18.558] <TB3> INFO: scanning low vcal = 150
[17:22:18.839] <TB3> INFO: Expecting 41600 events.
[17:22:22.806] <TB3> INFO: 41600 events read in total (3376ms).
[17:22:22.806] <TB3> INFO: Test took 4248ms.
[17:22:22.810] <TB3> INFO: scanning low vcal = 160
[17:22:23.093] <TB3> INFO: Expecting 41600 events.
[17:22:27.063] <TB3> INFO: 41600 events read in total (3378ms).
[17:22:27.063] <TB3> INFO: Test took 4253ms.
[17:22:27.066] <TB3> INFO: scanning low vcal = 170
[17:22:27.343] <TB3> INFO: Expecting 41600 events.
[17:22:31.315] <TB3> INFO: 41600 events read in total (3380ms).
[17:22:31.316] <TB3> INFO: Test took 4249ms.
[17:22:31.321] <TB3> INFO: scanning low vcal = 180
[17:22:31.597] <TB3> INFO: Expecting 41600 events.
[17:22:35.582] <TB3> INFO: 41600 events read in total (3393ms).
[17:22:35.583] <TB3> INFO: Test took 4262ms.
[17:22:35.586] <TB3> INFO: scanning low vcal = 190
[17:22:35.905] <TB3> INFO: Expecting 41600 events.
[17:22:39.854] <TB3> INFO: 41600 events read in total (3357ms).
[17:22:39.855] <TB3> INFO: Test took 4269ms.
[17:22:39.858] <TB3> INFO: scanning low vcal = 200
[17:22:40.134] <TB3> INFO: Expecting 41600 events.
[17:22:44.117] <TB3> INFO: 41600 events read in total (3391ms).
[17:22:44.117] <TB3> INFO: Test took 4259ms.
[17:22:44.120] <TB3> INFO: scanning low vcal = 210
[17:22:44.397] <TB3> INFO: Expecting 41600 events.
[17:22:48.383] <TB3> INFO: 41600 events read in total (3394ms).
[17:22:48.384] <TB3> INFO: Test took 4264ms.
[17:22:48.387] <TB3> INFO: scanning low vcal = 220
[17:22:48.667] <TB3> INFO: Expecting 41600 events.
[17:22:52.645] <TB3> INFO: 41600 events read in total (3386ms).
[17:22:52.646] <TB3> INFO: Test took 4259ms.
[17:22:52.650] <TB3> INFO: scanning low vcal = 230
[17:22:52.944] <TB3> INFO: Expecting 41600 events.
[17:22:56.933] <TB3> INFO: 41600 events read in total (3397ms).
[17:22:56.934] <TB3> INFO: Test took 4283ms.
[17:22:56.937] <TB3> INFO: scanning low vcal = 240
[17:22:57.214] <TB3> INFO: Expecting 41600 events.
[17:23:01.186] <TB3> INFO: 41600 events read in total (3380ms).
[17:23:01.187] <TB3> INFO: Test took 4250ms.
[17:23:01.190] <TB3> INFO: scanning low vcal = 250
[17:23:01.466] <TB3> INFO: Expecting 41600 events.
[17:23:05.437] <TB3> INFO: 41600 events read in total (3379ms).
[17:23:05.438] <TB3> INFO: Test took 4248ms.
[17:23:05.442] <TB3> INFO: scanning high vcal = 30 (= 210 in low range)
[17:23:05.718] <TB3> INFO: Expecting 41600 events.
[17:23:09.818] <TB3> INFO: 41600 events read in total (3508ms).
[17:23:09.819] <TB3> INFO: Test took 4376ms.
[17:23:09.823] <TB3> INFO: scanning high vcal = 50 (= 350 in low range)
[17:23:10.126] <TB3> INFO: Expecting 41600 events.
[17:23:14.076] <TB3> INFO: 41600 events read in total (3358ms).
[17:23:14.076] <TB3> INFO: Test took 4253ms.
[17:23:14.080] <TB3> INFO: scanning high vcal = 70 (= 490 in low range)
[17:23:14.361] <TB3> INFO: Expecting 41600 events.
[17:23:18.310] <TB3> INFO: 41600 events read in total (3357ms).
[17:23:18.311] <TB3> INFO: Test took 4230ms.
[17:23:18.314] <TB3> INFO: scanning high vcal = 90 (= 630 in low range)
[17:23:18.594] <TB3> INFO: Expecting 41600 events.
[17:23:22.542] <TB3> INFO: 41600 events read in total (3356ms).
[17:23:22.543] <TB3> INFO: Test took 4227ms.
[17:23:22.546] <TB3> INFO: scanning high vcal = 200 (= 1400 in low range)
[17:23:22.822] <TB3> INFO: Expecting 41600 events.
[17:23:26.768] <TB3> INFO: 41600 events read in total (3354ms).
[17:23:26.769] <TB3> INFO: Test took 4223ms.
[17:23:27.178] <TB3> INFO: PixTestGainPedestal::measure() done
[17:24:05.557] <TB3> INFO: PixTestGainPedestal::fit() done
[17:24:05.557] <TB3> INFO: non-linearity mean: 0.935 0.946 1.010 0.984 0.963 0.928 0.996 0.900 0.983 0.959 0.959 0.983 0.954 0.927 0.979 0.935
[17:24:05.557] <TB3> INFO: non-linearity RMS: 0.111 0.050 0.170 0.003 0.037 0.187 0.186 0.097 0.005 0.033 0.043 0.004 0.061 0.114 0.004 0.064
[17:24:05.557] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[17:24:05.570] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[17:24:05.585] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[17:24:05.599] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[17:24:05.613] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[17:24:05.626] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[17:24:05.639] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[17:24:05.652] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[17:24:05.666] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[17:24:05.680] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[17:24:05.693] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[17:24:05.707] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[17:24:05.721] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[17:24:05.734] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[17:24:05.748] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[17:24:05.761] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[17:24:05.774] <TB3> INFO: PixTestGainPedestal::fullTest() done, duration: 165 seconds
[17:24:05.774] <TB3> INFO: Decoding statistics:
[17:24:05.774] <TB3> INFO: General information:
[17:24:05.774] <TB3> INFO: 16bit words read: 3261234
[17:24:05.774] <TB3> INFO: valid events total: 332800
[17:24:05.774] <TB3> INFO: empty events: 3293
[17:24:05.774] <TB3> INFO: valid events with pixels: 329507
[17:24:05.774] <TB3> INFO: valid pixel hits: 632217
[17:24:05.774] <TB3> INFO: Event errors: 0
[17:24:05.774] <TB3> INFO: start marker: 0
[17:24:05.774] <TB3> INFO: stop marker: 0
[17:24:05.774] <TB3> INFO: overflow: 0
[17:24:05.774] <TB3> INFO: invalid 5bit words: 0
[17:24:05.774] <TB3> INFO: invalid XOR eye diagram: 0
[17:24:05.774] <TB3> INFO: frame (failed synchr.): 0
[17:24:05.774] <TB3> INFO: idle data (no TBM trl): 0
[17:24:05.774] <TB3> INFO: no data (only TBM hdr): 0
[17:24:05.774] <TB3> INFO: TBM errors: 0
[17:24:05.774] <TB3> INFO: flawed TBM headers: 0
[17:24:05.774] <TB3> INFO: flawed TBM trailers: 0
[17:24:05.774] <TB3> INFO: event ID mismatches: 0
[17:24:05.774] <TB3> INFO: ROC errors: 0
[17:24:05.774] <TB3> INFO: missing ROC header(s): 0
[17:24:05.774] <TB3> INFO: misplaced readback start: 0
[17:24:05.774] <TB3> INFO: Pixel decoding errors: 0
[17:24:05.774] <TB3> INFO: pixel data incomplete: 0
[17:24:05.774] <TB3> INFO: pixel address: 0
[17:24:05.774] <TB3> INFO: pulse height fill bit: 0
[17:24:05.774] <TB3> INFO: buffer corruption: 0
[17:24:05.794] <TB3> INFO: Decoding statistics:
[17:24:05.794] <TB3> INFO: General information:
[17:24:05.794] <TB3> INFO: 16bit words read: 3390660
[17:24:05.794] <TB3> INFO: valid events total: 353536
[17:24:05.794] <TB3> INFO: empty events: 21524
[17:24:05.794] <TB3> INFO: valid events with pixels: 332012
[17:24:05.794] <TB3> INFO: valid pixel hits: 634722
[17:24:05.794] <TB3> INFO: Event errors: 0
[17:24:05.794] <TB3> INFO: start marker: 0
[17:24:05.794] <TB3> INFO: stop marker: 0
[17:24:05.794] <TB3> INFO: overflow: 0
[17:24:05.794] <TB3> INFO: invalid 5bit words: 0
[17:24:05.794] <TB3> INFO: invalid XOR eye diagram: 0
[17:24:05.794] <TB3> INFO: frame (failed synchr.): 0
[17:24:05.794] <TB3> INFO: idle data (no TBM trl): 0
[17:24:05.794] <TB3> INFO: no data (only TBM hdr): 0
[17:24:05.794] <TB3> INFO: TBM errors: 0
[17:24:05.794] <TB3> INFO: flawed TBM headers: 0
[17:24:05.794] <TB3> INFO: flawed TBM trailers: 0
[17:24:05.794] <TB3> INFO: event ID mismatches: 0
[17:24:05.794] <TB3> INFO: ROC errors: 0
[17:24:05.794] <TB3> INFO: missing ROC header(s): 0
[17:24:05.794] <TB3> INFO: misplaced readback start: 0
[17:24:05.794] <TB3> INFO: Pixel decoding errors: 0
[17:24:05.794] <TB3> INFO: pixel data incomplete: 0
[17:24:05.794] <TB3> INFO: pixel address: 0
[17:24:05.794] <TB3> INFO: pulse height fill bit: 0
[17:24:05.794] <TB3> INFO: buffer corruption: 0
[17:24:05.794] <TB3> INFO: enter test to run
[17:24:05.794] <TB3> INFO: test: trim80 no parameter change
[17:24:05.794] <TB3> INFO: running: trim80
[17:24:05.796] <TB3> INFO: ######################################################################
[17:24:05.796] <TB3> INFO: PixTestTrim80::doTest()
[17:24:05.796] <TB3> INFO: ######################################################################
[17:24:05.797] <TB3> INFO: ----------------------------------------------------------------------
[17:24:05.797] <TB3> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[17:24:05.797] <TB3> INFO: ----------------------------------------------------------------------
[17:24:05.838] <TB3> INFO: ---> VthrComp thr map (minimal VthrComp)
[17:24:05.838] <TB3> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:24:05.851] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[17:24:05.851] <TB3> INFO: run 1 of 1
[17:24:06.088] <TB3> INFO: Expecting 5025280 events.
[17:24:34.824] <TB3> INFO: 687200 events read in total (28144ms).
[17:25:02.687] <TB3> INFO: 1371800 events read in total (56007ms).
[17:25:30.803] <TB3> INFO: 2054448 events read in total (84123ms).
[17:25:59.145] <TB3> INFO: 2735496 events read in total (112465ms).
[17:26:27.004] <TB3> INFO: 3414384 events read in total (140324ms).
[17:26:54.984] <TB3> INFO: 4090928 events read in total (168304ms).
[17:27:22.915] <TB3> INFO: 4767248 events read in total (196235ms).
[17:27:33.667] <TB3> INFO: 5025280 events read in total (206987ms).
[17:27:33.740] <TB3> INFO: Test took 207889ms.
[17:27:56.030] <TB3> INFO: ROC 0 VthrComp = 78
[17:27:56.031] <TB3> INFO: ROC 1 VthrComp = 79
[17:27:56.031] <TB3> INFO: ROC 2 VthrComp = 75
[17:27:56.032] <TB3> INFO: ROC 3 VthrComp = 77
[17:27:56.032] <TB3> INFO: ROC 4 VthrComp = 78
[17:27:56.032] <TB3> INFO: ROC 5 VthrComp = 76
[17:27:56.032] <TB3> INFO: ROC 6 VthrComp = 78
[17:27:56.032] <TB3> INFO: ROC 7 VthrComp = 99
[17:27:56.032] <TB3> INFO: ROC 8 VthrComp = 79
[17:27:56.032] <TB3> INFO: ROC 9 VthrComp = 78
[17:27:56.032] <TB3> INFO: ROC 10 VthrComp = 80
[17:27:56.032] <TB3> INFO: ROC 11 VthrComp = 82
[17:27:56.032] <TB3> INFO: ROC 12 VthrComp = 84
[17:27:56.033] <TB3> INFO: ROC 13 VthrComp = 72
[17:27:56.033] <TB3> INFO: ROC 14 VthrComp = 70
[17:27:56.033] <TB3> INFO: ROC 15 VthrComp = 76
[17:27:56.273] <TB3> INFO: Expecting 41600 events.
[17:27:59.755] <TB3> INFO: 41600 events read in total (2891ms).
[17:27:59.756] <TB3> INFO: Test took 3722ms.
[17:27:59.765] <TB3> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[17:27:59.765] <TB3> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:27:59.777] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[17:27:59.777] <TB3> INFO: run 1 of 1
[17:28:00.103] <TB3> INFO: Expecting 5025280 events.
[17:28:28.296] <TB3> INFO: 684936 events read in total (27602ms).
[17:28:56.021] <TB3> INFO: 1367384 events read in total (55327ms).
[17:29:24.119] <TB3> INFO: 2049344 events read in total (83425ms).
[17:29:51.948] <TB3> INFO: 2728424 events read in total (111254ms).
[17:30:18.881] <TB3> INFO: 3403744 events read in total (138187ms).
[17:30:46.147] <TB3> INFO: 4078864 events read in total (165453ms).
[17:31:13.439] <TB3> INFO: 4752976 events read in total (192745ms).
[17:31:24.957] <TB3> INFO: 5025280 events read in total (204263ms).
[17:31:25.039] <TB3> INFO: Test took 205262ms.
[17:31:48.277] <TB3> INFO: roc 0 with ID = 0 has maximal Vcal 110.357 for pixel 1/16 mean/min/max = 94.18/77.9026/110.457
[17:31:48.277] <TB3> INFO: roc 1 with ID = 1 has maximal Vcal 114.021 for pixel 0/1 mean/min/max = 95.498/76.8732/114.123
[17:31:48.278] <TB3> INFO: roc 2 with ID = 2 has maximal Vcal 111.527 for pixel 0/23 mean/min/max = 94.6999/77.7254/111.674
[17:31:48.279] <TB3> INFO: roc 3 with ID = 3 has maximal Vcal 112.013 for pixel 0/3 mean/min/max = 94.7477/77.3488/112.147
[17:31:48.279] <TB3> INFO: roc 4 with ID = 4 has maximal Vcal 112.277 for pixel 0/17 mean/min/max = 94.8222/77.36/112.284
[17:31:48.279] <TB3> INFO: roc 5 with ID = 5 has maximal Vcal 107.888 for pixel 9/9 mean/min/max = 93.3371/78.6777/107.996
[17:31:48.280] <TB3> INFO: roc 6 with ID = 6 has maximal Vcal 110.999 for pixel 0/44 mean/min/max = 94.6172/78.0887/111.146
[17:31:48.281] <TB3> INFO: roc 7 with ID = 7 has maximal Vcal 109.025 for pixel 0/64 mean/min/max = 91.7154/74.2768/109.154
[17:31:48.281] <TB3> INFO: roc 8 with ID = 8 has maximal Vcal 108.962 for pixel 36/74 mean/min/max = 93.395/77.8017/108.988
[17:31:48.281] <TB3> INFO: roc 9 with ID = 9 has maximal Vcal 111.993 for pixel 0/9 mean/min/max = 94.5765/77.1536/111.999
[17:31:48.282] <TB3> INFO: roc 10 with ID = 10 has maximal Vcal 108.004 for pixel 51/79 mean/min/max = 91.5136/75.0212/108.006
[17:31:48.282] <TB3> INFO: roc 11 with ID = 11 has maximal Vcal 107.209 for pixel 12/9 mean/min/max = 91.1322/75.0267/107.238
[17:31:48.283] <TB3> INFO: roc 12 with ID = 12 has maximal Vcal 105.188 for pixel 10/54 mean/min/max = 90.1226/74.966/105.279
[17:31:48.283] <TB3> INFO: roc 13 with ID = 13 has maximal Vcal 108.143 for pixel 12/77 mean/min/max = 92.5346/76.9016/108.168
[17:31:48.283] <TB3> INFO: roc 14 with ID = 14 has maximal Vcal 106.019 for pixel 0/2 mean/min/max = 89.7493/73.4259/106.073
[17:31:48.284] <TB3> INFO: roc 15 with ID = 15 has maximal Vcal 112.227 for pixel 0/1 mean/min/max = 95.1116/77.7565/112.467
[17:31:48.284] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:31:48.373] <TB3> INFO: Expecting 411648 events.
[17:31:57.907] <TB3> INFO: 411648 events read in total (8942ms).
[17:31:57.915] <TB3> INFO: Expecting 411648 events.
[17:32:07.095] <TB3> INFO: 411648 events read in total (8777ms).
[17:32:07.107] <TB3> INFO: Expecting 411648 events.
[17:32:16.649] <TB3> INFO: 411648 events read in total (9139ms).
[17:32:16.663] <TB3> INFO: Expecting 411648 events.
[17:32:25.965] <TB3> INFO: 411648 events read in total (8899ms).
[17:32:25.981] <TB3> INFO: Expecting 411648 events.
[17:32:35.281] <TB3> INFO: 411648 events read in total (8897ms).
[17:32:35.306] <TB3> INFO: Expecting 411648 events.
[17:32:44.875] <TB3> INFO: 411648 events read in total (9166ms).
[17:32:44.897] <TB3> INFO: Expecting 411648 events.
[17:32:54.132] <TB3> INFO: 411648 events read in total (8832ms).
[17:32:54.165] <TB3> INFO: Expecting 411648 events.
[17:33:03.532] <TB3> INFO: 411648 events read in total (8964ms).
[17:33:03.565] <TB3> INFO: Expecting 411648 events.
[17:33:13.227] <TB3> INFO: 411648 events read in total (9259ms).
[17:33:13.258] <TB3> INFO: Expecting 411648 events.
[17:33:22.558] <TB3> INFO: 411648 events read in total (8897ms).
[17:33:22.602] <TB3> INFO: Expecting 411648 events.
[17:33:31.888] <TB3> INFO: 411648 events read in total (8883ms).
[17:33:31.925] <TB3> INFO: Expecting 411648 events.
[17:33:41.241] <TB3> INFO: 411648 events read in total (8913ms).
[17:33:41.317] <TB3> INFO: Expecting 411648 events.
[17:33:50.559] <TB3> INFO: 411648 events read in total (8838ms).
[17:33:50.624] <TB3> INFO: Expecting 411648 events.
[17:33:59.883] <TB3> INFO: 411648 events read in total (8856ms).
[17:33:59.941] <TB3> INFO: Expecting 411648 events.
[17:34:09.178] <TB3> INFO: 411648 events read in total (8834ms).
[17:34:09.240] <TB3> INFO: Expecting 411648 events.
[17:34:18.497] <TB3> INFO: 411648 events read in total (8854ms).
[17:34:18.565] <TB3> INFO: Test took 150281ms.
[17:34:20.031] <TB3> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[17:34:20.044] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[17:34:20.044] <TB3> INFO: run 1 of 1
[17:34:20.281] <TB3> INFO: Expecting 5025280 events.
[17:34:47.891] <TB3> INFO: 668712 events read in total (27018ms).
[17:35:15.392] <TB3> INFO: 1335768 events read in total (54519ms).
[17:35:42.585] <TB3> INFO: 2002960 events read in total (81713ms).
[17:36:09.722] <TB3> INFO: 2668384 events read in total (108849ms).
[17:36:36.784] <TB3> INFO: 3330112 events read in total (135911ms).
[17:37:04.669] <TB3> INFO: 3992200 events read in total (163796ms).
[17:37:32.287] <TB3> INFO: 4651432 events read in total (191414ms).
[17:37:47.623] <TB3> INFO: 5025280 events read in total (206750ms).
[17:37:47.743] <TB3> INFO: Test took 207699ms.
[17:38:09.283] <TB3> INFO: ---> TrimStepCorr4 extremal thresholds: 55.302621 .. 128.925905
[17:38:09.522] <TB3> INFO: Expecting 208000 events.
[17:38:19.141] <TB3> INFO: 208000 events read in total (9027ms).
[17:38:19.142] <TB3> INFO: Test took 9857ms.
[17:38:19.192] <TB3> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 45 .. 138 (-1/-1) hits flags = 528 (plus default)
[17:38:19.206] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[17:38:19.206] <TB3> INFO: run 1 of 1
[17:38:19.483] <TB3> INFO: Expecting 3128320 events.
[17:38:46.952] <TB3> INFO: 630016 events read in total (26877ms).
[17:39:13.151] <TB3> INFO: 1260248 events read in total (53076ms).
[17:39:39.618] <TB3> INFO: 1889776 events read in total (79543ms).
[17:40:06.544] <TB3> INFO: 2517496 events read in total (106469ms).
[17:40:32.872] <TB3> INFO: 3128320 events read in total (132797ms).
[17:40:32.927] <TB3> INFO: Test took 133721ms.
[17:40:57.120] <TB3> INFO: ---> TrimStepCorr2 extremal thresholds: 62.537386 .. 114.633872
[17:40:57.447] <TB3> INFO: Expecting 208000 events.
[17:41:07.471] <TB3> INFO: 208000 events read in total (9433ms).
[17:41:07.471] <TB3> INFO: Test took 10349ms.
[17:41:07.519] <TB3> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 52 .. 124 (-1/-1) hits flags = 528 (plus default)
[17:41:07.533] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[17:41:07.533] <TB3> INFO: run 1 of 1
[17:41:07.813] <TB3> INFO: Expecting 2429440 events.
[17:41:35.516] <TB3> INFO: 632320 events read in total (27112ms).
[17:42:03.121] <TB3> INFO: 1264240 events read in total (54717ms).
[17:42:30.243] <TB3> INFO: 1895720 events read in total (81839ms).
[17:42:53.218] <TB3> INFO: 2429440 events read in total (104814ms).
[17:42:53.279] <TB3> INFO: Test took 105745ms.
[17:43:12.804] <TB3> INFO: ---> TrimStepCorr1a extremal thresholds: 66.972655 .. 105.021786
[17:43:13.045] <TB3> INFO: Expecting 208000 events.
[17:43:22.689] <TB3> INFO: 208000 events read in total (9052ms).
[17:43:22.689] <TB3> INFO: Test took 9883ms.
[17:43:22.737] <TB3> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 56 .. 115 (-1/-1) hits flags = 528 (plus default)
[17:43:22.750] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[17:43:22.750] <TB3> INFO: run 1 of 1
[17:43:23.029] <TB3> INFO: Expecting 1996800 events.
[17:43:50.768] <TB3> INFO: 637880 events read in total (27148ms).
[17:44:17.847] <TB3> INFO: 1275272 events read in total (54227ms).
[17:44:46.357] <TB3> INFO: 1912272 events read in total (82737ms).
[17:44:50.673] <TB3> INFO: 1996800 events read in total (87053ms).
[17:44:50.707] <TB3> INFO: Test took 87957ms.
[17:45:09.312] <TB3> INFO: ---> TrimStepCorr1b extremal thresholds: 68.427153 .. 98.015159
[17:45:09.550] <TB3> INFO: Expecting 208000 events.
[17:45:19.933] <TB3> INFO: 208000 events read in total (9791ms).
[17:45:19.934] <TB3> INFO: Test took 10620ms.
[17:45:19.987] <TB3> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 58 .. 108 (-1/-1) hits flags = 528 (plus default)
[17:45:19.001] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[17:45:19.001] <TB3> INFO: run 1 of 1
[17:45:20.279] <TB3> INFO: Expecting 1697280 events.
[17:45:49.004] <TB3> INFO: 649064 events read in total (28133ms).
[17:46:16.427] <TB3> INFO: 1298096 events read in total (55556ms).
[17:46:33.523] <TB3> INFO: 1697280 events read in total (72652ms).
[17:46:33.571] <TB3> INFO: Test took 73571ms.
[17:46:51.782] <TB3> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[17:46:51.782] <TB3> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[17:46:51.796] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[17:46:51.796] <TB3> INFO: run 1 of 1
[17:46:52.045] <TB3> INFO: Expecting 1364480 events.
[17:47:20.936] <TB3> INFO: 667848 events read in total (28300ms).
[17:47:48.848] <TB3> INFO: 1334960 events read in total (56212ms).
[17:47:50.516] <TB3> INFO: 1364480 events read in total (57880ms).
[17:47:50.543] <TB3> INFO: Test took 58747ms.
[17:48:09.487] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C0.dat
[17:48:09.487] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C1.dat
[17:48:09.487] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C2.dat
[17:48:09.487] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C3.dat
[17:48:09.487] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C4.dat
[17:48:09.487] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C5.dat
[17:48:09.487] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C6.dat
[17:48:09.488] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C7.dat
[17:48:09.488] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C8.dat
[17:48:09.488] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C9.dat
[17:48:09.488] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C10.dat
[17:48:09.488] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C11.dat
[17:48:09.488] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C12.dat
[17:48:09.488] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C13.dat
[17:48:09.488] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C14.dat
[17:48:09.488] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C15.dat
[17:48:09.488] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C0.dat
[17:48:09.496] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C1.dat
[17:48:09.502] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C2.dat
[17:48:09.508] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C3.dat
[17:48:09.514] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C4.dat
[17:48:09.520] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C5.dat
[17:48:09.527] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C6.dat
[17:48:09.533] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C7.dat
[17:48:09.539] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C8.dat
[17:48:09.546] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C9.dat
[17:48:09.552] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C10.dat
[17:48:09.558] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C11.dat
[17:48:09.563] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C12.dat
[17:48:09.568] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C13.dat
[17:48:09.573] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C14.dat
[17:48:09.578] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1130_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C15.dat
[17:48:09.583] <TB3> INFO: PixTestTrim80::trimTest() done
[17:48:09.583] <TB3> INFO: vtrim: 105 105 101 106 104 110 101 111 94 111 90 99 94 99 85 114
[17:48:09.583] <TB3> INFO: vthrcomp: 78 79 75 77 78 76 78 99 79 78 80 82 84 72 70 76
[17:48:09.583] <TB3> INFO: vcal mean: 79.95 79.93 79.97 79.91 79.94 79.97 79.97 79.89 79.94 79.95 79.91 79.96 79.96 79.92 79.92 79.96
[17:48:09.583] <TB3> INFO: vcal RMS: 0.70 1.45 0.72 0.74 0.76 0.67 0.73 0.77 0.73 0.71 1.44 0.72 0.74 0.70 0.73 0.82
[17:48:09.583] <TB3> INFO: bits mean: 9.02 8.93 8.98 9.37 9.30 9.33 8.65 9.67 9.55 9.26 9.59 10.03 10.20 9.89 10.28 9.45
[17:48:09.583] <TB3> INFO: bits RMS: 2.39 2.45 2.37 2.27 2.31 2.18 2.47 2.62 2.21 2.32 2.62 2.39 2.40 2.16 2.61 2.14
[17:48:09.590] <TB3> INFO: ----------------------------------------------------------------------
[17:48:09.590] <TB3> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[17:48:09.590] <TB3> INFO: ----------------------------------------------------------------------
[17:48:09.594] <TB3> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[17:48:09.607] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[17:48:09.607] <TB3> INFO: run 1 of 1
[17:48:09.846] <TB3> INFO: Expecting 4160000 events.
[17:48:43.223] <TB3> INFO: 781635 events read in total (32786ms).
[17:49:14.860] <TB3> INFO: 1553975 events read in total (64423ms).
[17:49:46.879] <TB3> INFO: 2320235 events read in total (96442ms).
[17:50:19.026] <TB3> INFO: 3083920 events read in total (128589ms).
[17:50:51.514] <TB3> INFO: 3843275 events read in total (161077ms).
[17:51:04.984] <TB3> INFO: 4160000 events read in total (174547ms).
[17:51:05.064] <TB3> INFO: Test took 175456ms.
[17:51:28.753] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 224 (-1/-1) hits flags = 528 (plus default)
[17:51:28.770] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[17:51:28.770] <TB3> INFO: run 1 of 1
[17:51:29.007] <TB3> INFO: Expecting 4680000 events.
[17:52:01.204] <TB3> INFO: 720935 events read in total (31605ms).
[17:52:32.626] <TB3> INFO: 1436315 events read in total (63027ms).
[17:53:03.541] <TB3> INFO: 2148960 events read in total (93942ms).
[17:53:34.644] <TB3> INFO: 2857560 events read in total (125045ms).
[17:54:05.767] <TB3> INFO: 3566025 events read in total (156168ms).
[17:54:36.704] <TB3> INFO: 4270920 events read in total (187105ms).
[17:54:54.956] <TB3> INFO: 4680000 events read in total (205357ms).
[17:54:55.090] <TB3> INFO: Test took 206320ms.
[17:55:24.545] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 231 (-1/-1) hits flags = 528 (plus default)
[17:55:24.560] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[17:55:24.560] <TB3> INFO: run 1 of 1
[17:55:24.796] <TB3> INFO: Expecting 4825600 events.
[17:55:56.446] <TB3> INFO: 713610 events read in total (31058ms).
[17:56:27.306] <TB3> INFO: 1422350 events read in total (61918ms).
[17:56:58.395] <TB3> INFO: 2128345 events read in total (93007ms).
[17:57:29.291] <TB3> INFO: 2830555 events read in total (123903ms).
[17:58:00.310] <TB3> INFO: 3532710 events read in total (154922ms).
[17:58:31.014] <TB3> INFO: 4231505 events read in total (185626ms).
[17:58:57.944] <TB3> INFO: 4825600 events read in total (212557ms).
[17:58:58.092] <TB3> INFO: Test took 213532ms.
[17:59:31.367] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 237 (-1/-1) hits flags = 528 (plus default)
[17:59:31.381] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[17:59:31.381] <TB3> INFO: run 1 of 1
[17:59:31.713] <TB3> INFO: Expecting 4950400 events.
[18:00:01.866] <TB3> INFO: 708215 events read in total (29561ms).
[18:00:31.486] <TB3> INFO: 1411405 events read in total (59181ms).
[18:01:02.189] <TB3> INFO: 2112365 events read in total (89884ms).
[18:01:32.709] <TB3> INFO: 2809770 events read in total (120404ms).
[18:02:02.880] <TB3> INFO: 3506205 events read in total (150575ms).
[18:02:33.497] <TB3> INFO: 4201860 events read in total (181192ms).
[18:03:02.873] <TB3> INFO: 4897225 events read in total (210568ms).
[18:03:05.491] <TB3> INFO: 4950400 events read in total (213186ms).
[18:03:05.570] <TB3> INFO: Test took 214188ms.
[18:03:30.895] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[18:03:30.907] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[18:03:30.907] <TB3> INFO: run 1 of 1
[18:03:31.146] <TB3> INFO: Expecting 5324800 events.
[18:04:01.308] <TB3> INFO: 693240 events read in total (29570ms).
[18:04:31.513] <TB3> INFO: 1382160 events read in total (59775ms).
[18:05:01.655] <TB3> INFO: 2068640 events read in total (89917ms).
[18:05:31.665] <TB3> INFO: 2752510 events read in total (119927ms).
[18:06:01.165] <TB3> INFO: 3434775 events read in total (149427ms).
[18:06:30.441] <TB3> INFO: 4117760 events read in total (178703ms).
[18:07:00.920] <TB3> INFO: 4796915 events read in total (209182ms).
[18:07:24.290] <TB3> INFO: 5324800 events read in total (232552ms).
[18:07:24.453] <TB3> INFO: Test took 233546ms.
[18:07:50.962] <TB3> INFO: PixTestTrim80::trimBitTest() done
[18:07:50.963] <TB3> INFO: PixTestTrim80::doTest() done, duration: 2625 seconds
[18:07:51.589] <TB3> INFO: enter test to run
[18:07:51.589] <TB3> INFO: test: exit no parameter change
[18:07:51.776] <TB3> QUIET: Connection to board 126 closed.
[18:07:51.777] <TB3> INFO: pXar: this is the end, my friend