[14:19:56.559] <TB2> INFO: *** Welcome to pxar ***
[14:19:56.559] <TB2> INFO: *** Today: 2016/11/07
[14:19:56.565] <TB2> INFO: *** Version: c8ba-dirty
[14:19:56.565] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C15.dat
[14:19:56.566] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C1b.dat
[14:19:56.566] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//defaultMaskFile.dat
[14:19:56.566] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters_C15.dat
[14:19:56.641] <TB2> INFO: clk: 4
[14:19:56.641] <TB2> INFO: ctr: 4
[14:19:56.641] <TB2> INFO: sda: 19
[14:19:56.641] <TB2> INFO: tin: 9
[14:19:56.641] <TB2> INFO: level: 15
[14:19:56.641] <TB2> INFO: triggerdelay: 0
[14:19:56.641] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[14:19:56.641] <TB2> INFO: Log level: INFO
[14:19:56.650] <TB2> INFO: Found DTB DTB_WWXUD2
[14:19:56.657] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[14:19:56.659] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[14:19:56.663] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[14:19:58.158] <TB2> INFO: DUT info:
[14:19:58.158] <TB2> INFO: The DUT currently contains the following objects:
[14:19:58.158] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[14:19:58.158] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:19:58.158] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:19:58.158] <TB2> INFO: TBM Core alpha (2): 7 registers set
[14:19:58.158] <TB2> INFO: TBM Core beta (3): 7 registers set
[14:19:58.158] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[14:19:58.158] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.158] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.158] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.158] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.158] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.158] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.159] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.159] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.159] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.159] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.159] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.159] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.159] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.159] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.159] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.159] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:58.559] <TB2> INFO: enter 'restricted' command line mode
[14:19:58.559] <TB2> INFO: enter test to run
[14:19:58.560] <TB2> INFO: test: pretest no parameter change
[14:19:58.560] <TB2> INFO: running: pretest
[14:19:58.565] <TB2> INFO: ######################################################################
[14:19:58.565] <TB2> INFO: PixTestPretest::doTest()
[14:19:58.565] <TB2> INFO: ######################################################################
[14:19:58.566] <TB2> INFO: ----------------------------------------------------------------------
[14:19:58.566] <TB2> INFO: PixTestPretest::programROC()
[14:19:58.566] <TB2> INFO: ----------------------------------------------------------------------
[14:20:16.581] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[14:20:16.581] <TB2> INFO: IA differences per ROC: 18.5 19.3 19.3 20.9 19.3 16.9 20.1 22.5 20.1 19.3 18.5 20.9 17.7 19.3 19.3 17.7
[14:20:16.645] <TB2> INFO: ----------------------------------------------------------------------
[14:20:16.645] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[14:20:16.645] <TB2> INFO: ----------------------------------------------------------------------
[14:20:37.946] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 384.3 mA = 24.0187 mA/ROC
[14:20:37.946] <TB2> INFO: i(loss) [mA/ROC]: 20.9 19.3 19.3 20.1 19.3 19.3 20.1 20.1 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3
[14:20:37.979] <TB2> INFO: ----------------------------------------------------------------------
[14:20:37.980] <TB2> INFO: PixTestPretest::findTiming()
[14:20:37.980] <TB2> INFO: ----------------------------------------------------------------------
[14:20:37.980] <TB2> INFO: PixTestCmd::init()

[14:21:10.025] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 7, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[14:21:10.025] <TB2> INFO: (success/tries = 100/100), width = 3
[14:21:11.531] <TB2> INFO: ----------------------------------------------------------------------
[14:21:11.531] <TB2> INFO: PixTestPretest::findWorkingPixel()
[14:21:11.531] <TB2> INFO: ----------------------------------------------------------------------
[14:21:11.625] <TB2> INFO: Expecting 231680 events.
[14:21:21.533] <TB2> INFO: 231680 events read in total (9315ms).
[14:21:21.541] <TB2> INFO: Test took 10006ms.
[14:21:21.798] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[14:21:21.831] <TB2> INFO: ----------------------------------------------------------------------
[14:21:21.831] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[14:21:21.831] <TB2> INFO: ----------------------------------------------------------------------
[14:21:21.926] <TB2> INFO: Expecting 231680 events.
[14:21:31.760] <TB2> INFO: 231680 events read in total (9242ms).
[14:21:31.771] <TB2> INFO: Test took 9934ms.
[14:21:32.045] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[14:21:32.045] <TB2> INFO: CalDel: 102 112 109 96 103 87 102 108 97 105 101 103 95 103 109 102
[14:21:32.045] <TB2> INFO: VthrComp: 53 51 51 51 51 51 51 51 55 55 53 51 51 51 51 52
[14:21:32.048] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C0.dat
[14:21:32.048] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C1.dat
[14:21:32.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C2.dat
[14:21:32.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C3.dat
[14:21:32.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C4.dat
[14:21:32.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C5.dat
[14:21:32.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C6.dat
[14:21:32.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C7.dat
[14:21:32.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C8.dat
[14:21:32.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C9.dat
[14:21:32.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C10.dat
[14:21:32.050] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C11.dat
[14:21:32.050] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C12.dat
[14:21:32.050] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C13.dat
[14:21:32.050] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C14.dat
[14:21:32.050] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C15.dat
[14:21:32.050] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C0a.dat
[14:21:32.050] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C0b.dat
[14:21:32.050] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C1a.dat
[14:21:32.050] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C1b.dat
[14:21:32.050] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[14:21:32.103] <TB2> INFO: enter test to run
[14:21:32.103] <TB2> INFO: test: FullTest no parameter change
[14:21:32.103] <TB2> INFO: running: fulltest
[14:21:32.103] <TB2> INFO: ######################################################################
[14:21:32.103] <TB2> INFO: PixTestFullTest::doTest()
[14:21:32.103] <TB2> INFO: ######################################################################
[14:21:32.104] <TB2> INFO: ######################################################################
[14:21:32.104] <TB2> INFO: PixTestAlive::doTest()
[14:21:32.104] <TB2> INFO: ######################################################################
[14:21:32.106] <TB2> INFO: ----------------------------------------------------------------------
[14:21:32.106] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:21:32.106] <TB2> INFO: ----------------------------------------------------------------------
[14:21:32.348] <TB2> INFO: Expecting 41600 events.
[14:21:35.884] <TB2> INFO: 41600 events read in total (2944ms).
[14:21:35.885] <TB2> INFO: Test took 3778ms.
[14:21:36.117] <TB2> INFO: PixTestAlive::aliveTest() done
[14:21:36.117] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:21:36.119] <TB2> INFO: ----------------------------------------------------------------------
[14:21:36.119] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:21:36.119] <TB2> INFO: ----------------------------------------------------------------------
[14:21:36.363] <TB2> INFO: Expecting 41600 events.
[14:21:39.362] <TB2> INFO: 41600 events read in total (2407ms).
[14:21:39.363] <TB2> INFO: Test took 3242ms.
[14:21:39.363] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[14:21:39.602] <TB2> INFO: PixTestAlive::maskTest() done
[14:21:39.602] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:21:39.603] <TB2> INFO: ----------------------------------------------------------------------
[14:21:39.603] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:21:39.603] <TB2> INFO: ----------------------------------------------------------------------
[14:21:39.849] <TB2> INFO: Expecting 41600 events.
[14:21:43.356] <TB2> INFO: 41600 events read in total (2915ms).
[14:21:43.356] <TB2> INFO: Test took 3751ms.
[14:21:43.590] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[14:21:43.591] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:21:43.591] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[14:21:43.591] <TB2> INFO: Decoding statistics:
[14:21:43.591] <TB2> INFO: General information:
[14:21:43.591] <TB2> INFO: 16bit words read: 0
[14:21:43.591] <TB2> INFO: valid events total: 0
[14:21:43.591] <TB2> INFO: empty events: 0
[14:21:43.591] <TB2> INFO: valid events with pixels: 0
[14:21:43.591] <TB2> INFO: valid pixel hits: 0
[14:21:43.591] <TB2> INFO: Event errors: 0
[14:21:43.591] <TB2> INFO: start marker: 0
[14:21:43.591] <TB2> INFO: stop marker: 0
[14:21:43.591] <TB2> INFO: overflow: 0
[14:21:43.591] <TB2> INFO: invalid 5bit words: 0
[14:21:43.591] <TB2> INFO: invalid XOR eye diagram: 0
[14:21:43.591] <TB2> INFO: frame (failed synchr.): 0
[14:21:43.591] <TB2> INFO: idle data (no TBM trl): 0
[14:21:43.591] <TB2> INFO: no data (only TBM hdr): 0
[14:21:43.591] <TB2> INFO: TBM errors: 0
[14:21:43.591] <TB2> INFO: flawed TBM headers: 0
[14:21:43.591] <TB2> INFO: flawed TBM trailers: 0
[14:21:43.591] <TB2> INFO: event ID mismatches: 0
[14:21:43.591] <TB2> INFO: ROC errors: 0
[14:21:43.591] <TB2> INFO: missing ROC header(s): 0
[14:21:43.592] <TB2> INFO: misplaced readback start: 0
[14:21:43.592] <TB2> INFO: Pixel decoding errors: 0
[14:21:43.592] <TB2> INFO: pixel data incomplete: 0
[14:21:43.592] <TB2> INFO: pixel address: 0
[14:21:43.592] <TB2> INFO: pulse height fill bit: 0
[14:21:43.592] <TB2> INFO: buffer corruption: 0
[14:21:43.601] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C15.dat
[14:21:43.602] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[14:21:43.602] <TB2> INFO: ######################################################################
[14:21:43.602] <TB2> INFO: PixTestReadback::doTest()
[14:21:43.602] <TB2> INFO: ######################################################################
[14:21:43.602] <TB2> INFO: ----------------------------------------------------------------------
[14:21:43.602] <TB2> INFO: PixTestReadback::CalibrateVd()
[14:21:43.602] <TB2> INFO: ----------------------------------------------------------------------
[14:21:53.569] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C0.dat
[14:21:53.570] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C1.dat
[14:21:53.570] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C2.dat
[14:21:53.570] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C3.dat
[14:21:53.570] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C4.dat
[14:21:53.570] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C5.dat
[14:21:53.570] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C6.dat
[14:21:53.570] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C7.dat
[14:21:53.570] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C8.dat
[14:21:53.570] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C9.dat
[14:21:53.570] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C10.dat
[14:21:53.570] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C11.dat
[14:21:53.570] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C12.dat
[14:21:53.571] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C13.dat
[14:21:53.571] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C14.dat
[14:21:53.571] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C15.dat
[14:21:53.599] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:21:53.599] <TB2> INFO: ----------------------------------------------------------------------
[14:21:53.599] <TB2> INFO: PixTestReadback::CalibrateVa()
[14:21:53.599] <TB2> INFO: ----------------------------------------------------------------------
[14:22:03.545] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C0.dat
[14:22:03.545] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C1.dat
[14:22:03.545] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C2.dat
[14:22:03.546] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C3.dat
[14:22:03.546] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C4.dat
[14:22:03.546] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C5.dat
[14:22:03.546] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C6.dat
[14:22:03.546] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C7.dat
[14:22:03.546] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C8.dat
[14:22:03.546] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C9.dat
[14:22:03.546] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C10.dat
[14:22:03.546] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C11.dat
[14:22:03.546] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C12.dat
[14:22:03.546] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C13.dat
[14:22:03.546] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C14.dat
[14:22:03.546] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C15.dat
[14:22:03.575] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:22:03.575] <TB2> INFO: ----------------------------------------------------------------------
[14:22:03.575] <TB2> INFO: PixTestReadback::readbackVbg()
[14:22:03.575] <TB2> INFO: ----------------------------------------------------------------------
[14:22:11.262] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:22:11.262] <TB2> INFO: ----------------------------------------------------------------------
[14:22:11.262] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[14:22:11.262] <TB2> INFO: ----------------------------------------------------------------------
[14:22:11.262] <TB2> INFO: Vbg will be calibrated using Vd calibration
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 158.6calibrated Vbg = 1.18812 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 147.2calibrated Vbg = 1.18552 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 154.3calibrated Vbg = 1.17555 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 154.8calibrated Vbg = 1.17714 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 155.5calibrated Vbg = 1.17512 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 160.3calibrated Vbg = 1.18429 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 152.3calibrated Vbg = 1.18289 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 152.9calibrated Vbg = 1.18088 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 165.7calibrated Vbg = 1.17299 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 159.1calibrated Vbg = 1.17721 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 161.1calibrated Vbg = 1.16633 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 160.1calibrated Vbg = 1.17069 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 150calibrated Vbg = 1.17086 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 158.9calibrated Vbg = 1.17244 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 159.5calibrated Vbg = 1.17436 :::*/*/*/*/
[14:22:11.262] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 166.6calibrated Vbg = 1.17637 :::*/*/*/*/
[14:22:11.265] <TB2> INFO: ----------------------------------------------------------------------
[14:22:11.265] <TB2> INFO: PixTestReadback::CalibrateIa()
[14:22:11.265] <TB2> INFO: ----------------------------------------------------------------------
[14:24:52.139] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C0.dat
[14:24:52.139] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C1.dat
[14:24:52.139] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C2.dat
[14:24:52.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C3.dat
[14:24:52.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C4.dat
[14:24:52.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C5.dat
[14:24:52.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C6.dat
[14:24:52.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C7.dat
[14:24:52.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C8.dat
[14:24:52.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C9.dat
[14:24:52.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C10.dat
[14:24:52.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C11.dat
[14:24:52.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C12.dat
[14:24:52.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C13.dat
[14:24:52.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C14.dat
[14:24:52.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C15.dat
[14:24:52.168] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:24:52.169] <TB2> INFO: PixTestReadback::doTest() done
[14:24:52.170] <TB2> INFO: Decoding statistics:
[14:24:52.170] <TB2> INFO: General information:
[14:24:52.170] <TB2> INFO: 16bit words read: 1536
[14:24:52.170] <TB2> INFO: valid events total: 256
[14:24:52.170] <TB2> INFO: empty events: 256
[14:24:52.170] <TB2> INFO: valid events with pixels: 0
[14:24:52.170] <TB2> INFO: valid pixel hits: 0
[14:24:52.170] <TB2> INFO: Event errors: 0
[14:24:52.170] <TB2> INFO: start marker: 0
[14:24:52.170] <TB2> INFO: stop marker: 0
[14:24:52.170] <TB2> INFO: overflow: 0
[14:24:52.170] <TB2> INFO: invalid 5bit words: 0
[14:24:52.170] <TB2> INFO: invalid XOR eye diagram: 0
[14:24:52.170] <TB2> INFO: frame (failed synchr.): 0
[14:24:52.170] <TB2> INFO: idle data (no TBM trl): 0
[14:24:52.170] <TB2> INFO: no data (only TBM hdr): 0
[14:24:52.170] <TB2> INFO: TBM errors: 0
[14:24:52.170] <TB2> INFO: flawed TBM headers: 0
[14:24:52.170] <TB2> INFO: flawed TBM trailers: 0
[14:24:52.170] <TB2> INFO: event ID mismatches: 0
[14:24:52.170] <TB2> INFO: ROC errors: 0
[14:24:52.170] <TB2> INFO: missing ROC header(s): 0
[14:24:52.170] <TB2> INFO: misplaced readback start: 0
[14:24:52.170] <TB2> INFO: Pixel decoding errors: 0
[14:24:52.170] <TB2> INFO: pixel data incomplete: 0
[14:24:52.170] <TB2> INFO: pixel address: 0
[14:24:52.170] <TB2> INFO: pulse height fill bit: 0
[14:24:52.170] <TB2> INFO: buffer corruption: 0
[14:24:52.217] <TB2> INFO: ######################################################################
[14:24:52.217] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[14:24:52.217] <TB2> INFO: ######################################################################
[14:24:52.220] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[14:24:52.248] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:24:52.248] <TB2> INFO: run 1 of 1
[14:24:52.532] <TB2> INFO: Expecting 3120000 events.
[14:25:23.120] <TB2> INFO: 662125 events read in total (29996ms).











[14:25:53.416] <TB2> INFO: 1326980 events read in total (60292ms).











[14:26:23.790] <TB2> INFO: 1991225 events read in total (90666ms).











[14:26:54.144] <TB2> INFO: 2655580 events read in total (121020ms).











[14:27:15.104] <TB2> INFO: 3120000 events read in total (141980ms).
[14:27:15.209] <TB2> INFO: Test took 142961ms.
[14:27:39.281] <TB2> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 167 seconds
[14:27:39.281] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
[14:27:39.281] <TB2> INFO: separation cut (per ROC): 117 109 106 120 132 105 131 108 116 112 109 116 109 105 108 114
[14:27:39.281] <TB2> INFO: Decoding statistics:
[14:27:39.281] <TB2> INFO: General information:
[14:27:39.281] <TB2> INFO: 16bit words read: 0
[14:27:39.281] <TB2> INFO: valid events total: 0
[14:27:39.281] <TB2> INFO: empty events: 0
[14:27:39.281] <TB2> INFO: valid events with pixels: 0
[14:27:39.281] <TB2> INFO: valid pixel hits: 0
[14:27:39.281] <TB2> INFO: Event errors: 0
[14:27:39.281] <TB2> INFO: start marker: 0
[14:27:39.281] <TB2> INFO: stop marker: 0
[14:27:39.281] <TB2> INFO: overflow: 0
[14:27:39.281] <TB2> INFO: invalid 5bit words: 0
[14:27:39.281] <TB2> INFO: invalid XOR eye diagram: 0
[14:27:39.281] <TB2> INFO: frame (failed synchr.): 0
[14:27:39.281] <TB2> INFO: idle data (no TBM trl): 0
[14:27:39.281] <TB2> INFO: no data (only TBM hdr): 0
[14:27:39.281] <TB2> INFO: TBM errors: 0
[14:27:39.281] <TB2> INFO: flawed TBM headers: 0
[14:27:39.281] <TB2> INFO: flawed TBM trailers: 0
[14:27:39.281] <TB2> INFO: event ID mismatches: 0
[14:27:39.281] <TB2> INFO: ROC errors: 0
[14:27:39.281] <TB2> INFO: missing ROC header(s): 0
[14:27:39.281] <TB2> INFO: misplaced readback start: 0
[14:27:39.281] <TB2> INFO: Pixel decoding errors: 0
[14:27:39.281] <TB2> INFO: pixel data incomplete: 0
[14:27:39.281] <TB2> INFO: pixel address: 0
[14:27:39.281] <TB2> INFO: pulse height fill bit: 0
[14:27:39.281] <TB2> INFO: buffer corruption: 0
[14:27:39.318] <TB2> INFO: ######################################################################
[14:27:39.318] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:27:39.318] <TB2> INFO: ######################################################################
[14:27:39.318] <TB2> INFO: ----------------------------------------------------------------------
[14:27:39.318] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:27:39.318] <TB2> INFO: ----------------------------------------------------------------------
[14:27:39.319] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[14:27:39.336] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[14:27:39.336] <TB2> INFO: run 1 of 1
[14:27:39.574] <TB2> INFO: Expecting 36608000 events.
[14:28:03.661] <TB2> INFO: 677600 events read in total (23495ms).
[14:28:27.345] <TB2> INFO: 1346400 events read in total (47179ms).
[14:28:50.413] <TB2> INFO: 2013700 events read in total (70247ms).
[14:29:15.013] <TB2> INFO: 2681400 events read in total (94847ms).
[14:29:38.760] <TB2> INFO: 3348000 events read in total (118594ms).
[14:30:01.742] <TB2> INFO: 4014200 events read in total (141576ms).
[14:30:25.184] <TB2> INFO: 4679250 events read in total (165018ms).
[14:30:48.400] <TB2> INFO: 5344900 events read in total (188234ms).
[14:31:11.334] <TB2> INFO: 6010250 events read in total (211168ms).
[14:31:35.014] <TB2> INFO: 6676650 events read in total (234848ms).
[14:31:58.290] <TB2> INFO: 7343900 events read in total (258124ms).
[14:32:21.327] <TB2> INFO: 8009700 events read in total (281161ms).
[14:32:44.724] <TB2> INFO: 8674650 events read in total (304558ms).
[14:33:07.919] <TB2> INFO: 9339250 events read in total (327753ms).
[14:33:31.278] <TB2> INFO: 10005200 events read in total (351112ms).
[14:33:54.624] <TB2> INFO: 10671450 events read in total (374458ms).
[14:34:17.810] <TB2> INFO: 11338050 events read in total (397645ms).
[14:34:41.090] <TB2> INFO: 12002650 events read in total (420924ms).
[14:35:04.277] <TB2> INFO: 12669000 events read in total (444111ms).
[14:35:27.452] <TB2> INFO: 13331200 events read in total (467286ms).
[14:35:50.408] <TB2> INFO: 13994550 events read in total (490242ms).
[14:36:13.274] <TB2> INFO: 14657100 events read in total (513108ms).
[14:36:36.395] <TB2> INFO: 15319500 events read in total (536229ms).
[14:36:59.227] <TB2> INFO: 15981400 events read in total (559061ms).
[14:37:22.040] <TB2> INFO: 16644800 events read in total (581874ms).
[14:37:45.243] <TB2> INFO: 17307600 events read in total (605077ms).
[14:38:08.139] <TB2> INFO: 17970750 events read in total (627973ms).
[14:38:30.794] <TB2> INFO: 18632850 events read in total (650628ms).
[14:38:53.803] <TB2> INFO: 19292750 events read in total (673637ms).
[14:39:16.636] <TB2> INFO: 19954600 events read in total (696470ms).
[14:39:39.574] <TB2> INFO: 20615300 events read in total (719408ms).
[14:40:02.276] <TB2> INFO: 21275600 events read in total (742110ms).
[14:40:25.111] <TB2> INFO: 21934850 events read in total (764946ms).
[14:40:47.695] <TB2> INFO: 22593000 events read in total (787529ms).
[14:41:10.261] <TB2> INFO: 23249400 events read in total (810095ms).
[14:41:33.154] <TB2> INFO: 23908500 events read in total (832988ms).
[14:41:55.925] <TB2> INFO: 24567100 events read in total (855759ms).
[14:42:18.654] <TB2> INFO: 25227750 events read in total (878488ms).
[14:42:41.179] <TB2> INFO: 25886900 events read in total (901013ms).
[14:43:03.918] <TB2> INFO: 26545950 events read in total (923752ms).
[14:43:26.621] <TB2> INFO: 27205450 events read in total (946455ms).
[14:43:49.234] <TB2> INFO: 27865050 events read in total (969068ms).
[14:44:11.681] <TB2> INFO: 28524550 events read in total (991515ms).
[14:44:34.504] <TB2> INFO: 29183000 events read in total (1014338ms).
[14:44:57.279] <TB2> INFO: 29840250 events read in total (1037113ms).
[14:45:19.798] <TB2> INFO: 30499400 events read in total (1059632ms).
[14:45:42.402] <TB2> INFO: 31158000 events read in total (1082236ms).
[14:46:05.094] <TB2> INFO: 31817850 events read in total (1104928ms).
[14:46:27.592] <TB2> INFO: 32478350 events read in total (1127426ms).
[14:46:50.415] <TB2> INFO: 33136350 events read in total (1150249ms).
[14:47:13.231] <TB2> INFO: 33796850 events read in total (1173065ms).
[14:47:35.832] <TB2> INFO: 34456100 events read in total (1195666ms).
[14:47:58.556] <TB2> INFO: 35117000 events read in total (1218390ms).
[14:48:21.129] <TB2> INFO: 35779200 events read in total (1240963ms).
[14:48:43.914] <TB2> INFO: 36451350 events read in total (1263748ms).
[14:48:49.293] <TB2> INFO: 36608000 events read in total (1269127ms).
[14:48:49.387] <TB2> INFO: Test took 1270050ms.
[14:48:49.812] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:48:51.384] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:48:53.009] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:48:55.451] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:48:57.932] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:48:59.806] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:49:01.695] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:49:03.203] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:49:04.760] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:49:06.249] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:49:07.791] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:49:09.321] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:49:11.229] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:49:13.299] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:49:15.420] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:49:17.535] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:49:19.521] <TB2> INFO: PixTestScurves::scurves() done
[14:49:19.521] <TB2> INFO: Vcal mean: 125.85 112.55 115.05 119.51 121.75 113.78 112.95 109.71 126.18 123.39 120.48 118.99 115.99 118.10 117.72 115.34
[14:49:19.521] <TB2> INFO: Vcal RMS: 5.94 5.65 5.70 5.75 5.72 5.05 4.81 5.36 6.26 6.74 6.52 6.41 5.71 5.47 6.24 5.47
[14:49:19.521] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1300 seconds
[14:49:19.521] <TB2> INFO: Decoding statistics:
[14:49:19.521] <TB2> INFO: General information:
[14:49:19.521] <TB2> INFO: 16bit words read: 0
[14:49:19.521] <TB2> INFO: valid events total: 0
[14:49:19.521] <TB2> INFO: empty events: 0
[14:49:19.521] <TB2> INFO: valid events with pixels: 0
[14:49:19.521] <TB2> INFO: valid pixel hits: 0
[14:49:19.521] <TB2> INFO: Event errors: 0
[14:49:19.521] <TB2> INFO: start marker: 0
[14:49:19.521] <TB2> INFO: stop marker: 0
[14:49:19.521] <TB2> INFO: overflow: 0
[14:49:19.521] <TB2> INFO: invalid 5bit words: 0
[14:49:19.521] <TB2> INFO: invalid XOR eye diagram: 0
[14:49:19.521] <TB2> INFO: frame (failed synchr.): 0
[14:49:19.521] <TB2> INFO: idle data (no TBM trl): 0
[14:49:19.521] <TB2> INFO: no data (only TBM hdr): 0
[14:49:19.521] <TB2> INFO: TBM errors: 0
[14:49:19.521] <TB2> INFO: flawed TBM headers: 0
[14:49:19.521] <TB2> INFO: flawed TBM trailers: 0
[14:49:19.521] <TB2> INFO: event ID mismatches: 0
[14:49:19.521] <TB2> INFO: ROC errors: 0
[14:49:19.521] <TB2> INFO: missing ROC header(s): 0
[14:49:19.521] <TB2> INFO: misplaced readback start: 0
[14:49:19.521] <TB2> INFO: Pixel decoding errors: 0
[14:49:19.521] <TB2> INFO: pixel data incomplete: 0
[14:49:19.521] <TB2> INFO: pixel address: 0
[14:49:19.521] <TB2> INFO: pulse height fill bit: 0
[14:49:19.521] <TB2> INFO: buffer corruption: 0
[14:49:19.618] <TB2> INFO: ######################################################################
[14:49:19.618] <TB2> INFO: PixTestTrim::doTest()
[14:49:19.618] <TB2> INFO: ######################################################################
[14:49:19.619] <TB2> INFO: ----------------------------------------------------------------------
[14:49:19.619] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[14:49:19.619] <TB2> INFO: ----------------------------------------------------------------------
[14:49:19.697] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:49:19.697] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:49:19.712] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:49:19.712] <TB2> INFO: run 1 of 1
[14:49:20.043] <TB2> INFO: Expecting 5025280 events.
[14:49:50.594] <TB2> INFO: 825424 events read in total (29945ms).
[14:50:20.353] <TB2> INFO: 1648936 events read in total (59704ms).
[14:50:50.454] <TB2> INFO: 2468872 events read in total (89805ms).
[14:51:20.473] <TB2> INFO: 3284984 events read in total (119824ms).
[14:51:50.793] <TB2> INFO: 4098696 events read in total (150145ms).
[14:52:20.607] <TB2> INFO: 4912024 events read in total (179958ms).
[14:52:25.222] <TB2> INFO: 5025280 events read in total (184573ms).
[14:52:25.278] <TB2> INFO: Test took 185566ms.
[14:52:45.299] <TB2> INFO: ROC 0 VthrComp = 128
[14:52:45.300] <TB2> INFO: ROC 1 VthrComp = 111
[14:52:45.300] <TB2> INFO: ROC 2 VthrComp = 118
[14:52:45.300] <TB2> INFO: ROC 3 VthrComp = 129
[14:52:45.300] <TB2> INFO: ROC 4 VthrComp = 123
[14:52:45.300] <TB2> INFO: ROC 5 VthrComp = 112
[14:52:45.300] <TB2> INFO: ROC 6 VthrComp = 118
[14:52:45.301] <TB2> INFO: ROC 7 VthrComp = 116
[14:52:45.301] <TB2> INFO: ROC 8 VthrComp = 132
[14:52:45.301] <TB2> INFO: ROC 9 VthrComp = 126
[14:52:45.302] <TB2> INFO: ROC 10 VthrComp = 117
[14:52:45.302] <TB2> INFO: ROC 11 VthrComp = 116
[14:52:45.302] <TB2> INFO: ROC 12 VthrComp = 118
[14:52:45.302] <TB2> INFO: ROC 13 VthrComp = 122
[14:52:45.302] <TB2> INFO: ROC 14 VthrComp = 117
[14:52:45.302] <TB2> INFO: ROC 15 VthrComp = 117
[14:52:45.563] <TB2> INFO: Expecting 41600 events.
[14:52:49.201] <TB2> INFO: 41600 events read in total (3046ms).
[14:52:49.202] <TB2> INFO: Test took 3897ms.
[14:52:49.216] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:52:49.216] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:52:49.230] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:52:49.230] <TB2> INFO: run 1 of 1
[14:52:49.508] <TB2> INFO: Expecting 5025280 events.
[14:53:15.934] <TB2> INFO: 590264 events read in total (25834ms).
[14:53:41.710] <TB2> INFO: 1179712 events read in total (51610ms).
[14:54:07.449] <TB2> INFO: 1769488 events read in total (77349ms).
[14:54:33.512] <TB2> INFO: 2359096 events read in total (103412ms).
[14:54:59.130] <TB2> INFO: 2946192 events read in total (129030ms).
[14:55:24.993] <TB2> INFO: 3532768 events read in total (154893ms).
[14:55:50.574] <TB2> INFO: 4117952 events read in total (180474ms).
[14:56:16.169] <TB2> INFO: 4701728 events read in total (206069ms).
[14:56:30.674] <TB2> INFO: 5025280 events read in total (220574ms).
[14:56:30.792] <TB2> INFO: Test took 221562ms.
[14:56:56.732] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 61.93 for pixel 15/3 mean/min/max = 46.6124/30.9379/62.2868
[14:56:56.733] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 65.3475 for pixel 9/68 mean/min/max = 49.4086/33.369/65.4483
[14:56:56.733] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 62.5315 for pixel 4/3 mean/min/max = 47.1241/31.511/62.7372
[14:56:56.734] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 58.2378 for pixel 15/4 mean/min/max = 44.9071/31.4904/58.3238
[14:56:56.735] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 61.6607 for pixel 0/77 mean/min/max = 46.8462/31.909/61.7835
[14:56:56.735] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 60.3904 for pixel 43/15 mean/min/max = 46.5578/32.4733/60.6422
[14:56:56.736] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 58.9142 for pixel 51/0 mean/min/max = 45.6463/31.9008/59.3918
[14:56:56.737] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 59.725 for pixel 24/30 mean/min/max = 45.8925/31.9968/59.7882
[14:56:56.737] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 61.8242 for pixel 16/0 mean/min/max = 46.4519/30.7504/62.1535
[14:56:56.738] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 63.7693 for pixel 4/14 mean/min/max = 47.2764/30.6589/63.8938
[14:56:56.738] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 65.8982 for pixel 19/11 mean/min/max = 47.4812/28.8887/66.0738
[14:56:56.739] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 63.065 for pixel 25/79 mean/min/max = 47.373/31.6545/63.0915
[14:56:56.739] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 60.0602 for pixel 10/17 mean/min/max = 45.6939/31.1213/60.2665
[14:56:56.740] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 60.273 for pixel 11/24 mean/min/max = 45.701/31.0892/60.3129
[14:56:56.740] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 61.3144 for pixel 2/35 mean/min/max = 46.6823/31.8125/61.5521
[14:56:56.741] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 59.1882 for pixel 17/0 mean/min/max = 45.8902/32.4154/59.365
[14:56:56.741] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:56:56.830] <TB2> INFO: Expecting 411648 events.
[14:57:06.334] <TB2> INFO: 411648 events read in total (8913ms).
[14:57:06.342] <TB2> INFO: Expecting 411648 events.
[14:57:15.442] <TB2> INFO: 411648 events read in total (8697ms).
[14:57:15.452] <TB2> INFO: Expecting 411648 events.
[14:57:24.759] <TB2> INFO: 411648 events read in total (8904ms).
[14:57:24.776] <TB2> INFO: Expecting 411648 events.
[14:57:34.164] <TB2> INFO: 411648 events read in total (8985ms).
[14:57:34.180] <TB2> INFO: Expecting 411648 events.
[14:57:43.470] <TB2> INFO: 411648 events read in total (8887ms).
[14:57:43.490] <TB2> INFO: Expecting 411648 events.
[14:57:52.833] <TB2> INFO: 411648 events read in total (8940ms).
[14:57:52.854] <TB2> INFO: Expecting 411648 events.
[14:58:02.205] <TB2> INFO: 411648 events read in total (8947ms).
[14:58:02.235] <TB2> INFO: Expecting 411648 events.
[14:58:11.561] <TB2> INFO: 411648 events read in total (8923ms).
[14:58:11.589] <TB2> INFO: Expecting 411648 events.
[14:58:20.890] <TB2> INFO: 411648 events read in total (8898ms).
[14:58:20.918] <TB2> INFO: Expecting 411648 events.
[14:58:30.276] <TB2> INFO: 411648 events read in total (8955ms).
[14:58:30.308] <TB2> INFO: Expecting 411648 events.
[14:58:39.619] <TB2> INFO: 411648 events read in total (8908ms).
[14:58:39.654] <TB2> INFO: Expecting 411648 events.
[14:58:49.087] <TB2> INFO: 411648 events read in total (9030ms).
[14:58:49.135] <TB2> INFO: Expecting 411648 events.
[14:58:58.441] <TB2> INFO: 411648 events read in total (8903ms).
[14:58:58.481] <TB2> INFO: Expecting 411648 events.
[14:59:07.684] <TB2> INFO: 411648 events read in total (8799ms).
[14:59:07.735] <TB2> INFO: Expecting 411648 events.
[14:59:17.042] <TB2> INFO: 411648 events read in total (8904ms).
[14:59:17.135] <TB2> INFO: Expecting 411648 events.
[14:59:26.366] <TB2> INFO: 411648 events read in total (8827ms).
[14:59:26.446] <TB2> INFO: Test took 149705ms.
[14:59:27.179] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:59:27.194] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:59:27.194] <TB2> INFO: run 1 of 1
[14:59:27.444] <TB2> INFO: Expecting 5025280 events.
[14:59:54.062] <TB2> INFO: 591800 events read in total (26027ms).
[15:00:19.950] <TB2> INFO: 1179608 events read in total (51915ms).
[15:00:45.748] <TB2> INFO: 1766896 events read in total (77713ms).
[15:01:11.694] <TB2> INFO: 2353176 events read in total (103659ms).
[15:01:37.936] <TB2> INFO: 2941312 events read in total (129901ms).
[15:02:03.765] <TB2> INFO: 3529696 events read in total (155730ms).
[15:02:29.697] <TB2> INFO: 4119232 events read in total (181662ms).
[15:02:55.804] <TB2> INFO: 4709416 events read in total (207769ms).
[15:03:10.383] <TB2> INFO: 5025280 events read in total (222348ms).
[15:03:10.556] <TB2> INFO: Test took 223362ms.
[15:03:33.671] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 6.996329 .. 147.517598
[15:03:33.997] <TB2> INFO: Expecting 208000 events.
[15:03:43.926] <TB2> INFO: 208000 events read in total (9337ms).
[15:03:43.928] <TB2> INFO: Test took 10255ms.
[15:03:43.984] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 6 .. 157 (-1/-1) hits flags = 528 (plus default)
[15:03:43.997] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:03:43.997] <TB2> INFO: run 1 of 1
[15:03:44.283] <TB2> INFO: Expecting 5058560 events.
[15:04:10.513] <TB2> INFO: 577160 events read in total (25638ms).
[15:04:35.982] <TB2> INFO: 1154200 events read in total (51108ms).
[15:05:01.769] <TB2> INFO: 1731528 events read in total (76895ms).
[15:05:27.430] <TB2> INFO: 2308960 events read in total (102556ms).
[15:05:52.921] <TB2> INFO: 2885992 events read in total (128046ms).
[15:06:18.510] <TB2> INFO: 3462600 events read in total (153635ms).
[15:06:44.664] <TB2> INFO: 4039184 events read in total (179789ms).
[15:07:10.774] <TB2> INFO: 4615128 events read in total (205899ms).
[15:07:30.282] <TB2> INFO: 5058560 events read in total (225407ms).
[15:07:30.436] <TB2> INFO: Test took 226438ms.
[15:07:56.921] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.270003 .. 46.799893
[15:07:57.204] <TB2> INFO: Expecting 208000 events.
[15:08:07.625] <TB2> INFO: 208000 events read in total (9829ms).
[15:08:07.626] <TB2> INFO: Test took 10703ms.
[15:08:07.691] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[15:08:07.706] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:08:07.706] <TB2> INFO: run 1 of 1
[15:08:08.030] <TB2> INFO: Expecting 1331200 events.
[15:08:36.560] <TB2> INFO: 653984 events read in total (27938ms).
[15:09:04.399] <TB2> INFO: 1306832 events read in total (55778ms).
[15:09:05.898] <TB2> INFO: 1331200 events read in total (57277ms).
[15:09:05.932] <TB2> INFO: Test took 58226ms.
[15:09:20.844] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 25.607370 .. 47.123442
[15:09:21.170] <TB2> INFO: Expecting 208000 events.
[15:09:31.288] <TB2> INFO: 208000 events read in total (9526ms).
[15:09:31.289] <TB2> INFO: Test took 10443ms.
[15:09:31.356] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 57 (-1/-1) hits flags = 528 (plus default)
[15:09:31.370] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:09:31.370] <TB2> INFO: run 1 of 1
[15:09:31.648] <TB2> INFO: Expecting 1431040 events.
[15:10:00.082] <TB2> INFO: 659152 events read in total (27842ms).
[15:10:27.262] <TB2> INFO: 1317520 events read in total (55022ms).
[15:10:32.306] <TB2> INFO: 1431040 events read in total (60066ms).
[15:10:32.337] <TB2> INFO: Test took 60966ms.
[15:10:45.131] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 25.880447 .. 46.877560
[15:10:45.374] <TB2> INFO: Expecting 208000 events.
[15:10:55.635] <TB2> INFO: 208000 events read in total (9669ms).
[15:10:55.636] <TB2> INFO: Test took 10500ms.
[15:10:55.685] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 56 (-1/-1) hits flags = 528 (plus default)
[15:10:55.699] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:10:55.699] <TB2> INFO: run 1 of 1
[15:10:55.993] <TB2> INFO: Expecting 1397760 events.
[15:11:24.524] <TB2> INFO: 663024 events read in total (27939ms).
[15:11:53.360] <TB2> INFO: 1325832 events read in total (56775ms).
[15:11:56.947] <TB2> INFO: 1397760 events read in total (60362ms).
[15:11:56.977] <TB2> INFO: Test took 61278ms.
[15:12:10.931] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[15:12:10.931] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[15:12:10.944] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:12:10.944] <TB2> INFO: run 1 of 1
[15:12:11.203] <TB2> INFO: Expecting 1364480 events.
[15:12:39.538] <TB2> INFO: 667096 events read in total (27743ms).
[15:13:07.471] <TB2> INFO: 1333680 events read in total (55676ms).
[15:13:09.156] <TB2> INFO: 1364480 events read in total (57361ms).
[15:13:09.184] <TB2> INFO: Test took 58240ms.
[15:13:22.879] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C0.dat
[15:13:22.879] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C1.dat
[15:13:22.880] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C2.dat
[15:13:22.880] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C3.dat
[15:13:22.880] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C4.dat
[15:13:22.880] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C5.dat
[15:13:22.880] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C6.dat
[15:13:22.880] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C7.dat
[15:13:22.880] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C8.dat
[15:13:22.880] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C9.dat
[15:13:22.880] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C10.dat
[15:13:22.880] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C11.dat
[15:13:22.881] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C12.dat
[15:13:22.881] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C13.dat
[15:13:22.881] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C14.dat
[15:13:22.881] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C15.dat
[15:13:22.882] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C0.dat
[15:13:22.888] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C1.dat
[15:13:22.893] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C2.dat
[15:13:22.898] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C3.dat
[15:13:22.903] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C4.dat
[15:13:22.908] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C5.dat
[15:13:22.912] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C6.dat
[15:13:22.917] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C7.dat
[15:13:22.923] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C8.dat
[15:13:22.929] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C9.dat
[15:13:22.934] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C10.dat
[15:13:22.939] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C11.dat
[15:13:22.945] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C12.dat
[15:13:22.951] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C13.dat
[15:13:22.956] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C14.dat
[15:13:22.961] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C15.dat
[15:13:22.966] <TB2> INFO: PixTestTrim::trimTest() done
[15:13:22.966] <TB2> INFO: vtrim: 137 135 131 131 128 139 103 110 130 141 143 138 129 120 133 111
[15:13:22.966] <TB2> INFO: vthrcomp: 128 111 118 129 123 112 118 116 132 126 117 116 118 122 117 117
[15:13:22.966] <TB2> INFO: vcal mean: 35.05 34.98 35.04 34.96 34.96 34.98 35.01 34.91 35.00 35.04 35.21 34.96 34.95 34.93 34.99 34.99
[15:13:22.966] <TB2> INFO: vcal RMS: 1.27 1.04 1.16 1.04 1.07 1.05 1.02 0.96 1.17 1.37 1.42 1.10 1.15 1.11 1.04 0.99
[15:13:22.966] <TB2> INFO: bits mean: 9.63 8.73 9.73 10.03 8.79 9.65 8.85 9.78 9.92 9.73 10.07 9.22 9.68 9.84 9.51 9.14
[15:13:22.966] <TB2> INFO: bits RMS: 2.75 2.63 2.59 2.57 2.93 2.51 3.02 2.59 2.61 2.70 2.46 2.79 2.74 2.68 2.63 2.85
[15:13:22.974] <TB2> INFO: ----------------------------------------------------------------------
[15:13:22.974] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[15:13:22.974] <TB2> INFO: ----------------------------------------------------------------------
[15:13:22.977] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[15:13:22.989] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:13:22.990] <TB2> INFO: run 1 of 1
[15:13:23.234] <TB2> INFO: Expecting 4160000 events.
[15:13:55.728] <TB2> INFO: 749445 events read in total (31902ms).
[15:14:27.631] <TB2> INFO: 1495160 events read in total (63806ms).
[15:14:59.380] <TB2> INFO: 2235975 events read in total (95555ms).
[15:15:31.323] <TB2> INFO: 2972685 events read in total (127497ms).
[15:16:02.932] <TB2> INFO: 3708740 events read in total (159106ms).
[15:16:22.254] <TB2> INFO: 4160000 events read in total (178428ms).
[15:16:22.348] <TB2> INFO: Test took 179358ms.
[15:16:49.216] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[15:16:49.233] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:16:49.233] <TB2> INFO: run 1 of 1
[15:16:49.477] <TB2> INFO: Expecting 4284800 events.
[15:17:20.802] <TB2> INFO: 715640 events read in total (30734ms).
[15:17:51.612] <TB2> INFO: 1428560 events read in total (61544ms).
[15:18:22.238] <TB2> INFO: 2137940 events read in total (92170ms).
[15:18:53.278] <TB2> INFO: 2842645 events read in total (123210ms).
[15:19:24.006] <TB2> INFO: 3547020 events read in total (153938ms).
[15:19:55.149] <TB2> INFO: 4254085 events read in total (185081ms).
[15:19:56.833] <TB2> INFO: 4284800 events read in total (186765ms).
[15:19:56.911] <TB2> INFO: Test took 187678ms.
[15:20:27.250] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 188 (-1/-1) hits flags = 528 (plus default)
[15:20:27.264] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:20:27.264] <TB2> INFO: run 1 of 1
[15:20:27.589] <TB2> INFO: Expecting 3931200 events.
[15:20:59.609] <TB2> INFO: 738530 events read in total (31428ms).
[15:21:31.064] <TB2> INFO: 1473495 events read in total (62883ms).
[15:22:02.374] <TB2> INFO: 2203495 events read in total (94193ms).
[15:22:33.427] <TB2> INFO: 2928750 events read in total (125246ms).
[15:23:04.643] <TB2> INFO: 3654760 events read in total (156462ms).
[15:23:16.804] <TB2> INFO: 3931200 events read in total (168623ms).
[15:23:16.967] <TB2> INFO: Test took 169702ms.
[15:23:39.861] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 190 (-1/-1) hits flags = 528 (plus default)
[15:23:39.874] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:23:39.874] <TB2> INFO: run 1 of 1
[15:23:40.111] <TB2> INFO: Expecting 3972800 events.
[15:24:12.040] <TB2> INFO: 735570 events read in total (31338ms).
[15:24:43.103] <TB2> INFO: 1467760 events read in total (62401ms).
[15:25:14.345] <TB2> INFO: 2194665 events read in total (93643ms).
[15:25:45.603] <TB2> INFO: 2917835 events read in total (124901ms).
[15:26:17.265] <TB2> INFO: 3640295 events read in total (156563ms).
[15:26:32.548] <TB2> INFO: 3972800 events read in total (171846ms).
[15:26:32.668] <TB2> INFO: Test took 172793ms.
[15:27:00.509] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 190 (-1/-1) hits flags = 528 (plus default)
[15:27:00.524] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:27:00.524] <TB2> INFO: run 1 of 1
[15:27:00.770] <TB2> INFO: Expecting 3972800 events.
[15:27:32.784] <TB2> INFO: 735840 events read in total (31423ms).
[15:28:03.840] <TB2> INFO: 1468000 events read in total (62479ms).
[15:28:35.409] <TB2> INFO: 2194765 events read in total (94048ms).
[15:29:06.002] <TB2> INFO: 2917715 events read in total (125641ms).
[15:29:38.824] <TB2> INFO: 3640270 events read in total (157463ms).
[15:29:54.071] <TB2> INFO: 3972800 events read in total (172710ms).
[15:29:54.149] <TB2> INFO: Test took 173624ms.
[15:30:20.416] <TB2> INFO: PixTestTrim::trimBitTest() done
[15:30:20.417] <TB2> INFO: PixTestTrim::doTest() done, duration: 2460 seconds
[15:30:20.417] <TB2> INFO: Decoding statistics:
[15:30:20.417] <TB2> INFO: General information:
[15:30:20.417] <TB2> INFO: 16bit words read: 0
[15:30:20.417] <TB2> INFO: valid events total: 0
[15:30:20.417] <TB2> INFO: empty events: 0
[15:30:20.417] <TB2> INFO: valid events with pixels: 0
[15:30:20.417] <TB2> INFO: valid pixel hits: 0
[15:30:20.417] <TB2> INFO: Event errors: 0
[15:30:20.417] <TB2> INFO: start marker: 0
[15:30:20.417] <TB2> INFO: stop marker: 0
[15:30:20.417] <TB2> INFO: overflow: 0
[15:30:20.417] <TB2> INFO: invalid 5bit words: 0
[15:30:20.417] <TB2> INFO: invalid XOR eye diagram: 0
[15:30:20.417] <TB2> INFO: frame (failed synchr.): 0
[15:30:20.417] <TB2> INFO: idle data (no TBM trl): 0
[15:30:20.417] <TB2> INFO: no data (only TBM hdr): 0
[15:30:20.417] <TB2> INFO: TBM errors: 0
[15:30:20.417] <TB2> INFO: flawed TBM headers: 0
[15:30:20.417] <TB2> INFO: flawed TBM trailers: 0
[15:30:20.417] <TB2> INFO: event ID mismatches: 0
[15:30:20.417] <TB2> INFO: ROC errors: 0
[15:30:20.417] <TB2> INFO: missing ROC header(s): 0
[15:30:20.417] <TB2> INFO: misplaced readback start: 0
[15:30:20.417] <TB2> INFO: Pixel decoding errors: 0
[15:30:20.417] <TB2> INFO: pixel data incomplete: 0
[15:30:20.417] <TB2> INFO: pixel address: 0
[15:30:20.417] <TB2> INFO: pulse height fill bit: 0
[15:30:20.417] <TB2> INFO: buffer corruption: 0
[15:30:21.225] <TB2> INFO: ######################################################################
[15:30:21.225] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[15:30:21.225] <TB2> INFO: ######################################################################
[15:30:21.484] <TB2> INFO: Expecting 41600 events.
[15:30:25.043] <TB2> INFO: 41600 events read in total (2968ms).
[15:30:25.044] <TB2> INFO: Test took 3817ms.
[15:30:25.494] <TB2> INFO: Expecting 41600 events.
[15:30:29.107] <TB2> INFO: 41600 events read in total (3022ms).
[15:30:29.107] <TB2> INFO: Test took 3857ms.
[15:30:29.397] <TB2> INFO: Expecting 41600 events.
[15:30:32.939] <TB2> INFO: 41600 events read in total (2950ms).
[15:30:32.940] <TB2> INFO: Test took 3809ms.
[15:30:33.233] <TB2> INFO: Expecting 41600 events.
[15:30:36.800] <TB2> INFO: 41600 events read in total (2976ms).
[15:30:36.801] <TB2> INFO: Test took 3834ms.
[15:30:37.090] <TB2> INFO: Expecting 41600 events.
[15:30:40.634] <TB2> INFO: 41600 events read in total (2953ms).
[15:30:40.635] <TB2> INFO: Test took 3810ms.
[15:30:40.943] <TB2> INFO: Expecting 41600 events.
[15:30:44.478] <TB2> INFO: 41600 events read in total (2943ms).
[15:30:44.479] <TB2> INFO: Test took 3820ms.
[15:30:44.771] <TB2> INFO: Expecting 41600 events.
[15:30:48.272] <TB2> INFO: 41600 events read in total (2909ms).
[15:30:48.273] <TB2> INFO: Test took 3767ms.
[15:30:48.563] <TB2> INFO: Expecting 41600 events.
[15:30:52.146] <TB2> INFO: 41600 events read in total (2992ms).
[15:30:52.147] <TB2> INFO: Test took 3849ms.
[15:30:52.436] <TB2> INFO: Expecting 41600 events.
[15:30:55.980] <TB2> INFO: 41600 events read in total (2952ms).
[15:30:55.981] <TB2> INFO: Test took 3810ms.
[15:30:56.271] <TB2> INFO: Expecting 41600 events.
[15:30:59.824] <TB2> INFO: 41600 events read in total (2961ms).
[15:30:59.825] <TB2> INFO: Test took 3820ms.
[15:31:00.115] <TB2> INFO: Expecting 41600 events.
[15:31:03.742] <TB2> INFO: 41600 events read in total (3035ms).
[15:31:03.743] <TB2> INFO: Test took 3893ms.
[15:31:04.035] <TB2> INFO: Expecting 41600 events.
[15:31:07.694] <TB2> INFO: 41600 events read in total (3068ms).
[15:31:07.695] <TB2> INFO: Test took 3926ms.
[15:31:07.988] <TB2> INFO: Expecting 41600 events.
[15:31:11.573] <TB2> INFO: 41600 events read in total (2993ms).
[15:31:11.574] <TB2> INFO: Test took 3852ms.
[15:31:11.864] <TB2> INFO: Expecting 41600 events.
[15:31:15.394] <TB2> INFO: 41600 events read in total (2938ms).
[15:31:15.395] <TB2> INFO: Test took 3797ms.
[15:31:15.686] <TB2> INFO: Expecting 41600 events.
[15:31:19.324] <TB2> INFO: 41600 events read in total (3046ms).
[15:31:19.325] <TB2> INFO: Test took 3903ms.
[15:31:19.617] <TB2> INFO: Expecting 41600 events.
[15:31:23.163] <TB2> INFO: 41600 events read in total (2955ms).
[15:31:23.164] <TB2> INFO: Test took 3812ms.
[15:31:23.456] <TB2> INFO: Expecting 41600 events.
[15:31:27.027] <TB2> INFO: 41600 events read in total (2979ms).
[15:31:27.028] <TB2> INFO: Test took 3837ms.
[15:31:27.317] <TB2> INFO: Expecting 41600 events.
[15:31:30.861] <TB2> INFO: 41600 events read in total (2952ms).
[15:31:30.862] <TB2> INFO: Test took 3810ms.
[15:31:31.152] <TB2> INFO: Expecting 41600 events.
[15:31:34.734] <TB2> INFO: 41600 events read in total (2990ms).
[15:31:34.735] <TB2> INFO: Test took 3849ms.
[15:31:35.025] <TB2> INFO: Expecting 41600 events.
[15:31:38.531] <TB2> INFO: 41600 events read in total (2915ms).
[15:31:38.531] <TB2> INFO: Test took 3772ms.
[15:31:38.821] <TB2> INFO: Expecting 41600 events.
[15:31:42.390] <TB2> INFO: 41600 events read in total (2977ms).
[15:31:42.391] <TB2> INFO: Test took 3835ms.
[15:31:42.680] <TB2> INFO: Expecting 41600 events.
[15:31:46.224] <TB2> INFO: 41600 events read in total (2952ms).
[15:31:46.225] <TB2> INFO: Test took 3810ms.
[15:31:46.514] <TB2> INFO: Expecting 41600 events.
[15:31:49.986] <TB2> INFO: 41600 events read in total (2880ms).
[15:31:49.987] <TB2> INFO: Test took 3738ms.
[15:31:50.290] <TB2> INFO: Expecting 41600 events.
[15:31:54.047] <TB2> INFO: 41600 events read in total (3165ms).
[15:31:54.048] <TB2> INFO: Test took 4036ms.
[15:31:54.340] <TB2> INFO: Expecting 41600 events.
[15:31:57.896] <TB2> INFO: 41600 events read in total (2963ms).
[15:31:57.897] <TB2> INFO: Test took 3822ms.
[15:31:58.189] <TB2> INFO: Expecting 41600 events.
[15:32:01.723] <TB2> INFO: 41600 events read in total (2942ms).
[15:32:01.724] <TB2> INFO: Test took 3802ms.
[15:32:02.013] <TB2> INFO: Expecting 41600 events.
[15:32:05.544] <TB2> INFO: 41600 events read in total (2939ms).
[15:32:05.546] <TB2> INFO: Test took 3798ms.
[15:32:05.838] <TB2> INFO: Expecting 41600 events.
[15:32:09.403] <TB2> INFO: 41600 events read in total (2973ms).
[15:32:09.404] <TB2> INFO: Test took 3831ms.
[15:32:09.695] <TB2> INFO: Expecting 41600 events.
[15:32:13.221] <TB2> INFO: 41600 events read in total (2934ms).
[15:32:13.222] <TB2> INFO: Test took 3792ms.
[15:32:13.514] <TB2> INFO: Expecting 2560 events.
[15:32:14.408] <TB2> INFO: 2560 events read in total (302ms).
[15:32:14.409] <TB2> INFO: Test took 1170ms.
[15:32:14.716] <TB2> INFO: Expecting 2560 events.
[15:32:15.606] <TB2> INFO: 2560 events read in total (298ms).
[15:32:15.607] <TB2> INFO: Test took 1198ms.
[15:32:15.915] <TB2> INFO: Expecting 2560 events.
[15:32:16.800] <TB2> INFO: 2560 events read in total (294ms).
[15:32:16.800] <TB2> INFO: Test took 1193ms.
[15:32:17.110] <TB2> INFO: Expecting 2560 events.
[15:32:18.006] <TB2> INFO: 2560 events read in total (305ms).
[15:32:18.007] <TB2> INFO: Test took 1206ms.
[15:32:18.313] <TB2> INFO: Expecting 2560 events.
[15:32:19.203] <TB2> INFO: 2560 events read in total (298ms).
[15:32:19.203] <TB2> INFO: Test took 1196ms.
[15:32:19.510] <TB2> INFO: Expecting 2560 events.
[15:32:20.395] <TB2> INFO: 2560 events read in total (292ms).
[15:32:20.396] <TB2> INFO: Test took 1192ms.
[15:32:20.703] <TB2> INFO: Expecting 2560 events.
[15:32:21.592] <TB2> INFO: 2560 events read in total (297ms).
[15:32:21.592] <TB2> INFO: Test took 1196ms.
[15:32:21.900] <TB2> INFO: Expecting 2560 events.
[15:32:22.789] <TB2> INFO: 2560 events read in total (297ms).
[15:32:22.789] <TB2> INFO: Test took 1197ms.
[15:32:23.096] <TB2> INFO: Expecting 2560 events.
[15:32:23.986] <TB2> INFO: 2560 events read in total (298ms).
[15:32:23.987] <TB2> INFO: Test took 1197ms.
[15:32:24.296] <TB2> INFO: Expecting 2560 events.
[15:32:25.179] <TB2> INFO: 2560 events read in total (292ms).
[15:32:25.179] <TB2> INFO: Test took 1192ms.
[15:32:25.486] <TB2> INFO: Expecting 2560 events.
[15:32:26.377] <TB2> INFO: 2560 events read in total (297ms).
[15:32:26.377] <TB2> INFO: Test took 1197ms.
[15:32:26.685] <TB2> INFO: Expecting 2560 events.
[15:32:27.577] <TB2> INFO: 2560 events read in total (300ms).
[15:32:27.577] <TB2> INFO: Test took 1199ms.
[15:32:27.885] <TB2> INFO: Expecting 2560 events.
[15:32:28.774] <TB2> INFO: 2560 events read in total (297ms).
[15:32:28.774] <TB2> INFO: Test took 1197ms.
[15:32:29.082] <TB2> INFO: Expecting 2560 events.
[15:32:29.977] <TB2> INFO: 2560 events read in total (303ms).
[15:32:29.977] <TB2> INFO: Test took 1203ms.
[15:32:30.285] <TB2> INFO: Expecting 2560 events.
[15:32:31.175] <TB2> INFO: 2560 events read in total (298ms).
[15:32:31.175] <TB2> INFO: Test took 1198ms.
[15:32:31.483] <TB2> INFO: Expecting 2560 events.
[15:32:32.366] <TB2> INFO: 2560 events read in total (292ms).
[15:32:32.366] <TB2> INFO: Test took 1190ms.
[15:32:32.370] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:32:32.674] <TB2> INFO: Expecting 655360 events.
[15:32:47.595] <TB2> INFO: 655360 events read in total (14329ms).
[15:32:47.612] <TB2> INFO: Expecting 655360 events.
[15:33:02.148] <TB2> INFO: 655360 events read in total (14133ms).
[15:33:02.164] <TB2> INFO: Expecting 655360 events.
[15:33:16.785] <TB2> INFO: 655360 events read in total (14218ms).
[15:33:16.805] <TB2> INFO: Expecting 655360 events.
[15:33:31.444] <TB2> INFO: 655360 events read in total (14236ms).
[15:33:31.470] <TB2> INFO: Expecting 655360 events.
[15:33:45.978] <TB2> INFO: 655360 events read in total (14105ms).
[15:33:46.007] <TB2> INFO: Expecting 655360 events.
[15:34:00.639] <TB2> INFO: 655360 events read in total (14229ms).
[15:34:00.679] <TB2> INFO: Expecting 655360 events.
[15:34:15.396] <TB2> INFO: 655360 events read in total (14314ms).
[15:34:15.449] <TB2> INFO: Expecting 655360 events.
[15:34:30.068] <TB2> INFO: 655360 events read in total (14216ms).
[15:34:30.111] <TB2> INFO: Expecting 655360 events.
[15:34:44.593] <TB2> INFO: 655360 events read in total (14079ms).
[15:34:44.640] <TB2> INFO: Expecting 655360 events.
[15:34:59.276] <TB2> INFO: 655360 events read in total (14233ms).
[15:34:59.328] <TB2> INFO: Expecting 655360 events.
[15:35:13.774] <TB2> INFO: 655360 events read in total (14043ms).
[15:35:13.836] <TB2> INFO: Expecting 655360 events.
[15:35:28.377] <TB2> INFO: 655360 events read in total (14139ms).
[15:35:28.511] <TB2> INFO: Expecting 655360 events.
[15:35:43.070] <TB2> INFO: 655360 events read in total (14156ms).
[15:35:43.141] <TB2> INFO: Expecting 655360 events.
[15:35:57.644] <TB2> INFO: 655360 events read in total (14100ms).
[15:35:57.735] <TB2> INFO: Expecting 655360 events.
[15:36:12.189] <TB2> INFO: 655360 events read in total (14051ms).
[15:36:12.285] <TB2> INFO: Expecting 655360 events.
[15:36:26.786] <TB2> INFO: 655360 events read in total (14097ms).
[15:36:26.912] <TB2> INFO: Test took 234542ms.
[15:36:27.015] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:36:27.269] <TB2> INFO: Expecting 655360 events.
[15:36:41.799] <TB2> INFO: 655360 events read in total (13939ms).
[15:36:41.815] <TB2> INFO: Expecting 655360 events.
[15:36:56.205] <TB2> INFO: 655360 events read in total (13987ms).
[15:36:56.225] <TB2> INFO: Expecting 655360 events.
[15:37:10.567] <TB2> INFO: 655360 events read in total (13938ms).
[15:37:10.588] <TB2> INFO: Expecting 655360 events.
[15:37:24.951] <TB2> INFO: 655360 events read in total (13960ms).
[15:37:24.976] <TB2> INFO: Expecting 655360 events.
[15:37:39.318] <TB2> INFO: 655360 events read in total (13939ms).
[15:37:39.347] <TB2> INFO: Expecting 655360 events.
[15:37:53.863] <TB2> INFO: 655360 events read in total (14113ms).
[15:37:53.899] <TB2> INFO: Expecting 655360 events.
[15:38:08.290] <TB2> INFO: 655360 events read in total (13988ms).
[15:38:08.329] <TB2> INFO: Expecting 655360 events.
[15:38:22.809] <TB2> INFO: 655360 events read in total (14077ms).
[15:38:22.851] <TB2> INFO: Expecting 655360 events.
[15:38:37.360] <TB2> INFO: 655360 events read in total (14106ms).
[15:38:37.406] <TB2> INFO: Expecting 655360 events.
[15:38:51.710] <TB2> INFO: 655360 events read in total (13901ms).
[15:38:51.777] <TB2> INFO: Expecting 655360 events.
[15:39:06.105] <TB2> INFO: 655360 events read in total (13925ms).
[15:39:06.161] <TB2> INFO: Expecting 655360 events.
[15:39:20.629] <TB2> INFO: 655360 events read in total (14065ms).
[15:39:20.723] <TB2> INFO: Expecting 655360 events.
[15:39:35.283] <TB2> INFO: 655360 events read in total (14157ms).
[15:39:35.358] <TB2> INFO: Expecting 655360 events.
[15:39:49.819] <TB2> INFO: 655360 events read in total (14058ms).
[15:39:49.937] <TB2> INFO: Expecting 655360 events.
[15:40:04.500] <TB2> INFO: 655360 events read in total (14159ms).
[15:40:04.596] <TB2> INFO: Expecting 655360 events.
[15:40:19.077] <TB2> INFO: 655360 events read in total (14078ms).
[15:40:19.217] <TB2> INFO: Test took 232202ms.
[15:40:19.409] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.414] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:40:19.420] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:40:19.426] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:40:19.432] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:40:19.438] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:40:19.443] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[15:40:19.449] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[15:40:19.455] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[15:40:19.461] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[15:40:19.466] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[15:40:19.472] <TB2> INFO: safety margin for low PH: adding 11, margin is now 31
[15:40:19.478] <TB2> INFO: safety margin for low PH: adding 12, margin is now 32
[15:40:19.484] <TB2> INFO: safety margin for low PH: adding 13, margin is now 33
[15:40:19.490] <TB2> INFO: safety margin for low PH: adding 14, margin is now 34
[15:40:19.496] <TB2> INFO: safety margin for low PH: adding 15, margin is now 35
[15:40:19.502] <TB2> INFO: safety margin for low PH: adding 16, margin is now 36
[15:40:19.508] <TB2> INFO: safety margin for low PH: adding 17, margin is now 37
[15:40:19.513] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.519] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.525] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.530] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.536] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.542] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.548] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.554] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:40:19.559] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.565] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.571] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.577] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.583] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:40:19.588] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:40:19.594] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:40:19.600] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:40:19.606] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:40:19.611] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[15:40:19.617] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[15:40:19.623] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.628] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:40:19.634] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.640] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:40:19.646] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:40:19.652] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.657] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.663] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:40:19.669] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:40:19.674] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:40:19.680] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:40:19.686] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:40:19.724] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C0.dat
[15:40:19.724] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C1.dat
[15:40:19.724] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C2.dat
[15:40:19.724] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C3.dat
[15:40:19.724] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C4.dat
[15:40:19.724] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C5.dat
[15:40:19.724] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C6.dat
[15:40:19.724] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C7.dat
[15:40:19.724] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C8.dat
[15:40:19.724] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C9.dat
[15:40:19.725] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C10.dat
[15:40:19.725] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C11.dat
[15:40:19.725] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C12.dat
[15:40:19.725] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C13.dat
[15:40:19.725] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C14.dat
[15:40:19.725] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C15.dat
[15:40:19.966] <TB2> INFO: Expecting 41600 events.
[15:40:23.134] <TB2> INFO: 41600 events read in total (2576ms).
[15:40:23.135] <TB2> INFO: Test took 3407ms.
[15:40:23.595] <TB2> INFO: Expecting 41600 events.
[15:40:26.704] <TB2> INFO: 41600 events read in total (2518ms).
[15:40:26.705] <TB2> INFO: Test took 3354ms.
[15:40:27.160] <TB2> INFO: Expecting 41600 events.
[15:40:30.356] <TB2> INFO: 41600 events read in total (2604ms).
[15:40:30.357] <TB2> INFO: Test took 3440ms.
[15:40:30.576] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:30.665] <TB2> INFO: Expecting 2560 events.
[15:40:31.553] <TB2> INFO: 2560 events read in total (296ms).
[15:40:31.553] <TB2> INFO: Test took 978ms.
[15:40:31.558] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:31.861] <TB2> INFO: Expecting 2560 events.
[15:40:32.753] <TB2> INFO: 2560 events read in total (300ms).
[15:40:32.754] <TB2> INFO: Test took 1196ms.
[15:40:32.757] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:33.061] <TB2> INFO: Expecting 2560 events.
[15:40:33.954] <TB2> INFO: 2560 events read in total (301ms).
[15:40:33.955] <TB2> INFO: Test took 1198ms.
[15:40:33.957] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:34.262] <TB2> INFO: Expecting 2560 events.
[15:40:35.159] <TB2> INFO: 2560 events read in total (304ms).
[15:40:35.159] <TB2> INFO: Test took 1202ms.
[15:40:35.162] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:35.467] <TB2> INFO: Expecting 2560 events.
[15:40:36.361] <TB2> INFO: 2560 events read in total (302ms).
[15:40:36.363] <TB2> INFO: Test took 1201ms.
[15:40:36.367] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:36.670] <TB2> INFO: Expecting 2560 events.
[15:40:37.563] <TB2> INFO: 2560 events read in total (302ms).
[15:40:37.564] <TB2> INFO: Test took 1197ms.
[15:40:37.567] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:37.872] <TB2> INFO: Expecting 2560 events.
[15:40:38.765] <TB2> INFO: 2560 events read in total (302ms).
[15:40:38.765] <TB2> INFO: Test took 1198ms.
[15:40:38.770] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:39.073] <TB2> INFO: Expecting 2560 events.
[15:40:39.964] <TB2> INFO: 2560 events read in total (299ms).
[15:40:39.965] <TB2> INFO: Test took 1195ms.
[15:40:39.967] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:40.274] <TB2> INFO: Expecting 2560 events.
[15:40:41.165] <TB2> INFO: 2560 events read in total (300ms).
[15:40:41.166] <TB2> INFO: Test took 1199ms.
[15:40:41.169] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:41.474] <TB2> INFO: Expecting 2560 events.
[15:40:42.367] <TB2> INFO: 2560 events read in total (301ms).
[15:40:42.367] <TB2> INFO: Test took 1198ms.
[15:40:42.370] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:42.676] <TB2> INFO: Expecting 2560 events.
[15:40:43.568] <TB2> INFO: 2560 events read in total (300ms).
[15:40:43.568] <TB2> INFO: Test took 1198ms.
[15:40:43.572] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:43.876] <TB2> INFO: Expecting 2560 events.
[15:40:44.768] <TB2> INFO: 2560 events read in total (300ms).
[15:40:44.768] <TB2> INFO: Test took 1196ms.
[15:40:44.771] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:45.077] <TB2> INFO: Expecting 2560 events.
[15:40:45.969] <TB2> INFO: 2560 events read in total (301ms).
[15:40:45.969] <TB2> INFO: Test took 1198ms.
[15:40:45.972] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:46.277] <TB2> INFO: Expecting 2560 events.
[15:40:47.165] <TB2> INFO: 2560 events read in total (296ms).
[15:40:47.165] <TB2> INFO: Test took 1193ms.
[15:40:47.168] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:47.472] <TB2> INFO: Expecting 2560 events.
[15:40:48.356] <TB2> INFO: 2560 events read in total (292ms).
[15:40:48.357] <TB2> INFO: Test took 1189ms.
[15:40:48.359] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:48.665] <TB2> INFO: Expecting 2560 events.
[15:40:49.548] <TB2> INFO: 2560 events read in total (291ms).
[15:40:49.548] <TB2> INFO: Test took 1189ms.
[15:40:49.552] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:49.857] <TB2> INFO: Expecting 2560 events.
[15:40:50.740] <TB2> INFO: 2560 events read in total (291ms).
[15:40:50.740] <TB2> INFO: Test took 1189ms.
[15:40:50.743] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:51.048] <TB2> INFO: Expecting 2560 events.
[15:40:51.939] <TB2> INFO: 2560 events read in total (299ms).
[15:40:51.939] <TB2> INFO: Test took 1196ms.
[15:40:51.943] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:52.246] <TB2> INFO: Expecting 2560 events.
[15:40:53.138] <TB2> INFO: 2560 events read in total (300ms).
[15:40:53.138] <TB2> INFO: Test took 1195ms.
[15:40:53.140] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:53.448] <TB2> INFO: Expecting 2560 events.
[15:40:54.328] <TB2> INFO: 2560 events read in total (289ms).
[15:40:54.328] <TB2> INFO: Test took 1188ms.
[15:40:54.331] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:54.637] <TB2> INFO: Expecting 2560 events.
[15:40:55.526] <TB2> INFO: 2560 events read in total (297ms).
[15:40:55.526] <TB2> INFO: Test took 1195ms.
[15:40:55.529] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:55.834] <TB2> INFO: Expecting 2560 events.
[15:40:56.729] <TB2> INFO: 2560 events read in total (304ms).
[15:40:56.730] <TB2> INFO: Test took 1201ms.
[15:40:56.733] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:57.038] <TB2> INFO: Expecting 2560 events.
[15:40:57.927] <TB2> INFO: 2560 events read in total (297ms).
[15:40:57.928] <TB2> INFO: Test took 1195ms.
[15:40:57.931] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:58.235] <TB2> INFO: Expecting 2560 events.
[15:40:59.126] <TB2> INFO: 2560 events read in total (300ms).
[15:40:59.127] <TB2> INFO: Test took 1196ms.
[15:40:59.130] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:59.435] <TB2> INFO: Expecting 2560 events.
[15:41:00.330] <TB2> INFO: 2560 events read in total (303ms).
[15:41:00.330] <TB2> INFO: Test took 1200ms.
[15:41:00.334] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:41:00.639] <TB2> INFO: Expecting 2560 events.
[15:41:01.523] <TB2> INFO: 2560 events read in total (293ms).
[15:41:01.523] <TB2> INFO: Test took 1190ms.
[15:41:01.527] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:41:01.832] <TB2> INFO: Expecting 2560 events.
[15:41:02.718] <TB2> INFO: 2560 events read in total (294ms).
[15:41:02.718] <TB2> INFO: Test took 1191ms.
[15:41:02.723] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:41:03.026] <TB2> INFO: Expecting 2560 events.
[15:41:03.913] <TB2> INFO: 2560 events read in total (294ms).
[15:41:03.913] <TB2> INFO: Test took 1190ms.
[15:41:03.917] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:41:04.222] <TB2> INFO: Expecting 2560 events.
[15:41:05.115] <TB2> INFO: 2560 events read in total (301ms).
[15:41:05.116] <TB2> INFO: Test took 1199ms.
[15:41:05.119] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:41:05.423] <TB2> INFO: Expecting 2560 events.
[15:41:06.310] <TB2> INFO: 2560 events read in total (295ms).
[15:41:06.310] <TB2> INFO: Test took 1191ms.
[15:41:06.314] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:41:06.619] <TB2> INFO: Expecting 2560 events.
[15:41:07.512] <TB2> INFO: 2560 events read in total (301ms).
[15:41:07.513] <TB2> INFO: Test took 1199ms.
[15:41:07.518] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:41:07.821] <TB2> INFO: Expecting 2560 events.
[15:41:08.713] <TB2> INFO: 2560 events read in total (300ms).
[15:41:08.713] <TB2> INFO: Test took 1195ms.
[15:41:09.186] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 647 seconds
[15:41:09.186] <TB2> INFO: PH scale (per ROC): 49 51 55 65 61 52 48 53 44 41 37 42 66 44 58 48
[15:41:09.186] <TB2> INFO: PH offset (per ROC): 110 124 128 121 130 112 101 132 104 112 87 106 114 100 113 105
[15:41:09.193] <TB2> INFO: Decoding statistics:
[15:41:09.193] <TB2> INFO: General information:
[15:41:09.193] <TB2> INFO: 16bit words read: 127888
[15:41:09.193] <TB2> INFO: valid events total: 20480
[15:41:09.193] <TB2> INFO: empty events: 17976
[15:41:09.193] <TB2> INFO: valid events with pixels: 2504
[15:41:09.193] <TB2> INFO: valid pixel hits: 2504
[15:41:09.193] <TB2> INFO: Event errors: 0
[15:41:09.193] <TB2> INFO: start marker: 0
[15:41:09.193] <TB2> INFO: stop marker: 0
[15:41:09.193] <TB2> INFO: overflow: 0
[15:41:09.193] <TB2> INFO: invalid 5bit words: 0
[15:41:09.193] <TB2> INFO: invalid XOR eye diagram: 0
[15:41:09.193] <TB2> INFO: frame (failed synchr.): 0
[15:41:09.193] <TB2> INFO: idle data (no TBM trl): 0
[15:41:09.193] <TB2> INFO: no data (only TBM hdr): 0
[15:41:09.193] <TB2> INFO: TBM errors: 0
[15:41:09.193] <TB2> INFO: flawed TBM headers: 0
[15:41:09.193] <TB2> INFO: flawed TBM trailers: 0
[15:41:09.193] <TB2> INFO: event ID mismatches: 0
[15:41:09.193] <TB2> INFO: ROC errors: 0
[15:41:09.193] <TB2> INFO: missing ROC header(s): 0
[15:41:09.194] <TB2> INFO: misplaced readback start: 0
[15:41:09.194] <TB2> INFO: Pixel decoding errors: 0
[15:41:09.194] <TB2> INFO: pixel data incomplete: 0
[15:41:09.194] <TB2> INFO: pixel address: 0
[15:41:09.194] <TB2> INFO: pulse height fill bit: 0
[15:41:09.194] <TB2> INFO: buffer corruption: 0
[15:41:09.363] <TB2> INFO: ######################################################################
[15:41:09.363] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:41:09.363] <TB2> INFO: ######################################################################
[15:41:09.379] <TB2> INFO: scanning low vcal = 10
[15:41:09.617] <TB2> INFO: Expecting 41600 events.
[15:41:13.234] <TB2> INFO: 41600 events read in total (3026ms).
[15:41:13.234] <TB2> INFO: Test took 3855ms.
[15:41:13.236] <TB2> INFO: scanning low vcal = 20
[15:41:13.530] <TB2> INFO: Expecting 41600 events.
[15:41:17.149] <TB2> INFO: 41600 events read in total (3027ms).
[15:41:17.149] <TB2> INFO: Test took 3913ms.
[15:41:17.151] <TB2> INFO: scanning low vcal = 30
[15:41:17.447] <TB2> INFO: Expecting 41600 events.
[15:41:21.103] <TB2> INFO: 41600 events read in total (3064ms).
[15:41:21.104] <TB2> INFO: Test took 3953ms.
[15:41:21.107] <TB2> INFO: scanning low vcal = 40
[15:41:21.385] <TB2> INFO: Expecting 41600 events.
[15:41:25.359] <TB2> INFO: 41600 events read in total (3382ms).
[15:41:25.361] <TB2> INFO: Test took 4254ms.
[15:41:25.365] <TB2> INFO: scanning low vcal = 50
[15:41:25.642] <TB2> INFO: Expecting 41600 events.
[15:41:29.678] <TB2> INFO: 41600 events read in total (3443ms).
[15:41:29.679] <TB2> INFO: Test took 4314ms.
[15:41:29.683] <TB2> INFO: scanning low vcal = 60
[15:41:29.960] <TB2> INFO: Expecting 41600 events.
[15:41:33.909] <TB2> INFO: 41600 events read in total (3357ms).
[15:41:33.910] <TB2> INFO: Test took 4227ms.
[15:41:33.913] <TB2> INFO: scanning low vcal = 70
[15:41:34.190] <TB2> INFO: Expecting 41600 events.
[15:41:38.168] <TB2> INFO: 41600 events read in total (3387ms).
[15:41:38.168] <TB2> INFO: Test took 4255ms.
[15:41:38.171] <TB2> INFO: scanning low vcal = 80
[15:41:38.449] <TB2> INFO: Expecting 41600 events.
[15:41:42.473] <TB2> INFO: 41600 events read in total (3433ms).
[15:41:42.474] <TB2> INFO: Test took 4303ms.
[15:41:42.477] <TB2> INFO: scanning low vcal = 90
[15:41:42.755] <TB2> INFO: Expecting 41600 events.
[15:41:46.723] <TB2> INFO: 41600 events read in total (3376ms).
[15:41:46.724] <TB2> INFO: Test took 4247ms.
[15:41:46.728] <TB2> INFO: scanning low vcal = 100
[15:41:47.004] <TB2> INFO: Expecting 41600 events.
[15:41:51.021] <TB2> INFO: 41600 events read in total (3425ms).
[15:41:51.022] <TB2> INFO: Test took 4294ms.
[15:41:51.025] <TB2> INFO: scanning low vcal = 110
[15:41:51.302] <TB2> INFO: Expecting 41600 events.
[15:41:55.287] <TB2> INFO: 41600 events read in total (3393ms).
[15:41:55.288] <TB2> INFO: Test took 4263ms.
[15:41:55.291] <TB2> INFO: scanning low vcal = 120
[15:41:55.568] <TB2> INFO: Expecting 41600 events.
[15:41:59.585] <TB2> INFO: 41600 events read in total (3425ms).
[15:41:59.586] <TB2> INFO: Test took 4295ms.
[15:41:59.589] <TB2> INFO: scanning low vcal = 130
[15:41:59.866] <TB2> INFO: Expecting 41600 events.
[15:42:03.828] <TB2> INFO: 41600 events read in total (3370ms).
[15:42:03.828] <TB2> INFO: Test took 4239ms.
[15:42:03.831] <TB2> INFO: scanning low vcal = 140
[15:42:04.109] <TB2> INFO: Expecting 41600 events.
[15:42:08.100] <TB2> INFO: 41600 events read in total (3399ms).
[15:42:08.101] <TB2> INFO: Test took 4270ms.
[15:42:08.104] <TB2> INFO: scanning low vcal = 150
[15:42:08.380] <TB2> INFO: Expecting 41600 events.
[15:42:12.423] <TB2> INFO: 41600 events read in total (3451ms).
[15:42:12.424] <TB2> INFO: Test took 4320ms.
[15:42:12.427] <TB2> INFO: scanning low vcal = 160
[15:42:12.705] <TB2> INFO: Expecting 41600 events.
[15:42:16.671] <TB2> INFO: 41600 events read in total (3374ms).
[15:42:16.672] <TB2> INFO: Test took 4245ms.
[15:42:16.675] <TB2> INFO: scanning low vcal = 170
[15:42:16.952] <TB2> INFO: Expecting 41600 events.
[15:42:20.919] <TB2> INFO: 41600 events read in total (3375ms).
[15:42:20.920] <TB2> INFO: Test took 4245ms.
[15:42:20.925] <TB2> INFO: scanning low vcal = 180
[15:42:21.201] <TB2> INFO: Expecting 41600 events.
[15:42:25.207] <TB2> INFO: 41600 events read in total (3415ms).
[15:42:25.208] <TB2> INFO: Test took 4283ms.
[15:42:25.211] <TB2> INFO: scanning low vcal = 190
[15:42:25.489] <TB2> INFO: Expecting 41600 events.
[15:42:29.515] <TB2> INFO: 41600 events read in total (3434ms).
[15:42:29.516] <TB2> INFO: Test took 4305ms.
[15:42:29.518] <TB2> INFO: scanning low vcal = 200
[15:42:29.796] <TB2> INFO: Expecting 41600 events.
[15:42:33.826] <TB2> INFO: 41600 events read in total (3438ms).
[15:42:33.826] <TB2> INFO: Test took 4307ms.
[15:42:33.829] <TB2> INFO: scanning low vcal = 210
[15:42:34.107] <TB2> INFO: Expecting 41600 events.
[15:42:38.168] <TB2> INFO: 41600 events read in total (3469ms).
[15:42:38.168] <TB2> INFO: Test took 4339ms.
[15:42:38.171] <TB2> INFO: scanning low vcal = 220
[15:42:38.449] <TB2> INFO: Expecting 41600 events.
[15:42:42.440] <TB2> INFO: 41600 events read in total (3399ms).
[15:42:42.441] <TB2> INFO: Test took 4270ms.
[15:42:42.444] <TB2> INFO: scanning low vcal = 230
[15:42:42.722] <TB2> INFO: Expecting 41600 events.
[15:42:46.714] <TB2> INFO: 41600 events read in total (3400ms).
[15:42:46.715] <TB2> INFO: Test took 4271ms.
[15:42:46.718] <TB2> INFO: scanning low vcal = 240
[15:42:46.996] <TB2> INFO: Expecting 41600 events.
[15:42:51.059] <TB2> INFO: 41600 events read in total (3471ms).
[15:42:51.060] <TB2> INFO: Test took 4342ms.
[15:42:51.063] <TB2> INFO: scanning low vcal = 250
[15:42:51.346] <TB2> INFO: Expecting 41600 events.
[15:42:55.395] <TB2> INFO: 41600 events read in total (3457ms).
[15:42:55.396] <TB2> INFO: Test took 4333ms.
[15:42:55.400] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[15:42:55.676] <TB2> INFO: Expecting 41600 events.
[15:42:59.695] <TB2> INFO: 41600 events read in total (3427ms).
[15:42:59.696] <TB2> INFO: Test took 4296ms.
[15:42:59.699] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[15:42:59.977] <TB2> INFO: Expecting 41600 events.
[15:43:03.967] <TB2> INFO: 41600 events read in total (3399ms).
[15:43:03.968] <TB2> INFO: Test took 4269ms.
[15:43:03.971] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[15:43:04.247] <TB2> INFO: Expecting 41600 events.
[15:43:08.197] <TB2> INFO: 41600 events read in total (3358ms).
[15:43:08.198] <TB2> INFO: Test took 4227ms.
[15:43:08.201] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[15:43:08.478] <TB2> INFO: Expecting 41600 events.
[15:43:12.433] <TB2> INFO: 41600 events read in total (3363ms).
[15:43:12.434] <TB2> INFO: Test took 4232ms.
[15:43:12.437] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:43:12.713] <TB2> INFO: Expecting 41600 events.
[15:43:16.700] <TB2> INFO: 41600 events read in total (3395ms).
[15:43:16.701] <TB2> INFO: Test took 4264ms.
[15:43:17.343] <TB2> INFO: PixTestGainPedestal::measure() done
[15:43:56.221] <TB2> INFO: PixTestGainPedestal::fit() done
[15:43:56.221] <TB2> INFO: non-linearity mean: 0.965 0.981 0.982 0.983 0.982 0.980 0.935 0.981 0.938 0.929 1.019 0.957 0.989 0.927 0.986 0.941
[15:43:56.221] <TB2> INFO: non-linearity RMS: 0.042 0.004 0.004 0.004 0.003 0.003 0.086 0.004 0.112 0.063 0.167 0.061 0.002 0.135 0.003 0.081
[15:43:56.221] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[15:43:56.234] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[15:43:56.248] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[15:43:56.261] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[15:43:56.274] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[15:43:56.287] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[15:43:56.301] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[15:43:56.314] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[15:43:56.328] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[15:43:56.341] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[15:43:56.355] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[15:43:56.369] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[15:43:56.383] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[15:43:56.396] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[15:43:56.410] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[15:43:56.424] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[15:43:56.437] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 167 seconds
[15:43:56.437] <TB2> INFO: Decoding statistics:
[15:43:56.437] <TB2> INFO: General information:
[15:43:56.437] <TB2> INFO: 16bit words read: 3327650
[15:43:56.437] <TB2> INFO: valid events total: 332800
[15:43:56.437] <TB2> INFO: empty events: 0
[15:43:56.437] <TB2> INFO: valid events with pixels: 332800
[15:43:56.437] <TB2> INFO: valid pixel hits: 665425
[15:43:56.437] <TB2> INFO: Event errors: 0
[15:43:56.437] <TB2> INFO: start marker: 0
[15:43:56.437] <TB2> INFO: stop marker: 0
[15:43:56.437] <TB2> INFO: overflow: 0
[15:43:56.437] <TB2> INFO: invalid 5bit words: 0
[15:43:56.437] <TB2> INFO: invalid XOR eye diagram: 0
[15:43:56.437] <TB2> INFO: frame (failed synchr.): 0
[15:43:56.437] <TB2> INFO: idle data (no TBM trl): 0
[15:43:56.437] <TB2> INFO: no data (only TBM hdr): 0
[15:43:56.437] <TB2> INFO: TBM errors: 0
[15:43:56.437] <TB2> INFO: flawed TBM headers: 0
[15:43:56.437] <TB2> INFO: flawed TBM trailers: 0
[15:43:56.437] <TB2> INFO: event ID mismatches: 0
[15:43:56.437] <TB2> INFO: ROC errors: 0
[15:43:56.437] <TB2> INFO: missing ROC header(s): 0
[15:43:56.437] <TB2> INFO: misplaced readback start: 0
[15:43:56.437] <TB2> INFO: Pixel decoding errors: 0
[15:43:56.437] <TB2> INFO: pixel data incomplete: 0
[15:43:56.437] <TB2> INFO: pixel address: 0
[15:43:56.437] <TB2> INFO: pulse height fill bit: 0
[15:43:56.437] <TB2> INFO: buffer corruption: 0
[15:43:56.455] <TB2> INFO: Decoding statistics:
[15:43:56.455] <TB2> INFO: General information:
[15:43:56.455] <TB2> INFO: 16bit words read: 3457074
[15:43:56.455] <TB2> INFO: valid events total: 353536
[15:43:56.455] <TB2> INFO: empty events: 18232
[15:43:56.455] <TB2> INFO: valid events with pixels: 335304
[15:43:56.455] <TB2> INFO: valid pixel hits: 667929
[15:43:56.455] <TB2> INFO: Event errors: 0
[15:43:56.455] <TB2> INFO: start marker: 0
[15:43:56.455] <TB2> INFO: stop marker: 0
[15:43:56.455] <TB2> INFO: overflow: 0
[15:43:56.455] <TB2> INFO: invalid 5bit words: 0
[15:43:56.455] <TB2> INFO: invalid XOR eye diagram: 0
[15:43:56.455] <TB2> INFO: frame (failed synchr.): 0
[15:43:56.455] <TB2> INFO: idle data (no TBM trl): 0
[15:43:56.455] <TB2> INFO: no data (only TBM hdr): 0
[15:43:56.455] <TB2> INFO: TBM errors: 0
[15:43:56.455] <TB2> INFO: flawed TBM headers: 0
[15:43:56.455] <TB2> INFO: flawed TBM trailers: 0
[15:43:56.455] <TB2> INFO: event ID mismatches: 0
[15:43:56.455] <TB2> INFO: ROC errors: 0
[15:43:56.455] <TB2> INFO: missing ROC header(s): 0
[15:43:56.455] <TB2> INFO: misplaced readback start: 0
[15:43:56.455] <TB2> INFO: Pixel decoding errors: 0
[15:43:56.455] <TB2> INFO: pixel data incomplete: 0
[15:43:56.455] <TB2> INFO: pixel address: 0
[15:43:56.455] <TB2> INFO: pulse height fill bit: 0
[15:43:56.455] <TB2> INFO: buffer corruption: 0
[15:43:56.455] <TB2> INFO: enter test to run
[15:43:56.455] <TB2> INFO: test: exit no parameter change
[15:43:56.578] <TB2> QUIET: Connection to board 149 closed.
[15:43:56.579] <TB2> INFO: pXar: this is the end, my friend