[15:55:48.556] <TB2> INFO: *** Welcome to pxar ***
[15:55:48.556] <TB2> INFO: *** Today: 2016/11/07
[15:55:48.563] <TB2> INFO: *** Version: c8ba-dirty
[15:55:48.563] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C15.dat
[15:55:48.563] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[15:55:48.563] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//defaultMaskFile.dat
[15:55:48.563] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters_C15.dat
[15:55:48.629] <TB2> INFO: clk: 4
[15:55:48.629] <TB2> INFO: ctr: 4
[15:55:48.629] <TB2> INFO: sda: 19
[15:55:48.629] <TB2> INFO: tin: 9
[15:55:48.629] <TB2> INFO: level: 15
[15:55:48.629] <TB2> INFO: triggerdelay: 0
[15:55:48.629] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[15:55:48.629] <TB2> INFO: Log level: INFO
[15:55:48.638] <TB2> INFO: Found DTB DTB_WWXUD2
[15:55:48.645] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[15:55:48.647] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
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[15:55:48.649] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[15:55:50.142] <TB2> INFO: DUT info:
[15:55:50.142] <TB2> INFO: The DUT currently contains the following objects:
[15:55:50.142] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[15:55:50.142] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:55:50.142] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:55:50.142] <TB2> INFO: TBM Core alpha (2): 7 registers set
[15:55:50.142] <TB2> INFO: TBM Core beta (3): 7 registers set
[15:55:50.142] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[15:55:50.142] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.142] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.142] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.142] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.142] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.142] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.142] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.142] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.142] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.142] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.142] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.142] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.142] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.142] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.142] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.143] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:50.544] <TB2> INFO: enter 'restricted' command line mode
[15:55:50.544] <TB2> INFO: enter test to run
[15:55:50.544] <TB2> INFO: test: pretest no parameter change
[15:55:50.544] <TB2> INFO: running: pretest
[15:55:50.549] <TB2> INFO: ######################################################################
[15:55:50.549] <TB2> INFO: PixTestPretest::doTest()
[15:55:50.549] <TB2> INFO: ######################################################################
[15:55:50.550] <TB2> INFO: ----------------------------------------------------------------------
[15:55:50.550] <TB2> INFO: PixTestPretest::programROC()
[15:55:50.550] <TB2> INFO: ----------------------------------------------------------------------
[15:56:08.565] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[15:56:08.565] <TB2> INFO: IA differences per ROC: 18.5 18.5 19.3 20.9 20.1 16.9 19.3 20.9 19.3 18.5 18.5 20.9 18.5 18.5 19.3 18.5
[15:56:08.628] <TB2> INFO: ----------------------------------------------------------------------
[15:56:08.628] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[15:56:08.628] <TB2> INFO: ----------------------------------------------------------------------
[15:56:16.640] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 381.9 mA = 23.8688 mA/ROC
[15:56:16.640] <TB2> INFO: i(loss) [mA/ROC]: 18.5 19.3 18.5 19.3 19.3 18.5 19.3 18.5 18.5 18.5 18.5 18.5 19.3 18.5 18.5 18.5
[15:56:16.673] <TB2> INFO: ----------------------------------------------------------------------
[15:56:16.673] <TB2> INFO: PixTestPretest::findTiming()
[15:56:16.673] <TB2> INFO: ----------------------------------------------------------------------
[15:56:16.673] <TB2> INFO: PixTestCmd::init()

[15:56:49.163] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[15:56:49.163] <TB2> INFO: (success/tries = 100/100), width = 4
[15:56:50.668] <TB2> INFO: ----------------------------------------------------------------------
[15:56:50.668] <TB2> INFO: PixTestPretest::findWorkingPixel()
[15:56:50.668] <TB2> INFO: ----------------------------------------------------------------------
[15:56:50.763] <TB2> INFO: Expecting 231680 events.
[15:57:00.765] <TB2> INFO: 231680 events read in total (9410ms).
[15:57:00.774] <TB2> INFO: Test took 10101ms.
[15:57:01.021] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[15:57:01.053] <TB2> INFO: ----------------------------------------------------------------------
[15:57:01.053] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[15:57:01.053] <TB2> INFO: ----------------------------------------------------------------------
[15:57:01.147] <TB2> INFO: Expecting 231680 events.
[15:57:11.284] <TB2> INFO: 231680 events read in total (9545ms).
[15:57:11.294] <TB2> INFO: Test took 10236ms.
[15:57:11.560] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[15:57:11.560] <TB2> INFO: CalDel: 91 103 96 85 93 79 92 97 88 94 90 93 84 92 98 93
[15:57:11.560] <TB2> INFO: VthrComp: 53 51 51 51 51 51 51 51 57 56 53 51 51 51 51 52
[15:57:11.564] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C0.dat
[15:57:11.564] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C1.dat
[15:57:11.564] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C2.dat
[15:57:11.564] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C3.dat
[15:57:11.564] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C4.dat
[15:57:11.564] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C5.dat
[15:57:11.565] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C6.dat
[15:57:11.565] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C7.dat
[15:57:11.565] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C8.dat
[15:57:11.565] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C9.dat
[15:57:11.565] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C10.dat
[15:57:11.565] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C11.dat
[15:57:11.566] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C12.dat
[15:57:11.566] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C13.dat
[15:57:11.566] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C14.dat
[15:57:11.566] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C15.dat
[15:57:11.566] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[15:57:11.566] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[15:57:11.566] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[15:57:11.566] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[15:57:11.566] <TB2> INFO: PixTestPretest::doTest() done, duration: 81 seconds
[15:57:11.621] <TB2> INFO: enter test to run
[15:57:11.621] <TB2> INFO: test: fulltest no parameter change
[15:57:11.621] <TB2> INFO: running: fulltest
[15:57:11.621] <TB2> INFO: ######################################################################
[15:57:11.621] <TB2> INFO: PixTestFullTest::doTest()
[15:57:11.621] <TB2> INFO: ######################################################################
[15:57:11.622] <TB2> INFO: ######################################################################
[15:57:11.622] <TB2> INFO: PixTestAlive::doTest()
[15:57:11.622] <TB2> INFO: ######################################################################
[15:57:11.623] <TB2> INFO: ----------------------------------------------------------------------
[15:57:11.623] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:57:11.623] <TB2> INFO: ----------------------------------------------------------------------
[15:57:11.863] <TB2> INFO: Expecting 41600 events.
[15:57:15.448] <TB2> INFO: 41600 events read in total (2993ms).
[15:57:15.449] <TB2> INFO: Test took 3824ms.
[15:57:15.682] <TB2> INFO: PixTestAlive::aliveTest() done
[15:57:15.682] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:57:15.684] <TB2> INFO: ----------------------------------------------------------------------
[15:57:15.684] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:57:15.684] <TB2> INFO: ----------------------------------------------------------------------
[15:57:15.928] <TB2> INFO: Expecting 41600 events.
[15:57:18.877] <TB2> INFO: 41600 events read in total (2359ms).
[15:57:18.878] <TB2> INFO: Test took 3193ms.
[15:57:18.878] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[15:57:19.122] <TB2> INFO: PixTestAlive::maskTest() done
[15:57:19.122] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:57:19.123] <TB2> INFO: ----------------------------------------------------------------------
[15:57:19.124] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:57:19.124] <TB2> INFO: ----------------------------------------------------------------------
[15:57:19.362] <TB2> INFO: Expecting 41600 events.
[15:57:22.844] <TB2> INFO: 41600 events read in total (2890ms).
[15:57:22.845] <TB2> INFO: Test took 3720ms.
[15:57:23.079] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[15:57:23.079] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:57:23.079] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[15:57:23.079] <TB2> INFO: Decoding statistics:
[15:57:23.079] <TB2> INFO: General information:
[15:57:23.079] <TB2> INFO: 16bit words read: 0
[15:57:23.079] <TB2> INFO: valid events total: 0
[15:57:23.079] <TB2> INFO: empty events: 0
[15:57:23.079] <TB2> INFO: valid events with pixels: 0
[15:57:23.079] <TB2> INFO: valid pixel hits: 0
[15:57:23.079] <TB2> INFO: Event errors: 0
[15:57:23.079] <TB2> INFO: start marker: 0
[15:57:23.079] <TB2> INFO: stop marker: 0
[15:57:23.079] <TB2> INFO: overflow: 0
[15:57:23.079] <TB2> INFO: invalid 5bit words: 0
[15:57:23.080] <TB2> INFO: invalid XOR eye diagram: 0
[15:57:23.080] <TB2> INFO: frame (failed synchr.): 0
[15:57:23.080] <TB2> INFO: idle data (no TBM trl): 0
[15:57:23.080] <TB2> INFO: no data (only TBM hdr): 0
[15:57:23.080] <TB2> INFO: TBM errors: 0
[15:57:23.080] <TB2> INFO: flawed TBM headers: 0
[15:57:23.080] <TB2> INFO: flawed TBM trailers: 0
[15:57:23.080] <TB2> INFO: event ID mismatches: 0
[15:57:23.080] <TB2> INFO: ROC errors: 0
[15:57:23.080] <TB2> INFO: missing ROC header(s): 0
[15:57:23.080] <TB2> INFO: misplaced readback start: 0
[15:57:23.080] <TB2> INFO: Pixel decoding errors: 0
[15:57:23.080] <TB2> INFO: pixel data incomplete: 0
[15:57:23.080] <TB2> INFO: pixel address: 0
[15:57:23.080] <TB2> INFO: pulse height fill bit: 0
[15:57:23.080] <TB2> INFO: buffer corruption: 0
[15:57:23.087] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[15:57:23.087] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[15:57:23.087] <TB2> INFO: ######################################################################
[15:57:23.087] <TB2> INFO: PixTestReadback::doTest()
[15:57:23.087] <TB2> INFO: ######################################################################
[15:57:23.087] <TB2> INFO: ----------------------------------------------------------------------
[15:57:23.087] <TB2> INFO: PixTestReadback::CalibrateVd()
[15:57:23.087] <TB2> INFO: ----------------------------------------------------------------------
[15:57:33.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat
[15:57:33.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C1.dat
[15:57:33.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C2.dat
[15:57:33.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C3.dat
[15:57:33.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C4.dat
[15:57:33.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C5.dat
[15:57:33.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C6.dat
[15:57:33.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C7.dat
[15:57:33.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C8.dat
[15:57:33.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C9.dat
[15:57:33.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C10.dat
[15:57:33.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C11.dat
[15:57:33.063] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C12.dat
[15:57:33.063] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C13.dat
[15:57:33.063] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C14.dat
[15:57:33.063] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[15:57:33.095] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[15:57:33.095] <TB2> INFO: ----------------------------------------------------------------------
[15:57:33.095] <TB2> INFO: PixTestReadback::CalibrateVa()
[15:57:33.095] <TB2> INFO: ----------------------------------------------------------------------
[15:57:43.027] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat
[15:57:43.027] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C1.dat
[15:57:43.027] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C2.dat
[15:57:43.027] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C3.dat
[15:57:43.027] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C4.dat
[15:57:43.027] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C5.dat
[15:57:43.027] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C6.dat
[15:57:43.027] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C7.dat
[15:57:43.027] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C8.dat
[15:57:43.027] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C9.dat
[15:57:43.027] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C10.dat
[15:57:43.028] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C11.dat
[15:57:43.028] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C12.dat
[15:57:43.028] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C13.dat
[15:57:43.028] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C14.dat
[15:57:43.028] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[15:57:43.061] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[15:57:43.062] <TB2> INFO: ----------------------------------------------------------------------
[15:57:43.062] <TB2> INFO: PixTestReadback::readbackVbg()
[15:57:43.062] <TB2> INFO: ----------------------------------------------------------------------
[15:57:50.732] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[15:57:50.732] <TB2> INFO: ----------------------------------------------------------------------
[15:57:50.732] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[15:57:50.732] <TB2> INFO: ----------------------------------------------------------------------
[15:57:50.732] <TB2> INFO: Vbg will be calibrated using Vd calibration
[15:57:50.732] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 159calibrated Vbg = 1.20396 :::*/*/*/*/
[15:57:50.732] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 148.6calibrated Vbg = 1.20398 :::*/*/*/*/
[15:57:50.732] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 154.9calibrated Vbg = 1.19478 :::*/*/*/*/
[15:57:50.732] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 154.8calibrated Vbg = 1.19003 :::*/*/*/*/
[15:57:50.732] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 156.7calibrated Vbg = 1.19643 :::*/*/*/*/
[15:57:50.732] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 160.5calibrated Vbg = 1.20318 :::*/*/*/*/
[15:57:50.732] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 152.9calibrated Vbg = 1.19868 :::*/*/*/*/
[15:57:50.732] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 153.9calibrated Vbg = 1.20424 :::*/*/*/*/
[15:57:50.732] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 165.5calibrated Vbg = 1.18852 :::*/*/*/*/
[15:57:50.732] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 159.8calibrated Vbg = 1.19126 :::*/*/*/*/
[15:57:50.733] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 161.2calibrated Vbg = 1.18869 :::*/*/*/*/
[15:57:50.733] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 159.9calibrated Vbg = 1.18525 :::*/*/*/*/
[15:57:50.733] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 152.2calibrated Vbg = 1.19022 :::*/*/*/*/
[15:57:50.733] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 159.7calibrated Vbg = 1.18766 :::*/*/*/*/
[15:57:50.733] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 159.4calibrated Vbg = 1.19108 :::*/*/*/*/
[15:57:50.733] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 166.6calibrated Vbg = 1.19121 :::*/*/*/*/
[15:57:50.736] <TB2> INFO: ----------------------------------------------------------------------
[15:57:50.736] <TB2> INFO: PixTestReadback::CalibrateIa()
[15:57:50.736] <TB2> INFO: ----------------------------------------------------------------------
[16:00:31.553] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat
[16:00:31.553] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C1.dat
[16:00:31.553] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C2.dat
[16:00:31.553] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C3.dat
[16:00:31.553] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C4.dat
[16:00:31.553] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C5.dat
[16:00:31.553] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C6.dat
[16:00:31.553] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C7.dat
[16:00:31.553] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C8.dat
[16:00:31.553] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C9.dat
[16:00:31.553] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C10.dat
[16:00:31.553] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C11.dat
[16:00:31.553] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C12.dat
[16:00:31.553] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C13.dat
[16:00:31.554] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C14.dat
[16:00:31.554] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[16:00:31.581] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:00:31.582] <TB2> INFO: PixTestReadback::doTest() done
[16:00:31.582] <TB2> INFO: Decoding statistics:
[16:00:31.582] <TB2> INFO: General information:
[16:00:31.582] <TB2> INFO: 16bit words read: 1536
[16:00:31.582] <TB2> INFO: valid events total: 256
[16:00:31.582] <TB2> INFO: empty events: 256
[16:00:31.582] <TB2> INFO: valid events with pixels: 0
[16:00:31.582] <TB2> INFO: valid pixel hits: 0
[16:00:31.582] <TB2> INFO: Event errors: 0
[16:00:31.582] <TB2> INFO: start marker: 0
[16:00:31.582] <TB2> INFO: stop marker: 0
[16:00:31.582] <TB2> INFO: overflow: 0
[16:00:31.582] <TB2> INFO: invalid 5bit words: 0
[16:00:31.582] <TB2> INFO: invalid XOR eye diagram: 0
[16:00:31.582] <TB2> INFO: frame (failed synchr.): 0
[16:00:31.582] <TB2> INFO: idle data (no TBM trl): 0
[16:00:31.582] <TB2> INFO: no data (only TBM hdr): 0
[16:00:31.582] <TB2> INFO: TBM errors: 0
[16:00:31.582] <TB2> INFO: flawed TBM headers: 0
[16:00:31.582] <TB2> INFO: flawed TBM trailers: 0
[16:00:31.582] <TB2> INFO: event ID mismatches: 0
[16:00:31.582] <TB2> INFO: ROC errors: 0
[16:00:31.582] <TB2> INFO: missing ROC header(s): 0
[16:00:31.582] <TB2> INFO: misplaced readback start: 0
[16:00:31.582] <TB2> INFO: Pixel decoding errors: 0
[16:00:31.582] <TB2> INFO: pixel data incomplete: 0
[16:00:31.582] <TB2> INFO: pixel address: 0
[16:00:31.582] <TB2> INFO: pulse height fill bit: 0
[16:00:31.582] <TB2> INFO: buffer corruption: 0
[16:00:31.641] <TB2> INFO: ######################################################################
[16:00:31.641] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[16:00:31.641] <TB2> INFO: ######################################################################
[16:00:31.643] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[16:00:32.060] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:00:32.060] <TB2> INFO: run 1 of 1
[16:00:32.296] <TB2> INFO: Expecting 3120000 events.
[16:01:03.305] <TB2> INFO: 673520 events read in total (30417ms).











[16:01:33.471] <TB2> INFO: 1350305 events read in total (60583ms).











[16:02:03.955] <TB2> INFO: 2025675 events read in total (91067ms).




















[16:02:34.275] <TB2> INFO: 2700725 events read in total (121387ms).











[16:02:53.067] <TB2> INFO: 3120000 events read in total (140179ms).
[16:02:53.153] <TB2> INFO: Test took 141093ms.
[16:03:18.102] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 166 seconds
[16:03:18.102] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0
[16:03:18.102] <TB2> INFO: separation cut (per ROC): 115 121 109 125 138 112 135 116 123 118 111 122 110 106 118 120
[16:03:18.102] <TB2> INFO: Decoding statistics:
[16:03:18.102] <TB2> INFO: General information:
[16:03:18.102] <TB2> INFO: 16bit words read: 0
[16:03:18.102] <TB2> INFO: valid events total: 0
[16:03:18.102] <TB2> INFO: empty events: 0
[16:03:18.102] <TB2> INFO: valid events with pixels: 0
[16:03:18.102] <TB2> INFO: valid pixel hits: 0
[16:03:18.102] <TB2> INFO: Event errors: 0
[16:03:18.103] <TB2> INFO: start marker: 0
[16:03:18.103] <TB2> INFO: stop marker: 0
[16:03:18.103] <TB2> INFO: overflow: 0
[16:03:18.103] <TB2> INFO: invalid 5bit words: 0
[16:03:18.103] <TB2> INFO: invalid XOR eye diagram: 0
[16:03:18.103] <TB2> INFO: frame (failed synchr.): 0
[16:03:18.103] <TB2> INFO: idle data (no TBM trl): 0
[16:03:18.103] <TB2> INFO: no data (only TBM hdr): 0
[16:03:18.103] <TB2> INFO: TBM errors: 0
[16:03:18.103] <TB2> INFO: flawed TBM headers: 0
[16:03:18.103] <TB2> INFO: flawed TBM trailers: 0
[16:03:18.103] <TB2> INFO: event ID mismatches: 0
[16:03:18.103] <TB2> INFO: ROC errors: 0
[16:03:18.103] <TB2> INFO: missing ROC header(s): 0
[16:03:18.103] <TB2> INFO: misplaced readback start: 0
[16:03:18.103] <TB2> INFO: Pixel decoding errors: 0
[16:03:18.103] <TB2> INFO: pixel data incomplete: 0
[16:03:18.103] <TB2> INFO: pixel address: 0
[16:03:18.103] <TB2> INFO: pulse height fill bit: 0
[16:03:18.103] <TB2> INFO: buffer corruption: 0
[16:03:18.153] <TB2> INFO: ######################################################################
[16:03:18.153] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:03:18.153] <TB2> INFO: ######################################################################
[16:03:18.153] <TB2> INFO: ----------------------------------------------------------------------
[16:03:18.153] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:03:18.153] <TB2> INFO: ----------------------------------------------------------------------
[16:03:18.153] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[16:03:18.168] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[16:03:18.168] <TB2> INFO: run 1 of 1
[16:03:18.453] <TB2> INFO: Expecting 36608000 events.
[16:03:42.634] <TB2> INFO: 704550 events read in total (23589ms).
[16:04:05.825] <TB2> INFO: 1396900 events read in total (46780ms).
[16:04:29.146] <TB2> INFO: 2087350 events read in total (70101ms).
[16:04:52.363] <TB2> INFO: 2778750 events read in total (93318ms).
[16:05:15.459] <TB2> INFO: 3467100 events read in total (116414ms).
[16:05:38.859] <TB2> INFO: 4158600 events read in total (139814ms).
[16:06:02.304] <TB2> INFO: 4845600 events read in total (163259ms).
[16:06:25.548] <TB2> INFO: 5532950 events read in total (186503ms).
[16:06:48.731] <TB2> INFO: 6220800 events read in total (209686ms).
[16:07:11.953] <TB2> INFO: 6910900 events read in total (232908ms).
[16:07:35.123] <TB2> INFO: 7599150 events read in total (256078ms).
[16:07:58.512] <TB2> INFO: 8287300 events read in total (279467ms).
[16:08:21.747] <TB2> INFO: 8973700 events read in total (302702ms).
[16:08:44.866] <TB2> INFO: 9661400 events read in total (325821ms).
[16:09:07.933] <TB2> INFO: 10349650 events read in total (348888ms).
[16:09:31.031] <TB2> INFO: 11038850 events read in total (371986ms).
[16:09:54.194] <TB2> INFO: 11726550 events read in total (395149ms).
[16:10:17.654] <TB2> INFO: 12414250 events read in total (418609ms).
[16:10:40.970] <TB2> INFO: 13100950 events read in total (441925ms).
[16:11:04.191] <TB2> INFO: 13785600 events read in total (465146ms).
[16:11:27.065] <TB2> INFO: 14469400 events read in total (488020ms).
[16:11:50.103] <TB2> INFO: 15152600 events read in total (511058ms).
[16:12:13.107] <TB2> INFO: 15836600 events read in total (534062ms).
[16:12:36.079] <TB2> INFO: 16518700 events read in total (557034ms).
[16:12:59.170] <TB2> INFO: 17203250 events read in total (580125ms).
[16:13:22.269] <TB2> INFO: 17888050 events read in total (603224ms).
[16:13:45.159] <TB2> INFO: 18569650 events read in total (626114ms).
[16:14:08.306] <TB2> INFO: 19249800 events read in total (649261ms).
[16:14:31.195] <TB2> INFO: 19930700 events read in total (672150ms).
[16:14:54.178] <TB2> INFO: 20611550 events read in total (695133ms).
[16:15:17.384] <TB2> INFO: 21292300 events read in total (718339ms).
[16:15:40.386] <TB2> INFO: 21970600 events read in total (741341ms).
[16:16:03.372] <TB2> INFO: 22647800 events read in total (764328ms).
[16:16:26.057] <TB2> INFO: 23324450 events read in total (787012ms).
[16:16:49.050] <TB2> INFO: 24003050 events read in total (810005ms).
[16:17:12.083] <TB2> INFO: 24681050 events read in total (833038ms).
[16:17:34.978] <TB2> INFO: 25360850 events read in total (855933ms).
[16:17:57.938] <TB2> INFO: 26037900 events read in total (878893ms).
[16:18:20.839] <TB2> INFO: 26715850 events read in total (901794ms).
[16:18:43.993] <TB2> INFO: 27393150 events read in total (924948ms).
[16:19:07.009] <TB2> INFO: 28071500 events read in total (947964ms).
[16:19:30.049] <TB2> INFO: 28748900 events read in total (971004ms).
[16:19:52.743] <TB2> INFO: 29426750 events read in total (993698ms).
[16:20:15.717] <TB2> INFO: 30102350 events read in total (1016672ms).
[16:20:38.965] <TB2> INFO: 30779600 events read in total (1039920ms).
[16:21:02.012] <TB2> INFO: 31457050 events read in total (1062967ms).
[16:21:25.086] <TB2> INFO: 32136500 events read in total (1086041ms).
[16:21:47.998] <TB2> INFO: 32813950 events read in total (1108953ms).
[16:22:11.076] <TB2> INFO: 33492550 events read in total (1132031ms).
[16:22:34.444] <TB2> INFO: 34171600 events read in total (1155399ms).
[16:22:57.669] <TB2> INFO: 34852050 events read in total (1178624ms).
[16:23:20.881] <TB2> INFO: 35533450 events read in total (1201836ms).
[16:23:44.043] <TB2> INFO: 36223650 events read in total (1224998ms).
[16:23:57.141] <TB2> INFO: 36608000 events read in total (1238096ms).
[16:23:57.206] <TB2> INFO: Test took 1239038ms.
[16:23:57.568] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:23:59.268] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:00.994] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:02.483] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:03.924] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:05.457] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:06.929] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:08.397] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:10.292] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:12.276] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:13.830] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:15.841] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:17.870] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:19.891] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:21.935] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:24.023] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:24:25.552] <TB2> INFO: PixTestScurves::scurves() done
[16:24:25.553] <TB2> INFO: Vcal mean: 130.69 125.83 127.06 129.80 133.80 123.69 124.19 119.89 136.07 135.33 128.47 129.55 130.10 131.01 129.69 125.56
[16:24:25.553] <TB2> INFO: Vcal RMS: 5.92 6.65 6.23 5.88 5.78 5.81 5.70 6.33 5.96 6.58 6.68 6.57 6.34 5.78 6.78 6.43
[16:24:25.553] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1267 seconds
[16:24:25.553] <TB2> INFO: Decoding statistics:
[16:24:25.553] <TB2> INFO: General information:
[16:24:25.553] <TB2> INFO: 16bit words read: 0
[16:24:25.553] <TB2> INFO: valid events total: 0
[16:24:25.553] <TB2> INFO: empty events: 0
[16:24:25.553] <TB2> INFO: valid events with pixels: 0
[16:24:25.553] <TB2> INFO: valid pixel hits: 0
[16:24:25.553] <TB2> INFO: Event errors: 0
[16:24:25.553] <TB2> INFO: start marker: 0
[16:24:25.553] <TB2> INFO: stop marker: 0
[16:24:25.553] <TB2> INFO: overflow: 0
[16:24:25.553] <TB2> INFO: invalid 5bit words: 0
[16:24:25.553] <TB2> INFO: invalid XOR eye diagram: 0
[16:24:25.553] <TB2> INFO: frame (failed synchr.): 0
[16:24:25.553] <TB2> INFO: idle data (no TBM trl): 0
[16:24:25.553] <TB2> INFO: no data (only TBM hdr): 0
[16:24:25.553] <TB2> INFO: TBM errors: 0
[16:24:25.553] <TB2> INFO: flawed TBM headers: 0
[16:24:25.553] <TB2> INFO: flawed TBM trailers: 0
[16:24:25.553] <TB2> INFO: event ID mismatches: 0
[16:24:25.553] <TB2> INFO: ROC errors: 0
[16:24:25.553] <TB2> INFO: missing ROC header(s): 0
[16:24:25.553] <TB2> INFO: misplaced readback start: 0
[16:24:25.553] <TB2> INFO: Pixel decoding errors: 0
[16:24:25.553] <TB2> INFO: pixel data incomplete: 0
[16:24:25.553] <TB2> INFO: pixel address: 0
[16:24:25.553] <TB2> INFO: pulse height fill bit: 0
[16:24:25.553] <TB2> INFO: buffer corruption: 0
[16:24:25.634] <TB2> INFO: ######################################################################
[16:24:25.634] <TB2> INFO: PixTestTrim::doTest()
[16:24:25.634] <TB2> INFO: ######################################################################
[16:24:25.635] <TB2> INFO: ----------------------------------------------------------------------
[16:24:25.635] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[16:24:25.635] <TB2> INFO: ----------------------------------------------------------------------
[16:24:25.677] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[16:24:25.677] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:24:25.691] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:24:25.691] <TB2> INFO: run 1 of 1
[16:24:25.931] <TB2> INFO: Expecting 5025280 events.
[16:24:56.940] <TB2> INFO: 835608 events read in total (30411ms).
[16:25:27.393] <TB2> INFO: 1669704 events read in total (60864ms).
[16:25:57.000] <TB2> INFO: 2500640 events read in total (91471ms).
[16:26:28.121] <TB2> INFO: 3327288 events read in total (121592ms).
[16:26:58.094] <TB2> INFO: 4150928 events read in total (151565ms).
[16:27:28.308] <TB2> INFO: 4974544 events read in total (181779ms).
[16:27:30.646] <TB2> INFO: 5025280 events read in total (184117ms).
[16:27:30.697] <TB2> INFO: Test took 185005ms.
[16:27:47.340] <TB2> INFO: ROC 0 VthrComp = 124
[16:27:47.340] <TB2> INFO: ROC 1 VthrComp = 120
[16:27:47.340] <TB2> INFO: ROC 2 VthrComp = 125
[16:27:47.340] <TB2> INFO: ROC 3 VthrComp = 131
[16:27:47.340] <TB2> INFO: ROC 4 VthrComp = 129
[16:27:47.341] <TB2> INFO: ROC 5 VthrComp = 119
[16:27:47.341] <TB2> INFO: ROC 6 VthrComp = 125
[16:27:47.341] <TB2> INFO: ROC 7 VthrComp = 121
[16:27:47.341] <TB2> INFO: ROC 8 VthrComp = 131
[16:27:47.341] <TB2> INFO: ROC 9 VthrComp = 129
[16:27:47.341] <TB2> INFO: ROC 10 VthrComp = 119
[16:27:47.341] <TB2> INFO: ROC 11 VthrComp = 122
[16:27:47.341] <TB2> INFO: ROC 12 VthrComp = 128
[16:27:47.341] <TB2> INFO: ROC 13 VthrComp = 129
[16:27:47.341] <TB2> INFO: ROC 14 VthrComp = 125
[16:27:47.341] <TB2> INFO: ROC 15 VthrComp = 120
[16:27:47.607] <TB2> INFO: Expecting 41600 events.
[16:27:51.318] <TB2> INFO: 41600 events read in total (3119ms).
[16:27:51.318] <TB2> INFO: Test took 3975ms.
[16:27:51.328] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[16:27:51.328] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:27:51.340] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:27:51.341] <TB2> INFO: run 1 of 1
[16:27:51.619] <TB2> INFO: Expecting 5025280 events.
[16:28:18.774] <TB2> INFO: 592640 events read in total (26564ms).
[16:28:44.140] <TB2> INFO: 1184200 events read in total (51930ms).
[16:29:09.917] <TB2> INFO: 1775832 events read in total (77707ms).
[16:29:35.443] <TB2> INFO: 2367016 events read in total (103233ms).
[16:30:01.190] <TB2> INFO: 2955432 events read in total (128981ms).
[16:30:26.720] <TB2> INFO: 3542752 events read in total (154510ms).
[16:30:52.320] <TB2> INFO: 4128856 events read in total (180110ms).
[16:31:17.870] <TB2> INFO: 4714352 events read in total (205660ms).
[16:31:31.665] <TB2> INFO: 5025280 events read in total (219455ms).
[16:31:31.745] <TB2> INFO: Test took 220405ms.
[16:31:57.532] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 63.5409 for pixel 8/14 mean/min/max = 48.0726/32.2969/63.8482
[16:31:57.532] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 64.6516 for pixel 1/1 mean/min/max = 48.3905/32.1251/64.6559
[16:31:57.533] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 64.0885 for pixel 0/12 mean/min/max = 48.4505/32.7853/64.1157
[16:31:57.533] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.0884 for pixel 51/73 mean/min/max = 47.1465/34.1993/60.0937
[16:31:57.534] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 62.2592 for pixel 12/68 mean/min/max = 46.9821/31.6279/62.3363
[16:31:57.535] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 59.9321 for pixel 3/11 mean/min/max = 45.7747/31.4813/60.0682
[16:31:57.535] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 59.7852 for pixel 25/17 mean/min/max = 45.8889/31.8729/59.9049
[16:31:57.536] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 61.3757 for pixel 14/73 mean/min/max = 47.1519/32.909/61.3949
[16:31:57.536] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 67.9697 for pixel 29/6 mean/min/max = 51.6804/35.3227/68.0382
[16:31:57.537] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 66.455 for pixel 8/79 mean/min/max = 49.7259/32.9635/66.4883
[16:31:57.537] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 63.2513 for pixel 16/9 mean/min/max = 47.6965/31.9104/63.4826
[16:31:57.538] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 63.6248 for pixel 2/79 mean/min/max = 48.1338/32.63/63.6377
[16:31:57.538] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 60.8868 for pixel 0/2 mean/min/max = 46.3854/31.7994/60.9713
[16:31:57.539] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 61.2275 for pixel 11/9 mean/min/max = 46.5634/31.8926/61.2341
[16:31:57.540] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 62.012 for pixel 18/5 mean/min/max = 46.9405/31.8592/62.0218
[16:31:57.540] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 61.092 for pixel 51/3 mean/min/max = 47.3857/33.6676/61.1039
[16:31:57.541] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:31:57.630] <TB2> INFO: Expecting 411648 events.
[16:32:07.106] <TB2> INFO: 411648 events read in total (8882ms).
[16:32:07.115] <TB2> INFO: Expecting 411648 events.
[16:32:16.407] <TB2> INFO: 411648 events read in total (8889ms).
[16:32:16.420] <TB2> INFO: Expecting 411648 events.
[16:32:25.598] <TB2> INFO: 411648 events read in total (8775ms).
[16:32:25.615] <TB2> INFO: Expecting 411648 events.
[16:32:34.972] <TB2> INFO: 411648 events read in total (8954ms).
[16:32:34.987] <TB2> INFO: Expecting 411648 events.
[16:32:44.429] <TB2> INFO: 411648 events read in total (9038ms).
[16:32:44.448] <TB2> INFO: Expecting 411648 events.
[16:32:53.903] <TB2> INFO: 411648 events read in total (9052ms).
[16:32:53.924] <TB2> INFO: Expecting 411648 events.
[16:33:03.315] <TB2> INFO: 411648 events read in total (8988ms).
[16:33:03.338] <TB2> INFO: Expecting 411648 events.
[16:33:12.740] <TB2> INFO: 411648 events read in total (8999ms).
[16:33:12.765] <TB2> INFO: Expecting 411648 events.
[16:33:22.212] <TB2> INFO: 411648 events read in total (9044ms).
[16:33:22.243] <TB2> INFO: Expecting 411648 events.
[16:33:31.666] <TB2> INFO: 411648 events read in total (9020ms).
[16:33:31.705] <TB2> INFO: Expecting 411648 events.
[16:33:41.136] <TB2> INFO: 411648 events read in total (9028ms).
[16:33:41.170] <TB2> INFO: Expecting 411648 events.
[16:33:50.627] <TB2> INFO: 411648 events read in total (9054ms).
[16:33:50.671] <TB2> INFO: Expecting 411648 events.
[16:34:00.035] <TB2> INFO: 411648 events read in total (8961ms).
[16:34:00.077] <TB2> INFO: Expecting 411648 events.
[16:34:09.471] <TB2> INFO: 411648 events read in total (8991ms).
[16:34:09.561] <TB2> INFO: Expecting 411648 events.
[16:34:19.044] <TB2> INFO: 411648 events read in total (9080ms).
[16:34:19.093] <TB2> INFO: Expecting 411648 events.
[16:34:28.565] <TB2> INFO: 411648 events read in total (9069ms).
[16:34:28.646] <TB2> INFO: Test took 151106ms.
[16:34:29.263] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[16:34:29.276] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:34:29.276] <TB2> INFO: run 1 of 1
[16:34:29.543] <TB2> INFO: Expecting 5025280 events.
[16:34:56.356] <TB2> INFO: 592024 events read in total (26221ms).
[16:35:22.024] <TB2> INFO: 1183848 events read in total (51889ms).
[16:35:48.641] <TB2> INFO: 1773984 events read in total (78507ms).
[16:36:15.094] <TB2> INFO: 2364392 events read in total (104959ms).
[16:36:41.326] <TB2> INFO: 2954872 events read in total (131191ms).
[16:37:07.297] <TB2> INFO: 3547864 events read in total (157162ms).
[16:37:33.609] <TB2> INFO: 4143792 events read in total (183474ms).
[16:37:59.925] <TB2> INFO: 4739616 events read in total (209791ms).
[16:38:13.034] <TB2> INFO: 5025280 events read in total (222899ms).
[16:38:13.220] <TB2> INFO: Test took 223945ms.
[16:38:38.307] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 0.778892 .. 147.768522
[16:38:38.633] <TB2> INFO: Expecting 208000 events.
[16:38:48.519] <TB2> INFO: 208000 events read in total (9293ms).
[16:38:48.521] <TB2> INFO: Test took 10212ms.
[16:38:48.600] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 157 (-1/-1) hits flags = 528 (plus default)
[16:38:48.615] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:38:48.615] <TB2> INFO: run 1 of 1
[16:38:48.919] <TB2> INFO: Expecting 5258240 events.
[16:39:15.379] <TB2> INFO: 585584 events read in total (25868ms).
[16:39:41.363] <TB2> INFO: 1170936 events read in total (51853ms).
[16:40:07.343] <TB2> INFO: 1756032 events read in total (77832ms).
[16:40:33.518] <TB2> INFO: 2341688 events read in total (104007ms).
[16:40:59.224] <TB2> INFO: 2926920 events read in total (129713ms).
[16:41:25.403] <TB2> INFO: 3512128 events read in total (155892ms).
[16:41:51.341] <TB2> INFO: 4097528 events read in total (181830ms).
[16:42:17.257] <TB2> INFO: 4682064 events read in total (207746ms).
[16:42:42.633] <TB2> INFO: 5258240 events read in total (233122ms).
[16:42:42.789] <TB2> INFO: Test took 234175ms.
[16:43:08.761] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.543432 .. 47.688473
[16:43:09.052] <TB2> INFO: Expecting 208000 events.
[16:43:19.335] <TB2> INFO: 208000 events read in total (9692ms).
[16:43:19.336] <TB2> INFO: Test took 10572ms.
[16:43:19.384] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 57 (-1/-1) hits flags = 528 (plus default)
[16:43:19.398] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:43:19.398] <TB2> INFO: run 1 of 1
[16:43:19.676] <TB2> INFO: Expecting 1364480 events.
[16:43:48.671] <TB2> INFO: 655816 events read in total (28404ms).
[16:44:16.046] <TB2> INFO: 1309536 events read in total (55780ms).
[16:44:18.774] <TB2> INFO: 1364480 events read in total (58507ms).
[16:44:18.819] <TB2> INFO: Test took 59422ms.
[16:44:32.950] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 27.919041 .. 49.090675
[16:44:33.203] <TB2> INFO: Expecting 208000 events.
[16:44:43.466] <TB2> INFO: 208000 events read in total (9672ms).
[16:44:43.468] <TB2> INFO: Test took 10512ms.
[16:44:43.540] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 59 (-1/-1) hits flags = 528 (plus default)
[16:44:43.554] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:44:43.554] <TB2> INFO: run 1 of 1
[16:44:43.832] <TB2> INFO: Expecting 1431040 events.
[16:45:12.162] <TB2> INFO: 647120 events read in total (27738ms).
[16:45:39.343] <TB2> INFO: 1293312 events read in total (54919ms).
[16:45:45.524] <TB2> INFO: 1431040 events read in total (61100ms).
[16:45:45.561] <TB2> INFO: Test took 62007ms.
[16:46:00.238] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 26.003775 .. 50.118374
[16:46:00.490] <TB2> INFO: Expecting 208000 events.
[16:46:10.497] <TB2> INFO: 208000 events read in total (9416ms).
[16:46:10.498] <TB2> INFO: Test took 10258ms.
[16:46:10.548] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 60 (-1/-1) hits flags = 528 (plus default)
[16:46:10.562] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:46:10.562] <TB2> INFO: run 1 of 1
[16:46:10.844] <TB2> INFO: Expecting 1497600 events.
[16:46:38.945] <TB2> INFO: 646592 events read in total (27509ms).
[16:47:06.516] <TB2> INFO: 1292400 events read in total (55080ms).
[16:47:15.459] <TB2> INFO: 1497600 events read in total (64023ms).
[16:47:15.491] <TB2> INFO: Test took 64930ms.
[16:47:29.426] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[16:47:29.426] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[16:47:29.440] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:47:29.440] <TB2> INFO: run 1 of 1
[16:47:29.684] <TB2> INFO: Expecting 1364480 events.
[16:47:57.764] <TB2> INFO: 668888 events read in total (27488ms).
[16:48:25.253] <TB2> INFO: 1336160 events read in total (54977ms).
[16:48:26.886] <TB2> INFO: 1364480 events read in total (56611ms).
[16:48:26.917] <TB2> INFO: Test took 57477ms.
[16:48:41.720] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C0.dat
[16:48:41.720] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C1.dat
[16:48:41.720] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C2.dat
[16:48:41.720] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C3.dat
[16:48:41.720] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C4.dat
[16:48:41.720] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C5.dat
[16:48:41.720] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C6.dat
[16:48:41.720] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C7.dat
[16:48:41.720] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C8.dat
[16:48:41.720] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C9.dat
[16:48:41.720] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C10.dat
[16:48:41.721] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C11.dat
[16:48:41.721] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C12.dat
[16:48:41.721] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C13.dat
[16:48:41.721] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C14.dat
[16:48:41.721] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C15.dat
[16:48:41.721] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C0.dat
[16:48:41.728] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C1.dat
[16:48:41.735] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C2.dat
[16:48:41.741] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C3.dat
[16:48:41.748] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C4.dat
[16:48:41.754] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C5.dat
[16:48:41.760] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C6.dat
[16:48:41.766] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C7.dat
[16:48:41.773] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C8.dat
[16:48:41.779] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C9.dat
[16:48:41.785] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C10.dat
[16:48:41.792] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C11.dat
[16:48:41.798] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C12.dat
[16:48:41.804] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C13.dat
[16:48:41.811] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C14.dat
[16:48:41.818] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C15.dat
[16:48:41.824] <TB2> INFO: PixTestTrim::trimTest() done
[16:48:41.824] <TB2> INFO: vtrim: 141 133 116 121 143 122 118 109 143 135 123 131 115 131 135 111
[16:48:41.824] <TB2> INFO: vthrcomp: 124 120 125 131 129 119 125 121 131 129 119 122 128 129 125 120
[16:48:41.824] <TB2> INFO: vcal mean: 36.09 35.08 35.35 35.04 34.98 34.97 34.97 35.02 35.73 35.62 35.86 35.21 35.10 35.15 35.06 35.06
[16:48:41.824] <TB2> INFO: vcal RMS: 2.26 1.28 1.41 1.01 1.23 1.13 1.09 1.02 1.98 1.90 1.99 1.23 1.14 1.25 1.15 1.04
[16:48:41.824] <TB2> INFO: bits mean: 10.02 9.29 8.62 8.46 9.60 9.45 9.71 9.20 8.53 8.91 9.75 8.88 8.81 10.04 9.57 8.63
[16:48:41.824] <TB2> INFO: bits RMS: 2.60 2.69 2.94 2.77 2.65 2.81 2.65 2.68 2.59 2.82 2.77 2.85 3.05 2.51 2.62 2.83
[16:48:41.832] <TB2> INFO: ----------------------------------------------------------------------
[16:48:41.832] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[16:48:41.832] <TB2> INFO: ----------------------------------------------------------------------
[16:48:41.835] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[16:48:41.849] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:48:41.849] <TB2> INFO: run 1 of 1
[16:48:42.133] <TB2> INFO: Expecting 4160000 events.
[16:49:15.576] <TB2> INFO: 779650 events read in total (32852ms).
[16:49:47.930] <TB2> INFO: 1554360 events read in total (65206ms).
[16:50:20.346] <TB2> INFO: 2322215 events read in total (97622ms).
[16:50:52.455] <TB2> INFO: 3084250 events read in total (129731ms).
[16:51:24.638] <TB2> INFO: 3846245 events read in total (161914ms).
[16:51:37.931] <TB2> INFO: 4160000 events read in total (175207ms).
[16:51:38.014] <TB2> INFO: Test took 176164ms.
[16:52:04.654] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[16:52:04.668] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:52:04.668] <TB2> INFO: run 1 of 1
[16:52:04.994] <TB2> INFO: Expecting 5324800 events.
[16:52:36.535] <TB2> INFO: 688675 events read in total (30950ms).
[16:53:07.010] <TB2> INFO: 1374910 events read in total (61425ms).
[16:53:37.186] <TB2> INFO: 2060320 events read in total (91601ms).
[16:54:07.242] <TB2> INFO: 2742320 events read in total (121657ms).
[16:54:37.478] <TB2> INFO: 3422015 events read in total (151893ms).
[16:55:07.782] <TB2> INFO: 4101345 events read in total (182197ms).
[16:55:38.555] <TB2> INFO: 4779715 events read in total (212970ms).
[16:56:02.375] <TB2> INFO: 5324800 events read in total (236790ms).
[16:56:02.512] <TB2> INFO: Test took 237844ms.
[16:56:33.918] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[16:56:33.931] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:56:33.932] <TB2> INFO: run 1 of 1
[16:56:34.175] <TB2> INFO: Expecting 4284800 events.
[16:57:05.963] <TB2> INFO: 741910 events read in total (31196ms).
[16:57:37.340] <TB2> INFO: 1480140 events read in total (62573ms).
[16:58:08.704] <TB2> INFO: 2213520 events read in total (93937ms).
[16:58:39.990] <TB2> INFO: 2942860 events read in total (125223ms).
[16:59:12.155] <TB2> INFO: 3670650 events read in total (157388ms).
[16:59:38.874] <TB2> INFO: 4284800 events read in total (184107ms).
[16:59:39.009] <TB2> INFO: Test took 185077ms.
[17:00:03.593] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[17:00:03.606] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:00:03.606] <TB2> INFO: run 1 of 1
[17:00:03.842] <TB2> INFO: Expecting 4243200 events.
[17:00:35.939] <TB2> INFO: 744630 events read in total (31505ms).
[17:01:07.757] <TB2> INFO: 1486050 events read in total (63323ms).
[17:01:40.050] <TB2> INFO: 2222290 events read in total (95616ms).
[17:02:11.551] <TB2> INFO: 2954390 events read in total (127117ms).
[17:02:42.672] <TB2> INFO: 3684990 events read in total (158238ms).
[17:03:06.554] <TB2> INFO: 4243200 events read in total (182120ms).
[17:03:06.704] <TB2> INFO: Test took 183098ms.
[17:03:32.756] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[17:03:32.770] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:03:32.770] <TB2> INFO: run 1 of 1
[17:03:33.015] <TB2> INFO: Expecting 4264000 events.
[17:04:05.218] <TB2> INFO: 743515 events read in total (31612ms).
[17:04:36.709] <TB2> INFO: 1483535 events read in total (63103ms).
[17:05:08.215] <TB2> INFO: 2218440 events read in total (94610ms).
[17:05:39.252] <TB2> INFO: 2949040 events read in total (125646ms).
[17:06:10.481] <TB2> INFO: 3677830 events read in total (156875ms).
[17:06:35.549] <TB2> INFO: 4264000 events read in total (181944ms).
[17:06:35.626] <TB2> INFO: Test took 182856ms.
[17:07:01.232] <TB2> INFO: PixTestTrim::trimBitTest() done
[17:07:01.233] <TB2> INFO: PixTestTrim::doTest() done, duration: 2555 seconds
[17:07:01.233] <TB2> INFO: Decoding statistics:
[17:07:01.233] <TB2> INFO: General information:
[17:07:01.233] <TB2> INFO: 16bit words read: 0
[17:07:01.233] <TB2> INFO: valid events total: 0
[17:07:01.233] <TB2> INFO: empty events: 0
[17:07:01.233] <TB2> INFO: valid events with pixels: 0
[17:07:01.233] <TB2> INFO: valid pixel hits: 0
[17:07:01.233] <TB2> INFO: Event errors: 0
[17:07:01.233] <TB2> INFO: start marker: 0
[17:07:01.233] <TB2> INFO: stop marker: 0
[17:07:01.233] <TB2> INFO: overflow: 0
[17:07:01.233] <TB2> INFO: invalid 5bit words: 0
[17:07:01.233] <TB2> INFO: invalid XOR eye diagram: 0
[17:07:01.233] <TB2> INFO: frame (failed synchr.): 0
[17:07:01.233] <TB2> INFO: idle data (no TBM trl): 0
[17:07:01.233] <TB2> INFO: no data (only TBM hdr): 0
[17:07:01.233] <TB2> INFO: TBM errors: 0
[17:07:01.233] <TB2> INFO: flawed TBM headers: 0
[17:07:01.233] <TB2> INFO: flawed TBM trailers: 0
[17:07:01.233] <TB2> INFO: event ID mismatches: 0
[17:07:01.233] <TB2> INFO: ROC errors: 0
[17:07:01.233] <TB2> INFO: missing ROC header(s): 0
[17:07:01.233] <TB2> INFO: misplaced readback start: 0
[17:07:01.233] <TB2> INFO: Pixel decoding errors: 0
[17:07:01.233] <TB2> INFO: pixel data incomplete: 0
[17:07:01.233] <TB2> INFO: pixel address: 0
[17:07:01.233] <TB2> INFO: pulse height fill bit: 0
[17:07:01.233] <TB2> INFO: buffer corruption: 0
[17:07:01.884] <TB2> INFO: ######################################################################
[17:07:01.884] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[17:07:01.884] <TB2> INFO: ######################################################################
[17:07:02.165] <TB2> INFO: Expecting 41600 events.
[17:07:05.618] <TB2> INFO: 41600 events read in total (2861ms).
[17:07:05.619] <TB2> INFO: Test took 3734ms.
[17:07:06.058] <TB2> INFO: Expecting 41600 events.
[17:07:09.641] <TB2> INFO: 41600 events read in total (2992ms).
[17:07:09.643] <TB2> INFO: Test took 3821ms.
[17:07:09.936] <TB2> INFO: Expecting 41600 events.
[17:07:13.620] <TB2> INFO: 41600 events read in total (3092ms).
[17:07:13.621] <TB2> INFO: Test took 3951ms.
[17:07:13.915] <TB2> INFO: Expecting 41600 events.
[17:07:17.649] <TB2> INFO: 41600 events read in total (3142ms).
[17:07:17.650] <TB2> INFO: Test took 4004ms.
[17:07:17.942] <TB2> INFO: Expecting 41600 events.
[17:07:21.619] <TB2> INFO: 41600 events read in total (3086ms).
[17:07:21.620] <TB2> INFO: Test took 3943ms.
[17:07:21.909] <TB2> INFO: Expecting 41600 events.
[17:07:25.516] <TB2> INFO: 41600 events read in total (3015ms).
[17:07:25.517] <TB2> INFO: Test took 3873ms.
[17:07:25.806] <TB2> INFO: Expecting 41600 events.
[17:07:29.361] <TB2> INFO: 41600 events read in total (2963ms).
[17:07:29.362] <TB2> INFO: Test took 3821ms.
[17:07:29.654] <TB2> INFO: Expecting 41600 events.
[17:07:33.156] <TB2> INFO: 41600 events read in total (2910ms).
[17:07:33.157] <TB2> INFO: Test took 3768ms.
[17:07:33.446] <TB2> INFO: Expecting 41600 events.
[17:07:36.943] <TB2> INFO: 41600 events read in total (2905ms).
[17:07:36.944] <TB2> INFO: Test took 3763ms.
[17:07:37.234] <TB2> INFO: Expecting 41600 events.
[17:07:40.855] <TB2> INFO: 41600 events read in total (3029ms).
[17:07:40.856] <TB2> INFO: Test took 3888ms.
[17:07:41.147] <TB2> INFO: Expecting 41600 events.
[17:07:44.662] <TB2> INFO: 41600 events read in total (2924ms).
[17:07:44.662] <TB2> INFO: Test took 3781ms.
[17:07:44.952] <TB2> INFO: Expecting 41600 events.
[17:07:48.412] <TB2> INFO: 41600 events read in total (2868ms).
[17:07:48.413] <TB2> INFO: Test took 3726ms.
[17:07:48.760] <TB2> INFO: Expecting 41600 events.
[17:07:52.459] <TB2> INFO: 41600 events read in total (3107ms).
[17:07:52.460] <TB2> INFO: Test took 4022ms.
[17:07:52.754] <TB2> INFO: Expecting 41600 events.
[17:07:56.252] <TB2> INFO: 41600 events read in total (2906ms).
[17:07:56.253] <TB2> INFO: Test took 3764ms.
[17:07:56.573] <TB2> INFO: Expecting 41600 events.
[17:08:00.066] <TB2> INFO: 41600 events read in total (2901ms).
[17:08:00.066] <TB2> INFO: Test took 3788ms.
[17:08:00.356] <TB2> INFO: Expecting 41600 events.
[17:08:03.911] <TB2> INFO: 41600 events read in total (2963ms).
[17:08:03.912] <TB2> INFO: Test took 3821ms.
[17:08:04.208] <TB2> INFO: Expecting 41600 events.
[17:08:07.887] <TB2> INFO: 41600 events read in total (3087ms).
[17:08:07.888] <TB2> INFO: Test took 3950ms.
[17:08:08.179] <TB2> INFO: Expecting 41600 events.
[17:08:11.766] <TB2> INFO: 41600 events read in total (2996ms).
[17:08:11.767] <TB2> INFO: Test took 3854ms.
[17:08:12.059] <TB2> INFO: Expecting 41600 events.
[17:08:15.671] <TB2> INFO: 41600 events read in total (3020ms).
[17:08:15.672] <TB2> INFO: Test took 3878ms.
[17:08:15.963] <TB2> INFO: Expecting 41600 events.
[17:08:19.468] <TB2> INFO: 41600 events read in total (2914ms).
[17:08:19.469] <TB2> INFO: Test took 3772ms.
[17:08:19.763] <TB2> INFO: Expecting 41600 events.
[17:08:23.238] <TB2> INFO: 41600 events read in total (2883ms).
[17:08:23.240] <TB2> INFO: Test took 3742ms.
[17:08:23.533] <TB2> INFO: Expecting 41600 events.
[17:08:27.069] <TB2> INFO: 41600 events read in total (2944ms).
[17:08:27.070] <TB2> INFO: Test took 3802ms.
[17:08:27.359] <TB2> INFO: Expecting 41600 events.
[17:08:30.948] <TB2> INFO: 41600 events read in total (2997ms).
[17:08:30.949] <TB2> INFO: Test took 3855ms.
[17:08:31.254] <TB2> INFO: Expecting 41600 events.
[17:08:34.746] <TB2> INFO: 41600 events read in total (2900ms).
[17:08:34.748] <TB2> INFO: Test took 3773ms.
[17:08:35.040] <TB2> INFO: Expecting 41600 events.
[17:08:38.616] <TB2> INFO: 41600 events read in total (2985ms).
[17:08:38.617] <TB2> INFO: Test took 3842ms.
[17:08:38.907] <TB2> INFO: Expecting 41600 events.
[17:08:42.419] <TB2> INFO: 41600 events read in total (2920ms).
[17:08:42.419] <TB2> INFO: Test took 3778ms.
[17:08:42.709] <TB2> INFO: Expecting 41600 events.
[17:08:46.225] <TB2> INFO: 41600 events read in total (2924ms).
[17:08:46.226] <TB2> INFO: Test took 3782ms.
[17:08:46.517] <TB2> INFO: Expecting 41600 events.
[17:08:50.048] <TB2> INFO: 41600 events read in total (2939ms).
[17:08:50.048] <TB2> INFO: Test took 3796ms.
[17:08:50.340] <TB2> INFO: Expecting 2560 events.
[17:08:51.224] <TB2> INFO: 2560 events read in total (293ms).
[17:08:51.224] <TB2> INFO: Test took 1162ms.
[17:08:51.532] <TB2> INFO: Expecting 2560 events.
[17:08:52.421] <TB2> INFO: 2560 events read in total (297ms).
[17:08:52.421] <TB2> INFO: Test took 1196ms.
[17:08:52.729] <TB2> INFO: Expecting 2560 events.
[17:08:53.615] <TB2> INFO: 2560 events read in total (294ms).
[17:08:53.615] <TB2> INFO: Test took 1194ms.
[17:08:53.921] <TB2> INFO: Expecting 2560 events.
[17:08:54.805] <TB2> INFO: 2560 events read in total (292ms).
[17:08:54.805] <TB2> INFO: Test took 1189ms.
[17:08:55.113] <TB2> INFO: Expecting 2560 events.
[17:08:55.996] <TB2> INFO: 2560 events read in total (292ms).
[17:08:55.996] <TB2> INFO: Test took 1190ms.
[17:08:56.304] <TB2> INFO: Expecting 2560 events.
[17:08:57.186] <TB2> INFO: 2560 events read in total (290ms).
[17:08:57.186] <TB2> INFO: Test took 1190ms.
[17:08:57.494] <TB2> INFO: Expecting 2560 events.
[17:08:58.372] <TB2> INFO: 2560 events read in total (286ms).
[17:08:58.372] <TB2> INFO: Test took 1185ms.
[17:08:58.680] <TB2> INFO: Expecting 2560 events.
[17:08:59.562] <TB2> INFO: 2560 events read in total (290ms).
[17:08:59.562] <TB2> INFO: Test took 1189ms.
[17:08:59.870] <TB2> INFO: Expecting 2560 events.
[17:09:00.749] <TB2> INFO: 2560 events read in total (287ms).
[17:09:00.750] <TB2> INFO: Test took 1188ms.
[17:09:01.057] <TB2> INFO: Expecting 2560 events.
[17:09:01.943] <TB2> INFO: 2560 events read in total (294ms).
[17:09:01.943] <TB2> INFO: Test took 1193ms.
[17:09:02.251] <TB2> INFO: Expecting 2560 events.
[17:09:03.135] <TB2> INFO: 2560 events read in total (292ms).
[17:09:03.135] <TB2> INFO: Test took 1191ms.
[17:09:03.443] <TB2> INFO: Expecting 2560 events.
[17:09:04.323] <TB2> INFO: 2560 events read in total (288ms).
[17:09:04.323] <TB2> INFO: Test took 1187ms.
[17:09:04.631] <TB2> INFO: Expecting 2560 events.
[17:09:05.515] <TB2> INFO: 2560 events read in total (292ms).
[17:09:05.515] <TB2> INFO: Test took 1192ms.
[17:09:05.824] <TB2> INFO: Expecting 2560 events.
[17:09:06.722] <TB2> INFO: 2560 events read in total (306ms).
[17:09:06.722] <TB2> INFO: Test took 1206ms.
[17:09:07.030] <TB2> INFO: Expecting 2560 events.
[17:09:07.927] <TB2> INFO: 2560 events read in total (305ms).
[17:09:07.927] <TB2> INFO: Test took 1204ms.
[17:09:08.235] <TB2> INFO: Expecting 2560 events.
[17:09:09.126] <TB2> INFO: 2560 events read in total (299ms).
[17:09:09.127] <TB2> INFO: Test took 1199ms.
[17:09:09.131] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:09.436] <TB2> INFO: Expecting 655360 events.
[17:09:24.192] <TB2> INFO: 655360 events read in total (14165ms).
[17:09:24.204] <TB2> INFO: Expecting 655360 events.
[17:09:38.731] <TB2> INFO: 655360 events read in total (14124ms).
[17:09:38.747] <TB2> INFO: Expecting 655360 events.
[17:09:53.258] <TB2> INFO: 655360 events read in total (14108ms).
[17:09:53.280] <TB2> INFO: Expecting 655360 events.
[17:10:07.510] <TB2> INFO: 655360 events read in total (13827ms).
[17:10:07.538] <TB2> INFO: Expecting 655360 events.
[17:10:21.796] <TB2> INFO: 655360 events read in total (13855ms).
[17:10:21.825] <TB2> INFO: Expecting 655360 events.
[17:10:36.565] <TB2> INFO: 655360 events read in total (14337ms).
[17:10:36.600] <TB2> INFO: Expecting 655360 events.
[17:10:51.276] <TB2> INFO: 655360 events read in total (14272ms).
[17:10:51.335] <TB2> INFO: Expecting 655360 events.
[17:11:06.132] <TB2> INFO: 655360 events read in total (14394ms).
[17:11:06.188] <TB2> INFO: Expecting 655360 events.
[17:11:20.955] <TB2> INFO: 655360 events read in total (14364ms).
[17:11:21.014] <TB2> INFO: Expecting 655360 events.
[17:11:35.757] <TB2> INFO: 655360 events read in total (14340ms).
[17:11:35.812] <TB2> INFO: Expecting 655360 events.
[17:11:50.459] <TB2> INFO: 655360 events read in total (14244ms).
[17:11:50.561] <TB2> INFO: Expecting 655360 events.
[17:12:05.337] <TB2> INFO: 655360 events read in total (14373ms).
[17:12:05.438] <TB2> INFO: Expecting 655360 events.
[17:12:20.144] <TB2> INFO: 655360 events read in total (14303ms).
[17:12:20.227] <TB2> INFO: Expecting 655360 events.
[17:12:35.109] <TB2> INFO: 655360 events read in total (14479ms).
[17:12:35.204] <TB2> INFO: Expecting 655360 events.
[17:12:50.046] <TB2> INFO: 655360 events read in total (14439ms).
[17:12:50.140] <TB2> INFO: Expecting 655360 events.
[17:13:04.873] <TB2> INFO: 655360 events read in total (14330ms).
[17:13:05.032] <TB2> INFO: Test took 235901ms.
[17:13:05.128] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:13:05.385] <TB2> INFO: Expecting 655360 events.
[17:13:20.106] <TB2> INFO: 655360 events read in total (14129ms).
[17:13:20.121] <TB2> INFO: Expecting 655360 events.
[17:13:34.786] <TB2> INFO: 655360 events read in total (14261ms).
[17:13:34.807] <TB2> INFO: Expecting 655360 events.
[17:13:49.456] <TB2> INFO: 655360 events read in total (14246ms).
[17:13:49.482] <TB2> INFO: Expecting 655360 events.
[17:14:04.122] <TB2> INFO: 655360 events read in total (14237ms).
[17:14:04.147] <TB2> INFO: Expecting 655360 events.
[17:14:18.867] <TB2> INFO: 655360 events read in total (14317ms).
[17:14:18.905] <TB2> INFO: Expecting 655360 events.
[17:14:33.630] <TB2> INFO: 655360 events read in total (14322ms).
[17:14:33.672] <TB2> INFO: Expecting 655360 events.
[17:14:48.431] <TB2> INFO: 655360 events read in total (14356ms).
[17:14:48.473] <TB2> INFO: Expecting 655360 events.
[17:15:02.914] <TB2> INFO: 655360 events read in total (14038ms).
[17:15:02.957] <TB2> INFO: Expecting 655360 events.
[17:15:17.375] <TB2> INFO: 655360 events read in total (14014ms).
[17:15:17.433] <TB2> INFO: Expecting 655360 events.
[17:15:31.755] <TB2> INFO: 655360 events read in total (13919ms).
[17:15:31.807] <TB2> INFO: Expecting 655360 events.
[17:15:46.267] <TB2> INFO: 655360 events read in total (14057ms).
[17:15:46.337] <TB2> INFO: Expecting 655360 events.
[17:16:00.814] <TB2> INFO: 655360 events read in total (14074ms).
[17:16:00.889] <TB2> INFO: Expecting 655360 events.
[17:16:15.575] <TB2> INFO: 655360 events read in total (14283ms).
[17:16:15.692] <TB2> INFO: Expecting 655360 events.
[17:16:30.567] <TB2> INFO: 655360 events read in total (14472ms).
[17:16:30.670] <TB2> INFO: Expecting 655360 events.
[17:16:45.514] <TB2> INFO: 655360 events read in total (14441ms).
[17:16:45.611] <TB2> INFO: Expecting 655360 events.
[17:17:00.479] <TB2> INFO: 655360 events read in total (14465ms).
[17:17:00.576] <TB2> INFO: Test took 235448ms.
[17:17:00.746] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.752] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.758] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.765] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:17:00.770] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.776] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.781] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.787] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.793] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.798] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:17:00.804] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.810] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.815] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.821] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.827] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:17:00.832] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[17:17:00.838] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.843] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.849] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:17:00.855] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[17:17:00.861] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[17:17:00.868] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[17:17:00.874] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.880] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:17:00.886] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[17:17:00.892] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[17:17:00.898] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:17:00.935] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C0.dat
[17:17:00.935] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C1.dat
[17:17:00.935] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C2.dat
[17:17:00.935] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C3.dat
[17:17:00.935] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C4.dat
[17:17:00.935] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C5.dat
[17:17:00.935] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C6.dat
[17:17:00.935] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C7.dat
[17:17:00.936] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C8.dat
[17:17:00.936] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C9.dat
[17:17:00.936] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C10.dat
[17:17:00.936] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C11.dat
[17:17:00.936] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C12.dat
[17:17:00.936] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C13.dat
[17:17:00.936] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C14.dat
[17:17:00.936] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C15.dat
[17:17:01.178] <TB2> INFO: Expecting 41600 events.
[17:17:04.354] <TB2> INFO: 41600 events read in total (2584ms).
[17:17:04.355] <TB2> INFO: Test took 3415ms.
[17:17:04.811] <TB2> INFO: Expecting 41600 events.
[17:17:07.905] <TB2> INFO: 41600 events read in total (2502ms).
[17:17:07.906] <TB2> INFO: Test took 3334ms.
[17:17:08.394] <TB2> INFO: Expecting 41600 events.
[17:17:11.586] <TB2> INFO: 41600 events read in total (2600ms).
[17:17:11.587] <TB2> INFO: Test took 3469ms.
[17:17:11.806] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:11.895] <TB2> INFO: Expecting 2560 events.
[17:17:12.788] <TB2> INFO: 2560 events read in total (301ms).
[17:17:12.788] <TB2> INFO: Test took 982ms.
[17:17:12.791] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:13.095] <TB2> INFO: Expecting 2560 events.
[17:17:13.989] <TB2> INFO: 2560 events read in total (302ms).
[17:17:13.990] <TB2> INFO: Test took 1199ms.
[17:17:13.994] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:14.298] <TB2> INFO: Expecting 2560 events.
[17:17:15.192] <TB2> INFO: 2560 events read in total (302ms).
[17:17:15.193] <TB2> INFO: Test took 1199ms.
[17:17:15.198] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:15.500] <TB2> INFO: Expecting 2560 events.
[17:17:16.394] <TB2> INFO: 2560 events read in total (302ms).
[17:17:16.394] <TB2> INFO: Test took 1196ms.
[17:17:16.397] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:16.702] <TB2> INFO: Expecting 2560 events.
[17:17:17.591] <TB2> INFO: 2560 events read in total (296ms).
[17:17:17.592] <TB2> INFO: Test took 1195ms.
[17:17:17.594] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:17.899] <TB2> INFO: Expecting 2560 events.
[17:17:18.793] <TB2> INFO: 2560 events read in total (302ms).
[17:17:18.793] <TB2> INFO: Test took 1199ms.
[17:17:18.796] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:19.101] <TB2> INFO: Expecting 2560 events.
[17:17:19.998] <TB2> INFO: 2560 events read in total (303ms).
[17:17:19.999] <TB2> INFO: Test took 1203ms.
[17:17:20.004] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:20.307] <TB2> INFO: Expecting 2560 events.
[17:17:21.192] <TB2> INFO: 2560 events read in total (294ms).
[17:17:21.192] <TB2> INFO: Test took 1188ms.
[17:17:21.195] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:21.500] <TB2> INFO: Expecting 2560 events.
[17:17:22.385] <TB2> INFO: 2560 events read in total (293ms).
[17:17:22.386] <TB2> INFO: Test took 1191ms.
[17:17:22.388] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:22.695] <TB2> INFO: Expecting 2560 events.
[17:17:23.586] <TB2> INFO: 2560 events read in total (300ms).
[17:17:23.587] <TB2> INFO: Test took 1199ms.
[17:17:23.590] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:23.895] <TB2> INFO: Expecting 2560 events.
[17:17:24.785] <TB2> INFO: 2560 events read in total (298ms).
[17:17:24.785] <TB2> INFO: Test took 1195ms.
[17:17:24.791] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:25.093] <TB2> INFO: Expecting 2560 events.
[17:17:25.972] <TB2> INFO: 2560 events read in total (287ms).
[17:17:25.973] <TB2> INFO: Test took 1182ms.
[17:17:25.975] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:26.282] <TB2> INFO: Expecting 2560 events.
[17:17:27.173] <TB2> INFO: 2560 events read in total (299ms).
[17:17:27.173] <TB2> INFO: Test took 1199ms.
[17:17:27.176] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:27.481] <TB2> INFO: Expecting 2560 events.
[17:17:28.371] <TB2> INFO: 2560 events read in total (298ms).
[17:17:28.371] <TB2> INFO: Test took 1195ms.
[17:17:28.375] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:28.679] <TB2> INFO: Expecting 2560 events.
[17:17:29.563] <TB2> INFO: 2560 events read in total (291ms).
[17:17:29.563] <TB2> INFO: Test took 1188ms.
[17:17:29.566] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:29.871] <TB2> INFO: Expecting 2560 events.
[17:17:30.762] <TB2> INFO: 2560 events read in total (299ms).
[17:17:30.763] <TB2> INFO: Test took 1197ms.
[17:17:30.766] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:31.070] <TB2> INFO: Expecting 2560 events.
[17:17:31.959] <TB2> INFO: 2560 events read in total (297ms).
[17:17:31.960] <TB2> INFO: Test took 1195ms.
[17:17:31.963] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:32.268] <TB2> INFO: Expecting 2560 events.
[17:17:33.156] <TB2> INFO: 2560 events read in total (296ms).
[17:17:33.157] <TB2> INFO: Test took 1195ms.
[17:17:33.160] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:33.464] <TB2> INFO: Expecting 2560 events.
[17:17:34.346] <TB2> INFO: 2560 events read in total (290ms).
[17:17:34.347] <TB2> INFO: Test took 1188ms.
[17:17:34.350] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:34.653] <TB2> INFO: Expecting 2560 events.
[17:17:35.541] <TB2> INFO: 2560 events read in total (296ms).
[17:17:35.542] <TB2> INFO: Test took 1192ms.
[17:17:35.545] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:35.850] <TB2> INFO: Expecting 2560 events.
[17:17:36.741] <TB2> INFO: 2560 events read in total (299ms).
[17:17:36.742] <TB2> INFO: Test took 1197ms.
[17:17:36.746] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:37.050] <TB2> INFO: Expecting 2560 events.
[17:17:37.940] <TB2> INFO: 2560 events read in total (298ms).
[17:17:37.940] <TB2> INFO: Test took 1195ms.
[17:17:37.943] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:38.248] <TB2> INFO: Expecting 2560 events.
[17:17:39.128] <TB2> INFO: 2560 events read in total (288ms).
[17:17:39.129] <TB2> INFO: Test took 1186ms.
[17:17:39.132] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:39.437] <TB2> INFO: Expecting 2560 events.
[17:17:40.329] <TB2> INFO: 2560 events read in total (300ms).
[17:17:40.330] <TB2> INFO: Test took 1198ms.
[17:17:40.334] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:40.637] <TB2> INFO: Expecting 2560 events.
[17:17:41.527] <TB2> INFO: 2560 events read in total (298ms).
[17:17:41.527] <TB2> INFO: Test took 1193ms.
[17:17:41.531] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:41.834] <TB2> INFO: Expecting 2560 events.
[17:17:42.719] <TB2> INFO: 2560 events read in total (293ms).
[17:17:42.719] <TB2> INFO: Test took 1189ms.
[17:17:42.723] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:43.027] <TB2> INFO: Expecting 2560 events.
[17:17:43.920] <TB2> INFO: 2560 events read in total (302ms).
[17:17:43.921] <TB2> INFO: Test took 1198ms.
[17:17:43.923] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:44.228] <TB2> INFO: Expecting 2560 events.
[17:17:45.124] <TB2> INFO: 2560 events read in total (304ms).
[17:17:45.124] <TB2> INFO: Test took 1201ms.
[17:17:45.126] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:45.433] <TB2> INFO: Expecting 2560 events.
[17:17:46.316] <TB2> INFO: 2560 events read in total (291ms).
[17:17:46.316] <TB2> INFO: Test took 1190ms.
[17:17:46.319] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:46.625] <TB2> INFO: Expecting 2560 events.
[17:17:47.523] <TB2> INFO: 2560 events read in total (306ms).
[17:17:47.524] <TB2> INFO: Test took 1206ms.
[17:17:47.528] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:47.832] <TB2> INFO: Expecting 2560 events.
[17:17:48.718] <TB2> INFO: 2560 events read in total (294ms).
[17:17:48.719] <TB2> INFO: Test took 1192ms.
[17:17:48.722] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:49.027] <TB2> INFO: Expecting 2560 events.
[17:17:49.917] <TB2> INFO: 2560 events read in total (298ms).
[17:17:49.917] <TB2> INFO: Test took 1195ms.
[17:17:50.393] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 648 seconds
[17:17:50.393] <TB2> INFO: PH scale (per ROC): 41 35 49 42 53 36 39 29 36 43 30 35 42 34 29 38
[17:17:50.393] <TB2> INFO: PH offset (per ROC): 101 111 123 109 123 92 97 113 98 103 83 98 96 95 97 99
[17:17:50.400] <TB2> INFO: Decoding statistics:
[17:17:50.400] <TB2> INFO: General information:
[17:17:50.400] <TB2> INFO: 16bit words read: 127886
[17:17:50.400] <TB2> INFO: valid events total: 20480
[17:17:50.400] <TB2> INFO: empty events: 17977
[17:17:50.400] <TB2> INFO: valid events with pixels: 2503
[17:17:50.400] <TB2> INFO: valid pixel hits: 2503
[17:17:50.400] <TB2> INFO: Event errors: 0
[17:17:50.400] <TB2> INFO: start marker: 0
[17:17:50.400] <TB2> INFO: stop marker: 0
[17:17:50.400] <TB2> INFO: overflow: 0
[17:17:50.400] <TB2> INFO: invalid 5bit words: 0
[17:17:50.400] <TB2> INFO: invalid XOR eye diagram: 0
[17:17:50.400] <TB2> INFO: frame (failed synchr.): 0
[17:17:50.400] <TB2> INFO: idle data (no TBM trl): 0
[17:17:50.400] <TB2> INFO: no data (only TBM hdr): 0
[17:17:50.400] <TB2> INFO: TBM errors: 0
[17:17:50.400] <TB2> INFO: flawed TBM headers: 0
[17:17:50.400] <TB2> INFO: flawed TBM trailers: 0
[17:17:50.400] <TB2> INFO: event ID mismatches: 0
[17:17:50.400] <TB2> INFO: ROC errors: 0
[17:17:50.400] <TB2> INFO: missing ROC header(s): 0
[17:17:50.400] <TB2> INFO: misplaced readback start: 0
[17:17:50.400] <TB2> INFO: Pixel decoding errors: 0
[17:17:50.400] <TB2> INFO: pixel data incomplete: 0
[17:17:50.400] <TB2> INFO: pixel address: 0
[17:17:50.400] <TB2> INFO: pulse height fill bit: 0
[17:17:50.400] <TB2> INFO: buffer corruption: 0
[17:17:50.564] <TB2> INFO: ######################################################################
[17:17:50.564] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[17:17:50.564] <TB2> INFO: ######################################################################
[17:17:50.578] <TB2> INFO: scanning low vcal = 10
[17:17:50.816] <TB2> INFO: Expecting 41600 events.
[17:17:54.414] <TB2> INFO: 41600 events read in total (3006ms).
[17:17:54.415] <TB2> INFO: Test took 3836ms.
[17:17:54.416] <TB2> INFO: scanning low vcal = 20
[17:17:54.711] <TB2> INFO: Expecting 41600 events.
[17:17:58.300] <TB2> INFO: 41600 events read in total (2997ms).
[17:17:58.300] <TB2> INFO: Test took 3884ms.
[17:17:58.302] <TB2> INFO: scanning low vcal = 30
[17:17:58.595] <TB2> INFO: Expecting 41600 events.
[17:18:02.246] <TB2> INFO: 41600 events read in total (3059ms).
[17:18:02.247] <TB2> INFO: Test took 3945ms.
[17:18:02.250] <TB2> INFO: scanning low vcal = 40
[17:18:02.527] <TB2> INFO: Expecting 41600 events.
[17:18:06.561] <TB2> INFO: 41600 events read in total (3442ms).
[17:18:06.563] <TB2> INFO: Test took 4313ms.
[17:18:06.566] <TB2> INFO: scanning low vcal = 50
[17:18:06.843] <TB2> INFO: Expecting 41600 events.
[17:18:10.862] <TB2> INFO: 41600 events read in total (3427ms).
[17:18:10.863] <TB2> INFO: Test took 4297ms.
[17:18:10.866] <TB2> INFO: scanning low vcal = 60
[17:18:11.143] <TB2> INFO: Expecting 41600 events.
[17:18:15.173] <TB2> INFO: 41600 events read in total (3438ms).
[17:18:15.174] <TB2> INFO: Test took 4308ms.
[17:18:15.177] <TB2> INFO: scanning low vcal = 70
[17:18:15.454] <TB2> INFO: Expecting 41600 events.
[17:18:19.452] <TB2> INFO: 41600 events read in total (3406ms).
[17:18:19.453] <TB2> INFO: Test took 4276ms.
[17:18:19.456] <TB2> INFO: scanning low vcal = 80
[17:18:19.733] <TB2> INFO: Expecting 41600 events.
[17:18:23.786] <TB2> INFO: 41600 events read in total (3461ms).
[17:18:23.787] <TB2> INFO: Test took 4331ms.
[17:18:23.790] <TB2> INFO: scanning low vcal = 90
[17:18:24.068] <TB2> INFO: Expecting 41600 events.
[17:18:28.097] <TB2> INFO: 41600 events read in total (3438ms).
[17:18:28.098] <TB2> INFO: Test took 4308ms.
[17:18:28.102] <TB2> INFO: scanning low vcal = 100
[17:18:28.377] <TB2> INFO: Expecting 41600 events.
[17:18:32.397] <TB2> INFO: 41600 events read in total (3428ms).
[17:18:32.397] <TB2> INFO: Test took 4295ms.
[17:18:32.401] <TB2> INFO: scanning low vcal = 110
[17:18:32.677] <TB2> INFO: Expecting 41600 events.
[17:18:36.724] <TB2> INFO: 41600 events read in total (3455ms).
[17:18:36.725] <TB2> INFO: Test took 4324ms.
[17:18:36.728] <TB2> INFO: scanning low vcal = 120
[17:18:37.006] <TB2> INFO: Expecting 41600 events.
[17:18:40.002] <TB2> INFO: 41600 events read in total (3404ms).
[17:18:40.003] <TB2> INFO: Test took 4275ms.
[17:18:41.006] <TB2> INFO: scanning low vcal = 130
[17:18:41.283] <TB2> INFO: Expecting 41600 events.
[17:18:45.308] <TB2> INFO: 41600 events read in total (3434ms).
[17:18:45.310] <TB2> INFO: Test took 4304ms.
[17:18:45.313] <TB2> INFO: scanning low vcal = 140
[17:18:45.589] <TB2> INFO: Expecting 41600 events.
[17:18:49.593] <TB2> INFO: 41600 events read in total (3412ms).
[17:18:49.594] <TB2> INFO: Test took 4281ms.
[17:18:49.597] <TB2> INFO: scanning low vcal = 150
[17:18:49.874] <TB2> INFO: Expecting 41600 events.
[17:18:53.915] <TB2> INFO: 41600 events read in total (3449ms).
[17:18:53.916] <TB2> INFO: Test took 4319ms.
[17:18:53.919] <TB2> INFO: scanning low vcal = 160
[17:18:54.196] <TB2> INFO: Expecting 41600 events.
[17:18:58.200] <TB2> INFO: 41600 events read in total (3413ms).
[17:18:58.201] <TB2> INFO: Test took 4282ms.
[17:18:58.204] <TB2> INFO: scanning low vcal = 170
[17:18:58.481] <TB2> INFO: Expecting 41600 events.
[17:19:02.466] <TB2> INFO: 41600 events read in total (3394ms).
[17:19:02.467] <TB2> INFO: Test took 4263ms.
[17:19:02.472] <TB2> INFO: scanning low vcal = 180
[17:19:02.747] <TB2> INFO: Expecting 41600 events.
[17:19:06.706] <TB2> INFO: 41600 events read in total (3367ms).
[17:19:06.707] <TB2> INFO: Test took 4235ms.
[17:19:06.710] <TB2> INFO: scanning low vcal = 190
[17:19:06.986] <TB2> INFO: Expecting 41600 events.
[17:19:11.094] <TB2> INFO: 41600 events read in total (3516ms).
[17:19:11.095] <TB2> INFO: Test took 4385ms.
[17:19:11.098] <TB2> INFO: scanning low vcal = 200
[17:19:11.423] <TB2> INFO: Expecting 41600 events.
[17:19:15.385] <TB2> INFO: 41600 events read in total (3370ms).
[17:19:15.386] <TB2> INFO: Test took 4288ms.
[17:19:15.389] <TB2> INFO: scanning low vcal = 210
[17:19:15.666] <TB2> INFO: Expecting 41600 events.
[17:19:19.603] <TB2> INFO: 41600 events read in total (3345ms).
[17:19:19.604] <TB2> INFO: Test took 4215ms.
[17:19:19.607] <TB2> INFO: scanning low vcal = 220
[17:19:19.884] <TB2> INFO: Expecting 41600 events.
[17:19:23.834] <TB2> INFO: 41600 events read in total (3359ms).
[17:19:23.835] <TB2> INFO: Test took 4228ms.
[17:19:23.838] <TB2> INFO: scanning low vcal = 230
[17:19:24.114] <TB2> INFO: Expecting 41600 events.
[17:19:28.076] <TB2> INFO: 41600 events read in total (3370ms).
[17:19:28.077] <TB2> INFO: Test took 4239ms.
[17:19:28.081] <TB2> INFO: scanning low vcal = 240
[17:19:28.357] <TB2> INFO: Expecting 41600 events.
[17:19:32.400] <TB2> INFO: 41600 events read in total (3451ms).
[17:19:32.401] <TB2> INFO: Test took 4320ms.
[17:19:32.405] <TB2> INFO: scanning low vcal = 250
[17:19:32.681] <TB2> INFO: Expecting 41600 events.
[17:19:36.650] <TB2> INFO: 41600 events read in total (3377ms).
[17:19:36.651] <TB2> INFO: Test took 4246ms.
[17:19:36.655] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[17:19:36.931] <TB2> INFO: Expecting 41600 events.
[17:19:40.888] <TB2> INFO: 41600 events read in total (3365ms).
[17:19:40.889] <TB2> INFO: Test took 4234ms.
[17:19:40.892] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[17:19:41.168] <TB2> INFO: Expecting 41600 events.
[17:19:45.162] <TB2> INFO: 41600 events read in total (3403ms).
[17:19:45.164] <TB2> INFO: Test took 4272ms.
[17:19:45.167] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[17:19:45.444] <TB2> INFO: Expecting 41600 events.
[17:19:49.381] <TB2> INFO: 41600 events read in total (3346ms).
[17:19:49.382] <TB2> INFO: Test took 4214ms.
[17:19:49.386] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[17:19:49.662] <TB2> INFO: Expecting 41600 events.
[17:19:53.591] <TB2> INFO: 41600 events read in total (3337ms).
[17:19:53.592] <TB2> INFO: Test took 4207ms.
[17:19:53.597] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[17:19:53.873] <TB2> INFO: Expecting 41600 events.
[17:19:57.843] <TB2> INFO: 41600 events read in total (3378ms).
[17:19:57.844] <TB2> INFO: Test took 4247ms.
[17:19:58.465] <TB2> INFO: PixTestGainPedestal::measure() done
[17:20:37.967] <TB2> INFO: PixTestGainPedestal::fit() done
[17:20:37.967] <TB2> INFO: non-linearity mean: 0.952 0.932 0.984 0.940 0.984 0.927 0.927 1.007 0.943 0.955 1.037 0.955 0.952 0.943 1.001 0.925
[17:20:37.967] <TB2> INFO: non-linearity RMS: 0.079 0.097 0.003 0.086 0.003 0.124 0.106 0.182 0.132 0.036 0.148 0.073 0.100 0.148 0.184 0.102
[17:20:37.967] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[17:20:37.980] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[17:20:37.994] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[17:20:38.007] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[17:20:38.020] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[17:20:38.034] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[17:20:38.047] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[17:20:38.060] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[17:20:38.074] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[17:20:38.087] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[17:20:38.101] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[17:20:38.114] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[17:20:38.128] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[17:20:38.141] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[17:20:38.154] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[17:20:38.168] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[17:20:38.181] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 167 seconds
[17:20:38.181] <TB2> INFO: Decoding statistics:
[17:20:38.181] <TB2> INFO: General information:
[17:20:38.181] <TB2> INFO: 16bit words read: 3279040
[17:20:38.181] <TB2> INFO: valid events total: 332800
[17:20:38.181] <TB2> INFO: empty events: 505
[17:20:38.181] <TB2> INFO: valid events with pixels: 332295
[17:20:38.181] <TB2> INFO: valid pixel hits: 641120
[17:20:38.181] <TB2> INFO: Event errors: 0
[17:20:38.181] <TB2> INFO: start marker: 0
[17:20:38.181] <TB2> INFO: stop marker: 0
[17:20:38.181] <TB2> INFO: overflow: 0
[17:20:38.181] <TB2> INFO: invalid 5bit words: 0
[17:20:38.181] <TB2> INFO: invalid XOR eye diagram: 0
[17:20:38.181] <TB2> INFO: frame (failed synchr.): 0
[17:20:38.181] <TB2> INFO: idle data (no TBM trl): 0
[17:20:38.181] <TB2> INFO: no data (only TBM hdr): 0
[17:20:38.181] <TB2> INFO: TBM errors: 0
[17:20:38.181] <TB2> INFO: flawed TBM headers: 0
[17:20:38.181] <TB2> INFO: flawed TBM trailers: 0
[17:20:38.181] <TB2> INFO: event ID mismatches: 0
[17:20:38.181] <TB2> INFO: ROC errors: 0
[17:20:38.181] <TB2> INFO: missing ROC header(s): 0
[17:20:38.181] <TB2> INFO: misplaced readback start: 0
[17:20:38.181] <TB2> INFO: Pixel decoding errors: 0
[17:20:38.181] <TB2> INFO: pixel data incomplete: 0
[17:20:38.181] <TB2> INFO: pixel address: 0
[17:20:38.181] <TB2> INFO: pulse height fill bit: 0
[17:20:38.181] <TB2> INFO: buffer corruption: 0
[17:20:38.199] <TB2> INFO: Decoding statistics:
[17:20:38.199] <TB2> INFO: General information:
[17:20:38.199] <TB2> INFO: 16bit words read: 3408462
[17:20:38.199] <TB2> INFO: valid events total: 353536
[17:20:38.199] <TB2> INFO: empty events: 18738
[17:20:38.199] <TB2> INFO: valid events with pixels: 334798
[17:20:38.199] <TB2> INFO: valid pixel hits: 643623
[17:20:38.199] <TB2> INFO: Event errors: 0
[17:20:38.199] <TB2> INFO: start marker: 0
[17:20:38.199] <TB2> INFO: stop marker: 0
[17:20:38.199] <TB2> INFO: overflow: 0
[17:20:38.199] <TB2> INFO: invalid 5bit words: 0
[17:20:38.199] <TB2> INFO: invalid XOR eye diagram: 0
[17:20:38.199] <TB2> INFO: frame (failed synchr.): 0
[17:20:38.199] <TB2> INFO: idle data (no TBM trl): 0
[17:20:38.199] <TB2> INFO: no data (only TBM hdr): 0
[17:20:38.199] <TB2> INFO: TBM errors: 0
[17:20:38.199] <TB2> INFO: flawed TBM headers: 0
[17:20:38.199] <TB2> INFO: flawed TBM trailers: 0
[17:20:38.199] <TB2> INFO: event ID mismatches: 0
[17:20:38.199] <TB2> INFO: ROC errors: 0
[17:20:38.199] <TB2> INFO: missing ROC header(s): 0
[17:20:38.199] <TB2> INFO: misplaced readback start: 0
[17:20:38.199] <TB2> INFO: Pixel decoding errors: 0
[17:20:38.199] <TB2> INFO: pixel data incomplete: 0
[17:20:38.199] <TB2> INFO: pixel address: 0
[17:20:38.199] <TB2> INFO: pulse height fill bit: 0
[17:20:38.199] <TB2> INFO: buffer corruption: 0
[17:20:38.199] <TB2> INFO: enter test to run
[17:20:38.199] <TB2> INFO: test: trim80 no parameter change
[17:20:38.199] <TB2> INFO: running: trim80
[17:20:38.201] <TB2> INFO: ######################################################################
[17:20:38.201] <TB2> INFO: PixTestTrim80::doTest()
[17:20:38.201] <TB2> INFO: ######################################################################
[17:20:38.202] <TB2> INFO: ----------------------------------------------------------------------
[17:20:38.202] <TB2> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[17:20:38.202] <TB2> INFO: ----------------------------------------------------------------------
[17:20:38.248] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[17:20:38.248] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:20:38.262] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:20:38.262] <TB2> INFO: run 1 of 1
[17:20:38.500] <TB2> INFO: Expecting 5025280 events.
[17:21:06.361] <TB2> INFO: 687304 events read in total (27269ms).
[17:21:33.737] <TB2> INFO: 1371400 events read in total (54645ms).
[17:22:00.956] <TB2> INFO: 2052912 events read in total (81864ms).
[17:22:28.508] <TB2> INFO: 2732744 events read in total (109416ms).
[17:22:55.970] <TB2> INFO: 3412296 events read in total (136878ms).
[17:23:23.021] <TB2> INFO: 4091840 events read in total (163929ms).
[17:23:51.260] <TB2> INFO: 4772312 events read in total (192168ms).
[17:24:01.994] <TB2> INFO: 5025280 events read in total (202902ms).
[17:24:02.090] <TB2> INFO: Test took 203828ms.
[17:24:23.268] <TB2> INFO: ROC 0 VthrComp = 81
[17:24:23.268] <TB2> INFO: ROC 1 VthrComp = 75
[17:24:23.268] <TB2> INFO: ROC 2 VthrComp = 77
[17:24:23.268] <TB2> INFO: ROC 3 VthrComp = 81
[17:24:23.269] <TB2> INFO: ROC 4 VthrComp = 81
[17:24:23.269] <TB2> INFO: ROC 5 VthrComp = 74
[17:24:23.269] <TB2> INFO: ROC 6 VthrComp = 76
[17:24:23.269] <TB2> INFO: ROC 7 VthrComp = 74
[17:24:23.269] <TB2> INFO: ROC 8 VthrComp = 89
[17:24:23.269] <TB2> INFO: ROC 9 VthrComp = 84
[17:24:23.269] <TB2> INFO: ROC 10 VthrComp = 77
[17:24:23.270] <TB2> INFO: ROC 11 VthrComp = 77
[17:24:23.270] <TB2> INFO: ROC 12 VthrComp = 79
[17:24:23.270] <TB2> INFO: ROC 13 VthrComp = 80
[17:24:23.270] <TB2> INFO: ROC 14 VthrComp = 77
[17:24:23.270] <TB2> INFO: ROC 15 VthrComp = 75
[17:24:23.521] <TB2> INFO: Expecting 41600 events.
[17:24:27.037] <TB2> INFO: 41600 events read in total (2924ms).
[17:24:27.038] <TB2> INFO: Test took 3764ms.
[17:24:27.048] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[17:24:27.048] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:24:27.059] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:24:27.059] <TB2> INFO: run 1 of 1
[17:24:27.344] <TB2> INFO: Expecting 5025280 events.
[17:24:55.550] <TB2> INFO: 690288 events read in total (27615ms).
[17:25:23.251] <TB2> INFO: 1376920 events read in total (55317ms).
[17:25:51.064] <TB2> INFO: 2061840 events read in total (83129ms).
[17:26:18.770] <TB2> INFO: 2744176 events read in total (110835ms).
[17:26:46.450] <TB2> INFO: 3423400 events read in total (138515ms).
[17:27:13.986] <TB2> INFO: 4100328 events read in total (166051ms).
[17:27:41.319] <TB2> INFO: 4775392 events read in total (193384ms).
[17:27:51.918] <TB2> INFO: 5025280 events read in total (203983ms).
[17:27:51.985] <TB2> INFO: Test took 204926ms.
[17:28:13.553] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 107.582 for pixel 2/22 mean/min/max = 91.3161/74.8596/107.773
[17:28:13.553] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 112.348 for pixel 2/74 mean/min/max = 95.2086/78.0465/112.371
[17:28:13.554] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 112.765 for pixel 0/12 mean/min/max = 95.0655/77.3116/112.819
[17:28:13.555] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 106.326 for pixel 19/74 mean/min/max = 90.7596/75.1579/106.361
[17:28:13.555] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 109.109 for pixel 6/79 mean/min/max = 92.3423/75.4675/109.217
[17:28:13.556] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 109.855 for pixel 0/17 mean/min/max = 94.1818/78.0316/110.332
[17:28:13.557] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 108.752 for pixel 50/9 mean/min/max = 93.5185/78.2829/108.754
[17:28:13.557] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 110.36 for pixel 3/59 mean/min/max = 93.706/77.0423/110.37
[17:28:13.558] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 109.572 for pixel 0/47 mean/min/max = 92.9176/76.245/109.59
[17:28:13.559] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 111.77 for pixel 8/79 mean/min/max = 93.1601/74.4086/111.912
[17:28:13.559] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 114.441 for pixel 16/70 mean/min/max = 96.8526/78.8618/114.843
[17:28:13.560] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 113.283 for pixel 9/78 mean/min/max = 95.4078/77.5251/113.291
[17:28:13.561] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 111.858 for pixel 2/79 mean/min/max = 94.729/77.4987/111.959
[17:28:13.561] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 107.339 for pixel 0/59 mean/min/max = 91.2072/74.986/107.428
[17:28:13.562] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 113.091 for pixel 51/2 mean/min/max = 95.238/77.3175/113.158
[17:28:13.562] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 111.162 for pixel 17/40 mean/min/max = 95.0732/78.5544/111.592
[17:28:13.563] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:28:13.652] <TB2> INFO: Expecting 411648 events.
[17:28:23.161] <TB2> INFO: 411648 events read in total (8917ms).
[17:28:23.171] <TB2> INFO: Expecting 411648 events.
[17:28:32.713] <TB2> INFO: 411648 events read in total (9139ms).
[17:28:32.724] <TB2> INFO: Expecting 411648 events.
[17:28:42.066] <TB2> INFO: 411648 events read in total (8939ms).
[17:28:42.083] <TB2> INFO: Expecting 411648 events.
[17:28:51.404] <TB2> INFO: 411648 events read in total (8918ms).
[17:28:51.421] <TB2> INFO: Expecting 411648 events.
[17:29:01.014] <TB2> INFO: 411648 events read in total (9190ms).
[17:29:01.040] <TB2> INFO: Expecting 411648 events.
[17:29:10.293] <TB2> INFO: 411648 events read in total (8849ms).
[17:29:10.323] <TB2> INFO: Expecting 411648 events.
[17:29:19.625] <TB2> INFO: 411648 events read in total (8899ms).
[17:29:19.652] <TB2> INFO: Expecting 411648 events.
[17:29:29.232] <TB2> INFO: 411648 events read in total (9177ms).
[17:29:29.265] <TB2> INFO: Expecting 411648 events.
[17:29:38.537] <TB2> INFO: 411648 events read in total (8869ms).
[17:29:38.569] <TB2> INFO: Expecting 411648 events.
[17:29:47.844] <TB2> INFO: 411648 events read in total (8872ms).
[17:29:47.879] <TB2> INFO: Expecting 411648 events.
[17:29:57.262] <TB2> INFO: 411648 events read in total (8980ms).
[17:29:57.310] <TB2> INFO: Expecting 411648 events.
[17:30:06.604] <TB2> INFO: 411648 events read in total (8891ms).
[17:30:06.674] <TB2> INFO: Expecting 411648 events.
[17:30:15.901] <TB2> INFO: 411648 events read in total (8824ms).
[17:30:15.982] <TB2> INFO: Expecting 411648 events.
[17:30:25.419] <TB2> INFO: 411648 events read in total (9032ms).
[17:30:25.515] <TB2> INFO: Expecting 411648 events.
[17:30:34.777] <TB2> INFO: 411648 events read in total (8859ms).
[17:30:34.854] <TB2> INFO: Expecting 411648 events.
[17:30:44.138] <TB2> INFO: 411648 events read in total (8881ms).
[17:30:44.214] <TB2> INFO: Test took 150652ms.
[17:30:45.676] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[17:30:45.690] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:30:45.690] <TB2> INFO: run 1 of 1
[17:30:45.936] <TB2> INFO: Expecting 5025280 events.
[17:31:13.925] <TB2> INFO: 666976 events read in total (27397ms).
[17:31:41.910] <TB2> INFO: 1331616 events read in total (55382ms).
[17:32:08.702] <TB2> INFO: 1996464 events read in total (82174ms).
[17:32:35.716] <TB2> INFO: 2658928 events read in total (109188ms).
[17:33:02.916] <TB2> INFO: 3317784 events read in total (136388ms).
[17:33:30.723] <TB2> INFO: 3975536 events read in total (164195ms).
[17:33:57.237] <TB2> INFO: 4632152 events read in total (190709ms).
[17:34:13.112] <TB2> INFO: 5025280 events read in total (206584ms).
[17:34:13.213] <TB2> INFO: Test took 207524ms.
[17:34:35.516] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 49.485274 .. 99.494398
[17:34:35.754] <TB2> INFO: Expecting 208000 events.
[17:34:45.565] <TB2> INFO: 208000 events read in total (9219ms).
[17:34:45.565] <TB2> INFO: Test took 10048ms.
[17:34:45.637] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 39 .. 109 (-1/-1) hits flags = 528 (plus default)
[17:34:45.651] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:34:45.651] <TB2> INFO: run 1 of 1
[17:34:45.929] <TB2> INFO: Expecting 2362880 events.
[17:35:14.722] <TB2> INFO: 702472 events read in total (28202ms).
[17:35:43.553] <TB2> INFO: 1403400 events read in total (57033ms).
[17:36:11.593] <TB2> INFO: 2098192 events read in total (85073ms).
[17:36:22.884] <TB2> INFO: 2362880 events read in total (96364ms).
[17:36:22.926] <TB2> INFO: Test took 97275ms.
[17:36:39.205] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 60.570244 .. 89.227780
[17:36:39.450] <TB2> INFO: Expecting 208000 events.
[17:36:49.082] <TB2> INFO: 208000 events read in total (9040ms).
[17:36:49.083] <TB2> INFO: Test took 9877ms.
[17:36:49.132] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 50 .. 99 (-1/-1) hits flags = 528 (plus default)
[17:36:49.145] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:36:49.145] <TB2> INFO: run 1 of 1
[17:36:49.423] <TB2> INFO: Expecting 1664000 events.
[17:37:17.992] <TB2> INFO: 708232 events read in total (27977ms).
[17:37:46.244] <TB2> INFO: 1415504 events read in total (56229ms).
[17:37:56.417] <TB2> INFO: 1664000 events read in total (66402ms).
[17:37:56.461] <TB2> INFO: Test took 67315ms.
[17:38:13.658] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 65.875334 .. 84.428736
[17:38:13.899] <TB2> INFO: Expecting 208000 events.
[17:38:23.856] <TB2> INFO: 208000 events read in total (9365ms).
[17:38:23.857] <TB2> INFO: Test took 10198ms.
[17:38:23.911] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 55 .. 94 (-1/-1) hits flags = 528 (plus default)
[17:38:23.925] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:38:23.925] <TB2> INFO: run 1 of 1
[17:38:24.203] <TB2> INFO: Expecting 1331200 events.
[17:38:54.321] <TB2> INFO: 719032 events read in total (29526ms).
[17:39:19.022] <TB2> INFO: 1331200 events read in total (54228ms).
[17:39:19.061] <TB2> INFO: Test took 55136ms.
[17:39:34.991] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 69.419979 .. 83.750505
[17:39:35.256] <TB2> INFO: Expecting 208000 events.
[17:39:44.943] <TB2> INFO: 208000 events read in total (9096ms).
[17:39:44.945] <TB2> INFO: Test took 9953ms.
[17:39:44.994] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 59 .. 93 (-1/-1) hits flags = 528 (plus default)
[17:39:45.005] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:39:45.005] <TB2> INFO: run 1 of 1
[17:39:45.283] <TB2> INFO: Expecting 1164800 events.
[17:40:15.045] <TB2> INFO: 712592 events read in total (29170ms).
[17:40:33.743] <TB2> INFO: 1164800 events read in total (47869ms).
[17:40:33.773] <TB2> INFO: Test took 48768ms.
[17:40:52.687] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[17:40:52.687] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[17:40:52.701] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:40:52.701] <TB2> INFO: run 1 of 1
[17:40:52.980] <TB2> INFO: Expecting 1364480 events.
[17:41:21.248] <TB2> INFO: 668680 events read in total (27676ms).
[17:41:49.356] <TB2> INFO: 1336440 events read in total (55785ms).
[17:41:50.913] <TB2> INFO: 1364480 events read in total (57341ms).
[17:41:50.939] <TB2> INFO: Test took 58239ms.
[17:42:06.617] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C0.dat
[17:42:06.617] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C1.dat
[17:42:06.617] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C2.dat
[17:42:06.617] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C3.dat
[17:42:06.617] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C4.dat
[17:42:06.618] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C5.dat
[17:42:06.618] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C6.dat
[17:42:06.618] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C7.dat
[17:42:06.618] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C8.dat
[17:42:06.619] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C9.dat
[17:42:06.619] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C10.dat
[17:42:06.619] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C11.dat
[17:42:06.619] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C12.dat
[17:42:06.619] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C13.dat
[17:42:06.619] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C14.dat
[17:42:06.619] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C15.dat
[17:42:06.620] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C0.dat
[17:42:06.630] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C1.dat
[17:42:06.637] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C2.dat
[17:42:06.644] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C3.dat
[17:42:06.650] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C4.dat
[17:42:06.656] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C5.dat
[17:42:06.662] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C6.dat
[17:42:06.669] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C7.dat
[17:42:06.675] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C8.dat
[17:42:06.681] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C9.dat
[17:42:06.688] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C10.dat
[17:42:06.694] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C11.dat
[17:42:06.700] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C12.dat
[17:42:06.707] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C13.dat
[17:42:06.713] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C14.dat
[17:42:06.719] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1129_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C15.dat
[17:42:06.726] <TB2> INFO: PixTestTrim80::trimTest() done
[17:42:06.726] <TB2> INFO: vtrim: 99 109 101 93 107 97 93 86 103 114 115 124 116 87 118 102
[17:42:06.726] <TB2> INFO: vthrcomp: 81 75 77 81 81 74 76 74 89 84 77 77 79 80 77 75
[17:42:06.726] <TB2> INFO: vcal mean: 79.99 79.99 79.95 79.98 79.98 80.01 79.96 80.00 79.96 79.99 79.97 79.95 79.99 80.01 79.99 79.96
[17:42:06.726] <TB2> INFO: vcal RMS: 0.73 0.75 0.72 0.69 0.72 0.71 0.70 0.72 0.80 0.81 0.79 0.79 0.76 0.76 0.78 0.72
[17:42:06.726] <TB2> INFO: bits mean: 10.15 9.28 9.20 9.88 9.86 8.70 9.27 9.43 9.96 10.27 9.42 9.51 9.59 9.98 9.59 9.42
[17:42:06.726] <TB2> INFO: bits RMS: 2.38 2.27 2.32 2.50 2.36 2.47 2.26 2.34 2.27 2.27 2.05 2.20 2.16 2.43 2.20 2.12
[17:42:06.734] <TB2> INFO: ----------------------------------------------------------------------
[17:42:06.734] <TB2> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[17:42:06.734] <TB2> INFO: ----------------------------------------------------------------------
[17:42:06.736] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[17:42:06.750] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:42:06.750] <TB2> INFO: run 1 of 1
[17:42:06.986] <TB2> INFO: Expecting 4160000 events.
[17:42:40.313] <TB2> INFO: 779590 events read in total (32735ms).
[17:43:12.715] <TB2> INFO: 1554150 events read in total (65138ms).
[17:43:44.746] <TB2> INFO: 2321895 events read in total (97168ms).
[17:44:16.739] <TB2> INFO: 3083860 events read in total (129161ms).
[17:44:49.768] <TB2> INFO: 3845865 events read in total (162190ms).
[17:45:03.302] <TB2> INFO: 4160000 events read in total (175724ms).
[17:45:03.374] <TB2> INFO: Test took 176624ms.
[17:45:26.180] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 218 (-1/-1) hits flags = 528 (plus default)
[17:45:26.194] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:45:26.194] <TB2> INFO: run 1 of 1
[17:45:26.429] <TB2> INFO: Expecting 4555200 events.
[17:45:58.083] <TB2> INFO: 724690 events read in total (31062ms).
[17:46:29.397] <TB2> INFO: 1446395 events read in total (62376ms).
[17:47:00.833] <TB2> INFO: 2164490 events read in total (93812ms).
[17:47:32.084] <TB2> INFO: 2878475 events read in total (125063ms).
[17:48:03.533] <TB2> INFO: 3591015 events read in total (156512ms).
[17:48:35.065] <TB2> INFO: 4303180 events read in total (188044ms).
[17:48:46.188] <TB2> INFO: 4555200 events read in total (199167ms).
[17:48:46.268] <TB2> INFO: Test took 200074ms.
[17:49:13.325] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[17:49:13.338] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:49:13.338] <TB2> INFO: run 1 of 1
[17:49:13.575] <TB2> INFO: Expecting 4243200 events.
[17:49:45.747] <TB2> INFO: 744470 events read in total (31580ms).
[17:50:17.240] <TB2> INFO: 1485685 events read in total (63073ms).
[17:50:48.472] <TB2> INFO: 2221560 events read in total (94305ms).
[17:51:19.732] <TB2> INFO: 2953720 events read in total (125565ms).
[17:51:51.584] <TB2> INFO: 3684210 events read in total (157417ms).
[17:52:15.789] <TB2> INFO: 4243200 events read in total (181622ms).
[17:52:15.868] <TB2> INFO: Test took 182530ms.
[17:52:39.871] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[17:52:39.884] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:52:39.884] <TB2> INFO: run 1 of 1
[17:52:40.122] <TB2> INFO: Expecting 4264000 events.
[17:53:12.692] <TB2> INFO: 743170 events read in total (31978ms).
[17:53:44.488] <TB2> INFO: 1483090 events read in total (63774ms).
[17:54:15.849] <TB2> INFO: 2217795 events read in total (95136ms).
[17:54:47.594] <TB2> INFO: 2948115 events read in total (126880ms).
[17:55:19.910] <TB2> INFO: 3677000 events read in total (159196ms).
[17:55:45.185] <TB2> INFO: 4264000 events read in total (184471ms).
[17:55:45.265] <TB2> INFO: Test took 185381ms.
[17:56:09.048] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 202 (-1/-1) hits flags = 528 (plus default)
[17:56:09.061] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:56:09.061] <TB2> INFO: run 1 of 1
[17:56:09.301] <TB2> INFO: Expecting 4222400 events.
[17:56:41.460] <TB2> INFO: 746020 events read in total (31568ms).
[17:57:13.239] <TB2> INFO: 1488690 events read in total (63347ms).
[17:57:44.521] <TB2> INFO: 2225825 events read in total (94629ms).
[17:58:15.907] <TB2> INFO: 2959050 events read in total (126015ms).
[17:58:46.742] <TB2> INFO: 3691005 events read in total (156850ms).
[17:59:09.734] <TB2> INFO: 4222400 events read in total (179842ms).
[17:59:09.836] <TB2> INFO: Test took 180774ms.
[17:59:39.430] <TB2> INFO: PixTestTrim80::trimBitTest() done
[17:59:39.431] <TB2> INFO: PixTestTrim80::doTest() done, duration: 2341 seconds
[17:59:40.052] <TB2> INFO: enter test to run
[17:59:40.052] <TB2> INFO: test: exit no parameter change
[17:59:40.241] <TB2> QUIET: Connection to board 149 closed.
[17:59:40.242] <TB2> INFO: pXar: this is the end, my friend