[14:19:46.542] <TB1> INFO: *** Welcome to pxar ***
[14:19:46.542] <TB1> INFO: *** Today: 2016/11/07
[14:19:46.550] <TB1> INFO: *** Version: c8ba-dirty
[14:19:46.550] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C15.dat
[14:19:46.550] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C1b.dat
[14:19:46.550] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//defaultMaskFile.dat
[14:19:46.550] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters_C15.dat
[14:19:46.613] <TB1> INFO: clk: 4
[14:19:46.613] <TB1> INFO: ctr: 4
[14:19:46.613] <TB1> INFO: sda: 19
[14:19:46.613] <TB1> INFO: tin: 9
[14:19:46.613] <TB1> INFO: level: 15
[14:19:46.613] <TB1> INFO: triggerdelay: 0
[14:19:46.613] <TB1> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[14:19:46.613] <TB1> INFO: Log level: INFO
[14:19:46.621] <TB1> INFO: Found DTB DTB_WXC03A
[14:19:46.633] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[14:19:46.635] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
------------------------------------------------------
[14:19:46.637] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[14:19:48.195] <TB1> INFO: DUT info:
[14:19:48.195] <TB1> INFO: The DUT currently contains the following objects:
[14:19:48.195] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[14:19:48.195] <TB1> INFO: TBM Core alpha (0): 7 registers set
[14:19:48.195] <TB1> INFO: TBM Core beta (1): 7 registers set
[14:19:48.195] <TB1> INFO: TBM Core alpha (2): 7 registers set
[14:19:48.195] <TB1> INFO: TBM Core beta (3): 7 registers set
[14:19:48.195] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[14:19:48.195] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.195] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.195] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.195] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.195] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.195] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.195] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.195] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.195] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.195] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.195] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.195] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.196] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.196] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.196] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.196] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[14:19:48.596] <TB1> INFO: enter 'restricted' command line mode
[14:19:48.597] <TB1> INFO: enter test to run
[14:19:48.597] <TB1> INFO: test: pretest no parameter change
[14:19:48.597] <TB1> INFO: running: pretest
[14:19:48.602] <TB1> INFO: ######################################################################
[14:19:48.602] <TB1> INFO: PixTestPretest::doTest()
[14:19:48.602] <TB1> INFO: ######################################################################
[14:19:48.604] <TB1> INFO: ----------------------------------------------------------------------
[14:19:48.604] <TB1> INFO: PixTestPretest::programROC()
[14:19:48.604] <TB1> INFO: ----------------------------------------------------------------------
[14:20:06.617] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[14:20:06.617] <TB1> INFO: IA differences per ROC: 20.9 17.7 20.1 20.1 20.9 16.1 17.7 20.1 17.7 20.1 18.5 20.1 20.1 20.1 22.5 19.3
[14:20:06.685] <TB1> INFO: ----------------------------------------------------------------------
[14:20:06.685] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[14:20:06.685] <TB1> INFO: ----------------------------------------------------------------------
[14:20:27.986] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 377.8 mA = 23.6125 mA/ROC
[14:20:27.986] <TB1> INFO: i(loss) [mA/ROC]: 19.3 18.5 19.3 19.3 18.5 19.3 19.3 19.3 18.5 19.3 19.3 18.5 18.5 18.5 19.3 18.5
[14:20:28.019] <TB1> INFO: ----------------------------------------------------------------------
[14:20:28.019] <TB1> INFO: PixTestPretest::findTiming()
[14:20:28.019] <TB1> INFO: ----------------------------------------------------------------------
[14:20:28.019] <TB1> INFO: PixTestCmd::init()

[14:21:00.483] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[14:21:00.483] <TB1> INFO: (success/tries = 100/100), width = 4
[14:21:01.991] <TB1> INFO: ----------------------------------------------------------------------
[14:21:01.991] <TB1> INFO: PixTestPretest::findWorkingPixel()
[14:21:01.991] <TB1> INFO: ----------------------------------------------------------------------
[14:21:02.083] <TB1> INFO: Expecting 231680 events.
[14:21:12.037] <TB1> INFO: 231680 events read in total (9362ms).
[14:21:12.051] <TB1> INFO: Test took 10058ms.
[14:21:12.303] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[14:21:12.346] <TB1> INFO: ----------------------------------------------------------------------
[14:21:12.346] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[14:21:12.346] <TB1> INFO: ----------------------------------------------------------------------
[14:21:12.439] <TB1> INFO: Expecting 231680 events.
[14:21:22.318] <TB1> INFO: 231680 events read in total (9287ms).
[14:21:22.331] <TB1> INFO: Test took 9981ms.
[14:21:22.607] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[14:21:22.607] <TB1> INFO: CalDel: 111 108 112 107 100 94 98 118 98 89 104 97 95 103 97 102
[14:21:22.607] <TB1> INFO: VthrComp: 51 51 51 51 51 51 51 52 51 51 51 51 51 54 51 51
[14:21:22.610] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C0.dat
[14:21:22.610] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C1.dat
[14:21:22.610] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C2.dat
[14:21:22.610] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C3.dat
[14:21:22.610] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C4.dat
[14:21:22.611] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C5.dat
[14:21:22.611] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C6.dat
[14:21:22.611] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C7.dat
[14:21:22.611] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C8.dat
[14:21:22.611] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C9.dat
[14:21:22.611] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C10.dat
[14:21:22.611] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C11.dat
[14:21:22.611] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C12.dat
[14:21:22.611] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C13.dat
[14:21:22.611] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C14.dat
[14:21:22.611] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters_C15.dat
[14:21:22.612] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C0a.dat
[14:21:22.612] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C0b.dat
[14:21:22.612] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C1a.dat
[14:21:22.612] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//tbmParameters_C1b.dat
[14:21:22.612] <TB1> INFO: PixTestPretest::doTest() done, duration: 94 seconds
[14:21:22.681] <TB1> INFO: enter test to run
[14:21:22.681] <TB1> INFO: test: FullTest no parameter change
[14:21:22.681] <TB1> INFO: running: fulltest
[14:21:22.681] <TB1> INFO: ######################################################################
[14:21:22.681] <TB1> INFO: PixTestFullTest::doTest()
[14:21:22.681] <TB1> INFO: ######################################################################
[14:21:22.682] <TB1> INFO: ######################################################################
[14:21:22.682] <TB1> INFO: PixTestAlive::doTest()
[14:21:22.682] <TB1> INFO: ######################################################################
[14:21:22.683] <TB1> INFO: ----------------------------------------------------------------------
[14:21:22.683] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:21:22.683] <TB1> INFO: ----------------------------------------------------------------------
[14:21:22.924] <TB1> INFO: Expecting 41600 events.
[14:21:26.469] <TB1> INFO: 41600 events read in total (2953ms).
[14:21:26.469] <TB1> INFO: Test took 3784ms.
[14:21:26.702] <TB1> INFO: PixTestAlive::aliveTest() done
[14:21:26.703] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:21:26.704] <TB1> INFO: ----------------------------------------------------------------------
[14:21:26.704] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:21:26.704] <TB1> INFO: ----------------------------------------------------------------------
[14:21:26.947] <TB1> INFO: Expecting 41600 events.
[14:21:29.902] <TB1> INFO: 41600 events read in total (2363ms).
[14:21:29.902] <TB1> INFO: Test took 3196ms.
[14:21:29.902] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[14:21:30.137] <TB1> INFO: PixTestAlive::maskTest() done
[14:21:30.137] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:21:30.138] <TB1> INFO: ----------------------------------------------------------------------
[14:21:30.138] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:21:30.138] <TB1> INFO: ----------------------------------------------------------------------
[14:21:30.379] <TB1> INFO: Expecting 41600 events.
[14:21:34.013] <TB1> INFO: 41600 events read in total (3042ms).
[14:21:34.014] <TB1> INFO: Test took 3874ms.
[14:21:34.253] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[14:21:34.253] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:21:34.253] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[14:21:34.253] <TB1> INFO: Decoding statistics:
[14:21:34.253] <TB1> INFO: General information:
[14:21:34.253] <TB1> INFO: 16bit words read: 0
[14:21:34.253] <TB1> INFO: valid events total: 0
[14:21:34.253] <TB1> INFO: empty events: 0
[14:21:34.253] <TB1> INFO: valid events with pixels: 0
[14:21:34.253] <TB1> INFO: valid pixel hits: 0
[14:21:34.253] <TB1> INFO: Event errors: 0
[14:21:34.253] <TB1> INFO: start marker: 0
[14:21:34.253] <TB1> INFO: stop marker: 0
[14:21:34.253] <TB1> INFO: overflow: 0
[14:21:34.253] <TB1> INFO: invalid 5bit words: 0
[14:21:34.253] <TB1> INFO: invalid XOR eye diagram: 0
[14:21:34.253] <TB1> INFO: frame (failed synchr.): 0
[14:21:34.254] <TB1> INFO: idle data (no TBM trl): 0
[14:21:34.254] <TB1> INFO: no data (only TBM hdr): 0
[14:21:34.254] <TB1> INFO: TBM errors: 0
[14:21:34.254] <TB1> INFO: flawed TBM headers: 0
[14:21:34.254] <TB1> INFO: flawed TBM trailers: 0
[14:21:34.254] <TB1> INFO: event ID mismatches: 0
[14:21:34.254] <TB1> INFO: ROC errors: 0
[14:21:34.254] <TB1> INFO: missing ROC header(s): 0
[14:21:34.254] <TB1> INFO: misplaced readback start: 0
[14:21:34.254] <TB1> INFO: Pixel decoding errors: 0
[14:21:34.254] <TB1> INFO: pixel data incomplete: 0
[14:21:34.254] <TB1> INFO: pixel address: 0
[14:21:34.254] <TB1> INFO: pulse height fill bit: 0
[14:21:34.254] <TB1> INFO: buffer corruption: 0
[14:21:34.264] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C15.dat
[14:21:34.265] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[14:21:34.265] <TB1> INFO: ######################################################################
[14:21:34.265] <TB1> INFO: PixTestReadback::doTest()
[14:21:34.265] <TB1> INFO: ######################################################################
[14:21:34.265] <TB1> INFO: ----------------------------------------------------------------------
[14:21:34.265] <TB1> INFO: PixTestReadback::CalibrateVd()
[14:21:34.265] <TB1> INFO: ----------------------------------------------------------------------
[14:21:44.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C0.dat
[14:21:44.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C1.dat
[14:21:44.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C2.dat
[14:21:44.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C3.dat
[14:21:44.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C4.dat
[14:21:44.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C5.dat
[14:21:44.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C6.dat
[14:21:44.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C7.dat
[14:21:44.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C8.dat
[14:21:44.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C9.dat
[14:21:44.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C10.dat
[14:21:44.242] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C11.dat
[14:21:44.242] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C12.dat
[14:21:44.242] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C13.dat
[14:21:44.242] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C14.dat
[14:21:44.242] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C15.dat
[14:21:44.275] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[14:21:44.275] <TB1> INFO: ----------------------------------------------------------------------
[14:21:44.275] <TB1> INFO: PixTestReadback::CalibrateVa()
[14:21:44.275] <TB1> INFO: ----------------------------------------------------------------------
[14:21:54.202] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C0.dat
[14:21:54.202] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C1.dat
[14:21:54.202] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C2.dat
[14:21:54.202] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C3.dat
[14:21:54.202] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C4.dat
[14:21:54.202] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C5.dat
[14:21:54.202] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C6.dat
[14:21:54.202] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C7.dat
[14:21:54.202] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C8.dat
[14:21:54.203] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C9.dat
[14:21:54.203] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C10.dat
[14:21:54.203] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C11.dat
[14:21:54.203] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C12.dat
[14:21:54.203] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C13.dat
[14:21:54.203] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C14.dat
[14:21:54.203] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C15.dat
[14:21:54.234] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[14:21:54.234] <TB1> INFO: ----------------------------------------------------------------------
[14:21:54.234] <TB1> INFO: PixTestReadback::readbackVbg()
[14:21:54.234] <TB1> INFO: ----------------------------------------------------------------------
[14:22:01.904] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[14:22:01.904] <TB1> INFO: ----------------------------------------------------------------------
[14:22:01.904] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[14:22:01.904] <TB1> INFO: ----------------------------------------------------------------------
[14:22:01.904] <TB1> INFO: Vbg will be calibrated using Vd calibration
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 157.7calibrated Vbg = 1.18101 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 154.6calibrated Vbg = 1.18335 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 158.4calibrated Vbg = 1.18012 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 150.9calibrated Vbg = 1.17864 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 150.8calibrated Vbg = 1.17656 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 157.1calibrated Vbg = 1.1797 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 152.9calibrated Vbg = 1.18606 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 158.6calibrated Vbg = 1.18475 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 154.8calibrated Vbg = 1.17804 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 153.9calibrated Vbg = 1.17205 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 146.8calibrated Vbg = 1.17567 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 156.9calibrated Vbg = 1.16811 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 154.6calibrated Vbg = 1.17149 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 159calibrated Vbg = 1.17826 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 159.9calibrated Vbg = 1.17573 :::*/*/*/*/
[14:22:01.904] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 161.5calibrated Vbg = 1.18309 :::*/*/*/*/
[14:22:01.906] <TB1> INFO: ----------------------------------------------------------------------
[14:22:01.906] <TB1> INFO: PixTestReadback::CalibrateIa()
[14:22:01.906] <TB1> INFO: ----------------------------------------------------------------------
[14:24:42.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C0.dat
[14:24:42.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C1.dat
[14:24:42.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C2.dat
[14:24:42.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C3.dat
[14:24:42.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C4.dat
[14:24:42.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C5.dat
[14:24:42.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C6.dat
[14:24:42.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C7.dat
[14:24:42.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C8.dat
[14:24:42.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C9.dat
[14:24:42.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C10.dat
[14:24:42.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C11.dat
[14:24:42.755] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C12.dat
[14:24:42.755] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C13.dat
[14:24:42.755] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C14.dat
[14:24:42.755] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//readbackCal_C15.dat
[14:24:42.784] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[14:24:42.787] <TB1> INFO: PixTestReadback::doTest() done
[14:24:42.787] <TB1> INFO: Decoding statistics:
[14:24:42.787] <TB1> INFO: General information:
[14:24:42.787] <TB1> INFO: 16bit words read: 1536
[14:24:42.787] <TB1> INFO: valid events total: 256
[14:24:42.787] <TB1> INFO: empty events: 256
[14:24:42.787] <TB1> INFO: valid events with pixels: 0
[14:24:42.787] <TB1> INFO: valid pixel hits: 0
[14:24:42.787] <TB1> INFO: Event errors: 0
[14:24:42.787] <TB1> INFO: start marker: 0
[14:24:42.787] <TB1> INFO: stop marker: 0
[14:24:42.787] <TB1> INFO: overflow: 0
[14:24:42.787] <TB1> INFO: invalid 5bit words: 0
[14:24:42.787] <TB1> INFO: invalid XOR eye diagram: 0
[14:24:42.787] <TB1> INFO: frame (failed synchr.): 0
[14:24:42.787] <TB1> INFO: idle data (no TBM trl): 0
[14:24:42.787] <TB1> INFO: no data (only TBM hdr): 0
[14:24:42.787] <TB1> INFO: TBM errors: 0
[14:24:42.787] <TB1> INFO: flawed TBM headers: 0
[14:24:42.787] <TB1> INFO: flawed TBM trailers: 0
[14:24:42.787] <TB1> INFO: event ID mismatches: 0
[14:24:42.787] <TB1> INFO: ROC errors: 0
[14:24:42.787] <TB1> INFO: missing ROC header(s): 0
[14:24:42.787] <TB1> INFO: misplaced readback start: 0
[14:24:42.787] <TB1> INFO: Pixel decoding errors: 0
[14:24:42.787] <TB1> INFO: pixel data incomplete: 0
[14:24:42.787] <TB1> INFO: pixel address: 0
[14:24:42.787] <TB1> INFO: pulse height fill bit: 0
[14:24:42.787] <TB1> INFO: buffer corruption: 0
[14:24:42.839] <TB1> INFO: ######################################################################
[14:24:42.839] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[14:24:42.839] <TB1> INFO: ######################################################################
[14:24:42.842] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[14:24:42.862] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:24:42.862] <TB1> INFO: run 1 of 1
[14:24:43.103] <TB1> INFO: Expecting 3120000 events.
[14:25:14.324] <TB1> INFO: 656140 events read in total (30629ms).











[14:25:44.526] <TB1> INFO: 1310270 events read in total (60831ms).











[14:26:14.902] <TB1> INFO: 1962475 events read in total (91207ms).











[14:26:45.071] <TB1> INFO: 2616630 events read in total (121376ms).











[14:27:09.082] <TB1> INFO: 3120000 events read in total (145387ms).
[14:27:09.183] <TB1> INFO: Test took 146321ms.
[14:27:36.645] <TB1> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 173 seconds
[14:27:36.645] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0
[14:27:36.645] <TB1> INFO: separation cut (per ROC): 105 96 105 102 105 105 103 105 78 105 99 105 99 104 95 103
[14:27:36.645] <TB1> INFO: Decoding statistics:
[14:27:36.645] <TB1> INFO: General information:
[14:27:36.645] <TB1> INFO: 16bit words read: 0
[14:27:36.645] <TB1> INFO: valid events total: 0
[14:27:36.645] <TB1> INFO: empty events: 0
[14:27:36.645] <TB1> INFO: valid events with pixels: 0
[14:27:36.645] <TB1> INFO: valid pixel hits: 0
[14:27:36.645] <TB1> INFO: Event errors: 0
[14:27:36.645] <TB1> INFO: start marker: 0
[14:27:36.645] <TB1> INFO: stop marker: 0
[14:27:36.645] <TB1> INFO: overflow: 0
[14:27:36.645] <TB1> INFO: invalid 5bit words: 0
[14:27:36.645] <TB1> INFO: invalid XOR eye diagram: 0
[14:27:36.645] <TB1> INFO: frame (failed synchr.): 0
[14:27:36.645] <TB1> INFO: idle data (no TBM trl): 0
[14:27:36.645] <TB1> INFO: no data (only TBM hdr): 0
[14:27:36.645] <TB1> INFO: TBM errors: 0
[14:27:36.645] <TB1> INFO: flawed TBM headers: 0
[14:27:36.645] <TB1> INFO: flawed TBM trailers: 0
[14:27:36.645] <TB1> INFO: event ID mismatches: 0
[14:27:36.645] <TB1> INFO: ROC errors: 0
[14:27:36.645] <TB1> INFO: missing ROC header(s): 0
[14:27:36.645] <TB1> INFO: misplaced readback start: 0
[14:27:36.645] <TB1> INFO: Pixel decoding errors: 0
[14:27:36.645] <TB1> INFO: pixel data incomplete: 0
[14:27:36.645] <TB1> INFO: pixel address: 0
[14:27:36.645] <TB1> INFO: pulse height fill bit: 0
[14:27:36.646] <TB1> INFO: buffer corruption: 0
[14:27:36.690] <TB1> INFO: ######################################################################
[14:27:36.690] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:27:36.690] <TB1> INFO: ######################################################################
[14:27:36.690] <TB1> INFO: ----------------------------------------------------------------------
[14:27:36.690] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:27:36.690] <TB1> INFO: ----------------------------------------------------------------------
[14:27:36.690] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[14:27:36.703] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[14:27:36.703] <TB1> INFO: run 1 of 1
[14:27:36.957] <TB1> INFO: Expecting 36608000 events.
[14:28:00.857] <TB1> INFO: 661350 events read in total (23308ms).
[14:28:24.602] <TB1> INFO: 1311950 events read in total (47053ms).
[14:28:47.605] <TB1> INFO: 1962300 events read in total (70056ms).
[14:29:11.767] <TB1> INFO: 2610300 events read in total (94218ms).
[14:29:35.823] <TB1> INFO: 3258900 events read in total (118274ms).
[14:29:58.652] <TB1> INFO: 3906650 events read in total (141103ms).
[14:30:21.238] <TB1> INFO: 4555600 events read in total (163689ms).
[14:30:43.742] <TB1> INFO: 5205300 events read in total (186193ms).
[14:31:06.322] <TB1> INFO: 5851500 events read in total (208773ms).
[14:31:29.287] <TB1> INFO: 6500200 events read in total (231738ms).
[14:31:51.737] <TB1> INFO: 7145950 events read in total (254188ms).
[14:32:14.538] <TB1> INFO: 7794050 events read in total (276989ms).
[14:32:37.208] <TB1> INFO: 8438200 events read in total (299659ms).
[14:33:00.096] <TB1> INFO: 9084300 events read in total (322547ms).
[14:33:22.737] <TB1> INFO: 9728200 events read in total (345188ms).
[14:33:45.457] <TB1> INFO: 10374000 events read in total (367908ms).
[14:34:08.126] <TB1> INFO: 11017950 events read in total (390577ms).
[14:34:30.861] <TB1> INFO: 11663350 events read in total (413312ms).
[14:34:53.546] <TB1> INFO: 12307300 events read in total (435997ms).
[14:35:16.195] <TB1> INFO: 12950950 events read in total (458646ms).
[14:35:38.629] <TB1> INFO: 13594400 events read in total (481080ms).
[14:36:00.976] <TB1> INFO: 14237000 events read in total (503427ms).
[14:36:23.462] <TB1> INFO: 14879800 events read in total (525913ms).
[14:36:45.850] <TB1> INFO: 15521500 events read in total (548301ms).
[14:37:08.415] <TB1> INFO: 16164150 events read in total (570866ms).
[14:37:30.899] <TB1> INFO: 16805050 events read in total (593350ms).
[14:37:53.415] <TB1> INFO: 17447700 events read in total (615866ms).
[14:38:15.949] <TB1> INFO: 18089200 events read in total (638400ms).
[14:38:38.873] <TB1> INFO: 18731300 events read in total (661324ms).
[14:39:01.432] <TB1> INFO: 19372350 events read in total (683883ms).
[14:39:23.879] <TB1> INFO: 20010500 events read in total (706330ms).
[14:39:46.303] <TB1> INFO: 20650800 events read in total (728754ms).
[14:40:08.984] <TB1> INFO: 21289950 events read in total (751435ms).
[14:40:31.344] <TB1> INFO: 21928850 events read in total (773795ms).
[14:40:53.592] <TB1> INFO: 22565700 events read in total (796043ms).
[14:41:16.012] <TB1> INFO: 23205250 events read in total (818463ms).
[14:41:38.258] <TB1> INFO: 23842950 events read in total (840709ms).
[14:42:00.356] <TB1> INFO: 24480450 events read in total (862807ms).
[14:42:22.598] <TB1> INFO: 25118600 events read in total (885049ms).
[14:42:45.025] <TB1> INFO: 25757150 events read in total (907476ms).
[14:43:07.529] <TB1> INFO: 26396850 events read in total (929980ms).
[14:43:30.082] <TB1> INFO: 27034500 events read in total (952533ms).
[14:43:52.279] <TB1> INFO: 27673600 events read in total (974730ms).
[14:44:14.357] <TB1> INFO: 28311700 events read in total (996808ms).
[14:44:36.806] <TB1> INFO: 28950550 events read in total (1019257ms).
[14:44:59.173] <TB1> INFO: 29587450 events read in total (1041624ms).
[14:45:21.610] <TB1> INFO: 30225800 events read in total (1064061ms).
[14:45:44.278] <TB1> INFO: 30860900 events read in total (1086729ms).
[14:46:06.844] <TB1> INFO: 31501150 events read in total (1109295ms).
[14:46:29.432] <TB1> INFO: 32140700 events read in total (1131883ms).
[14:46:51.967] <TB1> INFO: 32780350 events read in total (1154418ms).
[14:47:14.254] <TB1> INFO: 33420200 events read in total (1176705ms).
[14:47:36.810] <TB1> INFO: 34060950 events read in total (1199262ms).
[14:47:59.319] <TB1> INFO: 34700850 events read in total (1221770ms).
[14:48:21.854] <TB1> INFO: 35338500 events read in total (1244305ms).
[14:48:44.626] <TB1> INFO: 35979450 events read in total (1267077ms).
[14:49:06.636] <TB1> INFO: 36608000 events read in total (1289087ms).
[14:49:06.745] <TB1> INFO: Test took 1290042ms.
[14:49:07.234] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:08.781] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:10.303] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:11.818] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:13.331] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:14.873] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:16.489] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:18.294] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:20.272] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:21.977] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:24.083] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:26.029] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:28.072] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:30.065] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:32.200] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:34.301] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:49:36.395] <TB1> INFO: PixTestScurves::scurves() done
[14:49:36.396] <TB1> INFO: Vcal mean: 111.29 109.66 107.60 100.86 116.17 116.44 108.57 117.94 94.15 106.35 100.64 110.02 105.50 115.18 98.90 104.78
[14:49:36.396] <TB1> INFO: Vcal RMS: 4.87 5.14 4.67 5.31 5.59 5.08 4.85 5.95 5.27 5.12 5.31 4.84 4.96 5.62 5.27 4.82
[14:49:36.396] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1319 seconds
[14:49:36.396] <TB1> INFO: Decoding statistics:
[14:49:36.396] <TB1> INFO: General information:
[14:49:36.396] <TB1> INFO: 16bit words read: 0
[14:49:36.396] <TB1> INFO: valid events total: 0
[14:49:36.396] <TB1> INFO: empty events: 0
[14:49:36.396] <TB1> INFO: valid events with pixels: 0
[14:49:36.396] <TB1> INFO: valid pixel hits: 0
[14:49:36.396] <TB1> INFO: Event errors: 0
[14:49:36.396] <TB1> INFO: start marker: 0
[14:49:36.396] <TB1> INFO: stop marker: 0
[14:49:36.396] <TB1> INFO: overflow: 0
[14:49:36.396] <TB1> INFO: invalid 5bit words: 0
[14:49:36.396] <TB1> INFO: invalid XOR eye diagram: 0
[14:49:36.396] <TB1> INFO: frame (failed synchr.): 0
[14:49:36.396] <TB1> INFO: idle data (no TBM trl): 0
[14:49:36.396] <TB1> INFO: no data (only TBM hdr): 0
[14:49:36.396] <TB1> INFO: TBM errors: 0
[14:49:36.396] <TB1> INFO: flawed TBM headers: 0
[14:49:36.396] <TB1> INFO: flawed TBM trailers: 0
[14:49:36.396] <TB1> INFO: event ID mismatches: 0
[14:49:36.396] <TB1> INFO: ROC errors: 0
[14:49:36.396] <TB1> INFO: missing ROC header(s): 0
[14:49:36.396] <TB1> INFO: misplaced readback start: 0
[14:49:36.396] <TB1> INFO: Pixel decoding errors: 0
[14:49:36.396] <TB1> INFO: pixel data incomplete: 0
[14:49:36.396] <TB1> INFO: pixel address: 0
[14:49:36.396] <TB1> INFO: pulse height fill bit: 0
[14:49:36.396] <TB1> INFO: buffer corruption: 0
[14:49:36.465] <TB1> INFO: ######################################################################
[14:49:36.465] <TB1> INFO: PixTestTrim::doTest()
[14:49:36.465] <TB1> INFO: ######################################################################
[14:49:36.466] <TB1> INFO: ----------------------------------------------------------------------
[14:49:36.466] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[14:49:36.466] <TB1> INFO: ----------------------------------------------------------------------
[14:49:36.508] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:49:36.508] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:49:36.521] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:49:36.521] <TB1> INFO: run 1 of 1
[14:49:36.768] <TB1> INFO: Expecting 5025280 events.
[14:50:06.739] <TB1> INFO: 811352 events read in total (29363ms).
[14:50:36.297] <TB1> INFO: 1619600 events read in total (58921ms).
[14:51:05.001] <TB1> INFO: 2424016 events read in total (88626ms).
[14:51:35.561] <TB1> INFO: 3225136 events read in total (118185ms).
[14:52:05.321] <TB1> INFO: 4024624 events read in total (147946ms).
[14:52:34.770] <TB1> INFO: 4822792 events read in total (177394ms).
[14:52:42.557] <TB1> INFO: 5025280 events read in total (185181ms).
[14:52:42.648] <TB1> INFO: Test took 186128ms.
[14:53:02.847] <TB1> INFO: ROC 0 VthrComp = 117
[14:53:02.847] <TB1> INFO: ROC 1 VthrComp = 108
[14:53:02.847] <TB1> INFO: ROC 2 VthrComp = 113
[14:53:02.847] <TB1> INFO: ROC 3 VthrComp = 107
[14:53:02.847] <TB1> INFO: ROC 4 VthrComp = 121
[14:53:02.847] <TB1> INFO: ROC 5 VthrComp = 123
[14:53:02.847] <TB1> INFO: ROC 6 VthrComp = 109
[14:53:02.847] <TB1> INFO: ROC 7 VthrComp = 121
[14:53:02.848] <TB1> INFO: ROC 8 VthrComp = 95
[14:53:02.848] <TB1> INFO: ROC 9 VthrComp = 119
[14:53:02.848] <TB1> INFO: ROC 10 VthrComp = 104
[14:53:02.848] <TB1> INFO: ROC 11 VthrComp = 117
[14:53:02.848] <TB1> INFO: ROC 12 VthrComp = 114
[14:53:02.848] <TB1> INFO: ROC 13 VthrComp = 124
[14:53:02.849] <TB1> INFO: ROC 14 VthrComp = 105
[14:53:02.849] <TB1> INFO: ROC 15 VthrComp = 112
[14:53:03.093] <TB1> INFO: Expecting 41600 events.
[14:53:06.690] <TB1> INFO: 41600 events read in total (3005ms).
[14:53:06.691] <TB1> INFO: Test took 3841ms.
[14:53:06.701] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:53:06.701] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:53:06.713] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:53:06.713] <TB1> INFO: run 1 of 1
[14:53:06.991] <TB1> INFO: Expecting 5025280 events.
[14:53:33.607] <TB1> INFO: 591336 events read in total (26024ms).
[14:53:59.500] <TB1> INFO: 1181272 events read in total (51917ms).
[14:54:25.105] <TB1> INFO: 1770544 events read in total (77522ms).
[14:54:50.867] <TB1> INFO: 2359144 events read in total (103284ms).
[14:55:16.737] <TB1> INFO: 2945496 events read in total (129154ms).
[14:55:42.489] <TB1> INFO: 3530824 events read in total (154906ms).
[14:56:08.608] <TB1> INFO: 4116200 events read in total (181025ms).
[14:56:34.222] <TB1> INFO: 4700792 events read in total (206639ms).
[14:56:48.315] <TB1> INFO: 5025280 events read in total (220732ms).
[14:56:48.404] <TB1> INFO: Test took 221691ms.
[14:57:15.484] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 58.1812 for pixel 50/6 mean/min/max = 45.0247/31.863/58.1864
[14:57:15.485] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 63.5723 for pixel 16/69 mean/min/max = 48.9122/34.1151/63.7092
[14:57:15.485] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 58.6639 for pixel 16/2 mean/min/max = 45.7422/32.7753/58.7091
[14:57:15.486] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 59.4338 for pixel 36/45 mean/min/max = 47.1765/34.861/59.4919
[14:57:15.486] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 60.7133 for pixel 4/4 mean/min/max = 46.3809/31.9808/60.781
[14:57:15.486] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 58.7867 for pixel 40/0 mean/min/max = 44.8404/30.8764/58.8043
[14:57:15.487] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 61.8927 for pixel 5/28 mean/min/max = 48.2441/34.5898/61.8984
[14:57:15.487] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 60.378 for pixel 40/3 mean/min/max = 46.1151/31.696/60.5341
[14:57:15.487] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 60.6731 for pixel 2/68 mean/min/max = 46.9138/33.0423/60.7853
[14:57:15.488] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 57.1899 for pixel 4/1 mean/min/max = 44.3223/31.1903/57.4542
[14:57:15.488] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 61.4581 for pixel 20/13 mean/min/max = 48.3246/35.1049/61.5443
[14:57:15.489] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 59.1017 for pixel 20/76 mean/min/max = 45.4884/31.8182/59.1586
[14:57:15.489] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 57.7997 for pixel 14/0 mean/min/max = 44.943/32.0856/57.8004
[14:57:15.489] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 60.7098 for pixel 0/19 mean/min/max = 45.9175/31.1177/60.7173
[14:57:15.490] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 59.8875 for pixel 16/5 mean/min/max = 47.489/35.0586/59.9195
[14:57:15.490] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 56.9998 for pixel 33/10 mean/min/max = 45.2512/33.0737/57.4286
[14:57:15.491] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:57:15.580] <TB1> INFO: Expecting 411648 events.
[14:57:25.125] <TB1> INFO: 411648 events read in total (8953ms).
[14:57:25.132] <TB1> INFO: Expecting 411648 events.
[14:57:34.441] <TB1> INFO: 411648 events read in total (8906ms).
[14:57:34.452] <TB1> INFO: Expecting 411648 events.
[14:57:43.869] <TB1> INFO: 411648 events read in total (9014ms).
[14:57:43.882] <TB1> INFO: Expecting 411648 events.
[14:57:53.313] <TB1> INFO: 411648 events read in total (9028ms).
[14:57:53.329] <TB1> INFO: Expecting 411648 events.
[14:58:02.705] <TB1> INFO: 411648 events read in total (8973ms).
[14:58:02.724] <TB1> INFO: Expecting 411648 events.
[14:58:12.134] <TB1> INFO: 411648 events read in total (9006ms).
[14:58:12.162] <TB1> INFO: Expecting 411648 events.
[14:58:21.566] <TB1> INFO: 411648 events read in total (9001ms).
[14:58:21.591] <TB1> INFO: Expecting 411648 events.
[14:58:31.067] <TB1> INFO: 411648 events read in total (9073ms).
[14:58:31.094] <TB1> INFO: Expecting 411648 events.
[14:58:40.545] <TB1> INFO: 411648 events read in total (9048ms).
[14:58:40.585] <TB1> INFO: Expecting 411648 events.
[14:58:50.025] <TB1> INFO: 411648 events read in total (9037ms).
[14:58:50.069] <TB1> INFO: Expecting 411648 events.
[14:58:59.506] <TB1> INFO: 411648 events read in total (9034ms).
[14:58:59.551] <TB1> INFO: Expecting 411648 events.
[14:59:08.864] <TB1> INFO: 411648 events read in total (8910ms).
[14:59:08.904] <TB1> INFO: Expecting 411648 events.
[14:59:18.299] <TB1> INFO: 411648 events read in total (8991ms).
[14:59:18.346] <TB1> INFO: Expecting 411648 events.
[14:59:27.558] <TB1> INFO: 411648 events read in total (8809ms).
[14:59:27.610] <TB1> INFO: Expecting 411648 events.
[14:59:37.130] <TB1> INFO: 411648 events read in total (9117ms).
[14:59:37.187] <TB1> INFO: Expecting 411648 events.
[14:59:46.395] <TB1> INFO: 411648 events read in total (8805ms).
[14:59:46.477] <TB1> INFO: Test took 150986ms.
[14:59:47.299] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:59:47.314] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:59:47.314] <TB1> INFO: run 1 of 1
[14:59:47.556] <TB1> INFO: Expecting 5025280 events.
[15:00:14.091] <TB1> INFO: 586248 events read in total (25943ms).
[15:00:39.700] <TB1> INFO: 1170600 events read in total (51553ms).
[15:01:05.855] <TB1> INFO: 1755184 events read in total (77707ms).
[15:01:31.836] <TB1> INFO: 2339696 events read in total (103688ms).
[15:01:57.413] <TB1> INFO: 2921496 events read in total (129265ms).
[15:02:23.472] <TB1> INFO: 3502624 events read in total (155324ms).
[15:02:49.096] <TB1> INFO: 4083112 events read in total (180948ms).
[15:03:15.942] <TB1> INFO: 4664600 events read in total (207794ms).
[15:03:32.274] <TB1> INFO: 5025280 events read in total (224126ms).
[15:03:32.436] <TB1> INFO: Test took 225124ms.
[15:03:55.043] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 2.377991 .. 141.683275
[15:03:55.301] <TB1> INFO: Expecting 208000 events.
[15:04:04.870] <TB1> INFO: 208000 events read in total (8977ms).
[15:04:04.872] <TB1> INFO: Test took 9828ms.
[15:04:04.939] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 151 (-1/-1) hits flags = 528 (plus default)
[15:04:04.954] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[15:04:04.954] <TB1> INFO: run 1 of 1
[15:04:05.232] <TB1> INFO: Expecting 4992000 events.
[15:04:31.125] <TB1> INFO: 584680 events read in total (25301ms).
[15:04:56.493] <TB1> INFO: 1169304 events read in total (50669ms).
[15:05:22.169] <TB1> INFO: 1753816 events read in total (76345ms).
[15:05:47.660] <TB1> INFO: 2338416 events read in total (101836ms).
[15:06:13.331] <TB1> INFO: 2922832 events read in total (127507ms).
[15:06:38.757] <TB1> INFO: 3506816 events read in total (152933ms).
[15:07:04.571] <TB1> INFO: 4090464 events read in total (178747ms).
[15:07:30.584] <TB1> INFO: 4673816 events read in total (204760ms).
[15:07:45.022] <TB1> INFO: 4992000 events read in total (219198ms).
[15:07:45.114] <TB1> INFO: Test took 220160ms.
[15:08:10.456] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 28.152258 .. 46.925116
[15:08:10.696] <TB1> INFO: Expecting 208000 events.
[15:08:20.548] <TB1> INFO: 208000 events read in total (9261ms).
[15:08:20.549] <TB1> INFO: Test took 10091ms.
[15:08:20.597] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 18 .. 56 (-1/-1) hits flags = 528 (plus default)
[15:08:20.610] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[15:08:20.610] <TB1> INFO: run 1 of 1
[15:08:20.888] <TB1> INFO: Expecting 1297920 events.
[15:08:49.883] <TB1> INFO: 650128 events read in total (28403ms).
[15:09:17.207] <TB1> INFO: 1297920 events read in total (55728ms).
[15:09:17.250] <TB1> INFO: Test took 56640ms.
[15:09:31.888] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 25.879530 .. 45.574652
[15:09:32.172] <TB1> INFO: Expecting 208000 events.
[15:09:41.803] <TB1> INFO: 208000 events read in total (9040ms).
[15:09:41.804] <TB1> INFO: Test took 9914ms.
[15:09:41.875] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[15:09:41.888] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[15:09:41.888] <TB1> INFO: run 1 of 1
[15:09:42.166] <TB1> INFO: Expecting 1364480 events.
[15:10:10.519] <TB1> INFO: 667496 events read in total (27762ms).
[15:10:38.620] <TB1> INFO: 1333856 events read in total (55863ms).
[15:10:40.412] <TB1> INFO: 1364480 events read in total (57655ms).
[15:10:40.441] <TB1> INFO: Test took 58554ms.
[15:10:55.881] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 24.140199 .. 43.142969
[15:10:56.126] <TB1> INFO: Expecting 208000 events.
[15:11:05.754] <TB1> INFO: 208000 events read in total (9036ms).
[15:11:05.755] <TB1> INFO: Test took 9873ms.
[15:11:05.803] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 53 (-1/-1) hits flags = 528 (plus default)
[15:11:05.814] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[15:11:05.814] <TB1> INFO: run 1 of 1
[15:11:06.092] <TB1> INFO: Expecting 1331200 events.
[15:11:34.492] <TB1> INFO: 679688 events read in total (27808ms).
[15:12:02.105] <TB1> INFO: 1331200 events read in total (55421ms).
[15:12:02.145] <TB1> INFO: Test took 56331ms.
[15:12:15.676] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[15:12:15.676] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[15:12:15.688] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[15:12:15.688] <TB1> INFO: run 1 of 1
[15:12:15.925] <TB1> INFO: Expecting 1364480 events.
[15:12:44.712] <TB1> INFO: 667088 events read in total (28195ms).
[15:13:12.542] <TB1> INFO: 1333872 events read in total (56026ms).
[15:13:14.224] <TB1> INFO: 1364480 events read in total (57707ms).
[15:13:14.260] <TB1> INFO: Test took 58572ms.
[15:13:28.150] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C0.dat
[15:13:28.150] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C1.dat
[15:13:28.150] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C2.dat
[15:13:28.150] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C3.dat
[15:13:28.150] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C4.dat
[15:13:28.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C5.dat
[15:13:28.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C6.dat
[15:13:28.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C7.dat
[15:13:28.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C8.dat
[15:13:28.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C9.dat
[15:13:28.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C10.dat
[15:13:28.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C11.dat
[15:13:28.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C12.dat
[15:13:28.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C13.dat
[15:13:28.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C14.dat
[15:13:28.151] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C15.dat
[15:13:28.151] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C0.dat
[15:13:28.156] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C1.dat
[15:13:28.161] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C2.dat
[15:13:28.166] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C3.dat
[15:13:28.171] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C4.dat
[15:13:28.175] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C5.dat
[15:13:28.180] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C6.dat
[15:13:28.185] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C7.dat
[15:13:28.190] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C8.dat
[15:13:28.195] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C9.dat
[15:13:28.200] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C10.dat
[15:13:28.205] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C11.dat
[15:13:28.211] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C12.dat
[15:13:28.217] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C13.dat
[15:13:28.224] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C14.dat
[15:13:28.230] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//trimParameters35_C15.dat
[15:13:28.236] <TB1> INFO: PixTestTrim::trimTest() done
[15:13:28.236] <TB1> INFO: vtrim: 124 146 116 122 132 133 127 126 118 118 132 120 116 117 134 112
[15:13:28.236] <TB1> INFO: vthrcomp: 117 108 113 107 121 123 109 121 95 119 104 117 114 124 105 112
[15:13:28.236] <TB1> INFO: vcal mean: 34.95 35.04 34.95 34.94 34.92 34.97 34.96 34.97 35.01 34.90 34.95 34.88 34.92 34.96 35.00 34.93
[15:13:28.236] <TB1> INFO: vcal RMS: 1.00 1.10 0.93 0.89 1.04 1.12 1.01 1.13 1.22 1.08 0.95 1.08 0.99 1.13 0.94 0.94
[15:13:28.236] <TB1> INFO: bits mean: 9.82 8.88 9.44 8.77 9.05 10.20 8.79 9.66 9.72 9.70 8.42 9.99 9.63 9.41 8.82 9.43
[15:13:28.236] <TB1> INFO: bits RMS: 2.63 2.49 2.67 2.51 2.90 2.59 2.50 2.64 2.47 2.83 2.62 2.52 2.70 2.86 2.48 2.66
[15:13:28.244] <TB1> INFO: ----------------------------------------------------------------------
[15:13:28.244] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[15:13:28.244] <TB1> INFO: ----------------------------------------------------------------------
[15:13:28.247] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[15:13:28.259] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:13:28.259] <TB1> INFO: run 1 of 1
[15:13:28.497] <TB1> INFO: Expecting 4160000 events.
[15:14:00.374] <TB1> INFO: 726040 events read in total (31285ms).
[15:14:31.603] <TB1> INFO: 1445255 events read in total (62514ms).
[15:15:02.449] <TB1> INFO: 2160215 events read in total (93360ms).
[15:15:33.450] <TB1> INFO: 2870400 events read in total (124361ms).
[15:16:04.872] <TB1> INFO: 3579970 events read in total (155783ms).
[15:16:29.665] <TB1> INFO: 4160000 events read in total (180576ms).
[15:16:29.751] <TB1> INFO: Test took 181492ms.
[15:17:03.441] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 191 (-1/-1) hits flags = 528 (plus default)
[15:17:03.455] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:17:03.455] <TB1> INFO: run 1 of 1
[15:17:03.693] <TB1> INFO: Expecting 3993600 events.
[15:17:35.134] <TB1> INFO: 712620 events read in total (30849ms).
[15:18:05.853] <TB1> INFO: 1419570 events read in total (61568ms).
[15:18:36.723] <TB1> INFO: 2122535 events read in total (92438ms).
[15:19:07.432] <TB1> INFO: 2821925 events read in total (123147ms).
[15:19:38.535] <TB1> INFO: 3521020 events read in total (154250ms).
[15:19:59.073] <TB1> INFO: 3993600 events read in total (174788ms).
[15:19:59.200] <TB1> INFO: Test took 175744ms.
[15:20:24.532] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 184 (-1/-1) hits flags = 528 (plus default)
[15:20:24.546] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:20:24.546] <TB1> INFO: run 1 of 1
[15:20:24.829] <TB1> INFO: Expecting 3848000 events.
[15:20:56.645] <TB1> INFO: 722010 events read in total (31225ms).
[15:21:27.763] <TB1> INFO: 1437515 events read in total (62343ms).
[15:21:58.865] <TB1> INFO: 2148930 events read in total (93445ms).
[15:22:29.845] <TB1> INFO: 2856470 events read in total (124425ms).
[15:23:00.674] <TB1> INFO: 3564885 events read in total (155254ms).
[15:23:13.199] <TB1> INFO: 3848000 events read in total (167779ms).
[15:23:13.269] <TB1> INFO: Test took 168722ms.
[15:23:38.721] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 186 (-1/-1) hits flags = 528 (plus default)
[15:23:38.734] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:23:38.734] <TB1> INFO: run 1 of 1
[15:23:38.998] <TB1> INFO: Expecting 3889600 events.
[15:24:10.902] <TB1> INFO: 719420 events read in total (31312ms).
[15:24:41.459] <TB1> INFO: 1433050 events read in total (61869ms).
[15:25:12.309] <TB1> INFO: 2142055 events read in total (92719ms).
[15:25:42.730] <TB1> INFO: 2847635 events read in total (123140ms).
[15:26:13.745] <TB1> INFO: 3553435 events read in total (154155ms).
[15:26:28.596] <TB1> INFO: 3889600 events read in total (169006ms).
[15:26:28.676] <TB1> INFO: Test took 169942ms.
[15:26:53.592] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 185 (-1/-1) hits flags = 528 (plus default)
[15:26:53.605] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:26:53.605] <TB1> INFO: run 1 of 1
[15:26:53.842] <TB1> INFO: Expecting 3868800 events.
[15:27:25.457] <TB1> INFO: 720605 events read in total (31024ms).
[15:27:56.406] <TB1> INFO: 1435465 events read in total (61973ms).
[15:28:27.115] <TB1> INFO: 2145815 events read in total (92682ms).
[15:28:57.882] <TB1> INFO: 2852860 events read in total (123449ms).
[15:29:28.906] <TB1> INFO: 3560095 events read in total (154474ms).
[15:29:42.809] <TB1> INFO: 3868800 events read in total (168376ms).
[15:29:42.880] <TB1> INFO: Test took 169275ms.
[15:30:11.321] <TB1> INFO: PixTestTrim::trimBitTest() done
[15:30:11.322] <TB1> INFO: PixTestTrim::doTest() done, duration: 2434 seconds
[15:30:11.322] <TB1> INFO: Decoding statistics:
[15:30:11.322] <TB1> INFO: General information:
[15:30:11.322] <TB1> INFO: 16bit words read: 0
[15:30:11.322] <TB1> INFO: valid events total: 0
[15:30:11.322] <TB1> INFO: empty events: 0
[15:30:11.322] <TB1> INFO: valid events with pixels: 0
[15:30:11.322] <TB1> INFO: valid pixel hits: 0
[15:30:11.322] <TB1> INFO: Event errors: 0
[15:30:11.322] <TB1> INFO: start marker: 0
[15:30:11.322] <TB1> INFO: stop marker: 0
[15:30:11.322] <TB1> INFO: overflow: 0
[15:30:11.323] <TB1> INFO: invalid 5bit words: 0
[15:30:11.323] <TB1> INFO: invalid XOR eye diagram: 0
[15:30:11.323] <TB1> INFO: frame (failed synchr.): 0
[15:30:11.323] <TB1> INFO: idle data (no TBM trl): 0
[15:30:11.323] <TB1> INFO: no data (only TBM hdr): 0
[15:30:11.323] <TB1> INFO: TBM errors: 0
[15:30:11.323] <TB1> INFO: flawed TBM headers: 0
[15:30:11.323] <TB1> INFO: flawed TBM trailers: 0
[15:30:11.323] <TB1> INFO: event ID mismatches: 0
[15:30:11.323] <TB1> INFO: ROC errors: 0
[15:30:11.323] <TB1> INFO: missing ROC header(s): 0
[15:30:11.323] <TB1> INFO: misplaced readback start: 0
[15:30:11.323] <TB1> INFO: Pixel decoding errors: 0
[15:30:11.323] <TB1> INFO: pixel data incomplete: 0
[15:30:11.323] <TB1> INFO: pixel address: 0
[15:30:11.323] <TB1> INFO: pulse height fill bit: 0
[15:30:11.323] <TB1> INFO: buffer corruption: 0
[15:30:11.003] <TB1> INFO: ######################################################################
[15:30:11.003] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[15:30:11.003] <TB1> INFO: ######################################################################
[15:30:12.292] <TB1> INFO: Expecting 41600 events.
[15:30:15.852] <TB1> INFO: 41600 events read in total (2968ms).
[15:30:15.853] <TB1> INFO: Test took 3849ms.
[15:30:16.310] <TB1> INFO: Expecting 41600 events.
[15:30:19.912] <TB1> INFO: 41600 events read in total (3010ms).
[15:30:19.914] <TB1> INFO: Test took 3851ms.
[15:30:20.205] <TB1> INFO: Expecting 41600 events.
[15:30:23.687] <TB1> INFO: 41600 events read in total (2890ms).
[15:30:23.688] <TB1> INFO: Test took 3747ms.
[15:30:23.977] <TB1> INFO: Expecting 41600 events.
[15:30:27.520] <TB1> INFO: 41600 events read in total (2952ms).
[15:30:27.520] <TB1> INFO: Test took 3808ms.
[15:30:27.814] <TB1> INFO: Expecting 41600 events.
[15:30:31.376] <TB1> INFO: 41600 events read in total (2971ms).
[15:30:31.377] <TB1> INFO: Test took 3830ms.
[15:30:31.667] <TB1> INFO: Expecting 41600 events.
[15:30:35.213] <TB1> INFO: 41600 events read in total (2955ms).
[15:30:35.214] <TB1> INFO: Test took 3813ms.
[15:30:35.502] <TB1> INFO: Expecting 41600 events.
[15:30:39.112] <TB1> INFO: 41600 events read in total (3018ms).
[15:30:39.112] <TB1> INFO: Test took 3875ms.
[15:30:39.414] <TB1> INFO: Expecting 41600 events.
[15:30:43.071] <TB1> INFO: 41600 events read in total (3065ms).
[15:30:43.071] <TB1> INFO: Test took 3935ms.
[15:30:43.406] <TB1> INFO: Expecting 41600 events.
[15:30:46.938] <TB1> INFO: 41600 events read in total (2940ms).
[15:30:46.939] <TB1> INFO: Test took 3844ms.
[15:30:47.230] <TB1> INFO: Expecting 41600 events.
[15:30:50.721] <TB1> INFO: 41600 events read in total (2899ms).
[15:30:50.721] <TB1> INFO: Test took 3755ms.
[15:30:51.056] <TB1> INFO: Expecting 41600 events.
[15:30:54.554] <TB1> INFO: 41600 events read in total (2907ms).
[15:30:54.555] <TB1> INFO: Test took 3810ms.
[15:30:54.845] <TB1> INFO: Expecting 41600 events.
[15:30:58.347] <TB1> INFO: 41600 events read in total (2911ms).
[15:30:58.348] <TB1> INFO: Test took 3768ms.
[15:30:58.637] <TB1> INFO: Expecting 41600 events.
[15:31:02.241] <TB1> INFO: 41600 events read in total (3012ms).
[15:31:02.242] <TB1> INFO: Test took 3869ms.
[15:31:02.531] <TB1> INFO: Expecting 41600 events.
[15:31:06.127] <TB1> INFO: 41600 events read in total (3004ms).
[15:31:06.127] <TB1> INFO: Test took 3861ms.
[15:31:06.416] <TB1> INFO: Expecting 41600 events.
[15:31:09.924] <TB1> INFO: 41600 events read in total (2917ms).
[15:31:09.925] <TB1> INFO: Test took 3774ms.
[15:31:10.215] <TB1> INFO: Expecting 41600 events.
[15:31:13.865] <TB1> INFO: 41600 events read in total (3059ms).
[15:31:13.866] <TB1> INFO: Test took 3917ms.
[15:31:14.155] <TB1> INFO: Expecting 41600 events.
[15:31:17.774] <TB1> INFO: 41600 events read in total (3027ms).
[15:31:17.775] <TB1> INFO: Test took 3885ms.
[15:31:18.066] <TB1> INFO: Expecting 41600 events.
[15:31:21.582] <TB1> INFO: 41600 events read in total (2925ms).
[15:31:21.582] <TB1> INFO: Test took 3781ms.
[15:31:21.871] <TB1> INFO: Expecting 41600 events.
[15:31:25.372] <TB1> INFO: 41600 events read in total (2909ms).
[15:31:25.373] <TB1> INFO: Test took 3767ms.
[15:31:25.663] <TB1> INFO: Expecting 41600 events.
[15:31:29.250] <TB1> INFO: 41600 events read in total (2996ms).
[15:31:29.250] <TB1> INFO: Test took 3852ms.
[15:31:29.540] <TB1> INFO: Expecting 41600 events.
[15:31:33.193] <TB1> INFO: 41600 events read in total (3061ms).
[15:31:33.194] <TB1> INFO: Test took 3919ms.
[15:31:33.482] <TB1> INFO: Expecting 41600 events.
[15:31:37.025] <TB1> INFO: 41600 events read in total (2951ms).
[15:31:37.026] <TB1> INFO: Test took 3808ms.
[15:31:37.315] <TB1> INFO: Expecting 41600 events.
[15:31:40.809] <TB1> INFO: 41600 events read in total (2902ms).
[15:31:40.809] <TB1> INFO: Test took 3759ms.
[15:31:41.098] <TB1> INFO: Expecting 41600 events.
[15:31:44.773] <TB1> INFO: 41600 events read in total (3083ms).
[15:31:44.774] <TB1> INFO: Test took 3941ms.
[15:31:45.083] <TB1> INFO: Expecting 41600 events.
[15:31:48.703] <TB1> INFO: 41600 events read in total (3029ms).
[15:31:48.704] <TB1> INFO: Test took 3906ms.
[15:31:48.003] <TB1> INFO: Expecting 41600 events.
[15:31:52.475] <TB1> INFO: 41600 events read in total (2881ms).
[15:31:52.475] <TB1> INFO: Test took 3744ms.
[15:31:52.765] <TB1> INFO: Expecting 41600 events.
[15:31:56.456] <TB1> INFO: 41600 events read in total (3100ms).
[15:31:56.456] <TB1> INFO: Test took 3956ms.
[15:31:56.749] <TB1> INFO: Expecting 41600 events.
[15:32:00.340] <TB1> INFO: 41600 events read in total (2999ms).
[15:32:00.341] <TB1> INFO: Test took 3857ms.
[15:32:00.652] <TB1> INFO: Expecting 41600 events.
[15:32:04.129] <TB1> INFO: 41600 events read in total (2886ms).
[15:32:04.130] <TB1> INFO: Test took 3763ms.
[15:32:04.420] <TB1> INFO: Expecting 41600 events.
[15:32:07.911] <TB1> INFO: 41600 events read in total (2899ms).
[15:32:07.912] <TB1> INFO: Test took 3757ms.
[15:32:08.202] <TB1> INFO: Expecting 2560 events.
[15:32:09.084] <TB1> INFO: 2560 events read in total (291ms).
[15:32:09.085] <TB1> INFO: Test took 1160ms.
[15:32:09.395] <TB1> INFO: Expecting 2560 events.
[15:32:10.281] <TB1> INFO: 2560 events read in total (294ms).
[15:32:10.281] <TB1> INFO: Test took 1197ms.
[15:32:10.589] <TB1> INFO: Expecting 2560 events.
[15:32:11.472] <TB1> INFO: 2560 events read in total (291ms).
[15:32:11.472] <TB1> INFO: Test took 1190ms.
[15:32:11.780] <TB1> INFO: Expecting 2560 events.
[15:32:12.665] <TB1> INFO: 2560 events read in total (293ms).
[15:32:12.665] <TB1> INFO: Test took 1192ms.
[15:32:12.977] <TB1> INFO: Expecting 2560 events.
[15:32:13.857] <TB1> INFO: 2560 events read in total (289ms).
[15:32:13.858] <TB1> INFO: Test took 1193ms.
[15:32:14.166] <TB1> INFO: Expecting 2560 events.
[15:32:15.055] <TB1> INFO: 2560 events read in total (297ms).
[15:32:15.056] <TB1> INFO: Test took 1198ms.
[15:32:15.363] <TB1> INFO: Expecting 2560 events.
[15:32:16.253] <TB1> INFO: 2560 events read in total (298ms).
[15:32:16.253] <TB1> INFO: Test took 1197ms.
[15:32:16.561] <TB1> INFO: Expecting 2560 events.
[15:32:17.451] <TB1> INFO: 2560 events read in total (299ms).
[15:32:17.451] <TB1> INFO: Test took 1198ms.
[15:32:17.761] <TB1> INFO: Expecting 2560 events.
[15:32:18.651] <TB1> INFO: 2560 events read in total (299ms).
[15:32:18.652] <TB1> INFO: Test took 1200ms.
[15:32:18.959] <TB1> INFO: Expecting 2560 events.
[15:32:19.853] <TB1> INFO: 2560 events read in total (302ms).
[15:32:19.854] <TB1> INFO: Test took 1202ms.
[15:32:20.160] <TB1> INFO: Expecting 2560 events.
[15:32:21.049] <TB1> INFO: 2560 events read in total (297ms).
[15:32:21.049] <TB1> INFO: Test took 1195ms.
[15:32:21.358] <TB1> INFO: Expecting 2560 events.
[15:32:22.242] <TB1> INFO: 2560 events read in total (292ms).
[15:32:22.243] <TB1> INFO: Test took 1193ms.
[15:32:22.550] <TB1> INFO: Expecting 2560 events.
[15:32:23.437] <TB1> INFO: 2560 events read in total (295ms).
[15:32:23.438] <TB1> INFO: Test took 1195ms.
[15:32:23.746] <TB1> INFO: Expecting 2560 events.
[15:32:24.632] <TB1> INFO: 2560 events read in total (295ms).
[15:32:24.632] <TB1> INFO: Test took 1194ms.
[15:32:24.939] <TB1> INFO: Expecting 2560 events.
[15:32:25.830] <TB1> INFO: 2560 events read in total (299ms).
[15:32:25.830] <TB1> INFO: Test took 1197ms.
[15:32:26.138] <TB1> INFO: Expecting 2560 events.
[15:32:27.034] <TB1> INFO: 2560 events read in total (304ms).
[15:32:27.035] <TB1> INFO: Test took 1204ms.
[15:32:27.039] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:32:27.343] <TB1> INFO: Expecting 655360 events.
[15:32:42.349] <TB1> INFO: 655360 events read in total (14414ms).
[15:32:42.360] <TB1> INFO: Expecting 655360 events.
[15:32:57.080] <TB1> INFO: 655360 events read in total (14316ms).
[15:32:57.101] <TB1> INFO: Expecting 655360 events.
[15:33:11.840] <TB1> INFO: 655360 events read in total (14336ms).
[15:33:11.860] <TB1> INFO: Expecting 655360 events.
[15:33:26.635] <TB1> INFO: 655360 events read in total (14372ms).
[15:33:26.661] <TB1> INFO: Expecting 655360 events.
[15:33:41.321] <TB1> INFO: 655360 events read in total (14257ms).
[15:33:41.349] <TB1> INFO: Expecting 655360 events.
[15:33:56.222] <TB1> INFO: 655360 events read in total (14470ms).
[15:33:56.258] <TB1> INFO: Expecting 655360 events.
[15:34:11.117] <TB1> INFO: 655360 events read in total (14456ms).
[15:34:11.160] <TB1> INFO: Expecting 655360 events.
[15:34:25.997] <TB1> INFO: 655360 events read in total (14434ms).
[15:34:26.052] <TB1> INFO: Expecting 655360 events.
[15:34:40.862] <TB1> INFO: 655360 events read in total (14407ms).
[15:34:40.970] <TB1> INFO: Expecting 655360 events.
[15:34:55.693] <TB1> INFO: 655360 events read in total (14320ms).
[15:34:55.748] <TB1> INFO: Expecting 655360 events.
[15:35:10.539] <TB1> INFO: 655360 events read in total (14388ms).
[15:35:10.614] <TB1> INFO: Expecting 655360 events.
[15:35:25.257] <TB1> INFO: 655360 events read in total (14240ms).
[15:35:25.321] <TB1> INFO: Expecting 655360 events.
[15:35:40.121] <TB1> INFO: 655360 events read in total (14397ms).
[15:35:40.226] <TB1> INFO: Expecting 655360 events.
[15:35:55.078] <TB1> INFO: 655360 events read in total (14449ms).
[15:35:55.194] <TB1> INFO: Expecting 655360 events.
[15:36:09.896] <TB1> INFO: 655360 events read in total (14299ms).
[15:36:10.011] <TB1> INFO: Expecting 655360 events.
[15:36:24.681] <TB1> INFO: 655360 events read in total (14267ms).
[15:36:24.799] <TB1> INFO: Test took 237760ms.
[15:36:24.902] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:36:25.159] <TB1> INFO: Expecting 655360 events.
[15:36:40.157] <TB1> INFO: 655360 events read in total (14406ms).
[15:36:40.169] <TB1> INFO: Expecting 655360 events.
[15:36:54.698] <TB1> INFO: 655360 events read in total (14125ms).
[15:36:54.715] <TB1> INFO: Expecting 655360 events.
[15:37:09.298] <TB1> INFO: 655360 events read in total (14180ms).
[15:37:09.318] <TB1> INFO: Expecting 655360 events.
[15:37:23.754] <TB1> INFO: 655360 events read in total (14033ms).
[15:37:23.780] <TB1> INFO: Expecting 655360 events.
[15:37:38.265] <TB1> INFO: 655360 events read in total (14082ms).
[15:37:38.294] <TB1> INFO: Expecting 655360 events.
[15:37:53.007] <TB1> INFO: 655360 events read in total (14310ms).
[15:37:53.055] <TB1> INFO: Expecting 655360 events.
[15:38:07.480] <TB1> INFO: 655360 events read in total (14019ms).
[15:38:07.522] <TB1> INFO: Expecting 655360 events.
[15:38:21.918] <TB1> INFO: 655360 events read in total (13993ms).
[15:38:21.960] <TB1> INFO: Expecting 655360 events.
[15:38:36.552] <TB1> INFO: 655360 events read in total (14189ms).
[15:38:36.629] <TB1> INFO: Expecting 655360 events.
[15:38:51.068] <TB1> INFO: 655360 events read in total (14036ms).
[15:38:51.136] <TB1> INFO: Expecting 655360 events.
[15:39:05.642] <TB1> INFO: 655360 events read in total (14099ms).
[15:39:05.775] <TB1> INFO: Expecting 655360 events.
[15:39:20.234] <TB1> INFO: 655360 events read in total (14055ms).
[15:39:20.297] <TB1> INFO: Expecting 655360 events.
[15:39:34.822] <TB1> INFO: 655360 events read in total (14122ms).
[15:39:34.905] <TB1> INFO: Expecting 655360 events.
[15:39:49.371] <TB1> INFO: 655360 events read in total (14062ms).
[15:39:49.459] <TB1> INFO: Expecting 655360 events.
[15:40:03.934] <TB1> INFO: 655360 events read in total (14069ms).
[15:40:04.035] <TB1> INFO: Expecting 655360 events.
[15:40:18.549] <TB1> INFO: 655360 events read in total (14111ms).
[15:40:18.689] <TB1> INFO: Test took 233787ms.
[15:40:18.869] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:18.875] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:18.882] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:40:18.889] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:40:18.895] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:40:18.902] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:18.908] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:18.915] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:40:18.922] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:40:18.928] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:40:18.934] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:18.941] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:18.947] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:18.954] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:18.960] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:18.967] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:40:18.973] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:40:18.979] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:40:18.986] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[15:40:18.992] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:18.998] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.005] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.011] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.017] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.023] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.030] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:40:19.036] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:40:19.071] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C0.dat
[15:40:19.072] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C1.dat
[15:40:19.072] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C2.dat
[15:40:19.072] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C3.dat
[15:40:19.072] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C4.dat
[15:40:19.072] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C5.dat
[15:40:19.072] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C6.dat
[15:40:19.072] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C7.dat
[15:40:19.072] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C8.dat
[15:40:19.072] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C9.dat
[15:40:19.073] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C10.dat
[15:40:19.073] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C11.dat
[15:40:19.073] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C12.dat
[15:40:19.073] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C13.dat
[15:40:19.073] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C14.dat
[15:40:19.073] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//dacParameters35_C15.dat
[15:40:19.315] <TB1> INFO: Expecting 41600 events.
[15:40:22.477] <TB1> INFO: 41600 events read in total (2571ms).
[15:40:22.478] <TB1> INFO: Test took 3402ms.
[15:40:22.930] <TB1> INFO: Expecting 41600 events.
[15:40:26.067] <TB1> INFO: 41600 events read in total (2545ms).
[15:40:26.068] <TB1> INFO: Test took 3377ms.
[15:40:26.521] <TB1> INFO: Expecting 41600 events.
[15:40:29.703] <TB1> INFO: 41600 events read in total (2590ms).
[15:40:29.704] <TB1> INFO: Test took 3422ms.
[15:40:29.923] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:30.012] <TB1> INFO: Expecting 2560 events.
[15:40:30.898] <TB1> INFO: 2560 events read in total (294ms).
[15:40:30.898] <TB1> INFO: Test took 975ms.
[15:40:30.901] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:31.206] <TB1> INFO: Expecting 2560 events.
[15:40:32.103] <TB1> INFO: 2560 events read in total (305ms).
[15:40:32.104] <TB1> INFO: Test took 1203ms.
[15:40:32.107] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:32.411] <TB1> INFO: Expecting 2560 events.
[15:40:33.301] <TB1> INFO: 2560 events read in total (298ms).
[15:40:33.302] <TB1> INFO: Test took 1195ms.
[15:40:33.305] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:33.610] <TB1> INFO: Expecting 2560 events.
[15:40:34.505] <TB1> INFO: 2560 events read in total (303ms).
[15:40:34.505] <TB1> INFO: Test took 1200ms.
[15:40:34.508] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:34.814] <TB1> INFO: Expecting 2560 events.
[15:40:35.706] <TB1> INFO: 2560 events read in total (300ms).
[15:40:35.706] <TB1> INFO: Test took 1198ms.
[15:40:35.710] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:36.014] <TB1> INFO: Expecting 2560 events.
[15:40:36.904] <TB1> INFO: 2560 events read in total (298ms).
[15:40:36.905] <TB1> INFO: Test took 1195ms.
[15:40:36.907] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:37.213] <TB1> INFO: Expecting 2560 events.
[15:40:38.101] <TB1> INFO: 2560 events read in total (296ms).
[15:40:38.101] <TB1> INFO: Test took 1194ms.
[15:40:38.104] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:38.409] <TB1> INFO: Expecting 2560 events.
[15:40:39.303] <TB1> INFO: 2560 events read in total (302ms).
[15:40:39.303] <TB1> INFO: Test took 1199ms.
[15:40:39.308] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:39.611] <TB1> INFO: Expecting 2560 events.
[15:40:40.500] <TB1> INFO: 2560 events read in total (297ms).
[15:40:40.501] <TB1> INFO: Test took 1193ms.
[15:40:40.505] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:40.809] <TB1> INFO: Expecting 2560 events.
[15:40:41.702] <TB1> INFO: 2560 events read in total (301ms).
[15:40:41.703] <TB1> INFO: Test took 1198ms.
[15:40:41.707] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:42.011] <TB1> INFO: Expecting 2560 events.
[15:40:42.903] <TB1> INFO: 2560 events read in total (300ms).
[15:40:42.903] <TB1> INFO: Test took 1196ms.
[15:40:42.906] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:43.211] <TB1> INFO: Expecting 2560 events.
[15:40:44.102] <TB1> INFO: 2560 events read in total (299ms).
[15:40:44.103] <TB1> INFO: Test took 1197ms.
[15:40:44.108] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:44.411] <TB1> INFO: Expecting 2560 events.
[15:40:45.303] <TB1> INFO: 2560 events read in total (300ms).
[15:40:45.304] <TB1> INFO: Test took 1197ms.
[15:40:45.307] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:45.611] <TB1> INFO: Expecting 2560 events.
[15:40:46.506] <TB1> INFO: 2560 events read in total (303ms).
[15:40:46.506] <TB1> INFO: Test took 1199ms.
[15:40:46.508] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:46.813] <TB1> INFO: Expecting 2560 events.
[15:40:47.694] <TB1> INFO: 2560 events read in total (289ms).
[15:40:47.695] <TB1> INFO: Test took 1187ms.
[15:40:47.697] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:47.002] <TB1> INFO: Expecting 2560 events.
[15:40:48.887] <TB1> INFO: 2560 events read in total (293ms).
[15:40:48.887] <TB1> INFO: Test took 1190ms.
[15:40:48.891] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:49.196] <TB1> INFO: Expecting 2560 events.
[15:40:50.085] <TB1> INFO: 2560 events read in total (297ms).
[15:40:50.086] <TB1> INFO: Test took 1195ms.
[15:40:50.090] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:50.393] <TB1> INFO: Expecting 2560 events.
[15:40:51.284] <TB1> INFO: 2560 events read in total (299ms).
[15:40:51.284] <TB1> INFO: Test took 1194ms.
[15:40:51.287] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:51.593] <TB1> INFO: Expecting 2560 events.
[15:40:52.480] <TB1> INFO: 2560 events read in total (296ms).
[15:40:52.480] <TB1> INFO: Test took 1193ms.
[15:40:52.483] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:52.791] <TB1> INFO: Expecting 2560 events.
[15:40:53.679] <TB1> INFO: 2560 events read in total (296ms).
[15:40:53.680] <TB1> INFO: Test took 1197ms.
[15:40:53.683] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:53.989] <TB1> INFO: Expecting 2560 events.
[15:40:54.879] <TB1> INFO: 2560 events read in total (298ms).
[15:40:54.880] <TB1> INFO: Test took 1197ms.
[15:40:54.883] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:55.187] <TB1> INFO: Expecting 2560 events.
[15:40:56.075] <TB1> INFO: 2560 events read in total (296ms).
[15:40:56.075] <TB1> INFO: Test took 1192ms.
[15:40:56.078] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:56.384] <TB1> INFO: Expecting 2560 events.
[15:40:57.276] <TB1> INFO: 2560 events read in total (300ms).
[15:40:57.276] <TB1> INFO: Test took 1198ms.
[15:40:57.280] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:57.584] <TB1> INFO: Expecting 2560 events.
[15:40:58.470] <TB1> INFO: 2560 events read in total (295ms).
[15:40:58.470] <TB1> INFO: Test took 1190ms.
[15:40:58.473] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:58.778] <TB1> INFO: Expecting 2560 events.
[15:40:59.671] <TB1> INFO: 2560 events read in total (301ms).
[15:40:59.672] <TB1> INFO: Test took 1199ms.
[15:40:59.676] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:40:59.980] <TB1> INFO: Expecting 2560 events.
[15:41:00.872] <TB1> INFO: 2560 events read in total (300ms).
[15:41:00.872] <TB1> INFO: Test took 1196ms.
[15:41:00.875] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:41:01.180] <TB1> INFO: Expecting 2560 events.
[15:41:02.075] <TB1> INFO: 2560 events read in total (303ms).
[15:41:02.075] <TB1> INFO: Test took 1200ms.
[15:41:02.078] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:41:02.385] <TB1> INFO: Expecting 2560 events.
[15:41:03.278] <TB1> INFO: 2560 events read in total (301ms).
[15:41:03.279] <TB1> INFO: Test took 1201ms.
[15:41:03.285] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:41:03.587] <TB1> INFO: Expecting 2560 events.
[15:41:04.483] <TB1> INFO: 2560 events read in total (305ms).
[15:41:04.484] <TB1> INFO: Test took 1199ms.
[15:41:04.487] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:41:04.792] <TB1> INFO: Expecting 2560 events.
[15:41:05.682] <TB1> INFO: 2560 events read in total (298ms).
[15:41:05.682] <TB1> INFO: Test took 1196ms.
[15:41:05.686] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:41:05.991] <TB1> INFO: Expecting 2560 events.
[15:41:06.885] <TB1> INFO: 2560 events read in total (303ms).
[15:41:06.886] <TB1> INFO: Test took 1201ms.
[15:41:06.890] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:41:07.194] <TB1> INFO: Expecting 2560 events.
[15:41:08.086] <TB1> INFO: 2560 events read in total (300ms).
[15:41:08.086] <TB1> INFO: Test took 1197ms.
[15:41:08.565] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 656 seconds
[15:41:08.565] <TB1> INFO: PH scale (per ROC): 61 43 60 50 51 51 62 53 42 64 54 57 51 48 60 62
[15:41:08.565] <TB1> INFO: PH offset (per ROC): 125 110 124 107 133 94 130 116 107 128 137 130 114 111 116 110
[15:41:08.572] <TB1> INFO: Decoding statistics:
[15:41:08.573] <TB1> INFO: General information:
[15:41:08.573] <TB1> INFO: 16bit words read: 127888
[15:41:08.573] <TB1> INFO: valid events total: 20480
[15:41:08.573] <TB1> INFO: empty events: 17976
[15:41:08.573] <TB1> INFO: valid events with pixels: 2504
[15:41:08.573] <TB1> INFO: valid pixel hits: 2504
[15:41:08.573] <TB1> INFO: Event errors: 0
[15:41:08.573] <TB1> INFO: start marker: 0
[15:41:08.573] <TB1> INFO: stop marker: 0
[15:41:08.573] <TB1> INFO: overflow: 0
[15:41:08.573] <TB1> INFO: invalid 5bit words: 0
[15:41:08.573] <TB1> INFO: invalid XOR eye diagram: 0
[15:41:08.573] <TB1> INFO: frame (failed synchr.): 0
[15:41:08.573] <TB1> INFO: idle data (no TBM trl): 0
[15:41:08.573] <TB1> INFO: no data (only TBM hdr): 0
[15:41:08.573] <TB1> INFO: TBM errors: 0
[15:41:08.573] <TB1> INFO: flawed TBM headers: 0
[15:41:08.573] <TB1> INFO: flawed TBM trailers: 0
[15:41:08.573] <TB1> INFO: event ID mismatches: 0
[15:41:08.573] <TB1> INFO: ROC errors: 0
[15:41:08.573] <TB1> INFO: missing ROC header(s): 0
[15:41:08.573] <TB1> INFO: misplaced readback start: 0
[15:41:08.573] <TB1> INFO: Pixel decoding errors: 0
[15:41:08.573] <TB1> INFO: pixel data incomplete: 0
[15:41:08.573] <TB1> INFO: pixel address: 0
[15:41:08.573] <TB1> INFO: pulse height fill bit: 0
[15:41:08.573] <TB1> INFO: buffer corruption: 0
[15:41:08.787] <TB1> INFO: ######################################################################
[15:41:08.787] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:41:08.787] <TB1> INFO: ######################################################################
[15:41:08.801] <TB1> INFO: scanning low vcal = 10
[15:41:09.038] <TB1> INFO: Expecting 41600 events.
[15:41:12.651] <TB1> INFO: 41600 events read in total (3022ms).
[15:41:12.651] <TB1> INFO: Test took 3849ms.
[15:41:12.653] <TB1> INFO: scanning low vcal = 20
[15:41:12.948] <TB1> INFO: Expecting 41600 events.
[15:41:16.557] <TB1> INFO: 41600 events read in total (3017ms).
[15:41:16.558] <TB1> INFO: Test took 3905ms.
[15:41:16.560] <TB1> INFO: scanning low vcal = 30
[15:41:16.853] <TB1> INFO: Expecting 41600 events.
[15:41:20.511] <TB1> INFO: 41600 events read in total (3066ms).
[15:41:20.512] <TB1> INFO: Test took 3951ms.
[15:41:20.515] <TB1> INFO: scanning low vcal = 40
[15:41:20.792] <TB1> INFO: Expecting 41600 events.
[15:41:24.765] <TB1> INFO: 41600 events read in total (3382ms).
[15:41:24.766] <TB1> INFO: Test took 4251ms.
[15:41:24.770] <TB1> INFO: scanning low vcal = 50
[15:41:25.049] <TB1> INFO: Expecting 41600 events.
[15:41:29.067] <TB1> INFO: 41600 events read in total (3426ms).
[15:41:29.068] <TB1> INFO: Test took 4298ms.
[15:41:29.071] <TB1> INFO: scanning low vcal = 60
[15:41:29.359] <TB1> INFO: Expecting 41600 events.
[15:41:33.367] <TB1> INFO: 41600 events read in total (3416ms).
[15:41:33.368] <TB1> INFO: Test took 4297ms.
[15:41:33.371] <TB1> INFO: scanning low vcal = 70
[15:41:33.647] <TB1> INFO: Expecting 41600 events.
[15:41:37.662] <TB1> INFO: 41600 events read in total (3423ms).
[15:41:37.663] <TB1> INFO: Test took 4292ms.
[15:41:37.666] <TB1> INFO: scanning low vcal = 80
[15:41:37.943] <TB1> INFO: Expecting 41600 events.
[15:41:41.962] <TB1> INFO: 41600 events read in total (3427ms).
[15:41:41.963] <TB1> INFO: Test took 4297ms.
[15:41:41.966] <TB1> INFO: scanning low vcal = 90
[15:41:42.243] <TB1> INFO: Expecting 41600 events.
[15:41:46.254] <TB1> INFO: 41600 events read in total (3419ms).
[15:41:46.255] <TB1> INFO: Test took 4289ms.
[15:41:46.259] <TB1> INFO: scanning low vcal = 100
[15:41:46.535] <TB1> INFO: Expecting 41600 events.
[15:41:50.550] <TB1> INFO: 41600 events read in total (3423ms).
[15:41:50.551] <TB1> INFO: Test took 4292ms.
[15:41:50.554] <TB1> INFO: scanning low vcal = 110
[15:41:50.831] <TB1> INFO: Expecting 41600 events.
[15:41:54.868] <TB1> INFO: 41600 events read in total (3445ms).
[15:41:54.869] <TB1> INFO: Test took 4315ms.
[15:41:54.871] <TB1> INFO: scanning low vcal = 120
[15:41:55.149] <TB1> INFO: Expecting 41600 events.
[15:41:59.206] <TB1> INFO: 41600 events read in total (3465ms).
[15:41:59.207] <TB1> INFO: Test took 4335ms.
[15:41:59.210] <TB1> INFO: scanning low vcal = 130
[15:41:59.490] <TB1> INFO: Expecting 41600 events.
[15:42:03.475] <TB1> INFO: 41600 events read in total (3393ms).
[15:42:03.476] <TB1> INFO: Test took 4266ms.
[15:42:03.479] <TB1> INFO: scanning low vcal = 140
[15:42:03.756] <TB1> INFO: Expecting 41600 events.
[15:42:07.751] <TB1> INFO: 41600 events read in total (3403ms).
[15:42:07.752] <TB1> INFO: Test took 4273ms.
[15:42:07.755] <TB1> INFO: scanning low vcal = 150
[15:42:08.032] <TB1> INFO: Expecting 41600 events.
[15:42:12.053] <TB1> INFO: 41600 events read in total (3429ms).
[15:42:12.053] <TB1> INFO: Test took 4298ms.
[15:42:12.057] <TB1> INFO: scanning low vcal = 160
[15:42:12.334] <TB1> INFO: Expecting 41600 events.
[15:42:16.364] <TB1> INFO: 41600 events read in total (3438ms).
[15:42:16.365] <TB1> INFO: Test took 4308ms.
[15:42:16.368] <TB1> INFO: scanning low vcal = 170
[15:42:16.644] <TB1> INFO: Expecting 41600 events.
[15:42:20.620] <TB1> INFO: 41600 events read in total (3384ms).
[15:42:20.621] <TB1> INFO: Test took 4253ms.
[15:42:20.626] <TB1> INFO: scanning low vcal = 180
[15:42:20.901] <TB1> INFO: Expecting 41600 events.
[15:42:24.912] <TB1> INFO: 41600 events read in total (3419ms).
[15:42:24.913] <TB1> INFO: Test took 4287ms.
[15:42:24.918] <TB1> INFO: scanning low vcal = 190
[15:42:25.193] <TB1> INFO: Expecting 41600 events.
[15:42:29.184] <TB1> INFO: 41600 events read in total (3399ms).
[15:42:29.185] <TB1> INFO: Test took 4267ms.
[15:42:29.188] <TB1> INFO: scanning low vcal = 200
[15:42:29.465] <TB1> INFO: Expecting 41600 events.
[15:42:33.513] <TB1> INFO: 41600 events read in total (3456ms).
[15:42:33.513] <TB1> INFO: Test took 4325ms.
[15:42:33.516] <TB1> INFO: scanning low vcal = 210
[15:42:33.794] <TB1> INFO: Expecting 41600 events.
[15:42:37.842] <TB1> INFO: 41600 events read in total (3456ms).
[15:42:37.842] <TB1> INFO: Test took 4325ms.
[15:42:37.845] <TB1> INFO: scanning low vcal = 220
[15:42:38.123] <TB1> INFO: Expecting 41600 events.
[15:42:42.139] <TB1> INFO: 41600 events read in total (3424ms).
[15:42:42.140] <TB1> INFO: Test took 4295ms.
[15:42:42.142] <TB1> INFO: scanning low vcal = 230
[15:42:42.420] <TB1> INFO: Expecting 41600 events.
[15:42:46.480] <TB1> INFO: 41600 events read in total (3467ms).
[15:42:46.481] <TB1> INFO: Test took 4338ms.
[15:42:46.484] <TB1> INFO: scanning low vcal = 240
[15:42:46.760] <TB1> INFO: Expecting 41600 events.
[15:42:50.761] <TB1> INFO: 41600 events read in total (3409ms).
[15:42:50.762] <TB1> INFO: Test took 4278ms.
[15:42:50.765] <TB1> INFO: scanning low vcal = 250
[15:42:51.042] <TB1> INFO: Expecting 41600 events.
[15:42:55.056] <TB1> INFO: 41600 events read in total (3422ms).
[15:42:55.057] <TB1> INFO: Test took 4292ms.
[15:42:55.061] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[15:42:55.344] <TB1> INFO: Expecting 41600 events.
[15:42:59.398] <TB1> INFO: 41600 events read in total (3462ms).
[15:42:59.398] <TB1> INFO: Test took 4337ms.
[15:42:59.401] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[15:42:59.679] <TB1> INFO: Expecting 41600 events.
[15:43:03.617] <TB1> INFO: 41600 events read in total (3346ms).
[15:43:03.617] <TB1> INFO: Test took 4216ms.
[15:43:03.621] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[15:43:03.951] <TB1> INFO: Expecting 41600 events.
[15:43:07.897] <TB1> INFO: 41600 events read in total (3354ms).
[15:43:07.898] <TB1> INFO: Test took 4277ms.
[15:43:07.902] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[15:43:08.178] <TB1> INFO: Expecting 41600 events.
[15:43:12.141] <TB1> INFO: 41600 events read in total (3371ms).
[15:43:12.142] <TB1> INFO: Test took 4240ms.
[15:43:12.146] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:43:12.422] <TB1> INFO: Expecting 41600 events.
[15:43:16.387] <TB1> INFO: 41600 events read in total (3374ms).
[15:43:16.388] <TB1> INFO: Test took 4242ms.
[15:43:16.792] <TB1> INFO: PixTestGainPedestal::measure() done
[15:43:54.136] <TB1> INFO: PixTestGainPedestal::fit() done
[15:43:54.136] <TB1> INFO: non-linearity mean: 0.981 0.919 0.981 0.969 0.982 0.940 0.983 0.971 0.954 0.979 0.980 0.980 0.923 0.949 0.981 0.984
[15:43:54.136] <TB1> INFO: non-linearity RMS: 0.004 0.111 0.003 0.009 0.004 0.065 0.003 0.029 0.169 0.004 0.006 0.003 0.095 0.042 0.004 0.003
[15:43:54.137] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[15:43:54.150] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[15:43:54.164] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[15:43:54.177] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[15:43:54.191] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[15:43:54.204] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[15:43:54.218] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[15:43:54.232] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[15:43:54.245] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[15:43:54.259] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[15:43:54.272] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[15:43:54.286] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[15:43:54.299] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[15:43:54.313] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[15:43:54.326] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[15:43:54.340] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[15:43:54.353] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 165 seconds
[15:43:54.353] <TB1> INFO: Decoding statistics:
[15:43:54.353] <TB1> INFO: General information:
[15:43:54.353] <TB1> INFO: 16bit words read: 3327948
[15:43:54.353] <TB1> INFO: valid events total: 332800
[15:43:54.353] <TB1> INFO: empty events: 0
[15:43:54.353] <TB1> INFO: valid events with pixels: 332800
[15:43:54.353] <TB1> INFO: valid pixel hits: 665574
[15:43:54.353] <TB1> INFO: Event errors: 0
[15:43:54.353] <TB1> INFO: start marker: 0
[15:43:54.353] <TB1> INFO: stop marker: 0
[15:43:54.353] <TB1> INFO: overflow: 0
[15:43:54.353] <TB1> INFO: invalid 5bit words: 0
[15:43:54.353] <TB1> INFO: invalid XOR eye diagram: 0
[15:43:54.353] <TB1> INFO: frame (failed synchr.): 0
[15:43:54.353] <TB1> INFO: idle data (no TBM trl): 0
[15:43:54.353] <TB1> INFO: no data (only TBM hdr): 0
[15:43:54.353] <TB1> INFO: TBM errors: 0
[15:43:54.353] <TB1> INFO: flawed TBM headers: 0
[15:43:54.353] <TB1> INFO: flawed TBM trailers: 0
[15:43:54.353] <TB1> INFO: event ID mismatches: 0
[15:43:54.353] <TB1> INFO: ROC errors: 0
[15:43:54.353] <TB1> INFO: missing ROC header(s): 0
[15:43:54.353] <TB1> INFO: misplaced readback start: 0
[15:43:54.353] <TB1> INFO: Pixel decoding errors: 0
[15:43:54.353] <TB1> INFO: pixel data incomplete: 0
[15:43:54.353] <TB1> INFO: pixel address: 0
[15:43:54.353] <TB1> INFO: pulse height fill bit: 0
[15:43:54.353] <TB1> INFO: buffer corruption: 0
[15:43:54.369] <TB1> INFO: Decoding statistics:
[15:43:54.369] <TB1> INFO: General information:
[15:43:54.369] <TB1> INFO: 16bit words read: 3457372
[15:43:54.369] <TB1> INFO: valid events total: 353536
[15:43:54.369] <TB1> INFO: empty events: 18232
[15:43:54.369] <TB1> INFO: valid events with pixels: 335304
[15:43:54.369] <TB1> INFO: valid pixel hits: 668078
[15:43:54.369] <TB1> INFO: Event errors: 0
[15:43:54.369] <TB1> INFO: start marker: 0
[15:43:54.369] <TB1> INFO: stop marker: 0
[15:43:54.369] <TB1> INFO: overflow: 0
[15:43:54.369] <TB1> INFO: invalid 5bit words: 0
[15:43:54.369] <TB1> INFO: invalid XOR eye diagram: 0
[15:43:54.369] <TB1> INFO: frame (failed synchr.): 0
[15:43:54.369] <TB1> INFO: idle data (no TBM trl): 0
[15:43:54.369] <TB1> INFO: no data (only TBM hdr): 0
[15:43:54.369] <TB1> INFO: TBM errors: 0
[15:43:54.369] <TB1> INFO: flawed TBM headers: 0
[15:43:54.369] <TB1> INFO: flawed TBM trailers: 0
[15:43:54.369] <TB1> INFO: event ID mismatches: 0
[15:43:54.369] <TB1> INFO: ROC errors: 0
[15:43:54.369] <TB1> INFO: missing ROC header(s): 0
[15:43:54.369] <TB1> INFO: misplaced readback start: 0
[15:43:54.369] <TB1> INFO: Pixel decoding errors: 0
[15:43:54.369] <TB1> INFO: pixel data incomplete: 0
[15:43:54.369] <TB1> INFO: pixel address: 0
[15:43:54.369] <TB1> INFO: pulse height fill bit: 0
[15:43:54.369] <TB1> INFO: buffer corruption: 0
[15:43:54.369] <TB1> INFO: enter test to run
[15:43:54.369] <TB1> INFO: test: exit no parameter change
[15:43:54.527] <TB1> QUIET: Connection to board 154 closed.
[15:43:54.528] <TB1> INFO: pXar: this is the end, my friend