[15:55:38.534] <TB1> INFO: *** Welcome to pxar ***
[15:55:38.534] <TB1> INFO: *** Today: 2016/11/07
[15:55:38.541] <TB1> INFO: *** Version: c8ba-dirty
[15:55:38.541] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C15.dat
[15:55:38.542] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[15:55:38.542] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//defaultMaskFile.dat
[15:55:38.542] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters_C15.dat
[15:55:38.604] <TB1> INFO: clk: 4
[15:55:38.604] <TB1> INFO: ctr: 4
[15:55:38.604] <TB1> INFO: sda: 19
[15:55:38.604] <TB1> INFO: tin: 9
[15:55:38.604] <TB1> INFO: level: 15
[15:55:38.604] <TB1> INFO: triggerdelay: 0
[15:55:38.604] <TB1> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[15:55:38.604] <TB1> INFO: Log level: INFO
[15:55:38.612] <TB1> INFO: Found DTB DTB_WXC03A
[15:55:38.624] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[15:55:38.626] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
------------------------------------------------------
[15:55:38.627] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[15:55:40.140] <TB1> INFO: DUT info:
[15:55:40.140] <TB1> INFO: The DUT currently contains the following objects:
[15:55:40.140] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[15:55:40.140] <TB1> INFO: TBM Core alpha (0): 7 registers set
[15:55:40.140] <TB1> INFO: TBM Core beta (1): 7 registers set
[15:55:40.140] <TB1> INFO: TBM Core alpha (2): 7 registers set
[15:55:40.140] <TB1> INFO: TBM Core beta (3): 7 registers set
[15:55:40.140] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[15:55:40.140] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.140] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.140] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.141] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.141] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.141] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.141] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.141] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.141] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.141] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.141] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.141] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.141] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.141] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.141] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.141] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:40.542] <TB1> INFO: enter 'restricted' command line mode
[15:55:40.542] <TB1> INFO: enter test to run
[15:55:40.542] <TB1> INFO: test: pretest no parameter change
[15:55:40.542] <TB1> INFO: running: pretest
[15:55:40.548] <TB1> INFO: ######################################################################
[15:55:40.549] <TB1> INFO: PixTestPretest::doTest()
[15:55:40.549] <TB1> INFO: ######################################################################
[15:55:40.550] <TB1> INFO: ----------------------------------------------------------------------
[15:55:40.550] <TB1> INFO: PixTestPretest::programROC()
[15:55:40.550] <TB1> INFO: ----------------------------------------------------------------------
[15:55:58.563] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[15:55:58.563] <TB1> INFO: IA differences per ROC: 20.1 17.7 20.1 19.3 20.9 16.9 17.7 19.3 17.7 19.3 18.5 19.3 20.1 19.3 21.7 19.3
[15:55:58.625] <TB1> INFO: ----------------------------------------------------------------------
[15:55:58.625] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[15:55:58.625] <TB1> INFO: ----------------------------------------------------------------------
[15:56:19.917] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 381.9 mA = 23.8688 mA/ROC
[15:56:19.917] <TB1> INFO: i(loss) [mA/ROC]: 19.3 20.1 19.3 18.5 19.3 18.5 17.7 19.3 18.5 18.5 19.3 20.1 18.5 18.5 17.7 19.3
[15:56:19.954] <TB1> INFO: ----------------------------------------------------------------------
[15:56:19.954] <TB1> INFO: PixTestPretest::findTiming()
[15:56:19.954] <TB1> INFO: ----------------------------------------------------------------------
[15:56:19.954] <TB1> INFO: PixTestCmd::init()

[15:56:52.681] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[15:56:52.681] <TB1> INFO: (success/tries = 100/100), width = 4
[15:56:54.196] <TB1> INFO: ----------------------------------------------------------------------
[15:56:54.196] <TB1> INFO: PixTestPretest::findWorkingPixel()
[15:56:54.196] <TB1> INFO: ----------------------------------------------------------------------
[15:56:54.291] <TB1> INFO: Expecting 231680 events.
[15:57:04.415] <TB1> INFO: 231680 events read in total (9532ms).
[15:57:04.423] <TB1> INFO: Test took 10222ms.
[15:57:04.672] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[15:57:04.709] <TB1> INFO: ----------------------------------------------------------------------
[15:57:04.709] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[15:57:04.709] <TB1> INFO: ----------------------------------------------------------------------
[15:57:04.803] <TB1> INFO: Expecting 231680 events.
[15:57:14.674] <TB1> INFO: 231680 events read in total (9279ms).
[15:57:14.687] <TB1> INFO: Test took 9974ms.
[15:57:14.952] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[15:57:14.952] <TB1> INFO: CalDel: 100 95 102 94 88 83 88 108 86 80 93 85 84 92 87 92
[15:57:14.952] <TB1> INFO: VthrComp: 51 52 51 51 51 51 51 52 51 51 51 51 51 54 51 51
[15:57:14.956] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C0.dat
[15:57:14.956] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C1.dat
[15:57:14.956] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C2.dat
[15:57:14.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C3.dat
[15:57:14.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C4.dat
[15:57:14.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C5.dat
[15:57:14.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C6.dat
[15:57:14.958] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C7.dat
[15:57:14.958] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C8.dat
[15:57:14.958] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C9.dat
[15:57:14.958] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C10.dat
[15:57:14.959] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C11.dat
[15:57:14.959] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C12.dat
[15:57:14.959] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C13.dat
[15:57:14.959] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C14.dat
[15:57:14.959] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C15.dat
[15:57:14.959] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[15:57:14.960] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[15:57:14.960] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[15:57:14.960] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[15:57:14.960] <TB1> INFO: PixTestPretest::doTest() done, duration: 94 seconds
[15:57:15.015] <TB1> INFO: enter test to run
[15:57:15.015] <TB1> INFO: test: fulltest no parameter change
[15:57:15.015] <TB1> INFO: running: fulltest
[15:57:15.015] <TB1> INFO: ######################################################################
[15:57:15.015] <TB1> INFO: PixTestFullTest::doTest()
[15:57:15.015] <TB1> INFO: ######################################################################
[15:57:15.016] <TB1> INFO: ######################################################################
[15:57:15.017] <TB1> INFO: PixTestAlive::doTest()
[15:57:15.017] <TB1> INFO: ######################################################################
[15:57:15.018] <TB1> INFO: ----------------------------------------------------------------------
[15:57:15.018] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:57:15.018] <TB1> INFO: ----------------------------------------------------------------------
[15:57:15.300] <TB1> INFO: Expecting 41600 events.
[15:57:18.877] <TB1> INFO: 41600 events read in total (2985ms).
[15:57:18.878] <TB1> INFO: Test took 3859ms.
[15:57:19.108] <TB1> INFO: PixTestAlive::aliveTest() done
[15:57:19.108] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:57:19.110] <TB1> INFO: ----------------------------------------------------------------------
[15:57:19.110] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:57:19.110] <TB1> INFO: ----------------------------------------------------------------------
[15:57:19.353] <TB1> INFO: Expecting 41600 events.
[15:57:22.377] <TB1> INFO: 41600 events read in total (2432ms).
[15:57:22.377] <TB1> INFO: Test took 3265ms.
[15:57:22.378] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[15:57:22.616] <TB1> INFO: PixTestAlive::maskTest() done
[15:57:22.616] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:57:22.617] <TB1> INFO: ----------------------------------------------------------------------
[15:57:22.618] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:57:22.618] <TB1> INFO: ----------------------------------------------------------------------
[15:57:22.859] <TB1> INFO: Expecting 41600 events.
[15:57:26.388] <TB1> INFO: 41600 events read in total (2937ms).
[15:57:26.389] <TB1> INFO: Test took 3769ms.
[15:57:26.624] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[15:57:26.624] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:57:26.624] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[15:57:26.624] <TB1> INFO: Decoding statistics:
[15:57:26.624] <TB1> INFO: General information:
[15:57:26.624] <TB1> INFO: 16bit words read: 0
[15:57:26.624] <TB1> INFO: valid events total: 0
[15:57:26.624] <TB1> INFO: empty events: 0
[15:57:26.624] <TB1> INFO: valid events with pixels: 0
[15:57:26.624] <TB1> INFO: valid pixel hits: 0
[15:57:26.625] <TB1> INFO: Event errors: 0
[15:57:26.625] <TB1> INFO: start marker: 0
[15:57:26.625] <TB1> INFO: stop marker: 0
[15:57:26.625] <TB1> INFO: overflow: 0
[15:57:26.625] <TB1> INFO: invalid 5bit words: 0
[15:57:26.625] <TB1> INFO: invalid XOR eye diagram: 0
[15:57:26.625] <TB1> INFO: frame (failed synchr.): 0
[15:57:26.625] <TB1> INFO: idle data (no TBM trl): 0
[15:57:26.625] <TB1> INFO: no data (only TBM hdr): 0
[15:57:26.625] <TB1> INFO: TBM errors: 0
[15:57:26.625] <TB1> INFO: flawed TBM headers: 0
[15:57:26.625] <TB1> INFO: flawed TBM trailers: 0
[15:57:26.625] <TB1> INFO: event ID mismatches: 0
[15:57:26.625] <TB1> INFO: ROC errors: 0
[15:57:26.625] <TB1> INFO: missing ROC header(s): 0
[15:57:26.625] <TB1> INFO: misplaced readback start: 0
[15:57:26.625] <TB1> INFO: Pixel decoding errors: 0
[15:57:26.625] <TB1> INFO: pixel data incomplete: 0
[15:57:26.625] <TB1> INFO: pixel address: 0
[15:57:26.625] <TB1> INFO: pulse height fill bit: 0
[15:57:26.625] <TB1> INFO: buffer corruption: 0
[15:57:26.633] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[15:57:26.634] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[15:57:26.634] <TB1> INFO: ######################################################################
[15:57:26.634] <TB1> INFO: PixTestReadback::doTest()
[15:57:26.634] <TB1> INFO: ######################################################################
[15:57:26.634] <TB1> INFO: ----------------------------------------------------------------------
[15:57:26.634] <TB1> INFO: PixTestReadback::CalibrateVd()
[15:57:26.634] <TB1> INFO: ----------------------------------------------------------------------
[15:57:36.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat
[15:57:36.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C1.dat
[15:57:36.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C2.dat
[15:57:36.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C3.dat
[15:57:36.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C4.dat
[15:57:36.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C5.dat
[15:57:36.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C6.dat
[15:57:36.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C7.dat
[15:57:36.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C8.dat
[15:57:36.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C9.dat
[15:57:36.613] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C10.dat
[15:57:36.613] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C11.dat
[15:57:36.613] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C12.dat
[15:57:36.613] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C13.dat
[15:57:36.613] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C14.dat
[15:57:36.613] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[15:57:36.644] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[15:57:36.644] <TB1> INFO: ----------------------------------------------------------------------
[15:57:36.644] <TB1> INFO: PixTestReadback::CalibrateVa()
[15:57:36.644] <TB1> INFO: ----------------------------------------------------------------------
[15:57:46.581] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat
[15:57:46.581] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C1.dat
[15:57:46.581] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C2.dat
[15:57:46.581] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C3.dat
[15:57:46.581] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C4.dat
[15:57:46.581] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C5.dat
[15:57:46.581] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C6.dat
[15:57:46.581] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C7.dat
[15:57:46.581] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C8.dat
[15:57:46.581] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C9.dat
[15:57:46.582] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C10.dat
[15:57:46.582] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C11.dat
[15:57:46.582] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C12.dat
[15:57:46.582] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C13.dat
[15:57:46.582] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C14.dat
[15:57:46.582] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[15:57:46.612] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[15:57:46.612] <TB1> INFO: ----------------------------------------------------------------------
[15:57:46.612] <TB1> INFO: PixTestReadback::readbackVbg()
[15:57:46.612] <TB1> INFO: ----------------------------------------------------------------------
[15:57:54.286] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[15:57:54.287] <TB1> INFO: ----------------------------------------------------------------------
[15:57:54.287] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[15:57:54.287] <TB1> INFO: ----------------------------------------------------------------------
[15:57:54.287] <TB1> INFO: Vbg will be calibrated using Vd calibration
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 158.3calibrated Vbg = 1.19494 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 155.1calibrated Vbg = 1.20025 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 158.9calibrated Vbg = 1.1962 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 152.2calibrated Vbg = 1.19408 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 152.1calibrated Vbg = 1.19817 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 158calibrated Vbg = 1.19944 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 153.5calibrated Vbg = 1.19936 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 159calibrated Vbg = 1.20265 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 155.8calibrated Vbg = 1.19854 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154.2calibrated Vbg = 1.19012 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 147.3calibrated Vbg = 1.19551 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 157.1calibrated Vbg = 1.18557 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 155.8calibrated Vbg = 1.19268 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 159.9calibrated Vbg = 1.19366 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 159.9calibrated Vbg = 1.19716 :::*/*/*/*/
[15:57:54.287] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 161calibrated Vbg = 1.19753 :::*/*/*/*/
[15:57:54.290] <TB1> INFO: ----------------------------------------------------------------------
[15:57:54.290] <TB1> INFO: PixTestReadback::CalibrateIa()
[15:57:54.290] <TB1> INFO: ----------------------------------------------------------------------
[16:00:35.087] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat
[16:00:35.087] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C1.dat
[16:00:35.087] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C2.dat
[16:00:35.087] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C3.dat
[16:00:35.087] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C4.dat
[16:00:35.087] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C5.dat
[16:00:35.087] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C6.dat
[16:00:35.087] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C7.dat
[16:00:35.088] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C8.dat
[16:00:35.088] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C9.dat
[16:00:35.088] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C10.dat
[16:00:35.088] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C11.dat
[16:00:35.088] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C12.dat
[16:00:35.088] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C13.dat
[16:00:35.088] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C14.dat
[16:00:35.088] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[16:00:35.117] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[16:00:35.119] <TB1> INFO: PixTestReadback::doTest() done
[16:00:35.120] <TB1> INFO: Decoding statistics:
[16:00:35.120] <TB1> INFO: General information:
[16:00:35.120] <TB1> INFO: 16bit words read: 1536
[16:00:35.120] <TB1> INFO: valid events total: 256
[16:00:35.120] <TB1> INFO: empty events: 256
[16:00:35.120] <TB1> INFO: valid events with pixels: 0
[16:00:35.120] <TB1> INFO: valid pixel hits: 0
[16:00:35.120] <TB1> INFO: Event errors: 0
[16:00:35.120] <TB1> INFO: start marker: 0
[16:00:35.120] <TB1> INFO: stop marker: 0
[16:00:35.120] <TB1> INFO: overflow: 0
[16:00:35.120] <TB1> INFO: invalid 5bit words: 0
[16:00:35.120] <TB1> INFO: invalid XOR eye diagram: 0
[16:00:35.120] <TB1> INFO: frame (failed synchr.): 0
[16:00:35.120] <TB1> INFO: idle data (no TBM trl): 0
[16:00:35.120] <TB1> INFO: no data (only TBM hdr): 0
[16:00:35.120] <TB1> INFO: TBM errors: 0
[16:00:35.120] <TB1> INFO: flawed TBM headers: 0
[16:00:35.120] <TB1> INFO: flawed TBM trailers: 0
[16:00:35.120] <TB1> INFO: event ID mismatches: 0
[16:00:35.120] <TB1> INFO: ROC errors: 0
[16:00:35.120] <TB1> INFO: missing ROC header(s): 0
[16:00:35.120] <TB1> INFO: misplaced readback start: 0
[16:00:35.120] <TB1> INFO: Pixel decoding errors: 0
[16:00:35.120] <TB1> INFO: pixel data incomplete: 0
[16:00:35.120] <TB1> INFO: pixel address: 0
[16:00:35.120] <TB1> INFO: pulse height fill bit: 0
[16:00:35.120] <TB1> INFO: buffer corruption: 0
[16:00:35.172] <TB1> INFO: ######################################################################
[16:00:35.172] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[16:00:35.172] <TB1> INFO: ######################################################################
[16:00:35.176] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[16:00:35.314] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[16:00:35.314] <TB1> INFO: run 1 of 1
[16:00:35.560] <TB1> INFO: Expecting 3120000 events.
[16:01:06.734] <TB1> INFO: 667155 events read in total (30582ms).











[16:01:37.028] <TB1> INFO: 1332415 events read in total (60876ms).





















[16:02:07.212] <TB1> INFO: 1994770 events read in total (91060ms).











[16:02:37.545] <TB1> INFO: 2658975 events read in total (121393ms).





















[16:02:59.163] <TB1> INFO: 3120000 events read in total (143011ms).
[16:02:59.235] <TB1> INFO: Test took 143921ms.
[16:03:22.566] <TB1> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 167 seconds
[16:03:22.566] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1
[16:03:22.566] <TB1> INFO: separation cut (per ROC): 106 105 109 104 107 106 102 104 89 105 101 112 104 104 99 105
[16:03:22.567] <TB1> INFO: Decoding statistics:
[16:03:22.567] <TB1> INFO: General information:
[16:03:22.567] <TB1> INFO: 16bit words read: 0
[16:03:22.567] <TB1> INFO: valid events total: 0
[16:03:22.567] <TB1> INFO: empty events: 0
[16:03:22.567] <TB1> INFO: valid events with pixels: 0
[16:03:22.567] <TB1> INFO: valid pixel hits: 0
[16:03:22.567] <TB1> INFO: Event errors: 0
[16:03:22.567] <TB1> INFO: start marker: 0
[16:03:22.567] <TB1> INFO: stop marker: 0
[16:03:22.567] <TB1> INFO: overflow: 0
[16:03:22.567] <TB1> INFO: invalid 5bit words: 0
[16:03:22.567] <TB1> INFO: invalid XOR eye diagram: 0
[16:03:22.567] <TB1> INFO: frame (failed synchr.): 0
[16:03:22.567] <TB1> INFO: idle data (no TBM trl): 0
[16:03:22.567] <TB1> INFO: no data (only TBM hdr): 0
[16:03:22.567] <TB1> INFO: TBM errors: 0
[16:03:22.567] <TB1> INFO: flawed TBM headers: 0
[16:03:22.567] <TB1> INFO: flawed TBM trailers: 0
[16:03:22.567] <TB1> INFO: event ID mismatches: 0
[16:03:22.567] <TB1> INFO: ROC errors: 0
[16:03:22.567] <TB1> INFO: missing ROC header(s): 0
[16:03:22.567] <TB1> INFO: misplaced readback start: 0
[16:03:22.567] <TB1> INFO: Pixel decoding errors: 0
[16:03:22.567] <TB1> INFO: pixel data incomplete: 0
[16:03:22.567] <TB1> INFO: pixel address: 0
[16:03:22.567] <TB1> INFO: pulse height fill bit: 0
[16:03:22.567] <TB1> INFO: buffer corruption: 0
[16:03:22.606] <TB1> INFO: ######################################################################
[16:03:22.606] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:03:22.606] <TB1> INFO: ######################################################################
[16:03:22.606] <TB1> INFO: ----------------------------------------------------------------------
[16:03:22.606] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:03:22.606] <TB1> INFO: ----------------------------------------------------------------------
[16:03:22.606] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[16:03:22.620] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[16:03:22.620] <TB1> INFO: run 1 of 1
[16:03:22.864] <TB1> INFO: Expecting 36608000 events.
[16:03:46.419] <TB1> INFO: 685350 events read in total (22963ms).
[16:04:09.415] <TB1> INFO: 1356500 events read in total (45959ms).
[16:04:32.422] <TB1> INFO: 2028250 events read in total (68966ms).
[16:04:55.155] <TB1> INFO: 2695100 events read in total (91699ms).
[16:05:18.081] <TB1> INFO: 3364700 events read in total (114625ms).
[16:05:41.252] <TB1> INFO: 4034050 events read in total (137796ms).
[16:06:04.208] <TB1> INFO: 4704400 events read in total (160752ms).
[16:06:27.148] <TB1> INFO: 5373600 events read in total (183692ms).
[16:06:50.481] <TB1> INFO: 6044550 events read in total (207025ms).
[16:07:13.487] <TB1> INFO: 6714350 events read in total (230031ms).
[16:07:36.484] <TB1> INFO: 7383850 events read in total (253028ms).
[16:07:59.513] <TB1> INFO: 8053450 events read in total (276057ms).
[16:08:22.742] <TB1> INFO: 8724050 events read in total (299286ms).
[16:08:45.718] <TB1> INFO: 9394700 events read in total (322262ms).
[16:09:08.348] <TB1> INFO: 10063300 events read in total (344892ms).
[16:09:31.345] <TB1> INFO: 10731550 events read in total (367889ms).
[16:09:54.450] <TB1> INFO: 11399050 events read in total (390994ms).
[16:10:17.314] <TB1> INFO: 12065350 events read in total (413858ms).
[16:10:40.320] <TB1> INFO: 12731000 events read in total (436864ms).
[16:11:03.175] <TB1> INFO: 13397900 events read in total (459719ms).
[16:11:26.181] <TB1> INFO: 14062700 events read in total (482725ms).
[16:11:49.240] <TB1> INFO: 14729600 events read in total (505784ms).
[16:12:12.275] <TB1> INFO: 15393800 events read in total (528819ms).
[16:12:35.209] <TB1> INFO: 16057250 events read in total (551753ms).
[16:12:57.972] <TB1> INFO: 16720400 events read in total (574516ms).
[16:13:21.035] <TB1> INFO: 17386050 events read in total (597579ms).
[16:13:43.682] <TB1> INFO: 18051350 events read in total (620226ms).
[16:14:06.724] <TB1> INFO: 18714400 events read in total (643268ms).
[16:14:29.505] <TB1> INFO: 19376200 events read in total (666049ms).
[16:14:52.376] <TB1> INFO: 20036750 events read in total (688920ms).
[16:15:15.141] <TB1> INFO: 20697900 events read in total (711685ms).
[16:15:37.818] <TB1> INFO: 21359550 events read in total (734362ms).
[16:16:00.618] <TB1> INFO: 22022850 events read in total (757162ms).
[16:16:23.065] <TB1> INFO: 22683800 events read in total (779609ms).
[16:16:45.651] <TB1> INFO: 23345350 events read in total (802195ms).
[16:17:08.384] <TB1> INFO: 24005450 events read in total (824928ms).
[16:17:30.995] <TB1> INFO: 24667400 events read in total (847539ms).
[16:17:53.797] <TB1> INFO: 25327550 events read in total (870341ms).
[16:18:16.476] <TB1> INFO: 25990800 events read in total (893020ms).
[16:18:39.633] <TB1> INFO: 26651500 events read in total (916177ms).
[16:19:02.331] <TB1> INFO: 27312950 events read in total (938875ms).
[16:19:25.044] <TB1> INFO: 27972600 events read in total (961588ms).
[16:19:47.754] <TB1> INFO: 28632850 events read in total (984298ms).
[16:20:10.612] <TB1> INFO: 29292150 events read in total (1007156ms).
[16:20:33.575] <TB1> INFO: 29951100 events read in total (1030119ms).
[16:20:56.211] <TB1> INFO: 30611000 events read in total (1052755ms).
[16:21:19.369] <TB1> INFO: 31269950 events read in total (1075913ms).
[16:21:42.294] <TB1> INFO: 31930150 events read in total (1098838ms).
[16:22:04.953] <TB1> INFO: 32590150 events read in total (1121497ms).
[16:22:27.784] <TB1> INFO: 33248850 events read in total (1144328ms).
[16:22:50.903] <TB1> INFO: 33909500 events read in total (1167447ms).
[16:23:13.736] <TB1> INFO: 34570750 events read in total (1190280ms).
[16:23:36.685] <TB1> INFO: 35231200 events read in total (1213229ms).
[16:23:59.967] <TB1> INFO: 35894100 events read in total (1236511ms).
[16:24:23.459] <TB1> INFO: 36567050 events read in total (1260003ms).
[16:24:25.345] <TB1> INFO: 36608000 events read in total (1261889ms).
[16:24:25.438] <TB1> INFO: Test took 1262818ms.
[16:24:25.872] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:27.488] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:29.459] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:31.387] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:32.995] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:34.447] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:35.932] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:37.731] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:40.111] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:41.973] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:43.430] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:45.261] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:47.219] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:49.140] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:51.209] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:53.011] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:24:54.705] <TB1> INFO: PixTestScurves::scurves() done
[16:24:54.705] <TB1> INFO: Vcal mean: 124.39 124.96 119.38 111.35 130.99 128.26 113.75 129.13 109.77 117.53 112.74 124.76 116.59 124.71 108.13 116.74
[16:24:54.705] <TB1> INFO: Vcal RMS: 6.21 5.93 5.40 4.80 6.35 5.52 5.12 6.38 4.79 5.73 4.72 5.85 5.33 6.52 5.05 4.99
[16:24:54.706] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1292 seconds
[16:24:54.706] <TB1> INFO: Decoding statistics:
[16:24:54.706] <TB1> INFO: General information:
[16:24:54.706] <TB1> INFO: 16bit words read: 0
[16:24:54.706] <TB1> INFO: valid events total: 0
[16:24:54.706] <TB1> INFO: empty events: 0
[16:24:54.706] <TB1> INFO: valid events with pixels: 0
[16:24:54.706] <TB1> INFO: valid pixel hits: 0
[16:24:54.706] <TB1> INFO: Event errors: 0
[16:24:54.706] <TB1> INFO: start marker: 0
[16:24:54.706] <TB1> INFO: stop marker: 0
[16:24:54.706] <TB1> INFO: overflow: 0
[16:24:54.706] <TB1> INFO: invalid 5bit words: 0
[16:24:54.706] <TB1> INFO: invalid XOR eye diagram: 0
[16:24:54.706] <TB1> INFO: frame (failed synchr.): 0
[16:24:54.706] <TB1> INFO: idle data (no TBM trl): 0
[16:24:54.706] <TB1> INFO: no data (only TBM hdr): 0
[16:24:54.706] <TB1> INFO: TBM errors: 0
[16:24:54.706] <TB1> INFO: flawed TBM headers: 0
[16:24:54.706] <TB1> INFO: flawed TBM trailers: 0
[16:24:54.706] <TB1> INFO: event ID mismatches: 0
[16:24:54.706] <TB1> INFO: ROC errors: 0
[16:24:54.706] <TB1> INFO: missing ROC header(s): 0
[16:24:54.706] <TB1> INFO: misplaced readback start: 0
[16:24:54.706] <TB1> INFO: Pixel decoding errors: 0
[16:24:54.706] <TB1> INFO: pixel data incomplete: 0
[16:24:54.706] <TB1> INFO: pixel address: 0
[16:24:54.706] <TB1> INFO: pulse height fill bit: 0
[16:24:54.706] <TB1> INFO: buffer corruption: 0
[16:24:54.773] <TB1> INFO: ######################################################################
[16:24:54.773] <TB1> INFO: PixTestTrim::doTest()
[16:24:54.773] <TB1> INFO: ######################################################################
[16:24:54.774] <TB1> INFO: ----------------------------------------------------------------------
[16:24:54.774] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[16:24:54.774] <TB1> INFO: ----------------------------------------------------------------------
[16:24:54.843] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[16:24:54.843] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:24:54.857] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:24:54.858] <TB1> INFO: run 1 of 1
[16:24:55.188] <TB1> INFO: Expecting 5025280 events.
[16:25:25.989] <TB1> INFO: 825720 events read in total (30204ms).
[16:25:56.009] <TB1> INFO: 1649120 events read in total (60225ms).
[16:26:26.472] <TB1> INFO: 2469368 events read in total (90687ms).
[16:26:56.724] <TB1> INFO: 3284560 events read in total (120939ms).
[16:27:26.573] <TB1> INFO: 4098536 events read in total (150788ms).
[16:27:57.271] <TB1> INFO: 4910840 events read in total (181486ms).
[16:28:01.678] <TB1> INFO: 5025280 events read in total (185893ms).
[16:28:01.754] <TB1> INFO: Test took 186896ms.
[16:28:18.546] <TB1> INFO: ROC 0 VthrComp = 127
[16:28:18.546] <TB1> INFO: ROC 1 VthrComp = 127
[16:28:18.546] <TB1> INFO: ROC 2 VthrComp = 123
[16:28:18.546] <TB1> INFO: ROC 3 VthrComp = 114
[16:28:18.547] <TB1> INFO: ROC 4 VthrComp = 132
[16:28:18.547] <TB1> INFO: ROC 5 VthrComp = 129
[16:28:18.547] <TB1> INFO: ROC 6 VthrComp = 108
[16:28:18.547] <TB1> INFO: ROC 7 VthrComp = 127
[16:28:18.547] <TB1> INFO: ROC 8 VthrComp = 108
[16:28:18.547] <TB1> INFO: ROC 9 VthrComp = 126
[16:28:18.547] <TB1> INFO: ROC 10 VthrComp = 115
[16:28:18.547] <TB1> INFO: ROC 11 VthrComp = 132
[16:28:18.547] <TB1> INFO: ROC 12 VthrComp = 123
[16:28:18.547] <TB1> INFO: ROC 13 VthrComp = 128
[16:28:18.547] <TB1> INFO: ROC 14 VthrComp = 108
[16:28:18.548] <TB1> INFO: ROC 15 VthrComp = 127
[16:28:18.841] <TB1> INFO: Expecting 41600 events.
[16:28:22.313] <TB1> INFO: 41600 events read in total (2880ms).
[16:28:22.313] <TB1> INFO: Test took 3764ms.
[16:28:22.323] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[16:28:22.323] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:28:22.334] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:28:22.334] <TB1> INFO: run 1 of 1
[16:28:22.612] <TB1> INFO: Expecting 5025280 events.
[16:28:48.795] <TB1> INFO: 591032 events read in total (25591ms).
[16:29:14.877] <TB1> INFO: 1181240 events read in total (51673ms).
[16:29:40.382] <TB1> INFO: 1771368 events read in total (77178ms).
[16:30:05.879] <TB1> INFO: 2360264 events read in total (102675ms).
[16:30:31.685] <TB1> INFO: 2947512 events read in total (128481ms).
[16:30:57.694] <TB1> INFO: 3533560 events read in total (154490ms).
[16:31:23.147] <TB1> INFO: 4118432 events read in total (179943ms).
[16:31:48.589] <TB1> INFO: 4702432 events read in total (205385ms).
[16:32:03.302] <TB1> INFO: 5025280 events read in total (220098ms).
[16:32:03.384] <TB1> INFO: Test took 221051ms.
[16:32:28.161] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 58.3011 for pixel 13/0 mean/min/max = 44.9833/31.609/58.3576
[16:32:28.161] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 60.481 for pixel 9/4 mean/min/max = 45.7958/31.0557/60.5359
[16:32:28.162] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 58.8886 for pixel 20/7 mean/min/max = 45.7536/32.5971/58.91
[16:32:28.162] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 58.0137 for pixel 18/5 mean/min/max = 45.5466/33.0113/58.0819
[16:32:28.163] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 61.5258 for pixel 0/50 mean/min/max = 47.1327/32.7104/61.5549
[16:32:28.163] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 59.862 for pixel 0/0 mean/min/max = 46.2845/32.6235/59.9455
[16:32:28.164] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 63.8897 for pixel 0/56 mean/min/max = 49.6345/35.3361/63.933
[16:32:28.164] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 60.4024 for pixel 5/6 mean/min/max = 46.0792/31.6163/60.5421
[16:32:28.164] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 63.1795 for pixel 3/10 mean/min/max = 49.3406/35.4927/63.1886
[16:32:28.165] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 58.1395 for pixel 14/19 mean/min/max = 45.0814/31.936/58.2269
[16:32:28.165] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 59.2432 for pixel 12/3 mean/min/max = 45.8664/32.4504/59.2823
[16:32:28.165] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 59.1879 for pixel 10/7 mean/min/max = 45.8868/32.4591/59.3146
[16:32:28.166] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 58.2026 for pixel 8/14 mean/min/max = 45.2814/32.2332/58.3295
[16:32:28.166] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 61.8167 for pixel 2/12 mean/min/max = 46.7704/31.6823/61.8585
[16:32:28.166] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 62.1053 for pixel 10/78 mean/min/max = 48.8171/35.5231/62.111
[16:32:28.166] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 56.9173 for pixel 2/0 mean/min/max = 44.1148/31.2867/56.943
[16:32:28.168] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:32:28.256] <TB1> INFO: Expecting 411648 events.
[16:32:37.887] <TB1> INFO: 411648 events read in total (9039ms).
[16:32:37.894] <TB1> INFO: Expecting 411648 events.
[16:32:47.339] <TB1> INFO: 411648 events read in total (9042ms).
[16:32:47.351] <TB1> INFO: Expecting 411648 events.
[16:32:56.807] <TB1> INFO: 411648 events read in total (9053ms).
[16:32:56.824] <TB1> INFO: Expecting 411648 events.
[16:33:06.265] <TB1> INFO: 411648 events read in total (9038ms).
[16:33:06.280] <TB1> INFO: Expecting 411648 events.
[16:33:15.665] <TB1> INFO: 411648 events read in total (8982ms).
[16:33:15.685] <TB1> INFO: Expecting 411648 events.
[16:33:25.161] <TB1> INFO: 411648 events read in total (9073ms).
[16:33:25.184] <TB1> INFO: Expecting 411648 events.
[16:33:34.560] <TB1> INFO: 411648 events read in total (8973ms).
[16:33:34.583] <TB1> INFO: Expecting 411648 events.
[16:33:44.059] <TB1> INFO: 411648 events read in total (9073ms).
[16:33:44.084] <TB1> INFO: Expecting 411648 events.
[16:33:53.487] <TB1> INFO: 411648 events read in total (8999ms).
[16:33:53.516] <TB1> INFO: Expecting 411648 events.
[16:34:02.874] <TB1> INFO: 411648 events read in total (8955ms).
[16:34:02.907] <TB1> INFO: Expecting 411648 events.
[16:34:12.283] <TB1> INFO: 411648 events read in total (8973ms).
[16:34:12.317] <TB1> INFO: Expecting 411648 events.
[16:34:21.720] <TB1> INFO: 411648 events read in total (9000ms).
[16:34:21.761] <TB1> INFO: Expecting 411648 events.
[16:34:31.166] <TB1> INFO: 411648 events read in total (9002ms).
[16:34:31.206] <TB1> INFO: Expecting 411648 events.
[16:34:40.747] <TB1> INFO: 411648 events read in total (9138ms).
[16:34:40.793] <TB1> INFO: Expecting 411648 events.
[16:34:50.032] <TB1> INFO: 411648 events read in total (8837ms).
[16:34:50.148] <TB1> INFO: Expecting 411648 events.
[16:34:59.441] <TB1> INFO: 411648 events read in total (8890ms).
[16:34:59.491] <TB1> INFO: Test took 151323ms.
[16:35:00.270] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[16:35:00.285] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:35:00.285] <TB1> INFO: run 1 of 1
[16:35:00.535] <TB1> INFO: Expecting 5025280 events.
[16:35:26.842] <TB1> INFO: 588136 events read in total (25715ms).
[16:35:53.138] <TB1> INFO: 1174752 events read in total (52011ms).
[16:36:19.329] <TB1> INFO: 1761736 events read in total (78202ms).
[16:36:45.643] <TB1> INFO: 2348088 events read in total (104516ms).
[16:37:11.676] <TB1> INFO: 2931968 events read in total (130549ms).
[16:37:37.822] <TB1> INFO: 3515736 events read in total (156695ms).
[16:38:03.958] <TB1> INFO: 4098536 events read in total (182831ms).
[16:38:30.050] <TB1> INFO: 4683056 events read in total (208923ms).
[16:38:45.390] <TB1> INFO: 5025280 events read in total (224263ms).
[16:38:45.525] <TB1> INFO: Test took 225241ms.
[16:39:11.206] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 6.369174 .. 147.713399
[16:39:11.517] <TB1> INFO: Expecting 208000 events.
[16:39:21.350] <TB1> INFO: 208000 events read in total (9241ms).
[16:39:21.352] <TB1> INFO: Test took 10144ms.
[16:39:21.423] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 6 .. 157 (-1/-1) hits flags = 528 (plus default)
[16:39:21.437] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:39:21.437] <TB1> INFO: run 1 of 1
[16:39:21.715] <TB1> INFO: Expecting 5058560 events.
[16:39:47.615] <TB1> INFO: 577280 events read in total (25308ms).
[16:40:13.008] <TB1> INFO: 1154720 events read in total (50701ms).
[16:40:38.664] <TB1> INFO: 1731800 events read in total (76357ms).
[16:41:04.119] <TB1> INFO: 2308808 events read in total (101812ms).
[16:41:29.619] <TB1> INFO: 2886152 events read in total (127312ms).
[16:41:55.256] <TB1> INFO: 3462864 events read in total (152949ms).
[16:42:20.924] <TB1> INFO: 4039296 events read in total (178617ms).
[16:42:46.862] <TB1> INFO: 4614896 events read in total (204555ms).
[16:43:07.171] <TB1> INFO: 5058560 events read in total (224864ms).
[16:43:07.346] <TB1> INFO: Test took 225910ms.
[16:43:35.428] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.948755 .. 46.090146
[16:43:35.668] <TB1> INFO: Expecting 208000 events.
[16:43:45.639] <TB1> INFO: 208000 events read in total (9380ms).
[16:43:45.640] <TB1> INFO: Test took 10210ms.
[16:43:45.687] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[16:43:45.700] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:43:45.700] <TB1> INFO: run 1 of 1
[16:43:45.978] <TB1> INFO: Expecting 1331200 events.
[16:44:14.251] <TB1> INFO: 655584 events read in total (27682ms).
[16:44:42.464] <TB1> INFO: 1309688 events read in total (55896ms).
[16:44:43.812] <TB1> INFO: 1331200 events read in total (57244ms).
[16:44:43.855] <TB1> INFO: Test took 58156ms.
[16:44:58.020] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 26.014167 .. 46.705568
[16:44:58.260] <TB1> INFO: Expecting 208000 events.
[16:45:07.950] <TB1> INFO: 208000 events read in total (9099ms).
[16:45:07.951] <TB1> INFO: Test took 9930ms.
[16:45:07.000] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 56 (-1/-1) hits flags = 528 (plus default)
[16:45:08.014] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:45:08.014] <TB1> INFO: run 1 of 1
[16:45:08.292] <TB1> INFO: Expecting 1364480 events.
[16:45:36.806] <TB1> INFO: 660520 events read in total (27923ms).
[16:46:04.734] <TB1> INFO: 1320016 events read in total (55852ms).
[16:46:07.081] <TB1> INFO: 1364480 events read in total (58198ms).
[16:46:07.117] <TB1> INFO: Test took 59104ms.
[16:46:21.113] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 22.440198 .. 45.294049
[16:46:21.372] <TB1> INFO: Expecting 208000 events.
[16:46:31.214] <TB1> INFO: 208000 events read in total (9251ms).
[16:46:31.216] <TB1> INFO: Test took 10101ms.
[16:46:31.299] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 12 .. 55 (-1/-1) hits flags = 528 (plus default)
[16:46:31.313] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:46:31.313] <TB1> INFO: run 1 of 1
[16:46:31.591] <TB1> INFO: Expecting 1464320 events.
[16:46:59.997] <TB1> INFO: 678656 events read in total (27814ms).
[16:47:29.054] <TB1> INFO: 1358224 events read in total (56871ms).
[16:47:33.871] <TB1> INFO: 1464320 events read in total (61688ms).
[16:47:33.900] <TB1> INFO: Test took 62587ms.
[16:47:46.405] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[16:47:46.405] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[16:47:46.419] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:47:46.419] <TB1> INFO: run 1 of 1
[16:47:46.711] <TB1> INFO: Expecting 1364480 events.
[16:48:15.287] <TB1> INFO: 668264 events read in total (27984ms).
[16:48:43.262] <TB1> INFO: 1335128 events read in total (55959ms).
[16:48:44.883] <TB1> INFO: 1364480 events read in total (57581ms).
[16:48:44.915] <TB1> INFO: Test took 58497ms.
[16:48:56.988] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C0.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C1.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C2.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C3.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C4.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C5.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C6.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C7.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C8.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C9.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C10.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C11.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C12.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C13.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C14.dat
[16:48:56.989] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C15.dat
[16:48:56.990] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C0.dat
[16:48:56.994] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C1.dat
[16:48:56.999] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C2.dat
[16:48:57.004] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C3.dat
[16:48:57.008] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C4.dat
[16:48:57.013] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C5.dat
[16:48:57.018] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C6.dat
[16:48:57.023] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C7.dat
[16:48:57.028] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C8.dat
[16:48:57.032] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C9.dat
[16:48:57.037] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C10.dat
[16:48:57.042] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C11.dat
[16:48:57.047] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C12.dat
[16:48:57.052] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C13.dat
[16:48:57.056] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C14.dat
[16:48:57.061] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C15.dat
[16:48:57.066] <TB1> INFO: PixTestTrim::trimTest() done
[16:48:57.066] <TB1> INFO: vtrim: 119 140 115 121 140 120 118 120 126 128 124 119 116 129 129 122
[16:48:57.066] <TB1> INFO: vthrcomp: 127 127 123 114 132 129 108 127 108 126 115 132 123 128 108 127
[16:48:57.066] <TB1> INFO: vcal mean: 34.92 34.93 34.98 34.90 34.94 34.98 35.22 35.09 35.10 34.94 34.98 34.95 34.95 34.99 35.04 34.96
[16:48:57.066] <TB1> INFO: vcal RMS: 1.03 1.20 1.00 0.95 1.07 1.04 1.31 1.31 1.22 1.07 1.01 1.02 1.03 1.24 0.98 1.02
[16:48:57.066] <TB1> INFO: bits mean: 9.77 9.69 9.36 9.83 8.83 8.94 8.24 9.62 8.45 9.87 9.46 9.48 9.56 9.66 8.29 10.27
[16:48:57.066] <TB1> INFO: bits RMS: 2.72 2.76 2.74 2.49 2.86 2.89 2.63 2.76 2.52 2.60 2.78 2.69 2.73 2.67 2.51 2.59
[16:48:57.074] <TB1> INFO: ----------------------------------------------------------------------
[16:48:57.074] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[16:48:57.074] <TB1> INFO: ----------------------------------------------------------------------
[16:48:57.077] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[16:48:57.090] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[16:48:57.090] <TB1> INFO: run 1 of 1
[16:48:57.327] <TB1> INFO: Expecting 4160000 events.
[16:49:30.484] <TB1> INFO: 753840 events read in total (32565ms).
[16:50:02.882] <TB1> INFO: 1502770 events read in total (64963ms).
[16:50:35.486] <TB1> INFO: 2245800 events read in total (97567ms).
[16:51:07.658] <TB1> INFO: 2985330 events read in total (129739ms).
[16:51:39.393] <TB1> INFO: 3722975 events read in total (161474ms).
[16:51:58.864] <TB1> INFO: 4160000 events read in total (180945ms).
[16:51:58.958] <TB1> INFO: Test took 181868ms.
[16:52:25.268] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[16:52:25.283] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[16:52:25.283] <TB1> INFO: run 1 of 1
[16:52:25.530] <TB1> INFO: Expecting 4284800 events.
[16:52:57.605] <TB1> INFO: 722460 events read in total (31483ms).
[16:53:28.746] <TB1> INFO: 1441735 events read in total (62624ms).
[16:53:59.531] <TB1> INFO: 2156155 events read in total (93409ms).
[16:54:30.751] <TB1> INFO: 2866085 events read in total (124629ms).
[16:55:01.664] <TB1> INFO: 3575735 events read in total (155542ms).
[16:55:32.584] <TB1> INFO: 4284800 events read in total (186462ms).
[16:55:32.694] <TB1> INFO: Test took 187411ms.
[16:55:59.287] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[16:55:59.300] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[16:55:59.300] <TB1> INFO: run 1 of 1
[16:55:59.537] <TB1> INFO: Expecting 4160000 events.
[16:56:31.409] <TB1> INFO: 730825 events read in total (31281ms).
[16:57:03.482] <TB1> INFO: 1457595 events read in total (63354ms).
[16:57:34.742] <TB1> INFO: 2178825 events read in total (94614ms).
[16:58:06.165] <TB1> INFO: 2896725 events read in total (126037ms).
[16:58:37.497] <TB1> INFO: 3613470 events read in total (157369ms).
[16:59:01.251] <TB1> INFO: 4160000 events read in total (181123ms).
[16:59:01.358] <TB1> INFO: Test took 182057ms.
[16:59:27.160] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 192 (-1/-1) hits flags = 528 (plus default)
[16:59:27.174] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[16:59:27.174] <TB1> INFO: run 1 of 1
[16:59:27.448] <TB1> INFO: Expecting 4014400 events.
[17:00:00.292] <TB1> INFO: 740990 events read in total (32253ms).
[17:00:32.053] <TB1> INFO: 1477360 events read in total (64014ms).
[17:01:03.898] <TB1> INFO: 2207765 events read in total (95859ms).
[17:01:35.199] <TB1> INFO: 2935820 events read in total (127160ms).
[17:02:06.673] <TB1> INFO: 3660945 events read in total (158634ms).
[17:02:22.717] <TB1> INFO: 4014400 events read in total (174678ms).
[17:02:22.787] <TB1> INFO: Test took 175612ms.
[17:02:49.279] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 192 (-1/-1) hits flags = 528 (plus default)
[17:02:49.293] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:02:49.293] <TB1> INFO: run 1 of 1
[17:02:49.570] <TB1> INFO: Expecting 4014400 events.
[17:03:21.356] <TB1> INFO: 740920 events read in total (31194ms).
[17:03:53.283] <TB1> INFO: 1477260 events read in total (63121ms).
[17:04:25.353] <TB1> INFO: 2207165 events read in total (95191ms).
[17:04:57.372] <TB1> INFO: 2935205 events read in total (127210ms).
[17:05:29.013] <TB1> INFO: 3660235 events read in total (158851ms).
[17:05:44.359] <TB1> INFO: 4014400 events read in total (174197ms).
[17:05:44.438] <TB1> INFO: Test took 175145ms.
[17:06:09.332] <TB1> INFO: PixTestTrim::trimBitTest() done
[17:06:09.333] <TB1> INFO: PixTestTrim::doTest() done, duration: 2474 seconds
[17:06:09.333] <TB1> INFO: Decoding statistics:
[17:06:09.333] <TB1> INFO: General information:
[17:06:09.333] <TB1> INFO: 16bit words read: 0
[17:06:09.333] <TB1> INFO: valid events total: 0
[17:06:09.333] <TB1> INFO: empty events: 0
[17:06:09.333] <TB1> INFO: valid events with pixels: 0
[17:06:09.333] <TB1> INFO: valid pixel hits: 0
[17:06:09.333] <TB1> INFO: Event errors: 0
[17:06:09.333] <TB1> INFO: start marker: 0
[17:06:09.333] <TB1> INFO: stop marker: 0
[17:06:09.333] <TB1> INFO: overflow: 0
[17:06:09.333] <TB1> INFO: invalid 5bit words: 0
[17:06:09.333] <TB1> INFO: invalid XOR eye diagram: 0
[17:06:09.333] <TB1> INFO: frame (failed synchr.): 0
[17:06:09.333] <TB1> INFO: idle data (no TBM trl): 0
[17:06:09.333] <TB1> INFO: no data (only TBM hdr): 0
[17:06:09.333] <TB1> INFO: TBM errors: 0
[17:06:09.333] <TB1> INFO: flawed TBM headers: 0
[17:06:09.333] <TB1> INFO: flawed TBM trailers: 0
[17:06:09.333] <TB1> INFO: event ID mismatches: 0
[17:06:09.333] <TB1> INFO: ROC errors: 0
[17:06:09.333] <TB1> INFO: missing ROC header(s): 0
[17:06:09.333] <TB1> INFO: misplaced readback start: 0
[17:06:09.333] <TB1> INFO: Pixel decoding errors: 0
[17:06:09.333] <TB1> INFO: pixel data incomplete: 0
[17:06:09.333] <TB1> INFO: pixel address: 0
[17:06:09.333] <TB1> INFO: pulse height fill bit: 0
[17:06:09.333] <TB1> INFO: buffer corruption: 0
[17:06:09.987] <TB1> INFO: ######################################################################
[17:06:09.987] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[17:06:09.987] <TB1> INFO: ######################################################################
[17:06:10.225] <TB1> INFO: Expecting 41600 events.
[17:06:13.721] <TB1> INFO: 41600 events read in total (2904ms).
[17:06:13.721] <TB1> INFO: Test took 3733ms.
[17:06:14.161] <TB1> INFO: Expecting 41600 events.
[17:06:17.838] <TB1> INFO: 41600 events read in total (3086ms).
[17:06:17.838] <TB1> INFO: Test took 3913ms.
[17:06:18.128] <TB1> INFO: Expecting 41600 events.
[17:06:21.664] <TB1> INFO: 41600 events read in total (2944ms).
[17:06:21.665] <TB1> INFO: Test took 3802ms.
[17:06:21.954] <TB1> INFO: Expecting 41600 events.
[17:06:25.493] <TB1> INFO: 41600 events read in total (2947ms).
[17:06:25.494] <TB1> INFO: Test took 3804ms.
[17:06:25.784] <TB1> INFO: Expecting 41600 events.
[17:06:29.285] <TB1> INFO: 41600 events read in total (2910ms).
[17:06:29.285] <TB1> INFO: Test took 3766ms.
[17:06:29.590] <TB1> INFO: Expecting 41600 events.
[17:06:33.065] <TB1> INFO: 41600 events read in total (2884ms).
[17:06:33.066] <TB1> INFO: Test took 3757ms.
[17:06:33.355] <TB1> INFO: Expecting 41600 events.
[17:06:36.897] <TB1> INFO: 41600 events read in total (2950ms).
[17:06:36.898] <TB1> INFO: Test took 3808ms.
[17:06:37.188] <TB1> INFO: Expecting 41600 events.
[17:06:40.885] <TB1> INFO: 41600 events read in total (3106ms).
[17:06:40.886] <TB1> INFO: Test took 3963ms.
[17:06:41.175] <TB1> INFO: Expecting 41600 events.
[17:06:44.808] <TB1> INFO: 41600 events read in total (3041ms).
[17:06:44.809] <TB1> INFO: Test took 3899ms.
[17:06:45.101] <TB1> INFO: Expecting 41600 events.
[17:06:48.584] <TB1> INFO: 41600 events read in total (2892ms).
[17:06:48.584] <TB1> INFO: Test took 3748ms.
[17:06:48.873] <TB1> INFO: Expecting 41600 events.
[17:06:52.407] <TB1> INFO: 41600 events read in total (2942ms).
[17:06:52.408] <TB1> INFO: Test took 3799ms.
[17:06:52.697] <TB1> INFO: Expecting 41600 events.
[17:06:56.162] <TB1> INFO: 41600 events read in total (2874ms).
[17:06:56.162] <TB1> INFO: Test took 3730ms.
[17:06:56.451] <TB1> INFO: Expecting 41600 events.
[17:07:00.275] <TB1> INFO: 41600 events read in total (3232ms).
[17:07:00.276] <TB1> INFO: Test took 4089ms.
[17:07:00.570] <TB1> INFO: Expecting 41600 events.
[17:07:04.155] <TB1> INFO: 41600 events read in total (2994ms).
[17:07:04.156] <TB1> INFO: Test took 3851ms.
[17:07:04.445] <TB1> INFO: Expecting 41600 events.
[17:07:08.011] <TB1> INFO: 41600 events read in total (2974ms).
[17:07:08.012] <TB1> INFO: Test took 3832ms.
[17:07:08.300] <TB1> INFO: Expecting 41600 events.
[17:07:11.858] <TB1> INFO: 41600 events read in total (2966ms).
[17:07:11.859] <TB1> INFO: Test took 3823ms.
[17:07:12.149] <TB1> INFO: Expecting 41600 events.
[17:07:15.677] <TB1> INFO: 41600 events read in total (2936ms).
[17:07:15.678] <TB1> INFO: Test took 3795ms.
[17:07:15.972] <TB1> INFO: Expecting 41600 events.
[17:07:19.578] <TB1> INFO: 41600 events read in total (3014ms).
[17:07:19.578] <TB1> INFO: Test took 3871ms.
[17:07:19.869] <TB1> INFO: Expecting 41600 events.
[17:07:23.461] <TB1> INFO: 41600 events read in total (3000ms).
[17:07:23.461] <TB1> INFO: Test took 3856ms.
[17:07:23.751] <TB1> INFO: Expecting 41600 events.
[17:07:27.244] <TB1> INFO: 41600 events read in total (2901ms).
[17:07:27.245] <TB1> INFO: Test took 3759ms.
[17:07:27.551] <TB1> INFO: Expecting 41600 events.
[17:07:31.119] <TB1> INFO: 41600 events read in total (2976ms).
[17:07:31.120] <TB1> INFO: Test took 3848ms.
[17:07:31.410] <TB1> INFO: Expecting 41600 events.
[17:07:35.021] <TB1> INFO: 41600 events read in total (3020ms).
[17:07:35.022] <TB1> INFO: Test took 3878ms.
[17:07:35.312] <TB1> INFO: Expecting 41600 events.
[17:07:38.883] <TB1> INFO: 41600 events read in total (2979ms).
[17:07:38.884] <TB1> INFO: Test took 3838ms.
[17:07:39.174] <TB1> INFO: Expecting 41600 events.
[17:07:42.754] <TB1> INFO: 41600 events read in total (2988ms).
[17:07:42.754] <TB1> INFO: Test took 3845ms.
[17:07:43.048] <TB1> INFO: Expecting 41600 events.
[17:07:46.646] <TB1> INFO: 41600 events read in total (3007ms).
[17:07:46.647] <TB1> INFO: Test took 3865ms.
[17:07:46.938] <TB1> INFO: Expecting 41600 events.
[17:07:50.424] <TB1> INFO: 41600 events read in total (2894ms).
[17:07:50.425] <TB1> INFO: Test took 3751ms.
[17:07:50.715] <TB1> INFO: Expecting 41600 events.
[17:07:54.234] <TB1> INFO: 41600 events read in total (2928ms).
[17:07:54.234] <TB1> INFO: Test took 3784ms.
[17:07:54.526] <TB1> INFO: Expecting 41600 events.
[17:07:58.037] <TB1> INFO: 41600 events read in total (2919ms).
[17:07:58.038] <TB1> INFO: Test took 3777ms.
[17:07:58.332] <TB1> INFO: Expecting 41600 events.
[17:08:01.902] <TB1> INFO: 41600 events read in total (2980ms).
[17:08:01.903] <TB1> INFO: Test took 3836ms.
[17:08:02.194] <TB1> INFO: Expecting 2560 events.
[17:08:03.081] <TB1> INFO: 2560 events read in total (296ms).
[17:08:03.081] <TB1> INFO: Test took 1164ms.
[17:08:03.388] <TB1> INFO: Expecting 2560 events.
[17:08:04.275] <TB1> INFO: 2560 events read in total (295ms).
[17:08:04.275] <TB1> INFO: Test took 1193ms.
[17:08:04.583] <TB1> INFO: Expecting 2560 events.
[17:08:05.480] <TB1> INFO: 2560 events read in total (305ms).
[17:08:05.480] <TB1> INFO: Test took 1204ms.
[17:08:05.788] <TB1> INFO: Expecting 2560 events.
[17:08:06.675] <TB1> INFO: 2560 events read in total (295ms).
[17:08:06.675] <TB1> INFO: Test took 1194ms.
[17:08:06.982] <TB1> INFO: Expecting 2560 events.
[17:08:07.869] <TB1> INFO: 2560 events read in total (295ms).
[17:08:07.869] <TB1> INFO: Test took 1193ms.
[17:08:08.177] <TB1> INFO: Expecting 2560 events.
[17:08:09.066] <TB1> INFO: 2560 events read in total (297ms).
[17:08:09.066] <TB1> INFO: Test took 1196ms.
[17:08:09.373] <TB1> INFO: Expecting 2560 events.
[17:08:10.256] <TB1> INFO: 2560 events read in total (291ms).
[17:08:10.257] <TB1> INFO: Test took 1190ms.
[17:08:10.563] <TB1> INFO: Expecting 2560 events.
[17:08:11.446] <TB1> INFO: 2560 events read in total (291ms).
[17:08:11.447] <TB1> INFO: Test took 1189ms.
[17:08:11.755] <TB1> INFO: Expecting 2560 events.
[17:08:12.644] <TB1> INFO: 2560 events read in total (297ms).
[17:08:12.645] <TB1> INFO: Test took 1198ms.
[17:08:12.952] <TB1> INFO: Expecting 2560 events.
[17:08:13.839] <TB1> INFO: 2560 events read in total (295ms).
[17:08:13.840] <TB1> INFO: Test took 1194ms.
[17:08:14.148] <TB1> INFO: Expecting 2560 events.
[17:08:15.027] <TB1> INFO: 2560 events read in total (287ms).
[17:08:15.027] <TB1> INFO: Test took 1187ms.
[17:08:15.336] <TB1> INFO: Expecting 2560 events.
[17:08:16.226] <TB1> INFO: 2560 events read in total (299ms).
[17:08:16.226] <TB1> INFO: Test took 1198ms.
[17:08:16.533] <TB1> INFO: Expecting 2560 events.
[17:08:17.422] <TB1> INFO: 2560 events read in total (297ms).
[17:08:17.423] <TB1> INFO: Test took 1196ms.
[17:08:17.731] <TB1> INFO: Expecting 2560 events.
[17:08:18.614] <TB1> INFO: 2560 events read in total (291ms).
[17:08:18.614] <TB1> INFO: Test took 1191ms.
[17:08:18.922] <TB1> INFO: Expecting 2560 events.
[17:08:19.808] <TB1> INFO: 2560 events read in total (294ms).
[17:08:19.808] <TB1> INFO: Test took 1194ms.
[17:08:20.116] <TB1> INFO: Expecting 2560 events.
[17:08:20.001] <TB1> INFO: 2560 events read in total (294ms).
[17:08:20.001] <TB1> INFO: Test took 1192ms.
[17:08:21.006] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:08:21.311] <TB1> INFO: Expecting 655360 events.
[17:08:36.045] <TB1> INFO: 655360 events read in total (14143ms).
[17:08:36.060] <TB1> INFO: Expecting 655360 events.
[17:08:50.841] <TB1> INFO: 655360 events read in total (14377ms).
[17:08:50.864] <TB1> INFO: Expecting 655360 events.
[17:09:05.275] <TB1> INFO: 655360 events read in total (14008ms).
[17:09:05.301] <TB1> INFO: Expecting 655360 events.
[17:09:19.797] <TB1> INFO: 655360 events read in total (14093ms).
[17:09:19.828] <TB1> INFO: Expecting 655360 events.
[17:09:34.152] <TB1> INFO: 655360 events read in total (13921ms).
[17:09:34.188] <TB1> INFO: Expecting 655360 events.
[17:09:48.729] <TB1> INFO: 655360 events read in total (14138ms).
[17:09:48.769] <TB1> INFO: Expecting 655360 events.
[17:10:03.169] <TB1> INFO: 655360 events read in total (13997ms).
[17:10:03.228] <TB1> INFO: Expecting 655360 events.
[17:10:17.375] <TB1> INFO: 655360 events read in total (13744ms).
[17:10:17.425] <TB1> INFO: Expecting 655360 events.
[17:10:31.857] <TB1> INFO: 655360 events read in total (14029ms).
[17:10:31.943] <TB1> INFO: Expecting 655360 events.
[17:10:46.434] <TB1> INFO: 655360 events read in total (14088ms).
[17:10:46.505] <TB1> INFO: Expecting 655360 events.
[17:11:01.068] <TB1> INFO: 655360 events read in total (14161ms).
[17:11:01.172] <TB1> INFO: Expecting 655360 events.
[17:11:15.774] <TB1> INFO: 655360 events read in total (14199ms).
[17:11:15.869] <TB1> INFO: Expecting 655360 events.
[17:11:30.532] <TB1> INFO: 655360 events read in total (14259ms).
[17:11:30.623] <TB1> INFO: Expecting 655360 events.
[17:11:45.257] <TB1> INFO: 655360 events read in total (14231ms).
[17:11:45.368] <TB1> INFO: Expecting 655360 events.
[17:11:59.995] <TB1> INFO: 655360 events read in total (14224ms).
[17:12:00.098] <TB1> INFO: Expecting 655360 events.
[17:12:14.779] <TB1> INFO: 655360 events read in total (14278ms).
[17:12:14.965] <TB1> INFO: Test took 233959ms.
[17:12:15.078] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:12:15.336] <TB1> INFO: Expecting 655360 events.
[17:12:30.180] <TB1> INFO: 655360 events read in total (14252ms).
[17:12:30.198] <TB1> INFO: Expecting 655360 events.
[17:12:44.721] <TB1> INFO: 655360 events read in total (14120ms).
[17:12:44.747] <TB1> INFO: Expecting 655360 events.
[17:12:59.155] <TB1> INFO: 655360 events read in total (14005ms).
[17:12:59.180] <TB1> INFO: Expecting 655360 events.
[17:13:13.567] <TB1> INFO: 655360 events read in total (13984ms).
[17:13:13.598] <TB1> INFO: Expecting 655360 events.
[17:13:27.717] <TB1> INFO: 655360 events read in total (13716ms).
[17:13:27.752] <TB1> INFO: Expecting 655360 events.
[17:13:42.148] <TB1> INFO: 655360 events read in total (13992ms).
[17:13:42.198] <TB1> INFO: Expecting 655360 events.
[17:13:56.757] <TB1> INFO: 655360 events read in total (14156ms).
[17:13:56.802] <TB1> INFO: Expecting 655360 events.
[17:14:10.905] <TB1> INFO: 655360 events read in total (13700ms).
[17:14:10.954] <TB1> INFO: Expecting 655360 events.
[17:14:25.403] <TB1> INFO: 655360 events read in total (14046ms).
[17:14:25.495] <TB1> INFO: Expecting 655360 events.
[17:14:39.777] <TB1> INFO: 655360 events read in total (13879ms).
[17:14:39.856] <TB1> INFO: Expecting 655360 events.
[17:14:54.284] <TB1> INFO: 655360 events read in total (14025ms).
[17:14:54.361] <TB1> INFO: Expecting 655360 events.
[17:15:08.831] <TB1> INFO: 655360 events read in total (14067ms).
[17:15:08.971] <TB1> INFO: Expecting 655360 events.
[17:15:23.414] <TB1> INFO: 655360 events read in total (14040ms).
[17:15:23.535] <TB1> INFO: Expecting 655360 events.
[17:15:37.964] <TB1> INFO: 655360 events read in total (14026ms).
[17:15:38.111] <TB1> INFO: Expecting 655360 events.
[17:15:52.454] <TB1> INFO: 655360 events read in total (13939ms).
[17:15:52.583] <TB1> INFO: Expecting 655360 events.
[17:16:07.024] <TB1> INFO: 655360 events read in total (14038ms).
[17:16:07.165] <TB1> INFO: Test took 232087ms.
[17:16:07.333] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.339] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.345] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:07.351] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[17:16:07.357] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[17:16:07.363] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[17:16:07.369] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[17:16:07.375] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[17:16:07.381] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[17:16:07.387] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[17:16:07.393] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[17:16:07.399] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.404] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.411] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:07.416] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[17:16:07.423] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.429] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.434] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:07.440] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[17:16:07.446] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[17:16:07.452] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[17:16:07.457] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[17:16:07.463] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.469] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.475] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.480] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.486] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.492] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.498] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.503] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.509] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.515] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:07.520] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:07.558] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C0.dat
[17:16:07.558] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C1.dat
[17:16:07.558] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C2.dat
[17:16:07.559] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C3.dat
[17:16:07.559] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C4.dat
[17:16:07.559] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C5.dat
[17:16:07.559] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C6.dat
[17:16:07.559] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C7.dat
[17:16:07.559] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C8.dat
[17:16:07.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C9.dat
[17:16:07.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C10.dat
[17:16:07.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C11.dat
[17:16:07.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C12.dat
[17:16:07.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C13.dat
[17:16:07.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C14.dat
[17:16:07.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C15.dat
[17:16:07.811] <TB1> INFO: Expecting 41600 events.
[17:16:10.981] <TB1> INFO: 41600 events read in total (2578ms).
[17:16:10.981] <TB1> INFO: Test took 3418ms.
[17:16:11.434] <TB1> INFO: Expecting 41600 events.
[17:16:14.467] <TB1> INFO: 41600 events read in total (2442ms).
[17:16:14.468] <TB1> INFO: Test took 3272ms.
[17:16:14.948] <TB1> INFO: Expecting 41600 events.
[17:16:18.083] <TB1> INFO: 41600 events read in total (2543ms).
[17:16:18.084] <TB1> INFO: Test took 3403ms.
[17:16:18.307] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:18.396] <TB1> INFO: Expecting 2560 events.
[17:16:19.281] <TB1> INFO: 2560 events read in total (294ms).
[17:16:19.281] <TB1> INFO: Test took 975ms.
[17:16:19.283] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:19.589] <TB1> INFO: Expecting 2560 events.
[17:16:20.480] <TB1> INFO: 2560 events read in total (299ms).
[17:16:20.480] <TB1> INFO: Test took 1197ms.
[17:16:20.482] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:20.789] <TB1> INFO: Expecting 2560 events.
[17:16:21.675] <TB1> INFO: 2560 events read in total (294ms).
[17:16:21.675] <TB1> INFO: Test took 1193ms.
[17:16:21.680] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:21.984] <TB1> INFO: Expecting 2560 events.
[17:16:22.880] <TB1> INFO: 2560 events read in total (304ms).
[17:16:22.880] <TB1> INFO: Test took 1200ms.
[17:16:22.883] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:23.188] <TB1> INFO: Expecting 2560 events.
[17:16:24.081] <TB1> INFO: 2560 events read in total (301ms).
[17:16:24.081] <TB1> INFO: Test took 1198ms.
[17:16:24.084] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:24.389] <TB1> INFO: Expecting 2560 events.
[17:16:25.279] <TB1> INFO: 2560 events read in total (298ms).
[17:16:25.279] <TB1> INFO: Test took 1196ms.
[17:16:25.282] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:25.588] <TB1> INFO: Expecting 2560 events.
[17:16:26.476] <TB1> INFO: 2560 events read in total (296ms).
[17:16:26.476] <TB1> INFO: Test took 1195ms.
[17:16:26.480] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:26.784] <TB1> INFO: Expecting 2560 events.
[17:16:27.676] <TB1> INFO: 2560 events read in total (300ms).
[17:16:27.676] <TB1> INFO: Test took 1196ms.
[17:16:27.678] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:27.985] <TB1> INFO: Expecting 2560 events.
[17:16:28.868] <TB1> INFO: 2560 events read in total (292ms).
[17:16:28.868] <TB1> INFO: Test took 1190ms.
[17:16:28.872] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:29.176] <TB1> INFO: Expecting 2560 events.
[17:16:30.056] <TB1> INFO: 2560 events read in total (289ms).
[17:16:30.056] <TB1> INFO: Test took 1185ms.
[17:16:30.062] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:30.364] <TB1> INFO: Expecting 2560 events.
[17:16:31.250] <TB1> INFO: 2560 events read in total (294ms).
[17:16:31.250] <TB1> INFO: Test took 1188ms.
[17:16:31.252] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:31.560] <TB1> INFO: Expecting 2560 events.
[17:16:32.443] <TB1> INFO: 2560 events read in total (292ms).
[17:16:32.444] <TB1> INFO: Test took 1192ms.
[17:16:32.446] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:32.751] <TB1> INFO: Expecting 2560 events.
[17:16:33.636] <TB1> INFO: 2560 events read in total (293ms).
[17:16:33.637] <TB1> INFO: Test took 1191ms.
[17:16:33.640] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:33.944] <TB1> INFO: Expecting 2560 events.
[17:16:34.831] <TB1> INFO: 2560 events read in total (295ms).
[17:16:34.831] <TB1> INFO: Test took 1191ms.
[17:16:34.834] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:35.144] <TB1> INFO: Expecting 2560 events.
[17:16:36.026] <TB1> INFO: 2560 events read in total (290ms).
[17:16:36.026] <TB1> INFO: Test took 1192ms.
[17:16:36.029] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:36.334] <TB1> INFO: Expecting 2560 events.
[17:16:37.219] <TB1> INFO: 2560 events read in total (293ms).
[17:16:37.219] <TB1> INFO: Test took 1190ms.
[17:16:37.222] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:37.528] <TB1> INFO: Expecting 2560 events.
[17:16:38.416] <TB1> INFO: 2560 events read in total (296ms).
[17:16:38.417] <TB1> INFO: Test took 1195ms.
[17:16:38.420] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:38.723] <TB1> INFO: Expecting 2560 events.
[17:16:39.612] <TB1> INFO: 2560 events read in total (297ms).
[17:16:39.612] <TB1> INFO: Test took 1192ms.
[17:16:39.614] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:39.920] <TB1> INFO: Expecting 2560 events.
[17:16:40.815] <TB1> INFO: 2560 events read in total (303ms).
[17:16:40.815] <TB1> INFO: Test took 1201ms.
[17:16:40.818] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:41.123] <TB1> INFO: Expecting 2560 events.
[17:16:42.015] <TB1> INFO: 2560 events read in total (300ms).
[17:16:42.015] <TB1> INFO: Test took 1197ms.
[17:16:42.019] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:42.323] <TB1> INFO: Expecting 2560 events.
[17:16:43.207] <TB1> INFO: 2560 events read in total (293ms).
[17:16:43.208] <TB1> INFO: Test took 1189ms.
[17:16:43.210] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:43.515] <TB1> INFO: Expecting 2560 events.
[17:16:44.396] <TB1> INFO: 2560 events read in total (289ms).
[17:16:44.397] <TB1> INFO: Test took 1187ms.
[17:16:44.400] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:44.704] <TB1> INFO: Expecting 2560 events.
[17:16:45.585] <TB1> INFO: 2560 events read in total (289ms).
[17:16:45.585] <TB1> INFO: Test took 1185ms.
[17:16:45.587] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:45.893] <TB1> INFO: Expecting 2560 events.
[17:16:46.781] <TB1> INFO: 2560 events read in total (296ms).
[17:16:46.781] <TB1> INFO: Test took 1194ms.
[17:16:46.784] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:47.090] <TB1> INFO: Expecting 2560 events.
[17:16:47.977] <TB1> INFO: 2560 events read in total (295ms).
[17:16:47.977] <TB1> INFO: Test took 1193ms.
[17:16:47.981] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:48.286] <TB1> INFO: Expecting 2560 events.
[17:16:49.174] <TB1> INFO: 2560 events read in total (297ms).
[17:16:49.174] <TB1> INFO: Test took 1193ms.
[17:16:49.178] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:49.483] <TB1> INFO: Expecting 2560 events.
[17:16:50.376] <TB1> INFO: 2560 events read in total (301ms).
[17:16:50.376] <TB1> INFO: Test took 1199ms.
[17:16:50.378] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:50.685] <TB1> INFO: Expecting 2560 events.
[17:16:51.571] <TB1> INFO: 2560 events read in total (294ms).
[17:16:51.572] <TB1> INFO: Test took 1194ms.
[17:16:51.574] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:51.880] <TB1> INFO: Expecting 2560 events.
[17:16:52.771] <TB1> INFO: 2560 events read in total (299ms).
[17:16:52.771] <TB1> INFO: Test took 1198ms.
[17:16:52.774] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:53.078] <TB1> INFO: Expecting 2560 events.
[17:16:53.971] <TB1> INFO: 2560 events read in total (301ms).
[17:16:53.973] <TB1> INFO: Test took 1199ms.
[17:16:53.975] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:54.278] <TB1> INFO: Expecting 2560 events.
[17:16:55.168] <TB1> INFO: 2560 events read in total (298ms).
[17:16:55.168] <TB1> INFO: Test took 1193ms.
[17:16:55.171] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:55.477] <TB1> INFO: Expecting 2560 events.
[17:16:56.361] <TB1> INFO: 2560 events read in total (292ms).
[17:16:56.362] <TB1> INFO: Test took 1192ms.
[17:16:56.838] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 646 seconds
[17:16:56.838] <TB1> INFO: PH scale (per ROC): 51 48 45 44 51 45 58 39 35 51 49 46 44 45 50 41
[17:16:56.838] <TB1> INFO: PH offset (per ROC): 119 109 104 99 124 90 123 113 99 124 128 113 109 102 112 92
[17:16:56.846] <TB1> INFO: Decoding statistics:
[17:16:56.846] <TB1> INFO: General information:
[17:16:56.846] <TB1> INFO: 16bit words read: 127888
[17:16:56.846] <TB1> INFO: valid events total: 20480
[17:16:56.846] <TB1> INFO: empty events: 17976
[17:16:56.846] <TB1> INFO: valid events with pixels: 2504
[17:16:56.846] <TB1> INFO: valid pixel hits: 2504
[17:16:56.846] <TB1> INFO: Event errors: 0
[17:16:56.846] <TB1> INFO: start marker: 0
[17:16:56.846] <TB1> INFO: stop marker: 0
[17:16:56.846] <TB1> INFO: overflow: 0
[17:16:56.846] <TB1> INFO: invalid 5bit words: 0
[17:16:56.846] <TB1> INFO: invalid XOR eye diagram: 0
[17:16:56.846] <TB1> INFO: frame (failed synchr.): 0
[17:16:56.846] <TB1> INFO: idle data (no TBM trl): 0
[17:16:56.846] <TB1> INFO: no data (only TBM hdr): 0
[17:16:56.846] <TB1> INFO: TBM errors: 0
[17:16:56.846] <TB1> INFO: flawed TBM headers: 0
[17:16:56.846] <TB1> INFO: flawed TBM trailers: 0
[17:16:56.847] <TB1> INFO: event ID mismatches: 0
[17:16:56.847] <TB1> INFO: ROC errors: 0
[17:16:56.847] <TB1> INFO: missing ROC header(s): 0
[17:16:56.847] <TB1> INFO: misplaced readback start: 0
[17:16:56.847] <TB1> INFO: Pixel decoding errors: 0
[17:16:56.847] <TB1> INFO: pixel data incomplete: 0
[17:16:56.847] <TB1> INFO: pixel address: 0
[17:16:56.847] <TB1> INFO: pulse height fill bit: 0
[17:16:56.847] <TB1> INFO: buffer corruption: 0
[17:16:57.013] <TB1> INFO: ######################################################################
[17:16:57.013] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[17:16:57.013] <TB1> INFO: ######################################################################
[17:16:57.028] <TB1> INFO: scanning low vcal = 10
[17:16:57.283] <TB1> INFO: Expecting 41600 events.
[17:17:00.863] <TB1> INFO: 41600 events read in total (2988ms).
[17:17:00.864] <TB1> INFO: Test took 3836ms.
[17:17:00.866] <TB1> INFO: scanning low vcal = 20
[17:17:01.160] <TB1> INFO: Expecting 41600 events.
[17:17:04.764] <TB1> INFO: 41600 events read in total (3012ms).
[17:17:04.764] <TB1> INFO: Test took 3898ms.
[17:17:04.767] <TB1> INFO: scanning low vcal = 30
[17:17:05.057] <TB1> INFO: Expecting 41600 events.
[17:17:08.740] <TB1> INFO: 41600 events read in total (3091ms).
[17:17:08.741] <TB1> INFO: Test took 3973ms.
[17:17:08.743] <TB1> INFO: scanning low vcal = 40
[17:17:09.021] <TB1> INFO: Expecting 41600 events.
[17:17:12.003] <TB1> INFO: 41600 events read in total (3390ms).
[17:17:13.004] <TB1> INFO: Test took 4260ms.
[17:17:13.006] <TB1> INFO: scanning low vcal = 50
[17:17:13.284] <TB1> INFO: Expecting 41600 events.
[17:17:17.275] <TB1> INFO: 41600 events read in total (3399ms).
[17:17:17.276] <TB1> INFO: Test took 4270ms.
[17:17:17.280] <TB1> INFO: scanning low vcal = 60
[17:17:17.556] <TB1> INFO: Expecting 41600 events.
[17:17:21.621] <TB1> INFO: 41600 events read in total (3473ms).
[17:17:21.621] <TB1> INFO: Test took 4341ms.
[17:17:21.624] <TB1> INFO: scanning low vcal = 70
[17:17:21.909] <TB1> INFO: Expecting 41600 events.
[17:17:25.949] <TB1> INFO: 41600 events read in total (3448ms).
[17:17:25.950] <TB1> INFO: Test took 4326ms.
[17:17:25.953] <TB1> INFO: scanning low vcal = 80
[17:17:26.230] <TB1> INFO: Expecting 41600 events.
[17:17:30.218] <TB1> INFO: 41600 events read in total (3396ms).
[17:17:30.218] <TB1> INFO: Test took 4265ms.
[17:17:30.221] <TB1> INFO: scanning low vcal = 90
[17:17:30.499] <TB1> INFO: Expecting 41600 events.
[17:17:34.487] <TB1> INFO: 41600 events read in total (3396ms).
[17:17:34.487] <TB1> INFO: Test took 4266ms.
[17:17:34.491] <TB1> INFO: scanning low vcal = 100
[17:17:34.768] <TB1> INFO: Expecting 41600 events.
[17:17:38.815] <TB1> INFO: 41600 events read in total (3455ms).
[17:17:38.816] <TB1> INFO: Test took 4325ms.
[17:17:38.819] <TB1> INFO: scanning low vcal = 110
[17:17:39.096] <TB1> INFO: Expecting 41600 events.
[17:17:43.131] <TB1> INFO: 41600 events read in total (3443ms).
[17:17:43.132] <TB1> INFO: Test took 4313ms.
[17:17:43.135] <TB1> INFO: scanning low vcal = 120
[17:17:43.412] <TB1> INFO: Expecting 41600 events.
[17:17:47.421] <TB1> INFO: 41600 events read in total (3417ms).
[17:17:47.422] <TB1> INFO: Test took 4287ms.
[17:17:47.428] <TB1> INFO: scanning low vcal = 130
[17:17:47.703] <TB1> INFO: Expecting 41600 events.
[17:17:51.767] <TB1> INFO: 41600 events read in total (3472ms).
[17:17:51.767] <TB1> INFO: Test took 4339ms.
[17:17:51.771] <TB1> INFO: scanning low vcal = 140
[17:17:52.049] <TB1> INFO: Expecting 41600 events.
[17:17:56.054] <TB1> INFO: 41600 events read in total (3414ms).
[17:17:56.055] <TB1> INFO: Test took 4284ms.
[17:17:56.058] <TB1> INFO: scanning low vcal = 150
[17:17:56.334] <TB1> INFO: Expecting 41600 events.
[17:18:00.363] <TB1> INFO: 41600 events read in total (3437ms).
[17:18:00.364] <TB1> INFO: Test took 4306ms.
[17:18:00.367] <TB1> INFO: scanning low vcal = 160
[17:18:00.644] <TB1> INFO: Expecting 41600 events.
[17:18:04.662] <TB1> INFO: 41600 events read in total (3426ms).
[17:18:04.663] <TB1> INFO: Test took 4296ms.
[17:18:04.666] <TB1> INFO: scanning low vcal = 170
[17:18:04.943] <TB1> INFO: Expecting 41600 events.
[17:18:09.007] <TB1> INFO: 41600 events read in total (3472ms).
[17:18:09.007] <TB1> INFO: Test took 4341ms.
[17:18:09.013] <TB1> INFO: scanning low vcal = 180
[17:18:09.288] <TB1> INFO: Expecting 41600 events.
[17:18:13.304] <TB1> INFO: 41600 events read in total (3424ms).
[17:18:13.305] <TB1> INFO: Test took 4292ms.
[17:18:13.308] <TB1> INFO: scanning low vcal = 190
[17:18:13.585] <TB1> INFO: Expecting 41600 events.
[17:18:17.609] <TB1> INFO: 41600 events read in total (3432ms).
[17:18:17.610] <TB1> INFO: Test took 4302ms.
[17:18:17.613] <TB1> INFO: scanning low vcal = 200
[17:18:17.890] <TB1> INFO: Expecting 41600 events.
[17:18:21.938] <TB1> INFO: 41600 events read in total (3456ms).
[17:18:21.939] <TB1> INFO: Test took 4326ms.
[17:18:21.942] <TB1> INFO: scanning low vcal = 210
[17:18:22.219] <TB1> INFO: Expecting 41600 events.
[17:18:26.251] <TB1> INFO: 41600 events read in total (3440ms).
[17:18:26.251] <TB1> INFO: Test took 4309ms.
[17:18:26.254] <TB1> INFO: scanning low vcal = 220
[17:18:26.531] <TB1> INFO: Expecting 41600 events.
[17:18:30.524] <TB1> INFO: 41600 events read in total (3401ms).
[17:18:30.525] <TB1> INFO: Test took 4271ms.
[17:18:30.528] <TB1> INFO: scanning low vcal = 230
[17:18:30.805] <TB1> INFO: Expecting 41600 events.
[17:18:34.817] <TB1> INFO: 41600 events read in total (3420ms).
[17:18:34.818] <TB1> INFO: Test took 4290ms.
[17:18:34.821] <TB1> INFO: scanning low vcal = 240
[17:18:35.098] <TB1> INFO: Expecting 41600 events.
[17:18:39.136] <TB1> INFO: 41600 events read in total (3446ms).
[17:18:39.137] <TB1> INFO: Test took 4316ms.
[17:18:39.139] <TB1> INFO: scanning low vcal = 250
[17:18:39.417] <TB1> INFO: Expecting 41600 events.
[17:18:43.415] <TB1> INFO: 41600 events read in total (3406ms).
[17:18:43.416] <TB1> INFO: Test took 4277ms.
[17:18:43.420] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[17:18:43.696] <TB1> INFO: Expecting 41600 events.
[17:18:47.728] <TB1> INFO: 41600 events read in total (3440ms).
[17:18:47.728] <TB1> INFO: Test took 4308ms.
[17:18:47.731] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[17:18:48.009] <TB1> INFO: Expecting 41600 events.
[17:18:52.046] <TB1> INFO: 41600 events read in total (3446ms).
[17:18:52.047] <TB1> INFO: Test took 4316ms.
[17:18:52.050] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[17:18:52.327] <TB1> INFO: Expecting 41600 events.
[17:18:56.335] <TB1> INFO: 41600 events read in total (3416ms).
[17:18:56.336] <TB1> INFO: Test took 4286ms.
[17:18:56.339] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[17:18:56.616] <TB1> INFO: Expecting 41600 events.
[17:19:00.649] <TB1> INFO: 41600 events read in total (3442ms).
[17:19:00.650] <TB1> INFO: Test took 4311ms.
[17:19:00.653] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[17:19:00.930] <TB1> INFO: Expecting 41600 events.
[17:19:04.990] <TB1> INFO: 41600 events read in total (3468ms).
[17:19:04.991] <TB1> INFO: Test took 4338ms.
[17:19:05.586] <TB1> INFO: PixTestGainPedestal::measure() done
[17:19:39.413] <TB1> INFO: PixTestGainPedestal::fit() done
[17:19:39.413] <TB1> INFO: non-linearity mean: 0.981 0.972 0.940 0.963 0.984 0.936 0.984 0.955 0.983 0.976 0.980 0.961 0.910 0.953 0.981 0.919
[17:19:39.413] <TB1> INFO: non-linearity RMS: 0.004 0.026 0.103 0.013 0.004 0.070 0.003 0.040 0.191 0.004 0.005 0.029 0.124 0.047 0.003 0.092
[17:19:39.413] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[17:19:39.433] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[17:19:39.452] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[17:19:39.465] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[17:19:39.479] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[17:19:39.493] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[17:19:39.507] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[17:19:39.521] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[17:19:39.535] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[17:19:39.548] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[17:19:39.563] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[17:19:39.576] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[17:19:39.590] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[17:19:39.603] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[17:19:39.617] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[17:19:39.631] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[17:19:39.647] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 162 seconds
[17:19:39.647] <TB1> INFO: Decoding statistics:
[17:19:39.647] <TB1> INFO: General information:
[17:19:39.647] <TB1> INFO: 16bit words read: 3314650
[17:19:39.647] <TB1> INFO: valid events total: 332800
[17:19:39.647] <TB1> INFO: empty events: 147
[17:19:39.647] <TB1> INFO: valid events with pixels: 332653
[17:19:39.647] <TB1> INFO: valid pixel hits: 658925
[17:19:39.647] <TB1> INFO: Event errors: 0
[17:19:39.647] <TB1> INFO: start marker: 0
[17:19:39.647] <TB1> INFO: stop marker: 0
[17:19:39.647] <TB1> INFO: overflow: 0
[17:19:39.647] <TB1> INFO: invalid 5bit words: 0
[17:19:39.647] <TB1> INFO: invalid XOR eye diagram: 0
[17:19:39.647] <TB1> INFO: frame (failed synchr.): 0
[17:19:39.647] <TB1> INFO: idle data (no TBM trl): 0
[17:19:39.647] <TB1> INFO: no data (only TBM hdr): 0
[17:19:39.647] <TB1> INFO: TBM errors: 0
[17:19:39.647] <TB1> INFO: flawed TBM headers: 0
[17:19:39.647] <TB1> INFO: flawed TBM trailers: 0
[17:19:39.647] <TB1> INFO: event ID mismatches: 0
[17:19:39.647] <TB1> INFO: ROC errors: 0
[17:19:39.647] <TB1> INFO: missing ROC header(s): 0
[17:19:39.647] <TB1> INFO: misplaced readback start: 0
[17:19:39.647] <TB1> INFO: Pixel decoding errors: 0
[17:19:39.647] <TB1> INFO: pixel data incomplete: 0
[17:19:39.647] <TB1> INFO: pixel address: 0
[17:19:39.647] <TB1> INFO: pulse height fill bit: 0
[17:19:39.647] <TB1> INFO: buffer corruption: 0
[17:19:39.663] <TB1> INFO: Decoding statistics:
[17:19:39.663] <TB1> INFO: General information:
[17:19:39.663] <TB1> INFO: 16bit words read: 3444074
[17:19:39.663] <TB1> INFO: valid events total: 353536
[17:19:39.663] <TB1> INFO: empty events: 18379
[17:19:39.663] <TB1> INFO: valid events with pixels: 335157
[17:19:39.663] <TB1> INFO: valid pixel hits: 661429
[17:19:39.663] <TB1> INFO: Event errors: 0
[17:19:39.663] <TB1> INFO: start marker: 0
[17:19:39.663] <TB1> INFO: stop marker: 0
[17:19:39.663] <TB1> INFO: overflow: 0
[17:19:39.663] <TB1> INFO: invalid 5bit words: 0
[17:19:39.663] <TB1> INFO: invalid XOR eye diagram: 0
[17:19:39.663] <TB1> INFO: frame (failed synchr.): 0
[17:19:39.663] <TB1> INFO: idle data (no TBM trl): 0
[17:19:39.663] <TB1> INFO: no data (only TBM hdr): 0
[17:19:39.663] <TB1> INFO: TBM errors: 0
[17:19:39.663] <TB1> INFO: flawed TBM headers: 0
[17:19:39.663] <TB1> INFO: flawed TBM trailers: 0
[17:19:39.663] <TB1> INFO: event ID mismatches: 0
[17:19:39.663] <TB1> INFO: ROC errors: 0
[17:19:39.663] <TB1> INFO: missing ROC header(s): 0
[17:19:39.663] <TB1> INFO: misplaced readback start: 0
[17:19:39.663] <TB1> INFO: Pixel decoding errors: 0
[17:19:39.663] <TB1> INFO: pixel data incomplete: 0
[17:19:39.663] <TB1> INFO: pixel address: 0
[17:19:39.663] <TB1> INFO: pulse height fill bit: 0
[17:19:39.663] <TB1> INFO: buffer corruption: 0
[17:19:39.663] <TB1> INFO: enter test to run
[17:19:39.663] <TB1> INFO: test: trim80 no parameter change
[17:19:39.663] <TB1> INFO: running: trim80
[17:19:39.665] <TB1> INFO: ######################################################################
[17:19:39.665] <TB1> INFO: PixTestTrim80::doTest()
[17:19:39.665] <TB1> INFO: ######################################################################
[17:19:39.666] <TB1> INFO: ----------------------------------------------------------------------
[17:19:39.666] <TB1> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[17:19:39.666] <TB1> INFO: ----------------------------------------------------------------------
[17:19:39.707] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[17:19:39.707] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:19:39.721] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:19:39.721] <TB1> INFO: run 1 of 1
[17:19:39.977] <TB1> INFO: Expecting 5025280 events.
[17:20:07.379] <TB1> INFO: 675440 events read in total (26810ms).
[17:20:34.402] <TB1> INFO: 1347344 events read in total (53833ms).
[17:21:01.911] <TB1> INFO: 2016192 events read in total (81342ms).
[17:21:29.681] <TB1> INFO: 2683600 events read in total (109112ms).
[17:21:57.128] <TB1> INFO: 3351464 events read in total (136559ms).
[17:22:24.612] <TB1> INFO: 4019624 events read in total (164043ms).
[17:22:52.613] <TB1> INFO: 4688912 events read in total (192044ms).
[17:23:06.901] <TB1> INFO: 5025280 events read in total (206332ms).
[17:23:07.008] <TB1> INFO: Test took 207287ms.
[17:23:29.888] <TB1> INFO: ROC 0 VthrComp = 77
[17:23:29.888] <TB1> INFO: ROC 1 VthrComp = 76
[17:23:29.888] <TB1> INFO: ROC 2 VthrComp = 74
[17:23:29.888] <TB1> INFO: ROC 3 VthrComp = 69
[17:23:29.888] <TB1> INFO: ROC 4 VthrComp = 80
[17:23:29.888] <TB1> INFO: ROC 5 VthrComp = 79
[17:23:29.889] <TB1> INFO: ROC 6 VthrComp = 69
[17:23:29.889] <TB1> INFO: ROC 7 VthrComp = 79
[17:23:29.889] <TB1> INFO: ROC 8 VthrComp = 67
[17:23:29.889] <TB1> INFO: ROC 9 VthrComp = 73
[17:23:29.889] <TB1> INFO: ROC 10 VthrComp = 69
[17:23:29.889] <TB1> INFO: ROC 11 VthrComp = 77
[17:23:29.889] <TB1> INFO: ROC 12 VthrComp = 72
[17:23:29.890] <TB1> INFO: ROC 13 VthrComp = 78
[17:23:29.890] <TB1> INFO: ROC 14 VthrComp = 64
[17:23:29.890] <TB1> INFO: ROC 15 VthrComp = 73
[17:23:30.128] <TB1> INFO: Expecting 41600 events.
[17:23:33.627] <TB1> INFO: 41600 events read in total (2907ms).
[17:23:33.628] <TB1> INFO: Test took 3737ms.
[17:23:33.637] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[17:23:33.637] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:23:33.648] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:23:33.648] <TB1> INFO: run 1 of 1
[17:23:33.926] <TB1> INFO: Expecting 5025280 events.
[17:24:03.024] <TB1> INFO: 685936 events read in total (28506ms).
[17:24:30.674] <TB1> INFO: 1369360 events read in total (56156ms).
[17:24:58.374] <TB1> INFO: 2051160 events read in total (83856ms).
[17:25:25.991] <TB1> INFO: 2729512 events read in total (111473ms).
[17:25:53.728] <TB1> INFO: 3404256 events read in total (139210ms).
[17:26:21.222] <TB1> INFO: 4078288 events read in total (166704ms).
[17:26:49.011] <TB1> INFO: 4751832 events read in total (194493ms).
[17:27:00.265] <TB1> INFO: 5025280 events read in total (205747ms).
[17:27:00.373] <TB1> INFO: Test took 206725ms.
[17:27:23.234] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 108.736 for pixel 0/36 mean/min/max = 93.8471/78.6446/109.05
[17:27:23.234] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 112.758 for pixel 51/36 mean/min/max = 95.8058/78.7948/112.817
[17:27:23.234] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 107.821 for pixel 11/8 mean/min/max = 92.8579/77.492/108.224
[17:27:23.235] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 104.626 for pixel 51/77 mean/min/max = 89.2187/73.7792/104.658
[17:27:23.235] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 108.524 for pixel 15/0 mean/min/max = 92.2401/75.7012/108.779
[17:27:23.236] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 108.703 for pixel 7/70 mean/min/max = 93.6129/78.5033/108.722
[17:27:23.236] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 106.953 for pixel 0/8 mean/min/max = 90.5896/74.2067/106.972
[17:27:23.236] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 111.209 for pixel 0/24 mean/min/max = 94.755/78.2594/111.251
[17:27:23.237] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 105.211 for pixel 0/9 mean/min/max = 89.7361/74.1715/105.301
[17:27:23.237] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 108.784 for pixel 0/5 mean/min/max = 93.2631/77.3447/109.181
[17:27:23.237] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 105.563 for pixel 0/16 mean/min/max = 90.0187/74.4502/105.587
[17:27:23.238] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 110.655 for pixel 0/62 mean/min/max = 94.3764/78.0062/110.746
[17:27:23.238] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 108.482 for pixel 26/79 mean/min/max = 93.3047/78.1136/108.496
[17:27:23.238] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 112.634 for pixel 0/17 mean/min/max = 95.5281/78.1503/112.906
[17:27:23.239] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 107.564 for pixel 18/57 mean/min/max = 91.7402/75.8805/107.6
[17:27:23.239] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 106.576 for pixel 12/79 mean/min/max = 91.8449/77.0744/106.615
[17:27:23.240] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:27:23.329] <TB1> INFO: Expecting 411648 events.
[17:27:32.838] <TB1> INFO: 411648 events read in total (8917ms).
[17:27:32.848] <TB1> INFO: Expecting 411648 events.
[17:27:42.294] <TB1> INFO: 411648 events read in total (9043ms).
[17:27:42.308] <TB1> INFO: Expecting 411648 events.
[17:27:51.691] <TB1> INFO: 411648 events read in total (8980ms).
[17:27:51.706] <TB1> INFO: Expecting 411648 events.
[17:28:00.976] <TB1> INFO: 411648 events read in total (8866ms).
[17:28:00.997] <TB1> INFO: Expecting 411648 events.
[17:28:10.125] <TB1> INFO: 411648 events read in total (8725ms).
[17:28:10.148] <TB1> INFO: Expecting 411648 events.
[17:28:19.360] <TB1> INFO: 411648 events read in total (8809ms).
[17:28:19.382] <TB1> INFO: Expecting 411648 events.
[17:28:28.590] <TB1> INFO: 411648 events read in total (8805ms).
[17:28:28.620] <TB1> INFO: Expecting 411648 events.
[17:28:38.009] <TB1> INFO: 411648 events read in total (8986ms).
[17:28:38.037] <TB1> INFO: Expecting 411648 events.
[17:28:47.376] <TB1> INFO: 411648 events read in total (8936ms).
[17:28:47.431] <TB1> INFO: Expecting 411648 events.
[17:28:56.626] <TB1> INFO: 411648 events read in total (8792ms).
[17:28:56.667] <TB1> INFO: Expecting 411648 events.
[17:29:06.153] <TB1> INFO: 411648 events read in total (9083ms).
[17:29:06.221] <TB1> INFO: Expecting 411648 events.
[17:29:15.529] <TB1> INFO: 411648 events read in total (8905ms).
[17:29:15.579] <TB1> INFO: Expecting 411648 events.
[17:29:24.864] <TB1> INFO: 411648 events read in total (8882ms).
[17:29:24.939] <TB1> INFO: Expecting 411648 events.
[17:29:34.366] <TB1> INFO: 411648 events read in total (9024ms).
[17:29:34.432] <TB1> INFO: Expecting 411648 events.
[17:29:43.821] <TB1> INFO: 411648 events read in total (8986ms).
[17:29:43.941] <TB1> INFO: Expecting 411648 events.
[17:29:53.202] <TB1> INFO: 411648 events read in total (8858ms).
[17:29:53.318] <TB1> INFO: Test took 150079ms.
[17:29:55.104] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[17:29:55.118] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:29:55.118] <TB1> INFO: run 1 of 1
[17:29:55.364] <TB1> INFO: Expecting 5025280 events.
[17:30:23.077] <TB1> INFO: 670752 events read in total (27121ms).
[17:30:50.384] <TB1> INFO: 1339920 events read in total (54428ms).
[17:31:18.276] <TB1> INFO: 2007464 events read in total (82320ms).
[17:31:46.541] <TB1> INFO: 2673264 events read in total (110585ms).
[17:32:13.734] <TB1> INFO: 3336024 events read in total (137778ms).
[17:32:40.823] <TB1> INFO: 3997720 events read in total (164867ms).
[17:33:07.764] <TB1> INFO: 4658176 events read in total (191808ms).
[17:33:23.079] <TB1> INFO: 5025280 events read in total (207123ms).
[17:33:23.173] <TB1> INFO: Test took 208055ms.
[17:33:46.874] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 55.115809 .. 100.520294
[17:33:47.114] <TB1> INFO: Expecting 208000 events.
[17:33:57.191] <TB1> INFO: 208000 events read in total (9485ms).
[17:33:57.192] <TB1> INFO: Test took 10317ms.
[17:33:57.272] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 45 .. 110 (-1/-1) hits flags = 528 (plus default)
[17:33:57.286] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:33:57.287] <TB1> INFO: run 1 of 1
[17:33:57.612] <TB1> INFO: Expecting 2196480 events.
[17:34:26.399] <TB1> INFO: 686072 events read in total (28195ms).
[17:34:54.377] <TB1> INFO: 1369704 events read in total (56173ms).
[17:35:22.288] <TB1> INFO: 2047304 events read in total (84084ms).
[17:35:28.840] <TB1> INFO: 2196480 events read in total (90636ms).
[17:35:28.879] <TB1> INFO: Test took 91592ms.
[17:35:48.040] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 63.492504 .. 91.925766
[17:35:48.294] <TB1> INFO: Expecting 208000 events.
[17:35:58.572] <TB1> INFO: 208000 events read in total (9687ms).
[17:35:58.573] <TB1> INFO: Test took 10532ms.
[17:35:58.624] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 53 .. 101 (-1/-1) hits flags = 528 (plus default)
[17:35:58.636] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:35:58.636] <TB1> INFO: run 1 of 1
[17:35:58.914] <TB1> INFO: Expecting 1630720 events.
[17:36:27.991] <TB1> INFO: 690504 events read in total (28485ms).
[17:36:56.371] <TB1> INFO: 1379888 events read in total (56865ms).
[17:37:06.992] <TB1> INFO: 1630720 events read in total (67486ms).
[17:37:07.032] <TB1> INFO: Test took 68396ms.
[17:37:23.656] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 68.717571 .. 87.573800
[17:37:23.896] <TB1> INFO: Expecting 208000 events.
[17:37:33.818] <TB1> INFO: 208000 events read in total (9330ms).
[17:37:33.819] <TB1> INFO: Test took 10161ms.
[17:37:33.892] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 58 .. 97 (-1/-1) hits flags = 528 (plus default)
[17:37:33.906] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:37:33.906] <TB1> INFO: run 1 of 1
[17:37:34.233] <TB1> INFO: Expecting 1331200 events.
[17:38:04.299] <TB1> INFO: 691400 events read in total (29474ms).
[17:38:30.922] <TB1> INFO: 1331200 events read in total (56097ms).
[17:38:30.951] <TB1> INFO: Test took 57045ms.
[17:38:47.016] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 71.351294 .. 87.573800
[17:38:47.256] <TB1> INFO: Expecting 208000 events.
[17:38:57.512] <TB1> INFO: 208000 events read in total (9664ms).
[17:38:57.513] <TB1> INFO: Test took 10496ms.
[17:38:57.561] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 61 .. 97 (-1/-1) hits flags = 528 (plus default)
[17:38:57.575] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:38:57.575] <TB1> INFO: run 1 of 1
[17:38:57.856] <TB1> INFO: Expecting 1231360 events.
[17:39:26.503] <TB1> INFO: 680688 events read in total (28055ms).
[17:39:49.582] <TB1> INFO: 1231360 events read in total (51135ms).
[17:39:49.624] <TB1> INFO: Test took 52049ms.
[17:40:06.662] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[17:40:06.662] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[17:40:06.676] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:40:06.676] <TB1> INFO: run 1 of 1
[17:40:06.918] <TB1> INFO: Expecting 1364480 events.
[17:40:35.365] <TB1> INFO: 669176 events read in total (27856ms).
[17:41:03.436] <TB1> INFO: 1338152 events read in total (55927ms).
[17:41:04.936] <TB1> INFO: 1364480 events read in total (57427ms).
[17:41:04.960] <TB1> INFO: Test took 58285ms.
[17:41:23.314] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C0.dat
[17:41:23.314] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C1.dat
[17:41:23.314] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C2.dat
[17:41:23.314] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C3.dat
[17:41:23.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C4.dat
[17:41:23.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C5.dat
[17:41:23.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C6.dat
[17:41:23.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C7.dat
[17:41:23.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C8.dat
[17:41:23.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C9.dat
[17:41:23.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C10.dat
[17:41:23.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C11.dat
[17:41:23.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C12.dat
[17:41:23.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C13.dat
[17:41:23.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C14.dat
[17:41:23.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C15.dat
[17:41:23.316] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C0.dat
[17:41:23.322] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C1.dat
[17:41:23.326] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C2.dat
[17:41:23.331] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C3.dat
[17:41:23.336] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C4.dat
[17:41:23.341] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C5.dat
[17:41:23.346] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C6.dat
[17:41:23.351] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C7.dat
[17:41:23.355] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C8.dat
[17:41:23.360] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C9.dat
[17:41:23.365] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C10.dat
[17:41:23.370] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C11.dat
[17:41:23.375] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C12.dat
[17:41:23.380] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C13.dat
[17:41:23.384] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C14.dat
[17:41:23.389] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1128_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C15.dat
[17:41:23.394] <TB1> INFO: PixTestTrim80::trimTest() done
[17:41:23.394] <TB1> INFO: vtrim: 101 126 95 82 110 100 85 100 82 98 90 91 94 106 94 92
[17:41:23.394] <TB1> INFO: vthrcomp: 77 76 74 69 80 79 69 79 67 73 69 77 72 78 64 73
[17:41:23.394] <TB1> INFO: vcal mean: 80.01 80.01 80.03 79.99 80.04 80.08 79.98 80.03 80.02 80.03 80.00 80.06 80.06 80.05 80.04 80.02
[17:41:23.394] <TB1> INFO: vcal RMS: 0.69 0.74 0.68 0.70 0.71 0.73 0.72 0.75 0.74 0.69 0.68 0.70 0.71 0.77 0.72 0.68
[17:41:23.394] <TB1> INFO: bits mean: 9.13 9.44 9.62 10.54 9.67 9.13 10.37 8.86 10.32 9.26 10.36 8.83 9.25 9.18 9.97 9.72
[17:41:23.394] <TB1> INFO: bits RMS: 2.25 2.06 2.23 2.46 2.49 2.30 2.39 2.36 2.49 2.36 2.42 2.42 2.30 2.27 2.35 2.21
[17:41:23.400] <TB1> INFO: ----------------------------------------------------------------------
[17:41:23.400] <TB1> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[17:41:23.400] <TB1> INFO: ----------------------------------------------------------------------
[17:41:23.403] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[17:41:23.416] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:41:23.416] <TB1> INFO: run 1 of 1
[17:41:23.652] <TB1> INFO: Expecting 4160000 events.
[17:41:56.367] <TB1> INFO: 753650 events read in total (32125ms).
[17:42:28.672] <TB1> INFO: 1502400 events read in total (64429ms).
[17:43:01.088] <TB1> INFO: 2245940 events read in total (96845ms).
[17:43:33.199] <TB1> INFO: 2985785 events read in total (128956ms).
[17:44:05.312] <TB1> INFO: 3722925 events read in total (161069ms).
[17:44:24.589] <TB1> INFO: 4160000 events read in total (180346ms).
[17:44:24.663] <TB1> INFO: Test took 181247ms.
[17:44:49.965] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[17:44:49.978] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:44:49.978] <TB1> INFO: run 1 of 1
[17:44:50.215] <TB1> INFO: Expecting 4243200 events.
[17:45:22.665] <TB1> INFO: 724940 events read in total (31858ms).
[17:45:53.995] <TB1> INFO: 1446035 events read in total (63188ms).
[17:46:25.075] <TB1> INFO: 2163025 events read in total (94268ms).
[17:46:55.986] <TB1> INFO: 2875800 events read in total (125179ms).
[17:47:27.283] <TB1> INFO: 3587085 events read in total (156476ms).
[17:47:56.073] <TB1> INFO: 4243200 events read in total (185266ms).
[17:47:56.202] <TB1> INFO: Test took 186224ms.
[17:48:24.782] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 201 (-1/-1) hits flags = 528 (plus default)
[17:48:24.796] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:48:24.796] <TB1> INFO: run 1 of 1
[17:48:25.084] <TB1> INFO: Expecting 4201600 events.
[17:48:57.481] <TB1> INFO: 727965 events read in total (31805ms).
[17:49:28.849] <TB1> INFO: 1451800 events read in total (63173ms).
[17:50:00.489] <TB1> INFO: 2171030 events read in total (94813ms).
[17:50:31.585] <TB1> INFO: 2886190 events read in total (125909ms).
[17:51:02.673] <TB1> INFO: 3600270 events read in total (156997ms).
[17:51:28.987] <TB1> INFO: 4201600 events read in total (183311ms).
[17:51:29.083] <TB1> INFO: Test took 184287ms.
[17:51:55.703] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[17:51:55.716] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:51:55.716] <TB1> INFO: run 1 of 1
[17:51:55.968] <TB1> INFO: Expecting 4160000 events.
[17:52:28.158] <TB1> INFO: 730700 events read in total (31598ms).
[17:53:00.219] <TB1> INFO: 1457020 events read in total (63659ms).
[17:53:31.672] <TB1> INFO: 2178860 events read in total (95112ms).
[17:54:03.053] <TB1> INFO: 2896445 events read in total (126493ms).
[17:54:34.718] <TB1> INFO: 3612865 events read in total (158158ms).
[17:54:58.709] <TB1> INFO: 4160000 events read in total (182149ms).
[17:54:58.816] <TB1> INFO: Test took 183099ms.
[17:55:26.897] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[17:55:26.911] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:55:26.911] <TB1> INFO: run 1 of 1
[17:55:27.236] <TB1> INFO: Expecting 4160000 events.
[17:56:00.098] <TB1> INFO: 730755 events read in total (32270ms).
[17:56:31.342] <TB1> INFO: 1457295 events read in total (63514ms).
[17:57:02.158] <TB1> INFO: 2179275 events read in total (94330ms).
[17:57:33.374] <TB1> INFO: 2896965 events read in total (125546ms).
[17:58:05.280] <TB1> INFO: 3613695 events read in total (157452ms).
[17:58:29.086] <TB1> INFO: 4160000 events read in total (181258ms).
[17:58:29.191] <TB1> INFO: Test took 182280ms.
[17:58:55.431] <TB1> INFO: PixTestTrim80::trimBitTest() done
[17:58:55.432] <TB1> INFO: PixTestTrim80::doTest() done, duration: 2355 seconds
[17:58:56.136] <TB1> INFO: enter test to run
[17:58:56.136] <TB1> INFO: test: exit no parameter change
[17:58:56.331] <TB1> QUIET: Connection to board 154 closed.
[17:58:56.332] <TB1> INFO: pXar: this is the end, my friend