[15:55:28.504] <TB0> INFO: *** Welcome to pxar ***
[15:55:28.504] <TB0> INFO: *** Today: 2016/11/07
[15:55:28.510] <TB0> INFO: *** Version: c8ba-dirty
[15:55:28.510] <TB0> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C15.dat
[15:55:28.511] <TB0> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[15:55:28.511] <TB0> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//defaultMaskFile.dat
[15:55:28.511] <TB0> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters_C15.dat
[15:55:28.571] <TB0> INFO: clk: 4
[15:55:28.571] <TB0> INFO: ctr: 4
[15:55:28.571] <TB0> INFO: sda: 19
[15:55:28.571] <TB0> INFO: tin: 9
[15:55:28.571] <TB0> INFO: level: 15
[15:55:28.571] <TB0> INFO: triggerdelay: 0
[15:55:28.571] <TB0> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[15:55:28.571] <TB0> INFO: Log level: INFO
[15:55:28.580] <TB0> INFO: Found DTB DTB_WRQ4OZ
[15:55:28.590] <TB0> QUIET: Connection to board DTB_WRQ4OZ opened.
[15:55:28.592] <TB0> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 71
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WRQ4OZ
MAC address: 40D855118047
Hostname: pixelDTB071
Comment:
------------------------------------------------------
[15:55:28.594] <TB0> INFO: RPC call hashes of host and DTB match: 486171790
[15:55:30.082] <TB0> INFO: DUT info:
[15:55:30.082] <TB0> INFO: The DUT currently contains the following objects:
[15:55:30.082] <TB0> INFO: 4 TBM Cores tbm10c (4 ON)
[15:55:30.082] <TB0> INFO: TBM Core alpha (0): 7 registers set
[15:55:30.082] <TB0> INFO: TBM Core beta (1): 7 registers set
[15:55:30.082] <TB0> INFO: TBM Core alpha (2): 7 registers set
[15:55:30.082] <TB0> INFO: TBM Core beta (3): 7 registers set
[15:55:30.082] <TB0> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[15:55:30.082] <TB0> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.082] <TB0> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.082] <TB0> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.082] <TB0> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.082] <TB0> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.083] <TB0> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.083] <TB0> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.083] <TB0> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.083] <TB0> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.083] <TB0> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.083] <TB0> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.083] <TB0> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.083] <TB0> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.083] <TB0> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.083] <TB0> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.083] <TB0> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[15:55:30.484] <TB0> INFO: enter 'restricted' command line mode
[15:55:30.484] <TB0> INFO: enter test to run
[15:55:30.484] <TB0> INFO: test: pretest no parameter change
[15:55:30.484] <TB0> INFO: running: pretest
[15:55:30.488] <TB0> INFO: ######################################################################
[15:55:30.488] <TB0> INFO: PixTestPretest::doTest()
[15:55:30.488] <TB0> INFO: ######################################################################
[15:55:30.489] <TB0> INFO: ----------------------------------------------------------------------
[15:55:30.489] <TB0> INFO: PixTestPretest::programROC()
[15:55:30.489] <TB0> INFO: ----------------------------------------------------------------------
[15:55:48.503] <TB0> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[15:55:48.503] <TB0> INFO: IA differences per ROC: 18.5 20.9 20.1 21.7 20.1 20.1 18.5 20.1 17.7 17.7 19.3 19.3 19.3 17.7 20.1 18.5
[15:55:48.558] <TB0> INFO: ----------------------------------------------------------------------
[15:55:48.559] <TB0> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[15:55:48.559] <TB0> INFO: ----------------------------------------------------------------------
[15:55:55.240] <TB0> INFO: PixTestPretest::setVana() done, Module Ia 377.8 mA = 23.6125 mA/ROC
[15:55:55.240] <TB0> INFO: i(loss) [mA/ROC]: 19.3 18.5 19.3 19.3 18.5 19.3 19.3 19.3 19.3 19.3 19.3 18.5 19.3 19.3 18.5 19.3
[15:55:55.270] <TB0> INFO: ----------------------------------------------------------------------
[15:55:55.270] <TB0> INFO: PixTestPretest::findTiming()
[15:55:55.270] <TB0> INFO: ----------------------------------------------------------------------
[15:55:55.270] <TB0> INFO: PixTestCmd::init()

[15:56:27.385] <TB0> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[15:56:27.385] <TB0> INFO: (success/tries = 100/100), width = 3
[15:56:28.887] <TB0> INFO: ----------------------------------------------------------------------
[15:56:28.887] <TB0> INFO: PixTestPretest::findWorkingPixel()
[15:56:28.887] <TB0> INFO: ----------------------------------------------------------------------
[15:56:28.983] <TB0> INFO: Expecting 231680 events.
[15:56:39.047] <TB0> INFO: 231680 events read in total (9473ms).
[15:56:39.055] <TB0> INFO: Test took 10162ms.
[15:56:39.301] <TB0> INFO: Found working pixel in all ROCs: col/row = 12/22
[15:56:39.339] <TB0> INFO: ----------------------------------------------------------------------
[15:56:39.339] <TB0> INFO: PixTestPretest::setVthrCompCalDel()
[15:56:39.339] <TB0> INFO: ----------------------------------------------------------------------
[15:56:39.434] <TB0> INFO: Expecting 231680 events.
[15:56:49.540] <TB0> INFO: 231680 events read in total (9514ms).
[15:56:49.550] <TB0> INFO: Test took 10206ms.
[15:56:49.800] <TB0> INFO: PixTestPretest::setVthrCompCalDel() done
[15:56:49.800] <TB0> INFO: CalDel: 93 90 79 96 88 101 95 95 77 91 77 101 88 101 96 90
[15:56:49.800] <TB0> INFO: VthrComp: 51 51 51 51 51 51 51 51 55 51 51 51 51 51 51 53
[15:56:49.802] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C0.dat
[15:56:49.802] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C1.dat
[15:56:49.802] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C2.dat
[15:56:49.802] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C3.dat
[15:56:49.802] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C4.dat
[15:56:49.803] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C5.dat
[15:56:49.803] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C6.dat
[15:56:49.803] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C7.dat
[15:56:49.803] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C8.dat
[15:56:49.803] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C9.dat
[15:56:49.803] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C10.dat
[15:56:49.803] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C11.dat
[15:56:49.803] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C12.dat
[15:56:49.803] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C13.dat
[15:56:49.803] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C14.dat
[15:56:49.803] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters_C15.dat
[15:56:49.803] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[15:56:49.803] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[15:56:49.803] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[15:56:49.803] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[15:56:49.804] <TB0> INFO: PixTestPretest::doTest() done, duration: 79 seconds
[15:56:49.855] <TB0> INFO: enter test to run
[15:56:49.855] <TB0> INFO: test: fulltest no parameter change
[15:56:49.855] <TB0> INFO: running: fulltest
[15:56:49.855] <TB0> INFO: ######################################################################
[15:56:49.855] <TB0> INFO: PixTestFullTest::doTest()
[15:56:49.855] <TB0> INFO: ######################################################################
[15:56:49.857] <TB0> INFO: ######################################################################
[15:56:49.857] <TB0> INFO: PixTestAlive::doTest()
[15:56:49.857] <TB0> INFO: ######################################################################
[15:56:49.858] <TB0> INFO: ----------------------------------------------------------------------
[15:56:49.858] <TB0> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:56:49.858] <TB0> INFO: ----------------------------------------------------------------------
[15:56:50.096] <TB0> INFO: Expecting 41600 events.
[15:56:53.599] <TB0> INFO: 41600 events read in total (2912ms).
[15:56:53.600] <TB0> INFO: Test took 3740ms.
[15:56:53.826] <TB0> INFO: PixTestAlive::aliveTest() done
[15:56:53.826] <TB0> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:56:53.828] <TB0> INFO: ----------------------------------------------------------------------
[15:56:53.828] <TB0> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:56:53.828] <TB0> INFO: ----------------------------------------------------------------------
[15:56:54.087] <TB0> INFO: Expecting 41600 events.
[15:56:57.070] <TB0> INFO: 41600 events read in total (2391ms).
[15:56:57.071] <TB0> INFO: Test took 3241ms.
[15:56:57.071] <TB0> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[15:56:57.310] <TB0> INFO: PixTestAlive::maskTest() done
[15:56:57.310] <TB0> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:56:57.312] <TB0> INFO: ----------------------------------------------------------------------
[15:56:57.312] <TB0> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:56:57.312] <TB0> INFO: ----------------------------------------------------------------------
[15:56:57.558] <TB0> INFO: Expecting 41600 events.
[15:57:01.137] <TB0> INFO: 41600 events read in total (2987ms).
[15:57:01.137] <TB0> INFO: Test took 3823ms.
[15:57:01.368] <TB0> INFO: PixTestAlive::addressDecodingTest() done
[15:57:01.368] <TB0> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:57:01.368] <TB0> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[15:57:01.368] <TB0> INFO: Decoding statistics:
[15:57:01.368] <TB0> INFO: General information:
[15:57:01.368] <TB0> INFO: 16bit words read: 0
[15:57:01.368] <TB0> INFO: valid events total: 0
[15:57:01.368] <TB0> INFO: empty events: 0
[15:57:01.368] <TB0> INFO: valid events with pixels: 0
[15:57:01.369] <TB0> INFO: valid pixel hits: 0
[15:57:01.369] <TB0> INFO: Event errors: 0
[15:57:01.369] <TB0> INFO: start marker: 0
[15:57:01.369] <TB0> INFO: stop marker: 0
[15:57:01.369] <TB0> INFO: overflow: 0
[15:57:01.369] <TB0> INFO: invalid 5bit words: 0
[15:57:01.369] <TB0> INFO: invalid XOR eye diagram: 0
[15:57:01.369] <TB0> INFO: frame (failed synchr.): 0
[15:57:01.369] <TB0> INFO: idle data (no TBM trl): 0
[15:57:01.369] <TB0> INFO: no data (only TBM hdr): 0
[15:57:01.369] <TB0> INFO: TBM errors: 0
[15:57:01.369] <TB0> INFO: flawed TBM headers: 0
[15:57:01.369] <TB0> INFO: flawed TBM trailers: 0
[15:57:01.369] <TB0> INFO: event ID mismatches: 0
[15:57:01.369] <TB0> INFO: ROC errors: 0
[15:57:01.369] <TB0> INFO: missing ROC header(s): 0
[15:57:01.369] <TB0> INFO: misplaced readback start: 0
[15:57:01.369] <TB0> INFO: Pixel decoding errors: 0
[15:57:01.369] <TB0> INFO: pixel data incomplete: 0
[15:57:01.369] <TB0> INFO: pixel address: 0
[15:57:01.369] <TB0> INFO: pulse height fill bit: 0
[15:57:01.369] <TB0> INFO: buffer corruption: 0
[15:57:01.377] <TB0> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[15:57:01.378] <TB0> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[15:57:01.378] <TB0> INFO: ######################################################################
[15:57:01.378] <TB0> INFO: PixTestReadback::doTest()
[15:57:01.378] <TB0> INFO: ######################################################################
[15:57:01.378] <TB0> INFO: ----------------------------------------------------------------------
[15:57:01.378] <TB0> INFO: PixTestReadback::CalibrateVd()
[15:57:01.378] <TB0> INFO: ----------------------------------------------------------------------
[15:57:11.342] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat
[15:57:11.342] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C1.dat
[15:57:11.342] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C2.dat
[15:57:11.342] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C3.dat
[15:57:11.342] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C4.dat
[15:57:11.342] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C5.dat
[15:57:11.342] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C6.dat
[15:57:11.342] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C7.dat
[15:57:11.342] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C8.dat
[15:57:11.342] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C9.dat
[15:57:11.342] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C10.dat
[15:57:11.342] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C11.dat
[15:57:11.342] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C12.dat
[15:57:11.343] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C13.dat
[15:57:11.343] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C14.dat
[15:57:11.343] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[15:57:11.374] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[15:57:11.374] <TB0> INFO: ----------------------------------------------------------------------
[15:57:11.374] <TB0> INFO: PixTestReadback::CalibrateVa()
[15:57:11.374] <TB0> INFO: ----------------------------------------------------------------------
[15:57:21.289] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat
[15:57:21.289] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C1.dat
[15:57:21.289] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C2.dat
[15:57:21.290] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C3.dat
[15:57:21.290] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C4.dat
[15:57:21.290] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C5.dat
[15:57:21.290] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C6.dat
[15:57:21.290] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C7.dat
[15:57:21.290] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C8.dat
[15:57:21.290] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C9.dat
[15:57:21.290] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C10.dat
[15:57:21.290] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C11.dat
[15:57:21.290] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C12.dat
[15:57:21.290] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C13.dat
[15:57:21.290] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C14.dat
[15:57:21.290] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[15:57:21.316] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[15:57:21.316] <TB0> INFO: ----------------------------------------------------------------------
[15:57:21.316] <TB0> INFO: PixTestReadback::readbackVbg()
[15:57:21.316] <TB0> INFO: ----------------------------------------------------------------------
[15:57:28.980] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[15:57:28.980] <TB0> INFO: ----------------------------------------------------------------------
[15:57:28.980] <TB0> INFO: PixTestReadback::getCalibratedVbg()
[15:57:28.980] <TB0> INFO: ----------------------------------------------------------------------
[15:57:28.980] <TB0> INFO: Vbg will be calibrated using Vd calibration
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 155.2calibrated Vbg = 1.18636 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 151.6calibrated Vbg = 1.18683 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 157.9calibrated Vbg = 1.18093 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 154.8calibrated Vbg = 1.18263 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 150.6calibrated Vbg = 1.18683 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 160.8calibrated Vbg = 1.18606 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 161.7calibrated Vbg = 1.18777 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 159.3calibrated Vbg = 1.1886 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 156calibrated Vbg = 1.17654 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 159.2calibrated Vbg = 1.17814 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 152.7calibrated Vbg = 1.1738 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 157.1calibrated Vbg = 1.17269 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 158calibrated Vbg = 1.17626 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 149.9calibrated Vbg = 1.18409 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 160.1calibrated Vbg = 1.1858 :::*/*/*/*/
[15:57:28.980] <TB0> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 152.3calibrated Vbg = 1.18539 :::*/*/*/*/
[15:57:28.983] <TB0> INFO: ----------------------------------------------------------------------
[15:57:28.983] <TB0> INFO: PixTestReadback::CalibrateIa()
[15:57:28.983] <TB0> INFO: ----------------------------------------------------------------------
[16:00:09.829] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C0.dat
[16:00:09.829] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C1.dat
[16:00:09.829] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C2.dat
[16:00:09.830] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C3.dat
[16:00:09.830] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C4.dat
[16:00:09.830] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C5.dat
[16:00:09.830] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C6.dat
[16:00:09.830] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C7.dat
[16:00:09.830] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C8.dat
[16:00:09.830] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C9.dat
[16:00:09.830] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C10.dat
[16:00:09.830] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C11.dat
[16:00:09.830] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C12.dat
[16:00:09.830] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C13.dat
[16:00:09.830] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C14.dat
[16:00:09.830] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//readbackCal_C15.dat
[16:00:09.861] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[16:00:09.864] <TB0> INFO: PixTestReadback::doTest() done
[16:00:09.864] <TB0> INFO: Decoding statistics:
[16:00:09.864] <TB0> INFO: General information:
[16:00:09.864] <TB0> INFO: 16bit words read: 1536
[16:00:09.864] <TB0> INFO: valid events total: 256
[16:00:09.864] <TB0> INFO: empty events: 256
[16:00:09.864] <TB0> INFO: valid events with pixels: 0
[16:00:09.864] <TB0> INFO: valid pixel hits: 0
[16:00:09.864] <TB0> INFO: Event errors: 0
[16:00:09.864] <TB0> INFO: start marker: 0
[16:00:09.864] <TB0> INFO: stop marker: 0
[16:00:09.864] <TB0> INFO: overflow: 0
[16:00:09.864] <TB0> INFO: invalid 5bit words: 0
[16:00:09.864] <TB0> INFO: invalid XOR eye diagram: 0
[16:00:09.864] <TB0> INFO: frame (failed synchr.): 0
[16:00:09.865] <TB0> INFO: idle data (no TBM trl): 0
[16:00:09.865] <TB0> INFO: no data (only TBM hdr): 0
[16:00:09.865] <TB0> INFO: TBM errors: 0
[16:00:09.865] <TB0> INFO: flawed TBM headers: 0
[16:00:09.865] <TB0> INFO: flawed TBM trailers: 0
[16:00:09.865] <TB0> INFO: event ID mismatches: 0
[16:00:09.865] <TB0> INFO: ROC errors: 0
[16:00:09.865] <TB0> INFO: missing ROC header(s): 0
[16:00:09.865] <TB0> INFO: misplaced readback start: 0
[16:00:09.865] <TB0> INFO: Pixel decoding errors: 0
[16:00:09.865] <TB0> INFO: pixel data incomplete: 0
[16:00:09.865] <TB0> INFO: pixel address: 0
[16:00:09.865] <TB0> INFO: pulse height fill bit: 0
[16:00:09.865] <TB0> INFO: buffer corruption: 0
[16:00:09.915] <TB0> INFO: ######################################################################
[16:00:09.915] <TB0> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[16:00:09.915] <TB0> INFO: ######################################################################
[16:00:09.918] <TB0> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[16:00:10.380] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[16:00:10.380] <TB0> INFO: run 1 of 1
[16:00:10.616] <TB0> INFO: Expecting 3120000 events.
[16:00:43.150] <TB0> INFO: 661960 events read in total (31942ms).











[16:01:13.239] <TB0> INFO: 1323100 events read in total (62031ms).











[16:01:43.897] <TB0> INFO: 1980720 events read in total (92689ms).











[16:02:14.350] <TB0> INFO: 2637465 events read in total (123142ms).











[16:02:36.483] <TB0> INFO: 3120000 events read in total (145275ms).
[16:02:36.588] <TB0> INFO: Test took 146209ms.
[16:03:00.347] <TB0> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 170 seconds
[16:03:00.347] <TB0> INFO: number of dead bumps (per ROC): 1 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0
[16:03:00.347] <TB0> INFO: separation cut (per ROC): 103 102 105 109 101 108 106 101 106 105 103 90 102 102 103 106
[16:03:00.348] <TB0> INFO: Decoding statistics:
[16:03:00.348] <TB0> INFO: General information:
[16:03:00.348] <TB0> INFO: 16bit words read: 0
[16:03:00.348] <TB0> INFO: valid events total: 0
[16:03:00.348] <TB0> INFO: empty events: 0
[16:03:00.348] <TB0> INFO: valid events with pixels: 0
[16:03:00.348] <TB0> INFO: valid pixel hits: 0
[16:03:00.348] <TB0> INFO: Event errors: 0
[16:03:00.348] <TB0> INFO: start marker: 0
[16:03:00.348] <TB0> INFO: stop marker: 0
[16:03:00.348] <TB0> INFO: overflow: 0
[16:03:00.348] <TB0> INFO: invalid 5bit words: 0
[16:03:00.348] <TB0> INFO: invalid XOR eye diagram: 0
[16:03:00.348] <TB0> INFO: frame (failed synchr.): 0
[16:03:00.348] <TB0> INFO: idle data (no TBM trl): 0
[16:03:00.348] <TB0> INFO: no data (only TBM hdr): 0
[16:03:00.348] <TB0> INFO: TBM errors: 0
[16:03:00.348] <TB0> INFO: flawed TBM headers: 0
[16:03:00.348] <TB0> INFO: flawed TBM trailers: 0
[16:03:00.348] <TB0> INFO: event ID mismatches: 0
[16:03:00.348] <TB0> INFO: ROC errors: 0
[16:03:00.348] <TB0> INFO: missing ROC header(s): 0
[16:03:00.348] <TB0> INFO: misplaced readback start: 0
[16:03:00.348] <TB0> INFO: Pixel decoding errors: 0
[16:03:00.348] <TB0> INFO: pixel data incomplete: 0
[16:03:00.348] <TB0> INFO: pixel address: 0
[16:03:00.348] <TB0> INFO: pulse height fill bit: 0
[16:03:00.348] <TB0> INFO: buffer corruption: 0
[16:03:00.386] <TB0> INFO: ######################################################################
[16:03:00.386] <TB0> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:03:00.386] <TB0> INFO: ######################################################################
[16:03:00.386] <TB0> INFO: ----------------------------------------------------------------------
[16:03:00.386] <TB0> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:03:00.386] <TB0> INFO: ----------------------------------------------------------------------
[16:03:00.386] <TB0> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[16:03:00.399] <TB0> INFO: dacScan split into 1 runs with ntrig = 50
[16:03:00.399] <TB0> INFO: run 1 of 1
[16:03:00.638] <TB0> INFO: Expecting 36608000 events.
[16:03:24.779] <TB0> INFO: 693850 events read in total (23549ms).
[16:03:47.972] <TB0> INFO: 1372000 events read in total (46742ms).
[16:04:11.134] <TB0> INFO: 2052000 events read in total (69904ms).
[16:04:34.665] <TB0> INFO: 2732000 events read in total (93435ms).
[16:04:58.029] <TB0> INFO: 3411350 events read in total (116799ms).
[16:05:21.157] <TB0> INFO: 4090100 events read in total (139927ms).
[16:05:44.732] <TB0> INFO: 4769250 events read in total (163502ms).
[16:06:08.228] <TB0> INFO: 5448850 events read in total (186998ms).
[16:06:31.721] <TB0> INFO: 6127900 events read in total (210491ms).
[16:06:55.240] <TB0> INFO: 6807000 events read in total (234010ms).
[16:07:18.566] <TB0> INFO: 7486200 events read in total (257336ms).
[16:07:41.966] <TB0> INFO: 8164800 events read in total (280736ms).
[16:08:05.378] <TB0> INFO: 8843650 events read in total (304148ms).
[16:08:28.873] <TB0> INFO: 9522550 events read in total (327643ms).
[16:08:52.432] <TB0> INFO: 10201000 events read in total (351202ms).
[16:09:15.853] <TB0> INFO: 10876850 events read in total (374623ms).
[16:09:39.557] <TB0> INFO: 11554450 events read in total (398327ms).
[16:10:03.332] <TB0> INFO: 12233300 events read in total (422102ms).
[16:10:26.809] <TB0> INFO: 12910600 events read in total (445579ms).
[16:10:50.413] <TB0> INFO: 13586700 events read in total (469183ms).
[16:11:13.772] <TB0> INFO: 14262500 events read in total (492542ms).
[16:11:37.134] <TB0> INFO: 14938650 events read in total (515904ms).
[16:12:00.928] <TB0> INFO: 15613100 events read in total (539698ms).
[16:12:24.469] <TB0> INFO: 16288000 events read in total (563239ms).
[16:12:47.724] <TB0> INFO: 16963350 events read in total (586494ms).
[16:13:11.205] <TB0> INFO: 17639150 events read in total (609975ms).
[16:13:34.373] <TB0> INFO: 18312700 events read in total (633143ms).
[16:13:57.387] <TB0> INFO: 18984850 events read in total (656157ms).
[16:14:20.640] <TB0> INFO: 19656450 events read in total (679410ms).
[16:14:44.152] <TB0> INFO: 20326550 events read in total (702922ms).
[16:15:07.432] <TB0> INFO: 20997100 events read in total (726202ms).
[16:15:30.609] <TB0> INFO: 21666500 events read in total (749379ms).
[16:15:53.810] <TB0> INFO: 22334500 events read in total (772580ms).
[16:16:16.951] <TB0> INFO: 23004350 events read in total (795721ms).
[16:16:39.759] <TB0> INFO: 23675400 events read in total (818529ms).
[16:17:02.874] <TB0> INFO: 24345700 events read in total (841644ms).
[16:17:25.947] <TB0> INFO: 25015900 events read in total (864717ms).
[16:17:48.929] <TB0> INFO: 25685850 events read in total (887699ms).
[16:18:12.013] <TB0> INFO: 26354700 events read in total (910783ms).
[16:18:35.289] <TB0> INFO: 27023900 events read in total (934059ms).
[16:18:58.461] <TB0> INFO: 27693850 events read in total (957231ms).
[16:19:21.284] <TB0> INFO: 28362950 events read in total (980054ms).
[16:19:44.273] <TB0> INFO: 29033700 events read in total (1003043ms).
[16:20:07.155] <TB0> INFO: 29701800 events read in total (1025925ms).
[16:20:30.178] <TB0> INFO: 30370050 events read in total (1048948ms).
[16:20:53.118] <TB0> INFO: 31039150 events read in total (1071888ms).
[16:21:16.074] <TB0> INFO: 31708500 events read in total (1094844ms).
[16:21:39.229] <TB0> INFO: 32377650 events read in total (1117999ms).
[16:22:02.297] <TB0> INFO: 33048900 events read in total (1141067ms).
[16:22:25.527] <TB0> INFO: 33719500 events read in total (1164297ms).
[16:22:48.751] <TB0> INFO: 34388650 events read in total (1187521ms).
[16:23:11.847] <TB0> INFO: 35058550 events read in total (1210617ms).
[16:23:34.893] <TB0> INFO: 35727500 events read in total (1233663ms).
[16:23:58.127] <TB0> INFO: 36407100 events read in total (1256897ms).
[16:24:05.052] <TB0> INFO: 36608000 events read in total (1263822ms).
[16:24:05.127] <TB0> INFO: Test took 1264727ms.
[16:24:05.673] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:07.711] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:09.730] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:11.187] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:12.656] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:14.176] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:15.767] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:17.244] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:18.751] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:20.280] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:21.807] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:23.393] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:25.510] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:27.436] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:29.313] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:31.233] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[16:24:33.284] <TB0> INFO: PixTestScurves::scurves() done
[16:24:33.284] <TB0> INFO: Vcal mean: 118.38 116.84 120.62 135.83 114.12 129.75 125.67 116.87 131.03 121.98 120.40 116.44 117.60 119.74 118.38 131.28
[16:24:33.284] <TB0> INFO: Vcal RMS: 5.77 5.44 5.79 5.82 5.13 6.13 6.27 5.32 6.55 6.45 5.48 5.05 5.18 6.24 5.67 6.92
[16:24:33.284] <TB0> INFO: PixTestScurves::fullTest() done, duration: 1292 seconds
[16:24:33.284] <TB0> INFO: Decoding statistics:
[16:24:33.284] <TB0> INFO: General information:
[16:24:33.284] <TB0> INFO: 16bit words read: 0
[16:24:33.284] <TB0> INFO: valid events total: 0
[16:24:33.284] <TB0> INFO: empty events: 0
[16:24:33.284] <TB0> INFO: valid events with pixels: 0
[16:24:33.284] <TB0> INFO: valid pixel hits: 0
[16:24:33.284] <TB0> INFO: Event errors: 0
[16:24:33.284] <TB0> INFO: start marker: 0
[16:24:33.284] <TB0> INFO: stop marker: 0
[16:24:33.284] <TB0> INFO: overflow: 0
[16:24:33.284] <TB0> INFO: invalid 5bit words: 0
[16:24:33.284] <TB0> INFO: invalid XOR eye diagram: 0
[16:24:33.284] <TB0> INFO: frame (failed synchr.): 0
[16:24:33.284] <TB0> INFO: idle data (no TBM trl): 0
[16:24:33.284] <TB0> INFO: no data (only TBM hdr): 0
[16:24:33.284] <TB0> INFO: TBM errors: 0
[16:24:33.284] <TB0> INFO: flawed TBM headers: 0
[16:24:33.284] <TB0> INFO: flawed TBM trailers: 0
[16:24:33.284] <TB0> INFO: event ID mismatches: 0
[16:24:33.284] <TB0> INFO: ROC errors: 0
[16:24:33.284] <TB0> INFO: missing ROC header(s): 0
[16:24:33.285] <TB0> INFO: misplaced readback start: 0
[16:24:33.285] <TB0> INFO: Pixel decoding errors: 0
[16:24:33.285] <TB0> INFO: pixel data incomplete: 0
[16:24:33.285] <TB0> INFO: pixel address: 0
[16:24:33.285] <TB0> INFO: pulse height fill bit: 0
[16:24:33.285] <TB0> INFO: buffer corruption: 0
[16:24:33.372] <TB0> INFO: ######################################################################
[16:24:33.372] <TB0> INFO: PixTestTrim::doTest()
[16:24:33.372] <TB0> INFO: ######################################################################
[16:24:33.373] <TB0> INFO: ----------------------------------------------------------------------
[16:24:33.373] <TB0> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[16:24:33.374] <TB0> INFO: ----------------------------------------------------------------------
[16:24:33.430] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[16:24:33.430] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:24:33.444] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[16:24:33.444] <TB0> INFO: run 1 of 1
[16:24:33.726] <TB0> INFO: Expecting 5025280 events.
[16:25:05.507] <TB0> INFO: 830128 events read in total (31184ms).
[16:25:36.737] <TB0> INFO: 1657248 events read in total (62414ms).
[16:26:07.725] <TB0> INFO: 2481776 events read in total (93402ms).
[16:26:38.814] <TB0> INFO: 3302096 events read in total (124491ms).
[16:27:09.739] <TB0> INFO: 4119040 events read in total (155417ms).
[16:27:39.711] <TB0> INFO: 4934736 events read in total (185388ms).
[16:27:43.339] <TB0> INFO: 5025280 events read in total (189016ms).
[16:27:43.406] <TB0> INFO: Test took 189961ms.
[16:28:00.057] <TB0> INFO: ROC 0 VthrComp = 116
[16:28:00.057] <TB0> INFO: ROC 1 VthrComp = 119
[16:28:00.057] <TB0> INFO: ROC 2 VthrComp = 125
[16:28:00.057] <TB0> INFO: ROC 3 VthrComp = 134
[16:28:00.057] <TB0> INFO: ROC 4 VthrComp = 114
[16:28:00.057] <TB0> INFO: ROC 5 VthrComp = 130
[16:28:00.057] <TB0> INFO: ROC 6 VthrComp = 123
[16:28:00.057] <TB0> INFO: ROC 7 VthrComp = 114
[16:28:00.057] <TB0> INFO: ROC 8 VthrComp = 126
[16:28:00.058] <TB0> INFO: ROC 9 VthrComp = 120
[16:28:00.058] <TB0> INFO: ROC 10 VthrComp = 125
[16:28:00.058] <TB0> INFO: ROC 11 VthrComp = 109
[16:28:00.058] <TB0> INFO: ROC 12 VthrComp = 121
[16:28:00.058] <TB0> INFO: ROC 13 VthrComp = 117
[16:28:00.058] <TB0> INFO: ROC 14 VthrComp = 115
[16:28:00.058] <TB0> INFO: ROC 15 VthrComp = 125
[16:28:00.298] <TB0> INFO: Expecting 41600 events.
[16:28:03.852] <TB0> INFO: 41600 events read in total (2961ms).
[16:28:03.853] <TB0> INFO: Test took 3793ms.
[16:28:03.863] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[16:28:03.863] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:28:03.874] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[16:28:03.874] <TB0> INFO: run 1 of 1
[16:28:04.152] <TB0> INFO: Expecting 5025280 events.
[16:28:31.468] <TB0> INFO: 591544 events read in total (26724ms).
[16:28:57.394] <TB0> INFO: 1182008 events read in total (52650ms).
[16:29:23.571] <TB0> INFO: 1772560 events read in total (78827ms).
[16:29:49.651] <TB0> INFO: 2362496 events read in total (104907ms).
[16:30:15.791] <TB0> INFO: 2950488 events read in total (131047ms).
[16:30:41.836] <TB0> INFO: 3536560 events read in total (157092ms).
[16:31:07.522] <TB0> INFO: 4122328 events read in total (182778ms).
[16:31:33.240] <TB0> INFO: 4708280 events read in total (208496ms).
[16:31:47.233] <TB0> INFO: 5025280 events read in total (222489ms).
[16:31:47.316] <TB0> INFO: Test took 223442ms.
[16:32:12.783] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 60.8511 for pixel 10/9 mean/min/max = 46.6922/32.4595/60.9249
[16:32:12.783] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 58.2703 for pixel 6/2 mean/min/max = 45.2322/32.1318/58.3326
[16:32:12.784] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 58.7457 for pixel 26/17 mean/min/max = 45.3592/31.8348/58.8837
[16:32:12.784] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 64.5626 for pixel 6/40 mean/min/max = 50.3019/35.8517/64.7521
[16:32:12.785] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 59.8985 for pixel 1/7 mean/min/max = 46.5238/33.0468/60.0008
[16:32:12.785] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 59.6551 for pixel 15/1 mean/min/max = 45.7737/31.8902/59.6573
[16:32:12.786] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 61.0814 for pixel 5/2 mean/min/max = 46.7/32.1458/61.2542
[16:32:12.786] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 60.8446 for pixel 10/7 mean/min/max = 47.2052/33.1557/61.2547
[16:32:12.787] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 67.0926 for pixel 16/60 mean/min/max = 50.1352/32.9955/67.2749
[16:32:12.787] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 62.5868 for pixel 11/9 mean/min/max = 47.6252/32.3242/62.9262
[16:32:12.787] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 58.5263 for pixel 46/12 mean/min/max = 45.1145/31.6896/58.5395
[16:32:12.788] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 64.1281 for pixel 39/19 mean/min/max = 49.8555/35.458/64.2531
[16:32:12.788] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 59.2188 for pixel 38/2 mean/min/max = 46.2592/33.1852/59.3331
[16:32:12.788] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 60.1511 for pixel 0/11 mean/min/max = 46.2842/32.1996/60.3688
[16:32:12.789] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 60.757 for pixel 10/69 mean/min/max = 46.5287/32.2309/60.8264
[16:32:12.789] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 65.4885 for pixel 2/1 mean/min/max = 48.9071/31.7647/66.0494
[16:32:12.789] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:32:12.879] <TB0> INFO: Expecting 411648 events.
[16:32:22.280] <TB0> INFO: 411648 events read in total (8808ms).
[16:32:22.287] <TB0> INFO: Expecting 411648 events.
[16:32:31.476] <TB0> INFO: 411648 events read in total (8786ms).
[16:32:31.488] <TB0> INFO: Expecting 411648 events.
[16:32:40.880] <TB0> INFO: 411648 events read in total (8988ms).
[16:32:40.894] <TB0> INFO: Expecting 411648 events.
[16:32:50.313] <TB0> INFO: 411648 events read in total (9016ms).
[16:32:50.335] <TB0> INFO: Expecting 411648 events.
[16:32:59.700] <TB0> INFO: 411648 events read in total (8961ms).
[16:32:59.723] <TB0> INFO: Expecting 411648 events.
[16:33:09.082] <TB0> INFO: 411648 events read in total (8956ms).
[16:33:09.104] <TB0> INFO: Expecting 411648 events.
[16:33:18.401] <TB0> INFO: 411648 events read in total (8894ms).
[16:33:18.424] <TB0> INFO: Expecting 411648 events.
[16:33:27.780] <TB0> INFO: 411648 events read in total (8953ms).
[16:33:27.806] <TB0> INFO: Expecting 411648 events.
[16:33:37.220] <TB0> INFO: 411648 events read in total (9011ms).
[16:33:37.250] <TB0> INFO: Expecting 411648 events.
[16:33:46.668] <TB0> INFO: 411648 events read in total (9014ms).
[16:33:46.700] <TB0> INFO: Expecting 411648 events.
[16:33:56.052] <TB0> INFO: 411648 events read in total (8948ms).
[16:33:56.087] <TB0> INFO: Expecting 411648 events.
[16:34:05.484] <TB0> INFO: 411648 events read in total (8994ms).
[16:34:05.521] <TB0> INFO: Expecting 411648 events.
[16:34:14.785] <TB0> INFO: 411648 events read in total (8861ms).
[16:34:14.833] <TB0> INFO: Expecting 411648 events.
[16:34:24.089] <TB0> INFO: 411648 events read in total (8853ms).
[16:34:24.137] <TB0> INFO: Expecting 411648 events.
[16:34:33.456] <TB0> INFO: 411648 events read in total (8916ms).
[16:34:33.555] <TB0> INFO: Expecting 411648 events.
[16:34:42.786] <TB0> INFO: 411648 events read in total (8828ms).
[16:34:42.872] <TB0> INFO: Test took 150083ms.
[16:34:43.571] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[16:34:43.585] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[16:34:43.585] <TB0> INFO: run 1 of 1
[16:34:43.824] <TB0> INFO: Expecting 5025280 events.
[16:35:10.622] <TB0> INFO: 589992 events read in total (26207ms).
[16:35:36.983] <TB0> INFO: 1179360 events read in total (52568ms).
[16:36:03.602] <TB0> INFO: 1769976 events read in total (79187ms).
[16:36:30.007] <TB0> INFO: 2358552 events read in total (105592ms).
[16:36:56.486] <TB0> INFO: 2947624 events read in total (132071ms).
[16:37:23.403] <TB0> INFO: 3537448 events read in total (158988ms).
[16:37:49.785] <TB0> INFO: 4126624 events read in total (185370ms).
[16:38:15.913] <TB0> INFO: 4715184 events read in total (211498ms).
[16:38:30.348] <TB0> INFO: 5025280 events read in total (225933ms).
[16:38:30.485] <TB0> INFO: Test took 226900ms.
[16:38:54.700] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 6.133592 .. 144.769648
[16:38:54.942] <TB0> INFO: Expecting 208000 events.
[16:39:04.783] <TB0> INFO: 208000 events read in total (9249ms).
[16:39:04.785] <TB0> INFO: Test took 10083ms.
[16:39:04.866] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 6 .. 154 (-1/-1) hits flags = 528 (plus default)
[16:39:04.880] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[16:39:04.880] <TB0> INFO: run 1 of 1
[16:39:05.209] <TB0> INFO: Expecting 4958720 events.
[16:39:31.824] <TB0> INFO: 578944 events read in total (26024ms).
[16:39:58.270] <TB0> INFO: 1157816 events read in total (52471ms).
[16:40:24.157] <TB0> INFO: 1736240 events read in total (78358ms).
[16:40:50.370] <TB0> INFO: 2314400 events read in total (104570ms).
[16:41:16.501] <TB0> INFO: 2892984 events read in total (130701ms).
[16:41:42.614] <TB0> INFO: 3471016 events read in total (156814ms).
[16:42:08.935] <TB0> INFO: 4048696 events read in total (183135ms).
[16:42:34.702] <TB0> INFO: 4626496 events read in total (208902ms).
[16:42:50.068] <TB0> INFO: 4958720 events read in total (224268ms).
[16:42:50.170] <TB0> INFO: Test took 225288ms.
[16:43:16.687] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 26.701958 .. 45.486395
[16:43:16.991] <TB0> INFO: Expecting 208000 events.
[16:43:26.829] <TB0> INFO: 208000 events read in total (9246ms).
[16:43:26.831] <TB0> INFO: Test took 10142ms.
[16:43:26.880] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 55 (-1/-1) hits flags = 528 (plus default)
[16:43:26.894] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[16:43:26.894] <TB0> INFO: run 1 of 1
[16:43:27.172] <TB0> INFO: Expecting 1331200 events.
[16:43:56.078] <TB0> INFO: 666072 events read in total (28315ms).
[16:44:24.479] <TB0> INFO: 1329496 events read in total (56717ms).
[16:44:24.975] <TB0> INFO: 1331200 events read in total (57212ms).
[16:44:25.018] <TB0> INFO: Test took 58125ms.
[16:44:39.921] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 27.444396 .. 49.360843
[16:44:40.159] <TB0> INFO: Expecting 208000 events.
[16:44:50.385] <TB0> INFO: 208000 events read in total (9634ms).
[16:44:50.386] <TB0> INFO: Test took 10464ms.
[16:44:50.436] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 59 (-1/-1) hits flags = 528 (plus default)
[16:44:50.449] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[16:44:50.449] <TB0> INFO: run 1 of 1
[16:44:50.727] <TB0> INFO: Expecting 1431040 events.
[16:45:19.074] <TB0> INFO: 646888 events read in total (27755ms).
[16:45:46.720] <TB0> INFO: 1292896 events read in total (55402ms).
[16:45:53.147] <TB0> INFO: 1431040 events read in total (61829ms).
[16:45:53.182] <TB0> INFO: Test took 62734ms.
[16:46:08.241] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 27.053186 .. 50.470964
[16:46:08.495] <TB0> INFO: Expecting 208000 events.
[16:46:18.224] <TB0> INFO: 208000 events read in total (9138ms).
[16:46:18.225] <TB0> INFO: Test took 9983ms.
[16:46:18.274] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 17 .. 60 (-1/-1) hits flags = 528 (plus default)
[16:46:18.287] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[16:46:18.287] <TB0> INFO: run 1 of 1
[16:46:18.565] <TB0> INFO: Expecting 1464320 events.
[16:46:46.648] <TB0> INFO: 642408 events read in total (27491ms).
[16:47:14.339] <TB0> INFO: 1284800 events read in total (55182ms).
[16:47:22.449] <TB0> INFO: 1464320 events read in total (63292ms).
[16:47:22.481] <TB0> INFO: Test took 64195ms.
[16:47:37.053] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[16:47:37.053] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[16:47:37.067] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[16:47:37.067] <TB0> INFO: run 1 of 1
[16:47:37.304] <TB0> INFO: Expecting 1364480 events.
[16:48:05.838] <TB0> INFO: 668768 events read in total (27942ms).
[16:48:33.720] <TB0> INFO: 1336200 events read in total (55825ms).
[16:48:35.318] <TB0> INFO: 1364480 events read in total (57422ms).
[16:48:35.350] <TB0> INFO: Test took 58283ms.
[16:48:48.375] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C0.dat
[16:48:48.375] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C1.dat
[16:48:48.375] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C2.dat
[16:48:48.375] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C3.dat
[16:48:48.375] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C4.dat
[16:48:48.375] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C5.dat
[16:48:48.375] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C6.dat
[16:48:48.376] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C7.dat
[16:48:48.376] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C8.dat
[16:48:48.376] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C9.dat
[16:48:48.376] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C10.dat
[16:48:48.376] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C11.dat
[16:48:48.376] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C12.dat
[16:48:48.376] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C13.dat
[16:48:48.376] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C14.dat
[16:48:48.376] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C15.dat
[16:48:48.376] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C0.dat
[16:48:48.383] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C1.dat
[16:48:48.388] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C2.dat
[16:48:48.392] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C3.dat
[16:48:48.397] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C4.dat
[16:48:48.402] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C5.dat
[16:48:48.407] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C6.dat
[16:48:48.411] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C7.dat
[16:48:48.416] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C8.dat
[16:48:48.421] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C9.dat
[16:48:48.425] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C10.dat
[16:48:48.430] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C11.dat
[16:48:48.435] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C12.dat
[16:48:48.440] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C13.dat
[16:48:48.445] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C14.dat
[16:48:48.450] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters35_C15.dat
[16:48:48.454] <TB0> INFO: PixTestTrim::trimTest() done
[16:48:48.454] <TB0> INFO: vtrim: 112 121 132 143 112 120 117 127 138 143 128 128 131 104 113 142
[16:48:48.454] <TB0> INFO: vthrcomp: 116 119 125 134 114 130 123 114 126 120 125 109 121 117 115 125
[16:48:48.454] <TB0> INFO: vcal mean: 35.06 34.96 34.99 35.22 35.18 34.93 35.03 35.05 36.31 35.09 35.00 35.29 34.91 34.94 35.05 35.73
[16:48:48.454] <TB0> INFO: vcal RMS: 1.04 1.03 1.03 1.34 1.17 1.03 1.17 1.18 2.49 1.22 1.12 1.48 0.99 1.14 1.01 1.96
[16:48:48.454] <TB0> INFO: bits mean: 9.21 9.69 9.72 8.40 9.14 9.31 9.22 9.12 9.44 9.35 10.24 8.63 9.23 9.05 9.52 9.27
[16:48:48.454] <TB0> INFO: bits RMS: 2.78 2.69 2.69 2.42 2.77 2.83 2.81 2.71 2.71 2.65 2.47 2.55 2.68 2.88 2.65 2.89
[16:48:48.462] <TB0> INFO: ----------------------------------------------------------------------
[16:48:48.462] <TB0> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[16:48:48.462] <TB0> INFO: ----------------------------------------------------------------------
[16:48:48.465] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[16:48:48.479] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[16:48:48.479] <TB0> INFO: run 1 of 1
[16:48:48.727] <TB0> INFO: Expecting 4160000 events.
[16:49:21.122] <TB0> INFO: 768080 events read in total (31803ms).
[16:49:53.520] <TB0> INFO: 1533220 events read in total (64201ms).
[16:50:25.581] <TB0> INFO: 2292010 events read in total (96262ms).
[16:50:57.607] <TB0> INFO: 3044920 events read in total (128288ms).
[16:51:29.981] <TB0> INFO: 3797965 events read in total (160662ms).
[16:51:46.070] <TB0> INFO: 4160000 events read in total (176751ms).
[16:51:46.167] <TB0> INFO: Test took 177688ms.
[16:52:14.689] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[16:52:14.703] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[16:52:14.703] <TB0> INFO: run 1 of 1
[16:52:14.983] <TB0> INFO: Expecting 4347200 events.
[16:52:47.359] <TB0> INFO: 730240 events read in total (31785ms).
[16:53:18.915] <TB0> INFO: 1458515 events read in total (63341ms).
[16:53:50.407] <TB0> INFO: 2183090 events read in total (94833ms).
[16:54:21.773] <TB0> INFO: 2902695 events read in total (126199ms).
[16:54:53.259] <TB0> INFO: 3621620 events read in total (157685ms).
[16:55:24.856] <TB0> INFO: 4342525 events read in total (189282ms).
[16:55:25.473] <TB0> INFO: 4347200 events read in total (189899ms).
[16:55:25.551] <TB0> INFO: Test took 190848ms.
[16:55:53.558] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[16:55:53.572] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[16:55:53.572] <TB0> INFO: run 1 of 1
[16:55:53.810] <TB0> INFO: Expecting 4305600 events.
[16:56:26.767] <TB0> INFO: 733710 events read in total (32365ms).
[16:56:57.946] <TB0> INFO: 1464880 events read in total (63544ms).
[16:57:29.808] <TB0> INFO: 2192105 events read in total (95406ms).
[16:58:01.804] <TB0> INFO: 2914950 events read in total (127402ms).
[16:58:33.648] <TB0> INFO: 3636385 events read in total (159246ms).
[16:59:03.144] <TB0> INFO: 4305600 events read in total (188742ms).
[16:59:03.258] <TB0> INFO: Test took 189686ms.
[16:59:30.339] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 209 (-1/-1) hits flags = 528 (plus default)
[16:59:30.354] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[16:59:30.354] <TB0> INFO: run 1 of 1
[16:59:30.623] <TB0> INFO: Expecting 4368000 events.
[17:00:03.161] <TB0> INFO: 729895 events read in total (31947ms).
[17:00:34.529] <TB0> INFO: 1457280 events read in total (63315ms).
[17:01:06.316] <TB0> INFO: 2181395 events read in total (95102ms).
[17:01:38.043] <TB0> INFO: 2900565 events read in total (126829ms).
[17:02:09.691] <TB0> INFO: 3618505 events read in total (158477ms).
[17:02:41.206] <TB0> INFO: 4338155 events read in total (189992ms).
[17:02:42.869] <TB0> INFO: 4368000 events read in total (191655ms).
[17:02:42.957] <TB0> INFO: Test took 192603ms.
[17:03:09.683] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[17:03:09.696] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[17:03:09.696] <TB0> INFO: run 1 of 1
[17:03:09.982] <TB0> INFO: Expecting 4305600 events.
[17:03:42.030] <TB0> INFO: 733660 events read in total (31457ms).
[17:04:13.295] <TB0> INFO: 1464700 events read in total (62722ms).
[17:04:44.855] <TB0> INFO: 2192385 events read in total (94282ms).
[17:05:15.991] <TB0> INFO: 2915080 events read in total (125418ms).
[17:05:47.286] <TB0> INFO: 3636115 events read in total (156713ms).
[17:06:16.460] <TB0> INFO: 4305600 events read in total (185887ms).
[17:06:16.589] <TB0> INFO: Test took 186893ms.
[17:06:45.790] <TB0> INFO: PixTestTrim::trimBitTest() done
[17:06:45.792] <TB0> INFO: PixTestTrim::doTest() done, duration: 2532 seconds
[17:06:45.792] <TB0> INFO: Decoding statistics:
[17:06:45.792] <TB0> INFO: General information:
[17:06:45.792] <TB0> INFO: 16bit words read: 0
[17:06:45.792] <TB0> INFO: valid events total: 0
[17:06:45.792] <TB0> INFO: empty events: 0
[17:06:45.792] <TB0> INFO: valid events with pixels: 0
[17:06:45.792] <TB0> INFO: valid pixel hits: 0
[17:06:45.792] <TB0> INFO: Event errors: 0
[17:06:45.792] <TB0> INFO: start marker: 0
[17:06:45.792] <TB0> INFO: stop marker: 0
[17:06:45.792] <TB0> INFO: overflow: 0
[17:06:45.792] <TB0> INFO: invalid 5bit words: 0
[17:06:45.792] <TB0> INFO: invalid XOR eye diagram: 0
[17:06:45.792] <TB0> INFO: frame (failed synchr.): 0
[17:06:45.792] <TB0> INFO: idle data (no TBM trl): 0
[17:06:45.792] <TB0> INFO: no data (only TBM hdr): 0
[17:06:45.792] <TB0> INFO: TBM errors: 0
[17:06:45.792] <TB0> INFO: flawed TBM headers: 0
[17:06:45.792] <TB0> INFO: flawed TBM trailers: 0
[17:06:45.792] <TB0> INFO: event ID mismatches: 0
[17:06:45.792] <TB0> INFO: ROC errors: 0
[17:06:45.792] <TB0> INFO: missing ROC header(s): 0
[17:06:45.792] <TB0> INFO: misplaced readback start: 0
[17:06:45.792] <TB0> INFO: Pixel decoding errors: 0
[17:06:45.792] <TB0> INFO: pixel data incomplete: 0
[17:06:45.792] <TB0> INFO: pixel address: 0
[17:06:45.792] <TB0> INFO: pulse height fill bit: 0
[17:06:45.792] <TB0> INFO: buffer corruption: 0
[17:06:46.550] <TB0> INFO: ######################################################################
[17:06:46.550] <TB0> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[17:06:46.550] <TB0> INFO: ######################################################################
[17:06:46.789] <TB0> INFO: Expecting 41600 events.
[17:06:50.355] <TB0> INFO: 41600 events read in total (2974ms).
[17:06:50.356] <TB0> INFO: Test took 3805ms.
[17:06:50.831] <TB0> INFO: Expecting 41600 events.
[17:06:54.343] <TB0> INFO: 41600 events read in total (2920ms).
[17:06:54.345] <TB0> INFO: Test took 3786ms.
[17:06:54.634] <TB0> INFO: Expecting 41600 events.
[17:06:58.137] <TB0> INFO: 41600 events read in total (2911ms).
[17:06:58.138] <TB0> INFO: Test took 3768ms.
[17:06:58.428] <TB0> INFO: Expecting 41600 events.
[17:07:02.074] <TB0> INFO: 41600 events read in total (3054ms).
[17:07:02.075] <TB0> INFO: Test took 3912ms.
[17:07:02.365] <TB0> INFO: Expecting 41600 events.
[17:07:05.858] <TB0> INFO: 41600 events read in total (2901ms).
[17:07:05.859] <TB0> INFO: Test took 3760ms.
[17:07:06.149] <TB0> INFO: Expecting 41600 events.
[17:07:09.654] <TB0> INFO: 41600 events read in total (2913ms).
[17:07:09.655] <TB0> INFO: Test took 3772ms.
[17:07:09.944] <TB0> INFO: Expecting 41600 events.
[17:07:13.616] <TB0> INFO: 41600 events read in total (3080ms).
[17:07:13.617] <TB0> INFO: Test took 3938ms.
[17:07:13.908] <TB0> INFO: Expecting 41600 events.
[17:07:17.549] <TB0> INFO: 41600 events read in total (3050ms).
[17:07:17.550] <TB0> INFO: Test took 3908ms.
[17:07:17.846] <TB0> INFO: Expecting 41600 events.
[17:07:21.327] <TB0> INFO: 41600 events read in total (2890ms).
[17:07:21.328] <TB0> INFO: Test took 3753ms.
[17:07:21.619] <TB0> INFO: Expecting 41600 events.
[17:07:25.168] <TB0> INFO: 41600 events read in total (2958ms).
[17:07:25.169] <TB0> INFO: Test took 3815ms.
[17:07:25.458] <TB0> INFO: Expecting 41600 events.
[17:07:29.086] <TB0> INFO: 41600 events read in total (3036ms).
[17:07:29.087] <TB0> INFO: Test took 3894ms.
[17:07:29.376] <TB0> INFO: Expecting 41600 events.
[17:07:32.859] <TB0> INFO: 41600 events read in total (2892ms).
[17:07:32.860] <TB0> INFO: Test took 3749ms.
[17:07:33.151] <TB0> INFO: Expecting 41600 events.
[17:07:36.737] <TB0> INFO: 41600 events read in total (2995ms).
[17:07:36.738] <TB0> INFO: Test took 3852ms.
[17:07:37.048] <TB0> INFO: Expecting 41600 events.
[17:07:40.672] <TB0> INFO: 41600 events read in total (3032ms).
[17:07:40.673] <TB0> INFO: Test took 3911ms.
[17:07:40.965] <TB0> INFO: Expecting 41600 events.
[17:07:44.470] <TB0> INFO: 41600 events read in total (2913ms).
[17:07:44.471] <TB0> INFO: Test took 3771ms.
[17:07:44.760] <TB0> INFO: Expecting 41600 events.
[17:07:48.367] <TB0> INFO: 41600 events read in total (3015ms).
[17:07:48.368] <TB0> INFO: Test took 3873ms.
[17:07:48.659] <TB0> INFO: Expecting 41600 events.
[17:07:52.124] <TB0> INFO: 41600 events read in total (2874ms).
[17:07:52.125] <TB0> INFO: Test took 3731ms.
[17:07:52.415] <TB0> INFO: Expecting 41600 events.
[17:07:55.902] <TB0> INFO: 41600 events read in total (2896ms).
[17:07:55.903] <TB0> INFO: Test took 3753ms.
[17:07:56.194] <TB0> INFO: Expecting 41600 events.
[17:07:59.714] <TB0> INFO: 41600 events read in total (2929ms).
[17:07:59.715] <TB0> INFO: Test took 3787ms.
[17:08:00.004] <TB0> INFO: Expecting 41600 events.
[17:08:03.540] <TB0> INFO: 41600 events read in total (2944ms).
[17:08:03.541] <TB0> INFO: Test took 3802ms.
[17:08:03.835] <TB0> INFO: Expecting 41600 events.
[17:08:07.361] <TB0> INFO: 41600 events read in total (2934ms).
[17:08:07.361] <TB0> INFO: Test took 3791ms.
[17:08:07.652] <TB0> INFO: Expecting 41600 events.
[17:08:11.191] <TB0> INFO: 41600 events read in total (2948ms).
[17:08:11.192] <TB0> INFO: Test took 3806ms.
[17:08:11.482] <TB0> INFO: Expecting 41600 events.
[17:08:15.005] <TB0> INFO: 41600 events read in total (2931ms).
[17:08:15.006] <TB0> INFO: Test took 3789ms.
[17:08:15.296] <TB0> INFO: Expecting 41600 events.
[17:08:18.860] <TB0> INFO: 41600 events read in total (2973ms).
[17:08:18.861] <TB0> INFO: Test took 3830ms.
[17:08:19.150] <TB0> INFO: Expecting 41600 events.
[17:08:22.753] <TB0> INFO: 41600 events read in total (3011ms).
[17:08:22.754] <TB0> INFO: Test took 3868ms.
[17:08:23.044] <TB0> INFO: Expecting 41600 events.
[17:08:26.518] <TB0> INFO: 41600 events read in total (2882ms).
[17:08:26.519] <TB0> INFO: Test took 3740ms.
[17:08:26.814] <TB0> INFO: Expecting 41600 events.
[17:08:30.328] <TB0> INFO: 41600 events read in total (2922ms).
[17:08:30.329] <TB0> INFO: Test took 3780ms.
[17:08:30.619] <TB0> INFO: Expecting 2560 events.
[17:08:31.508] <TB0> INFO: 2560 events read in total (297ms).
[17:08:31.509] <TB0> INFO: Test took 1166ms.
[17:08:31.815] <TB0> INFO: Expecting 2560 events.
[17:08:32.700] <TB0> INFO: 2560 events read in total (293ms).
[17:08:32.700] <TB0> INFO: Test took 1190ms.
[17:08:33.009] <TB0> INFO: Expecting 2560 events.
[17:08:33.892] <TB0> INFO: 2560 events read in total (292ms).
[17:08:33.893] <TB0> INFO: Test took 1192ms.
[17:08:34.200] <TB0> INFO: Expecting 2560 events.
[17:08:35.087] <TB0> INFO: 2560 events read in total (295ms).
[17:08:35.087] <TB0> INFO: Test took 1194ms.
[17:08:35.395] <TB0> INFO: Expecting 2560 events.
[17:08:36.280] <TB0> INFO: 2560 events read in total (293ms).
[17:08:36.280] <TB0> INFO: Test took 1192ms.
[17:08:36.588] <TB0> INFO: Expecting 2560 events.
[17:08:37.481] <TB0> INFO: 2560 events read in total (300ms).
[17:08:37.483] <TB0> INFO: Test took 1202ms.
[17:08:37.788] <TB0> INFO: Expecting 2560 events.
[17:08:38.678] <TB0> INFO: 2560 events read in total (299ms).
[17:08:38.678] <TB0> INFO: Test took 1194ms.
[17:08:38.987] <TB0> INFO: Expecting 2560 events.
[17:08:39.881] <TB0> INFO: 2560 events read in total (302ms).
[17:08:39.881] <TB0> INFO: Test took 1203ms.
[17:08:40.189] <TB0> INFO: Expecting 2560 events.
[17:08:41.079] <TB0> INFO: 2560 events read in total (299ms).
[17:08:41.079] <TB0> INFO: Test took 1196ms.
[17:08:41.386] <TB0> INFO: Expecting 2560 events.
[17:08:42.265] <TB0> INFO: 2560 events read in total (287ms).
[17:08:42.265] <TB0> INFO: Test took 1185ms.
[17:08:42.573] <TB0> INFO: Expecting 2560 events.
[17:08:43.467] <TB0> INFO: 2560 events read in total (302ms).
[17:08:43.467] <TB0> INFO: Test took 1201ms.
[17:08:43.774] <TB0> INFO: Expecting 2560 events.
[17:08:44.662] <TB0> INFO: 2560 events read in total (296ms).
[17:08:44.662] <TB0> INFO: Test took 1194ms.
[17:08:44.969] <TB0> INFO: Expecting 2560 events.
[17:08:45.861] <TB0> INFO: 2560 events read in total (301ms).
[17:08:45.861] <TB0> INFO: Test took 1198ms.
[17:08:46.170] <TB0> INFO: Expecting 2560 events.
[17:08:47.064] <TB0> INFO: 2560 events read in total (302ms).
[17:08:47.064] <TB0> INFO: Test took 1202ms.
[17:08:47.371] <TB0> INFO: Expecting 2560 events.
[17:08:48.259] <TB0> INFO: 2560 events read in total (296ms).
[17:08:48.259] <TB0> INFO: Test took 1194ms.
[17:08:48.567] <TB0> INFO: Expecting 2560 events.
[17:08:49.454] <TB0> INFO: 2560 events read in total (295ms).
[17:08:49.454] <TB0> INFO: Test took 1194ms.
[17:08:49.457] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:08:49.763] <TB0> INFO: Expecting 655360 events.
[17:09:04.349] <TB0> INFO: 655360 events read in total (13995ms).
[17:09:04.364] <TB0> INFO: Expecting 655360 events.
[17:09:19.024] <TB0> INFO: 655360 events read in total (14257ms).
[17:09:19.044] <TB0> INFO: Expecting 655360 events.
[17:09:33.431] <TB0> INFO: 655360 events read in total (13984ms).
[17:09:33.454] <TB0> INFO: Expecting 655360 events.
[17:09:48.096] <TB0> INFO: 655360 events read in total (14239ms).
[17:09:48.125] <TB0> INFO: Expecting 655360 events.
[17:10:02.454] <TB0> INFO: 655360 events read in total (13926ms).
[17:10:02.487] <TB0> INFO: Expecting 655360 events.
[17:10:16.622] <TB0> INFO: 655360 events read in total (13732ms).
[17:10:16.665] <TB0> INFO: Expecting 655360 events.
[17:10:31.109] <TB0> INFO: 655360 events read in total (14041ms).
[17:10:31.187] <TB0> INFO: Expecting 655360 events.
[17:10:45.924] <TB0> INFO: 655360 events read in total (14333ms).
[17:10:45.982] <TB0> INFO: Expecting 655360 events.
[17:11:00.485] <TB0> INFO: 655360 events read in total (14100ms).
[17:11:00.544] <TB0> INFO: Expecting 655360 events.
[17:11:15.091] <TB0> INFO: 655360 events read in total (14144ms).
[17:11:15.146] <TB0> INFO: Expecting 655360 events.
[17:11:29.762] <TB0> INFO: 655360 events read in total (14213ms).
[17:11:29.835] <TB0> INFO: Expecting 655360 events.
[17:11:44.399] <TB0> INFO: 655360 events read in total (14161ms).
[17:11:44.486] <TB0> INFO: Expecting 655360 events.
[17:11:59.094] <TB0> INFO: 655360 events read in total (14205ms).
[17:11:59.179] <TB0> INFO: Expecting 655360 events.
[17:12:13.818] <TB0> INFO: 655360 events read in total (14236ms).
[17:12:13.913] <TB0> INFO: Expecting 655360 events.
[17:12:28.504] <TB0> INFO: 655360 events read in total (14188ms).
[17:12:28.596] <TB0> INFO: Expecting 655360 events.
[17:12:43.218] <TB0> INFO: 655360 events read in total (14219ms).
[17:12:43.338] <TB0> INFO: Test took 233881ms.
[17:12:43.435] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:12:43.692] <TB0> INFO: Expecting 655360 events.
[17:12:58.085] <TB0> INFO: 655360 events read in total (13801ms).
[17:12:58.098] <TB0> INFO: Expecting 655360 events.
[17:13:12.542] <TB0> INFO: 655360 events read in total (14041ms).
[17:13:12.559] <TB0> INFO: Expecting 655360 events.
[17:13:26.995] <TB0> INFO: 655360 events read in total (14033ms).
[17:13:27.015] <TB0> INFO: Expecting 655360 events.
[17:13:41.573] <TB0> INFO: 655360 events read in total (14155ms).
[17:13:41.608] <TB0> INFO: Expecting 655360 events.
[17:13:55.885] <TB0> INFO: 655360 events read in total (13874ms).
[17:13:55.913] <TB0> INFO: Expecting 655360 events.
[17:14:10.523] <TB0> INFO: 655360 events read in total (14207ms).
[17:14:10.558] <TB0> INFO: Expecting 655360 events.
[17:14:25.037] <TB0> INFO: 655360 events read in total (14076ms).
[17:14:25.084] <TB0> INFO: Expecting 655360 events.
[17:14:39.332] <TB0> INFO: 655360 events read in total (13845ms).
[17:14:39.378] <TB0> INFO: Expecting 655360 events.
[17:14:53.770] <TB0> INFO: 655360 events read in total (13989ms).
[17:14:53.818] <TB0> INFO: Expecting 655360 events.
[17:15:08.198] <TB0> INFO: 655360 events read in total (13977ms).
[17:15:08.267] <TB0> INFO: Expecting 655360 events.
[17:15:22.588] <TB0> INFO: 655360 events read in total (13918ms).
[17:15:22.700] <TB0> INFO: Expecting 655360 events.
[17:15:37.107] <TB0> INFO: 655360 events read in total (14004ms).
[17:15:37.200] <TB0> INFO: Expecting 655360 events.
[17:15:51.609] <TB0> INFO: 655360 events read in total (14006ms).
[17:15:51.693] <TB0> INFO: Expecting 655360 events.
[17:16:06.142] <TB0> INFO: 655360 events read in total (14045ms).
[17:16:06.260] <TB0> INFO: Expecting 655360 events.
[17:16:20.940] <TB0> INFO: 655360 events read in total (14277ms).
[17:16:21.036] <TB0> INFO: Expecting 655360 events.
[17:16:35.501] <TB0> INFO: 655360 events read in total (14062ms).
[17:16:35.602] <TB0> INFO: Test took 232167ms.
[17:16:35.775] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:35.781] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:35.787] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[17:16:35.792] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[17:16:35.798] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[17:16:35.804] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:35.809] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:35.815] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[17:16:35.821] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:35.827] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:35.834] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:35.840] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[17:16:35.845] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[17:16:35.851] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[17:16:35.857] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[17:16:35.863] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[17:16:35.870] <TB0> INFO: safety margin for low PH: adding 7, margin is now 27
[17:16:35.875] <TB0> INFO: safety margin for low PH: adding 8, margin is now 28
[17:16:35.881] <TB0> INFO: safety margin for low PH: adding 9, margin is now 29
[17:16:35.887] <TB0> INFO: safety margin for low PH: adding 10, margin is now 30
[17:16:35.893] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:35.899] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:35.904] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[17:16:35.910] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:35.916] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:35.922] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:35.928] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:35.933] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:35.939] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:35.945] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:35.950] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[17:16:35.956] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[17:16:35.962] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[17:16:35.968] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[17:16:35.974] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:35.980] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:35.985] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:35.991] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[17:16:35.997] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[17:16:35.003] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[17:16:36.009] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:36.014] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:36.020] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[17:16:36.026] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[17:16:36.032] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[17:16:36.038] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[17:16:36.046] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[17:16:36.053] <TB0> INFO: safety margin for low PH: adding 7, margin is now 27
[17:16:36.059] <TB0> INFO: safety margin for low PH: adding 8, margin is now 28
[17:16:36.065] <TB0> INFO: safety margin for low PH: adding 9, margin is now 29
[17:16:36.071] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:36.078] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:36.086] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[17:16:36.095] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[17:16:36.103] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:36.112] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:36.153] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C0.dat
[17:16:36.154] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C1.dat
[17:16:36.154] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C2.dat
[17:16:36.154] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C3.dat
[17:16:36.154] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C4.dat
[17:16:36.154] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C5.dat
[17:16:36.154] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C6.dat
[17:16:36.154] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C7.dat
[17:16:36.154] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C8.dat
[17:16:36.154] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C9.dat
[17:16:36.154] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C10.dat
[17:16:36.154] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C11.dat
[17:16:36.155] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C12.dat
[17:16:36.155] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C13.dat
[17:16:36.155] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C14.dat
[17:16:36.155] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters35_C15.dat
[17:16:36.435] <TB0> INFO: Expecting 41600 events.
[17:16:39.606] <TB0> INFO: 41600 events read in total (2579ms).
[17:16:39.607] <TB0> INFO: Test took 3450ms.
[17:16:40.100] <TB0> INFO: Expecting 41600 events.
[17:16:43.143] <TB0> INFO: 41600 events read in total (2451ms).
[17:16:43.144] <TB0> INFO: Test took 3325ms.
[17:16:43.594] <TB0> INFO: Expecting 41600 events.
[17:16:46.763] <TB0> INFO: 41600 events read in total (2577ms).
[17:16:46.764] <TB0> INFO: Test took 3408ms.
[17:16:46.983] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:47.073] <TB0> INFO: Expecting 2560 events.
[17:16:47.966] <TB0> INFO: 2560 events read in total (302ms).
[17:16:47.966] <TB0> INFO: Test took 983ms.
[17:16:47.968] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:48.275] <TB0> INFO: Expecting 2560 events.
[17:16:49.170] <TB0> INFO: 2560 events read in total (303ms).
[17:16:49.170] <TB0> INFO: Test took 1202ms.
[17:16:49.173] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:49.479] <TB0> INFO: Expecting 2560 events.
[17:16:50.369] <TB0> INFO: 2560 events read in total (299ms).
[17:16:50.370] <TB0> INFO: Test took 1197ms.
[17:16:50.373] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:50.679] <TB0> INFO: Expecting 2560 events.
[17:16:51.565] <TB0> INFO: 2560 events read in total (294ms).
[17:16:51.566] <TB0> INFO: Test took 1193ms.
[17:16:51.571] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:51.874] <TB0> INFO: Expecting 2560 events.
[17:16:52.766] <TB0> INFO: 2560 events read in total (301ms).
[17:16:52.766] <TB0> INFO: Test took 1195ms.
[17:16:52.769] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:53.074] <TB0> INFO: Expecting 2560 events.
[17:16:53.969] <TB0> INFO: 2560 events read in total (304ms).
[17:16:53.969] <TB0> INFO: Test took 1200ms.
[17:16:53.973] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:54.277] <TB0> INFO: Expecting 2560 events.
[17:16:55.167] <TB0> INFO: 2560 events read in total (298ms).
[17:16:55.168] <TB0> INFO: Test took 1196ms.
[17:16:55.169] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:55.476] <TB0> INFO: Expecting 2560 events.
[17:16:56.358] <TB0> INFO: 2560 events read in total (290ms).
[17:16:56.359] <TB0> INFO: Test took 1190ms.
[17:16:56.362] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:56.667] <TB0> INFO: Expecting 2560 events.
[17:16:57.552] <TB0> INFO: 2560 events read in total (293ms).
[17:16:57.552] <TB0> INFO: Test took 1190ms.
[17:16:57.555] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:57.860] <TB0> INFO: Expecting 2560 events.
[17:16:58.741] <TB0> INFO: 2560 events read in total (289ms).
[17:16:58.742] <TB0> INFO: Test took 1187ms.
[17:16:58.747] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:59.050] <TB0> INFO: Expecting 2560 events.
[17:16:59.935] <TB0> INFO: 2560 events read in total (293ms).
[17:16:59.935] <TB0> INFO: Test took 1188ms.
[17:16:59.938] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:00.244] <TB0> INFO: Expecting 2560 events.
[17:17:01.129] <TB0> INFO: 2560 events read in total (294ms).
[17:17:01.130] <TB0> INFO: Test took 1192ms.
[17:17:01.133] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:01.438] <TB0> INFO: Expecting 2560 events.
[17:17:02.324] <TB0> INFO: 2560 events read in total (294ms).
[17:17:02.325] <TB0> INFO: Test took 1192ms.
[17:17:02.328] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:02.632] <TB0> INFO: Expecting 2560 events.
[17:17:03.518] <TB0> INFO: 2560 events read in total (294ms).
[17:17:03.518] <TB0> INFO: Test took 1190ms.
[17:17:03.522] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:03.826] <TB0> INFO: Expecting 2560 events.
[17:17:04.707] <TB0> INFO: 2560 events read in total (289ms).
[17:17:04.707] <TB0> INFO: Test took 1185ms.
[17:17:04.711] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:05.017] <TB0> INFO: Expecting 2560 events.
[17:17:05.911] <TB0> INFO: 2560 events read in total (302ms).
[17:17:05.912] <TB0> INFO: Test took 1201ms.
[17:17:05.915] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:06.221] <TB0> INFO: Expecting 2560 events.
[17:17:07.110] <TB0> INFO: 2560 events read in total (297ms).
[17:17:07.110] <TB0> INFO: Test took 1195ms.
[17:17:07.113] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:07.418] <TB0> INFO: Expecting 2560 events.
[17:17:08.307] <TB0> INFO: 2560 events read in total (297ms).
[17:17:08.308] <TB0> INFO: Test took 1195ms.
[17:17:08.310] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:08.617] <TB0> INFO: Expecting 2560 events.
[17:17:09.507] <TB0> INFO: 2560 events read in total (298ms).
[17:17:09.508] <TB0> INFO: Test took 1198ms.
[17:17:09.512] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:09.816] <TB0> INFO: Expecting 2560 events.
[17:17:10.705] <TB0> INFO: 2560 events read in total (297ms).
[17:17:10.706] <TB0> INFO: Test took 1195ms.
[17:17:10.708] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:11.015] <TB0> INFO: Expecting 2560 events.
[17:17:11.901] <TB0> INFO: 2560 events read in total (295ms).
[17:17:11.902] <TB0> INFO: Test took 1195ms.
[17:17:11.904] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:12.210] <TB0> INFO: Expecting 2560 events.
[17:17:13.091] <TB0> INFO: 2560 events read in total (289ms).
[17:17:13.091] <TB0> INFO: Test took 1187ms.
[17:17:13.093] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:13.400] <TB0> INFO: Expecting 2560 events.
[17:17:14.284] <TB0> INFO: 2560 events read in total (292ms).
[17:17:14.285] <TB0> INFO: Test took 1192ms.
[17:17:14.289] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:14.593] <TB0> INFO: Expecting 2560 events.
[17:17:15.482] <TB0> INFO: 2560 events read in total (297ms).
[17:17:15.482] <TB0> INFO: Test took 1194ms.
[17:17:15.485] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:15.790] <TB0> INFO: Expecting 2560 events.
[17:17:16.683] <TB0> INFO: 2560 events read in total (301ms).
[17:17:16.683] <TB0> INFO: Test took 1199ms.
[17:17:16.686] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:16.990] <TB0> INFO: Expecting 2560 events.
[17:17:17.884] <TB0> INFO: 2560 events read in total (302ms).
[17:17:17.885] <TB0> INFO: Test took 1199ms.
[17:17:17.888] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:18.192] <TB0> INFO: Expecting 2560 events.
[17:17:19.084] <TB0> INFO: 2560 events read in total (300ms).
[17:17:19.084] <TB0> INFO: Test took 1196ms.
[17:17:19.087] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:19.393] <TB0> INFO: Expecting 2560 events.
[17:17:20.287] <TB0> INFO: 2560 events read in total (303ms).
[17:17:20.287] <TB0> INFO: Test took 1200ms.
[17:17:20.290] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:20.597] <TB0> INFO: Expecting 2560 events.
[17:17:21.485] <TB0> INFO: 2560 events read in total (296ms).
[17:17:21.485] <TB0> INFO: Test took 1196ms.
[17:17:21.488] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:21.791] <TB0> INFO: Expecting 2560 events.
[17:17:22.688] <TB0> INFO: 2560 events read in total (305ms).
[17:17:22.688] <TB0> INFO: Test took 1200ms.
[17:17:22.692] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:22.996] <TB0> INFO: Expecting 2560 events.
[17:17:23.886] <TB0> INFO: 2560 events read in total (297ms).
[17:17:23.886] <TB0> INFO: Test took 1194ms.
[17:17:23.888] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:24.195] <TB0> INFO: Expecting 2560 events.
[17:17:25.086] <TB0> INFO: 2560 events read in total (299ms).
[17:17:25.087] <TB0> INFO: Test took 1199ms.
[17:17:25.563] <TB0> INFO: PixTestPhOptimization::doTest() done, duration: 639 seconds
[17:17:25.564] <TB0> INFO: PH scale (per ROC): 46 42 47 40 47 37 32 50 31 58 42 36 32 38 35 45
[17:17:25.564] <TB0> INFO: PH offset (per ROC): 114 101 98 112 108 103 96 119 100 126 106 106 93 112 102 97
[17:17:25.572] <TB0> INFO: Decoding statistics:
[17:17:25.572] <TB0> INFO: General information:
[17:17:25.572] <TB0> INFO: 16bit words read: 127860
[17:17:25.572] <TB0> INFO: valid events total: 20480
[17:17:25.572] <TB0> INFO: empty events: 17990
[17:17:25.572] <TB0> INFO: valid events with pixels: 2490
[17:17:25.572] <TB0> INFO: valid pixel hits: 2490
[17:17:25.572] <TB0> INFO: Event errors: 0
[17:17:25.572] <TB0> INFO: start marker: 0
[17:17:25.572] <TB0> INFO: stop marker: 0
[17:17:25.572] <TB0> INFO: overflow: 0
[17:17:25.572] <TB0> INFO: invalid 5bit words: 0
[17:17:25.572] <TB0> INFO: invalid XOR eye diagram: 0
[17:17:25.572] <TB0> INFO: frame (failed synchr.): 0
[17:17:25.572] <TB0> INFO: idle data (no TBM trl): 0
[17:17:25.572] <TB0> INFO: no data (only TBM hdr): 0
[17:17:25.572] <TB0> INFO: TBM errors: 0
[17:17:25.572] <TB0> INFO: flawed TBM headers: 0
[17:17:25.573] <TB0> INFO: flawed TBM trailers: 0
[17:17:25.573] <TB0> INFO: event ID mismatches: 0
[17:17:25.573] <TB0> INFO: ROC errors: 0
[17:17:25.573] <TB0> INFO: missing ROC header(s): 0
[17:17:25.573] <TB0> INFO: misplaced readback start: 0
[17:17:25.573] <TB0> INFO: Pixel decoding errors: 0
[17:17:25.573] <TB0> INFO: pixel data incomplete: 0
[17:17:25.573] <TB0> INFO: pixel address: 0
[17:17:25.573] <TB0> INFO: pulse height fill bit: 0
[17:17:25.573] <TB0> INFO: buffer corruption: 0
[17:17:25.736] <TB0> INFO: ######################################################################
[17:17:25.736] <TB0> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[17:17:25.736] <TB0> INFO: ######################################################################
[17:17:25.752] <TB0> INFO: scanning low vcal = 10
[17:17:25.992] <TB0> INFO: Expecting 41600 events.
[17:17:29.576] <TB0> INFO: 41600 events read in total (2992ms).
[17:17:29.577] <TB0> INFO: Test took 3825ms.
[17:17:29.578] <TB0> INFO: scanning low vcal = 20
[17:17:29.874] <TB0> INFO: Expecting 41600 events.
[17:17:33.494] <TB0> INFO: 41600 events read in total (3028ms).
[17:17:33.495] <TB0> INFO: Test took 3916ms.
[17:17:33.496] <TB0> INFO: scanning low vcal = 30
[17:17:33.788] <TB0> INFO: Expecting 41600 events.
[17:17:37.474] <TB0> INFO: 41600 events read in total (3094ms).
[17:17:37.475] <TB0> INFO: Test took 3978ms.
[17:17:37.477] <TB0> INFO: scanning low vcal = 40
[17:17:37.755] <TB0> INFO: Expecting 41600 events.
[17:17:41.723] <TB0> INFO: 41600 events read in total (3376ms).
[17:17:41.724] <TB0> INFO: Test took 4246ms.
[17:17:41.728] <TB0> INFO: scanning low vcal = 50
[17:17:42.007] <TB0> INFO: Expecting 41600 events.
[17:17:46.032] <TB0> INFO: 41600 events read in total (3433ms).
[17:17:46.033] <TB0> INFO: Test took 4305ms.
[17:17:46.037] <TB0> INFO: scanning low vcal = 60
[17:17:46.313] <TB0> INFO: Expecting 41600 events.
[17:17:50.297] <TB0> INFO: 41600 events read in total (3392ms).
[17:17:50.298] <TB0> INFO: Test took 4261ms.
[17:17:50.302] <TB0> INFO: scanning low vcal = 70
[17:17:50.578] <TB0> INFO: Expecting 41600 events.
[17:17:54.597] <TB0> INFO: 41600 events read in total (3427ms).
[17:17:54.598] <TB0> INFO: Test took 4296ms.
[17:17:54.600] <TB0> INFO: scanning low vcal = 80
[17:17:54.878] <TB0> INFO: Expecting 41600 events.
[17:17:58.846] <TB0> INFO: 41600 events read in total (3376ms).
[17:17:58.847] <TB0> INFO: Test took 4246ms.
[17:17:58.850] <TB0> INFO: scanning low vcal = 90
[17:17:59.127] <TB0> INFO: Expecting 41600 events.
[17:18:03.114] <TB0> INFO: 41600 events read in total (3395ms).
[17:18:03.115] <TB0> INFO: Test took 4265ms.
[17:18:03.119] <TB0> INFO: scanning low vcal = 100
[17:18:03.395] <TB0> INFO: Expecting 41600 events.
[17:18:07.413] <TB0> INFO: 41600 events read in total (3426ms).
[17:18:07.414] <TB0> INFO: Test took 4295ms.
[17:18:07.417] <TB0> INFO: scanning low vcal = 110
[17:18:07.694] <TB0> INFO: Expecting 41600 events.
[17:18:11.701] <TB0> INFO: 41600 events read in total (3415ms).
[17:18:11.702] <TB0> INFO: Test took 4285ms.
[17:18:11.705] <TB0> INFO: scanning low vcal = 120
[17:18:11.982] <TB0> INFO: Expecting 41600 events.
[17:18:15.988] <TB0> INFO: 41600 events read in total (3415ms).
[17:18:15.989] <TB0> INFO: Test took 4284ms.
[17:18:15.992] <TB0> INFO: scanning low vcal = 130
[17:18:16.275] <TB0> INFO: Expecting 41600 events.
[17:18:20.297] <TB0> INFO: 41600 events read in total (3430ms).
[17:18:20.297] <TB0> INFO: Test took 4304ms.
[17:18:20.301] <TB0> INFO: scanning low vcal = 140
[17:18:20.578] <TB0> INFO: Expecting 41600 events.
[17:18:24.604] <TB0> INFO: 41600 events read in total (3435ms).
[17:18:24.605] <TB0> INFO: Test took 4304ms.
[17:18:24.608] <TB0> INFO: scanning low vcal = 150
[17:18:24.886] <TB0> INFO: Expecting 41600 events.
[17:18:28.881] <TB0> INFO: 41600 events read in total (3403ms).
[17:18:28.881] <TB0> INFO: Test took 4273ms.
[17:18:28.885] <TB0> INFO: scanning low vcal = 160
[17:18:29.167] <TB0> INFO: Expecting 41600 events.
[17:18:33.140] <TB0> INFO: 41600 events read in total (3381ms).
[17:18:33.141] <TB0> INFO: Test took 4256ms.
[17:18:33.145] <TB0> INFO: scanning low vcal = 170
[17:18:33.422] <TB0> INFO: Expecting 41600 events.
[17:18:37.431] <TB0> INFO: 41600 events read in total (3417ms).
[17:18:37.432] <TB0> INFO: Test took 4287ms.
[17:18:37.437] <TB0> INFO: scanning low vcal = 180
[17:18:37.712] <TB0> INFO: Expecting 41600 events.
[17:18:41.681] <TB0> INFO: 41600 events read in total (3377ms).
[17:18:41.682] <TB0> INFO: Test took 4245ms.
[17:18:41.685] <TB0> INFO: scanning low vcal = 190
[17:18:41.962] <TB0> INFO: Expecting 41600 events.
[17:18:45.936] <TB0> INFO: 41600 events read in total (3382ms).
[17:18:45.937] <TB0> INFO: Test took 4252ms.
[17:18:45.940] <TB0> INFO: scanning low vcal = 200
[17:18:46.217] <TB0> INFO: Expecting 41600 events.
[17:18:50.230] <TB0> INFO: 41600 events read in total (3421ms).
[17:18:50.230] <TB0> INFO: Test took 4289ms.
[17:18:50.234] <TB0> INFO: scanning low vcal = 210
[17:18:50.511] <TB0> INFO: Expecting 41600 events.
[17:18:54.505] <TB0> INFO: 41600 events read in total (3402ms).
[17:18:54.505] <TB0> INFO: Test took 4271ms.
[17:18:54.509] <TB0> INFO: scanning low vcal = 220
[17:18:54.786] <TB0> INFO: Expecting 41600 events.
[17:18:58.784] <TB0> INFO: 41600 events read in total (3407ms).
[17:18:58.785] <TB0> INFO: Test took 4276ms.
[17:18:58.788] <TB0> INFO: scanning low vcal = 230
[17:18:59.065] <TB0> INFO: Expecting 41600 events.
[17:19:03.053] <TB0> INFO: 41600 events read in total (3396ms).
[17:19:03.054] <TB0> INFO: Test took 4266ms.
[17:19:03.058] <TB0> INFO: scanning low vcal = 240
[17:19:03.334] <TB0> INFO: Expecting 41600 events.
[17:19:07.286] <TB0> INFO: 41600 events read in total (3360ms).
[17:19:07.286] <TB0> INFO: Test took 4228ms.
[17:19:07.289] <TB0> INFO: scanning low vcal = 250
[17:19:07.566] <TB0> INFO: Expecting 41600 events.
[17:19:11.525] <TB0> INFO: 41600 events read in total (3368ms).
[17:19:11.526] <TB0> INFO: Test took 4236ms.
[17:19:11.531] <TB0> INFO: scanning high vcal = 30 (= 210 in low range)
[17:19:11.807] <TB0> INFO: Expecting 41600 events.
[17:19:15.774] <TB0> INFO: 41600 events read in total (3376ms).
[17:19:15.775] <TB0> INFO: Test took 4244ms.
[17:19:15.779] <TB0> INFO: scanning high vcal = 50 (= 350 in low range)
[17:19:16.055] <TB0> INFO: Expecting 41600 events.
[17:19:20.017] <TB0> INFO: 41600 events read in total (3371ms).
[17:19:20.018] <TB0> INFO: Test took 4239ms.
[17:19:20.021] <TB0> INFO: scanning high vcal = 70 (= 490 in low range)
[17:19:20.298] <TB0> INFO: Expecting 41600 events.
[17:19:24.230] <TB0> INFO: 41600 events read in total (3341ms).
[17:19:24.231] <TB0> INFO: Test took 4209ms.
[17:19:24.234] <TB0> INFO: scanning high vcal = 90 (= 630 in low range)
[17:19:24.510] <TB0> INFO: Expecting 41600 events.
[17:19:28.460] <TB0> INFO: 41600 events read in total (3359ms).
[17:19:28.462] <TB0> INFO: Test took 4228ms.
[17:19:28.465] <TB0> INFO: scanning high vcal = 200 (= 1400 in low range)
[17:19:28.742] <TB0> INFO: Expecting 41600 events.
[17:19:32.713] <TB0> INFO: 41600 events read in total (3380ms).
[17:19:32.714] <TB0> INFO: Test took 4249ms.
[17:19:33.134] <TB0> INFO: PixTestGainPedestal::measure() done
[17:20:11.448] <TB0> INFO: PixTestGainPedestal::fit() done
[17:20:11.448] <TB0> INFO: non-linearity mean: 0.945 0.932 0.941 0.950 0.971 0.920 0.913 0.985 0.984 0.986 0.949 0.937 0.957 0.937 0.923 0.968
[17:20:11.448] <TB0> INFO: non-linearity RMS: 0.098 0.140 0.116 0.037 0.028 0.127 0.135 0.003 0.171 0.003 0.054 0.152 0.187 0.114 0.138 0.024
[17:20:11.448] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[17:20:11.462] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[17:20:11.475] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[17:20:11.489] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[17:20:11.502] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[17:20:11.516] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[17:20:11.529] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[17:20:11.543] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[17:20:11.556] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[17:20:11.570] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[17:20:11.583] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[17:20:11.597] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[17:20:11.611] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[17:20:11.624] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[17:20:11.638] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[17:20:11.651] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[17:20:11.664] <TB0> INFO: PixTestGainPedestal::fullTest() done, duration: 165 seconds
[17:20:11.664] <TB0> INFO: Decoding statistics:
[17:20:11.664] <TB0> INFO: General information:
[17:20:11.664] <TB0> INFO: 16bit words read: 3280230
[17:20:11.664] <TB0> INFO: valid events total: 332800
[17:20:11.664] <TB0> INFO: empty events: 505
[17:20:11.664] <TB0> INFO: valid events with pixels: 332295
[17:20:11.664] <TB0> INFO: valid pixel hits: 641715
[17:20:11.664] <TB0> INFO: Event errors: 0
[17:20:11.664] <TB0> INFO: start marker: 0
[17:20:11.664] <TB0> INFO: stop marker: 0
[17:20:11.664] <TB0> INFO: overflow: 0
[17:20:11.664] <TB0> INFO: invalid 5bit words: 0
[17:20:11.664] <TB0> INFO: invalid XOR eye diagram: 0
[17:20:11.664] <TB0> INFO: frame (failed synchr.): 0
[17:20:11.664] <TB0> INFO: idle data (no TBM trl): 0
[17:20:11.664] <TB0> INFO: no data (only TBM hdr): 0
[17:20:11.664] <TB0> INFO: TBM errors: 0
[17:20:11.664] <TB0> INFO: flawed TBM headers: 0
[17:20:11.664] <TB0> INFO: flawed TBM trailers: 0
[17:20:11.664] <TB0> INFO: event ID mismatches: 0
[17:20:11.664] <TB0> INFO: ROC errors: 0
[17:20:11.664] <TB0> INFO: missing ROC header(s): 0
[17:20:11.664] <TB0> INFO: misplaced readback start: 0
[17:20:11.664] <TB0> INFO: Pixel decoding errors: 0
[17:20:11.664] <TB0> INFO: pixel data incomplete: 0
[17:20:11.664] <TB0> INFO: pixel address: 0
[17:20:11.664] <TB0> INFO: pulse height fill bit: 0
[17:20:11.664] <TB0> INFO: buffer corruption: 0
[17:20:11.683] <TB0> INFO: Decoding statistics:
[17:20:11.683] <TB0> INFO: General information:
[17:20:11.683] <TB0> INFO: 16bit words read: 3409626
[17:20:11.683] <TB0> INFO: valid events total: 353536
[17:20:11.683] <TB0> INFO: empty events: 18751
[17:20:11.683] <TB0> INFO: valid events with pixels: 334785
[17:20:11.683] <TB0> INFO: valid pixel hits: 644205
[17:20:11.683] <TB0> INFO: Event errors: 0
[17:20:11.683] <TB0> INFO: start marker: 0
[17:20:11.683] <TB0> INFO: stop marker: 0
[17:20:11.683] <TB0> INFO: overflow: 0
[17:20:11.683] <TB0> INFO: invalid 5bit words: 0
[17:20:11.683] <TB0> INFO: invalid XOR eye diagram: 0
[17:20:11.683] <TB0> INFO: frame (failed synchr.): 0
[17:20:11.683] <TB0> INFO: idle data (no TBM trl): 0
[17:20:11.683] <TB0> INFO: no data (only TBM hdr): 0
[17:20:11.683] <TB0> INFO: TBM errors: 0
[17:20:11.683] <TB0> INFO: flawed TBM headers: 0
[17:20:11.683] <TB0> INFO: flawed TBM trailers: 0
[17:20:11.683] <TB0> INFO: event ID mismatches: 0
[17:20:11.683] <TB0> INFO: ROC errors: 0
[17:20:11.683] <TB0> INFO: missing ROC header(s): 0
[17:20:11.683] <TB0> INFO: misplaced readback start: 0
[17:20:11.683] <TB0> INFO: Pixel decoding errors: 0
[17:20:11.683] <TB0> INFO: pixel data incomplete: 0
[17:20:11.683] <TB0> INFO: pixel address: 0
[17:20:11.683] <TB0> INFO: pulse height fill bit: 0
[17:20:11.683] <TB0> INFO: buffer corruption: 0
[17:20:11.683] <TB0> INFO: enter test to run
[17:20:11.683] <TB0> INFO: test: trim80 no parameter change
[17:20:11.683] <TB0> INFO: running: trim80
[17:20:11.685] <TB0> INFO: ######################################################################
[17:20:11.685] <TB0> INFO: PixTestTrim80::doTest()
[17:20:11.685] <TB0> INFO: ######################################################################
[17:20:11.686] <TB0> INFO: ----------------------------------------------------------------------
[17:20:11.686] <TB0> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[17:20:11.686] <TB0> INFO: ----------------------------------------------------------------------
[17:20:11.729] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[17:20:11.730] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:20:11.742] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[17:20:11.742] <TB0> INFO: run 1 of 1
[17:20:11.978] <TB0> INFO: Expecting 5025280 events.
[17:20:41.060] <TB0> INFO: 686776 events read in total (28491ms).
[17:21:08.405] <TB0> INFO: 1370456 events read in total (55836ms).
[17:21:35.929] <TB0> INFO: 2051088 events read in total (83360ms).
[17:22:03.632] <TB0> INFO: 2730936 events read in total (111063ms).
[17:22:31.144] <TB0> INFO: 3410640 events read in total (138575ms).
[17:22:58.518] <TB0> INFO: 4089392 events read in total (165949ms).
[17:23:26.581] <TB0> INFO: 4768112 events read in total (194012ms).
[17:23:37.024] <TB0> INFO: 5025280 events read in total (204455ms).
[17:23:37.104] <TB0> INFO: Test took 205363ms.
[17:23:59.242] <TB0> INFO: ROC 0 VthrComp = 73
[17:23:59.242] <TB0> INFO: ROC 1 VthrComp = 73
[17:23:59.242] <TB0> INFO: ROC 2 VthrComp = 75
[17:23:59.242] <TB0> INFO: ROC 3 VthrComp = 87
[17:23:59.242] <TB0> INFO: ROC 4 VthrComp = 70
[17:23:59.242] <TB0> INFO: ROC 5 VthrComp = 79
[17:23:59.242] <TB0> INFO: ROC 6 VthrComp = 76
[17:23:59.242] <TB0> INFO: ROC 7 VthrComp = 72
[17:23:59.243] <TB0> INFO: ROC 8 VthrComp = 83
[17:23:59.243] <TB0> INFO: ROC 9 VthrComp = 73
[17:23:59.243] <TB0> INFO: ROC 10 VthrComp = 74
[17:23:59.243] <TB0> INFO: ROC 11 VthrComp = 71
[17:23:59.243] <TB0> INFO: ROC 12 VthrComp = 73
[17:23:59.243] <TB0> INFO: ROC 13 VthrComp = 73
[17:23:59.244] <TB0> INFO: ROC 14 VthrComp = 72
[17:23:59.244] <TB0> INFO: ROC 15 VthrComp = 80
[17:23:59.519] <TB0> INFO: Expecting 41600 events.
[17:24:03.223] <TB0> INFO: 41600 events read in total (3111ms).
[17:24:03.224] <TB0> INFO: Test took 3979ms.
[17:24:03.235] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[17:24:03.235] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:24:03.249] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[17:24:03.249] <TB0> INFO: run 1 of 1
[17:24:03.527] <TB0> INFO: Expecting 5025280 events.
[17:24:31.695] <TB0> INFO: 685456 events read in total (27576ms).
[17:24:59.357] <TB0> INFO: 1368472 events read in total (55238ms).
[17:25:26.866] <TB0> INFO: 2050960 events read in total (82747ms).
[17:25:54.452] <TB0> INFO: 2730344 events read in total (110333ms).
[17:26:21.603] <TB0> INFO: 3407520 events read in total (137484ms).
[17:26:49.149] <TB0> INFO: 4084000 events read in total (165030ms).
[17:27:16.731] <TB0> INFO: 4759672 events read in total (192612ms).
[17:27:27.000] <TB0> INFO: 5025280 events read in total (203881ms).
[17:27:28.088] <TB0> INFO: Test took 204839ms.
[17:27:51.601] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 108.57 for pixel 6/16 mean/min/max = 92.8273/76.9557/108.699
[17:27:51.602] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 107.674 for pixel 12/79 mean/min/max = 92.1719/76.5468/107.797
[17:27:51.603] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 107.749 for pixel 0/75 mean/min/max = 92.6497/77.5183/107.781
[17:27:51.603] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 106.829 for pixel 0/77 mean/min/max = 90.816/74.673/106.959
[17:27:51.604] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 106.666 for pixel 5/5 mean/min/max = 90.7968/74.8515/106.742
[17:27:51.605] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 110 for pixel 0/5 mean/min/max = 94.3335/78.4877/110.179
[17:27:51.605] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 111.075 for pixel 8/69 mean/min/max = 94.6562/78.1692/111.143
[17:27:51.606] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 108.184 for pixel 0/16 mean/min/max = 92.1539/76.0878/108.22
[17:27:51.606] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 110.285 for pixel 16/60 mean/min/max = 92.2864/74.1495/110.423
[17:27:51.607] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 112.436 for pixel 6/79 mean/min/max = 94.9659/77.4372/112.495
[17:27:51.607] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 109.056 for pixel 0/49 mean/min/max = 93.7923/78.3794/109.205
[17:27:51.608] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 104.958 for pixel 31/19 mean/min/max = 89.9168/74.6491/105.184
[17:27:51.609] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 106.524 for pixel 11/56 mean/min/max = 91.5949/76.3668/106.823
[17:27:51.609] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 109.088 for pixel 51/79 mean/min/max = 92.8777/76.6498/109.106
[17:27:51.610] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 108.871 for pixel 0/1 mean/min/max = 92.4936/76.0199/108.967
[17:27:51.610] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 111.703 for pixel 0/37 mean/min/max = 93.5162/75.0283/112.004
[17:27:51.611] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:27:51.701] <TB0> INFO: Expecting 411648 events.
[17:28:01.057] <TB0> INFO: 411648 events read in total (8764ms).
[17:28:01.064] <TB0> INFO: Expecting 411648 events.
[17:28:10.202] <TB0> INFO: 411648 events read in total (8735ms).
[17:28:10.215] <TB0> INFO: Expecting 411648 events.
[17:28:19.530] <TB0> INFO: 411648 events read in total (8912ms).
[17:28:19.548] <TB0> INFO: Expecting 411648 events.
[17:28:28.759] <TB0> INFO: 411648 events read in total (8808ms).
[17:28:28.776] <TB0> INFO: Expecting 411648 events.
[17:28:38.245] <TB0> INFO: 411648 events read in total (9066ms).
[17:28:38.269] <TB0> INFO: Expecting 411648 events.
[17:28:47.460] <TB0> INFO: 411648 events read in total (8788ms).
[17:28:47.482] <TB0> INFO: Expecting 411648 events.
[17:28:56.830] <TB0> INFO: 411648 events read in total (8945ms).
[17:28:56.858] <TB0> INFO: Expecting 411648 events.
[17:29:06.240] <TB0> INFO: 411648 events read in total (8979ms).
[17:29:06.268] <TB0> INFO: Expecting 411648 events.
[17:29:15.422] <TB0> INFO: 411648 events read in total (8751ms).
[17:29:15.460] <TB0> INFO: Expecting 411648 events.
[17:29:24.849] <TB0> INFO: 411648 events read in total (8986ms).
[17:29:24.896] <TB0> INFO: Expecting 411648 events.
[17:29:34.328] <TB0> INFO: 411648 events read in total (9029ms).
[17:29:34.420] <TB0> INFO: Expecting 411648 events.
[17:29:43.827] <TB0> INFO: 411648 events read in total (9004ms).
[17:29:43.884] <TB0> INFO: Expecting 411648 events.
[17:29:53.128] <TB0> INFO: 411648 events read in total (8841ms).
[17:29:53.186] <TB0> INFO: Expecting 411648 events.
[17:30:02.715] <TB0> INFO: 411648 events read in total (9126ms).
[17:30:02.774] <TB0> INFO: Expecting 411648 events.
[17:30:11.986] <TB0> INFO: 411648 events read in total (8809ms).
[17:30:12.058] <TB0> INFO: Expecting 411648 events.
[17:30:21.349] <TB0> INFO: 411648 events read in total (8888ms).
[17:30:21.416] <TB0> INFO: Test took 149805ms.
[17:30:22.953] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[17:30:22.968] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[17:30:22.968] <TB0> INFO: run 1 of 1
[17:30:23.205] <TB0> INFO: Expecting 5025280 events.
[17:30:50.963] <TB0> INFO: 669272 events read in total (27166ms).
[17:31:18.224] <TB0> INFO: 1336808 events read in total (54427ms).
[17:31:46.555] <TB0> INFO: 2003200 events read in total (82758ms).
[17:32:13.654] <TB0> INFO: 2666936 events read in total (109857ms).
[17:32:40.476] <TB0> INFO: 3326984 events read in total (136679ms).
[17:33:07.740] <TB0> INFO: 3985192 events read in total (163943ms).
[17:33:34.633] <TB0> INFO: 4641888 events read in total (190836ms).
[17:33:50.058] <TB0> INFO: 5025280 events read in total (206261ms).
[17:33:50.142] <TB0> INFO: Test took 207174ms.
[17:34:12.871] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 53.309082 .. 97.568223
[17:34:13.112] <TB0> INFO: Expecting 208000 events.
[17:34:23.692] <TB0> INFO: 208000 events read in total (9988ms).
[17:34:23.693] <TB0> INFO: Test took 10821ms.
[17:34:23.760] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 43 .. 107 (-1/-1) hits flags = 528 (plus default)
[17:34:23.774] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[17:34:23.774] <TB0> INFO: run 1 of 1
[17:34:24.052] <TB0> INFO: Expecting 2163200 events.
[17:34:52.577] <TB0> INFO: 699168 events read in total (27934ms).
[17:35:20.768] <TB0> INFO: 1396600 events read in total (56126ms).
[17:35:48.493] <TB0> INFO: 2088496 events read in total (83850ms).
[17:35:52.020] <TB0> INFO: 2163200 events read in total (87377ms).
[17:35:52.056] <TB0> INFO: Test took 88283ms.
[17:36:10.278] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 62.847053 .. 90.311796
[17:36:10.547] <TB0> INFO: Expecting 208000 events.
[17:36:20.395] <TB0> INFO: 208000 events read in total (9256ms).
[17:36:20.396] <TB0> INFO: Test took 10116ms.
[17:36:20.448] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 52 .. 100 (-1/-1) hits flags = 528 (plus default)
[17:36:20.462] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[17:36:20.462] <TB0> INFO: run 1 of 1
[17:36:20.740] <TB0> INFO: Expecting 1630720 events.
[17:36:49.725] <TB0> INFO: 697672 events read in total (28393ms).
[17:37:18.383] <TB0> INFO: 1394688 events read in total (57051ms).
[17:37:28.084] <TB0> INFO: 1630720 events read in total (66752ms).
[17:37:28.142] <TB0> INFO: Test took 67681ms.
[17:37:44.689] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 67.941564 .. 85.983624
[17:37:44.926] <TB0> INFO: Expecting 208000 events.
[17:37:55.156] <TB0> INFO: 208000 events read in total (9639ms).
[17:37:55.157] <TB0> INFO: Test took 10467ms.
[17:37:55.206] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 57 .. 95 (-1/-1) hits flags = 528 (plus default)
[17:37:55.220] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[17:37:55.220] <TB0> INFO: run 1 of 1
[17:37:55.507] <TB0> INFO: Expecting 1297920 events.
[17:38:24.732] <TB0> INFO: 706272 events read in total (28633ms).
[17:38:49.067] <TB0> INFO: 1297920 events read in total (52968ms).
[17:38:49.101] <TB0> INFO: Test took 53882ms.
[17:39:04.623] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 70.655149 .. 83.459460
[17:39:04.860] <TB0> INFO: Expecting 208000 events.
[17:39:14.776] <TB0> INFO: 208000 events read in total (9325ms).
[17:39:14.777] <TB0> INFO: Test took 10153ms.
[17:39:14.825] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 60 .. 93 (-1/-1) hits flags = 528 (plus default)
[17:39:14.839] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[17:39:14.839] <TB0> INFO: run 1 of 1
[17:39:15.117] <TB0> INFO: Expecting 1131520 events.
[17:39:44.190] <TB0> INFO: 708640 events read in total (28481ms).
[17:40:01.511] <TB0> INFO: 1131520 events read in total (45802ms).
[17:40:01.549] <TB0> INFO: Test took 46711ms.
[17:40:16.806] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[17:40:16.806] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[17:40:16.821] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[17:40:16.821] <TB0> INFO: run 1 of 1
[17:40:17.056] <TB0> INFO: Expecting 1364480 events.
[17:40:45.686] <TB0> INFO: 669408 events read in total (28038ms).
[17:41:13.385] <TB0> INFO: 1338136 events read in total (55737ms).
[17:41:14.872] <TB0> INFO: 1364480 events read in total (57224ms).
[17:41:14.900] <TB0> INFO: Test took 58079ms.
[17:41:31.425] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C0.dat
[17:41:31.425] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C1.dat
[17:41:31.425] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C2.dat
[17:41:31.425] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C3.dat
[17:41:31.425] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C4.dat
[17:41:31.426] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C5.dat
[17:41:31.426] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C6.dat
[17:41:31.426] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C7.dat
[17:41:31.426] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C8.dat
[17:41:31.426] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C9.dat
[17:41:31.426] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C10.dat
[17:41:31.426] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C11.dat
[17:41:31.426] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C12.dat
[17:41:31.426] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C13.dat
[17:41:31.426] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C14.dat
[17:41:31.426] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//dacParameters80_C15.dat
[17:41:31.426] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C0.dat
[17:41:31.433] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C1.dat
[17:41:31.439] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C2.dat
[17:41:31.445] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C3.dat
[17:41:31.450] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C4.dat
[17:41:31.456] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C5.dat
[17:41:31.462] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C6.dat
[17:41:31.468] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C7.dat
[17:41:31.475] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C8.dat
[17:41:31.481] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C9.dat
[17:41:31.487] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C10.dat
[17:41:31.493] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C11.dat
[17:41:31.499] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C12.dat
[17:41:31.505] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C13.dat
[17:41:31.511] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C14.dat
[17:41:31.518] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1127_FullQualification_2016-11-07_11h17m_1478513836//003_FulltestTrim80_p17//trimParameters80_C15.dat
[17:41:31.525] <TB0> INFO: PixTestTrim80::trimTest() done
[17:41:31.525] <TB0> INFO: vtrim: 98 100 97 88 84 100 110 99 104 112 94 87 99 82 90 116
[17:41:31.525] <TB0> INFO: vthrcomp: 73 73 75 87 70 79 76 72 83 73 74 71 73 73 72 80
[17:41:31.525] <TB0> INFO: vcal mean: 80.05 80.00 80.04 80.04 80.01 80.05 80.06 80.05 79.99 80.01 80.03 80.02 79.97 80.06 79.98 80.02
[17:41:31.525] <TB0> INFO: vcal RMS: 0.74 0.70 0.71 0.75 0.69 0.73 0.78 0.72 0.80 0.76 0.70 0.79 0.70 0.73 0.73 0.81
[17:41:31.525] <TB0> INFO: bits mean: 9.92 9.96 9.15 9.57 9.88 8.93 9.74 9.86 10.30 9.42 9.15 10.46 9.81 9.25 9.89 9.97
[17:41:31.525] <TB0> INFO: bits RMS: 2.21 2.22 2.42 2.69 2.52 2.34 2.06 2.30 2.37 2.27 2.29 2.35 2.32 2.51 2.31 2.33
[17:41:31.533] <TB0> INFO: ----------------------------------------------------------------------
[17:41:31.533] <TB0> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[17:41:31.533] <TB0> INFO: ----------------------------------------------------------------------
[17:41:31.535] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[17:41:31.547] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[17:41:31.547] <TB0> INFO: run 1 of 1
[17:41:31.870] <TB0> INFO: Expecting 4160000 events.
[17:42:04.975] <TB0> INFO: 767895 events read in total (32513ms).
[17:42:37.471] <TB0> INFO: 1532655 events read in total (65009ms).
[17:43:10.189] <TB0> INFO: 2291640 events read in total (97727ms).
[17:43:42.088] <TB0> INFO: 3044635 events read in total (129626ms).
[17:44:14.148] <TB0> INFO: 3797335 events read in total (161686ms).
[17:44:29.673] <TB0> INFO: 4160000 events read in total (177211ms).
[17:44:29.766] <TB0> INFO: Test took 178219ms.
[17:44:56.460] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[17:44:56.475] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[17:44:56.475] <TB0> INFO: run 1 of 1
[17:44:56.712] <TB0> INFO: Expecting 4326400 events.
[17:45:28.803] <TB0> INFO: 731550 events read in total (31499ms).
[17:46:00.333] <TB0> INFO: 1460835 events read in total (63029ms).
[17:46:31.576] <TB0> INFO: 2186680 events read in total (94272ms).
[17:47:03.095] <TB0> INFO: 2907660 events read in total (125791ms).
[17:47:34.724] <TB0> INFO: 3627355 events read in total (157420ms).
[17:48:05.289] <TB0> INFO: 4326400 events read in total (187985ms).
[17:48:05.400] <TB0> INFO: Test took 188925ms.
[17:48:29.698] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[17:48:29.712] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[17:48:29.712] <TB0> INFO: run 1 of 1
[17:48:29.951] <TB0> INFO: Expecting 4347200 events.
[17:49:01.738] <TB0> INFO: 730680 events read in total (31195ms).
[17:49:32.903] <TB0> INFO: 1458805 events read in total (62360ms).
[17:50:04.447] <TB0> INFO: 2183680 events read in total (93904ms).
[17:50:35.657] <TB0> INFO: 2903660 events read in total (125114ms).
[17:51:06.903] <TB0> INFO: 3622590 events read in total (156360ms).
[17:51:38.134] <TB0> INFO: 4343735 events read in total (187591ms).
[17:51:38.695] <TB0> INFO: 4347200 events read in total (188152ms).
[17:51:38.790] <TB0> INFO: Test took 189078ms.
[17:52:06.487] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 209 (-1/-1) hits flags = 528 (plus default)
[17:52:06.501] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[17:52:06.501] <TB0> INFO: run 1 of 1
[17:52:06.737] <TB0> INFO: Expecting 4368000 events.
[17:52:38.886] <TB0> INFO: 729415 events read in total (31557ms).
[17:53:10.267] <TB0> INFO: 1456365 events read in total (62938ms).
[17:53:41.921] <TB0> INFO: 2180335 events read in total (94592ms).
[17:54:13.053] <TB0> INFO: 2899100 events read in total (125724ms).
[17:54:44.578] <TB0> INFO: 3616830 events read in total (157249ms).
[17:55:17.412] <TB0> INFO: 4335880 events read in total (190083ms).
[17:55:19.248] <TB0> INFO: 4368000 events read in total (191919ms).
[17:55:19.326] <TB0> INFO: Test took 192825ms.
[17:55:43.942] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[17:55:43.955] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[17:55:43.955] <TB0> INFO: run 1 of 1
[17:55:44.193] <TB0> INFO: Expecting 4326400 events.
[17:56:15.920] <TB0> INFO: 732020 events read in total (31135ms).
[17:56:47.356] <TB0> INFO: 1461715 events read in total (62571ms).
[17:57:18.984] <TB0> INFO: 2187925 events read in total (94199ms).
[17:57:50.437] <TB0> INFO: 2909055 events read in total (125652ms).
[17:58:21.757] <TB0> INFO: 3629065 events read in total (156972ms).
[17:58:52.159] <TB0> INFO: 4326400 events read in total (187374ms).
[17:58:52.273] <TB0> INFO: Test took 188318ms.
[17:59:20.172] <TB0> INFO: PixTestTrim80::trimBitTest() done
[17:59:20.173] <TB0> INFO: PixTestTrim80::doTest() done, duration: 2348 seconds
[17:59:20.810] <TB0> INFO: enter test to run
[17:59:20.810] <TB0> INFO: test: exit no parameter change
[17:59:21.008] <TB0> QUIET: Connection to board 71 closed.
[17:59:21.008] <TB0> INFO: pXar: this is the end, my friend