[11:14:47.022] <TB0> INFO: *** Welcome to pxar ***
[11:14:47.022] <TB0> INFO: *** Today: 2016/11/09
[11:14:47.028] <TB0> INFO: *** Version: c8ba-dirty
[11:14:47.028] <TB0> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C15.dat
[11:14:47.028] <TB0> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//tbmParameters_C1b.dat
[11:14:47.028] <TB0> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//defaultMaskFile.dat
[11:14:47.028] <TB0> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters_C15.dat
[11:14:47.089] <TB0> INFO: clk: 4
[11:14:47.089] <TB0> INFO: ctr: 4
[11:14:47.089] <TB0> INFO: sda: 19
[11:14:47.089] <TB0> INFO: tin: 9
[11:14:47.089] <TB0> INFO: level: 15
[11:14:47.089] <TB0> INFO: triggerdelay: 0
[11:14:47.089] <TB0> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[11:14:47.089] <TB0> INFO: Log level: INFO
[11:14:47.097] <TB0> INFO: Found DTB DTB_WRQ4OZ
[11:14:47.107] <TB0> QUIET: Connection to board DTB_WRQ4OZ opened.
[11:14:47.109] <TB0> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 71
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WRQ4OZ
MAC address: 40D855118047
Hostname: pixelDTB071
Comment:
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[11:14:47.110] <TB0> INFO: RPC call hashes of host and DTB match: 486171790
[11:14:48.598] <TB0> INFO: DUT info:
[11:14:48.598] <TB0> INFO: The DUT currently contains the following objects:
[11:14:48.598] <TB0> INFO: 4 TBM Cores tbm10c (4 ON)
[11:14:48.598] <TB0> INFO: TBM Core alpha (0): 7 registers set
[11:14:48.598] <TB0> INFO: TBM Core beta (1): 7 registers set
[11:14:48.598] <TB0> INFO: TBM Core alpha (2): 7 registers set
[11:14:48.598] <TB0> INFO: TBM Core beta (3): 7 registers set
[11:14:48.598] <TB0> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:14:48.598] <TB0> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.598] <TB0> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.598] <TB0> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.598] <TB0> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.598] <TB0> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.598] <TB0> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.598] <TB0> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.598] <TB0> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.598] <TB0> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.598] <TB0> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.598] <TB0> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.598] <TB0> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.599] <TB0> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.599] <TB0> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.599] <TB0> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.599] <TB0> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:48.999] <TB0> INFO: enter 'restricted' command line mode
[11:14:48.999] <TB0> INFO: enter test to run
[11:14:48.999] <TB0> INFO: test: pretest no parameter change
[11:14:48.999] <TB0> INFO: running: pretest
[11:14:49.004] <TB0> INFO: ######################################################################
[11:14:49.004] <TB0> INFO: PixTestPretest::doTest()
[11:14:49.004] <TB0> INFO: ######################################################################
[11:14:49.005] <TB0> INFO: ----------------------------------------------------------------------
[11:14:49.005] <TB0> INFO: PixTestPretest::programROC()
[11:14:49.005] <TB0> INFO: ----------------------------------------------------------------------
[11:15:07.018] <TB0> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:15:07.018] <TB0> INFO: IA differences per ROC: 18.5 19.3 22.5 19.3 20.1 20.1 21.7 19.3 20.9 17.7 18.5 17.7 20.9 20.1 20.1 20.1
[11:15:07.081] <TB0> INFO: ----------------------------------------------------------------------
[11:15:07.081] <TB0> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:15:07.081] <TB0> INFO: ----------------------------------------------------------------------
[11:15:13.355] <TB0> INFO: PixTestPretest::setVana() done, Module Ia 381.9 mA = 23.8688 mA/ROC
[11:15:13.355] <TB0> INFO: i(loss) [mA/ROC]: 18.5 19.3 18.5 18.5 19.3 18.5 19.3 18.5 18.5 19.3 18.5 19.3 20.1 20.1 18.5 18.5
[11:15:13.382] <TB0> INFO: ----------------------------------------------------------------------
[11:15:13.382] <TB0> INFO: PixTestPretest::findTiming()
[11:15:13.382] <TB0> INFO: ----------------------------------------------------------------------
[11:15:13.382] <TB0> INFO: PixTestCmd::init()

[11:15:44.506] <TB0> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:15:44.506] <TB0> INFO: (success/tries = 100/100), width = 4
[11:15:46.005] <TB0> INFO: ----------------------------------------------------------------------
[11:15:46.005] <TB0> INFO: PixTestPretest::findWorkingPixel()
[11:15:46.005] <TB0> INFO: ----------------------------------------------------------------------
[11:15:46.097] <TB0> INFO: Expecting 231680 events.
[11:15:56.404] <TB0> INFO: 231680 events read in total (9715ms).
[11:15:56.411] <TB0> INFO: Test took 10405ms.
[11:15:56.646] <TB0> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:15:56.678] <TB0> INFO: ----------------------------------------------------------------------
[11:15:56.678] <TB0> INFO: PixTestPretest::setVthrCompCalDel()
[11:15:56.678] <TB0> INFO: ----------------------------------------------------------------------
[11:15:56.771] <TB0> INFO: Expecting 231680 events.
[11:16:06.562] <TB0> INFO: 231680 events read in total (9199ms).
[11:16:06.571] <TB0> INFO: Test took 9888ms.
[11:16:06.827] <TB0> INFO: PixTestPretest::setVthrCompCalDel() done
[11:16:06.827] <TB0> INFO: CalDel: 74 77 90 90 87 85 76 82 95 100 99 84 91 83 82 87
[11:16:06.827] <TB0> INFO: VthrComp: 51 51 51 51 51 55 51 51 51 51 51 51 51 51 51 51
[11:16:06.830] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C0.dat
[11:16:06.830] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C1.dat
[11:16:06.830] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C2.dat
[11:16:06.830] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C3.dat
[11:16:06.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C4.dat
[11:16:06.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C5.dat
[11:16:06.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C6.dat
[11:16:06.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C7.dat
[11:16:06.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C8.dat
[11:16:06.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C9.dat
[11:16:06.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C10.dat
[11:16:06.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C11.dat
[11:16:06.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C12.dat
[11:16:06.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C13.dat
[11:16:06.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C14.dat
[11:16:06.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C15.dat
[11:16:06.831] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//tbmParameters_C0a.dat
[11:16:06.831] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//tbmParameters_C0b.dat
[11:16:06.831] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//tbmParameters_C1a.dat
[11:16:06.831] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//tbmParameters_C1b.dat
[11:16:06.832] <TB0> INFO: PixTestPretest::doTest() done, duration: 77 seconds
[11:16:06.883] <TB0> INFO: enter test to run
[11:16:06.883] <TB0> INFO: test: fulltest no parameter change
[11:16:06.883] <TB0> INFO: running: fulltest
[11:16:06.883] <TB0> INFO: ######################################################################
[11:16:06.883] <TB0> INFO: PixTestFullTest::doTest()
[11:16:06.883] <TB0> INFO: ######################################################################
[11:16:06.884] <TB0> INFO: ######################################################################
[11:16:06.884] <TB0> INFO: PixTestAlive::doTest()
[11:16:06.884] <TB0> INFO: ######################################################################
[11:16:06.885] <TB0> INFO: ----------------------------------------------------------------------
[11:16:06.885] <TB0> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:16:06.885] <TB0> INFO: ----------------------------------------------------------------------
[11:16:07.134] <TB0> INFO: Expecting 41600 events.
[11:16:10.896] <TB0> INFO: 41600 events read in total (3170ms).
[11:16:10.896] <TB0> INFO: Test took 4009ms.
[11:16:11.123] <TB0> INFO: PixTestAlive::aliveTest() done
[11:16:11.123] <TB0> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:16:11.124] <TB0> INFO: ----------------------------------------------------------------------
[11:16:11.124] <TB0> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:16:11.124] <TB0> INFO: ----------------------------------------------------------------------
[11:16:11.363] <TB0> INFO: Expecting 41600 events.
[11:16:14.381] <TB0> INFO: 41600 events read in total (2427ms).
[11:16:14.382] <TB0> INFO: Test took 3256ms.
[11:16:14.382] <TB0> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:16:14.619] <TB0> INFO: PixTestAlive::maskTest() done
[11:16:14.619] <TB0> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:16:14.621] <TB0> INFO: ----------------------------------------------------------------------
[11:16:14.621] <TB0> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:16:14.621] <TB0> INFO: ----------------------------------------------------------------------
[11:16:14.919] <TB0> INFO: Expecting 41600 events.
[11:16:18.492] <TB0> INFO: 41600 events read in total (2981ms).
[11:16:18.493] <TB0> INFO: Test took 3869ms.
[11:16:18.727] <TB0> INFO: PixTestAlive::addressDecodingTest() done
[11:16:18.727] <TB0> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:16:18.727] <TB0> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:16:18.727] <TB0> INFO: Decoding statistics:
[11:16:18.727] <TB0> INFO: General information:
[11:16:18.727] <TB0> INFO: 16bit words read: 0
[11:16:18.727] <TB0> INFO: valid events total: 0
[11:16:18.727] <TB0> INFO: empty events: 0
[11:16:18.727] <TB0> INFO: valid events with pixels: 0
[11:16:18.727] <TB0> INFO: valid pixel hits: 0
[11:16:18.727] <TB0> INFO: Event errors: 0
[11:16:18.727] <TB0> INFO: start marker: 0
[11:16:18.727] <TB0> INFO: stop marker: 0
[11:16:18.727] <TB0> INFO: overflow: 0
[11:16:18.727] <TB0> INFO: invalid 5bit words: 0
[11:16:18.727] <TB0> INFO: invalid XOR eye diagram: 0
[11:16:18.727] <TB0> INFO: frame (failed synchr.): 0
[11:16:18.728] <TB0> INFO: idle data (no TBM trl): 0
[11:16:18.728] <TB0> INFO: no data (only TBM hdr): 0
[11:16:18.728] <TB0> INFO: TBM errors: 0
[11:16:18.728] <TB0> INFO: flawed TBM headers: 0
[11:16:18.728] <TB0> INFO: flawed TBM trailers: 0
[11:16:18.728] <TB0> INFO: event ID mismatches: 0
[11:16:18.728] <TB0> INFO: ROC errors: 0
[11:16:18.728] <TB0> INFO: missing ROC header(s): 0
[11:16:18.728] <TB0> INFO: misplaced readback start: 0
[11:16:18.728] <TB0> INFO: Pixel decoding errors: 0
[11:16:18.728] <TB0> INFO: pixel data incomplete: 0
[11:16:18.728] <TB0> INFO: pixel address: 0
[11:16:18.728] <TB0> INFO: pulse height fill bit: 0
[11:16:18.728] <TB0> INFO: buffer corruption: 0
[11:16:18.732] <TB0> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C15.dat
[11:16:18.732] <TB0> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[11:16:18.732] <TB0> INFO: ######################################################################
[11:16:18.732] <TB0> INFO: PixTestReadback::doTest()
[11:16:18.732] <TB0> INFO: ######################################################################
[11:16:18.732] <TB0> INFO: ----------------------------------------------------------------------
[11:16:18.732] <TB0> INFO: PixTestReadback::CalibrateVd()
[11:16:18.732] <TB0> INFO: ----------------------------------------------------------------------
[11:16:28.667] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C0.dat
[11:16:28.667] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C1.dat
[11:16:28.667] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C2.dat
[11:16:28.667] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C3.dat
[11:16:28.667] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C4.dat
[11:16:28.667] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C5.dat
[11:16:28.667] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C6.dat
[11:16:28.667] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C7.dat
[11:16:28.667] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C8.dat
[11:16:28.668] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C9.dat
[11:16:28.668] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C10.dat
[11:16:28.668] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C11.dat
[11:16:28.668] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C12.dat
[11:16:28.668] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C13.dat
[11:16:28.668] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C14.dat
[11:16:28.668] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C15.dat
[11:16:28.701] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[11:16:28.701] <TB0> INFO: ----------------------------------------------------------------------
[11:16:28.701] <TB0> INFO: PixTestReadback::CalibrateVa()
[11:16:28.701] <TB0> INFO: ----------------------------------------------------------------------
[11:16:38.598] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C0.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C1.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C2.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C3.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C4.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C5.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C6.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C7.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C8.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C9.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C10.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C11.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C12.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C13.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C14.dat
[11:16:38.599] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C15.dat
[11:16:38.627] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[11:16:38.627] <TB0> INFO: ----------------------------------------------------------------------
[11:16:38.627] <TB0> INFO: PixTestReadback::readbackVbg()
[11:16:38.627] <TB0> INFO: ----------------------------------------------------------------------
[11:16:46.275] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[11:16:46.275] <TB0> INFO: ----------------------------------------------------------------------
[11:16:46.275] <TB0> INFO: PixTestReadback::getCalibratedVbg()
[11:16:46.275] <TB0> INFO: ----------------------------------------------------------------------
[11:16:46.275] <TB0> INFO: Vbg will be calibrated using Vd calibration
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 158.7calibrated Vbg = 1.19286 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 158.2calibrated Vbg = 1.18932 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 158.7calibrated Vbg = 1.18987 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 157.4calibrated Vbg = 1.1804 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 167.9calibrated Vbg = 1.17848 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 157.6calibrated Vbg = 1.18659 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 152.7calibrated Vbg = 1.18972 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 161calibrated Vbg = 1.19382 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 159calibrated Vbg = 1.18426 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 163.4calibrated Vbg = 1.18667 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 159.8calibrated Vbg = 1.17762 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 153.2calibrated Vbg = 1.17102 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 164.2calibrated Vbg = 1.18334 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 153.4calibrated Vbg = 1.18548 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 149.3calibrated Vbg = 1.18773 :::*/*/*/*/
[11:16:46.275] <TB0> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 158calibrated Vbg = 1.18402 :::*/*/*/*/
[11:16:46.277] <TB0> INFO: ----------------------------------------------------------------------
[11:16:46.277] <TB0> INFO: PixTestReadback::CalibrateIa()
[11:16:46.277] <TB0> INFO: ----------------------------------------------------------------------
[11:19:26.595] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C0.dat
[11:19:26.595] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C1.dat
[11:19:26.595] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C2.dat
[11:19:26.596] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C3.dat
[11:19:26.596] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C4.dat
[11:19:26.596] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C5.dat
[11:19:26.596] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C6.dat
[11:19:26.596] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C7.dat
[11:19:26.596] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C8.dat
[11:19:26.596] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C9.dat
[11:19:26.596] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C10.dat
[11:19:26.596] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C11.dat
[11:19:26.596] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C12.dat
[11:19:26.596] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C13.dat
[11:19:26.596] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C14.dat
[11:19:26.596] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C15.dat
[11:19:26.624] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[11:19:26.625] <TB0> INFO: PixTestReadback::doTest() done
[11:19:26.625] <TB0> INFO: Decoding statistics:
[11:19:26.625] <TB0> INFO: General information:
[11:19:26.625] <TB0> INFO: 16bit words read: 1536
[11:19:26.625] <TB0> INFO: valid events total: 256
[11:19:26.625] <TB0> INFO: empty events: 256
[11:19:26.625] <TB0> INFO: valid events with pixels: 0
[11:19:26.625] <TB0> INFO: valid pixel hits: 0
[11:19:26.625] <TB0> INFO: Event errors: 0
[11:19:26.625] <TB0> INFO: start marker: 0
[11:19:26.625] <TB0> INFO: stop marker: 0
[11:19:26.625] <TB0> INFO: overflow: 0
[11:19:26.625] <TB0> INFO: invalid 5bit words: 0
[11:19:26.625] <TB0> INFO: invalid XOR eye diagram: 0
[11:19:26.625] <TB0> INFO: frame (failed synchr.): 0
[11:19:26.625] <TB0> INFO: idle data (no TBM trl): 0
[11:19:26.625] <TB0> INFO: no data (only TBM hdr): 0
[11:19:26.625] <TB0> INFO: TBM errors: 0
[11:19:26.625] <TB0> INFO: flawed TBM headers: 0
[11:19:26.625] <TB0> INFO: flawed TBM trailers: 0
[11:19:26.625] <TB0> INFO: event ID mismatches: 0
[11:19:26.625] <TB0> INFO: ROC errors: 0
[11:19:26.625] <TB0> INFO: missing ROC header(s): 0
[11:19:26.625] <TB0> INFO: misplaced readback start: 0
[11:19:26.625] <TB0> INFO: Pixel decoding errors: 0
[11:19:26.625] <TB0> INFO: pixel data incomplete: 0
[11:19:26.625] <TB0> INFO: pixel address: 0
[11:19:26.625] <TB0> INFO: pulse height fill bit: 0
[11:19:26.625] <TB0> INFO: buffer corruption: 0
[11:19:26.697] <TB0> INFO: ######################################################################
[11:19:26.697] <TB0> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:19:26.697] <TB0> INFO: ######################################################################
[11:19:26.700] <TB0> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:19:26.796] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[11:19:26.796] <TB0> INFO: run 1 of 1
[11:19:27.171] <TB0> INFO: Expecting 3120000 events.
[11:19:59.415] <TB0> INFO: 690215 events read in total (31652ms).











[11:20:31.108] <TB0> INFO: 1378435 events read in total (63345ms).




















[11:21:02.703] <TB0> INFO: 2063425 events read in total (94940ms).











[11:21:35.353] <TB0> INFO: 2748250 events read in total (127590ms).











[11:21:53.096] <TB0> INFO: 3120000 events read in total (145333ms).
[11:21:53.199] <TB0> INFO: Test took 146404ms.
[11:22:15.439] <TB0> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 168 seconds
[11:22:15.439] <TB0> INFO: number of dead bumps (per ROC): 0 0 1 0 1 0 1 1 0 0 2 1 0 0 0 0
[11:22:15.439] <TB0> INFO: separation cut (per ROC): 111 107 126 104 107 117 118 120 110 114 110 113 123 121 122 107
[11:22:15.439] <TB0> INFO: Decoding statistics:
[11:22:15.439] <TB0> INFO: General information:
[11:22:15.439] <TB0> INFO: 16bit words read: 0
[11:22:15.439] <TB0> INFO: valid events total: 0
[11:22:15.439] <TB0> INFO: empty events: 0
[11:22:15.439] <TB0> INFO: valid events with pixels: 0
[11:22:15.439] <TB0> INFO: valid pixel hits: 0
[11:22:15.439] <TB0> INFO: Event errors: 0
[11:22:15.439] <TB0> INFO: start marker: 0
[11:22:15.439] <TB0> INFO: stop marker: 0
[11:22:15.439] <TB0> INFO: overflow: 0
[11:22:15.439] <TB0> INFO: invalid 5bit words: 0
[11:22:15.439] <TB0> INFO: invalid XOR eye diagram: 0
[11:22:15.439] <TB0> INFO: frame (failed synchr.): 0
[11:22:15.439] <TB0> INFO: idle data (no TBM trl): 0
[11:22:15.439] <TB0> INFO: no data (only TBM hdr): 0
[11:22:15.439] <TB0> INFO: TBM errors: 0
[11:22:15.439] <TB0> INFO: flawed TBM headers: 0
[11:22:15.439] <TB0> INFO: flawed TBM trailers: 0
[11:22:15.439] <TB0> INFO: event ID mismatches: 0
[11:22:15.439] <TB0> INFO: ROC errors: 0
[11:22:15.439] <TB0> INFO: missing ROC header(s): 0
[11:22:15.439] <TB0> INFO: misplaced readback start: 0
[11:22:15.439] <TB0> INFO: Pixel decoding errors: 0
[11:22:15.439] <TB0> INFO: pixel data incomplete: 0
[11:22:15.440] <TB0> INFO: pixel address: 0
[11:22:15.440] <TB0> INFO: pulse height fill bit: 0
[11:22:15.440] <TB0> INFO: buffer corruption: 0
[11:22:15.479] <TB0> INFO: ######################################################################
[11:22:15.479] <TB0> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:22:15.479] <TB0> INFO: ######################################################################
[11:22:15.479] <TB0> INFO: ----------------------------------------------------------------------
[11:22:15.479] <TB0> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:22:15.479] <TB0> INFO: ----------------------------------------------------------------------
[11:22:15.479] <TB0> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[11:22:15.494] <TB0> INFO: dacScan split into 1 runs with ntrig = 50
[11:22:15.494] <TB0> INFO: run 1 of 1
[11:22:15.732] <TB0> INFO: Expecting 36608000 events.
[11:22:42.852] <TB0> INFO: 686650 events read in total (26528ms).
[11:23:07.657] <TB0> INFO: 1359050 events read in total (51333ms).
[11:23:31.486] <TB0> INFO: 2031800 events read in total (75162ms).
[11:23:54.769] <TB0> INFO: 2702250 events read in total (98445ms).
[11:24:18.435] <TB0> INFO: 3374650 events read in total (122111ms).
[11:24:42.617] <TB0> INFO: 4044200 events read in total (146293ms).
[11:25:06.707] <TB0> INFO: 4715750 events read in total (170384ms).
[11:25:30.373] <TB0> INFO: 5388150 events read in total (194049ms).
[11:25:53.921] <TB0> INFO: 6060100 events read in total (217597ms).
[11:26:17.941] <TB0> INFO: 6731000 events read in total (241617ms).
[11:26:42.017] <TB0> INFO: 7400600 events read in total (265693ms).
[11:27:05.392] <TB0> INFO: 8070600 events read in total (289068ms).
[11:27:29.243] <TB0> INFO: 8741800 events read in total (312919ms).
[11:27:53.270] <TB0> INFO: 9412850 events read in total (336946ms).
[11:28:16.995] <TB0> INFO: 10081500 events read in total (360671ms).
[11:28:40.480] <TB0> INFO: 10753400 events read in total (384156ms).
[11:29:04.449] <TB0> INFO: 11421650 events read in total (408125ms).
[11:29:28.498] <TB0> INFO: 12091400 events read in total (432174ms).
[11:29:52.586] <TB0> INFO: 12760800 events read in total (456262ms).
[11:30:17.405] <TB0> INFO: 13431100 events read in total (481081ms).
[11:30:42.624] <TB0> INFO: 14097050 events read in total (506300ms).
[11:31:07.037] <TB0> INFO: 14766350 events read in total (530713ms).
[11:31:30.940] <TB0> INFO: 15432350 events read in total (554616ms).
[11:31:54.226] <TB0> INFO: 16100600 events read in total (577902ms).
[11:32:17.424] <TB0> INFO: 16765800 events read in total (601100ms).
[11:32:41.282] <TB0> INFO: 17435300 events read in total (624958ms).
[11:33:04.552] <TB0> INFO: 18100550 events read in total (648228ms).
[11:33:27.569] <TB0> INFO: 18766050 events read in total (671245ms).
[11:33:51.410] <TB0> INFO: 19427800 events read in total (695086ms).
[11:34:15.914] <TB0> INFO: 20090150 events read in total (719590ms).
[11:34:40.108] <TB0> INFO: 20754850 events read in total (743784ms).
[11:35:03.219] <TB0> INFO: 21417200 events read in total (766895ms).
[11:35:26.874] <TB0> INFO: 22079550 events read in total (790550ms).
[11:35:50.478] <TB0> INFO: 22743500 events read in total (814154ms).
[11:36:13.860] <TB0> INFO: 23407150 events read in total (837536ms).
[11:36:37.578] <TB0> INFO: 24070400 events read in total (861254ms).
[11:37:00.935] <TB0> INFO: 24733750 events read in total (884611ms).
[11:37:24.216] <TB0> INFO: 25395700 events read in total (907892ms).
[11:37:48.377] <TB0> INFO: 26060700 events read in total (932053ms).
[11:38:12.370] <TB0> INFO: 26722000 events read in total (956046ms).
[11:38:35.519] <TB0> INFO: 27384450 events read in total (979195ms).
[11:38:58.927] <TB0> INFO: 28045050 events read in total (1002603ms).
[11:39:22.798] <TB0> INFO: 28708650 events read in total (1026474ms).
[11:39:46.566] <TB0> INFO: 29370850 events read in total (1050242ms).
[11:40:10.734] <TB0> INFO: 30033700 events read in total (1074410ms).
[11:40:34.531] <TB0> INFO: 30695900 events read in total (1098207ms).
[11:40:58.466] <TB0> INFO: 31359250 events read in total (1122142ms).
[11:41:22.011] <TB0> INFO: 32020300 events read in total (1145687ms).
[11:41:45.763] <TB0> INFO: 32681000 events read in total (1169439ms).
[11:42:09.729] <TB0> INFO: 33344250 events read in total (1193405ms).
[11:42:33.592] <TB0> INFO: 34006650 events read in total (1217268ms).
[11:42:57.326] <TB0> INFO: 34670500 events read in total (1241002ms).
[11:43:21.113] <TB0> INFO: 35333300 events read in total (1264789ms).
[11:43:44.974] <TB0> INFO: 35999150 events read in total (1288650ms).
[11:44:06.345] <TB0> INFO: 36608000 events read in total (1310021ms).
[11:44:06.551] <TB0> INFO: Test took 1311057ms.
[11:44:06.943] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:08.528] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:10.083] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:12.032] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:13.784] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:15.524] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:17.442] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:19.174] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:20.977] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:22.825] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:24.595] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:26.725] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:28.905] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:30.968] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:33.341] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:35.620] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[11:44:37.550] <TB0> INFO: PixTestScurves::scurves() done
[11:44:37.550] <TB0> INFO: Vcal mean: 112.57 114.21 118.38 118.23 115.29 129.11 123.50 121.23 119.94 118.51 121.11 121.23 124.10 123.50 116.12 119.41
[11:44:37.550] <TB0> INFO: Vcal RMS: 4.38 5.43 5.81 5.66 5.32 5.77 5.37 6.78 5.65 6.07 7.05 5.95 5.49 5.60 5.98 5.85
[11:44:37.550] <TB0> INFO: PixTestScurves::fullTest() done, duration: 1342 seconds
[11:44:37.550] <TB0> INFO: Decoding statistics:
[11:44:37.550] <TB0> INFO: General information:
[11:44:37.550] <TB0> INFO: 16bit words read: 0
[11:44:37.550] <TB0> INFO: valid events total: 0
[11:44:37.550] <TB0> INFO: empty events: 0
[11:44:37.551] <TB0> INFO: valid events with pixels: 0
[11:44:37.551] <TB0> INFO: valid pixel hits: 0
[11:44:37.551] <TB0> INFO: Event errors: 0
[11:44:37.551] <TB0> INFO: start marker: 0
[11:44:37.551] <TB0> INFO: stop marker: 0
[11:44:37.551] <TB0> INFO: overflow: 0
[11:44:37.551] <TB0> INFO: invalid 5bit words: 0
[11:44:37.551] <TB0> INFO: invalid XOR eye diagram: 0
[11:44:37.551] <TB0> INFO: frame (failed synchr.): 0
[11:44:37.551] <TB0> INFO: idle data (no TBM trl): 0
[11:44:37.551] <TB0> INFO: no data (only TBM hdr): 0
[11:44:37.551] <TB0> INFO: TBM errors: 0
[11:44:37.551] <TB0> INFO: flawed TBM headers: 0
[11:44:37.551] <TB0> INFO: flawed TBM trailers: 0
[11:44:37.551] <TB0> INFO: event ID mismatches: 0
[11:44:37.551] <TB0> INFO: ROC errors: 0
[11:44:37.551] <TB0> INFO: missing ROC header(s): 0
[11:44:37.551] <TB0> INFO: misplaced readback start: 0
[11:44:37.551] <TB0> INFO: Pixel decoding errors: 0
[11:44:37.551] <TB0> INFO: pixel data incomplete: 0
[11:44:37.551] <TB0> INFO: pixel address: 0
[11:44:37.551] <TB0> INFO: pulse height fill bit: 0
[11:44:37.551] <TB0> INFO: buffer corruption: 0
[11:44:37.646] <TB0> INFO: ######################################################################
[11:44:37.646] <TB0> INFO: PixTestTrim::doTest()
[11:44:37.646] <TB0> INFO: ######################################################################
[11:44:37.647] <TB0> INFO: ----------------------------------------------------------------------
[11:44:37.647] <TB0> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[11:44:37.647] <TB0> INFO: ----------------------------------------------------------------------
[11:44:37.715] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[11:44:37.715] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:44:37.729] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[11:44:37.729] <TB0> INFO: run 1 of 1
[11:44:38.054] <TB0> INFO: Expecting 5025280 events.
[11:45:09.717] <TB0> INFO: 826288 events read in total (31050ms).
[11:45:40.319] <TB0> INFO: 1650512 events read in total (61652ms).
[11:46:12.181] <TB0> INFO: 2472104 events read in total (93514ms).
[11:46:42.922] <TB0> INFO: 3289656 events read in total (124255ms).
[11:47:14.082] <TB0> INFO: 4103856 events read in total (155416ms).
[11:47:44.856] <TB0> INFO: 4915960 events read in total (186189ms).
[11:47:49.314] <TB0> INFO: 5025280 events read in total (190647ms).
[11:47:49.376] <TB0> INFO: Test took 191647ms.
[11:48:09.082] <TB0> INFO: ROC 0 VthrComp = 115
[11:48:09.082] <TB0> INFO: ROC 1 VthrComp = 118
[11:48:09.082] <TB0> INFO: ROC 2 VthrComp = 124
[11:48:09.082] <TB0> INFO: ROC 3 VthrComp = 114
[11:48:09.082] <TB0> INFO: ROC 4 VthrComp = 116
[11:48:09.082] <TB0> INFO: ROC 5 VthrComp = 130
[11:48:09.082] <TB0> INFO: ROC 6 VthrComp = 128
[11:48:09.082] <TB0> INFO: ROC 7 VthrComp = 119
[11:48:09.082] <TB0> INFO: ROC 8 VthrComp = 123
[11:48:09.083] <TB0> INFO: ROC 9 VthrComp = 110
[11:48:09.083] <TB0> INFO: ROC 10 VthrComp = 109
[11:48:09.083] <TB0> INFO: ROC 11 VthrComp = 117
[11:48:09.083] <TB0> INFO: ROC 12 VthrComp = 125
[11:48:09.083] <TB0> INFO: ROC 13 VthrComp = 127
[11:48:09.083] <TB0> INFO: ROC 14 VthrComp = 115
[11:48:09.083] <TB0> INFO: ROC 15 VthrComp = 118
[11:48:09.321] <TB0> INFO: Expecting 41600 events.
[11:48:13.153] <TB0> INFO: 41600 events read in total (3240ms).
[11:48:13.153] <TB0> INFO: Test took 4068ms.
[11:48:13.164] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[11:48:13.164] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:48:13.179] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[11:48:13.179] <TB0> INFO: run 1 of 1
[11:48:13.458] <TB0> INFO: Expecting 5025280 events.
[11:48:40.184] <TB0> INFO: 590832 events read in total (26133ms).
[11:49:06.840] <TB0> INFO: 1180664 events read in total (52789ms).
[11:49:33.498] <TB0> INFO: 1770704 events read in total (79447ms).
[11:50:00.628] <TB0> INFO: 2359944 events read in total (106577ms).
[11:50:27.629] <TB0> INFO: 2946504 events read in total (133578ms).
[11:50:54.186] <TB0> INFO: 3532376 events read in total (160135ms).
[11:51:20.305] <TB0> INFO: 4117488 events read in total (186254ms).
[11:51:46.863] <TB0> INFO: 4701824 events read in total (212812ms).
[11:52:01.917] <TB0> INFO: 5025280 events read in total (227866ms).
[11:52:01.999] <TB0> INFO: Test took 228821ms.
[11:52:30.299] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 57.6591 for pixel 8/10 mean/min/max = 45.2005/32.6923/57.7086
[11:52:30.300] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 59.4732 for pixel 18/14 mean/min/max = 45.8018/31.8882/59.7153
[11:52:30.300] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 58.6909 for pixel 20/56 mean/min/max = 45.5848/32.3235/58.846
[11:52:30.301] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 63.1175 for pixel 24/0 mean/min/max = 48.1654/33.1899/63.141
[11:52:30.301] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 60.7618 for pixel 10/0 mean/min/max = 46.7605/32.7269/60.794
[11:52:30.302] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 60.8637 for pixel 11/9 mean/min/max = 46.5411/31.846/61.2362
[11:52:30.302] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 59.6907 for pixel 5/12 mean/min/max = 46.5131/33.1706/59.8556
[11:52:30.303] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 62.5144 for pixel 0/8 mean/min/max = 46.9852/31.0282/62.9421
[11:52:30.303] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 59.925 for pixel 2/79 mean/min/max = 46.2323/32.3796/60.085
[11:52:30.304] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 66.4515 for pixel 11/5 mean/min/max = 50.2961/33.9857/66.6064
[11:52:30.304] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 67.1701 for pixel 0/69 mean/min/max = 50.6847/34.0741/67.2953
[11:52:30.305] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 61.4268 for pixel 18/2 mean/min/max = 46.9501/32.2866/61.6137
[11:52:30.305] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 59.6573 for pixel 44/6 mean/min/max = 45.8092/31.9287/59.6897
[11:52:30.305] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 59.6423 for pixel 0/12 mean/min/max = 45.8213/31.9325/59.7101
[11:52:30.306] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 59.532 for pixel 12/6 mean/min/max = 45.8567/32.1568/59.5566
[11:52:30.306] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 59.782 for pixel 2/19 mean/min/max = 45.6537/31.4212/59.8863
[11:52:30.307] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:52:30.398] <TB0> INFO: Expecting 411648 events.
[11:52:40.226] <TB0> INFO: 411648 events read in total (9230ms).
[11:52:40.233] <TB0> INFO: Expecting 411648 events.
[11:52:49.435] <TB0> INFO: 411648 events read in total (8799ms).
[11:52:49.445] <TB0> INFO: Expecting 411648 events.
[11:52:58.833] <TB0> INFO: 411648 events read in total (8985ms).
[11:52:58.849] <TB0> INFO: Expecting 411648 events.
[11:53:08.016] <TB0> INFO: 411648 events read in total (8764ms).
[11:53:08.036] <TB0> INFO: Expecting 411648 events.
[11:53:17.293] <TB0> INFO: 411648 events read in total (8855ms).
[11:53:17.327] <TB0> INFO: Expecting 411648 events.
[11:53:26.586] <TB0> INFO: 411648 events read in total (8856ms).
[11:53:26.611] <TB0> INFO: Expecting 411648 events.
[11:53:35.844] <TB0> INFO: 411648 events read in total (8830ms).
[11:53:35.876] <TB0> INFO: Expecting 411648 events.
[11:53:45.141] <TB0> INFO: 411648 events read in total (8862ms).
[11:53:45.175] <TB0> INFO: Expecting 411648 events.
[11:53:54.389] <TB0> INFO: 411648 events read in total (8811ms).
[11:53:54.429] <TB0> INFO: Expecting 411648 events.
[11:54:03.709] <TB0> INFO: 411648 events read in total (8877ms).
[11:54:03.896] <TB0> INFO: Expecting 411648 events.
[11:54:13.188] <TB0> INFO: 411648 events read in total (8889ms).
[11:54:13.239] <TB0> INFO: Expecting 411648 events.
[11:54:22.445] <TB0> INFO: 411648 events read in total (8803ms).
[11:54:22.636] <TB0> INFO: Expecting 411648 events.
[11:54:31.837] <TB0> INFO: 411648 events read in total (8798ms).
[11:54:32.018] <TB0> INFO: Expecting 411648 events.
[11:54:41.489] <TB0> INFO: 411648 events read in total (9068ms).
[11:54:41.543] <TB0> INFO: Expecting 411648 events.
[11:54:50.904] <TB0> INFO: 411648 events read in total (8958ms).
[11:54:50.999] <TB0> INFO: Expecting 411648 events.
[11:55:00.177] <TB0> INFO: 411648 events read in total (8775ms).
[11:55:00.242] <TB0> INFO: Test took 149935ms.
[11:55:01.014] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[11:55:01.027] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[11:55:01.027] <TB0> INFO: run 1 of 1
[11:55:01.264] <TB0> INFO: Expecting 5025280 events.
[11:55:28.235] <TB0> INFO: 590424 events read in total (26379ms).
[11:55:54.997] <TB0> INFO: 1178952 events read in total (53141ms).
[11:56:22.311] <TB0> INFO: 1767456 events read in total (80455ms).
[11:56:49.492] <TB0> INFO: 2354304 events read in total (107636ms).
[11:57:16.903] <TB0> INFO: 2942080 events read in total (135047ms).
[11:57:43.682] <TB0> INFO: 3532128 events read in total (161826ms).
[11:58:10.712] <TB0> INFO: 4120704 events read in total (188856ms).
[11:58:37.332] <TB0> INFO: 4707576 events read in total (215476ms).
[11:58:52.580] <TB0> INFO: 5025280 events read in total (230724ms).
[11:58:52.758] <TB0> INFO: Test took 231732ms.
[11:59:22.345] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 11.878604 .. 146.810763
[11:59:22.639] <TB0> INFO: Expecting 208000 events.
[11:59:32.598] <TB0> INFO: 208000 events read in total (9367ms).
[11:59:32.600] <TB0> INFO: Test took 10254ms.
[11:59:32.652] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 156 (-1/-1) hits flags = 528 (plus default)
[11:59:32.666] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[11:59:32.666] <TB0> INFO: run 1 of 1
[11:59:32.948] <TB0> INFO: Expecting 5191680 events.
[12:00:00.436] <TB0> INFO: 584648 events read in total (26896ms).
[12:00:27.412] <TB0> INFO: 1168920 events read in total (53872ms).
[12:00:53.544] <TB0> INFO: 1753144 events read in total (80005ms).
[12:01:19.724] <TB0> INFO: 2337720 events read in total (106184ms).
[12:01:46.810] <TB0> INFO: 2921952 events read in total (133270ms).
[12:02:13.340] <TB0> INFO: 3505696 events read in total (159800ms).
[12:02:39.811] <TB0> INFO: 4089128 events read in total (186271ms).
[12:03:06.701] <TB0> INFO: 4671608 events read in total (213161ms).
[12:03:30.959] <TB0> INFO: 5191680 events read in total (237419ms).
[12:03:31.154] <TB0> INFO: Test took 238489ms.
[12:04:01.424] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 27.255771 .. 48.043874
[12:04:01.753] <TB0> INFO: Expecting 208000 events.
[12:04:11.740] <TB0> INFO: 208000 events read in total (9394ms).
[12:04:11.742] <TB0> INFO: Test took 10317ms.
[12:04:11.795] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 58 (-1/-1) hits flags = 528 (plus default)
[12:04:11.809] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:04:11.809] <TB0> INFO: run 1 of 1
[12:04:12.087] <TB0> INFO: Expecting 1397760 events.
[12:04:40.654] <TB0> INFO: 648272 events read in total (27975ms).
[12:05:08.844] <TB0> INFO: 1295248 events read in total (56166ms).
[12:05:13.938] <TB0> INFO: 1397760 events read in total (61260ms).
[12:05:13.982] <TB0> INFO: Test took 62174ms.
[12:05:29.859] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 27.521587 .. 48.788032
[12:05:30.103] <TB0> INFO: Expecting 208000 events.
[12:05:39.932] <TB0> INFO: 208000 events read in total (9237ms).
[12:05:39.934] <TB0> INFO: Test took 10073ms.
[12:05:39.995] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 58 (-1/-1) hits flags = 528 (plus default)
[12:05:40.008] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:05:40.008] <TB0> INFO: run 1 of 1
[12:05:40.285] <TB0> INFO: Expecting 1397760 events.
[12:06:09.221] <TB0> INFO: 649016 events read in total (28344ms).
[12:06:38.050] <TB0> INFO: 1296592 events read in total (57174ms).
[12:06:42.920] <TB0> INFO: 1397760 events read in total (62043ms).
[12:06:42.961] <TB0> INFO: Test took 62953ms.
[12:07:01.233] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 24.548608 .. 47.347973
[12:07:01.484] <TB0> INFO: Expecting 208000 events.
[12:07:11.637] <TB0> INFO: 208000 events read in total (9561ms).
[12:07:11.638] <TB0> INFO: Test took 10403ms.
[12:07:11.697] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 57 (-1/-1) hits flags = 528 (plus default)
[12:07:11.712] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:07:11.712] <TB0> INFO: run 1 of 1
[12:07:11.990] <TB0> INFO: Expecting 1464320 events.
[12:07:41.362] <TB0> INFO: 664072 events read in total (28781ms).
[12:08:09.400] <TB0> INFO: 1328104 events read in total (56820ms).
[12:08:15.667] <TB0> INFO: 1464320 events read in total (63086ms).
[12:08:15.703] <TB0> INFO: Test took 63992ms.
[12:08:32.844] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:08:32.844] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:08:32.859] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:08:32.859] <TB0> INFO: run 1 of 1
[12:08:33.142] <TB0> INFO: Expecting 1364480 events.
[12:09:02.618] <TB0> INFO: 668968 events read in total (28885ms).
[12:09:31.666] <TB0> INFO: 1336536 events read in total (57933ms).
[12:09:33.239] <TB0> INFO: 1364480 events read in total (59506ms).
[12:09:33.274] <TB0> INFO: Test took 60415ms.
[12:09:48.528] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C0.dat
[12:09:48.529] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C1.dat
[12:09:48.529] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C2.dat
[12:09:48.529] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C3.dat
[12:09:48.529] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C4.dat
[12:09:48.529] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C5.dat
[12:09:48.529] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C6.dat
[12:09:48.529] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C7.dat
[12:09:48.529] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C8.dat
[12:09:48.529] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C9.dat
[12:09:48.529] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C10.dat
[12:09:48.529] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C11.dat
[12:09:48.530] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C12.dat
[12:09:48.530] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C13.dat
[12:09:48.530] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C14.dat
[12:09:48.530] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C15.dat
[12:09:48.530] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C0.dat
[12:09:48.538] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C1.dat
[12:09:48.547] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C2.dat
[12:09:48.555] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C3.dat
[12:09:48.564] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C4.dat
[12:09:48.572] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C5.dat
[12:09:48.580] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C6.dat
[12:09:48.589] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C7.dat
[12:09:48.597] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C8.dat
[12:09:48.605] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C9.dat
[12:09:48.614] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C10.dat
[12:09:48.622] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C11.dat
[12:09:48.631] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C12.dat
[12:09:48.639] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C13.dat
[12:09:48.647] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C14.dat
[12:09:48.656] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C15.dat
[12:09:48.664] <TB0> INFO: PixTestTrim::trimTest() done
[12:09:48.664] <TB0> INFO: vtrim: 113 125 115 124 129 128 129 122 98 147 121 135 122 114 129 134
[12:09:48.664] <TB0> INFO: vthrcomp: 115 118 124 114 116 130 128 119 123 110 109 117 125 127 115 118
[12:09:48.664] <TB0> INFO: vcal mean: 35.00 35.01 34.99 35.22 35.07 35.31 34.93 34.98 35.02 35.49 35.41 35.03 34.97 35.00 34.99 34.95
[12:09:48.664] <TB0> INFO: vcal RMS: 0.95 1.14 0.95 1.31 0.97 1.40 0.96 1.19 0.98 1.58 1.52 1.24 1.10 0.99 1.03 1.05
[12:09:48.664] <TB0> INFO: bits mean: 9.68 9.57 9.34 9.16 9.44 9.63 9.05 9.04 8.86 9.16 8.04 9.42 9.43 9.39 9.69 9.82
[12:09:48.664] <TB0> INFO: bits RMS: 2.62 2.72 2.73 2.70 2.60 2.75 2.73 3.03 2.96 2.48 2.90 2.67 2.79 2.78 2.62 2.69
[12:09:48.673] <TB0> INFO: ----------------------------------------------------------------------
[12:09:48.673] <TB0> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:09:48.673] <TB0> INFO: ----------------------------------------------------------------------
[12:09:48.676] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:09:48.689] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:09:48.689] <TB0> INFO: run 1 of 1
[12:09:48.927] <TB0> INFO: Expecting 4160000 events.
[12:10:22.703] <TB0> INFO: 757845 events read in total (33182ms).
[12:10:55.540] <TB0> INFO: 1510870 events read in total (66019ms).
[12:11:28.443] <TB0> INFO: 2258505 events read in total (98922ms).
[12:12:00.777] <TB0> INFO: 3001995 events read in total (131256ms).
[12:12:33.034] <TB0> INFO: 3743430 events read in total (163513ms).
[12:12:51.286] <TB0> INFO: 4160000 events read in total (181765ms).
[12:12:51.403] <TB0> INFO: Test took 182714ms.
[12:13:21.101] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[12:13:21.115] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:13:21.115] <TB0> INFO: run 1 of 1
[12:13:21.444] <TB0> INFO: Expecting 4347200 events.
[12:13:54.307] <TB0> INFO: 721910 events read in total (32270ms).
[12:14:26.205] <TB0> INFO: 1440795 events read in total (64168ms).
[12:14:58.165] <TB0> INFO: 2155715 events read in total (96128ms).
[12:15:29.812] <TB0> INFO: 2865140 events read in total (127775ms).
[12:16:01.264] <TB0> INFO: 3573670 events read in total (159227ms).
[12:16:32.882] <TB0> INFO: 4282385 events read in total (190845ms).
[12:16:35.960] <TB0> INFO: 4347200 events read in total (193923ms).
[12:16:36.038] <TB0> INFO: Test took 194921ms.
[12:17:05.533] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 197 (-1/-1) hits flags = 528 (plus default)
[12:17:05.548] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:17:05.548] <TB0> INFO: run 1 of 1
[12:17:05.790] <TB0> INFO: Expecting 4118400 events.
[12:17:39.229] <TB0> INFO: 737180 events read in total (32848ms).
[12:18:11.080] <TB0> INFO: 1470040 events read in total (64699ms).
[12:18:42.830] <TB0> INFO: 2197980 events read in total (96449ms).
[12:19:15.077] <TB0> INFO: 2921815 events read in total (128696ms).
[12:19:47.458] <TB0> INFO: 3643695 events read in total (161077ms).
[12:20:08.221] <TB0> INFO: 4118400 events read in total (181840ms).
[12:20:08.301] <TB0> INFO: Test took 182753ms.
[12:20:35.376] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 197 (-1/-1) hits flags = 528 (plus default)
[12:20:35.391] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:20:35.391] <TB0> INFO: run 1 of 1
[12:20:35.682] <TB0> INFO: Expecting 4118400 events.
[12:21:09.498] <TB0> INFO: 737335 events read in total (33224ms).
[12:21:42.092] <TB0> INFO: 1470725 events read in total (65818ms).
[12:22:14.598] <TB0> INFO: 2198835 events read in total (98324ms).
[12:22:46.321] <TB0> INFO: 2922670 events read in total (130047ms).
[12:23:18.354] <TB0> INFO: 3644750 events read in total (162080ms).
[12:23:39.224] <TB0> INFO: 4118400 events read in total (182950ms).
[12:23:39.331] <TB0> INFO: Test took 183939ms.
[12:24:04.236] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:24:04.251] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:24:04.251] <TB0> INFO: run 1 of 1
[12:24:04.541] <TB0> INFO: Expecting 4160000 events.
[12:24:38.245] <TB0> INFO: 734895 events read in total (33113ms).
[12:25:10.631] <TB0> INFO: 1465605 events read in total (65499ms).
[12:25:42.499] <TB0> INFO: 2191695 events read in total (97367ms).
[12:26:14.582] <TB0> INFO: 2912645 events read in total (129450ms).
[12:26:46.869] <TB0> INFO: 3632425 events read in total (161737ms).
[12:27:10.425] <TB0> INFO: 4160000 events read in total (185293ms).
[12:27:10.534] <TB0> INFO: Test took 186283ms.
[12:27:36.244] <TB0> INFO: PixTestTrim::trimBitTest() done
[12:27:36.245] <TB0> INFO: PixTestTrim::doTest() done, duration: 2578 seconds
[12:27:36.245] <TB0> INFO: Decoding statistics:
[12:27:36.245] <TB0> INFO: General information:
[12:27:36.245] <TB0> INFO: 16bit words read: 0
[12:27:36.245] <TB0> INFO: valid events total: 0
[12:27:36.245] <TB0> INFO: empty events: 0
[12:27:36.245] <TB0> INFO: valid events with pixels: 0
[12:27:36.245] <TB0> INFO: valid pixel hits: 0
[12:27:36.245] <TB0> INFO: Event errors: 0
[12:27:36.245] <TB0> INFO: start marker: 0
[12:27:36.245] <TB0> INFO: stop marker: 0
[12:27:36.245] <TB0> INFO: overflow: 0
[12:27:36.246] <TB0> INFO: invalid 5bit words: 0
[12:27:36.246] <TB0> INFO: invalid XOR eye diagram: 0
[12:27:36.246] <TB0> INFO: frame (failed synchr.): 0
[12:27:36.246] <TB0> INFO: idle data (no TBM trl): 0
[12:27:36.246] <TB0> INFO: no data (only TBM hdr): 0
[12:27:36.246] <TB0> INFO: TBM errors: 0
[12:27:36.246] <TB0> INFO: flawed TBM headers: 0
[12:27:36.246] <TB0> INFO: flawed TBM trailers: 0
[12:27:36.246] <TB0> INFO: event ID mismatches: 0
[12:27:36.246] <TB0> INFO: ROC errors: 0
[12:27:36.246] <TB0> INFO: missing ROC header(s): 0
[12:27:36.246] <TB0> INFO: misplaced readback start: 0
[12:27:36.246] <TB0> INFO: Pixel decoding errors: 0
[12:27:36.246] <TB0> INFO: pixel data incomplete: 0
[12:27:36.246] <TB0> INFO: pixel address: 0
[12:27:36.246] <TB0> INFO: pulse height fill bit: 0
[12:27:36.246] <TB0> INFO: buffer corruption: 0
[12:27:36.875] <TB0> INFO: ######################################################################
[12:27:36.875] <TB0> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:27:36.875] <TB0> INFO: ######################################################################
[12:27:37.114] <TB0> INFO: Expecting 41600 events.
[12:27:40.807] <TB0> INFO: 41600 events read in total (3101ms).
[12:27:40.808] <TB0> INFO: Test took 3932ms.
[12:27:41.265] <TB0> INFO: Expecting 41600 events.
[12:27:44.970] <TB0> INFO: 41600 events read in total (3113ms).
[12:27:44.972] <TB0> INFO: Test took 3959ms.
[12:27:45.264] <TB0> INFO: Expecting 41600 events.
[12:27:48.943] <TB0> INFO: 41600 events read in total (3088ms).
[12:27:48.944] <TB0> INFO: Test took 3947ms.
[12:27:49.233] <TB0> INFO: Expecting 41600 events.
[12:27:52.925] <TB0> INFO: 41600 events read in total (3100ms).
[12:27:52.926] <TB0> INFO: Test took 3958ms.
[12:27:53.219] <TB0> INFO: Expecting 41600 events.
[12:27:56.836] <TB0> INFO: 41600 events read in total (3025ms).
[12:27:56.837] <TB0> INFO: Test took 3886ms.
[12:27:57.145] <TB0> INFO: Expecting 41600 events.
[12:28:00.807] <TB0> INFO: 41600 events read in total (3070ms).
[12:28:00.808] <TB0> INFO: Test took 3947ms.
[12:28:01.098] <TB0> INFO: Expecting 41600 events.
[12:28:04.755] <TB0> INFO: 41600 events read in total (3065ms).
[12:28:04.756] <TB0> INFO: Test took 3922ms.
[12:28:05.046] <TB0> INFO: Expecting 41600 events.
[12:28:08.934] <TB0> INFO: 41600 events read in total (3296ms).
[12:28:08.936] <TB0> INFO: Test took 4154ms.
[12:28:09.233] <TB0> INFO: Expecting 41600 events.
[12:28:12.977] <TB0> INFO: 41600 events read in total (3153ms).
[12:28:12.978] <TB0> INFO: Test took 4011ms.
[12:28:13.301] <TB0> INFO: Expecting 41600 events.
[12:28:16.989] <TB0> INFO: 41600 events read in total (3096ms).
[12:28:16.990] <TB0> INFO: Test took 3985ms.
[12:28:17.279] <TB0> INFO: Expecting 41600 events.
[12:28:20.808] <TB0> INFO: 41600 events read in total (2937ms).
[12:28:20.809] <TB0> INFO: Test took 3794ms.
[12:28:21.101] <TB0> INFO: Expecting 41600 events.
[12:28:24.735] <TB0> INFO: 41600 events read in total (3042ms).
[12:28:24.736] <TB0> INFO: Test took 3900ms.
[12:28:25.028] <TB0> INFO: Expecting 41600 events.
[12:28:28.525] <TB0> INFO: 41600 events read in total (2905ms).
[12:28:28.526] <TB0> INFO: Test took 3762ms.
[12:28:28.815] <TB0> INFO: Expecting 41600 events.
[12:28:32.515] <TB0> INFO: 41600 events read in total (3108ms).
[12:28:32.516] <TB0> INFO: Test took 3965ms.
[12:28:32.809] <TB0> INFO: Expecting 41600 events.
[12:28:36.327] <TB0> INFO: 41600 events read in total (2927ms).
[12:28:36.329] <TB0> INFO: Test took 3785ms.
[12:28:36.619] <TB0> INFO: Expecting 41600 events.
[12:28:40.182] <TB0> INFO: 41600 events read in total (2971ms).
[12:28:40.183] <TB0> INFO: Test took 3829ms.
[12:28:40.476] <TB0> INFO: Expecting 41600 events.
[12:28:44.117] <TB0> INFO: 41600 events read in total (3049ms).
[12:28:44.118] <TB0> INFO: Test took 3907ms.
[12:28:44.408] <TB0> INFO: Expecting 41600 events.
[12:28:48.023] <TB0> INFO: 41600 events read in total (3023ms).
[12:28:48.024] <TB0> INFO: Test took 3881ms.
[12:28:48.312] <TB0> INFO: Expecting 41600 events.
[12:28:51.002] <TB0> INFO: 41600 events read in total (3098ms).
[12:28:52.003] <TB0> INFO: Test took 3955ms.
[12:28:52.293] <TB0> INFO: Expecting 41600 events.
[12:28:56.043] <TB0> INFO: 41600 events read in total (3158ms).
[12:28:56.044] <TB0> INFO: Test took 4016ms.
[12:28:56.337] <TB0> INFO: Expecting 41600 events.
[12:28:59.954] <TB0> INFO: 41600 events read in total (3025ms).
[12:28:59.955] <TB0> INFO: Test took 3882ms.
[12:29:00.245] <TB0> INFO: Expecting 41600 events.
[12:29:03.940] <TB0> INFO: 41600 events read in total (3104ms).
[12:29:03.941] <TB0> INFO: Test took 3961ms.
[12:29:04.234] <TB0> INFO: Expecting 41600 events.
[12:29:07.735] <TB0> INFO: 41600 events read in total (2909ms).
[12:29:07.736] <TB0> INFO: Test took 3767ms.
[12:29:08.026] <TB0> INFO: Expecting 41600 events.
[12:29:11.716] <TB0> INFO: 41600 events read in total (3099ms).
[12:29:11.717] <TB0> INFO: Test took 3956ms.
[12:29:12.013] <TB0> INFO: Expecting 41600 events.
[12:29:15.597] <TB0> INFO: 41600 events read in total (2992ms).
[12:29:15.598] <TB0> INFO: Test took 3849ms.
[12:29:15.930] <TB0> INFO: Expecting 41600 events.
[12:29:19.599] <TB0> INFO: 41600 events read in total (3078ms).
[12:29:19.600] <TB0> INFO: Test took 3967ms.
[12:29:19.894] <TB0> INFO: Expecting 2560 events.
[12:29:20.780] <TB0> INFO: 2560 events read in total (294ms).
[12:29:20.780] <TB0> INFO: Test took 1163ms.
[12:29:21.088] <TB0> INFO: Expecting 2560 events.
[12:29:21.974] <TB0> INFO: 2560 events read in total (294ms).
[12:29:21.974] <TB0> INFO: Test took 1193ms.
[12:29:22.281] <TB0> INFO: Expecting 2560 events.
[12:29:23.169] <TB0> INFO: 2560 events read in total (292ms).
[12:29:23.169] <TB0> INFO: Test took 1194ms.
[12:29:23.477] <TB0> INFO: Expecting 2560 events.
[12:29:24.364] <TB0> INFO: 2560 events read in total (295ms).
[12:29:24.364] <TB0> INFO: Test took 1195ms.
[12:29:24.674] <TB0> INFO: Expecting 2560 events.
[12:29:25.559] <TB0> INFO: 2560 events read in total (291ms).
[12:29:25.559] <TB0> INFO: Test took 1194ms.
[12:29:25.867] <TB0> INFO: Expecting 2560 events.
[12:29:26.745] <TB0> INFO: 2560 events read in total (287ms).
[12:29:26.745] <TB0> INFO: Test took 1184ms.
[12:29:27.053] <TB0> INFO: Expecting 2560 events.
[12:29:27.935] <TB0> INFO: 2560 events read in total (290ms).
[12:29:27.935] <TB0> INFO: Test took 1189ms.
[12:29:28.242] <TB0> INFO: Expecting 2560 events.
[12:29:29.130] <TB0> INFO: 2560 events read in total (296ms).
[12:29:29.130] <TB0> INFO: Test took 1195ms.
[12:29:29.438] <TB0> INFO: Expecting 2560 events.
[12:29:30.321] <TB0> INFO: 2560 events read in total (290ms).
[12:29:30.321] <TB0> INFO: Test took 1190ms.
[12:29:30.629] <TB0> INFO: Expecting 2560 events.
[12:29:31.510] <TB0> INFO: 2560 events read in total (289ms).
[12:29:31.510] <TB0> INFO: Test took 1188ms.
[12:29:31.817] <TB0> INFO: Expecting 2560 events.
[12:29:32.700] <TB0> INFO: 2560 events read in total (291ms).
[12:29:32.700] <TB0> INFO: Test took 1189ms.
[12:29:33.008] <TB0> INFO: Expecting 2560 events.
[12:29:33.895] <TB0> INFO: 2560 events read in total (295ms).
[12:29:33.895] <TB0> INFO: Test took 1194ms.
[12:29:34.204] <TB0> INFO: Expecting 2560 events.
[12:29:35.092] <TB0> INFO: 2560 events read in total (297ms).
[12:29:35.092] <TB0> INFO: Test took 1196ms.
[12:29:35.400] <TB0> INFO: Expecting 2560 events.
[12:29:36.288] <TB0> INFO: 2560 events read in total (297ms).
[12:29:36.288] <TB0> INFO: Test took 1195ms.
[12:29:36.595] <TB0> INFO: Expecting 2560 events.
[12:29:37.481] <TB0> INFO: 2560 events read in total (294ms).
[12:29:37.481] <TB0> INFO: Test took 1193ms.
[12:29:37.789] <TB0> INFO: Expecting 2560 events.
[12:29:38.679] <TB0> INFO: 2560 events read in total (298ms).
[12:29:38.679] <TB0> INFO: Test took 1197ms.
[12:29:38.683] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:29:38.988] <TB0> INFO: Expecting 655360 events.
[12:29:53.648] <TB0> INFO: 655360 events read in total (14069ms).
[12:29:53.661] <TB0> INFO: Expecting 655360 events.
[12:30:08.322] <TB0> INFO: 655360 events read in total (14258ms).
[12:30:08.344] <TB0> INFO: Expecting 655360 events.
[12:30:23.210] <TB0> INFO: 655360 events read in total (14463ms).
[12:30:23.232] <TB0> INFO: Expecting 655360 events.
[12:30:37.967] <TB0> INFO: 655360 events read in total (14332ms).
[12:30:37.993] <TB0> INFO: Expecting 655360 events.
[12:30:52.408] <TB0> INFO: 655360 events read in total (14012ms).
[12:30:52.438] <TB0> INFO: Expecting 655360 events.
[12:31:06.862] <TB0> INFO: 655360 events read in total (14022ms).
[12:31:06.910] <TB0> INFO: Expecting 655360 events.
[12:31:21.355] <TB0> INFO: 655360 events read in total (14042ms).
[12:31:21.409] <TB0> INFO: Expecting 655360 events.
[12:31:35.879] <TB0> INFO: 655360 events read in total (14066ms).
[12:31:35.928] <TB0> INFO: Expecting 655360 events.
[12:31:50.453] <TB0> INFO: 655360 events read in total (14122ms).
[12:31:50.500] <TB0> INFO: Expecting 655360 events.
[12:32:04.919] <TB0> INFO: 655360 events read in total (14016ms).
[12:32:04.972] <TB0> INFO: Expecting 655360 events.
[12:32:19.758] <TB0> INFO: 655360 events read in total (14383ms).
[12:32:19.824] <TB0> INFO: Expecting 655360 events.
[12:32:34.677] <TB0> INFO: 655360 events read in total (14448ms).
[12:32:34.750] <TB0> INFO: Expecting 655360 events.
[12:32:49.355] <TB0> INFO: 655360 events read in total (14202ms).
[12:32:49.435] <TB0> INFO: Expecting 655360 events.
[12:33:03.837] <TB0> INFO: 655360 events read in total (13999ms).
[12:33:03.930] <TB0> INFO: Expecting 655360 events.
[12:33:18.386] <TB0> INFO: 655360 events read in total (14053ms).
[12:33:18.483] <TB0> INFO: Expecting 655360 events.
[12:33:32.988] <TB0> INFO: 655360 events read in total (14102ms).
[12:33:33.160] <TB0> INFO: Test took 234477ms.
[12:33:33.294] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:33:33.551] <TB0> INFO: Expecting 655360 events.
[12:33:48.172] <TB0> INFO: 655360 events read in total (14029ms).
[12:33:48.191] <TB0> INFO: Expecting 655360 events.
[12:34:02.436] <TB0> INFO: 655360 events read in total (13841ms).
[12:34:02.453] <TB0> INFO: Expecting 655360 events.
[12:34:16.707] <TB0> INFO: 655360 events read in total (13851ms).
[12:34:16.729] <TB0> INFO: Expecting 655360 events.
[12:34:30.803] <TB0> INFO: 655360 events read in total (13671ms).
[12:34:30.842] <TB0> INFO: Expecting 655360 events.
[12:34:45.111] <TB0> INFO: 655360 events read in total (13866ms).
[12:34:45.142] <TB0> INFO: Expecting 655360 events.
[12:34:59.361] <TB0> INFO: 655360 events read in total (13816ms).
[12:34:59.395] <TB0> INFO: Expecting 655360 events.
[12:35:13.767] <TB0> INFO: 655360 events read in total (13969ms).
[12:35:13.821] <TB0> INFO: Expecting 655360 events.
[12:35:28.245] <TB0> INFO: 655360 events read in total (14021ms).
[12:35:28.287] <TB0> INFO: Expecting 655360 events.
[12:35:42.608] <TB0> INFO: 655360 events read in total (13918ms).
[12:35:42.655] <TB0> INFO: Expecting 655360 events.
[12:35:57.060] <TB0> INFO: 655360 events read in total (14002ms).
[12:35:57.111] <TB0> INFO: Expecting 655360 events.
[12:36:11.248] <TB0> INFO: 655360 events read in total (13734ms).
[12:36:11.349] <TB0> INFO: Expecting 655360 events.
[12:36:25.603] <TB0> INFO: 655360 events read in total (13851ms).
[12:36:25.670] <TB0> INFO: Expecting 655360 events.
[12:36:40.026] <TB0> INFO: 655360 events read in total (13953ms).
[12:36:40.160] <TB0> INFO: Expecting 655360 events.
[12:36:54.772] <TB0> INFO: 655360 events read in total (14210ms).
[12:36:54.865] <TB0> INFO: Expecting 655360 events.
[12:37:09.261] <TB0> INFO: 655360 events read in total (13993ms).
[12:37:09.396] <TB0> INFO: Expecting 655360 events.
[12:37:23.754] <TB0> INFO: 655360 events read in total (13955ms).
[12:37:23.885] <TB0> INFO: Test took 230591ms.
[12:37:24.072] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.079] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:24.085] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.092] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:24.098] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[12:37:24.104] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[12:37:24.110] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.116] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.122] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:24.127] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[12:37:24.133] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[12:37:24.139] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.145] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.151] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:24.157] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.164] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.171] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.176] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.183] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.189] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.195] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.201] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:24.207] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[12:37:24.213] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[12:37:24.219] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[12:37:24.225] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.231] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:24.237] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[12:37:24.243] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[12:37:24.249] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[12:37:24.255] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[12:37:24.260] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[12:37:24.267] <TB0> INFO: safety margin for low PH: adding 7, margin is now 27
[12:37:24.273] <TB0> INFO: safety margin for low PH: adding 8, margin is now 28
[12:37:24.278] <TB0> INFO: safety margin for low PH: adding 9, margin is now 29
[12:37:24.285] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.291] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:24.324] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C0.dat
[12:37:24.325] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C1.dat
[12:37:24.325] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C2.dat
[12:37:24.325] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C3.dat
[12:37:24.325] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C4.dat
[12:37:24.325] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C5.dat
[12:37:24.325] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C6.dat
[12:37:24.325] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C7.dat
[12:37:24.325] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C8.dat
[12:37:24.325] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C9.dat
[12:37:24.326] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C10.dat
[12:37:24.326] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C11.dat
[12:37:24.326] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C12.dat
[12:37:24.326] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C13.dat
[12:37:24.326] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C14.dat
[12:37:24.326] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C15.dat
[12:37:24.566] <TB0> INFO: Expecting 41600 events.
[12:37:27.677] <TB0> INFO: 41600 events read in total (2519ms).
[12:37:27.678] <TB0> INFO: Test took 3350ms.
[12:37:28.127] <TB0> INFO: Expecting 41600 events.
[12:37:31.164] <TB0> INFO: 41600 events read in total (2445ms).
[12:37:31.165] <TB0> INFO: Test took 3276ms.
[12:37:31.621] <TB0> INFO: Expecting 41600 events.
[12:37:34.849] <TB0> INFO: 41600 events read in total (2636ms).
[12:37:34.850] <TB0> INFO: Test took 3475ms.
[12:37:35.065] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:35.156] <TB0> INFO: Expecting 2560 events.
[12:37:36.040] <TB0> INFO: 2560 events read in total (293ms).
[12:37:36.040] <TB0> INFO: Test took 975ms.
[12:37:36.043] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:36.349] <TB0> INFO: Expecting 2560 events.
[12:37:37.236] <TB0> INFO: 2560 events read in total (296ms).
[12:37:37.236] <TB0> INFO: Test took 1193ms.
[12:37:37.238] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:37.544] <TB0> INFO: Expecting 2560 events.
[12:37:38.428] <TB0> INFO: 2560 events read in total (292ms).
[12:37:38.428] <TB0> INFO: Test took 1190ms.
[12:37:38.430] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:38.736] <TB0> INFO: Expecting 2560 events.
[12:37:39.619] <TB0> INFO: 2560 events read in total (291ms).
[12:37:39.619] <TB0> INFO: Test took 1189ms.
[12:37:39.622] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:39.927] <TB0> INFO: Expecting 2560 events.
[12:37:40.815] <TB0> INFO: 2560 events read in total (296ms).
[12:37:40.816] <TB0> INFO: Test took 1194ms.
[12:37:40.822] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:41.124] <TB0> INFO: Expecting 2560 events.
[12:37:42.008] <TB0> INFO: 2560 events read in total (293ms).
[12:37:42.008] <TB0> INFO: Test took 1187ms.
[12:37:42.010] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:42.319] <TB0> INFO: Expecting 2560 events.
[12:37:43.201] <TB0> INFO: 2560 events read in total (290ms).
[12:37:43.202] <TB0> INFO: Test took 1192ms.
[12:37:43.204] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:43.510] <TB0> INFO: Expecting 2560 events.
[12:37:44.394] <TB0> INFO: 2560 events read in total (293ms).
[12:37:44.394] <TB0> INFO: Test took 1190ms.
[12:37:44.398] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:44.706] <TB0> INFO: Expecting 2560 events.
[12:37:45.590] <TB0> INFO: 2560 events read in total (292ms).
[12:37:45.590] <TB0> INFO: Test took 1192ms.
[12:37:45.594] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:45.898] <TB0> INFO: Expecting 2560 events.
[12:37:46.777] <TB0> INFO: 2560 events read in total (287ms).
[12:37:46.777] <TB0> INFO: Test took 1183ms.
[12:37:46.779] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:47.086] <TB0> INFO: Expecting 2560 events.
[12:37:47.967] <TB0> INFO: 2560 events read in total (290ms).
[12:37:47.968] <TB0> INFO: Test took 1189ms.
[12:37:47.970] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:48.276] <TB0> INFO: Expecting 2560 events.
[12:37:49.157] <TB0> INFO: 2560 events read in total (289ms).
[12:37:49.157] <TB0> INFO: Test took 1187ms.
[12:37:49.159] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:49.465] <TB0> INFO: Expecting 2560 events.
[12:37:50.347] <TB0> INFO: 2560 events read in total (291ms).
[12:37:50.348] <TB0> INFO: Test took 1189ms.
[12:37:50.350] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:50.656] <TB0> INFO: Expecting 2560 events.
[12:37:51.536] <TB0> INFO: 2560 events read in total (288ms).
[12:37:51.536] <TB0> INFO: Test took 1186ms.
[12:37:51.539] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:51.844] <TB0> INFO: Expecting 2560 events.
[12:37:52.723] <TB0> INFO: 2560 events read in total (287ms).
[12:37:52.724] <TB0> INFO: Test took 1186ms.
[12:37:52.726] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:53.032] <TB0> INFO: Expecting 2560 events.
[12:37:53.910] <TB0> INFO: 2560 events read in total (286ms).
[12:37:53.910] <TB0> INFO: Test took 1184ms.
[12:37:53.912] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:54.219] <TB0> INFO: Expecting 2560 events.
[12:37:55.098] <TB0> INFO: 2560 events read in total (287ms).
[12:37:55.098] <TB0> INFO: Test took 1186ms.
[12:37:55.100] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:55.407] <TB0> INFO: Expecting 2560 events.
[12:37:56.289] <TB0> INFO: 2560 events read in total (291ms).
[12:37:56.290] <TB0> INFO: Test took 1190ms.
[12:37:56.292] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:56.597] <TB0> INFO: Expecting 2560 events.
[12:37:57.476] <TB0> INFO: 2560 events read in total (287ms).
[12:37:57.476] <TB0> INFO: Test took 1184ms.
[12:37:57.481] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:57.786] <TB0> INFO: Expecting 2560 events.
[12:37:58.666] <TB0> INFO: 2560 events read in total (287ms).
[12:37:58.667] <TB0> INFO: Test took 1186ms.
[12:37:58.670] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:58.977] <TB0> INFO: Expecting 2560 events.
[12:37:59.857] <TB0> INFO: 2560 events read in total (288ms).
[12:37:59.857] <TB0> INFO: Test took 1187ms.
[12:37:59.860] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:38:00.168] <TB0> INFO: Expecting 2560 events.
[12:38:01.047] <TB0> INFO: 2560 events read in total (287ms).
[12:38:01.047] <TB0> INFO: Test took 1187ms.
[12:38:01.049] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:38:01.355] <TB0> INFO: Expecting 2560 events.
[12:38:02.238] <TB0> INFO: 2560 events read in total (291ms).
[12:38:02.238] <TB0> INFO: Test took 1190ms.
[12:38:02.244] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:38:02.546] <TB0> INFO: Expecting 2560 events.
[12:38:03.424] <TB0> INFO: 2560 events read in total (286ms).
[12:38:03.425] <TB0> INFO: Test took 1181ms.
[12:38:03.427] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:38:03.733] <TB0> INFO: Expecting 2560 events.
[12:38:04.630] <TB0> INFO: 2560 events read in total (305ms).
[12:38:04.630] <TB0> INFO: Test took 1203ms.
[12:38:04.632] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:38:04.938] <TB0> INFO: Expecting 2560 events.
[12:38:05.826] <TB0> INFO: 2560 events read in total (296ms).
[12:38:05.827] <TB0> INFO: Test took 1195ms.
[12:38:05.834] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:38:06.135] <TB0> INFO: Expecting 2560 events.
[12:38:07.024] <TB0> INFO: 2560 events read in total (297ms).
[12:38:07.024] <TB0> INFO: Test took 1190ms.
[12:38:07.026] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:38:07.332] <TB0> INFO: Expecting 2560 events.
[12:38:08.219] <TB0> INFO: 2560 events read in total (295ms).
[12:38:08.220] <TB0> INFO: Test took 1194ms.
[12:38:08.222] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:38:08.528] <TB0> INFO: Expecting 2560 events.
[12:38:09.415] <TB0> INFO: 2560 events read in total (296ms).
[12:38:09.415] <TB0> INFO: Test took 1193ms.
[12:38:09.418] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:38:09.723] <TB0> INFO: Expecting 2560 events.
[12:38:10.607] <TB0> INFO: 2560 events read in total (293ms).
[12:38:10.607] <TB0> INFO: Test took 1189ms.
[12:38:10.612] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:38:10.915] <TB0> INFO: Expecting 2560 events.
[12:38:11.799] <TB0> INFO: 2560 events read in total (292ms).
[12:38:11.800] <TB0> INFO: Test took 1188ms.
[12:38:11.802] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:38:12.108] <TB0> INFO: Expecting 2560 events.
[12:38:12.001] <TB0> INFO: 2560 events read in total (301ms).
[12:38:12.001] <TB0> INFO: Test took 1199ms.
[12:38:13.465] <TB0> INFO: PixTestPhOptimization::doTest() done, duration: 636 seconds
[12:38:13.465] <TB0> INFO: PH scale (per ROC): 51 38 43 48 42 31 49 31 40 42 40 39 34 48 40 33
[12:38:13.465] <TB0> INFO: PH offset (per ROC): 129 102 104 131 111 93 126 106 111 104 94 103 103 108 102 99
[12:38:13.474] <TB0> INFO: Decoding statistics:
[12:38:13.475] <TB0> INFO: General information:
[12:38:13.475] <TB0> INFO: 16bit words read: 127892
[12:38:13.475] <TB0> INFO: valid events total: 20480
[12:38:13.475] <TB0> INFO: empty events: 17974
[12:38:13.475] <TB0> INFO: valid events with pixels: 2506
[12:38:13.475] <TB0> INFO: valid pixel hits: 2506
[12:38:13.475] <TB0> INFO: Event errors: 0
[12:38:13.475] <TB0> INFO: start marker: 0
[12:38:13.475] <TB0> INFO: stop marker: 0
[12:38:13.475] <TB0> INFO: overflow: 0
[12:38:13.475] <TB0> INFO: invalid 5bit words: 0
[12:38:13.475] <TB0> INFO: invalid XOR eye diagram: 0
[12:38:13.475] <TB0> INFO: frame (failed synchr.): 0
[12:38:13.475] <TB0> INFO: idle data (no TBM trl): 0
[12:38:13.475] <TB0> INFO: no data (only TBM hdr): 0
[12:38:13.475] <TB0> INFO: TBM errors: 0
[12:38:13.475] <TB0> INFO: flawed TBM headers: 0
[12:38:13.475] <TB0> INFO: flawed TBM trailers: 0
[12:38:13.475] <TB0> INFO: event ID mismatches: 0
[12:38:13.475] <TB0> INFO: ROC errors: 0
[12:38:13.475] <TB0> INFO: missing ROC header(s): 0
[12:38:13.475] <TB0> INFO: misplaced readback start: 0
[12:38:13.475] <TB0> INFO: Pixel decoding errors: 0
[12:38:13.475] <TB0> INFO: pixel data incomplete: 0
[12:38:13.475] <TB0> INFO: pixel address: 0
[12:38:13.475] <TB0> INFO: pulse height fill bit: 0
[12:38:13.475] <TB0> INFO: buffer corruption: 0
[12:38:13.645] <TB0> INFO: ######################################################################
[12:38:13.646] <TB0> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[12:38:13.646] <TB0> INFO: ######################################################################
[12:38:13.662] <TB0> INFO: scanning low vcal = 10
[12:38:13.898] <TB0> INFO: Expecting 41600 events.
[12:38:17.461] <TB0> INFO: 41600 events read in total (2971ms).
[12:38:17.461] <TB0> INFO: Test took 3799ms.
[12:38:17.463] <TB0> INFO: scanning low vcal = 20
[12:38:17.758] <TB0> INFO: Expecting 41600 events.
[12:38:21.325] <TB0> INFO: 41600 events read in total (2975ms).
[12:38:21.326] <TB0> INFO: Test took 3863ms.
[12:38:21.331] <TB0> INFO: scanning low vcal = 30
[12:38:21.622] <TB0> INFO: Expecting 41600 events.
[12:38:25.260] <TB0> INFO: 41600 events read in total (3047ms).
[12:38:25.261] <TB0> INFO: Test took 3929ms.
[12:38:25.264] <TB0> INFO: scanning low vcal = 40
[12:38:25.541] <TB0> INFO: Expecting 41600 events.
[12:38:29.544] <TB0> INFO: 41600 events read in total (3412ms).
[12:38:29.545] <TB0> INFO: Test took 4281ms.
[12:38:29.549] <TB0> INFO: scanning low vcal = 50
[12:38:29.894] <TB0> INFO: Expecting 41600 events.
[12:38:33.842] <TB0> INFO: 41600 events read in total (3356ms).
[12:38:33.843] <TB0> INFO: Test took 4294ms.
[12:38:33.846] <TB0> INFO: scanning low vcal = 60
[12:38:34.122] <TB0> INFO: Expecting 41600 events.
[12:38:38.086] <TB0> INFO: 41600 events read in total (3372ms).
[12:38:38.087] <TB0> INFO: Test took 4240ms.
[12:38:38.090] <TB0> INFO: scanning low vcal = 70
[12:38:38.367] <TB0> INFO: Expecting 41600 events.
[12:38:42.338] <TB0> INFO: 41600 events read in total (3380ms).
[12:38:42.339] <TB0> INFO: Test took 4248ms.
[12:38:42.342] <TB0> INFO: scanning low vcal = 80
[12:38:42.619] <TB0> INFO: Expecting 41600 events.
[12:38:46.601] <TB0> INFO: 41600 events read in total (3390ms).
[12:38:46.602] <TB0> INFO: Test took 4260ms.
[12:38:46.605] <TB0> INFO: scanning low vcal = 90
[12:38:46.882] <TB0> INFO: Expecting 41600 events.
[12:38:50.856] <TB0> INFO: 41600 events read in total (3383ms).
[12:38:50.857] <TB0> INFO: Test took 4252ms.
[12:38:50.861] <TB0> INFO: scanning low vcal = 100
[12:38:51.137] <TB0> INFO: Expecting 41600 events.
[12:38:55.087] <TB0> INFO: 41600 events read in total (3359ms).
[12:38:55.088] <TB0> INFO: Test took 4227ms.
[12:38:55.090] <TB0> INFO: scanning low vcal = 110
[12:38:55.381] <TB0> INFO: Expecting 41600 events.
[12:38:59.374] <TB0> INFO: 41600 events read in total (3402ms).
[12:38:59.375] <TB0> INFO: Test took 4284ms.
[12:38:59.378] <TB0> INFO: scanning low vcal = 120
[12:38:59.654] <TB0> INFO: Expecting 41600 events.
[12:39:03.624] <TB0> INFO: 41600 events read in total (3378ms).
[12:39:03.625] <TB0> INFO: Test took 4247ms.
[12:39:03.630] <TB0> INFO: scanning low vcal = 130
[12:39:03.905] <TB0> INFO: Expecting 41600 events.
[12:39:07.890] <TB0> INFO: 41600 events read in total (3393ms).
[12:39:07.891] <TB0> INFO: Test took 4260ms.
[12:39:07.894] <TB0> INFO: scanning low vcal = 140
[12:39:08.171] <TB0> INFO: Expecting 41600 events.
[12:39:12.144] <TB0> INFO: 41600 events read in total (3381ms).
[12:39:12.145] <TB0> INFO: Test took 4251ms.
[12:39:12.148] <TB0> INFO: scanning low vcal = 150
[12:39:12.424] <TB0> INFO: Expecting 41600 events.
[12:39:16.397] <TB0> INFO: 41600 events read in total (3381ms).
[12:39:16.398] <TB0> INFO: Test took 4250ms.
[12:39:16.402] <TB0> INFO: scanning low vcal = 160
[12:39:16.696] <TB0> INFO: Expecting 41600 events.
[12:39:20.621] <TB0> INFO: 41600 events read in total (3334ms).
[12:39:20.622] <TB0> INFO: Test took 4220ms.
[12:39:20.625] <TB0> INFO: scanning low vcal = 170
[12:39:20.901] <TB0> INFO: Expecting 41600 events.
[12:39:24.861] <TB0> INFO: 41600 events read in total (3368ms).
[12:39:24.862] <TB0> INFO: Test took 4237ms.
[12:39:24.867] <TB0> INFO: scanning low vcal = 180
[12:39:25.142] <TB0> INFO: Expecting 41600 events.
[12:39:29.075] <TB0> INFO: 41600 events read in total (3342ms).
[12:39:29.076] <TB0> INFO: Test took 4209ms.
[12:39:29.079] <TB0> INFO: scanning low vcal = 190
[12:39:29.355] <TB0> INFO: Expecting 41600 events.
[12:39:33.339] <TB0> INFO: 41600 events read in total (3392ms).
[12:39:33.340] <TB0> INFO: Test took 4261ms.
[12:39:33.343] <TB0> INFO: scanning low vcal = 200
[12:39:33.620] <TB0> INFO: Expecting 41600 events.
[12:39:37.623] <TB0> INFO: 41600 events read in total (3411ms).
[12:39:37.624] <TB0> INFO: Test took 4280ms.
[12:39:37.628] <TB0> INFO: scanning low vcal = 210
[12:39:38.009] <TB0> INFO: Expecting 41600 events.
[12:39:41.984] <TB0> INFO: 41600 events read in total (3384ms).
[12:39:41.984] <TB0> INFO: Test took 4356ms.
[12:39:41.987] <TB0> INFO: scanning low vcal = 220
[12:39:42.264] <TB0> INFO: Expecting 41600 events.
[12:39:46.237] <TB0> INFO: 41600 events read in total (3381ms).
[12:39:46.238] <TB0> INFO: Test took 4250ms.
[12:39:46.241] <TB0> INFO: scanning low vcal = 230
[12:39:46.517] <TB0> INFO: Expecting 41600 events.
[12:39:50.573] <TB0> INFO: 41600 events read in total (3464ms).
[12:39:50.573] <TB0> INFO: Test took 4332ms.
[12:39:50.576] <TB0> INFO: scanning low vcal = 240
[12:39:50.874] <TB0> INFO: Expecting 41600 events.
[12:39:54.885] <TB0> INFO: 41600 events read in total (3419ms).
[12:39:54.886] <TB0> INFO: Test took 4310ms.
[12:39:54.889] <TB0> INFO: scanning low vcal = 250
[12:39:55.166] <TB0> INFO: Expecting 41600 events.
[12:39:59.127] <TB0> INFO: 41600 events read in total (3369ms).
[12:39:59.128] <TB0> INFO: Test took 4238ms.
[12:39:59.133] <TB0> INFO: scanning high vcal = 30 (= 210 in low range)
[12:39:59.482] <TB0> INFO: Expecting 41600 events.
[12:40:03.466] <TB0> INFO: 41600 events read in total (3392ms).
[12:40:03.467] <TB0> INFO: Test took 4334ms.
[12:40:03.470] <TB0> INFO: scanning high vcal = 50 (= 350 in low range)
[12:40:03.746] <TB0> INFO: Expecting 41600 events.
[12:40:07.706] <TB0> INFO: 41600 events read in total (3368ms).
[12:40:07.707] <TB0> INFO: Test took 4237ms.
[12:40:07.710] <TB0> INFO: scanning high vcal = 70 (= 490 in low range)
[12:40:07.995] <TB0> INFO: Expecting 41600 events.
[12:40:11.994] <TB0> INFO: 41600 events read in total (3408ms).
[12:40:11.995] <TB0> INFO: Test took 4285ms.
[12:40:11.999] <TB0> INFO: scanning high vcal = 90 (= 630 in low range)
[12:40:12.275] <TB0> INFO: Expecting 41600 events.
[12:40:16.320] <TB0> INFO: 41600 events read in total (3454ms).
[12:40:16.321] <TB0> INFO: Test took 4322ms.
[12:40:16.324] <TB0> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:40:16.601] <TB0> INFO: Expecting 41600 events.
[12:40:20.601] <TB0> INFO: 41600 events read in total (3408ms).
[12:40:20.602] <TB0> INFO: Test took 4278ms.
[12:40:20.995] <TB0> INFO: PixTestGainPedestal::measure() done
[12:40:55.716] <TB0> INFO: PixTestGainPedestal::fit() done
[12:40:55.716] <TB0> INFO: non-linearity mean: 0.985 0.963 0.940 0.984 0.938 1.028 0.978 0.949 0.947 0.941 0.946 0.932 0.986 0.950 0.947 0.922
[12:40:55.716] <TB0> INFO: non-linearity RMS: 0.004 0.159 0.063 0.003 0.055 0.173 0.006 0.145 0.140 0.087 0.049 0.082 0.164 0.064 0.076 0.103
[12:40:55.716] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[12:40:55.733] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[12:40:55.746] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[12:40:55.759] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[12:40:55.772] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[12:40:55.785] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[12:40:55.798] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[12:40:55.811] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[12:40:55.824] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[12:40:55.837] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[12:40:55.850] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[12:40:55.864] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[12:40:55.877] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[12:40:55.891] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[12:40:55.906] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[12:40:55.919] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[12:40:55.933] <TB0> INFO: PixTestGainPedestal::fullTest() done, duration: 162 seconds
[12:40:55.933] <TB0> INFO: Decoding statistics:
[12:40:55.933] <TB0> INFO: General information:
[12:40:55.933] <TB0> INFO: 16bit words read: 3314390
[12:40:55.933] <TB0> INFO: valid events total: 332800
[12:40:55.933] <TB0> INFO: empty events: 7
[12:40:55.933] <TB0> INFO: valid events with pixels: 332793
[12:40:55.933] <TB0> INFO: valid pixel hits: 658795
[12:40:55.933] <TB0> INFO: Event errors: 0
[12:40:55.933] <TB0> INFO: start marker: 0
[12:40:55.933] <TB0> INFO: stop marker: 0
[12:40:55.933] <TB0> INFO: overflow: 0
[12:40:55.933] <TB0> INFO: invalid 5bit words: 0
[12:40:55.933] <TB0> INFO: invalid XOR eye diagram: 0
[12:40:55.933] <TB0> INFO: frame (failed synchr.): 0
[12:40:55.933] <TB0> INFO: idle data (no TBM trl): 0
[12:40:55.933] <TB0> INFO: no data (only TBM hdr): 0
[12:40:55.933] <TB0> INFO: TBM errors: 0
[12:40:55.933] <TB0> INFO: flawed TBM headers: 0
[12:40:55.933] <TB0> INFO: flawed TBM trailers: 0
[12:40:55.933] <TB0> INFO: event ID mismatches: 0
[12:40:55.933] <TB0> INFO: ROC errors: 0
[12:40:55.933] <TB0> INFO: missing ROC header(s): 0
[12:40:55.933] <TB0> INFO: misplaced readback start: 0
[12:40:55.933] <TB0> INFO: Pixel decoding errors: 0
[12:40:55.933] <TB0> INFO: pixel data incomplete: 0
[12:40:55.933] <TB0> INFO: pixel address: 0
[12:40:55.933] <TB0> INFO: pulse height fill bit: 0
[12:40:55.933] <TB0> INFO: buffer corruption: 0
[12:40:55.952] <TB0> INFO: Decoding statistics:
[12:40:55.952] <TB0> INFO: General information:
[12:40:55.952] <TB0> INFO: 16bit words read: 3443818
[12:40:55.952] <TB0> INFO: valid events total: 353536
[12:40:55.952] <TB0> INFO: empty events: 18237
[12:40:55.952] <TB0> INFO: valid events with pixels: 335299
[12:40:55.952] <TB0> INFO: valid pixel hits: 661301
[12:40:55.952] <TB0> INFO: Event errors: 0
[12:40:55.952] <TB0> INFO: start marker: 0
[12:40:55.952] <TB0> INFO: stop marker: 0
[12:40:55.952] <TB0> INFO: overflow: 0
[12:40:55.952] <TB0> INFO: invalid 5bit words: 0
[12:40:55.952] <TB0> INFO: invalid XOR eye diagram: 0
[12:40:55.952] <TB0> INFO: frame (failed synchr.): 0
[12:40:55.952] <TB0> INFO: idle data (no TBM trl): 0
[12:40:55.952] <TB0> INFO: no data (only TBM hdr): 0
[12:40:55.952] <TB0> INFO: TBM errors: 0
[12:40:55.952] <TB0> INFO: flawed TBM headers: 0
[12:40:55.952] <TB0> INFO: flawed TBM trailers: 0
[12:40:55.952] <TB0> INFO: event ID mismatches: 0
[12:40:55.952] <TB0> INFO: ROC errors: 0
[12:40:55.952] <TB0> INFO: missing ROC header(s): 0
[12:40:55.952] <TB0> INFO: misplaced readback start: 0
[12:40:55.952] <TB0> INFO: Pixel decoding errors: 0
[12:40:55.952] <TB0> INFO: pixel data incomplete: 0
[12:40:55.952] <TB0> INFO: pixel address: 0
[12:40:55.952] <TB0> INFO: pulse height fill bit: 0
[12:40:55.952] <TB0> INFO: buffer corruption: 0
[12:40:55.952] <TB0> INFO: enter test to run
[12:40:55.952] <TB0> INFO: test: trim80 no parameter change
[12:40:55.952] <TB0> INFO: running: trim80
[12:40:55.956] <TB0> INFO: ######################################################################
[12:40:55.956] <TB0> INFO: PixTestTrim80::doTest()
[12:40:55.956] <TB0> INFO: ######################################################################
[12:40:55.957] <TB0> INFO: ----------------------------------------------------------------------
[12:40:55.957] <TB0> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[12:40:55.957] <TB0> INFO: ----------------------------------------------------------------------
[12:40:55.998] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:40:55.998] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:40:56.010] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:40:56.010] <TB0> INFO: run 1 of 1
[12:40:56.246] <TB0> INFO: Expecting 5025280 events.
[12:41:26.271] <TB0> INFO: 683128 events read in total (29433ms).
[12:41:54.906] <TB0> INFO: 1362304 events read in total (58068ms).
[12:42:22.832] <TB0> INFO: 2040768 events read in total (85994ms).
[12:42:50.937] <TB0> INFO: 2717688 events read in total (114099ms).
[12:43:18.980] <TB0> INFO: 3394000 events read in total (142142ms).
[12:43:48.216] <TB0> INFO: 4069160 events read in total (171378ms).
[12:44:16.763] <TB0> INFO: 4743312 events read in total (199925ms).
[12:44:28.855] <TB0> INFO: 5025280 events read in total (212017ms).
[12:44:28.938] <TB0> INFO: Test took 212928ms.
[12:44:50.591] <TB0> INFO: ROC 0 VthrComp = 71
[12:44:50.591] <TB0> INFO: ROC 1 VthrComp = 71
[12:44:50.592] <TB0> INFO: ROC 2 VthrComp = 73
[12:44:50.592] <TB0> INFO: ROC 3 VthrComp = 72
[12:44:50.592] <TB0> INFO: ROC 4 VthrComp = 71
[12:44:50.595] <TB0> INFO: ROC 5 VthrComp = 83
[12:44:50.596] <TB0> INFO: ROC 6 VthrComp = 77
[12:44:50.597] <TB0> INFO: ROC 7 VthrComp = 72
[12:44:50.597] <TB0> INFO: ROC 8 VthrComp = 74
[12:44:50.597] <TB0> INFO: ROC 9 VthrComp = 71
[12:44:50.597] <TB0> INFO: ROC 10 VthrComp = 71
[12:44:50.597] <TB0> INFO: ROC 11 VthrComp = 73
[12:44:50.597] <TB0> INFO: ROC 12 VthrComp = 76
[12:44:50.598] <TB0> INFO: ROC 13 VthrComp = 76
[12:44:50.598] <TB0> INFO: ROC 14 VthrComp = 71
[12:44:50.598] <TB0> INFO: ROC 15 VthrComp = 73
[12:44:50.838] <TB0> INFO: Expecting 41600 events.
[12:44:54.505] <TB0> INFO: 41600 events read in total (3075ms).
[12:44:54.505] <TB0> INFO: Test took 3906ms.
[12:44:54.518] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:44:54.518] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:44:54.533] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:44:54.533] <TB0> INFO: run 1 of 1
[12:44:54.850] <TB0> INFO: Expecting 5025280 events.
[12:45:23.863] <TB0> INFO: 682432 events read in total (28422ms).
[12:45:51.573] <TB0> INFO: 1361448 events read in total (56132ms).
[12:46:19.525] <TB0> INFO: 2039680 events read in total (84084ms).
[12:46:47.708] <TB0> INFO: 2713192 events read in total (112267ms).
[12:47:16.208] <TB0> INFO: 3383864 events read in total (140767ms).
[12:47:44.430] <TB0> INFO: 4053704 events read in total (168989ms).
[12:48:12.370] <TB0> INFO: 4723480 events read in total (196929ms).
[12:48:25.273] <TB0> INFO: 5025280 events read in total (209832ms).
[12:48:25.346] <TB0> INFO: Test took 210813ms.
[12:48:49.138] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 102.336 for pixel 18/78 mean/min/max = 87.9603/73.3794/102.541
[12:48:49.139] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 107.289 for pixel 14/62 mean/min/max = 90.4658/73.5979/107.334
[12:48:49.139] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 108.926 for pixel 32/79 mean/min/max = 93.6732/78.3803/108.966
[12:48:49.140] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 109.304 for pixel 16/79 mean/min/max = 93.5791/77.728/109.43
[12:48:49.140] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 106.48 for pixel 0/79 mean/min/max = 90.3323/74.0436/106.621
[12:48:49.141] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 107.042 for pixel 0/79 mean/min/max = 91.2862/75.3352/107.237
[12:48:49.141] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 107.666 for pixel 0/43 mean/min/max = 93.1823/78.6682/107.696
[12:48:49.142] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 113.943 for pixel 0/76 mean/min/max = 95.6186/77.161/114.076
[12:48:49.142] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 109.968 for pixel 0/79 mean/min/max = 93.9452/77.8643/110.026
[12:48:49.143] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 108.111 for pixel 51/0 mean/min/max = 91.1402/73.9821/108.298
[12:48:49.143] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 109.84 for pixel 2/74 mean/min/max = 92.1242/73.9781/110.27
[12:48:49.144] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 110.04 for pixel 0/69 mean/min/max = 93.7129/77.1988/110.227
[12:48:49.144] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 108.559 for pixel 51/12 mean/min/max = 94.1152/79.2358/108.995
[12:48:49.145] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 108.606 for pixel 0/18 mean/min/max = 93.8823/79.1232/108.641
[12:48:49.145] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 107.186 for pixel 0/13 mean/min/max = 90.3335/73.4585/107.208
[12:48:49.146] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 108.314 for pixel 6/1 mean/min/max = 92.22/76.1247/108.315
[12:48:49.146] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:48:49.235] <TB0> INFO: Expecting 411648 events.
[12:48:58.793] <TB0> INFO: 411648 events read in total (8966ms).
[12:48:58.801] <TB0> INFO: Expecting 411648 events.
[12:49:08.167] <TB0> INFO: 411648 events read in total (8963ms).
[12:49:08.181] <TB0> INFO: Expecting 411648 events.
[12:49:17.524] <TB0> INFO: 411648 events read in total (8940ms).
[12:49:17.542] <TB0> INFO: Expecting 411648 events.
[12:49:27.055] <TB0> INFO: 411648 events read in total (9102ms).
[12:49:27.078] <TB0> INFO: Expecting 411648 events.
[12:49:36.628] <TB0> INFO: 411648 events read in total (9147ms).
[12:49:36.648] <TB0> INFO: Expecting 411648 events.
[12:49:45.940] <TB0> INFO: 411648 events read in total (8889ms).
[12:49:45.970] <TB0> INFO: Expecting 411648 events.
[12:49:55.353] <TB0> INFO: 411648 events read in total (8980ms).
[12:49:55.385] <TB0> INFO: Expecting 411648 events.
[12:50:04.588] <TB0> INFO: 411648 events read in total (8800ms).
[12:50:04.620] <TB0> INFO: Expecting 411648 events.
[12:50:13.803] <TB0> INFO: 411648 events read in total (8780ms).
[12:50:13.860] <TB0> INFO: Expecting 411648 events.
[12:50:23.274] <TB0> INFO: 411648 events read in total (9011ms).
[12:50:23.315] <TB0> INFO: Expecting 411648 events.
[12:50:32.601] <TB0> INFO: 411648 events read in total (8880ms).
[12:50:32.644] <TB0> INFO: Expecting 411648 events.
[12:50:41.894] <TB0> INFO: 411648 events read in total (8847ms).
[12:50:41.938] <TB0> INFO: Expecting 411648 events.
[12:50:51.299] <TB0> INFO: 411648 events read in total (8958ms).
[12:50:51.354] <TB0> INFO: Expecting 411648 events.
[12:51:00.569] <TB0> INFO: 411648 events read in total (8812ms).
[12:51:00.631] <TB0> INFO: Expecting 411648 events.
[12:51:09.984] <TB0> INFO: 411648 events read in total (8950ms).
[12:51:10.054] <TB0> INFO: Expecting 411648 events.
[12:51:19.373] <TB0> INFO: 411648 events read in total (8916ms).
[12:51:19.438] <TB0> INFO: Test took 150292ms.
[12:51:21.400] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:51:21.417] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:51:21.417] <TB0> INFO: run 1 of 1
[12:51:21.791] <TB0> INFO: Expecting 5025280 events.
[12:51:50.802] <TB0> INFO: 668864 events read in total (28419ms).
[12:52:18.530] <TB0> INFO: 1335648 events read in total (56147ms).
[12:52:46.035] <TB0> INFO: 2001936 events read in total (83652ms).
[12:53:13.572] <TB0> INFO: 2665344 events read in total (111189ms).
[12:53:41.803] <TB0> INFO: 3325272 events read in total (139420ms).
[12:54:09.459] <TB0> INFO: 3983816 events read in total (167076ms).
[12:54:36.812] <TB0> INFO: 4640880 events read in total (194429ms).
[12:54:53.476] <TB0> INFO: 5025280 events read in total (211093ms).
[12:54:53.538] <TB0> INFO: Test took 212121ms.
[12:55:15.896] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 51.061359 .. 105.469861
[12:55:16.136] <TB0> INFO: Expecting 208000 events.
[12:55:26.568] <TB0> INFO: 208000 events read in total (9840ms).
[12:55:26.569] <TB0> INFO: Test took 10672ms.
[12:55:26.657] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 41 .. 115 (-1/-1) hits flags = 528 (plus default)
[12:55:26.676] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:55:26.676] <TB0> INFO: run 1 of 1
[12:55:26.955] <TB0> INFO: Expecting 2496000 events.
[12:55:55.627] <TB0> INFO: 679416 events read in total (28080ms).
[12:56:23.814] <TB0> INFO: 1356120 events read in total (56267ms).
[12:56:52.027] <TB0> INFO: 2027200 events read in total (84480ms).
[12:57:11.779] <TB0> INFO: 2496000 events read in total (104232ms).
[12:57:11.831] <TB0> INFO: Test took 105154ms.
[12:57:30.288] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 60.070658 .. 94.796131
[12:57:30.535] <TB0> INFO: Expecting 208000 events.
[12:57:41.169] <TB0> INFO: 208000 events read in total (10041ms).
[12:57:41.170] <TB0> INFO: Test took 10880ms.
[12:57:41.220] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 50 .. 104 (-1/-1) hits flags = 528 (plus default)
[12:57:41.234] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:57:41.234] <TB0> INFO: run 1 of 1
[12:57:41.512] <TB0> INFO: Expecting 1830400 events.
[12:58:11.968] <TB0> INFO: 687008 events read in total (29864ms).
[12:58:40.721] <TB0> INFO: 1372808 events read in total (58618ms).
[12:59:00.139] <TB0> INFO: 1830400 events read in total (78035ms).
[12:59:00.188] <TB0> INFO: Test took 78954ms.
[12:59:17.745] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 64.513178 .. 91.084135
[12:59:17.982] <TB0> INFO: Expecting 208000 events.
[12:59:28.197] <TB0> INFO: 208000 events read in total (9623ms).
[12:59:28.198] <TB0> INFO: Test took 10452ms.
[12:59:28.247] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 54 .. 101 (-1/-1) hits flags = 528 (plus default)
[12:59:28.261] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:59:28.261] <TB0> INFO: run 1 of 1
[12:59:28.539] <TB0> INFO: Expecting 1597440 events.
[12:59:58.105] <TB0> INFO: 686424 events read in total (28974ms).
[13:00:27.300] <TB0> INFO: 1372040 events read in total (58169ms).
[13:00:37.315] <TB0> INFO: 1597440 events read in total (68184ms).
[13:00:37.354] <TB0> INFO: Test took 69093ms.
[13:00:54.507] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 67.278660 .. 91.084135
[13:00:54.773] <TB0> INFO: Expecting 208000 events.
[13:01:05.226] <TB0> INFO: 208000 events read in total (9861ms).
[13:01:05.226] <TB0> INFO: Test took 10718ms.
[13:01:05.306] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 57 .. 101 (-1/-1) hits flags = 528 (plus default)
[13:01:05.320] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:01:05.320] <TB0> INFO: run 1 of 1
[13:01:05.646] <TB0> INFO: Expecting 1497600 events.
[13:01:35.808] <TB0> INFO: 677720 events read in total (29570ms).
[13:02:05.051] <TB0> INFO: 1355000 events read in total (58813ms).
[13:02:11.561] <TB0> INFO: 1497600 events read in total (65324ms).
[13:02:11.602] <TB0> INFO: Test took 66282ms.
[13:02:31.441] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[13:02:31.441] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[13:02:31.455] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:02:31.455] <TB0> INFO: run 1 of 1
[13:02:31.694] <TB0> INFO: Expecting 1364480 events.
[13:03:01.431] <TB0> INFO: 669000 events read in total (29145ms).
[13:03:31.316] <TB0> INFO: 1337184 events read in total (59030ms).
[13:03:32.989] <TB0> INFO: 1364480 events read in total (60703ms).
[13:03:33.011] <TB0> INFO: Test took 61557ms.
[13:03:48.551] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C0.dat
[13:03:48.551] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C1.dat
[13:03:48.551] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C2.dat
[13:03:48.551] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C3.dat
[13:03:48.551] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C4.dat
[13:03:48.551] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C5.dat
[13:03:48.551] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C6.dat
[13:03:48.552] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C7.dat
[13:03:48.552] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C8.dat
[13:03:48.552] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C9.dat
[13:03:48.552] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C10.dat
[13:03:48.552] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C11.dat
[13:03:48.552] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C12.dat
[13:03:48.552] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C13.dat
[13:03:48.552] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C14.dat
[13:03:48.552] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C15.dat
[13:03:48.552] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C0.dat
[13:03:48.559] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C1.dat
[13:03:48.563] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C2.dat
[13:03:48.568] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C3.dat
[13:03:48.573] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C4.dat
[13:03:48.578] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C5.dat
[13:03:48.583] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C6.dat
[13:03:48.588] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C7.dat
[13:03:48.594] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C8.dat
[13:03:48.599] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C9.dat
[13:03:48.604] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C10.dat
[13:03:48.610] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C11.dat
[13:03:48.615] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C12.dat
[13:03:48.620] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C13.dat
[13:03:48.625] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C14.dat
[13:03:48.630] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1126_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C15.dat
[13:03:48.635] <TB0> INFO: PixTestTrim80::trimTest() done
[13:03:48.635] <TB0> INFO: vtrim: 82 92 96 91 85 92 96 111 85 94 96 105 99 91 97 109
[13:03:48.635] <TB0> INFO: vthrcomp: 71 71 73 72 71 83 77 72 74 71 71 73 76 76 71 73
[13:03:48.635] <TB0> INFO: vcal mean: 79.96 79.98 80.03 79.98 79.97 79.98 79.99 79.99 80.04 79.99 80.01 79.95 79.98 80.00 79.98 80.02
[13:03:48.635] <TB0> INFO: vcal RMS: 0.72 0.73 0.69 0.70 0.71 0.77 0.68 0.73 0.71 0.72 0.82 0.77 0.67 0.72 0.72 0.74
[13:03:48.635] <TB0> INFO: bits mean: 11.17 10.16 9.13 9.23 10.12 9.60 9.02 9.29 9.20 10.05 9.80 9.20 9.03 8.79 10.41 9.98
[13:03:48.635] <TB0> INFO: bits RMS: 2.27 2.54 2.26 2.35 2.55 2.56 2.36 2.32 2.30 2.58 2.63 2.39 2.22 2.38 2.49 2.27
[13:03:48.642] <TB0> INFO: ----------------------------------------------------------------------
[13:03:48.642] <TB0> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:03:48.642] <TB0> INFO: ----------------------------------------------------------------------
[13:03:48.645] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:03:48.659] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:03:48.660] <TB0> INFO: run 1 of 1
[13:03:48.938] <TB0> INFO: Expecting 4160000 events.
[13:04:22.437] <TB0> INFO: 757655 events read in total (32907ms).
[13:04:55.850] <TB0> INFO: 1510310 events read in total (66320ms).
[13:05:28.945] <TB0> INFO: 2257670 events read in total (99416ms).
[13:06:01.200] <TB0> INFO: 3000815 events read in total (131670ms).
[13:06:34.162] <TB0> INFO: 3741880 events read in total (164632ms).
[13:06:53.326] <TB0> INFO: 4160000 events read in total (183796ms).
[13:06:53.423] <TB0> INFO: Test took 184763ms.
[13:07:18.675] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[13:07:18.687] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:07:18.687] <TB0> INFO: run 1 of 1
[13:07:18.928] <TB0> INFO: Expecting 4243200 events.
[13:07:52.889] <TB0> INFO: 728165 events read in total (33369ms).
[13:08:24.630] <TB0> INFO: 1452555 events read in total (65110ms).
[13:08:56.883] <TB0> INFO: 2173230 events read in total (97363ms).
[13:09:28.601] <TB0> INFO: 2888275 events read in total (129081ms).
[13:10:00.689] <TB0> INFO: 3602315 events read in total (161169ms).
[13:10:29.436] <TB0> INFO: 4243200 events read in total (189916ms).
[13:10:29.544] <TB0> INFO: Test took 190856ms.
[13:10:58.843] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[13:10:58.857] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:10:58.858] <TB0> INFO: run 1 of 1
[13:10:59.185] <TB0> INFO: Expecting 4139200 events.
[13:11:32.541] <TB0> INFO: 735905 events read in total (32765ms).
[13:12:04.519] <TB0> INFO: 1467370 events read in total (64743ms).
[13:12:36.705] <TB0> INFO: 2194070 events read in total (96929ms).
[13:13:08.633] <TB0> INFO: 2915995 events read in total (128857ms).
[13:13:40.767] <TB0> INFO: 3636460 events read in total (160991ms).
[13:14:03.114] <TB0> INFO: 4139200 events read in total (183338ms).
[13:14:03.213] <TB0> INFO: Test took 184355ms.
[13:14:31.188] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[13:14:31.202] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:14:31.202] <TB0> INFO: run 1 of 1
[13:14:31.491] <TB0> INFO: Expecting 4097600 events.
[13:15:04.807] <TB0> INFO: 738765 events read in total (32724ms).
[13:15:37.868] <TB0> INFO: 1473605 events read in total (65785ms).
[13:16:09.620] <TB0> INFO: 2202740 events read in total (97537ms).
[13:16:42.343] <TB0> INFO: 2928010 events read in total (130260ms).
[13:17:14.215] <TB0> INFO: 3650995 events read in total (162132ms).
[13:17:34.568] <TB0> INFO: 4097600 events read in total (182485ms).
[13:17:34.676] <TB0> INFO: Test took 183474ms.
[13:18:00.318] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 197 (-1/-1) hits flags = 528 (plus default)
[13:18:00.331] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:18:00.331] <TB0> INFO: run 1 of 1
[13:18:00.567] <TB0> INFO: Expecting 4118400 events.
[13:18:33.288] <TB0> INFO: 737680 events read in total (32129ms).
[13:19:05.600] <TB0> INFO: 1471035 events read in total (64441ms).
[13:19:37.890] <TB0> INFO: 2199440 events read in total (96731ms).
[13:20:10.124] <TB0> INFO: 2923165 events read in total (128965ms).
[13:20:42.284] <TB0> INFO: 3645175 events read in total (161125ms).
[13:21:03.200] <TB0> INFO: 4118400 events read in total (182041ms).
[13:21:03.295] <TB0> INFO: Test took 182964ms.
[13:21:31.095] <TB0> INFO: PixTestTrim80::trimBitTest() done
[13:21:31.096] <TB0> INFO: PixTestTrim80::doTest() done, duration: 2435 seconds
[13:21:31.939] <TB0> INFO: enter test to run
[13:21:31.939] <TB0> INFO: test: exit no parameter change
[13:21:32.189] <TB0> QUIET: Connection to board 71 closed.
[13:21:32.190] <TB0> INFO: pXar: this is the end, my friend