[11:56:24.530] <TB3> INFO: *** Welcome to pxar ***
[11:56:24.530] <TB3> INFO: *** Today: 2016/11/03
[11:56:24.537] <TB3> INFO: *** Version: c8ba-dirty
[11:56:24.537] <TB3> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C15.dat
[11:56:24.538] <TB3> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[11:56:24.538] <TB3> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//defaultMaskFile.dat
[11:56:24.538] <TB3> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters_C15.dat
[11:56:24.616] <TB3> INFO: clk: 4
[11:56:24.616] <TB3> INFO: ctr: 4
[11:56:24.616] <TB3> INFO: sda: 19
[11:56:24.616] <TB3> INFO: tin: 9
[11:56:24.616] <TB3> INFO: level: 15
[11:56:24.616] <TB3> INFO: triggerdelay: 0
[11:56:24.616] <TB3> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[11:56:24.616] <TB3> INFO: Log level: INFO
[11:56:24.626] <TB3> INFO: Found DTB DTB_WZ4I6J
[11:56:24.634] <TB3> QUIET: Connection to board DTB_WZ4I6J opened.
[11:56:24.636] <TB3> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 170
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WZ4I6J
MAC address: 40D8551180AA
Hostname: pixelDTB170
Comment:
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[11:56:24.638] <TB3> INFO: RPC call hashes of host and DTB match: 486171790
[11:56:26.127] <TB3> INFO: DUT info:
[11:56:26.127] <TB3> INFO: The DUT currently contains the following objects:
[11:56:26.127] <TB3> INFO: 4 TBM Cores tbm10c (4 ON)
[11:56:26.127] <TB3> INFO: TBM Core alpha (0): 7 registers set
[11:56:26.127] <TB3> INFO: TBM Core beta (1): 7 registers set
[11:56:26.127] <TB3> INFO: TBM Core alpha (2): 7 registers set
[11:56:26.127] <TB3> INFO: TBM Core beta (3): 7 registers set
[11:56:26.127] <TB3> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:56:26.127] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.127] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.127] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.127] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.127] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.127] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.127] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.127] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.127] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.127] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.127] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.127] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.127] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.128] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.128] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.128] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:26.528] <TB3> INFO: enter 'restricted' command line mode
[11:56:26.528] <TB3> INFO: enter test to run
[11:56:26.528] <TB3> INFO: test: pretest no parameter change
[11:56:26.528] <TB3> INFO: running: pretest
[11:56:27.071] <TB3> INFO: ######################################################################
[11:56:27.071] <TB3> INFO: PixTestPretest::doTest()
[11:56:27.071] <TB3> INFO: ######################################################################
[11:56:27.072] <TB3> INFO: ----------------------------------------------------------------------
[11:56:27.072] <TB3> INFO: PixTestPretest::programROC()
[11:56:27.072] <TB3> INFO: ----------------------------------------------------------------------
[11:56:45.085] <TB3> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:56:45.085] <TB3> INFO: IA differences per ROC: 18.5 17.7 19.3 17.7 18.5 17.7 16.9 19.3 20.1 20.1 19.3 18.5 16.9 19.3 20.1 19.3
[11:56:45.120] <TB3> INFO: ----------------------------------------------------------------------
[11:56:45.121] <TB3> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:56:45.121] <TB3> INFO: ----------------------------------------------------------------------
[11:57:06.366] <TB3> INFO: PixTestPretest::setVana() done, Module Ia 384.3 mA = 24.0187 mA/ROC
[11:57:06.366] <TB3> INFO: i(loss) [mA/ROC]: 19.3 19.3 19.3 19.3 18.5 19.3 18.5 19.3 20.1 20.1 19.3 18.5 19.3 20.1 19.3 18.5
[11:57:06.398] <TB3> INFO: ----------------------------------------------------------------------
[11:57:06.398] <TB3> INFO: PixTestPretest::findTiming()
[11:57:06.398] <TB3> INFO: ----------------------------------------------------------------------
[11:57:06.398] <TB3> INFO: PixTestCmd::init()

[11:57:37.414] <TB3> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:57:37.414] <TB3> INFO: (success/tries = 100/100), width = 4
[11:57:38.928] <TB3> INFO: ----------------------------------------------------------------------
[11:57:38.928] <TB3> INFO: PixTestPretest::findWorkingPixel()
[11:57:38.928] <TB3> INFO: ----------------------------------------------------------------------
[11:57:39.019] <TB3> INFO: Expecting 231680 events.
[11:57:48.699] <TB3> INFO: 231680 events read in total (9088ms).
[11:57:48.707] <TB3> INFO: Test took 9777ms.
[11:57:48.953] <TB3> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:57:48.982] <TB3> INFO: ----------------------------------------------------------------------
[11:57:48.982] <TB3> INFO: PixTestPretest::setVthrCompCalDel()
[11:57:48.982] <TB3> INFO: ----------------------------------------------------------------------
[11:57:49.074] <TB3> INFO: Expecting 231680 events.
[11:57:58.780] <TB3> INFO: 231680 events read in total (9114ms).
[11:57:58.788] <TB3> INFO: Test took 9802ms.
[11:57:59.047] <TB3> INFO: PixTestPretest::setVthrCompCalDel() done
[11:57:59.047] <TB3> INFO: CalDel: 89 77 90 83 86 77 82 98 82 87 97 95 79 88 84 80
[11:57:59.047] <TB3> INFO: VthrComp: 51 51 51 51 51 55 54 55 51 51 53 51 51 55 53 51
[11:57:59.049] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C0.dat
[11:57:59.050] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C1.dat
[11:57:59.050] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C2.dat
[11:57:59.050] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C3.dat
[11:57:59.050] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C4.dat
[11:57:59.050] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C5.dat
[11:57:59.050] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C6.dat
[11:57:59.050] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C7.dat
[11:57:59.050] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C8.dat
[11:57:59.051] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C9.dat
[11:57:59.051] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C10.dat
[11:57:59.051] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C11.dat
[11:57:59.051] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C12.dat
[11:57:59.051] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C13.dat
[11:57:59.051] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C14.dat
[11:57:59.051] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C15.dat
[11:57:59.051] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[11:57:59.051] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[11:57:59.051] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[11:57:59.051] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[11:57:59.051] <TB3> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[11:57:59.147] <TB3> INFO: enter test to run
[11:57:59.147] <TB3> INFO: test: fulltest no parameter change
[11:57:59.147] <TB3> INFO: running: fulltest
[11:57:59.147] <TB3> INFO: ######################################################################
[11:57:59.147] <TB3> INFO: PixTestFullTest::doTest()
[11:57:59.147] <TB3> INFO: ######################################################################
[11:57:59.149] <TB3> INFO: ######################################################################
[11:57:59.149] <TB3> INFO: PixTestAlive::doTest()
[11:57:59.149] <TB3> INFO: ######################################################################
[11:57:59.150] <TB3> INFO: ----------------------------------------------------------------------
[11:57:59.150] <TB3> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:57:59.150] <TB3> INFO: ----------------------------------------------------------------------
[11:57:59.385] <TB3> INFO: Expecting 41600 events.
[11:58:02.805] <TB3> INFO: 41600 events read in total (2829ms).
[11:58:02.806] <TB3> INFO: Test took 3655ms.
[11:58:03.032] <TB3> INFO: PixTestAlive::aliveTest() done
[11:58:03.032] <TB3> INFO: number of dead pixels (per ROC): 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:58:03.034] <TB3> INFO: ----------------------------------------------------------------------
[11:58:03.034] <TB3> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:58:03.034] <TB3> INFO: ----------------------------------------------------------------------
[11:58:03.266] <TB3> INFO: Expecting 41600 events.
[11:58:06.192] <TB3> INFO: 41600 events read in total (2334ms).
[11:58:06.192] <TB3> INFO: Test took 3157ms.
[11:58:06.193] <TB3> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:58:06.431] <TB3> INFO: PixTestAlive::maskTest() done
[11:58:06.431] <TB3> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:58:06.432] <TB3> INFO: ----------------------------------------------------------------------
[11:58:06.432] <TB3> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:58:06.432] <TB3> INFO: ----------------------------------------------------------------------
[11:58:06.706] <TB3> INFO: Expecting 41600 events.
[11:58:10.235] <TB3> INFO: 41600 events read in total (2938ms).
[11:58:10.235] <TB3> INFO: Test took 3801ms.
[11:58:10.465] <TB3> INFO: PixTestAlive::addressDecodingTest() done
[11:58:10.465] <TB3> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:58:10.465] <TB3> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:58:10.465] <TB3> INFO: Decoding statistics:
[11:58:10.465] <TB3> INFO: General information:
[11:58:10.465] <TB3> INFO: 16bit words read: 0
[11:58:10.465] <TB3> INFO: valid events total: 0
[11:58:10.465] <TB3> INFO: empty events: 0
[11:58:10.466] <TB3> INFO: valid events with pixels: 0
[11:58:10.466] <TB3> INFO: valid pixel hits: 0
[11:58:10.466] <TB3> INFO: Event errors: 0
[11:58:10.466] <TB3> INFO: start marker: 0
[11:58:10.466] <TB3> INFO: stop marker: 0
[11:58:10.466] <TB3> INFO: overflow: 0
[11:58:10.466] <TB3> INFO: invalid 5bit words: 0
[11:58:10.466] <TB3> INFO: invalid XOR eye diagram: 0
[11:58:10.466] <TB3> INFO: frame (failed synchr.): 0
[11:58:10.466] <TB3> INFO: idle data (no TBM trl): 0
[11:58:10.466] <TB3> INFO: no data (only TBM hdr): 0
[11:58:10.466] <TB3> INFO: TBM errors: 0
[11:58:10.466] <TB3> INFO: flawed TBM headers: 0
[11:58:10.466] <TB3> INFO: flawed TBM trailers: 0
[11:58:10.466] <TB3> INFO: event ID mismatches: 0
[11:58:10.466] <TB3> INFO: ROC errors: 0
[11:58:10.466] <TB3> INFO: missing ROC header(s): 0
[11:58:10.466] <TB3> INFO: misplaced readback start: 0
[11:58:10.466] <TB3> INFO: Pixel decoding errors: 0
[11:58:10.466] <TB3> INFO: pixel data incomplete: 0
[11:58:10.466] <TB3> INFO: pixel address: 0
[11:58:10.466] <TB3> INFO: pulse height fill bit: 0
[11:58:10.466] <TB3> INFO: buffer corruption: 0
[11:58:10.472] <TB3> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:58:10.473] <TB3> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[11:58:10.473] <TB3> INFO: ######################################################################
[11:58:10.473] <TB3> INFO: PixTestReadback::doTest()
[11:58:10.473] <TB3> INFO: ######################################################################
[11:58:10.473] <TB3> INFO: ----------------------------------------------------------------------
[11:58:10.473] <TB3> INFO: PixTestReadback::CalibrateVd()
[11:58:10.473] <TB3> INFO: ----------------------------------------------------------------------
[11:58:20.432] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C0.dat
[11:58:20.433] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C1.dat
[11:58:20.433] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C2.dat
[11:58:20.433] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C3.dat
[11:58:20.433] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C4.dat
[11:58:20.433] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C5.dat
[11:58:20.433] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C6.dat
[11:58:20.433] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C7.dat
[11:58:20.433] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C8.dat
[11:58:20.433] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C9.dat
[11:58:20.433] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C10.dat
[11:58:20.433] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C11.dat
[11:58:20.433] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C12.dat
[11:58:20.433] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C13.dat
[11:58:20.434] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C14.dat
[11:58:20.434] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:58:20.462] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[11:58:20.462] <TB3> INFO: ----------------------------------------------------------------------
[11:58:20.462] <TB3> INFO: PixTestReadback::CalibrateVa()
[11:58:20.462] <TB3> INFO: ----------------------------------------------------------------------
[11:58:30.352] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C0.dat
[11:58:30.352] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C1.dat
[11:58:30.352] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C2.dat
[11:58:30.352] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C3.dat
[11:58:30.352] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C4.dat
[11:58:30.352] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C5.dat
[11:58:30.352] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C6.dat
[11:58:30.352] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C7.dat
[11:58:30.352] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C8.dat
[11:58:30.352] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C9.dat
[11:58:30.353] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C10.dat
[11:58:30.353] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C11.dat
[11:58:30.353] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C12.dat
[11:58:30.353] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C13.dat
[11:58:30.353] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C14.dat
[11:58:30.353] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:58:30.381] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[11:58:30.381] <TB3> INFO: ----------------------------------------------------------------------
[11:58:30.381] <TB3> INFO: PixTestReadback::readbackVbg()
[11:58:30.381] <TB3> INFO: ----------------------------------------------------------------------
[11:58:38.020] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[11:58:38.020] <TB3> INFO: ----------------------------------------------------------------------
[11:58:38.020] <TB3> INFO: PixTestReadback::getCalibratedVbg()
[11:58:38.020] <TB3> INFO: ----------------------------------------------------------------------
[11:58:38.020] <TB3> INFO: Vbg will be calibrated using Vd calibration
[11:58:38.020] <TB3> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 156.2calibrated Vbg = 1.1786 :::*/*/*/*/
[11:58:38.020] <TB3> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 156.9calibrated Vbg = 1.1841 :::*/*/*/*/
[11:58:38.020] <TB3> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 158calibrated Vbg = 1.17696 :::*/*/*/*/
[11:58:38.021] <TB3> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 164.1calibrated Vbg = 1.16751 :::*/*/*/*/
[11:58:38.021] <TB3> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 157.3calibrated Vbg = 1.17069 :::*/*/*/*/
[11:58:38.021] <TB3> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 161.7calibrated Vbg = 1.17345 :::*/*/*/*/
[11:58:38.021] <TB3> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 159.1calibrated Vbg = 1.17862 :::*/*/*/*/
[11:58:38.021] <TB3> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 156calibrated Vbg = 1.18343 :::*/*/*/*/
[11:58:38.021] <TB3> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 155.9calibrated Vbg = 1.1723 :::*/*/*/*/
[11:58:38.021] <TB3> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 164.3calibrated Vbg = 1.17463 :::*/*/*/*/
[11:58:38.021] <TB3> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 154.9calibrated Vbg = 1.16295 :::*/*/*/*/
[11:58:38.021] <TB3> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 156.9calibrated Vbg = 1.16449 :::*/*/*/*/
[11:58:38.021] <TB3> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 153.9calibrated Vbg = 1.16978 :::*/*/*/*/
[11:58:38.021] <TB3> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152.5calibrated Vbg = 1.18076 :::*/*/*/*/
[11:58:38.021] <TB3> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 154.1calibrated Vbg = 1.17947 :::*/*/*/*/
[11:58:38.021] <TB3> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 167calibrated Vbg = 1.17997 :::*/*/*/*/
[11:58:38.022] <TB3> INFO: ----------------------------------------------------------------------
[11:58:38.022] <TB3> INFO: PixTestReadback::CalibrateIa()
[11:58:38.022] <TB3> INFO: ----------------------------------------------------------------------
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:01:18.312] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:01:18.313] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:01:18.339] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[12:01:18.341] <TB3> INFO: PixTestReadback::doTest() done
[12:01:18.341] <TB3> INFO: Decoding statistics:
[12:01:18.341] <TB3> INFO: General information:
[12:01:18.341] <TB3> INFO: 16bit words read: 1536
[12:01:18.341] <TB3> INFO: valid events total: 256
[12:01:18.341] <TB3> INFO: empty events: 256
[12:01:18.341] <TB3> INFO: valid events with pixels: 0
[12:01:18.341] <TB3> INFO: valid pixel hits: 0
[12:01:18.341] <TB3> INFO: Event errors: 0
[12:01:18.341] <TB3> INFO: start marker: 0
[12:01:18.341] <TB3> INFO: stop marker: 0
[12:01:18.341] <TB3> INFO: overflow: 0
[12:01:18.341] <TB3> INFO: invalid 5bit words: 0
[12:01:18.341] <TB3> INFO: invalid XOR eye diagram: 0
[12:01:18.341] <TB3> INFO: frame (failed synchr.): 0
[12:01:18.341] <TB3> INFO: idle data (no TBM trl): 0
[12:01:18.341] <TB3> INFO: no data (only TBM hdr): 0
[12:01:18.341] <TB3> INFO: TBM errors: 0
[12:01:18.341] <TB3> INFO: flawed TBM headers: 0
[12:01:18.341] <TB3> INFO: flawed TBM trailers: 0
[12:01:18.341] <TB3> INFO: event ID mismatches: 0
[12:01:18.341] <TB3> INFO: ROC errors: 0
[12:01:18.341] <TB3> INFO: missing ROC header(s): 0
[12:01:18.341] <TB3> INFO: misplaced readback start: 0
[12:01:18.341] <TB3> INFO: Pixel decoding errors: 0
[12:01:18.341] <TB3> INFO: pixel data incomplete: 0
[12:01:18.341] <TB3> INFO: pixel address: 0
[12:01:18.341] <TB3> INFO: pulse height fill bit: 0
[12:01:18.341] <TB3> INFO: buffer corruption: 0
[12:01:18.378] <TB3> INFO: ######################################################################
[12:01:18.378] <TB3> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:01:18.378] <TB3> INFO: ######################################################################
[12:01:18.381] <TB3> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:01:18.394] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[12:01:18.394] <TB3> INFO: run 1 of 1
[12:01:18.625] <TB3> INFO: Expecting 3120000 events.
[12:01:49.480] <TB3> INFO: 678505 events read in total (30263ms).











[12:02:19.351] <TB3> INFO: 1351185 events read in total (60134ms).











[12:02:49.566] <TB3> INFO: 2020040 events read in total (90349ms).











[12:03:20.270] <TB3> INFO: 2687955 events read in total (121053ms).











[12:03:39.888] <TB3> INFO: 3120000 events read in total (140671ms).
[12:03:39.942] <TB3> INFO: Test took 141549ms.
[12:04:03.851] <TB3> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 165 seconds
[12:04:03.851] <TB3> INFO: number of dead bumps (per ROC): 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0
[12:04:03.851] <TB3> INFO: separation cut (per ROC): 106 108 107 106 104 113 107 105 105 105 120 103 103 119 120 114
[12:04:03.851] <TB3> INFO: Decoding statistics:
[12:04:03.851] <TB3> INFO: General information:
[12:04:03.851] <TB3> INFO: 16bit words read: 0
[12:04:03.851] <TB3> INFO: valid events total: 0
[12:04:03.851] <TB3> INFO: empty events: 0
[12:04:03.851] <TB3> INFO: valid events with pixels: 0
[12:04:03.851] <TB3> INFO: valid pixel hits: 0
[12:04:03.851] <TB3> INFO: Event errors: 0
[12:04:03.851] <TB3> INFO: start marker: 0
[12:04:03.851] <TB3> INFO: stop marker: 0
[12:04:03.851] <TB3> INFO: overflow: 0
[12:04:03.852] <TB3> INFO: invalid 5bit words: 0
[12:04:03.852] <TB3> INFO: invalid XOR eye diagram: 0
[12:04:03.852] <TB3> INFO: frame (failed synchr.): 0
[12:04:03.852] <TB3> INFO: idle data (no TBM trl): 0
[12:04:03.852] <TB3> INFO: no data (only TBM hdr): 0
[12:04:03.852] <TB3> INFO: TBM errors: 0
[12:04:03.852] <TB3> INFO: flawed TBM headers: 0
[12:04:03.852] <TB3> INFO: flawed TBM trailers: 0
[12:04:03.852] <TB3> INFO: event ID mismatches: 0
[12:04:03.852] <TB3> INFO: ROC errors: 0
[12:04:03.852] <TB3> INFO: missing ROC header(s): 0
[12:04:03.852] <TB3> INFO: misplaced readback start: 0
[12:04:03.852] <TB3> INFO: Pixel decoding errors: 0
[12:04:03.852] <TB3> INFO: pixel data incomplete: 0
[12:04:03.852] <TB3> INFO: pixel address: 0
[12:04:03.852] <TB3> INFO: pulse height fill bit: 0
[12:04:03.852] <TB3> INFO: buffer corruption: 0
[12:04:03.887] <TB3> INFO: ######################################################################
[12:04:03.887] <TB3> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:04:03.887] <TB3> INFO: ######################################################################
[12:04:03.887] <TB3> INFO: ----------------------------------------------------------------------
[12:04:03.887] <TB3> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:04:03.887] <TB3> INFO: ----------------------------------------------------------------------
[12:04:03.888] <TB3> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:04:03.898] <TB3> INFO: dacScan split into 1 runs with ntrig = 50
[12:04:03.898] <TB3> INFO: run 1 of 1
[12:04:04.131] <TB3> INFO: Expecting 36608000 events.
[12:04:27.626] <TB3> INFO: 706950 events read in total (22903ms).
[12:04:50.461] <TB3> INFO: 1393000 events read in total (45738ms).
[12:05:13.223] <TB3> INFO: 2081950 events read in total (68500ms).
[12:05:35.871] <TB3> INFO: 2767150 events read in total (91148ms).
[12:05:58.800] <TB3> INFO: 3451250 events read in total (114077ms).
[12:06:21.601] <TB3> INFO: 4133750 events read in total (136878ms).
[12:06:44.417] <TB3> INFO: 4819350 events read in total (159694ms).
[12:07:07.312] <TB3> INFO: 5501000 events read in total (182589ms).
[12:07:30.224] <TB3> INFO: 6184950 events read in total (205501ms).
[12:07:52.961] <TB3> INFO: 6867250 events read in total (228238ms).
[12:08:15.553] <TB3> INFO: 7550100 events read in total (250830ms).
[12:08:38.142] <TB3> INFO: 8233550 events read in total (273419ms).
[12:09:00.454] <TB3> INFO: 8915450 events read in total (295731ms).
[12:09:23.079] <TB3> INFO: 9597600 events read in total (318356ms).
[12:09:45.848] <TB3> INFO: 10277500 events read in total (341125ms).
[12:10:08.371] <TB3> INFO: 10956550 events read in total (363648ms).
[12:10:31.087] <TB3> INFO: 11635250 events read in total (386364ms).
[12:10:53.885] <TB3> INFO: 12316000 events read in total (409162ms).
[12:11:16.677] <TB3> INFO: 12996050 events read in total (431954ms).
[12:11:39.411] <TB3> INFO: 13674950 events read in total (454688ms).
[12:12:02.022] <TB3> INFO: 14353600 events read in total (477299ms).
[12:12:24.620] <TB3> INFO: 15031500 events read in total (499897ms).
[12:12:47.372] <TB3> INFO: 15707600 events read in total (522649ms).
[12:13:10.010] <TB3> INFO: 16384400 events read in total (545287ms).
[12:13:32.580] <TB3> INFO: 17060600 events read in total (567857ms).
[12:13:55.183] <TB3> INFO: 17739700 events read in total (590460ms).
[12:14:17.661] <TB3> INFO: 18414900 events read in total (612938ms).
[12:14:40.379] <TB3> INFO: 19090100 events read in total (635656ms).
[12:15:03.044] <TB3> INFO: 19762150 events read in total (658321ms).
[12:15:25.851] <TB3> INFO: 20436400 events read in total (681128ms).
[12:15:48.306] <TB3> INFO: 21108050 events read in total (703583ms).
[12:16:11.060] <TB3> INFO: 21781200 events read in total (726337ms).
[12:16:33.795] <TB3> INFO: 22453650 events read in total (749072ms).
[12:16:56.332] <TB3> INFO: 23126250 events read in total (771609ms).
[12:17:18.916] <TB3> INFO: 23800200 events read in total (794193ms).
[12:17:41.577] <TB3> INFO: 24470200 events read in total (816854ms).
[12:18:03.981] <TB3> INFO: 25139700 events read in total (839258ms).
[12:18:26.402] <TB3> INFO: 25813150 events read in total (861679ms).
[12:18:49.189] <TB3> INFO: 26485600 events read in total (884466ms).
[12:19:11.806] <TB3> INFO: 27155800 events read in total (907083ms).
[12:19:34.032] <TB3> INFO: 27825200 events read in total (929309ms).
[12:19:56.570] <TB3> INFO: 28494750 events read in total (951847ms).
[12:20:19.309] <TB3> INFO: 29164000 events read in total (974586ms).
[12:20:41.987] <TB3> INFO: 29832750 events read in total (997264ms).
[12:21:04.543] <TB3> INFO: 30502300 events read in total (1019820ms).
[12:21:27.039] <TB3> INFO: 31170400 events read in total (1042316ms).
[12:21:49.684] <TB3> INFO: 31843100 events read in total (1064961ms).
[12:22:12.313] <TB3> INFO: 32513350 events read in total (1087590ms).
[12:22:34.945] <TB3> INFO: 33183600 events read in total (1110222ms).
[12:22:57.833] <TB3> INFO: 33854750 events read in total (1133110ms).
[12:23:20.241] <TB3> INFO: 34526500 events read in total (1155518ms).
[12:23:42.747] <TB3> INFO: 35195100 events read in total (1178024ms).
[12:24:05.397] <TB3> INFO: 35866700 events read in total (1200674ms).
[12:24:28.763] <TB3> INFO: 36551800 events read in total (1224040ms).
[12:24:30.893] <TB3> INFO: 36608000 events read in total (1226170ms).
[12:24:30.943] <TB3> INFO: Test took 1227045ms.
[12:24:31.314] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:32.801] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:34.250] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:35.690] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:37.191] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:38.637] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:40.359] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:41.897] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:43.787] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:45.735] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:47.541] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:49.536] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:51.562] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:53.461] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:55.471] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:57.507] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:24:59.076] <TB3> INFO: PixTestScurves::scurves() done
[12:24:59.076] <TB3> INFO: Vcal mean: 128.06 126.32 118.01 119.32 126.74 125.74 131.57 127.62 120.02 120.80 137.37 111.92 120.08 127.44 126.98 127.19
[12:24:59.076] <TB3> INFO: Vcal RMS: 5.58 6.27 6.37 5.61 6.14 6.39 6.29 7.15 6.19 5.83 6.62 4.83 5.90 5.86 6.61 6.23
[12:24:59.077] <TB3> INFO: PixTestScurves::fullTest() done, duration: 1255 seconds
[12:24:59.077] <TB3> INFO: Decoding statistics:
[12:24:59.077] <TB3> INFO: General information:
[12:24:59.077] <TB3> INFO: 16bit words read: 0
[12:24:59.077] <TB3> INFO: valid events total: 0
[12:24:59.077] <TB3> INFO: empty events: 0
[12:24:59.077] <TB3> INFO: valid events with pixels: 0
[12:24:59.077] <TB3> INFO: valid pixel hits: 0
[12:24:59.077] <TB3> INFO: Event errors: 0
[12:24:59.077] <TB3> INFO: start marker: 0
[12:24:59.077] <TB3> INFO: stop marker: 0
[12:24:59.077] <TB3> INFO: overflow: 0
[12:24:59.077] <TB3> INFO: invalid 5bit words: 0
[12:24:59.077] <TB3> INFO: invalid XOR eye diagram: 0
[12:24:59.077] <TB3> INFO: frame (failed synchr.): 0
[12:24:59.077] <TB3> INFO: idle data (no TBM trl): 0
[12:24:59.077] <TB3> INFO: no data (only TBM hdr): 0
[12:24:59.077] <TB3> INFO: TBM errors: 0
[12:24:59.077] <TB3> INFO: flawed TBM headers: 0
[12:24:59.077] <TB3> INFO: flawed TBM trailers: 0
[12:24:59.077] <TB3> INFO: event ID mismatches: 0
[12:24:59.077] <TB3> INFO: ROC errors: 0
[12:24:59.077] <TB3> INFO: missing ROC header(s): 0
[12:24:59.077] <TB3> INFO: misplaced readback start: 0
[12:24:59.077] <TB3> INFO: Pixel decoding errors: 0
[12:24:59.077] <TB3> INFO: pixel data incomplete: 0
[12:24:59.077] <TB3> INFO: pixel address: 0
[12:24:59.077] <TB3> INFO: pulse height fill bit: 0
[12:24:59.077] <TB3> INFO: buffer corruption: 0
[12:24:59.141] <TB3> INFO: ######################################################################
[12:24:59.141] <TB3> INFO: PixTestTrim::doTest()
[12:24:59.141] <TB3> INFO: ######################################################################
[12:24:59.142] <TB3> INFO: ----------------------------------------------------------------------
[12:24:59.142] <TB3> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:24:59.142] <TB3> INFO: ----------------------------------------------------------------------
[12:24:59.200] <TB3> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:24:59.200] <TB3> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:24:59.212] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:24:59.212] <TB3> INFO: run 1 of 1
[12:24:59.488] <TB3> INFO: Expecting 5025280 events.
[12:25:30.133] <TB3> INFO: 830744 events read in total (30047ms).
[12:26:00.228] <TB3> INFO: 1658600 events read in total (60142ms).
[12:26:30.097] <TB3> INFO: 2483424 events read in total (90011ms).
[12:27:00.326] <TB3> INFO: 3303224 events read in total (120240ms).
[12:27:30.331] <TB3> INFO: 4118744 events read in total (150245ms).
[12:27:59.847] <TB3> INFO: 4933184 events read in total (179761ms).
[12:28:03.691] <TB3> INFO: 5025280 events read in total (183605ms).
[12:28:03.730] <TB3> INFO: Test took 184518ms.
[12:28:21.184] <TB3> INFO: ROC 0 VthrComp = 131
[12:28:21.184] <TB3> INFO: ROC 1 VthrComp = 126
[12:28:21.185] <TB3> INFO: ROC 2 VthrComp = 123
[12:28:21.185] <TB3> INFO: ROC 3 VthrComp = 125
[12:28:21.185] <TB3> INFO: ROC 4 VthrComp = 123
[12:28:21.185] <TB3> INFO: ROC 5 VthrComp = 129
[12:28:21.185] <TB3> INFO: ROC 6 VthrComp = 130
[12:28:21.185] <TB3> INFO: ROC 7 VthrComp = 124
[12:28:21.185] <TB3> INFO: ROC 8 VthrComp = 129
[12:28:21.185] <TB3> INFO: ROC 9 VthrComp = 129
[12:28:21.186] <TB3> INFO: ROC 10 VthrComp = 131
[12:28:21.186] <TB3> INFO: ROC 11 VthrComp = 114
[12:28:21.186] <TB3> INFO: ROC 12 VthrComp = 124
[12:28:21.186] <TB3> INFO: ROC 13 VthrComp = 132
[12:28:21.186] <TB3> INFO: ROC 14 VthrComp = 133
[12:28:21.186] <TB3> INFO: ROC 15 VthrComp = 130
[12:28:21.422] <TB3> INFO: Expecting 41600 events.
[12:28:25.075] <TB3> INFO: 41600 events read in total (3062ms).
[12:28:25.075] <TB3> INFO: Test took 3887ms.
[12:28:25.086] <TB3> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:28:25.086] <TB3> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:28:25.097] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:28:25.097] <TB3> INFO: run 1 of 1
[12:28:25.375] <TB3> INFO: Expecting 5025280 events.
[12:28:51.558] <TB3> INFO: 591992 events read in total (25591ms).
[12:29:16.860] <TB3> INFO: 1182808 events read in total (50893ms).
[12:29:42.152] <TB3> INFO: 1772904 events read in total (76185ms).
[12:30:07.429] <TB3> INFO: 2362216 events read in total (101462ms).
[12:30:32.877] <TB3> INFO: 2949560 events read in total (126910ms).
[12:30:58.225] <TB3> INFO: 3535584 events read in total (152258ms).
[12:31:23.573] <TB3> INFO: 4120152 events read in total (177606ms).
[12:31:50.024] <TB3> INFO: 4704728 events read in total (204057ms).
[12:32:04.090] <TB3> INFO: 5025280 events read in total (218124ms).
[12:32:04.148] <TB3> INFO: Test took 219052ms.
[12:32:28.524] <TB3> INFO: roc 0 with ID = 0 has maximal Vcal 60.9339 for pixel 11/3 mean/min/max = 46.9176/32.8574/60.9778
[12:32:28.524] <TB3> INFO: roc 1 with ID = 1 has maximal Vcal 62.1894 for pixel 13/2 mean/min/max = 47.0866/31.9709/62.2023
[12:32:28.524] <TB3> INFO: roc 2 with ID = 2 has maximal Vcal 59.6058 for pixel 13/2 mean/min/max = 45.8778/32.1103/59.6452
[12:32:28.525] <TB3> INFO: roc 3 with ID = 3 has maximal Vcal 58.6974 for pixel 0/1 mean/min/max = 45.2653/31.829/58.7016
[12:32:28.525] <TB3> INFO: roc 4 with ID = 4 has maximal Vcal 62.202 for pixel 28/21 mean/min/max = 47.1878/32.0769/62.2987
[12:32:28.526] <TB3> INFO: roc 5 with ID = 5 has maximal Vcal 64.5212 for pixel 45/10 mean/min/max = 48.8681/33.1174/64.6188
[12:32:28.526] <TB3> INFO: roc 6 with ID = 6 has maximal Vcal 62.6318 for pixel 28/5 mean/min/max = 48.0447/33.3989/62.6904
[12:32:28.526] <TB3> INFO: roc 7 with ID = 7 has maximal Vcal 66.1505 for pixel 0/7 mean/min/max = 48.9477/31.7203/66.175
[12:32:28.527] <TB3> INFO: roc 8 with ID = 8 has maximal Vcal 59.3751 for pixel 12/4 mean/min/max = 45.8581/32.2248/59.4913
[12:32:28.527] <TB3> INFO: roc 9 with ID = 9 has maximal Vcal 59.8096 for pixel 0/34 mean/min/max = 45.7417/31.317/60.1664
[12:32:28.527] <TB3> INFO: roc 10 with ID = 10 has maximal Vcal 66.5585 for pixel 25/7 mean/min/max = 49.6459/32.6512/66.6405
[12:32:28.528] <TB3> INFO: roc 11 with ID = 11 has maximal Vcal 58.9843 for pixel 3/21 mean/min/max = 45.8464/32.7019/58.991
[12:32:28.528] <TB3> INFO: roc 12 with ID = 12 has maximal Vcal 60.1632 for pixel 5/5 mean/min/max = 46.1195/31.9376/60.3014
[12:32:28.529] <TB3> INFO: roc 13 with ID = 13 has maximal Vcal 65.2168 for pixel 13/4 mean/min/max = 50.4925/35.5521/65.4329
[12:32:28.529] <TB3> INFO: roc 14 with ID = 14 has maximal Vcal 61.2935 for pixel 3/11 mean/min/max = 47.1342/32.8627/61.4057
[12:32:28.529] <TB3> INFO: roc 15 with ID = 15 has maximal Vcal 59.4706 for pixel 5/17 mean/min/max = 45.6053/31.6957/59.515
[12:32:28.530] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:32:28.618] <TB3> INFO: Expecting 411648 events.
[12:32:37.919] <TB3> INFO: 411648 events read in total (8709ms).
[12:32:37.926] <TB3> INFO: Expecting 411648 events.
[12:32:46.954] <TB3> INFO: 411648 events read in total (8625ms).
[12:32:46.964] <TB3> INFO: Expecting 411648 events.
[12:32:55.966] <TB3> INFO: 411648 events read in total (8599ms).
[12:32:55.979] <TB3> INFO: Expecting 411648 events.
[12:33:05.015] <TB3> INFO: 411648 events read in total (8633ms).
[12:33:05.030] <TB3> INFO: Expecting 411648 events.
[12:33:14.058] <TB3> INFO: 411648 events read in total (8626ms).
[12:33:14.075] <TB3> INFO: Expecting 411648 events.
[12:33:23.200] <TB3> INFO: 411648 events read in total (8722ms).
[12:33:23.226] <TB3> INFO: Expecting 411648 events.
[12:33:32.315] <TB3> INFO: 411648 events read in total (8687ms).
[12:33:32.343] <TB3> INFO: Expecting 411648 events.
[12:33:41.365] <TB3> INFO: 411648 events read in total (8618ms).
[12:33:41.389] <TB3> INFO: Expecting 411648 events.
[12:33:50.394] <TB3> INFO: 411648 events read in total (8603ms).
[12:33:50.421] <TB3> INFO: Expecting 411648 events.
[12:33:59.469] <TB3> INFO: 411648 events read in total (8645ms).
[12:33:59.498] <TB3> INFO: Expecting 411648 events.
[12:34:08.592] <TB3> INFO: 411648 events read in total (8692ms).
[12:34:08.629] <TB3> INFO: Expecting 411648 events.
[12:34:17.606] <TB3> INFO: 411648 events read in total (8574ms).
[12:34:17.640] <TB3> INFO: Expecting 411648 events.
[12:34:26.765] <TB3> INFO: 411648 events read in total (8722ms).
[12:34:26.801] <TB3> INFO: Expecting 411648 events.
[12:34:35.906] <TB3> INFO: 411648 events read in total (8702ms).
[12:34:35.947] <TB3> INFO: Expecting 411648 events.
[12:34:45.148] <TB3> INFO: 411648 events read in total (8798ms).
[12:34:45.207] <TB3> INFO: Expecting 411648 events.
[12:34:54.348] <TB3> INFO: 411648 events read in total (8738ms).
[12:34:54.414] <TB3> INFO: Test took 145885ms.
[12:34:55.112] <TB3> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:34:55.122] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:34:55.122] <TB3> INFO: run 1 of 1
[12:34:55.356] <TB3> INFO: Expecting 5025280 events.
[12:35:21.602] <TB3> INFO: 588632 events read in total (25654ms).
[12:35:46.922] <TB3> INFO: 1176856 events read in total (50974ms).
[12:36:12.572] <TB3> INFO: 1763392 events read in total (76624ms).
[12:36:38.223] <TB3> INFO: 2348480 events read in total (102275ms).
[12:37:04.060] <TB3> INFO: 2935592 events read in total (128113ms).
[12:37:29.787] <TB3> INFO: 3521968 events read in total (153839ms).
[12:37:55.353] <TB3> INFO: 4108720 events read in total (179405ms).
[12:38:21.856] <TB3> INFO: 4696144 events read in total (205908ms).
[12:38:36.319] <TB3> INFO: 5025280 events read in total (220372ms).
[12:38:36.438] <TB3> INFO: Test took 221317ms.
[12:38:59.198] <TB3> INFO: ---> TrimStepCorr4 extremal thresholds: 6.500000 .. 145.878405
[12:38:59.433] <TB3> INFO: Expecting 208000 events.
[12:39:08.808] <TB3> INFO: 208000 events read in total (8783ms).
[12:39:08.809] <TB3> INFO: Test took 9609ms.
[12:39:08.877] <TB3> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 6 .. 155 (-1/-1) hits flags = 528 (plus default)
[12:39:08.889] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:39:08.889] <TB3> INFO: run 1 of 1
[12:39:09.167] <TB3> INFO: Expecting 4992000 events.
[12:39:35.213] <TB3> INFO: 578328 events read in total (25455ms).
[12:40:00.599] <TB3> INFO: 1156800 events read in total (50841ms).
[12:40:26.014] <TB3> INFO: 1735192 events read in total (76256ms).
[12:40:51.947] <TB3> INFO: 2313360 events read in total (102189ms).
[12:41:17.823] <TB3> INFO: 2891488 events read in total (128065ms).
[12:41:43.571] <TB3> INFO: 3469088 events read in total (153813ms).
[12:42:09.219] <TB3> INFO: 4046136 events read in total (179461ms).
[12:42:35.197] <TB3> INFO: 4622208 events read in total (205439ms).
[12:42:52.639] <TB3> INFO: 4992000 events read in total (222881ms).
[12:42:52.740] <TB3> INFO: Test took 223852ms.
[12:43:16.377] <TB3> INFO: ---> TrimStepCorr2 extremal thresholds: 26.533554 .. 45.792423
[12:43:16.629] <TB3> INFO: Expecting 208000 events.
[12:43:26.668] <TB3> INFO: 208000 events read in total (9447ms).
[12:43:26.669] <TB3> INFO: Test took 10291ms.
[12:43:26.732] <TB3> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:43:26.743] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:43:26.743] <TB3> INFO: run 1 of 1
[12:43:27.021] <TB3> INFO: Expecting 1331200 events.
[12:43:55.092] <TB3> INFO: 664232 events read in total (27479ms).
[12:44:22.118] <TB3> INFO: 1326440 events read in total (54505ms).
[12:44:22.745] <TB3> INFO: 1331200 events read in total (55133ms).
[12:44:22.777] <TB3> INFO: Test took 56035ms.
[12:44:35.189] <TB3> INFO: ---> TrimStepCorr1a extremal thresholds: 25.729523 .. 49.113782
[12:44:35.422] <TB3> INFO: Expecting 208000 events.
[12:44:45.006] <TB3> INFO: 208000 events read in total (8992ms).
[12:44:45.007] <TB3> INFO: Test took 9816ms.
[12:44:45.054] <TB3> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 59 (-1/-1) hits flags = 528 (plus default)
[12:44:45.066] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:44:45.066] <TB3> INFO: run 1 of 1
[12:44:45.344] <TB3> INFO: Expecting 1497600 events.
[12:45:13.043] <TB3> INFO: 653328 events read in total (27107ms).
[12:45:40.060] <TB3> INFO: 1305624 events read in total (54124ms).
[12:45:48.154] <TB3> INFO: 1497600 events read in total (62218ms).
[12:45:48.180] <TB3> INFO: Test took 63115ms.
[12:46:01.043] <TB3> INFO: ---> TrimStepCorr1b extremal thresholds: 26.721778 .. 52.344016
[12:46:01.297] <TB3> INFO: Expecting 208000 events.
[12:46:11.231] <TB3> INFO: 208000 events read in total (9343ms).
[12:46:11.232] <TB3> INFO: Test took 10187ms.
[12:46:11.281] <TB3> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 62 (-1/-1) hits flags = 528 (plus default)
[12:46:11.294] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:46:11.294] <TB3> INFO: run 1 of 1
[12:46:11.612] <TB3> INFO: Expecting 1564160 events.
[12:46:38.815] <TB3> INFO: 640064 events read in total (26611ms).
[12:47:06.061] <TB3> INFO: 1280496 events read in total (53857ms).
[12:47:18.260] <TB3> INFO: 1564160 events read in total (66056ms).
[12:47:18.286] <TB3> INFO: Test took 66993ms.
[12:47:32.010] <TB3> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:47:32.010] <TB3> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:47:32.022] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:47:32.022] <TB3> INFO: run 1 of 1
[12:47:32.256] <TB3> INFO: Expecting 1364480 events.
[12:48:00.224] <TB3> INFO: 668296 events read in total (27377ms).
[12:48:28.357] <TB3> INFO: 1335904 events read in total (55510ms).
[12:48:29.944] <TB3> INFO: 1364480 events read in total (57098ms).
[12:48:29.966] <TB3> INFO: Test took 57945ms.
[12:48:41.745] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C0.dat
[12:48:41.745] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C1.dat
[12:48:41.745] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C2.dat
[12:48:41.745] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C3.dat
[12:48:41.745] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C4.dat
[12:48:41.746] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C5.dat
[12:48:41.746] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C6.dat
[12:48:41.746] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C7.dat
[12:48:41.746] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C8.dat
[12:48:41.746] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C9.dat
[12:48:41.746] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C10.dat
[12:48:41.746] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C11.dat
[12:48:41.746] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C12.dat
[12:48:41.746] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C13.dat
[12:48:41.746] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C14.dat
[12:48:41.746] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C15.dat
[12:48:41.747] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C0.dat
[12:48:41.755] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C1.dat
[12:48:41.763] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C2.dat
[12:48:41.771] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C3.dat
[12:48:41.777] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C4.dat
[12:48:41.784] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C5.dat
[12:48:41.792] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C6.dat
[12:48:41.800] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C7.dat
[12:48:41.807] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C8.dat
[12:48:41.813] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C9.dat
[12:48:41.819] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C10.dat
[12:48:41.825] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C11.dat
[12:48:41.832] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C12.dat
[12:48:41.839] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C13.dat
[12:48:41.846] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C14.dat
[12:48:41.854] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C15.dat
[12:48:41.861] <TB3> INFO: PixTestTrim::trimTest() done
[12:48:41.861] <TB3> INFO: vtrim: 140 146 134 125 157 165 137 130 142 141 156 121 131 175 141 124
[12:48:41.861] <TB3> INFO: vthrcomp: 131 126 123 125 123 129 130 124 129 129 131 114 124 132 133 130
[12:48:41.861] <TB3> INFO: vcal mean: 35.03 35.23 34.91 35.00 35.47 35.34 35.60 35.42 34.96 34.97 36.22 34.88 35.00 35.26 34.99 35.07
[12:48:41.861] <TB3> INFO: vcal RMS: 1.08 1.34 1.00 1.06 1.68 1.43 1.85 1.67 1.02 1.06 2.48 1.03 1.11 1.38 1.02 1.14
[12:48:41.861] <TB3> INFO: bits mean: 9.35 10.04 9.76 9.66 10.55 9.64 9.50 9.46 9.50 9.65 10.11 9.76 9.67 8.92 9.36 9.81
[12:48:41.861] <TB3> INFO: bits RMS: 2.59 2.44 2.55 2.71 2.20 2.38 2.61 2.69 2.71 2.73 2.38 2.53 2.62 2.30 2.57 2.69
[12:48:41.868] <TB3> INFO: ----------------------------------------------------------------------
[12:48:41.868] <TB3> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:48:41.869] <TB3> INFO: ----------------------------------------------------------------------
[12:48:41.871] <TB3> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:48:41.880] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[12:48:41.880] <TB3> INFO: run 1 of 1
[12:48:42.113] <TB3> INFO: Expecting 4160000 events.
[12:49:14.383] <TB3> INFO: 774310 events read in total (31678ms).
[12:49:46.139] <TB3> INFO: 1540880 events read in total (63434ms).
[12:50:17.790] <TB3> INFO: 2300895 events read in total (95085ms).
[12:50:49.483] <TB3> INFO: 3056360 events read in total (126778ms).
[12:51:21.194] <TB3> INFO: 3807765 events read in total (158489ms).
[12:51:36.944] <TB3> INFO: 4160000 events read in total (174239ms).
[12:51:37.030] <TB3> INFO: Test took 175150ms.
[12:52:00.190] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[12:52:00.199] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[12:52:00.199] <TB3> INFO: run 1 of 1
[12:52:00.432] <TB3> INFO: Expecting 4472000 events.
[12:52:31.748] <TB3> INFO: 728190 events read in total (30725ms).
[12:53:02.619] <TB3> INFO: 1450970 events read in total (61596ms).
[12:53:33.229] <TB3> INFO: 2170700 events read in total (92206ms).
[12:54:03.452] <TB3> INFO: 2886235 events read in total (122429ms).
[12:54:33.830] <TB3> INFO: 3598685 events read in total (152807ms).
[12:55:04.408] <TB3> INFO: 4310790 events read in total (183385ms).
[12:55:11.642] <TB3> INFO: 4472000 events read in total (190619ms).
[12:55:11.703] <TB3> INFO: Test took 191504ms.
[12:55:43.022] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[12:55:43.033] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[12:55:43.033] <TB3> INFO: run 1 of 1
[12:55:43.269] <TB3> INFO: Expecting 4264000 events.
[12:56:14.842] <TB3> INFO: 741650 events read in total (30981ms).
[12:56:45.641] <TB3> INFO: 1477000 events read in total (61780ms).
[12:57:16.269] <TB3> INFO: 2208840 events read in total (92408ms).
[12:57:47.094] <TB3> INFO: 2935795 events read in total (123233ms).
[12:58:17.688] <TB3> INFO: 3660235 events read in total (153827ms).
[12:58:43.584] <TB3> INFO: 4264000 events read in total (179723ms).
[12:58:43.637] <TB3> INFO: Test took 180604ms.
[12:59:14.273] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[12:59:14.283] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[12:59:14.284] <TB3> INFO: run 1 of 1
[12:59:14.526] <TB3> INFO: Expecting 4284800 events.
[12:59:46.233] <TB3> INFO: 740450 events read in total (31116ms).
[13:00:16.992] <TB3> INFO: 1474735 events read in total (61875ms).
[13:00:47.841] <TB3> INFO: 2205485 events read in total (92724ms).
[13:01:18.892] <TB3> INFO: 2931555 events read in total (123775ms).
[13:01:49.733] <TB3> INFO: 3654545 events read in total (154616ms).
[13:02:16.461] <TB3> INFO: 4284800 events read in total (181344ms).
[13:02:16.514] <TB3> INFO: Test took 182230ms.
[13:02:45.193] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[13:02:45.203] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:02:45.203] <TB3> INFO: run 1 of 1
[13:02:45.449] <TB3> INFO: Expecting 4264000 events.
[13:03:16.943] <TB3> INFO: 742280 events read in total (30902ms).
[13:03:47.786] <TB3> INFO: 1478200 events read in total (61745ms).
[13:04:18.687] <TB3> INFO: 2210770 events read in total (92646ms).
[13:04:49.298] <TB3> INFO: 2938365 events read in total (123257ms).
[13:05:19.842] <TB3> INFO: 3663200 events read in total (153801ms).
[13:05:45.157] <TB3> INFO: 4264000 events read in total (179116ms).
[13:05:45.209] <TB3> INFO: Test took 180005ms.
[13:06:12.600] <TB3> INFO: PixTestTrim::trimBitTest() done
[13:06:12.601] <TB3> INFO: PixTestTrim::doTest() done, duration: 2473 seconds
[13:06:12.601] <TB3> INFO: Decoding statistics:
[13:06:12.601] <TB3> INFO: General information:
[13:06:12.601] <TB3> INFO: 16bit words read: 0
[13:06:12.601] <TB3> INFO: valid events total: 0
[13:06:12.601] <TB3> INFO: empty events: 0
[13:06:12.601] <TB3> INFO: valid events with pixels: 0
[13:06:12.601] <TB3> INFO: valid pixel hits: 0
[13:06:12.601] <TB3> INFO: Event errors: 0
[13:06:12.601] <TB3> INFO: start marker: 0
[13:06:12.601] <TB3> INFO: stop marker: 0
[13:06:12.601] <TB3> INFO: overflow: 0
[13:06:12.601] <TB3> INFO: invalid 5bit words: 0
[13:06:12.601] <TB3> INFO: invalid XOR eye diagram: 0
[13:06:12.601] <TB3> INFO: frame (failed synchr.): 0
[13:06:12.601] <TB3> INFO: idle data (no TBM trl): 0
[13:06:12.601] <TB3> INFO: no data (only TBM hdr): 0
[13:06:12.601] <TB3> INFO: TBM errors: 0
[13:06:12.601] <TB3> INFO: flawed TBM headers: 0
[13:06:12.601] <TB3> INFO: flawed TBM trailers: 0
[13:06:12.601] <TB3> INFO: event ID mismatches: 0
[13:06:12.601] <TB3> INFO: ROC errors: 0
[13:06:12.601] <TB3> INFO: missing ROC header(s): 0
[13:06:12.602] <TB3> INFO: misplaced readback start: 0
[13:06:12.602] <TB3> INFO: Pixel decoding errors: 0
[13:06:12.602] <TB3> INFO: pixel data incomplete: 0
[13:06:12.602] <TB3> INFO: pixel address: 0
[13:06:12.602] <TB3> INFO: pulse height fill bit: 0
[13:06:12.602] <TB3> INFO: buffer corruption: 0
[13:06:13.386] <TB3> INFO: ######################################################################
[13:06:13.386] <TB3> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:06:13.386] <TB3> INFO: ######################################################################
[13:06:13.620] <TB3> INFO: Expecting 41600 events.
[13:06:17.238] <TB3> INFO: 41600 events read in total (3026ms).
[13:06:17.239] <TB3> INFO: Test took 3852ms.
[13:06:17.725] <TB3> INFO: Expecting 41600 events.
[13:06:21.203] <TB3> INFO: 41600 events read in total (2887ms).
[13:06:21.204] <TB3> INFO: Test took 3763ms.
[13:06:21.493] <TB3> INFO: Expecting 41600 events.
[13:06:24.987] <TB3> INFO: 41600 events read in total (2902ms).
[13:06:24.988] <TB3> INFO: Test took 3760ms.
[13:06:25.279] <TB3> INFO: Expecting 41600 events.
[13:06:28.885] <TB3> INFO: 41600 events read in total (3015ms).
[13:06:28.886] <TB3> INFO: Test took 3872ms.
[13:06:29.230] <TB3> INFO: Expecting 41600 events.
[13:06:32.769] <TB3> INFO: 41600 events read in total (2947ms).
[13:06:32.770] <TB3> INFO: Test took 3857ms.
[13:06:33.061] <TB3> INFO: Expecting 41600 events.
[13:06:36.560] <TB3> INFO: 41600 events read in total (2907ms).
[13:06:36.561] <TB3> INFO: Test took 3765ms.
[13:06:36.850] <TB3> INFO: Expecting 41600 events.
[13:06:40.455] <TB3> INFO: 41600 events read in total (3014ms).
[13:06:40.456] <TB3> INFO: Test took 3871ms.
[13:06:40.747] <TB3> INFO: Expecting 41600 events.
[13:06:44.279] <TB3> INFO: 41600 events read in total (2940ms).
[13:06:44.280] <TB3> INFO: Test took 3798ms.
[13:06:44.569] <TB3> INFO: Expecting 41600 events.
[13:06:48.046] <TB3> INFO: 41600 events read in total (2886ms).
[13:06:48.047] <TB3> INFO: Test took 3743ms.
[13:06:48.337] <TB3> INFO: Expecting 41600 events.
[13:06:51.835] <TB3> INFO: 41600 events read in total (2906ms).
[13:06:51.836] <TB3> INFO: Test took 3764ms.
[13:06:52.131] <TB3> INFO: Expecting 41600 events.
[13:06:55.598] <TB3> INFO: 41600 events read in total (2875ms).
[13:06:55.598] <TB3> INFO: Test took 3739ms.
[13:06:55.886] <TB3> INFO: Expecting 41600 events.
[13:06:59.512] <TB3> INFO: 41600 events read in total (3034ms).
[13:06:59.513] <TB3> INFO: Test took 3891ms.
[13:06:59.862] <TB3> INFO: Expecting 41600 events.
[13:07:03.447] <TB3> INFO: 41600 events read in total (2993ms).
[13:07:03.447] <TB3> INFO: Test took 3906ms.
[13:07:03.735] <TB3> INFO: Expecting 41600 events.
[13:07:07.259] <TB3> INFO: 41600 events read in total (2932ms).
[13:07:07.260] <TB3> INFO: Test took 3789ms.
[13:07:07.548] <TB3> INFO: Expecting 41600 events.
[13:07:11.006] <TB3> INFO: 41600 events read in total (2866ms).
[13:07:11.006] <TB3> INFO: Test took 3722ms.
[13:07:11.304] <TB3> INFO: Expecting 41600 events.
[13:07:14.790] <TB3> INFO: 41600 events read in total (2895ms).
[13:07:14.790] <TB3> INFO: Test took 3760ms.
[13:07:15.079] <TB3> INFO: Expecting 41600 events.
[13:07:18.564] <TB3> INFO: 41600 events read in total (2894ms).
[13:07:18.565] <TB3> INFO: Test took 3751ms.
[13:07:18.863] <TB3> INFO: Expecting 41600 events.
[13:07:22.446] <TB3> INFO: 41600 events read in total (2991ms).
[13:07:22.447] <TB3> INFO: Test took 3858ms.
[13:07:22.735] <TB3> INFO: Expecting 41600 events.
[13:07:26.342] <TB3> INFO: 41600 events read in total (3016ms).
[13:07:26.343] <TB3> INFO: Test took 3873ms.
[13:07:26.633] <TB3> INFO: Expecting 41600 events.
[13:07:30.169] <TB3> INFO: 41600 events read in total (2944ms).
[13:07:30.169] <TB3> INFO: Test took 3800ms.
[13:07:30.458] <TB3> INFO: Expecting 41600 events.
[13:07:33.994] <TB3> INFO: 41600 events read in total (2945ms).
[13:07:33.994] <TB3> INFO: Test took 3801ms.
[13:07:34.285] <TB3> INFO: Expecting 41600 events.
[13:07:37.832] <TB3> INFO: 41600 events read in total (2955ms).
[13:07:37.833] <TB3> INFO: Test took 3812ms.
[13:07:38.122] <TB3> INFO: Expecting 41600 events.
[13:07:41.587] <TB3> INFO: 41600 events read in total (2874ms).
[13:07:41.588] <TB3> INFO: Test took 3731ms.
[13:07:41.876] <TB3> INFO: Expecting 41600 events.
[13:07:45.398] <TB3> INFO: 41600 events read in total (2930ms).
[13:07:45.399] <TB3> INFO: Test took 3787ms.
[13:07:45.687] <TB3> INFO: Expecting 41600 events.
[13:07:49.193] <TB3> INFO: 41600 events read in total (2914ms).
[13:07:49.194] <TB3> INFO: Test took 3771ms.
[13:07:49.485] <TB3> INFO: Expecting 41600 events.
[13:07:53.021] <TB3> INFO: 41600 events read in total (2945ms).
[13:07:53.022] <TB3> INFO: Test took 3802ms.
[13:07:53.310] <TB3> INFO: Expecting 41600 events.
[13:07:56.757] <TB3> INFO: 41600 events read in total (2855ms).
[13:07:56.758] <TB3> INFO: Test took 3713ms.
[13:07:57.047] <TB3> INFO: Expecting 41600 events.
[13:08:00.489] <TB3> INFO: 41600 events read in total (2851ms).
[13:08:00.490] <TB3> INFO: Test took 3708ms.
[13:08:00.778] <TB3> INFO: Expecting 41600 events.
[13:08:04.271] <TB3> INFO: 41600 events read in total (2902ms).
[13:08:04.272] <TB3> INFO: Test took 3759ms.
[13:08:04.573] <TB3> INFO: Expecting 41600 events.
[13:08:08.147] <TB3> INFO: 41600 events read in total (2983ms).
[13:08:08.148] <TB3> INFO: Test took 3851ms.
[13:08:08.436] <TB3> INFO: Expecting 2560 events.
[13:08:09.322] <TB3> INFO: 2560 events read in total (294ms).
[13:08:09.322] <TB3> INFO: Test took 1162ms.
[13:08:09.629] <TB3> INFO: Expecting 2560 events.
[13:08:10.511] <TB3> INFO: 2560 events read in total (290ms).
[13:08:10.512] <TB3> INFO: Test took 1190ms.
[13:08:10.832] <TB3> INFO: Expecting 2560 events.
[13:08:11.715] <TB3> INFO: 2560 events read in total (292ms).
[13:08:11.715] <TB3> INFO: Test took 1203ms.
[13:08:12.023] <TB3> INFO: Expecting 2560 events.
[13:08:12.905] <TB3> INFO: 2560 events read in total (291ms).
[13:08:12.905] <TB3> INFO: Test took 1190ms.
[13:08:13.213] <TB3> INFO: Expecting 2560 events.
[13:08:14.091] <TB3> INFO: 2560 events read in total (286ms).
[13:08:14.091] <TB3> INFO: Test took 1185ms.
[13:08:14.399] <TB3> INFO: Expecting 2560 events.
[13:08:15.277] <TB3> INFO: 2560 events read in total (286ms).
[13:08:15.278] <TB3> INFO: Test took 1186ms.
[13:08:15.586] <TB3> INFO: Expecting 2560 events.
[13:08:16.468] <TB3> INFO: 2560 events read in total (291ms).
[13:08:16.468] <TB3> INFO: Test took 1190ms.
[13:08:16.776] <TB3> INFO: Expecting 2560 events.
[13:08:17.656] <TB3> INFO: 2560 events read in total (288ms).
[13:08:17.656] <TB3> INFO: Test took 1188ms.
[13:08:17.964] <TB3> INFO: Expecting 2560 events.
[13:08:18.843] <TB3> INFO: 2560 events read in total (287ms).
[13:08:18.843] <TB3> INFO: Test took 1187ms.
[13:08:19.151] <TB3> INFO: Expecting 2560 events.
[13:08:20.030] <TB3> INFO: 2560 events read in total (287ms).
[13:08:20.030] <TB3> INFO: Test took 1186ms.
[13:08:20.338] <TB3> INFO: Expecting 2560 events.
[13:08:21.217] <TB3> INFO: 2560 events read in total (288ms).
[13:08:21.217] <TB3> INFO: Test took 1187ms.
[13:08:21.525] <TB3> INFO: Expecting 2560 events.
[13:08:22.410] <TB3> INFO: 2560 events read in total (293ms).
[13:08:22.410] <TB3> INFO: Test took 1193ms.
[13:08:22.718] <TB3> INFO: Expecting 2560 events.
[13:08:23.603] <TB3> INFO: 2560 events read in total (293ms).
[13:08:23.603] <TB3> INFO: Test took 1192ms.
[13:08:23.911] <TB3> INFO: Expecting 2560 events.
[13:08:24.796] <TB3> INFO: 2560 events read in total (293ms).
[13:08:24.796] <TB3> INFO: Test took 1192ms.
[13:08:25.104] <TB3> INFO: Expecting 2560 events.
[13:08:25.986] <TB3> INFO: 2560 events read in total (290ms).
[13:08:25.986] <TB3> INFO: Test took 1189ms.
[13:08:26.294] <TB3> INFO: Expecting 2560 events.
[13:08:27.180] <TB3> INFO: 2560 events read in total (294ms).
[13:08:27.180] <TB3> INFO: Test took 1193ms.
[13:08:27.183] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:27.489] <TB3> INFO: Expecting 655360 events.
[13:08:41.806] <TB3> INFO: 655360 events read in total (13725ms).
[13:08:41.816] <TB3> INFO: Expecting 655360 events.
[13:08:55.938] <TB3> INFO: 655360 events read in total (13719ms).
[13:08:55.957] <TB3> INFO: Expecting 655360 events.
[13:09:10.071] <TB3> INFO: 655360 events read in total (13711ms).
[13:09:10.090] <TB3> INFO: Expecting 655360 events.
[13:09:24.324] <TB3> INFO: 655360 events read in total (13831ms).
[13:09:24.347] <TB3> INFO: Expecting 655360 events.
[13:09:38.404] <TB3> INFO: 655360 events read in total (13654ms).
[13:09:38.431] <TB3> INFO: Expecting 655360 events.
[13:09:52.502] <TB3> INFO: 655360 events read in total (13668ms).
[13:09:52.535] <TB3> INFO: Expecting 655360 events.
[13:10:06.690] <TB3> INFO: 655360 events read in total (13752ms).
[13:10:06.726] <TB3> INFO: Expecting 655360 events.
[13:10:20.807] <TB3> INFO: 655360 events read in total (13678ms).
[13:10:20.846] <TB3> INFO: Expecting 655360 events.
[13:10:34.866] <TB3> INFO: 655360 events read in total (13617ms).
[13:10:34.925] <TB3> INFO: Expecting 655360 events.
[13:10:48.883] <TB3> INFO: 655360 events read in total (13555ms).
[13:10:48.931] <TB3> INFO: Expecting 655360 events.
[13:11:03.014] <TB3> INFO: 655360 events read in total (13680ms).
[13:11:03.087] <TB3> INFO: Expecting 655360 events.
[13:11:17.179] <TB3> INFO: 655360 events read in total (13689ms).
[13:11:17.234] <TB3> INFO: Expecting 655360 events.
[13:11:31.258] <TB3> INFO: 655360 events read in total (13622ms).
[13:11:31.323] <TB3> INFO: Expecting 655360 events.
[13:11:45.346] <TB3> INFO: 655360 events read in total (13620ms).
[13:11:45.436] <TB3> INFO: Expecting 655360 events.
[13:11:59.503] <TB3> INFO: 655360 events read in total (13664ms).
[13:11:59.571] <TB3> INFO: Expecting 655360 events.
[13:12:13.588] <TB3> INFO: 655360 events read in total (13614ms).
[13:12:13.687] <TB3> INFO: Test took 226504ms.
[13:12:13.781] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:12:14.046] <TB3> INFO: Expecting 655360 events.
[13:12:27.001] <TB3> INFO: 655360 events read in total (13364ms).
[13:12:28.014] <TB3> INFO: Expecting 655360 events.
[13:12:42.043] <TB3> INFO: 655360 events read in total (13626ms).
[13:12:42.062] <TB3> INFO: Expecting 655360 events.
[13:12:56.043] <TB3> INFO: 655360 events read in total (13578ms).
[13:12:56.061] <TB3> INFO: Expecting 655360 events.
[13:13:09.913] <TB3> INFO: 655360 events read in total (13449ms).
[13:13:09.936] <TB3> INFO: Expecting 655360 events.
[13:13:23.896] <TB3> INFO: 655360 events read in total (13557ms).
[13:13:23.922] <TB3> INFO: Expecting 655360 events.
[13:13:37.937] <TB3> INFO: 655360 events read in total (13612ms).
[13:13:37.987] <TB3> INFO: Expecting 655360 events.
[13:13:51.773] <TB3> INFO: 655360 events read in total (13383ms).
[13:13:51.807] <TB3> INFO: Expecting 655360 events.
[13:14:05.542] <TB3> INFO: 655360 events read in total (13332ms).
[13:14:05.579] <TB3> INFO: Expecting 655360 events.
[13:14:19.322] <TB3> INFO: 655360 events read in total (13340ms).
[13:14:19.364] <TB3> INFO: Expecting 655360 events.
[13:14:33.171] <TB3> INFO: 655360 events read in total (13404ms).
[13:14:33.218] <TB3> INFO: Expecting 655360 events.
[13:14:46.881] <TB3> INFO: 655360 events read in total (13260ms).
[13:14:46.952] <TB3> INFO: Expecting 655360 events.
[13:15:00.887] <TB3> INFO: 655360 events read in total (13532ms).
[13:15:00.940] <TB3> INFO: Expecting 655360 events.
[13:15:14.701] <TB3> INFO: 655360 events read in total (13358ms).
[13:15:14.762] <TB3> INFO: Expecting 655360 events.
[13:15:28.664] <TB3> INFO: 655360 events read in total (13500ms).
[13:15:28.729] <TB3> INFO: Expecting 655360 events.
[13:15:42.561] <TB3> INFO: 655360 events read in total (13429ms).
[13:15:42.630] <TB3> INFO: Expecting 655360 events.
[13:15:56.627] <TB3> INFO: 655360 events read in total (13594ms).
[13:15:56.699] <TB3> INFO: Test took 222918ms.
[13:15:56.856] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:56.860] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:56.864] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:56.869] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:56.873] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[13:15:56.878] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[13:15:56.883] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:56.887] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:56.892] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[13:15:56.896] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[13:15:56.901] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[13:15:56.905] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[13:15:56.910] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[13:15:56.915] <TB3> INFO: safety margin for low PH: adding 6, margin is now 26
[13:15:56.920] <TB3> INFO: safety margin for low PH: adding 7, margin is now 27
[13:15:56.925] <TB3> INFO: safety margin for low PH: adding 8, margin is now 28
[13:15:56.929] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:56.934] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[13:15:56.939] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[13:15:56.944] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[13:15:56.951] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[13:15:56.957] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[13:15:56.963] <TB3> INFO: safety margin for low PH: adding 6, margin is now 26
[13:15:56.970] <TB3> INFO: safety margin for low PH: adding 7, margin is now 27
[13:15:56.976] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:56.983] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:56.989] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:56.995] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:56.002] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:57.008] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[13:15:57.015] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[13:15:57.021] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[13:15:57.028] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[13:15:57.034] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[13:15:57.040] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:57.047] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:57.054] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:57.060] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:57.096] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C0.dat
[13:15:57.097] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C1.dat
[13:15:57.097] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C2.dat
[13:15:57.097] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C3.dat
[13:15:57.097] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C4.dat
[13:15:57.097] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C5.dat
[13:15:57.097] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C6.dat
[13:15:57.097] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C7.dat
[13:15:57.097] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C8.dat
[13:15:57.097] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C9.dat
[13:15:57.097] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C10.dat
[13:15:57.098] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C11.dat
[13:15:57.098] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C12.dat
[13:15:57.098] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C13.dat
[13:15:57.098] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C14.dat
[13:15:57.098] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C15.dat
[13:15:57.378] <TB3> INFO: Expecting 41600 events.
[13:16:00.477] <TB3> INFO: 41600 events read in total (2507ms).
[13:16:00.478] <TB3> INFO: Test took 3377ms.
[13:16:00.921] <TB3> INFO: Expecting 41600 events.
[13:16:03.909] <TB3> INFO: 41600 events read in total (2397ms).
[13:16:03.910] <TB3> INFO: Test took 3221ms.
[13:16:04.353] <TB3> INFO: Expecting 41600 events.
[13:16:07.438] <TB3> INFO: 41600 events read in total (2493ms).
[13:16:07.439] <TB3> INFO: Test took 3318ms.
[13:16:07.653] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:07.741] <TB3> INFO: Expecting 2560 events.
[13:16:08.626] <TB3> INFO: 2560 events read in total (293ms).
[13:16:08.626] <TB3> INFO: Test took 973ms.
[13:16:08.628] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:08.934] <TB3> INFO: Expecting 2560 events.
[13:16:09.817] <TB3> INFO: 2560 events read in total (291ms).
[13:16:09.817] <TB3> INFO: Test took 1189ms.
[13:16:09.819] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:10.125] <TB3> INFO: Expecting 2560 events.
[13:16:11.009] <TB3> INFO: 2560 events read in total (292ms).
[13:16:11.009] <TB3> INFO: Test took 1190ms.
[13:16:11.011] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:11.318] <TB3> INFO: Expecting 2560 events.
[13:16:12.207] <TB3> INFO: 2560 events read in total (298ms).
[13:16:12.207] <TB3> INFO: Test took 1196ms.
[13:16:12.209] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:12.516] <TB3> INFO: Expecting 2560 events.
[13:16:13.401] <TB3> INFO: 2560 events read in total (294ms).
[13:16:13.401] <TB3> INFO: Test took 1192ms.
[13:16:13.402] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:13.709] <TB3> INFO: Expecting 2560 events.
[13:16:14.592] <TB3> INFO: 2560 events read in total (291ms).
[13:16:14.593] <TB3> INFO: Test took 1191ms.
[13:16:14.594] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:14.901] <TB3> INFO: Expecting 2560 events.
[13:16:15.784] <TB3> INFO: 2560 events read in total (291ms).
[13:16:15.784] <TB3> INFO: Test took 1190ms.
[13:16:15.786] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:16.092] <TB3> INFO: Expecting 2560 events.
[13:16:16.976] <TB3> INFO: 2560 events read in total (292ms).
[13:16:16.976] <TB3> INFO: Test took 1190ms.
[13:16:16.978] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:17.285] <TB3> INFO: Expecting 2560 events.
[13:16:18.164] <TB3> INFO: 2560 events read in total (288ms).
[13:16:18.164] <TB3> INFO: Test took 1186ms.
[13:16:18.166] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:18.472] <TB3> INFO: Expecting 2560 events.
[13:16:19.350] <TB3> INFO: 2560 events read in total (286ms).
[13:16:19.351] <TB3> INFO: Test took 1185ms.
[13:16:19.352] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:19.659] <TB3> INFO: Expecting 2560 events.
[13:16:20.538] <TB3> INFO: 2560 events read in total (288ms).
[13:16:20.539] <TB3> INFO: Test took 1187ms.
[13:16:20.540] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:20.847] <TB3> INFO: Expecting 2560 events.
[13:16:21.726] <TB3> INFO: 2560 events read in total (288ms).
[13:16:21.726] <TB3> INFO: Test took 1186ms.
[13:16:21.728] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:22.034] <TB3> INFO: Expecting 2560 events.
[13:16:22.916] <TB3> INFO: 2560 events read in total (290ms).
[13:16:22.916] <TB3> INFO: Test took 1188ms.
[13:16:22.918] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:23.224] <TB3> INFO: Expecting 2560 events.
[13:16:24.102] <TB3> INFO: 2560 events read in total (287ms).
[13:16:24.102] <TB3> INFO: Test took 1184ms.
[13:16:24.104] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:24.411] <TB3> INFO: Expecting 2560 events.
[13:16:25.288] <TB3> INFO: 2560 events read in total (286ms).
[13:16:25.289] <TB3> INFO: Test took 1186ms.
[13:16:25.290] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:25.597] <TB3> INFO: Expecting 2560 events.
[13:16:26.477] <TB3> INFO: 2560 events read in total (288ms).
[13:16:26.477] <TB3> INFO: Test took 1187ms.
[13:16:26.479] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:26.786] <TB3> INFO: Expecting 2560 events.
[13:16:27.667] <TB3> INFO: 2560 events read in total (290ms).
[13:16:27.668] <TB3> INFO: Test took 1189ms.
[13:16:27.669] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:27.976] <TB3> INFO: Expecting 2560 events.
[13:16:28.855] <TB3> INFO: 2560 events read in total (288ms).
[13:16:28.855] <TB3> INFO: Test took 1186ms.
[13:16:28.857] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:29.164] <TB3> INFO: Expecting 2560 events.
[13:16:30.042] <TB3> INFO: 2560 events read in total (287ms).
[13:16:30.042] <TB3> INFO: Test took 1185ms.
[13:16:30.044] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:30.351] <TB3> INFO: Expecting 2560 events.
[13:16:31.233] <TB3> INFO: 2560 events read in total (290ms).
[13:16:31.233] <TB3> INFO: Test took 1189ms.
[13:16:31.235] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:31.541] <TB3> INFO: Expecting 2560 events.
[13:16:32.421] <TB3> INFO: 2560 events read in total (288ms).
[13:16:32.421] <TB3> INFO: Test took 1186ms.
[13:16:32.423] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:32.730] <TB3> INFO: Expecting 2560 events.
[13:16:33.610] <TB3> INFO: 2560 events read in total (289ms).
[13:16:33.610] <TB3> INFO: Test took 1187ms.
[13:16:33.612] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:33.919] <TB3> INFO: Expecting 2560 events.
[13:16:34.796] <TB3> INFO: 2560 events read in total (286ms).
[13:16:34.797] <TB3> INFO: Test took 1185ms.
[13:16:34.799] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:35.105] <TB3> INFO: Expecting 2560 events.
[13:16:35.982] <TB3> INFO: 2560 events read in total (286ms).
[13:16:35.983] <TB3> INFO: Test took 1185ms.
[13:16:35.985] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:36.291] <TB3> INFO: Expecting 2560 events.
[13:16:37.173] <TB3> INFO: 2560 events read in total (291ms).
[13:16:37.173] <TB3> INFO: Test took 1188ms.
[13:16:37.175] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:37.482] <TB3> INFO: Expecting 2560 events.
[13:16:38.366] <TB3> INFO: 2560 events read in total (293ms).
[13:16:38.366] <TB3> INFO: Test took 1191ms.
[13:16:38.369] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:38.673] <TB3> INFO: Expecting 2560 events.
[13:16:39.557] <TB3> INFO: 2560 events read in total (292ms).
[13:16:39.557] <TB3> INFO: Test took 1188ms.
[13:16:39.559] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:39.865] <TB3> INFO: Expecting 2560 events.
[13:16:40.749] <TB3> INFO: 2560 events read in total (292ms).
[13:16:40.749] <TB3> INFO: Test took 1191ms.
[13:16:40.751] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:41.057] <TB3> INFO: Expecting 2560 events.
[13:16:41.943] <TB3> INFO: 2560 events read in total (294ms).
[13:16:41.943] <TB3> INFO: Test took 1192ms.
[13:16:41.945] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:42.251] <TB3> INFO: Expecting 2560 events.
[13:16:43.135] <TB3> INFO: 2560 events read in total (292ms).
[13:16:43.135] <TB3> INFO: Test took 1190ms.
[13:16:43.137] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:43.444] <TB3> INFO: Expecting 2560 events.
[13:16:44.329] <TB3> INFO: 2560 events read in total (294ms).
[13:16:44.329] <TB3> INFO: Test took 1192ms.
[13:16:44.331] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:44.638] <TB3> INFO: Expecting 2560 events.
[13:16:45.521] <TB3> INFO: 2560 events read in total (292ms).
[13:16:45.521] <TB3> INFO: Test took 1190ms.
[13:16:45.983] <TB3> INFO: PixTestPhOptimization::doTest() done, duration: 632 seconds
[13:16:45.983] <TB3> INFO: PH scale (per ROC): 49 49 50 48 45 48 42 32 63 45 44 41 55 51 54 47
[13:16:45.983] <TB3> INFO: PH offset (per ROC): 120 129 132 93 93 123 80 90 117 99 106 91 119 124 127 99
[13:16:45.989] <TB3> INFO: Decoding statistics:
[13:16:45.989] <TB3> INFO: General information:
[13:16:45.989] <TB3> INFO: 16bit words read: 127876
[13:16:45.989] <TB3> INFO: valid events total: 20480
[13:16:45.989] <TB3> INFO: empty events: 17982
[13:16:45.989] <TB3> INFO: valid events with pixels: 2498
[13:16:45.989] <TB3> INFO: valid pixel hits: 2498
[13:16:45.989] <TB3> INFO: Event errors: 0
[13:16:45.989] <TB3> INFO: start marker: 0
[13:16:45.989] <TB3> INFO: stop marker: 0
[13:16:45.989] <TB3> INFO: overflow: 0
[13:16:45.989] <TB3> INFO: invalid 5bit words: 0
[13:16:45.989] <TB3> INFO: invalid XOR eye diagram: 0
[13:16:45.989] <TB3> INFO: frame (failed synchr.): 0
[13:16:45.989] <TB3> INFO: idle data (no TBM trl): 0
[13:16:45.989] <TB3> INFO: no data (only TBM hdr): 0
[13:16:45.989] <TB3> INFO: TBM errors: 0
[13:16:45.989] <TB3> INFO: flawed TBM headers: 0
[13:16:45.989] <TB3> INFO: flawed TBM trailers: 0
[13:16:45.989] <TB3> INFO: event ID mismatches: 0
[13:16:45.989] <TB3> INFO: ROC errors: 0
[13:16:45.989] <TB3> INFO: missing ROC header(s): 0
[13:16:45.989] <TB3> INFO: misplaced readback start: 0
[13:16:45.989] <TB3> INFO: Pixel decoding errors: 0
[13:16:45.989] <TB3> INFO: pixel data incomplete: 0
[13:16:45.989] <TB3> INFO: pixel address: 0
[13:16:45.989] <TB3> INFO: pulse height fill bit: 0
[13:16:45.989] <TB3> INFO: buffer corruption: 0
[13:16:46.257] <TB3> INFO: ######################################################################
[13:16:46.257] <TB3> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:16:46.257] <TB3> INFO: ######################################################################
[13:16:46.270] <TB3> INFO: scanning low vcal = 10
[13:16:46.501] <TB3> INFO: Expecting 41600 events.
[13:16:50.046] <TB3> INFO: 41600 events read in total (2953ms).
[13:16:50.046] <TB3> INFO: Test took 3776ms.
[13:16:50.048] <TB3> INFO: scanning low vcal = 20
[13:16:50.347] <TB3> INFO: Expecting 41600 events.
[13:16:53.895] <TB3> INFO: 41600 events read in total (2956ms).
[13:16:53.895] <TB3> INFO: Test took 3847ms.
[13:16:53.897] <TB3> INFO: scanning low vcal = 30
[13:16:54.196] <TB3> INFO: Expecting 41600 events.
[13:16:57.840] <TB3> INFO: 41600 events read in total (3052ms).
[13:16:57.841] <TB3> INFO: Test took 3944ms.
[13:16:57.843] <TB3> INFO: scanning low vcal = 40
[13:16:58.120] <TB3> INFO: Expecting 41600 events.
[13:17:02.027] <TB3> INFO: 41600 events read in total (3315ms).
[13:17:02.028] <TB3> INFO: Test took 4185ms.
[13:17:02.030] <TB3> INFO: scanning low vcal = 50
[13:17:02.307] <TB3> INFO: Expecting 41600 events.
[13:17:06.247] <TB3> INFO: 41600 events read in total (3348ms).
[13:17:06.248] <TB3> INFO: Test took 4218ms.
[13:17:06.250] <TB3> INFO: scanning low vcal = 60
[13:17:06.527] <TB3> INFO: Expecting 41600 events.
[13:17:10.512] <TB3> INFO: 41600 events read in total (3393ms).
[13:17:10.513] <TB3> INFO: Test took 4263ms.
[13:17:10.516] <TB3> INFO: scanning low vcal = 70
[13:17:10.792] <TB3> INFO: Expecting 41600 events.
[13:17:14.733] <TB3> INFO: 41600 events read in total (3349ms).
[13:17:14.734] <TB3> INFO: Test took 4218ms.
[13:17:14.737] <TB3> INFO: scanning low vcal = 80
[13:17:15.014] <TB3> INFO: Expecting 41600 events.
[13:17:18.941] <TB3> INFO: 41600 events read in total (3335ms).
[13:17:18.941] <TB3> INFO: Test took 4204ms.
[13:17:18.944] <TB3> INFO: scanning low vcal = 90
[13:17:19.221] <TB3> INFO: Expecting 41600 events.
[13:17:23.222] <TB3> INFO: 41600 events read in total (3410ms).
[13:17:23.223] <TB3> INFO: Test took 4279ms.
[13:17:23.226] <TB3> INFO: scanning low vcal = 100
[13:17:23.503] <TB3> INFO: Expecting 41600 events.
[13:17:27.467] <TB3> INFO: 41600 events read in total (3373ms).
[13:17:27.468] <TB3> INFO: Test took 4242ms.
[13:17:27.471] <TB3> INFO: scanning low vcal = 110
[13:17:27.748] <TB3> INFO: Expecting 41600 events.
[13:17:31.729] <TB3> INFO: 41600 events read in total (3390ms).
[13:17:31.730] <TB3> INFO: Test took 4259ms.
[13:17:31.733] <TB3> INFO: scanning low vcal = 120
[13:17:32.009] <TB3> INFO: Expecting 41600 events.
[13:17:35.944] <TB3> INFO: 41600 events read in total (3343ms).
[13:17:35.945] <TB3> INFO: Test took 4212ms.
[13:17:35.948] <TB3> INFO: scanning low vcal = 130
[13:17:36.224] <TB3> INFO: Expecting 41600 events.
[13:17:40.164] <TB3> INFO: 41600 events read in total (3349ms).
[13:17:40.164] <TB3> INFO: Test took 4216ms.
[13:17:40.167] <TB3> INFO: scanning low vcal = 140
[13:17:40.444] <TB3> INFO: Expecting 41600 events.
[13:17:44.394] <TB3> INFO: 41600 events read in total (3358ms).
[13:17:44.395] <TB3> INFO: Test took 4228ms.
[13:17:44.398] <TB3> INFO: scanning low vcal = 150
[13:17:44.674] <TB3> INFO: Expecting 41600 events.
[13:17:48.628] <TB3> INFO: 41600 events read in total (3362ms).
[13:17:48.628] <TB3> INFO: Test took 4230ms.
[13:17:48.631] <TB3> INFO: scanning low vcal = 160
[13:17:48.908] <TB3> INFO: Expecting 41600 events.
[13:17:52.851] <TB3> INFO: 41600 events read in total (3352ms).
[13:17:52.852] <TB3> INFO: Test took 4221ms.
[13:17:52.855] <TB3> INFO: scanning low vcal = 170
[13:17:53.131] <TB3> INFO: Expecting 41600 events.
[13:17:57.053] <TB3> INFO: 41600 events read in total (3330ms).
[13:17:57.054] <TB3> INFO: Test took 4199ms.
[13:17:57.056] <TB3> INFO: scanning low vcal = 180
[13:17:57.333] <TB3> INFO: Expecting 41600 events.
[13:18:01.263] <TB3> INFO: 41600 events read in total (3339ms).
[13:18:01.264] <TB3> INFO: Test took 4208ms.
[13:18:01.266] <TB3> INFO: scanning low vcal = 190
[13:18:01.543] <TB3> INFO: Expecting 41600 events.
[13:18:05.526] <TB3> INFO: 41600 events read in total (3391ms).
[13:18:05.527] <TB3> INFO: Test took 4261ms.
[13:18:05.530] <TB3> INFO: scanning low vcal = 200
[13:18:05.806] <TB3> INFO: Expecting 41600 events.
[13:18:09.752] <TB3> INFO: 41600 events read in total (3354ms).
[13:18:09.752] <TB3> INFO: Test took 4222ms.
[13:18:09.755] <TB3> INFO: scanning low vcal = 210
[13:18:10.032] <TB3> INFO: Expecting 41600 events.
[13:18:13.955] <TB3> INFO: 41600 events read in total (3332ms).
[13:18:13.956] <TB3> INFO: Test took 4201ms.
[13:18:13.959] <TB3> INFO: scanning low vcal = 220
[13:18:14.235] <TB3> INFO: Expecting 41600 events.
[13:18:18.215] <TB3> INFO: 41600 events read in total (3389ms).
[13:18:18.216] <TB3> INFO: Test took 4257ms.
[13:18:18.219] <TB3> INFO: scanning low vcal = 230
[13:18:18.496] <TB3> INFO: Expecting 41600 events.
[13:18:22.435] <TB3> INFO: 41600 events read in total (3348ms).
[13:18:22.436] <TB3> INFO: Test took 4217ms.
[13:18:22.439] <TB3> INFO: scanning low vcal = 240
[13:18:22.715] <TB3> INFO: Expecting 41600 events.
[13:18:26.697] <TB3> INFO: 41600 events read in total (3390ms).
[13:18:26.697] <TB3> INFO: Test took 4258ms.
[13:18:26.700] <TB3> INFO: scanning low vcal = 250
[13:18:26.977] <TB3> INFO: Expecting 41600 events.
[13:18:30.902] <TB3> INFO: 41600 events read in total (3334ms).
[13:18:30.903] <TB3> INFO: Test took 4203ms.
[13:18:30.907] <TB3> INFO: scanning high vcal = 30 (= 210 in low range)
[13:18:31.183] <TB3> INFO: Expecting 41600 events.
[13:18:35.132] <TB3> INFO: 41600 events read in total (3357ms).
[13:18:35.133] <TB3> INFO: Test took 4226ms.
[13:18:35.136] <TB3> INFO: scanning high vcal = 50 (= 350 in low range)
[13:18:35.412] <TB3> INFO: Expecting 41600 events.
[13:18:39.391] <TB3> INFO: 41600 events read in total (3387ms).
[13:18:39.392] <TB3> INFO: Test took 4256ms.
[13:18:39.394] <TB3> INFO: scanning high vcal = 70 (= 490 in low range)
[13:18:39.671] <TB3> INFO: Expecting 41600 events.
[13:18:43.606] <TB3> INFO: 41600 events read in total (3343ms).
[13:18:43.607] <TB3> INFO: Test took 4212ms.
[13:18:43.609] <TB3> INFO: scanning high vcal = 90 (= 630 in low range)
[13:18:43.886] <TB3> INFO: Expecting 41600 events.
[13:18:47.830] <TB3> INFO: 41600 events read in total (3352ms).
[13:18:47.831] <TB3> INFO: Test took 4221ms.
[13:18:47.834] <TB3> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:18:48.111] <TB3> INFO: Expecting 41600 events.
[13:18:52.052] <TB3> INFO: 41600 events read in total (3350ms).
[13:18:52.053] <TB3> INFO: Test took 4219ms.
[13:18:52.658] <TB3> INFO: PixTestGainPedestal::measure() done
[13:19:34.345] <TB3> INFO: PixTestGainPedestal::fit() done
[13:19:34.345] <TB3> INFO: non-linearity mean: 0.980 0.981 0.978 0.956 0.955 0.979 0.935 0.958 0.986 0.938 0.931 0.939 0.985 0.980 0.982 0.952
[13:19:34.345] <TB3> INFO: non-linearity RMS: 0.003 0.005 0.005 0.045 0.042 0.004 0.085 0.017 0.003 0.070 0.136 0.142 0.003 0.005 0.003 0.072
[13:19:34.345] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[13:19:34.365] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[13:19:34.387] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[13:19:34.409] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[13:19:34.431] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[13:19:34.452] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[13:19:34.466] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[13:19:34.479] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[13:19:34.493] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[13:19:34.506] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[13:19:34.521] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[13:19:34.544] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[13:19:34.565] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[13:19:34.587] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[13:19:34.609] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[13:19:34.630] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[13:19:34.652] <TB3> INFO: PixTestGainPedestal::fullTest() done, duration: 168 seconds
[13:19:34.652] <TB3> INFO: Decoding statistics:
[13:19:34.652] <TB3> INFO: General information:
[13:19:34.652] <TB3> INFO: 16bit words read: 3281510
[13:19:34.652] <TB3> INFO: valid events total: 332800
[13:19:34.652] <TB3> INFO: empty events: 3500
[13:19:34.652] <TB3> INFO: valid events with pixels: 329300
[13:19:34.652] <TB3> INFO: valid pixel hits: 642355
[13:19:34.652] <TB3> INFO: Event errors: 0
[13:19:34.652] <TB3> INFO: start marker: 0
[13:19:34.652] <TB3> INFO: stop marker: 0
[13:19:34.652] <TB3> INFO: overflow: 0
[13:19:34.652] <TB3> INFO: invalid 5bit words: 0
[13:19:34.652] <TB3> INFO: invalid XOR eye diagram: 0
[13:19:34.652] <TB3> INFO: frame (failed synchr.): 0
[13:19:34.652] <TB3> INFO: idle data (no TBM trl): 0
[13:19:34.652] <TB3> INFO: no data (only TBM hdr): 0
[13:19:34.652] <TB3> INFO: TBM errors: 0
[13:19:34.652] <TB3> INFO: flawed TBM headers: 0
[13:19:34.652] <TB3> INFO: flawed TBM trailers: 0
[13:19:34.652] <TB3> INFO: event ID mismatches: 0
[13:19:34.652] <TB3> INFO: ROC errors: 0
[13:19:34.652] <TB3> INFO: missing ROC header(s): 0
[13:19:34.652] <TB3> INFO: misplaced readback start: 0
[13:19:34.652] <TB3> INFO: Pixel decoding errors: 0
[13:19:34.652] <TB3> INFO: pixel data incomplete: 0
[13:19:34.652] <TB3> INFO: pixel address: 0
[13:19:34.652] <TB3> INFO: pulse height fill bit: 0
[13:19:34.652] <TB3> INFO: buffer corruption: 0
[13:19:34.671] <TB3> INFO: Decoding statistics:
[13:19:34.671] <TB3> INFO: General information:
[13:19:34.671] <TB3> INFO: 16bit words read: 3410922
[13:19:34.671] <TB3> INFO: valid events total: 353536
[13:19:34.671] <TB3> INFO: empty events: 21738
[13:19:34.671] <TB3> INFO: valid events with pixels: 331798
[13:19:34.671] <TB3> INFO: valid pixel hits: 644853
[13:19:34.671] <TB3> INFO: Event errors: 0
[13:19:34.671] <TB3> INFO: start marker: 0
[13:19:34.671] <TB3> INFO: stop marker: 0
[13:19:34.671] <TB3> INFO: overflow: 0
[13:19:34.671] <TB3> INFO: invalid 5bit words: 0
[13:19:34.671] <TB3> INFO: invalid XOR eye diagram: 0
[13:19:34.671] <TB3> INFO: frame (failed synchr.): 0
[13:19:34.671] <TB3> INFO: idle data (no TBM trl): 0
[13:19:34.671] <TB3> INFO: no data (only TBM hdr): 0
[13:19:34.671] <TB3> INFO: TBM errors: 0
[13:19:34.671] <TB3> INFO: flawed TBM headers: 0
[13:19:34.671] <TB3> INFO: flawed TBM trailers: 0
[13:19:34.671] <TB3> INFO: event ID mismatches: 0
[13:19:34.671] <TB3> INFO: ROC errors: 0
[13:19:34.671] <TB3> INFO: missing ROC header(s): 0
[13:19:34.671] <TB3> INFO: misplaced readback start: 0
[13:19:34.672] <TB3> INFO: Pixel decoding errors: 0
[13:19:34.672] <TB3> INFO: pixel data incomplete: 0
[13:19:34.672] <TB3> INFO: pixel address: 0
[13:19:34.672] <TB3> INFO: pulse height fill bit: 0
[13:19:34.672] <TB3> INFO: buffer corruption: 0
[13:19:34.672] <TB3> INFO: enter test to run
[13:19:34.672] <TB3> INFO: test: Trim80 no parameter change
[13:19:34.672] <TB3> INFO: running: trim80
[13:19:34.695] <TB3> INFO: ######################################################################
[13:19:34.695] <TB3> INFO: PixTestTrim80::doTest()
[13:19:34.695] <TB3> INFO: ######################################################################
[13:19:34.696] <TB3> INFO: ----------------------------------------------------------------------
[13:19:34.696] <TB3> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[13:19:34.696] <TB3> INFO: ----------------------------------------------------------------------
[13:19:34.739] <TB3> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:19:34.739] <TB3> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:19:34.749] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:19:34.749] <TB3> INFO: run 1 of 1
[13:19:34.990] <TB3> INFO: Expecting 5025280 events.
[13:20:02.639] <TB3> INFO: 679552 events read in total (27057ms).
[13:20:29.685] <TB3> INFO: 1354736 events read in total (54103ms).
[13:20:56.955] <TB3> INFO: 2027576 events read in total (81373ms).
[13:21:23.559] <TB3> INFO: 2697680 events read in total (107977ms).
[13:21:50.442] <TB3> INFO: 3366160 events read in total (134860ms).
[13:22:17.531] <TB3> INFO: 4032544 events read in total (161949ms).
[13:22:43.913] <TB3> INFO: 4697768 events read in total (188331ms).
[13:22:56.933] <TB3> INFO: 5025280 events read in total (201351ms).
[13:22:57.011] <TB3> INFO: Test took 202262ms.
[13:23:19.844] <TB3> INFO: ROC 0 VthrComp = 79
[13:23:19.845] <TB3> INFO: ROC 1 VthrComp = 77
[13:23:19.845] <TB3> INFO: ROC 2 VthrComp = 72
[13:23:19.845] <TB3> INFO: ROC 3 VthrComp = 74
[13:23:19.845] <TB3> INFO: ROC 4 VthrComp = 77
[13:23:19.845] <TB3> INFO: ROC 5 VthrComp = 82
[13:23:19.846] <TB3> INFO: ROC 6 VthrComp = 82
[13:23:19.846] <TB3> INFO: ROC 7 VthrComp = 80
[13:23:19.846] <TB3> INFO: ROC 8 VthrComp = 74
[13:23:19.846] <TB3> INFO: ROC 9 VthrComp = 75
[13:23:19.846] <TB3> INFO: ROC 10 VthrComp = 86
[13:23:19.846] <TB3> INFO: ROC 11 VthrComp = 69
[13:23:19.846] <TB3> INFO: ROC 12 VthrComp = 73
[13:23:19.846] <TB3> INFO: ROC 13 VthrComp = 84
[13:23:19.846] <TB3> INFO: ROC 14 VthrComp = 81
[13:23:19.846] <TB3> INFO: ROC 15 VthrComp = 78
[13:23:20.103] <TB3> INFO: Expecting 41600 events.
[13:23:23.513] <TB3> INFO: 41600 events read in total (2819ms).
[13:23:23.514] <TB3> INFO: Test took 3666ms.
[13:23:23.523] <TB3> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:23:23.523] <TB3> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:23:23.531] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:23:23.531] <TB3> INFO: run 1 of 1
[13:23:23.809] <TB3> INFO: Expecting 5025280 events.
[13:23:52.026] <TB3> INFO: 686688 events read in total (27625ms).
[13:24:19.153] <TB3> INFO: 1368736 events read in total (54752ms).
[13:24:46.132] <TB3> INFO: 2050808 events read in total (81731ms).
[13:25:13.300] <TB3> INFO: 2729504 events read in total (108899ms).
[13:25:40.162] <TB3> INFO: 3403912 events read in total (135761ms).
[13:26:07.052] <TB3> INFO: 4076584 events read in total (162651ms).
[13:26:33.745] <TB3> INFO: 4748488 events read in total (189344ms).
[13:26:45.121] <TB3> INFO: 5025280 events read in total (200720ms).
[13:26:45.168] <TB3> INFO: Test took 201636ms.
[13:27:08.270] <TB3> INFO: roc 0 with ID = 0 has maximal Vcal 109.887 for pixel 0/2 mean/min/max = 94.0454/78.0939/109.997
[13:27:08.270] <TB3> INFO: roc 1 with ID = 1 has maximal Vcal 109.646 for pixel 14/74 mean/min/max = 94.377/78.7141/110.04
[13:27:08.271] <TB3> INFO: roc 2 with ID = 2 has maximal Vcal 110.744 for pixel 0/56 mean/min/max = 94.002/77.237/110.767
[13:27:08.271] <TB3> INFO: roc 3 with ID = 3 has maximal Vcal 108.532 for pixel 9/77 mean/min/max = 92.9423/77.1293/108.755
[13:27:08.271] <TB3> INFO: roc 4 with ID = 4 has maximal Vcal 109.215 for pixel 1/13 mean/min/max = 93.5177/77.4917/109.544
[13:27:08.272] <TB3> INFO: roc 5 with ID = 5 has maximal Vcal 108.212 for pixel 5/2 mean/min/max = 91.5625/74.864/108.261
[13:27:08.272] <TB3> INFO: roc 6 with ID = 6 has maximal Vcal 108.737 for pixel 12/79 mean/min/max = 92.2184/75.2316/109.205
[13:27:08.273] <TB3> INFO: roc 7 with ID = 7 has maximal Vcal 112.82 for pixel 16/79 mean/min/max = 93.7585/74.6733/112.844
[13:27:08.273] <TB3> INFO: roc 8 with ID = 8 has maximal Vcal 111.2 for pixel 51/20 mean/min/max = 94.4245/77.4864/111.363
[13:27:08.273] <TB3> INFO: roc 9 with ID = 9 has maximal Vcal 109.777 for pixel 6/8 mean/min/max = 93.6596/77.3886/109.931
[13:27:08.274] <TB3> INFO: roc 10 with ID = 10 has maximal Vcal 110.494 for pixel 2/31 mean/min/max = 92.2891/74.061/110.517
[13:27:08.274] <TB3> INFO: roc 11 with ID = 11 has maximal Vcal 105.077 for pixel 0/14 mean/min/max = 89.3911/73.652/105.13
[13:27:08.274] <TB3> INFO: roc 12 with ID = 12 has maximal Vcal 110.151 for pixel 0/4 mean/min/max = 93.9362/77.7028/110.17
[13:27:08.274] <TB3> INFO: roc 13 with ID = 13 has maximal Vcal 108.126 for pixel 0/22 mean/min/max = 91.9195/75.7056/108.133
[13:27:08.275] <TB3> INFO: roc 14 with ID = 14 has maximal Vcal 107.808 for pixel 16/32 mean/min/max = 91.3455/74.6749/108.016
[13:27:08.275] <TB3> INFO: roc 15 with ID = 15 has maximal Vcal 111.247 for pixel 0/34 mean/min/max = 94.3037/77.0939/111.514
[13:27:08.275] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:27:08.364] <TB3> INFO: Expecting 411648 events.
[13:27:17.584] <TB3> INFO: 411648 events read in total (8628ms).
[13:27:17.592] <TB3> INFO: Expecting 411648 events.
[13:27:26.712] <TB3> INFO: 411648 events read in total (8717ms).
[13:27:26.722] <TB3> INFO: Expecting 411648 events.
[13:27:35.779] <TB3> INFO: 411648 events read in total (8654ms).
[13:27:35.791] <TB3> INFO: Expecting 411648 events.
[13:27:44.988] <TB3> INFO: 411648 events read in total (8794ms).
[13:27:44.002] <TB3> INFO: Expecting 411648 events.
[13:27:54.076] <TB3> INFO: 411648 events read in total (8671ms).
[13:27:54.093] <TB3> INFO: Expecting 411648 events.
[13:28:03.186] <TB3> INFO: 411648 events read in total (8690ms).
[13:28:03.206] <TB3> INFO: Expecting 411648 events.
[13:28:12.502] <TB3> INFO: 411648 events read in total (8893ms).
[13:28:12.524] <TB3> INFO: Expecting 411648 events.
[13:28:21.671] <TB3> INFO: 411648 events read in total (8744ms).
[13:28:21.696] <TB3> INFO: Expecting 411648 events.
[13:28:30.734] <TB3> INFO: 411648 events read in total (8635ms).
[13:28:30.764] <TB3> INFO: Expecting 411648 events.
[13:28:39.797] <TB3> INFO: 411648 events read in total (8630ms).
[13:28:39.837] <TB3> INFO: Expecting 411648 events.
[13:28:48.829] <TB3> INFO: 411648 events read in total (8589ms).
[13:28:48.863] <TB3> INFO: Expecting 411648 events.
[13:28:57.904] <TB3> INFO: 411648 events read in total (8638ms).
[13:28:57.942] <TB3> INFO: Expecting 411648 events.
[13:29:06.933] <TB3> INFO: 411648 events read in total (8588ms).
[13:29:06.985] <TB3> INFO: Expecting 411648 events.
[13:29:16.062] <TB3> INFO: 411648 events read in total (8674ms).
[13:29:16.104] <TB3> INFO: Expecting 411648 events.
[13:29:25.182] <TB3> INFO: 411648 events read in total (8675ms).
[13:29:25.228] <TB3> INFO: Expecting 411648 events.
[13:29:34.325] <TB3> INFO: 411648 events read in total (8694ms).
[13:29:34.373] <TB3> INFO: Test took 146098ms.
[13:29:35.802] <TB3> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:29:35.813] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:29:35.813] <TB3> INFO: run 1 of 1
[13:29:36.043] <TB3> INFO: Expecting 5025280 events.
[13:30:02.974] <TB3> INFO: 666752 events read in total (26339ms).
[13:30:29.547] <TB3> INFO: 1330456 events read in total (52912ms).
[13:30:55.798] <TB3> INFO: 1992816 events read in total (79163ms).
[13:31:22.139] <TB3> INFO: 2652848 events read in total (105504ms).
[13:31:48.772] <TB3> INFO: 3308896 events read in total (132137ms).
[13:32:15.060] <TB3> INFO: 3963864 events read in total (158425ms).
[13:32:41.653] <TB3> INFO: 4615760 events read in total (185018ms).
[13:32:58.776] <TB3> INFO: 5025280 events read in total (202141ms).
[13:32:58.835] <TB3> INFO: Test took 203022ms.
[13:33:23.389] <TB3> INFO: ---> TrimStepCorr4 extremal thresholds: 49.402787 .. 121.749763
[13:33:23.621] <TB3> INFO: Expecting 208000 events.
[13:33:33.672] <TB3> INFO: 208000 events read in total (9458ms).
[13:33:33.673] <TB3> INFO: Test took 10283ms.
[13:33:33.721] <TB3> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 39 .. 131 (-1/-1) hits flags = 528 (plus default)
[13:33:33.734] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:33:33.734] <TB3> INFO: run 1 of 1
[13:33:34.036] <TB3> INFO: Expecting 3095040 events.
[13:34:01.458] <TB3> INFO: 652880 events read in total (26830ms).
[13:34:27.868] <TB3> INFO: 1304432 events read in total (53240ms).
[13:34:54.395] <TB3> INFO: 1952656 events read in total (79767ms).
[13:35:20.928] <TB3> INFO: 2597752 events read in total (106300ms).
[13:35:41.285] <TB3> INFO: 3095040 events read in total (126657ms).
[13:35:41.330] <TB3> INFO: Test took 127597ms.
[13:36:03.786] <TB3> INFO: ---> TrimStepCorr2 extremal thresholds: 61.180620 .. 107.517445
[13:36:04.037] <TB3> INFO: Expecting 208000 events.
[13:36:13.880] <TB3> INFO: 208000 events read in total (9251ms).
[13:36:13.880] <TB3> INFO: Test took 10092ms.
[13:36:13.925] <TB3> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 51 .. 117 (-1/-1) hits flags = 528 (plus default)
[13:36:13.936] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:36:13.936] <TB3> INFO: run 1 of 1
[13:36:14.214] <TB3> INFO: Expecting 2229760 events.
[13:36:41.642] <TB3> INFO: 647944 events read in total (26836ms).
[13:37:08.018] <TB3> INFO: 1295928 events read in total (53212ms).
[13:37:34.497] <TB3> INFO: 1942736 events read in total (79691ms).
[13:37:46.879] <TB3> INFO: 2229760 events read in total (92073ms).
[13:37:46.923] <TB3> INFO: Test took 92987ms.
[13:38:07.041] <TB3> INFO: ---> TrimStepCorr1a extremal thresholds: 67.434056 .. 99.037969
[13:38:07.273] <TB3> INFO: Expecting 208000 events.
[13:38:16.950] <TB3> INFO: 208000 events read in total (9085ms).
[13:38:16.951] <TB3> INFO: Test took 9909ms.
[13:38:16.999] <TB3> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 57 .. 109 (-1/-1) hits flags = 528 (plus default)
[13:38:17.009] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:38:17.009] <TB3> INFO: run 1 of 1
[13:38:17.287] <TB3> INFO: Expecting 1763840 events.
[13:38:44.922] <TB3> INFO: 649544 events read in total (27044ms).
[13:39:11.902] <TB3> INFO: 1298992 events read in total (54024ms).
[13:39:31.193] <TB3> INFO: 1763840 events read in total (73315ms).
[13:39:31.224] <TB3> INFO: Test took 74215ms.
[13:39:50.825] <TB3> INFO: ---> TrimStepCorr1b extremal thresholds: 68.669411 .. 99.037969
[13:39:51.097] <TB3> INFO: Expecting 208000 events.
[13:40:00.530] <TB3> INFO: 208000 events read in total (8841ms).
[13:40:00.531] <TB3> INFO: Test took 9704ms.
[13:40:00.586] <TB3> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 58 .. 109 (-1/-1) hits flags = 528 (plus default)
[13:40:00.595] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:40:00.595] <TB3> INFO: run 1 of 1
[13:40:00.873] <TB3> INFO: Expecting 1730560 events.
[13:40:28.610] <TB3> INFO: 647088 events read in total (27146ms).
[13:40:55.601] <TB3> INFO: 1293792 events read in total (54137ms).
[13:41:13.812] <TB3> INFO: 1730560 events read in total (72348ms).
[13:41:13.841] <TB3> INFO: Test took 73246ms.
[13:41:32.257] <TB3> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[13:41:32.257] <TB3> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[13:41:32.267] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:41:32.267] <TB3> INFO: run 1 of 1
[13:41:32.518] <TB3> INFO: Expecting 1364480 events.
[13:42:00.636] <TB3> INFO: 668016 events read in total (27527ms).
[13:42:28.283] <TB3> INFO: 1335848 events read in total (55175ms).
[13:42:29.856] <TB3> INFO: 1364480 events read in total (56747ms).
[13:42:29.877] <TB3> INFO: Test took 57611ms.
[13:42:45.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C0.dat
[13:42:45.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C1.dat
[13:42:45.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C2.dat
[13:42:45.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C3.dat
[13:42:45.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C4.dat
[13:42:45.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C5.dat
[13:42:45.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C6.dat
[13:42:45.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C7.dat
[13:42:45.548] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C8.dat
[13:42:45.548] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C9.dat
[13:42:45.548] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C10.dat
[13:42:45.548] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C11.dat
[13:42:45.548] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C12.dat
[13:42:45.548] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C13.dat
[13:42:45.548] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C14.dat
[13:42:45.548] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C15.dat
[13:42:45.548] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C0.dat
[13:42:45.555] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C1.dat
[13:42:45.563] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C2.dat
[13:42:45.570] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C3.dat
[13:42:45.578] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C4.dat
[13:42:45.585] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C5.dat
[13:42:45.593] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C6.dat
[13:42:45.601] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C7.dat
[13:42:45.608] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C8.dat
[13:42:45.616] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C9.dat
[13:42:45.623] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C10.dat
[13:42:45.630] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C11.dat
[13:42:45.637] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C12.dat
[13:42:45.645] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C13.dat
[13:42:45.652] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C14.dat
[13:42:45.660] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1124_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C15.dat
[13:42:45.667] <TB3> INFO: PixTestTrim80::trimTest() done
[13:42:45.667] <TB3> INFO: vtrim: 111 101 109 121 112 114 108 118 132 123 107 84 114 117 115 116
[13:42:45.667] <TB3> INFO: vthrcomp: 79 77 72 74 77 82 82 80 74 75 86 69 73 84 81 78
[13:42:45.667] <TB3> INFO: vcal mean: 80.00 79.95 79.97 79.96 79.96 79.98 79.95 79.95 79.98 79.95 79.93 79.95 79.94 79.95 79.96 79.95
[13:42:45.667] <TB3> INFO: vcal RMS: 0.77 1.44 0.72 0.76 0.84 0.79 0.78 0.85 0.74 0.77 0.81 0.73 0.77 0.76 0.76 0.76
[13:42:45.667] <TB3> INFO: bits mean: 9.39 9.04 9.62 10.40 9.86 10.35 10.14 10.58 9.87 9.90 10.20 10.71 10.05 10.34 10.79 9.94
[13:42:45.667] <TB3> INFO: bits RMS: 2.21 2.32 2.22 1.92 2.10 2.29 2.25 2.07 2.03 2.12 2.40 2.36 1.98 2.13 2.07 2.08
[13:42:45.674] <TB3> INFO: ----------------------------------------------------------------------
[13:42:45.674] <TB3> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:42:45.674] <TB3> INFO: ----------------------------------------------------------------------
[13:42:45.676] <TB3> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:42:45.685] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:42:45.685] <TB3> INFO: run 1 of 1
[13:42:45.917] <TB3> INFO: Expecting 4160000 events.
[13:43:18.179] <TB3> INFO: 774000 events read in total (31671ms).
[13:43:49.580] <TB3> INFO: 1540510 events read in total (63072ms).
[13:44:20.759] <TB3> INFO: 2300455 events read in total (94251ms).
[13:44:52.359] <TB3> INFO: 3055825 events read in total (125851ms).
[13:45:24.356] <TB3> INFO: 3807290 events read in total (157848ms).
[13:45:39.366] <TB3> INFO: 4160000 events read in total (172858ms).
[13:45:39.416] <TB3> INFO: Test took 173730ms.
[13:46:07.114] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 221 (-1/-1) hits flags = 528 (plus default)
[13:46:07.124] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:46:07.124] <TB3> INFO: run 1 of 1
[13:46:07.354] <TB3> INFO: Expecting 4617600 events.
[13:46:38.509] <TB3> INFO: 719765 events read in total (30563ms).
[13:47:09.201] <TB3> INFO: 1434225 events read in total (61255ms).
[13:47:40.103] <TB3> INFO: 2145635 events read in total (92157ms).
[13:48:10.340] <TB3> INFO: 2853840 events read in total (122394ms).
[13:48:40.844] <TB3> INFO: 3559290 events read in total (152898ms).
[13:49:11.101] <TB3> INFO: 4263405 events read in total (183155ms).
[13:49:26.695] <TB3> INFO: 4617600 events read in total (198749ms).
[13:49:26.754] <TB3> INFO: Test took 199631ms.
[13:49:56.779] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[13:49:56.791] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:49:56.791] <TB3> INFO: run 1 of 1
[13:49:57.024] <TB3> INFO: Expecting 4264000 events.
[13:50:28.802] <TB3> INFO: 741550 events read in total (31186ms).
[13:51:00.051] <TB3> INFO: 1476870 events read in total (62435ms).
[13:51:31.278] <TB3> INFO: 2208640 events read in total (93662ms).
[13:52:01.909] <TB3> INFO: 2935385 events read in total (124293ms).
[13:52:32.542] <TB3> INFO: 3659585 events read in total (154926ms).
[13:52:58.659] <TB3> INFO: 4264000 events read in total (181043ms).
[13:52:58.714] <TB3> INFO: Test took 181923ms.
[13:53:29.341] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[13:53:29.349] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:53:29.349] <TB3> INFO: run 1 of 1
[13:53:29.583] <TB3> INFO: Expecting 4284800 events.
[13:54:01.388] <TB3> INFO: 740135 events read in total (31214ms).
[13:54:32.862] <TB3> INFO: 1474275 events read in total (62688ms).
[13:55:03.860] <TB3> INFO: 2204930 events read in total (93686ms).
[13:55:34.854] <TB3> INFO: 2930825 events read in total (124680ms).
[13:56:05.776] <TB3> INFO: 3653955 events read in total (155602ms).
[13:56:32.839] <TB3> INFO: 4284800 events read in total (182665ms).
[13:56:32.905] <TB3> INFO: Test took 183556ms.
[13:57:01.650] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[13:57:01.663] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:57:01.663] <TB3> INFO: run 1 of 1
[13:57:01.934] <TB3> INFO: Expecting 4243200 events.
[13:57:33.830] <TB3> INFO: 743380 events read in total (31304ms).
[13:58:04.884] <TB3> INFO: 1480195 events read in total (62358ms).
[13:58:36.198] <TB3> INFO: 2213660 events read in total (93672ms).
[13:59:07.492] <TB3> INFO: 2942115 events read in total (124966ms).
[13:59:39.177] <TB3> INFO: 3667925 events read in total (156651ms).
[14:00:04.784] <TB3> INFO: 4243200 events read in total (182258ms).
[14:00:04.843] <TB3> INFO: Test took 183180ms.
[14:00:29.001] <TB3> INFO: PixTestTrim80::trimBitTest() done
[14:00:29.002] <TB3> INFO: PixTestTrim80::doTest() done, duration: 2455 seconds
[14:00:30.689] <TB3> INFO: enter test to run
[14:00:30.689] <TB3> INFO: test: exit no parameter change
[14:00:30.785] <TB3> QUIET: Connection to board 170 closed.
[14:00:30.786] <TB3> INFO: pXar: this is the end, my friend