[10:14:16.591] <TB2> INFO: *** Welcome to pxar ***
[10:14:16.591] <TB2> INFO: *** Today: 2016/11/03
[10:14:16.597] <TB2> INFO: *** Version: c8ba-dirty
[10:14:16.597] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C15.dat
[10:14:16.597] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//tbmParameters_C1b.dat
[10:14:16.597] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//defaultMaskFile.dat
[10:14:16.597] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters_C15.dat
[10:14:16.652] <TB2> INFO: clk: 4
[10:14:16.652] <TB2> INFO: ctr: 4
[10:14:16.652] <TB2> INFO: sda: 19
[10:14:16.652] <TB2> INFO: tin: 9
[10:14:16.652] <TB2> INFO: level: 15
[10:14:16.652] <TB2> INFO: triggerdelay: 0
[10:14:16.652] <TB2> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[10:14:16.652] <TB2> INFO: Log level: INFO
[10:14:16.661] <TB2> INFO: Found DTB DTB_WXC55Z
[10:14:16.672] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[10:14:16.674] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[10:14:16.676] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[10:14:18.216] <TB2> INFO: DUT info:
[10:14:18.216] <TB2> INFO: The DUT currently contains the following objects:
[10:14:18.216] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[10:14:18.216] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:14:18.216] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:14:18.216] <TB2> INFO: TBM Core alpha (2): 7 registers set
[10:14:18.216] <TB2> INFO: TBM Core beta (3): 7 registers set
[10:14:18.216] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[10:14:18.216] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.216] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.216] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.216] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.216] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.216] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.216] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.216] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.216] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.216] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.217] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.217] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.217] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.217] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.217] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.217] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:18.617] <TB2> INFO: enter 'restricted' command line mode
[10:14:18.617] <TB2> INFO: enter test to run
[10:14:18.617] <TB2> INFO: test: pretest no parameter change
[10:14:18.617] <TB2> INFO: running: pretest
[10:14:19.184] <TB2> INFO: ######################################################################
[10:14:19.184] <TB2> INFO: PixTestPretest::doTest()
[10:14:19.184] <TB2> INFO: ######################################################################
[10:14:19.185] <TB2> INFO: ----------------------------------------------------------------------
[10:14:19.185] <TB2> INFO: PixTestPretest::programROC()
[10:14:19.185] <TB2> INFO: ----------------------------------------------------------------------
[10:14:37.198] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[10:14:37.198] <TB2> INFO: IA differences per ROC: 17.7 19.3 16.9 16.9 19.3 17.7 19.3 19.3 16.1 20.1 17.7 18.5 15.3 19.3 19.3 17.7
[10:14:37.235] <TB2> INFO: ----------------------------------------------------------------------
[10:14:37.235] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[10:14:37.235] <TB2> INFO: ----------------------------------------------------------------------
[10:14:45.120] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 392.3 mA = 24.5187 mA/ROC
[10:14:45.120] <TB2> INFO: i(loss) [mA/ROC]: 20.9 20.9 20.9 20.9 20.9 20.1 20.9 20.9 20.9 20.9 20.9 20.9 20.1 20.1 20.9 20.9
[10:14:45.148] <TB2> INFO: ----------------------------------------------------------------------
[10:14:45.148] <TB2> INFO: PixTestPretest::findTiming()
[10:14:45.149] <TB2> INFO: ----------------------------------------------------------------------
[10:14:45.149] <TB2> INFO: PixTestCmd::init()

[10:15:16.518] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[10:15:16.518] <TB2> INFO: (success/tries = 100/100), width = 4
[10:15:18.016] <TB2> INFO: ----------------------------------------------------------------------
[10:15:18.016] <TB2> INFO: PixTestPretest::findWorkingPixel()
[10:15:18.016] <TB2> INFO: ----------------------------------------------------------------------
[10:15:18.107] <TB2> INFO: Expecting 231680 events.
[10:15:27.781] <TB2> INFO: 231680 events read in total (9082ms).
[10:15:27.787] <TB2> INFO: Test took 9769ms.
[10:15:28.032] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[10:15:28.062] <TB2> INFO: ----------------------------------------------------------------------
[10:15:28.062] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[10:15:28.062] <TB2> INFO: ----------------------------------------------------------------------
[10:15:28.154] <TB2> INFO: Expecting 231680 events.
[10:15:37.790] <TB2> INFO: 231680 events read in total (9045ms).
[10:15:37.798] <TB2> INFO: Test took 9733ms.
[10:15:38.055] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[10:15:38.055] <TB2> INFO: CalDel: 101 83 94 95 97 103 101 80 94 108 109 114 95 99 99 111
[10:15:38.055] <TB2> INFO: VthrComp: 51 55 51 51 51 51 51 51 51 51 51 54 51 51 51 52
[10:15:38.058] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C0.dat
[10:15:38.058] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C1.dat
[10:15:38.058] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C2.dat
[10:15:38.058] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C3.dat
[10:15:38.058] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C4.dat
[10:15:38.058] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C5.dat
[10:15:38.059] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C6.dat
[10:15:38.059] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C7.dat
[10:15:38.059] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C8.dat
[10:15:38.059] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C9.dat
[10:15:38.059] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C10.dat
[10:15:38.059] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C11.dat
[10:15:38.059] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C12.dat
[10:15:38.059] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C13.dat
[10:15:38.059] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C14.dat
[10:15:38.060] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C15.dat
[10:15:38.060] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//tbmParameters_C0a.dat
[10:15:38.060] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//tbmParameters_C0b.dat
[10:15:38.060] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//tbmParameters_C1a.dat
[10:15:38.060] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//tbmParameters_C1b.dat
[10:15:38.060] <TB2> INFO: PixTestPretest::doTest() done, duration: 79 seconds
[10:15:38.156] <TB2> INFO: enter test to run
[10:15:38.156] <TB2> INFO: test: FullTest no parameter change
[10:15:38.156] <TB2> INFO: running: fulltest
[10:15:38.156] <TB2> INFO: ######################################################################
[10:15:38.156] <TB2> INFO: PixTestFullTest::doTest()
[10:15:38.156] <TB2> INFO: ######################################################################
[10:15:38.158] <TB2> INFO: ######################################################################
[10:15:38.158] <TB2> INFO: PixTestAlive::doTest()
[10:15:38.158] <TB2> INFO: ######################################################################
[10:15:38.159] <TB2> INFO: ----------------------------------------------------------------------
[10:15:38.159] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:15:38.159] <TB2> INFO: ----------------------------------------------------------------------
[10:15:38.394] <TB2> INFO: Expecting 41600 events.
[10:15:41.922] <TB2> INFO: 41600 events read in total (2936ms).
[10:15:41.922] <TB2> INFO: Test took 3762ms.
[10:15:42.148] <TB2> INFO: PixTestAlive::aliveTest() done
[10:15:42.148] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:15:42.149] <TB2> INFO: ----------------------------------------------------------------------
[10:15:42.149] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:15:42.149] <TB2> INFO: ----------------------------------------------------------------------
[10:15:42.382] <TB2> INFO: Expecting 41600 events.
[10:15:45.309] <TB2> INFO: 41600 events read in total (2335ms).
[10:15:45.309] <TB2> INFO: Test took 3158ms.
[10:15:45.310] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[10:15:45.546] <TB2> INFO: PixTestAlive::maskTest() done
[10:15:45.546] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:15:45.547] <TB2> INFO: ----------------------------------------------------------------------
[10:15:45.547] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:15:45.547] <TB2> INFO: ----------------------------------------------------------------------
[10:15:45.780] <TB2> INFO: Expecting 41600 events.
[10:15:49.238] <TB2> INFO: 41600 events read in total (2866ms).
[10:15:49.239] <TB2> INFO: Test took 3690ms.
[10:15:49.465] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[10:15:49.465] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:15:49.465] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[10:15:49.465] <TB2> INFO: Decoding statistics:
[10:15:49.465] <TB2> INFO: General information:
[10:15:49.465] <TB2> INFO: 16bit words read: 0
[10:15:49.465] <TB2> INFO: valid events total: 0
[10:15:49.465] <TB2> INFO: empty events: 0
[10:15:49.465] <TB2> INFO: valid events with pixels: 0
[10:15:49.465] <TB2> INFO: valid pixel hits: 0
[10:15:49.465] <TB2> INFO: Event errors: 0
[10:15:49.465] <TB2> INFO: start marker: 0
[10:15:49.465] <TB2> INFO: stop marker: 0
[10:15:49.465] <TB2> INFO: overflow: 0
[10:15:49.465] <TB2> INFO: invalid 5bit words: 0
[10:15:49.465] <TB2> INFO: invalid XOR eye diagram: 0
[10:15:49.465] <TB2> INFO: frame (failed synchr.): 0
[10:15:49.466] <TB2> INFO: idle data (no TBM trl): 0
[10:15:49.466] <TB2> INFO: no data (only TBM hdr): 0
[10:15:49.466] <TB2> INFO: TBM errors: 0
[10:15:49.466] <TB2> INFO: flawed TBM headers: 0
[10:15:49.466] <TB2> INFO: flawed TBM trailers: 0
[10:15:49.466] <TB2> INFO: event ID mismatches: 0
[10:15:49.466] <TB2> INFO: ROC errors: 0
[10:15:49.466] <TB2> INFO: missing ROC header(s): 0
[10:15:49.466] <TB2> INFO: misplaced readback start: 0
[10:15:49.466] <TB2> INFO: Pixel decoding errors: 0
[10:15:49.466] <TB2> INFO: pixel data incomplete: 0
[10:15:49.466] <TB2> INFO: pixel address: 0
[10:15:49.466] <TB2> INFO: pulse height fill bit: 0
[10:15:49.466] <TB2> INFO: buffer corruption: 0
[10:15:49.472] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C15.dat
[10:15:49.473] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[10:15:49.473] <TB2> INFO: ######################################################################
[10:15:49.473] <TB2> INFO: PixTestReadback::doTest()
[10:15:49.473] <TB2> INFO: ######################################################################
[10:15:49.473] <TB2> INFO: ----------------------------------------------------------------------
[10:15:49.473] <TB2> INFO: PixTestReadback::CalibrateVd()
[10:15:49.473] <TB2> INFO: ----------------------------------------------------------------------
[10:15:59.432] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C0.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C1.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C2.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C3.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C4.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C5.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C6.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C7.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C8.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C9.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C10.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C11.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C12.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C13.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C14.dat
[10:15:59.433] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C15.dat
[10:15:59.462] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:15:59.462] <TB2> INFO: ----------------------------------------------------------------------
[10:15:59.462] <TB2> INFO: PixTestReadback::CalibrateVa()
[10:15:59.462] <TB2> INFO: ----------------------------------------------------------------------
[10:16:09.355] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C0.dat
[10:16:09.355] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C1.dat
[10:16:09.355] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C2.dat
[10:16:09.355] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C3.dat
[10:16:09.355] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C4.dat
[10:16:09.355] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C5.dat
[10:16:09.355] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C6.dat
[10:16:09.355] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C7.dat
[10:16:09.355] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C8.dat
[10:16:09.355] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C9.dat
[10:16:09.356] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C10.dat
[10:16:09.356] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C11.dat
[10:16:09.356] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C12.dat
[10:16:09.356] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C13.dat
[10:16:09.356] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C14.dat
[10:16:09.356] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C15.dat
[10:16:09.383] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:16:09.383] <TB2> INFO: ----------------------------------------------------------------------
[10:16:09.383] <TB2> INFO: PixTestReadback::readbackVbg()
[10:16:09.383] <TB2> INFO: ----------------------------------------------------------------------
[10:16:17.021] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:16:17.021] <TB2> INFO: ----------------------------------------------------------------------
[10:16:17.021] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[10:16:17.021] <TB2> INFO: ----------------------------------------------------------------------
[10:16:17.021] <TB2> INFO: Vbg will be calibrated using Vd calibration
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 156.5calibrated Vbg = 1.15365 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 153.8calibrated Vbg = 1.15893 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 155.6calibrated Vbg = 1.15194 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 152.9calibrated Vbg = 1.14836 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 154calibrated Vbg = 1.15246 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 155.7calibrated Vbg = 1.15676 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 156.6calibrated Vbg = 1.15842 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 163.5calibrated Vbg = 1.15717 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 158.2calibrated Vbg = 1.15596 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154.6calibrated Vbg = 1.15575 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 154.5calibrated Vbg = 1.14794 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 158.1calibrated Vbg = 1.14425 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 146.8calibrated Vbg = 1.15174 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 151.6calibrated Vbg = 1.16062 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 159.6calibrated Vbg = 1.159 :::*/*/*/*/
[10:16:17.021] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 160.7calibrated Vbg = 1.15966 :::*/*/*/*/
[10:16:17.023] <TB2> INFO: ----------------------------------------------------------------------
[10:16:17.023] <TB2> INFO: PixTestReadback::CalibrateIa()
[10:16:17.023] <TB2> INFO: ----------------------------------------------------------------------
[10:18:57.329] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C0.dat
[10:18:57.329] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C1.dat
[10:18:57.329] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C2.dat
[10:18:57.329] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C3.dat
[10:18:57.330] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C4.dat
[10:18:57.330] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C5.dat
[10:18:57.330] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C6.dat
[10:18:57.330] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C7.dat
[10:18:57.330] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C8.dat
[10:18:57.330] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C9.dat
[10:18:57.330] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C10.dat
[10:18:57.330] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C11.dat
[10:18:57.330] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C12.dat
[10:18:57.330] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C13.dat
[10:18:57.330] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C14.dat
[10:18:57.330] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C15.dat
[10:18:57.357] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:18:57.358] <TB2> INFO: PixTestReadback::doTest() done
[10:18:57.358] <TB2> INFO: Decoding statistics:
[10:18:57.358] <TB2> INFO: General information:
[10:18:57.358] <TB2> INFO: 16bit words read: 1536
[10:18:57.358] <TB2> INFO: valid events total: 256
[10:18:57.358] <TB2> INFO: empty events: 256
[10:18:57.358] <TB2> INFO: valid events with pixels: 0
[10:18:57.358] <TB2> INFO: valid pixel hits: 0
[10:18:57.358] <TB2> INFO: Event errors: 0
[10:18:57.358] <TB2> INFO: start marker: 0
[10:18:57.358] <TB2> INFO: stop marker: 0
[10:18:57.358] <TB2> INFO: overflow: 0
[10:18:57.358] <TB2> INFO: invalid 5bit words: 0
[10:18:57.358] <TB2> INFO: invalid XOR eye diagram: 0
[10:18:57.358] <TB2> INFO: frame (failed synchr.): 0
[10:18:57.358] <TB2> INFO: idle data (no TBM trl): 0
[10:18:57.358] <TB2> INFO: no data (only TBM hdr): 0
[10:18:57.358] <TB2> INFO: TBM errors: 0
[10:18:57.358] <TB2> INFO: flawed TBM headers: 0
[10:18:57.358] <TB2> INFO: flawed TBM trailers: 0
[10:18:57.358] <TB2> INFO: event ID mismatches: 0
[10:18:57.358] <TB2> INFO: ROC errors: 0
[10:18:57.358] <TB2> INFO: missing ROC header(s): 0
[10:18:57.358] <TB2> INFO: misplaced readback start: 0
[10:18:57.359] <TB2> INFO: Pixel decoding errors: 0
[10:18:57.359] <TB2> INFO: pixel data incomplete: 0
[10:18:57.359] <TB2> INFO: pixel address: 0
[10:18:57.359] <TB2> INFO: pulse height fill bit: 0
[10:18:57.359] <TB2> INFO: buffer corruption: 0
[10:18:57.392] <TB2> INFO: ######################################################################
[10:18:57.392] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[10:18:57.392] <TB2> INFO: ######################################################################
[10:18:57.394] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[10:18:57.406] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[10:18:57.406] <TB2> INFO: run 1 of 1
[10:18:57.638] <TB2> INFO: Expecting 3120000 events.
[10:19:27.778] <TB2> INFO: 672995 events read in total (29549ms).











[10:19:57.553] <TB2> INFO: 1341890 events read in total (59324ms).











[10:20:27.444] <TB2> INFO: 2008735 events read in total (89215ms).











[10:20:57.386] <TB2> INFO: 2675785 events read in total (119157ms).
[10:21:17.626] <TB2> INFO: 3120000 events read in total (139397ms).
[10:21:17.697] <TB2> INFO: Test took 140292ms.
[10:21:43.011] <TB2> INFO: PixTestBBMap::doTest() done, duration: 165 seconds
[10:21:43.011] <TB2> INFO: number of dead bumps (per ROC): 2 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0
[10:21:43.011] <TB2> INFO: separation cut (per ROC): 110 119 112 106 106 105 107 108 101 105 107 130 89 105 104 113
[10:21:43.011] <TB2> INFO: Decoding statistics:
[10:21:43.011] <TB2> INFO: General information:
[10:21:43.011] <TB2> INFO: 16bit words read: 0
[10:21:43.011] <TB2> INFO: valid events total: 0
[10:21:43.011] <TB2> INFO: empty events: 0
[10:21:43.011] <TB2> INFO: valid events with pixels: 0
[10:21:43.011] <TB2> INFO: valid pixel hits: 0
[10:21:43.011] <TB2> INFO: Event errors: 0
[10:21:43.011] <TB2> INFO: start marker: 0
[10:21:43.011] <TB2> INFO: stop marker: 0
[10:21:43.011] <TB2> INFO: overflow: 0
[10:21:43.011] <TB2> INFO: invalid 5bit words: 0
[10:21:43.011] <TB2> INFO: invalid XOR eye diagram: 0
[10:21:43.011] <TB2> INFO: frame (failed synchr.): 0
[10:21:43.011] <TB2> INFO: idle data (no TBM trl): 0
[10:21:43.011] <TB2> INFO: no data (only TBM hdr): 0
[10:21:43.011] <TB2> INFO: TBM errors: 0
[10:21:43.011] <TB2> INFO: flawed TBM headers: 0
[10:21:43.011] <TB2> INFO: flawed TBM trailers: 0
[10:21:43.011] <TB2> INFO: event ID mismatches: 0
[10:21:43.011] <TB2> INFO: ROC errors: 0
[10:21:43.011] <TB2> INFO: missing ROC header(s): 0
[10:21:43.011] <TB2> INFO: misplaced readback start: 0
[10:21:43.011] <TB2> INFO: Pixel decoding errors: 0
[10:21:43.011] <TB2> INFO: pixel data incomplete: 0
[10:21:43.011] <TB2> INFO: pixel address: 0
[10:21:43.011] <TB2> INFO: pulse height fill bit: 0
[10:21:43.011] <TB2> INFO: buffer corruption: 0
[10:21:43.047] <TB2> INFO: ######################################################################
[10:21:43.047] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:21:43.047] <TB2> INFO: ######################################################################
[10:21:43.047] <TB2> INFO: ----------------------------------------------------------------------
[10:21:43.047] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:21:43.047] <TB2> INFO: ----------------------------------------------------------------------
[10:21:43.047] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[10:21:43.059] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[10:21:43.059] <TB2> INFO: run 1 of 1
[10:21:43.305] <TB2> INFO: Expecting 36608000 events.
[10:22:06.752] <TB2> INFO: 670650 events read in total (22855ms).
[10:22:28.001] <TB2> INFO: 1328600 events read in total (45104ms).
[10:22:51.297] <TB2> INFO: 1988650 events read in total (67400ms).
[10:23:13.783] <TB2> INFO: 2646000 events read in total (89886ms).
[10:23:35.000] <TB2> INFO: 3300600 events read in total (112103ms).
[10:23:57.983] <TB2> INFO: 3957250 events read in total (134086ms).
[10:24:20.167] <TB2> INFO: 4613000 events read in total (156270ms).
[10:24:42.592] <TB2> INFO: 5269700 events read in total (178695ms).
[10:25:04.902] <TB2> INFO: 5926150 events read in total (201005ms).
[10:25:27.394] <TB2> INFO: 6581350 events read in total (223497ms).
[10:25:49.550] <TB2> INFO: 7236550 events read in total (245653ms).
[10:26:11.875] <TB2> INFO: 7891100 events read in total (267978ms).
[10:26:34.199] <TB2> INFO: 8544450 events read in total (290302ms).
[10:26:56.213] <TB2> INFO: 9200900 events read in total (312316ms).
[10:27:18.609] <TB2> INFO: 9854500 events read in total (334712ms).
[10:27:40.812] <TB2> INFO: 10509650 events read in total (356915ms).
[10:28:03.011] <TB2> INFO: 11162950 events read in total (379114ms).
[10:28:25.090] <TB2> INFO: 11815650 events read in total (401193ms).
[10:28:47.041] <TB2> INFO: 12468600 events read in total (423144ms).
[10:29:09.168] <TB2> INFO: 13122800 events read in total (445271ms).
[10:29:31.290] <TB2> INFO: 13776550 events read in total (467393ms).
[10:29:53.410] <TB2> INFO: 14429750 events read in total (489513ms).
[10:30:15.644] <TB2> INFO: 15082950 events read in total (511747ms).
[10:30:37.721] <TB2> INFO: 15736550 events read in total (533824ms).
[10:30:59.688] <TB2> INFO: 16389250 events read in total (555791ms).
[10:31:21.717] <TB2> INFO: 17041850 events read in total (577820ms).
[10:31:44.131] <TB2> INFO: 17694050 events read in total (600234ms).
[10:32:06.033] <TB2> INFO: 18344300 events read in total (622136ms).
[10:32:28.136] <TB2> INFO: 18993450 events read in total (644239ms).
[10:32:50.366] <TB2> INFO: 19640350 events read in total (666469ms).
[10:33:12.496] <TB2> INFO: 20289900 events read in total (688599ms).
[10:33:34.624] <TB2> INFO: 20937150 events read in total (710727ms).
[10:33:56.907] <TB2> INFO: 21585750 events read in total (733010ms).
[10:34:18.958] <TB2> INFO: 22235050 events read in total (755061ms).
[10:34:41.026] <TB2> INFO: 22885350 events read in total (777129ms).
[10:35:03.219] <TB2> INFO: 23534250 events read in total (799322ms).
[10:35:25.392] <TB2> INFO: 24182600 events read in total (821495ms).
[10:35:47.319] <TB2> INFO: 24832050 events read in total (843422ms).
[10:36:09.692] <TB2> INFO: 25479950 events read in total (865795ms).
[10:36:31.817] <TB2> INFO: 26128700 events read in total (887920ms).
[10:36:53.977] <TB2> INFO: 26776300 events read in total (910080ms).
[10:37:15.962] <TB2> INFO: 27424250 events read in total (932065ms).
[10:37:37.841] <TB2> INFO: 28070650 events read in total (953944ms).
[10:37:59.986] <TB2> INFO: 28719350 events read in total (976089ms).
[10:38:22.139] <TB2> INFO: 29364650 events read in total (998242ms).
[10:38:44.543] <TB2> INFO: 30012850 events read in total (1020646ms).
[10:39:06.617] <TB2> INFO: 30659600 events read in total (1042720ms).
[10:39:28.745] <TB2> INFO: 31307800 events read in total (1064848ms).
[10:39:50.922] <TB2> INFO: 31956550 events read in total (1087025ms).
[10:40:12.854] <TB2> INFO: 32603650 events read in total (1108957ms).
[10:40:34.777] <TB2> INFO: 33253200 events read in total (1130880ms).
[10:40:56.907] <TB2> INFO: 33902400 events read in total (1153010ms).
[10:41:19.179] <TB2> INFO: 34551300 events read in total (1175282ms).
[10:41:41.049] <TB2> INFO: 35198400 events read in total (1197152ms).
[10:42:03.123] <TB2> INFO: 35849050 events read in total (1219226ms).
[10:42:25.206] <TB2> INFO: 36508200 events read in total (1241310ms).
[10:42:28.887] <TB2> INFO: 36608000 events read in total (1244990ms).
[10:42:28.951] <TB2> INFO: Test took 1245893ms.
[10:42:29.357] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:31.010] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:32.594] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:34.173] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:35.976] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:37.958] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:39.902] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:41.886] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:43.763] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:45.768] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:47.742] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:49.753] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:51.715] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:53.549] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:55.648] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:57.627] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:42:59.384] <TB2> INFO: PixTestScurves::scurves() done
[10:42:59.384] <TB2> INFO: Vcal mean: 116.17 135.17 119.06 110.80 110.76 117.77 113.92 117.65 114.18 121.77 108.94 129.74 96.32 114.58 112.37 125.08
[10:42:59.384] <TB2> INFO: Vcal RMS: 5.86 6.15 5.86 5.35 4.64 5.68 5.17 5.65 4.87 6.72 5.52 6.28 5.39 5.12 5.02 6.14
[10:42:59.385] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1276 seconds
[10:42:59.385] <TB2> INFO: Decoding statistics:
[10:42:59.385] <TB2> INFO: General information:
[10:42:59.385] <TB2> INFO: 16bit words read: 0
[10:42:59.385] <TB2> INFO: valid events total: 0
[10:42:59.385] <TB2> INFO: empty events: 0
[10:42:59.385] <TB2> INFO: valid events with pixels: 0
[10:42:59.385] <TB2> INFO: valid pixel hits: 0
[10:42:59.385] <TB2> INFO: Event errors: 0
[10:42:59.385] <TB2> INFO: start marker: 0
[10:42:59.385] <TB2> INFO: stop marker: 0
[10:42:59.385] <TB2> INFO: overflow: 0
[10:42:59.385] <TB2> INFO: invalid 5bit words: 0
[10:42:59.385] <TB2> INFO: invalid XOR eye diagram: 0
[10:42:59.385] <TB2> INFO: frame (failed synchr.): 0
[10:42:59.385] <TB2> INFO: idle data (no TBM trl): 0
[10:42:59.385] <TB2> INFO: no data (only TBM hdr): 0
[10:42:59.385] <TB2> INFO: TBM errors: 0
[10:42:59.385] <TB2> INFO: flawed TBM headers: 0
[10:42:59.385] <TB2> INFO: flawed TBM trailers: 0
[10:42:59.385] <TB2> INFO: event ID mismatches: 0
[10:42:59.385] <TB2> INFO: ROC errors: 0
[10:42:59.385] <TB2> INFO: missing ROC header(s): 0
[10:42:59.385] <TB2> INFO: misplaced readback start: 0
[10:42:59.385] <TB2> INFO: Pixel decoding errors: 0
[10:42:59.385] <TB2> INFO: pixel data incomplete: 0
[10:42:59.385] <TB2> INFO: pixel address: 0
[10:42:59.385] <TB2> INFO: pulse height fill bit: 0
[10:42:59.385] <TB2> INFO: buffer corruption: 0
[10:42:59.478] <TB2> INFO: ######################################################################
[10:42:59.478] <TB2> INFO: PixTestTrim::doTest()
[10:42:59.478] <TB2> INFO: ######################################################################
[10:42:59.479] <TB2> INFO: ----------------------------------------------------------------------
[10:42:59.479] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[10:42:59.480] <TB2> INFO: ----------------------------------------------------------------------
[10:42:59.524] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[10:42:59.524] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:42:59.534] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:42:59.534] <TB2> INFO: run 1 of 1
[10:42:59.817] <TB2> INFO: Expecting 5025280 events.
[10:43:29.866] <TB2> INFO: 824864 events read in total (29455ms).
[10:43:59.453] <TB2> INFO: 1646712 events read in total (59042ms).
[10:44:29.004] <TB2> INFO: 2466840 events read in total (88594ms).
[10:44:58.452] <TB2> INFO: 3284160 events read in total (118041ms).
[10:45:27.630] <TB2> INFO: 4098720 events read in total (147220ms).
[10:45:57.165] <TB2> INFO: 4912288 events read in total (176754ms).
[10:46:01.592] <TB2> INFO: 5025280 events read in total (181181ms).
[10:46:01.651] <TB2> INFO: Test took 182117ms.
[10:46:20.966] <TB2> INFO: ROC 0 VthrComp = 123
[10:46:20.966] <TB2> INFO: ROC 1 VthrComp = 133
[10:46:20.966] <TB2> INFO: ROC 2 VthrComp = 130
[10:46:20.966] <TB2> INFO: ROC 3 VthrComp = 117
[10:46:20.967] <TB2> INFO: ROC 4 VthrComp = 117
[10:46:20.967] <TB2> INFO: ROC 5 VthrComp = 124
[10:46:20.967] <TB2> INFO: ROC 6 VthrComp = 120
[10:46:20.967] <TB2> INFO: ROC 7 VthrComp = 130
[10:46:20.968] <TB2> INFO: ROC 8 VthrComp = 116
[10:46:20.969] <TB2> INFO: ROC 9 VthrComp = 126
[10:46:20.969] <TB2> INFO: ROC 10 VthrComp = 117
[10:46:20.969] <TB2> INFO: ROC 11 VthrComp = 133
[10:46:20.969] <TB2> INFO: ROC 12 VthrComp = 99
[10:46:20.969] <TB2> INFO: ROC 13 VthrComp = 125
[10:46:20.970] <TB2> INFO: ROC 14 VthrComp = 116
[10:46:20.970] <TB2> INFO: ROC 15 VthrComp = 129
[10:46:21.233] <TB2> INFO: Expecting 41600 events.
[10:46:24.815] <TB2> INFO: 41600 events read in total (2991ms).
[10:46:24.816] <TB2> INFO: Test took 3845ms.
[10:46:24.827] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[10:46:24.827] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:46:24.838] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:46:24.838] <TB2> INFO: run 1 of 1
[10:46:25.116] <TB2> INFO: Expecting 5025280 events.
[10:46:50.914] <TB2> INFO: 589824 events read in total (25206ms).
[10:47:15.995] <TB2> INFO: 1178752 events read in total (50287ms).
[10:47:41.423] <TB2> INFO: 1767776 events read in total (75715ms).
[10:48:06.961] <TB2> INFO: 2356080 events read in total (101253ms).
[10:48:32.243] <TB2> INFO: 2942240 events read in total (126535ms).
[10:48:57.138] <TB2> INFO: 3527040 events read in total (151430ms).
[10:49:22.055] <TB2> INFO: 4110808 events read in total (176347ms).
[10:49:47.319] <TB2> INFO: 4695264 events read in total (201611ms).
[10:50:01.906] <TB2> INFO: 5025280 events read in total (216198ms).
[10:50:01.967] <TB2> INFO: Test took 217128ms.
[10:50:29.780] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 60.4955 for pixel 13/50 mean/min/max = 45.7046/30.7995/60.6098
[10:50:29.780] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 70.8476 for pixel 16/0 mean/min/max = 54.4297/37.4497/71.4097
[10:50:29.781] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 57.6196 for pixel 40/0 mean/min/max = 44.9347/32.0648/57.8046
[10:50:29.781] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 59.264 for pixel 12/64 mean/min/max = 45.328/31.3757/59.2803
[10:50:29.781] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 58.866 for pixel 12/77 mean/min/max = 45.5325/31.9814/59.0836
[10:50:29.782] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 58.8824 for pixel 51/0 mean/min/max = 45.1355/31.1755/59.0956
[10:50:29.782] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 60.2996 for pixel 22/2 mean/min/max = 46.2277/32.1443/60.3111
[10:50:29.782] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 57.6384 for pixel 14/31 mean/min/max = 44.6605/31.5856/57.7354
[10:50:29.783] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 59.7638 for pixel 17/21 mean/min/max = 46.2154/32.3813/60.0494
[10:50:29.783] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 61.8008 for pixel 0/1 mean/min/max = 46.7712/31.5859/61.9565
[10:50:29.783] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 60.1316 for pixel 12/0 mean/min/max = 45.6483/31.0075/60.2891
[10:50:29.784] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 69.0677 for pixel 8/37 mean/min/max = 53.1497/37.0606/69.2388
[10:50:29.784] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 58.1832 for pixel 0/15 mean/min/max = 45.7014/33.0688/58.334
[10:50:29.785] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 58.0896 for pixel 14/1 mean/min/max = 44.5872/31.0002/58.1742
[10:50:29.785] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 58.8899 for pixel 51/34 mean/min/max = 45.6695/32.306/59.033
[10:50:29.785] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 60.8022 for pixel 24/3 mean/min/max = 46.1332/31.3469/60.9195
[10:50:29.787] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:50:29.875] <TB2> INFO: Expecting 411648 events.
[10:50:39.441] <TB2> INFO: 411648 events read in total (8974ms).
[10:50:39.449] <TB2> INFO: Expecting 411648 events.
[10:50:48.558] <TB2> INFO: 411648 events read in total (8706ms).
[10:50:48.571] <TB2> INFO: Expecting 411648 events.
[10:50:57.671] <TB2> INFO: 411648 events read in total (8697ms).
[10:50:57.683] <TB2> INFO: Expecting 411648 events.
[10:51:06.735] <TB2> INFO: 411648 events read in total (8649ms).
[10:51:06.750] <TB2> INFO: Expecting 411648 events.
[10:51:15.771] <TB2> INFO: 411648 events read in total (8618ms).
[10:51:15.789] <TB2> INFO: Expecting 411648 events.
[10:51:24.785] <TB2> INFO: 411648 events read in total (8593ms).
[10:51:24.811] <TB2> INFO: Expecting 411648 events.
[10:51:33.897] <TB2> INFO: 411648 events read in total (8684ms).
[10:51:33.927] <TB2> INFO: Expecting 411648 events.
[10:51:42.943] <TB2> INFO: 411648 events read in total (8613ms).
[10:51:42.969] <TB2> INFO: Expecting 411648 events.
[10:51:52.040] <TB2> INFO: 411648 events read in total (8668ms).
[10:51:52.067] <TB2> INFO: Expecting 411648 events.
[10:52:01.139] <TB2> INFO: 411648 events read in total (8669ms).
[10:52:01.179] <TB2> INFO: Expecting 411648 events.
[10:52:10.293] <TB2> INFO: 411648 events read in total (8711ms).
[10:52:10.326] <TB2> INFO: Expecting 411648 events.
[10:52:19.474] <TB2> INFO: 411648 events read in total (8745ms).
[10:52:19.522] <TB2> INFO: Expecting 411648 events.
[10:52:28.474] <TB2> INFO: 411648 events read in total (8550ms).
[10:52:28.512] <TB2> INFO: Expecting 411648 events.
[10:52:37.574] <TB2> INFO: 411648 events read in total (8659ms).
[10:52:37.615] <TB2> INFO: Expecting 411648 events.
[10:52:46.639] <TB2> INFO: 411648 events read in total (8621ms).
[10:52:46.684] <TB2> INFO: Expecting 411648 events.
[10:52:55.776] <TB2> INFO: 411648 events read in total (8690ms).
[10:52:55.837] <TB2> INFO: Test took 146050ms.
[10:52:56.627] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[10:52:56.637] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:52:56.637] <TB2> INFO: run 1 of 1
[10:52:56.870] <TB2> INFO: Expecting 5025280 events.
[10:53:22.631] <TB2> INFO: 586576 events read in total (25169ms).
[10:53:47.781] <TB2> INFO: 1170944 events read in total (50319ms).
[10:54:13.219] <TB2> INFO: 1754936 events read in total (75757ms).
[10:54:38.560] <TB2> INFO: 2337984 events read in total (101098ms).
[10:55:04.192] <TB2> INFO: 2925616 events read in total (126730ms).
[10:55:29.638] <TB2> INFO: 3513192 events read in total (152176ms).
[10:55:55.309] <TB2> INFO: 4098776 events read in total (177847ms).
[10:56:20.500] <TB2> INFO: 4682248 events read in total (203038ms).
[10:56:35.752] <TB2> INFO: 5025280 events read in total (218290ms).
[10:56:35.889] <TB2> INFO: Test took 219251ms.
[10:57:00.346] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 1.500000 .. 147.596128
[10:57:00.622] <TB2> INFO: Expecting 208000 events.
[10:57:10.787] <TB2> INFO: 208000 events read in total (9573ms).
[10:57:10.788] <TB2> INFO: Test took 10440ms.
[10:57:10.835] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 157 (-1/-1) hits flags = 528 (plus default)
[10:57:10.845] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:57:10.845] <TB2> INFO: run 1 of 1
[10:57:11.123] <TB2> INFO: Expecting 5224960 events.
[10:57:37.405] <TB2> INFO: 583640 events read in total (25690ms).
[10:58:02.557] <TB2> INFO: 1166792 events read in total (50843ms).
[10:58:28.027] <TB2> INFO: 1750504 events read in total (76312ms).
[10:58:53.494] <TB2> INFO: 2334312 events read in total (101779ms).
[10:59:18.625] <TB2> INFO: 2917592 events read in total (126910ms).
[10:59:43.796] <TB2> INFO: 3500472 events read in total (152081ms).
[11:00:09.200] <TB2> INFO: 4082848 events read in total (177486ms).
[11:00:33.981] <TB2> INFO: 4664648 events read in total (202266ms).
[11:00:58.251] <TB2> INFO: 5224960 events read in total (226536ms).
[11:00:58.352] <TB2> INFO: Test took 227507ms.
[11:01:26.835] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.073750 .. 44.299419
[11:01:27.072] <TB2> INFO: Expecting 208000 events.
[11:01:37.483] <TB2> INFO: 208000 events read in total (9820ms).
[11:01:37.484] <TB2> INFO: Test took 10646ms.
[11:01:37.539] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 54 (-1/-1) hits flags = 528 (plus default)
[11:01:37.551] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:01:37.551] <TB2> INFO: run 1 of 1
[11:01:37.829] <TB2> INFO: Expecting 1264640 events.
[11:02:06.007] <TB2> INFO: 663208 events read in total (27587ms).
[11:02:31.067] <TB2> INFO: 1264640 events read in total (52648ms).
[11:02:31.094] <TB2> INFO: Test took 53543ms.
[11:02:45.136] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 25.558090 .. 47.652155
[11:02:45.410] <TB2> INFO: Expecting 208000 events.
[11:02:55.219] <TB2> INFO: 208000 events read in total (9217ms).
[11:02:55.220] <TB2> INFO: Test took 10082ms.
[11:02:55.287] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 57 (-1/-1) hits flags = 528 (plus default)
[11:02:55.298] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:02:55.298] <TB2> INFO: run 1 of 1
[11:02:55.576] <TB2> INFO: Expecting 1431040 events.
[11:03:23.832] <TB2> INFO: 659728 events read in total (27665ms).
[11:03:51.263] <TB2> INFO: 1318448 events read in total (55096ms).
[11:03:56.245] <TB2> INFO: 1431040 events read in total (60078ms).
[11:03:56.269] <TB2> INFO: Test took 60971ms.
[11:04:10.967] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 24.562793 .. 45.459413
[11:04:11.203] <TB2> INFO: Expecting 208000 events.
[11:04:20.767] <TB2> INFO: 208000 events read in total (8972ms).
[11:04:20.768] <TB2> INFO: Test took 9799ms.
[11:04:20.823] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 55 (-1/-1) hits flags = 528 (plus default)
[11:04:20.834] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:04:20.834] <TB2> INFO: run 1 of 1
[11:04:21.111] <TB2> INFO: Expecting 1397760 events.
[11:04:49.271] <TB2> INFO: 671184 events read in total (27568ms).
[11:05:16.713] <TB2> INFO: 1342016 events read in total (55010ms).
[11:05:19.468] <TB2> INFO: 1397760 events read in total (57765ms).
[11:05:19.491] <TB2> INFO: Test took 58657ms.
[11:05:33.283] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[11:05:33.283] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[11:05:33.294] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:05:33.294] <TB2> INFO: run 1 of 1
[11:05:33.541] <TB2> INFO: Expecting 1364480 events.
[11:06:01.663] <TB2> INFO: 667320 events read in total (27531ms).
[11:06:28.793] <TB2> INFO: 1333912 events read in total (54661ms).
[11:06:30.423] <TB2> INFO: 1364480 events read in total (56291ms).
[11:06:30.445] <TB2> INFO: Test took 57150ms.
[11:06:44.539] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C0.dat
[11:06:44.539] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C1.dat
[11:06:44.539] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C2.dat
[11:06:44.539] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C3.dat
[11:06:44.539] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C4.dat
[11:06:44.539] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C5.dat
[11:06:44.539] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C6.dat
[11:06:44.539] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C7.dat
[11:06:44.540] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C8.dat
[11:06:44.540] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C9.dat
[11:06:44.540] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C10.dat
[11:06:44.540] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C11.dat
[11:06:44.540] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C12.dat
[11:06:44.540] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C13.dat
[11:06:44.540] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C14.dat
[11:06:44.540] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C15.dat
[11:06:44.540] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C0.dat
[11:06:44.546] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C1.dat
[11:06:44.551] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C2.dat
[11:06:44.557] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C3.dat
[11:06:44.563] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C4.dat
[11:06:44.568] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C5.dat
[11:06:44.574] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C6.dat
[11:06:44.579] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C7.dat
[11:06:44.585] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C8.dat
[11:06:44.590] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C9.dat
[11:06:44.596] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C10.dat
[11:06:44.601] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C11.dat
[11:06:44.607] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C12.dat
[11:06:44.612] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C13.dat
[11:06:44.617] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C14.dat
[11:06:44.623] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C15.dat
[11:06:44.628] <TB2> INFO: PixTestTrim::trimTest() done
[11:06:44.628] <TB2> INFO: vtrim: 134 187 138 138 140 117 159 132 142 144 172 188 107 126 139 146
[11:06:44.628] <TB2> INFO: vthrcomp: 123 133 130 117 117 124 120 130 116 126 117 133 99 125 116 129
[11:06:44.628] <TB2> INFO: vcal mean: 34.93 35.40 34.94 34.94 34.98 34.93 34.95 34.94 34.99 34.94 34.98 35.04 34.99 34.91 34.89 34.91
[11:06:44.628] <TB2> INFO: vcal RMS: 1.10 1.64 1.03 1.04 0.99 1.11 1.17 1.09 1.10 1.18 1.16 1.20 0.92 1.09 0.98 1.12
[11:06:44.628] <TB2> INFO: bits mean: 10.16 8.39 9.95 10.13 9.89 10.00 10.53 9.92 9.90 9.34 10.87 8.41 9.12 10.22 9.72 9.72
[11:06:44.628] <TB2> INFO: bits RMS: 2.52 2.20 2.54 2.48 2.53 2.64 2.18 2.63 2.46 2.77 2.17 2.07 2.77 2.59 2.62 2.70
[11:06:44.635] <TB2> INFO: ----------------------------------------------------------------------
[11:06:44.635] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[11:06:44.635] <TB2> INFO: ----------------------------------------------------------------------
[11:06:44.638] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[11:06:44.649] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:06:44.649] <TB2> INFO: run 1 of 1
[11:06:44.883] <TB2> INFO: Expecting 4160000 events.
[11:07:16.141] <TB2> INFO: 739380 events read in total (30667ms).
[11:07:46.881] <TB2> INFO: 1472335 events read in total (61407ms).
[11:08:17.870] <TB2> INFO: 2201885 events read in total (92396ms).
[11:08:48.581] <TB2> INFO: 2926635 events read in total (123107ms).
[11:09:19.304] <TB2> INFO: 3649660 events read in total (153830ms).
[11:09:41.105] <TB2> INFO: 4160000 events read in total (175631ms).
[11:09:41.157] <TB2> INFO: Test took 176508ms.
[11:10:09.744] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[11:10:09.756] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:10:09.756] <TB2> INFO: run 1 of 1
[11:10:10.065] <TB2> INFO: Expecting 4430400 events.
[11:10:40.612] <TB2> INFO: 700455 events read in total (29955ms).
[11:11:10.427] <TB2> INFO: 1396230 events read in total (59770ms).
[11:11:40.320] <TB2> INFO: 2090410 events read in total (89663ms).
[11:12:10.236] <TB2> INFO: 2780540 events read in total (119579ms).
[11:12:40.359] <TB2> INFO: 3469705 events read in total (149702ms).
[11:13:10.301] <TB2> INFO: 4158580 events read in total (179644ms).
[11:13:22.585] <TB2> INFO: 4430400 events read in total (191928ms).
[11:13:22.711] <TB2> INFO: Test took 192955ms.
[11:13:54.652] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[11:13:54.664] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:13:54.664] <TB2> INFO: run 1 of 1
[11:13:54.985] <TB2> INFO: Expecting 4326400 events.
[11:14:25.608] <TB2> INFO: 705820 events read in total (30031ms).
[11:14:55.836] <TB2> INFO: 1407110 events read in total (60259ms).
[11:15:25.876] <TB2> INFO: 2106675 events read in total (90299ms).
[11:15:55.928] <TB2> INFO: 2801640 events read in total (120351ms).
[11:16:25.910] <TB2> INFO: 3496050 events read in total (150333ms).
[11:16:56.307] <TB2> INFO: 4190180 events read in total (180730ms).
[11:17:02.631] <TB2> INFO: 4326400 events read in total (187054ms).
[11:17:02.695] <TB2> INFO: Test took 188031ms.
[11:17:35.034] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[11:17:35.044] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:17:35.044] <TB2> INFO: run 1 of 1
[11:17:35.315] <TB2> INFO: Expecting 4326400 events.
[11:18:06.073] <TB2> INFO: 705900 events read in total (30167ms).
[11:18:35.818] <TB2> INFO: 1407225 events read in total (59912ms).
[11:19:05.839] <TB2> INFO: 2106830 events read in total (89933ms).
[11:19:35.714] <TB2> INFO: 2801780 events read in total (119808ms).
[11:20:05.728] <TB2> INFO: 3496160 events read in total (149822ms).
[11:20:35.967] <TB2> INFO: 4190605 events read in total (180061ms).
[11:20:42.067] <TB2> INFO: 4326400 events read in total (186161ms).
[11:20:42.125] <TB2> INFO: Test took 187081ms.
[11:21:11.396] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[11:21:11.407] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:21:11.407] <TB2> INFO: run 1 of 1
[11:21:11.639] <TB2> INFO: Expecting 4326400 events.
[11:21:42.934] <TB2> INFO: 706445 events read in total (30703ms).
[11:22:13.206] <TB2> INFO: 1408050 events read in total (60975ms).
[11:22:43.882] <TB2> INFO: 2107940 events read in total (91651ms).
[11:23:14.238] <TB2> INFO: 2803480 events read in total (122007ms).
[11:23:44.531] <TB2> INFO: 3498050 events read in total (152300ms).
[11:24:14.913] <TB2> INFO: 4192555 events read in total (182682ms).
[11:24:20.920] <TB2> INFO: 4326400 events read in total (188689ms).
[11:24:20.978] <TB2> INFO: Test took 189570ms.
[11:24:48.554] <TB2> INFO: PixTestTrim::trimBitTest() done
[11:24:48.555] <TB2> INFO: PixTestTrim::doTest() done, duration: 2509 seconds
[11:24:48.555] <TB2> INFO: Decoding statistics:
[11:24:48.555] <TB2> INFO: General information:
[11:24:48.555] <TB2> INFO: 16bit words read: 0
[11:24:48.555] <TB2> INFO: valid events total: 0
[11:24:48.555] <TB2> INFO: empty events: 0
[11:24:48.555] <TB2> INFO: valid events with pixels: 0
[11:24:48.555] <TB2> INFO: valid pixel hits: 0
[11:24:48.555] <TB2> INFO: Event errors: 0
[11:24:48.555] <TB2> INFO: start marker: 0
[11:24:48.555] <TB2> INFO: stop marker: 0
[11:24:48.555] <TB2> INFO: overflow: 0
[11:24:48.555] <TB2> INFO: invalid 5bit words: 0
[11:24:48.556] <TB2> INFO: invalid XOR eye diagram: 0
[11:24:48.556] <TB2> INFO: frame (failed synchr.): 0
[11:24:48.556] <TB2> INFO: idle data (no TBM trl): 0
[11:24:48.556] <TB2> INFO: no data (only TBM hdr): 0
[11:24:48.556] <TB2> INFO: TBM errors: 0
[11:24:48.556] <TB2> INFO: flawed TBM headers: 0
[11:24:48.556] <TB2> INFO: flawed TBM trailers: 0
[11:24:48.556] <TB2> INFO: event ID mismatches: 0
[11:24:48.556] <TB2> INFO: ROC errors: 0
[11:24:48.556] <TB2> INFO: missing ROC header(s): 0
[11:24:48.556] <TB2> INFO: misplaced readback start: 0
[11:24:48.556] <TB2> INFO: Pixel decoding errors: 0
[11:24:48.556] <TB2> INFO: pixel data incomplete: 0
[11:24:48.556] <TB2> INFO: pixel address: 0
[11:24:48.556] <TB2> INFO: pulse height fill bit: 0
[11:24:48.556] <TB2> INFO: buffer corruption: 0
[11:24:49.294] <TB2> INFO: ######################################################################
[11:24:49.294] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[11:24:49.294] <TB2> INFO: ######################################################################
[11:24:49.527] <TB2> INFO: Expecting 41600 events.
[11:24:53.076] <TB2> INFO: 41600 events read in total (2958ms).
[11:24:53.077] <TB2> INFO: Test took 3782ms.
[11:24:53.511] <TB2> INFO: Expecting 41600 events.
[11:24:57.042] <TB2> INFO: 41600 events read in total (2938ms).
[11:24:57.042] <TB2> INFO: Test took 3763ms.
[11:24:57.330] <TB2> INFO: Expecting 41600 events.
[11:25:00.857] <TB2> INFO: 41600 events read in total (2936ms).
[11:25:00.857] <TB2> INFO: Test took 3792ms.
[11:25:01.145] <TB2> INFO: Expecting 41600 events.
[11:25:04.617] <TB2> INFO: 41600 events read in total (2880ms).
[11:25:04.618] <TB2> INFO: Test took 3737ms.
[11:25:04.908] <TB2> INFO: Expecting 41600 events.
[11:25:08.514] <TB2> INFO: 41600 events read in total (3015ms).
[11:25:08.514] <TB2> INFO: Test took 3871ms.
[11:25:08.802] <TB2> INFO: Expecting 41600 events.
[11:25:12.403] <TB2> INFO: 41600 events read in total (3009ms).
[11:25:12.404] <TB2> INFO: Test took 3866ms.
[11:25:12.701] <TB2> INFO: Expecting 41600 events.
[11:25:16.181] <TB2> INFO: 41600 events read in total (2888ms).
[11:25:16.182] <TB2> INFO: Test took 3755ms.
[11:25:16.472] <TB2> INFO: Expecting 41600 events.
[11:25:20.007] <TB2> INFO: 41600 events read in total (2943ms).
[11:25:20.008] <TB2> INFO: Test took 3800ms.
[11:25:20.299] <TB2> INFO: Expecting 41600 events.
[11:25:23.842] <TB2> INFO: 41600 events read in total (2952ms).
[11:25:23.843] <TB2> INFO: Test took 3809ms.
[11:25:24.133] <TB2> INFO: Expecting 41600 events.
[11:25:27.691] <TB2> INFO: 41600 events read in total (2966ms).
[11:25:27.692] <TB2> INFO: Test took 3824ms.
[11:25:27.982] <TB2> INFO: Expecting 41600 events.
[11:25:31.528] <TB2> INFO: 41600 events read in total (2954ms).
[11:25:31.529] <TB2> INFO: Test took 3811ms.
[11:25:31.819] <TB2> INFO: Expecting 41600 events.
[11:25:35.362] <TB2> INFO: 41600 events read in total (2951ms).
[11:25:35.363] <TB2> INFO: Test took 3808ms.
[11:25:35.653] <TB2> INFO: Expecting 41600 events.
[11:25:39.297] <TB2> INFO: 41600 events read in total (3052ms).
[11:25:39.298] <TB2> INFO: Test took 3909ms.
[11:25:39.586] <TB2> INFO: Expecting 41600 events.
[11:25:43.111] <TB2> INFO: 41600 events read in total (2934ms).
[11:25:43.112] <TB2> INFO: Test took 3791ms.
[11:25:43.400] <TB2> INFO: Expecting 41600 events.
[11:25:46.894] <TB2> INFO: 41600 events read in total (2903ms).
[11:25:46.895] <TB2> INFO: Test took 3760ms.
[11:25:47.193] <TB2> INFO: Expecting 41600 events.
[11:25:50.748] <TB2> INFO: 41600 events read in total (2963ms).
[11:25:50.749] <TB2> INFO: Test took 3831ms.
[11:25:51.048] <TB2> INFO: Expecting 41600 events.
[11:25:54.593] <TB2> INFO: 41600 events read in total (2953ms).
[11:25:54.594] <TB2> INFO: Test took 3822ms.
[11:25:54.885] <TB2> INFO: Expecting 41600 events.
[11:25:58.368] <TB2> INFO: 41600 events read in total (2892ms).
[11:25:58.369] <TB2> INFO: Test took 3749ms.
[11:25:58.657] <TB2> INFO: Expecting 41600 events.
[11:26:02.168] <TB2> INFO: 41600 events read in total (2920ms).
[11:26:02.169] <TB2> INFO: Test took 3777ms.
[11:26:02.461] <TB2> INFO: Expecting 41600 events.
[11:26:05.929] <TB2> INFO: 41600 events read in total (2876ms).
[11:26:05.930] <TB2> INFO: Test took 3733ms.
[11:26:06.218] <TB2> INFO: Expecting 41600 events.
[11:26:09.669] <TB2> INFO: 41600 events read in total (2860ms).
[11:26:09.670] <TB2> INFO: Test took 3717ms.
[11:26:09.958] <TB2> INFO: Expecting 41600 events.
[11:26:13.516] <TB2> INFO: 41600 events read in total (2966ms).
[11:26:13.517] <TB2> INFO: Test took 3824ms.
[11:26:13.808] <TB2> INFO: Expecting 41600 events.
[11:26:17.358] <TB2> INFO: 41600 events read in total (2958ms).
[11:26:17.359] <TB2> INFO: Test took 3816ms.
[11:26:17.647] <TB2> INFO: Expecting 41600 events.
[11:26:21.101] <TB2> INFO: 41600 events read in total (2862ms).
[11:26:21.102] <TB2> INFO: Test took 3720ms.
[11:26:21.390] <TB2> INFO: Expecting 41600 events.
[11:26:24.844] <TB2> INFO: 41600 events read in total (2862ms).
[11:26:24.845] <TB2> INFO: Test took 3720ms.
[11:26:25.133] <TB2> INFO: Expecting 41600 events.
[11:26:28.624] <TB2> INFO: 41600 events read in total (2900ms).
[11:26:28.625] <TB2> INFO: Test took 3757ms.
[11:26:28.913] <TB2> INFO: Expecting 41600 events.
[11:26:32.401] <TB2> INFO: 41600 events read in total (2897ms).
[11:26:32.401] <TB2> INFO: Test took 3753ms.
[11:26:32.692] <TB2> INFO: Expecting 41600 events.
[11:26:36.227] <TB2> INFO: 41600 events read in total (2943ms).
[11:26:36.228] <TB2> INFO: Test took 3800ms.
[11:26:36.517] <TB2> INFO: Expecting 41600 events.
[11:26:39.979] <TB2> INFO: 41600 events read in total (2870ms).
[11:26:39.980] <TB2> INFO: Test took 3727ms.
[11:26:40.272] <TB2> INFO: Expecting 2560 events.
[11:26:41.154] <TB2> INFO: 2560 events read in total (291ms).
[11:26:41.155] <TB2> INFO: Test took 1160ms.
[11:26:41.463] <TB2> INFO: Expecting 2560 events.
[11:26:42.346] <TB2> INFO: 2560 events read in total (292ms).
[11:26:42.346] <TB2> INFO: Test took 1191ms.
[11:26:42.654] <TB2> INFO: Expecting 2560 events.
[11:26:43.536] <TB2> INFO: 2560 events read in total (290ms).
[11:26:43.536] <TB2> INFO: Test took 1190ms.
[11:26:43.845] <TB2> INFO: Expecting 2560 events.
[11:26:44.727] <TB2> INFO: 2560 events read in total (291ms).
[11:26:44.727] <TB2> INFO: Test took 1190ms.
[11:26:45.035] <TB2> INFO: Expecting 2560 events.
[11:26:45.917] <TB2> INFO: 2560 events read in total (291ms).
[11:26:45.917] <TB2> INFO: Test took 1189ms.
[11:26:46.225] <TB2> INFO: Expecting 2560 events.
[11:26:47.103] <TB2> INFO: 2560 events read in total (287ms).
[11:26:47.104] <TB2> INFO: Test took 1186ms.
[11:26:47.411] <TB2> INFO: Expecting 2560 events.
[11:26:48.290] <TB2> INFO: 2560 events read in total (287ms).
[11:26:48.290] <TB2> INFO: Test took 1186ms.
[11:26:48.598] <TB2> INFO: Expecting 2560 events.
[11:26:49.477] <TB2> INFO: 2560 events read in total (287ms).
[11:26:49.477] <TB2> INFO: Test took 1187ms.
[11:26:49.785] <TB2> INFO: Expecting 2560 events.
[11:26:50.663] <TB2> INFO: 2560 events read in total (287ms).
[11:26:50.664] <TB2> INFO: Test took 1187ms.
[11:26:50.971] <TB2> INFO: Expecting 2560 events.
[11:26:51.850] <TB2> INFO: 2560 events read in total (287ms).
[11:26:51.850] <TB2> INFO: Test took 1186ms.
[11:26:52.158] <TB2> INFO: Expecting 2560 events.
[11:26:53.041] <TB2> INFO: 2560 events read in total (291ms).
[11:26:53.041] <TB2> INFO: Test took 1190ms.
[11:26:53.350] <TB2> INFO: Expecting 2560 events.
[11:26:54.231] <TB2> INFO: 2560 events read in total (290ms).
[11:26:54.231] <TB2> INFO: Test took 1189ms.
[11:26:54.539] <TB2> INFO: Expecting 2560 events.
[11:26:55.421] <TB2> INFO: 2560 events read in total (290ms).
[11:26:55.421] <TB2> INFO: Test took 1189ms.
[11:26:55.730] <TB2> INFO: Expecting 2560 events.
[11:26:56.611] <TB2> INFO: 2560 events read in total (290ms).
[11:26:56.612] <TB2> INFO: Test took 1190ms.
[11:26:56.920] <TB2> INFO: Expecting 2560 events.
[11:26:57.807] <TB2> INFO: 2560 events read in total (296ms).
[11:26:57.807] <TB2> INFO: Test took 1195ms.
[11:26:58.115] <TB2> INFO: Expecting 2560 events.
[11:26:58.999] <TB2> INFO: 2560 events read in total (292ms).
[11:26:58.999] <TB2> INFO: Test took 1191ms.
[11:26:58.002] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:26:59.308] <TB2> INFO: Expecting 655360 events.
[11:27:13.621] <TB2> INFO: 655360 events read in total (13722ms).
[11:27:13.635] <TB2> INFO: Expecting 655360 events.
[11:27:27.750] <TB2> INFO: 655360 events read in total (13712ms).
[11:27:27.767] <TB2> INFO: Expecting 655360 events.
[11:27:41.952] <TB2> INFO: 655360 events read in total (13782ms).
[11:27:41.977] <TB2> INFO: Expecting 655360 events.
[11:27:56.199] <TB2> INFO: 655360 events read in total (13819ms).
[11:27:56.231] <TB2> INFO: Expecting 655360 events.
[11:28:10.374] <TB2> INFO: 655360 events read in total (13740ms).
[11:28:10.401] <TB2> INFO: Expecting 655360 events.
[11:28:24.557] <TB2> INFO: 655360 events read in total (13753ms).
[11:28:24.599] <TB2> INFO: Expecting 655360 events.
[11:28:38.687] <TB2> INFO: 655360 events read in total (13685ms).
[11:28:38.740] <TB2> INFO: Expecting 655360 events.
[11:28:52.827] <TB2> INFO: 655360 events read in total (13684ms).
[11:28:52.869] <TB2> INFO: Expecting 655360 events.
[11:29:06.900] <TB2> INFO: 655360 events read in total (13629ms).
[11:29:06.952] <TB2> INFO: Expecting 655360 events.
[11:29:21.043] <TB2> INFO: 655360 events read in total (13688ms).
[11:29:21.130] <TB2> INFO: Expecting 655360 events.
[11:29:35.171] <TB2> INFO: 655360 events read in total (13638ms).
[11:29:35.271] <TB2> INFO: Expecting 655360 events.
[11:29:49.334] <TB2> INFO: 655360 events read in total (13660ms).
[11:29:49.392] <TB2> INFO: Expecting 655360 events.
[11:30:03.536] <TB2> INFO: 655360 events read in total (13741ms).
[11:30:03.632] <TB2> INFO: Expecting 655360 events.
[11:30:17.458] <TB2> INFO: 644520 events read in total (13423ms).
[11:30:17.921] <TB2> INFO: 655360 events read in total (13886ms).
[11:30:18.010] <TB2> INFO: Expecting 655360 events.
[11:30:32.119] <TB2> INFO: 655360 events read in total (13706ms).
[11:30:32.245] <TB2> INFO: Expecting 655360 events.
[11:30:46.375] <TB2> INFO: 655360 events read in total (13727ms).
[11:30:46.492] <TB2> INFO: Test took 227490ms.
[11:30:46.573] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:30:46.838] <TB2> INFO: Expecting 655360 events.
[11:31:00.875] <TB2> INFO: 655360 events read in total (13446ms).
[11:31:00.891] <TB2> INFO: Expecting 655360 events.
[11:31:14.935] <TB2> INFO: 655360 events read in total (13641ms).
[11:31:14.951] <TB2> INFO: Expecting 655360 events.
[11:31:29.104] <TB2> INFO: 655360 events read in total (13750ms).
[11:31:29.125] <TB2> INFO: Expecting 655360 events.
[11:31:43.209] <TB2> INFO: 655360 events read in total (13681ms).
[11:31:43.243] <TB2> INFO: Expecting 655360 events.
[11:31:57.359] <TB2> INFO: 655360 events read in total (13713ms).
[11:31:57.387] <TB2> INFO: Expecting 655360 events.
[11:32:11.580] <TB2> INFO: 655360 events read in total (13790ms).
[11:32:11.612] <TB2> INFO: Expecting 655360 events.
[11:32:25.714] <TB2> INFO: 655360 events read in total (13700ms).
[11:32:25.766] <TB2> INFO: Expecting 655360 events.
[11:32:39.725] <TB2> INFO: 655360 events read in total (13556ms).
[11:32:39.766] <TB2> INFO: Expecting 655360 events.
[11:32:53.851] <TB2> INFO: 655360 events read in total (13682ms).
[11:32:53.946] <TB2> INFO: Expecting 655360 events.
[11:33:07.930] <TB2> INFO: 655360 events read in total (13581ms).
[11:33:08.018] <TB2> INFO: Expecting 655360 events.
[11:33:22.161] <TB2> INFO: 655360 events read in total (13740ms).
[11:33:22.224] <TB2> INFO: Expecting 655360 events.
[11:33:36.364] <TB2> INFO: 655360 events read in total (13737ms).
[11:33:36.475] <TB2> INFO: Expecting 655360 events.
[11:33:50.708] <TB2> INFO: 655360 events read in total (13830ms).
[11:33:50.794] <TB2> INFO: Expecting 655360 events.
[11:34:04.877] <TB2> INFO: 655360 events read in total (13680ms).
[11:34:04.966] <TB2> INFO: Expecting 655360 events.
[11:34:18.952] <TB2> INFO: 655360 events read in total (13583ms).
[11:34:19.057] <TB2> INFO: Expecting 655360 events.
[11:34:33.179] <TB2> INFO: 655360 events read in total (13719ms).
[11:34:33.281] <TB2> INFO: Test took 226708ms.
[11:34:33.440] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.444] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.449] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.453] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.458] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.462] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.467] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:34:33.471] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.476] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.481] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:34:33.485] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.490] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.495] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:34:33.499] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:34:33.503] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[11:34:33.508] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[11:34:33.513] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[11:34:33.517] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[11:34:33.522] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[11:34:33.527] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[11:34:33.531] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[11:34:33.536] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[11:34:33.540] <TB2> INFO: safety margin for low PH: adding 11, margin is now 31
[11:34:33.545] <TB2> INFO: safety margin for low PH: adding 12, margin is now 32
[11:34:33.550] <TB2> INFO: safety margin for low PH: adding 13, margin is now 33
[11:34:33.554] <TB2> INFO: safety margin for low PH: adding 14, margin is now 34
[11:34:33.559] <TB2> INFO: safety margin for low PH: adding 15, margin is now 35
[11:34:33.564] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.568] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:34:33.573] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.577] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:34:33.582] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:34:33.587] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[11:34:33.591] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[11:34:33.596] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.600] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.605] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.610] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:34:33.614] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:34:33.619] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:34:33.624] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:34:33.628] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[11:34:33.633] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[11:34:33.637] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[11:34:33.642] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[11:34:33.646] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[11:34:33.680] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C0.dat
[11:34:33.680] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C1.dat
[11:34:33.680] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C2.dat
[11:34:33.680] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C3.dat
[11:34:33.681] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C4.dat
[11:34:33.681] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C5.dat
[11:34:33.681] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C6.dat
[11:34:33.681] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C7.dat
[11:34:33.681] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C8.dat
[11:34:33.681] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C9.dat
[11:34:33.681] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C10.dat
[11:34:33.681] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C11.dat
[11:34:33.681] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C12.dat
[11:34:33.682] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C13.dat
[11:34:33.682] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C14.dat
[11:34:33.682] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C15.dat
[11:34:33.916] <TB2> INFO: Expecting 41600 events.
[11:34:37.050] <TB2> INFO: 41600 events read in total (2543ms).
[11:34:37.051] <TB2> INFO: Test took 3367ms.
[11:34:37.493] <TB2> INFO: Expecting 41600 events.
[11:34:40.529] <TB2> INFO: 41600 events read in total (2444ms).
[11:34:40.530] <TB2> INFO: Test took 3269ms.
[11:34:40.972] <TB2> INFO: Expecting 41600 events.
[11:34:44.056] <TB2> INFO: 41600 events read in total (2492ms).
[11:34:44.057] <TB2> INFO: Test took 3316ms.
[11:34:44.275] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:44.364] <TB2> INFO: Expecting 2560 events.
[11:34:45.250] <TB2> INFO: 2560 events read in total (295ms).
[11:34:45.250] <TB2> INFO: Test took 975ms.
[11:34:45.252] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:45.559] <TB2> INFO: Expecting 2560 events.
[11:34:46.441] <TB2> INFO: 2560 events read in total (291ms).
[11:34:46.441] <TB2> INFO: Test took 1189ms.
[11:34:46.443] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:46.749] <TB2> INFO: Expecting 2560 events.
[11:34:47.631] <TB2> INFO: 2560 events read in total (290ms).
[11:34:47.631] <TB2> INFO: Test took 1188ms.
[11:34:47.633] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:47.940] <TB2> INFO: Expecting 2560 events.
[11:34:48.823] <TB2> INFO: 2560 events read in total (292ms).
[11:34:48.823] <TB2> INFO: Test took 1190ms.
[11:34:48.825] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:49.131] <TB2> INFO: Expecting 2560 events.
[11:34:50.014] <TB2> INFO: 2560 events read in total (291ms).
[11:34:50.014] <TB2> INFO: Test took 1189ms.
[11:34:50.016] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:50.322] <TB2> INFO: Expecting 2560 events.
[11:34:51.206] <TB2> INFO: 2560 events read in total (292ms).
[11:34:51.206] <TB2> INFO: Test took 1190ms.
[11:34:51.208] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:51.514] <TB2> INFO: Expecting 2560 events.
[11:34:52.399] <TB2> INFO: 2560 events read in total (293ms).
[11:34:52.399] <TB2> INFO: Test took 1191ms.
[11:34:52.401] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:52.708] <TB2> INFO: Expecting 2560 events.
[11:34:53.591] <TB2> INFO: 2560 events read in total (292ms).
[11:34:53.591] <TB2> INFO: Test took 1190ms.
[11:34:53.593] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:53.899] <TB2> INFO: Expecting 2560 events.
[11:34:54.778] <TB2> INFO: 2560 events read in total (287ms).
[11:34:54.778] <TB2> INFO: Test took 1185ms.
[11:34:54.780] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:55.087] <TB2> INFO: Expecting 2560 events.
[11:34:55.965] <TB2> INFO: 2560 events read in total (287ms).
[11:34:55.965] <TB2> INFO: Test took 1185ms.
[11:34:55.967] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:56.273] <TB2> INFO: Expecting 2560 events.
[11:34:57.152] <TB2> INFO: 2560 events read in total (287ms).
[11:34:57.153] <TB2> INFO: Test took 1186ms.
[11:34:57.154] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:57.461] <TB2> INFO: Expecting 2560 events.
[11:34:58.340] <TB2> INFO: 2560 events read in total (287ms).
[11:34:58.340] <TB2> INFO: Test took 1186ms.
[11:34:58.342] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:58.648] <TB2> INFO: Expecting 2560 events.
[11:34:59.532] <TB2> INFO: 2560 events read in total (288ms).
[11:34:59.533] <TB2> INFO: Test took 1191ms.
[11:34:59.535] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:59.841] <TB2> INFO: Expecting 2560 events.
[11:35:00.721] <TB2> INFO: 2560 events read in total (288ms).
[11:35:00.721] <TB2> INFO: Test took 1187ms.
[11:35:00.723] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:01.029] <TB2> INFO: Expecting 2560 events.
[11:35:01.908] <TB2> INFO: 2560 events read in total (287ms).
[11:35:01.908] <TB2> INFO: Test took 1185ms.
[11:35:01.910] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:02.217] <TB2> INFO: Expecting 2560 events.
[11:35:03.095] <TB2> INFO: 2560 events read in total (287ms).
[11:35:03.096] <TB2> INFO: Test took 1186ms.
[11:35:03.097] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:03.404] <TB2> INFO: Expecting 2560 events.
[11:35:04.282] <TB2> INFO: 2560 events read in total (287ms).
[11:35:04.282] <TB2> INFO: Test took 1185ms.
[11:35:04.285] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:04.591] <TB2> INFO: Expecting 2560 events.
[11:35:05.470] <TB2> INFO: 2560 events read in total (288ms).
[11:35:05.470] <TB2> INFO: Test took 1185ms.
[11:35:05.472] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:05.778] <TB2> INFO: Expecting 2560 events.
[11:35:06.660] <TB2> INFO: 2560 events read in total (290ms).
[11:35:06.660] <TB2> INFO: Test took 1188ms.
[11:35:06.662] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:06.968] <TB2> INFO: Expecting 2560 events.
[11:35:07.848] <TB2> INFO: 2560 events read in total (288ms).
[11:35:07.848] <TB2> INFO: Test took 1186ms.
[11:35:07.850] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:08.160] <TB2> INFO: Expecting 2560 events.
[11:35:09.039] <TB2> INFO: 2560 events read in total (288ms).
[11:35:09.039] <TB2> INFO: Test took 1189ms.
[11:35:09.041] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:09.347] <TB2> INFO: Expecting 2560 events.
[11:35:10.226] <TB2> INFO: 2560 events read in total (287ms).
[11:35:10.226] <TB2> INFO: Test took 1185ms.
[11:35:10.228] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:10.534] <TB2> INFO: Expecting 2560 events.
[11:35:11.414] <TB2> INFO: 2560 events read in total (288ms).
[11:35:11.414] <TB2> INFO: Test took 1186ms.
[11:35:11.417] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:11.722] <TB2> INFO: Expecting 2560 events.
[11:35:12.606] <TB2> INFO: 2560 events read in total (292ms).
[11:35:12.606] <TB2> INFO: Test took 1189ms.
[11:35:12.608] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:12.915] <TB2> INFO: Expecting 2560 events.
[11:35:13.800] <TB2> INFO: 2560 events read in total (294ms).
[11:35:13.800] <TB2> INFO: Test took 1192ms.
[11:35:13.802] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:14.108] <TB2> INFO: Expecting 2560 events.
[11:35:14.994] <TB2> INFO: 2560 events read in total (294ms).
[11:35:14.994] <TB2> INFO: Test took 1192ms.
[11:35:14.996] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:15.303] <TB2> INFO: Expecting 2560 events.
[11:35:16.188] <TB2> INFO: 2560 events read in total (293ms).
[11:35:16.188] <TB2> INFO: Test took 1192ms.
[11:35:16.190] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:16.496] <TB2> INFO: Expecting 2560 events.
[11:35:17.380] <TB2> INFO: 2560 events read in total (292ms).
[11:35:17.380] <TB2> INFO: Test took 1190ms.
[11:35:17.382] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:17.688] <TB2> INFO: Expecting 2560 events.
[11:35:18.574] <TB2> INFO: 2560 events read in total (294ms).
[11:35:18.574] <TB2> INFO: Test took 1192ms.
[11:35:18.576] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:18.882] <TB2> INFO: Expecting 2560 events.
[11:35:19.765] <TB2> INFO: 2560 events read in total (291ms).
[11:35:19.766] <TB2> INFO: Test took 1190ms.
[11:35:19.768] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:20.074] <TB2> INFO: Expecting 2560 events.
[11:35:20.960] <TB2> INFO: 2560 events read in total (294ms).
[11:35:20.961] <TB2> INFO: Test took 1194ms.
[11:35:20.963] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:35:21.269] <TB2> INFO: Expecting 2560 events.
[11:35:22.152] <TB2> INFO: 2560 events read in total (292ms).
[11:35:22.153] <TB2> INFO: Test took 1190ms.
[11:35:22.615] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 633 seconds
[11:35:22.615] <TB2> INFO: PH scale (per ROC): 38 58 39 45 64 66 55 47 39 48 48 48 49 53 59 46
[11:35:22.615] <TB2> INFO: PH offset (per ROC): 108 130 103 103 120 130 140 104 100 112 101 110 87 126 102 97
[11:35:22.620] <TB2> INFO: Decoding statistics:
[11:35:22.620] <TB2> INFO: General information:
[11:35:22.620] <TB2> INFO: 16bit words read: 127882
[11:35:22.620] <TB2> INFO: valid events total: 20480
[11:35:22.620] <TB2> INFO: empty events: 17979
[11:35:22.620] <TB2> INFO: valid events with pixels: 2501
[11:35:22.620] <TB2> INFO: valid pixel hits: 2501
[11:35:22.620] <TB2> INFO: Event errors: 0
[11:35:22.620] <TB2> INFO: start marker: 0
[11:35:22.620] <TB2> INFO: stop marker: 0
[11:35:22.620] <TB2> INFO: overflow: 0
[11:35:22.620] <TB2> INFO: invalid 5bit words: 0
[11:35:22.620] <TB2> INFO: invalid XOR eye diagram: 0
[11:35:22.620] <TB2> INFO: frame (failed synchr.): 0
[11:35:22.621] <TB2> INFO: idle data (no TBM trl): 0
[11:35:22.621] <TB2> INFO: no data (only TBM hdr): 0
[11:35:22.621] <TB2> INFO: TBM errors: 0
[11:35:22.621] <TB2> INFO: flawed TBM headers: 0
[11:35:22.621] <TB2> INFO: flawed TBM trailers: 0
[11:35:22.621] <TB2> INFO: event ID mismatches: 0
[11:35:22.621] <TB2> INFO: ROC errors: 0
[11:35:22.621] <TB2> INFO: missing ROC header(s): 0
[11:35:22.621] <TB2> INFO: misplaced readback start: 0
[11:35:22.621] <TB2> INFO: Pixel decoding errors: 0
[11:35:22.621] <TB2> INFO: pixel data incomplete: 0
[11:35:22.621] <TB2> INFO: pixel address: 0
[11:35:22.621] <TB2> INFO: pulse height fill bit: 0
[11:35:22.621] <TB2> INFO: buffer corruption: 0
[11:35:22.886] <TB2> INFO: ######################################################################
[11:35:22.886] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[11:35:22.886] <TB2> INFO: ######################################################################
[11:35:22.897] <TB2> INFO: scanning low vcal = 10
[11:35:23.129] <TB2> INFO: Expecting 41600 events.
[11:35:26.691] <TB2> INFO: 41600 events read in total (2971ms).
[11:35:26.691] <TB2> INFO: Test took 3794ms.
[11:35:26.694] <TB2> INFO: scanning low vcal = 20
[11:35:26.992] <TB2> INFO: Expecting 41600 events.
[11:35:30.561] <TB2> INFO: 41600 events read in total (2977ms).
[11:35:30.561] <TB2> INFO: Test took 3867ms.
[11:35:30.563] <TB2> INFO: scanning low vcal = 30
[11:35:30.862] <TB2> INFO: Expecting 41600 events.
[11:35:34.535] <TB2> INFO: 41600 events read in total (3081ms).
[11:35:34.535] <TB2> INFO: Test took 3972ms.
[11:35:34.538] <TB2> INFO: scanning low vcal = 40
[11:35:34.816] <TB2> INFO: Expecting 41600 events.
[11:35:38.770] <TB2> INFO: 41600 events read in total (3362ms).
[11:35:38.770] <TB2> INFO: Test took 4232ms.
[11:35:38.773] <TB2> INFO: scanning low vcal = 50
[11:35:39.050] <TB2> INFO: Expecting 41600 events.
[11:35:43.021] <TB2> INFO: 41600 events read in total (3380ms).
[11:35:43.022] <TB2> INFO: Test took 4249ms.
[11:35:43.025] <TB2> INFO: scanning low vcal = 60
[11:35:43.301] <TB2> INFO: Expecting 41600 events.
[11:35:47.308] <TB2> INFO: 41600 events read in total (3415ms).
[11:35:47.309] <TB2> INFO: Test took 4284ms.
[11:35:47.312] <TB2> INFO: scanning low vcal = 70
[11:35:47.588] <TB2> INFO: Expecting 41600 events.
[11:35:51.591] <TB2> INFO: 41600 events read in total (3411ms).
[11:35:51.592] <TB2> INFO: Test took 4280ms.
[11:35:51.595] <TB2> INFO: scanning low vcal = 80
[11:35:51.888] <TB2> INFO: Expecting 41600 events.
[11:35:55.900] <TB2> INFO: 41600 events read in total (3421ms).
[11:35:55.901] <TB2> INFO: Test took 4306ms.
[11:35:55.904] <TB2> INFO: scanning low vcal = 90
[11:35:56.180] <TB2> INFO: Expecting 41600 events.
[11:36:00.258] <TB2> INFO: 41600 events read in total (3486ms).
[11:36:00.259] <TB2> INFO: Test took 4355ms.
[11:36:00.262] <TB2> INFO: scanning low vcal = 100
[11:36:00.538] <TB2> INFO: Expecting 41600 events.
[11:36:04.546] <TB2> INFO: 41600 events read in total (3416ms).
[11:36:04.547] <TB2> INFO: Test took 4285ms.
[11:36:04.550] <TB2> INFO: scanning low vcal = 110
[11:36:04.828] <TB2> INFO: Expecting 41600 events.
[11:36:08.822] <TB2> INFO: 41600 events read in total (3403ms).
[11:36:08.823] <TB2> INFO: Test took 4273ms.
[11:36:08.825] <TB2> INFO: scanning low vcal = 120
[11:36:09.102] <TB2> INFO: Expecting 41600 events.
[11:36:13.088] <TB2> INFO: 41600 events read in total (3395ms).
[11:36:13.089] <TB2> INFO: Test took 4264ms.
[11:36:13.092] <TB2> INFO: scanning low vcal = 130
[11:36:13.368] <TB2> INFO: Expecting 41600 events.
[11:36:17.333] <TB2> INFO: 41600 events read in total (3373ms).
[11:36:17.333] <TB2> INFO: Test took 4241ms.
[11:36:17.336] <TB2> INFO: scanning low vcal = 140
[11:36:17.613] <TB2> INFO: Expecting 41600 events.
[11:36:21.599] <TB2> INFO: 41600 events read in total (3395ms).
[11:36:21.600] <TB2> INFO: Test took 4264ms.
[11:36:21.603] <TB2> INFO: scanning low vcal = 150
[11:36:21.879] <TB2> INFO: Expecting 41600 events.
[11:36:25.835] <TB2> INFO: 41600 events read in total (3365ms).
[11:36:25.836] <TB2> INFO: Test took 4233ms.
[11:36:25.839] <TB2> INFO: scanning low vcal = 160
[11:36:26.116] <TB2> INFO: Expecting 41600 events.
[11:36:30.184] <TB2> INFO: 41600 events read in total (3477ms).
[11:36:30.185] <TB2> INFO: Test took 4346ms.
[11:36:30.188] <TB2> INFO: scanning low vcal = 170
[11:36:30.495] <TB2> INFO: Expecting 41600 events.
[11:36:34.455] <TB2> INFO: 41600 events read in total (3368ms).
[11:36:34.455] <TB2> INFO: Test took 4267ms.
[11:36:34.459] <TB2> INFO: scanning low vcal = 180
[11:36:34.773] <TB2> INFO: Expecting 41600 events.
[11:36:38.846] <TB2> INFO: 41600 events read in total (3482ms).
[11:36:38.847] <TB2> INFO: Test took 4388ms.
[11:36:38.850] <TB2> INFO: scanning low vcal = 190
[11:36:39.126] <TB2> INFO: Expecting 41600 events.
[11:36:43.113] <TB2> INFO: 41600 events read in total (3395ms).
[11:36:43.114] <TB2> INFO: Test took 4264ms.
[11:36:43.116] <TB2> INFO: scanning low vcal = 200
[11:36:43.393] <TB2> INFO: Expecting 41600 events.
[11:36:47.407] <TB2> INFO: 41600 events read in total (3422ms).
[11:36:47.408] <TB2> INFO: Test took 4291ms.
[11:36:47.410] <TB2> INFO: scanning low vcal = 210
[11:36:47.720] <TB2> INFO: Expecting 41600 events.
[11:36:51.738] <TB2> INFO: 41600 events read in total (3426ms).
[11:36:51.739] <TB2> INFO: Test took 4328ms.
[11:36:51.742] <TB2> INFO: scanning low vcal = 220
[11:36:52.018] <TB2> INFO: Expecting 41600 events.
[11:36:56.054] <TB2> INFO: 41600 events read in total (3444ms).
[11:36:56.055] <TB2> INFO: Test took 4313ms.
[11:36:56.059] <TB2> INFO: scanning low vcal = 230
[11:36:56.334] <TB2> INFO: Expecting 41600 events.
[11:37:00.323] <TB2> INFO: 41600 events read in total (3397ms).
[11:37:00.324] <TB2> INFO: Test took 4265ms.
[11:37:00.326] <TB2> INFO: scanning low vcal = 240
[11:37:00.638] <TB2> INFO: Expecting 41600 events.
[11:37:04.581] <TB2> INFO: 41600 events read in total (3352ms).
[11:37:04.582] <TB2> INFO: Test took 4255ms.
[11:37:04.585] <TB2> INFO: scanning low vcal = 250
[11:37:04.862] <TB2> INFO: Expecting 41600 events.
[11:37:08.844] <TB2> INFO: 41600 events read in total (3390ms).
[11:37:08.844] <TB2> INFO: Test took 4259ms.
[11:37:08.848] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[11:37:09.124] <TB2> INFO: Expecting 41600 events.
[11:37:13.075] <TB2> INFO: 41600 events read in total (3359ms).
[11:37:13.075] <TB2> INFO: Test took 4227ms.
[11:37:13.078] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[11:37:13.355] <TB2> INFO: Expecting 41600 events.
[11:37:17.298] <TB2> INFO: 41600 events read in total (3351ms).
[11:37:17.298] <TB2> INFO: Test took 4220ms.
[11:37:17.301] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[11:37:17.578] <TB2> INFO: Expecting 41600 events.
[11:37:21.520] <TB2> INFO: 41600 events read in total (3350ms).
[11:37:21.520] <TB2> INFO: Test took 4219ms.
[11:37:21.523] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[11:37:21.800] <TB2> INFO: Expecting 41600 events.
[11:37:25.746] <TB2> INFO: 41600 events read in total (3354ms).
[11:37:25.747] <TB2> INFO: Test took 4224ms.
[11:37:25.750] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[11:37:26.026] <TB2> INFO: Expecting 41600 events.
[11:37:29.968] <TB2> INFO: 41600 events read in total (3350ms).
[11:37:29.969] <TB2> INFO: Test took 4219ms.
[11:37:30.369] <TB2> INFO: PixTestGainPedestal::measure() done
[11:38:03.151] <TB2> INFO: PixTestGainPedestal::fit() done
[11:38:03.152] <TB2> INFO: non-linearity mean: 0.948 0.979 0.924 0.929 0.983 0.986 0.977 0.918 0.942 0.951 0.949 0.947 0.963 0.981 0.975 0.928
[11:38:03.152] <TB2> INFO: non-linearity RMS: 0.192 0.004 0.161 0.141 0.003 0.003 0.005 0.104 0.148 0.039 0.062 0.048 0.026 0.007 0.009 0.125
[11:38:03.152] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[11:38:03.175] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[11:38:03.198] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[11:38:03.221] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[11:38:03.244] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[11:38:03.266] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[11:38:03.289] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[11:38:03.312] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[11:38:03.335] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[11:38:03.358] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[11:38:03.380] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[11:38:03.403] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[11:38:03.426] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[11:38:03.449] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[11:38:03.471] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[11:38:03.494] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[11:38:03.516] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 160 seconds
[11:38:03.516] <TB2> INFO: Decoding statistics:
[11:38:03.516] <TB2> INFO: General information:
[11:38:03.516] <TB2> INFO: 16bit words read: 3327886
[11:38:03.516] <TB2> INFO: valid events total: 332800
[11:38:03.516] <TB2> INFO: empty events: 0
[11:38:03.517] <TB2> INFO: valid events with pixels: 332800
[11:38:03.517] <TB2> INFO: valid pixel hits: 665543
[11:38:03.517] <TB2> INFO: Event errors: 0
[11:38:03.517] <TB2> INFO: start marker: 0
[11:38:03.517] <TB2> INFO: stop marker: 0
[11:38:03.517] <TB2> INFO: overflow: 0
[11:38:03.517] <TB2> INFO: invalid 5bit words: 0
[11:38:03.517] <TB2> INFO: invalid XOR eye diagram: 0
[11:38:03.517] <TB2> INFO: frame (failed synchr.): 0
[11:38:03.517] <TB2> INFO: idle data (no TBM trl): 0
[11:38:03.517] <TB2> INFO: no data (only TBM hdr): 0
[11:38:03.517] <TB2> INFO: TBM errors: 0
[11:38:03.517] <TB2> INFO: flawed TBM headers: 0
[11:38:03.517] <TB2> INFO: flawed TBM trailers: 0
[11:38:03.517] <TB2> INFO: event ID mismatches: 0
[11:38:03.517] <TB2> INFO: ROC errors: 0
[11:38:03.517] <TB2> INFO: missing ROC header(s): 0
[11:38:03.517] <TB2> INFO: misplaced readback start: 0
[11:38:03.517] <TB2> INFO: Pixel decoding errors: 0
[11:38:03.517] <TB2> INFO: pixel data incomplete: 0
[11:38:03.517] <TB2> INFO: pixel address: 0
[11:38:03.517] <TB2> INFO: pulse height fill bit: 0
[11:38:03.517] <TB2> INFO: buffer corruption: 0
[11:38:03.534] <TB2> INFO: Decoding statistics:
[11:38:03.534] <TB2> INFO: General information:
[11:38:03.534] <TB2> INFO: 16bit words read: 3457304
[11:38:03.534] <TB2> INFO: valid events total: 353536
[11:38:03.534] <TB2> INFO: empty events: 18235
[11:38:03.534] <TB2> INFO: valid events with pixels: 335301
[11:38:03.534] <TB2> INFO: valid pixel hits: 668044
[11:38:03.534] <TB2> INFO: Event errors: 0
[11:38:03.534] <TB2> INFO: start marker: 0
[11:38:03.534] <TB2> INFO: stop marker: 0
[11:38:03.534] <TB2> INFO: overflow: 0
[11:38:03.534] <TB2> INFO: invalid 5bit words: 0
[11:38:03.534] <TB2> INFO: invalid XOR eye diagram: 0
[11:38:03.534] <TB2> INFO: frame (failed synchr.): 0
[11:38:03.534] <TB2> INFO: idle data (no TBM trl): 0
[11:38:03.534] <TB2> INFO: no data (only TBM hdr): 0
[11:38:03.534] <TB2> INFO: TBM errors: 0
[11:38:03.534] <TB2> INFO: flawed TBM headers: 0
[11:38:03.534] <TB2> INFO: flawed TBM trailers: 0
[11:38:03.534] <TB2> INFO: event ID mismatches: 0
[11:38:03.534] <TB2> INFO: ROC errors: 0
[11:38:03.534] <TB2> INFO: missing ROC header(s): 0
[11:38:03.534] <TB2> INFO: misplaced readback start: 0
[11:38:03.534] <TB2> INFO: Pixel decoding errors: 0
[11:38:03.534] <TB2> INFO: pixel data incomplete: 0
[11:38:03.534] <TB2> INFO: pixel address: 0
[11:38:03.534] <TB2> INFO: pulse height fill bit: 0
[11:38:03.534] <TB2> INFO: buffer corruption: 0
[11:38:03.534] <TB2> INFO: enter test to run
[11:38:03.535] <TB2> INFO: test: exit no parameter change
[11:38:03.575] <TB2> QUIET: Connection to board 156 closed.
[11:38:03.576] <TB2> INFO: pXar: this is the end, my friend