[11:56:14.564] <TB2> INFO: *** Welcome to pxar ***
[11:56:14.564] <TB2> INFO: *** Today: 2016/11/03
[11:56:14.570] <TB2> INFO: *** Version: c8ba-dirty
[11:56:14.570] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C15.dat
[11:56:14.570] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[11:56:14.570] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//defaultMaskFile.dat
[11:56:14.570] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters_C15.dat
[11:56:14.626] <TB2> INFO: clk: 4
[11:56:14.626] <TB2> INFO: ctr: 4
[11:56:14.626] <TB2> INFO: sda: 19
[11:56:14.626] <TB2> INFO: tin: 9
[11:56:14.626] <TB2> INFO: level: 15
[11:56:14.626] <TB2> INFO: triggerdelay: 0
[11:56:14.626] <TB2> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[11:56:14.626] <TB2> INFO: Log level: INFO
[11:56:14.635] <TB2> INFO: Found DTB DTB_WXC55Z
[11:56:14.646] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[11:56:14.648] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[11:56:14.650] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[11:56:16.137] <TB2> INFO: DUT info:
[11:56:16.137] <TB2> INFO: The DUT currently contains the following objects:
[11:56:16.137] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[11:56:16.137] <TB2> INFO: TBM Core alpha (0): 7 registers set
[11:56:16.137] <TB2> INFO: TBM Core beta (1): 7 registers set
[11:56:16.137] <TB2> INFO: TBM Core alpha (2): 7 registers set
[11:56:16.137] <TB2> INFO: TBM Core beta (3): 7 registers set
[11:56:16.137] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:56:16.137] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.137] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.137] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.137] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.138] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.138] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.138] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.138] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.138] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.138] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.138] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.138] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.138] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.138] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.138] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.138] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:16.538] <TB2> INFO: enter 'restricted' command line mode
[11:56:16.539] <TB2> INFO: enter test to run
[11:56:16.539] <TB2> INFO: test: pretest no parameter change
[11:56:16.539] <TB2> INFO: running: pretest
[11:56:17.079] <TB2> INFO: ######################################################################
[11:56:17.079] <TB2> INFO: PixTestPretest::doTest()
[11:56:17.079] <TB2> INFO: ######################################################################
[11:56:17.080] <TB2> INFO: ----------------------------------------------------------------------
[11:56:17.080] <TB2> INFO: PixTestPretest::programROC()
[11:56:17.080] <TB2> INFO: ----------------------------------------------------------------------
[11:56:35.093] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:56:35.093] <TB2> INFO: IA differences per ROC: 17.7 19.3 16.9 16.9 18.5 17.7 19.3 19.3 16.9 20.1 18.5 18.5 16.1 18.5 19.3 17.7
[11:56:35.129] <TB2> INFO: ----------------------------------------------------------------------
[11:56:35.129] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:56:35.129] <TB2> INFO: ----------------------------------------------------------------------
[11:56:42.312] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 385.9 mA = 24.1188 mA/ROC
[11:56:42.312] <TB2> INFO: i(loss) [mA/ROC]: 20.1 20.1 20.1 19.3 20.1 20.1 19.3 19.3 19.3 20.1 20.1 19.3 19.3 19.3 20.1 19.3
[11:56:42.340] <TB2> INFO: ----------------------------------------------------------------------
[11:56:42.340] <TB2> INFO: PixTestPretest::findTiming()
[11:56:42.340] <TB2> INFO: ----------------------------------------------------------------------
[11:56:42.340] <TB2> INFO: PixTestCmd::init()

[11:57:13.522] <TB2> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:57:13.522] <TB2> INFO: (success/tries = 100/100), width = 4
[11:57:15.018] <TB2> INFO: ----------------------------------------------------------------------
[11:57:15.018] <TB2> INFO: PixTestPretest::findWorkingPixel()
[11:57:15.018] <TB2> INFO: ----------------------------------------------------------------------
[11:57:15.109] <TB2> INFO: Expecting 231680 events.
[11:57:24.667] <TB2> INFO: 231680 events read in total (8966ms).
[11:57:24.673] <TB2> INFO: Test took 9653ms.
[11:57:24.919] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:57:24.948] <TB2> INFO: ----------------------------------------------------------------------
[11:57:24.948] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[11:57:24.948] <TB2> INFO: ----------------------------------------------------------------------
[11:57:25.040] <TB2> INFO: Expecting 231680 events.
[11:57:34.705] <TB2> INFO: 231680 events read in total (9074ms).
[11:57:34.713] <TB2> INFO: Test took 9762ms.
[11:57:34.971] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[11:57:34.971] <TB2> INFO: CalDel: 91 76 83 85 87 92 90 73 83 97 98 104 85 89 88 101
[11:57:34.971] <TB2> INFO: VthrComp: 51 56 51 51 51 52 51 51 51 51 51 54 51 51 51 52
[11:57:34.973] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C0.dat
[11:57:34.973] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C1.dat
[11:57:34.973] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C2.dat
[11:57:34.973] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C3.dat
[11:57:34.973] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C4.dat
[11:57:34.974] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C5.dat
[11:57:34.974] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C6.dat
[11:57:34.974] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C7.dat
[11:57:34.974] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C8.dat
[11:57:34.974] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C9.dat
[11:57:34.974] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C10.dat
[11:57:34.974] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C11.dat
[11:57:34.974] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C12.dat
[11:57:34.974] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C13.dat
[11:57:34.974] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C14.dat
[11:57:34.975] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C15.dat
[11:57:34.975] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[11:57:34.975] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[11:57:34.975] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[11:57:34.975] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[11:57:34.975] <TB2> INFO: PixTestPretest::doTest() done, duration: 78 seconds
[11:57:35.070] <TB2> INFO: enter test to run
[11:57:35.070] <TB2> INFO: test: fulltest no parameter change
[11:57:35.070] <TB2> INFO: running: fulltest
[11:57:35.070] <TB2> INFO: ######################################################################
[11:57:35.070] <TB2> INFO: PixTestFullTest::doTest()
[11:57:35.070] <TB2> INFO: ######################################################################
[11:57:35.071] <TB2> INFO: ######################################################################
[11:57:35.071] <TB2> INFO: PixTestAlive::doTest()
[11:57:35.071] <TB2> INFO: ######################################################################
[11:57:35.072] <TB2> INFO: ----------------------------------------------------------------------
[11:57:35.072] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:57:35.072] <TB2> INFO: ----------------------------------------------------------------------
[11:57:35.305] <TB2> INFO: Expecting 41600 events.
[11:57:38.745] <TB2> INFO: 41600 events read in total (2848ms).
[11:57:38.746] <TB2> INFO: Test took 3673ms.
[11:57:38.974] <TB2> INFO: PixTestAlive::aliveTest() done
[11:57:38.974] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
[11:57:38.975] <TB2> INFO: ----------------------------------------------------------------------
[11:57:38.975] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:57:38.975] <TB2> INFO: ----------------------------------------------------------------------
[11:57:39.207] <TB2> INFO: Expecting 41600 events.
[11:57:42.258] <TB2> INFO: 41600 events read in total (2459ms).
[11:57:42.258] <TB2> INFO: Test took 3282ms.
[11:57:42.259] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:57:42.498] <TB2> INFO: PixTestAlive::maskTest() done
[11:57:42.498] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:57:42.500] <TB2> INFO: ----------------------------------------------------------------------
[11:57:42.500] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:57:42.500] <TB2> INFO: ----------------------------------------------------------------------
[11:57:42.734] <TB2> INFO: Expecting 41600 events.
[11:57:46.191] <TB2> INFO: 41600 events read in total (2866ms).
[11:57:46.191] <TB2> INFO: Test took 3690ms.
[11:57:46.417] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[11:57:46.417] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:57:46.417] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:57:46.418] <TB2> INFO: Decoding statistics:
[11:57:46.418] <TB2> INFO: General information:
[11:57:46.418] <TB2> INFO: 16bit words read: 0
[11:57:46.418] <TB2> INFO: valid events total: 0
[11:57:46.418] <TB2> INFO: empty events: 0
[11:57:46.418] <TB2> INFO: valid events with pixels: 0
[11:57:46.418] <TB2> INFO: valid pixel hits: 0
[11:57:46.418] <TB2> INFO: Event errors: 0
[11:57:46.418] <TB2> INFO: start marker: 0
[11:57:46.418] <TB2> INFO: stop marker: 0
[11:57:46.418] <TB2> INFO: overflow: 0
[11:57:46.418] <TB2> INFO: invalid 5bit words: 0
[11:57:46.418] <TB2> INFO: invalid XOR eye diagram: 0
[11:57:46.418] <TB2> INFO: frame (failed synchr.): 0
[11:57:46.418] <TB2> INFO: idle data (no TBM trl): 0
[11:57:46.418] <TB2> INFO: no data (only TBM hdr): 0
[11:57:46.418] <TB2> INFO: TBM errors: 0
[11:57:46.418] <TB2> INFO: flawed TBM headers: 0
[11:57:46.418] <TB2> INFO: flawed TBM trailers: 0
[11:57:46.418] <TB2> INFO: event ID mismatches: 0
[11:57:46.418] <TB2> INFO: ROC errors: 0
[11:57:46.418] <TB2> INFO: missing ROC header(s): 0
[11:57:46.418] <TB2> INFO: misplaced readback start: 0
[11:57:46.418] <TB2> INFO: Pixel decoding errors: 0
[11:57:46.418] <TB2> INFO: pixel data incomplete: 0
[11:57:46.418] <TB2> INFO: pixel address: 0
[11:57:46.418] <TB2> INFO: pulse height fill bit: 0
[11:57:46.418] <TB2> INFO: buffer corruption: 0
[11:57:46.426] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:57:46.426] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[11:57:46.426] <TB2> INFO: ######################################################################
[11:57:46.426] <TB2> INFO: PixTestReadback::doTest()
[11:57:46.426] <TB2> INFO: ######################################################################
[11:57:46.426] <TB2> INFO: ----------------------------------------------------------------------
[11:57:46.426] <TB2> INFO: PixTestReadback::CalibrateVd()
[11:57:46.427] <TB2> INFO: ----------------------------------------------------------------------
[11:57:56.386] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C0.dat
[11:57:56.386] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C1.dat
[11:57:56.386] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C2.dat
[11:57:56.386] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C3.dat
[11:57:56.387] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C4.dat
[11:57:56.387] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C5.dat
[11:57:56.387] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C6.dat
[11:57:56.387] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C7.dat
[11:57:56.387] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C8.dat
[11:57:56.387] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C9.dat
[11:57:56.387] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C10.dat
[11:57:56.387] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C11.dat
[11:57:56.387] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C12.dat
[11:57:56.387] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C13.dat
[11:57:56.387] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C14.dat
[11:57:56.387] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:57:56.414] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:57:56.414] <TB2> INFO: ----------------------------------------------------------------------
[11:57:56.414] <TB2> INFO: PixTestReadback::CalibrateVa()
[11:57:56.414] <TB2> INFO: ----------------------------------------------------------------------
[11:58:06.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C0.dat
[11:58:06.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C1.dat
[11:58:06.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C2.dat
[11:58:06.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C3.dat
[11:58:06.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C4.dat
[11:58:06.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C5.dat
[11:58:06.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C6.dat
[11:58:06.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C7.dat
[11:58:06.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C8.dat
[11:58:06.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C9.dat
[11:58:06.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C10.dat
[11:58:06.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C11.dat
[11:58:06.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C12.dat
[11:58:06.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C13.dat
[11:58:06.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C14.dat
[11:58:06.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:58:06.329] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:58:06.329] <TB2> INFO: ----------------------------------------------------------------------
[11:58:06.329] <TB2> INFO: PixTestReadback::readbackVbg()
[11:58:06.329] <TB2> INFO: ----------------------------------------------------------------------
[11:58:13.970] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:58:13.970] <TB2> INFO: ----------------------------------------------------------------------
[11:58:13.970] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[11:58:13.970] <TB2> INFO: ----------------------------------------------------------------------
[11:58:13.970] <TB2> INFO: Vbg will be calibrated using Vd calibration
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 157.1calibrated Vbg = 1.17177 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 155.2calibrated Vbg = 1.18127 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 156.1calibrated Vbg = 1.16817 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 153.5calibrated Vbg = 1.16211 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 155calibrated Vbg = 1.16931 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 156.7calibrated Vbg = 1.17871 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 157calibrated Vbg = 1.17744 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 163.5calibrated Vbg = 1.17539 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 158.2calibrated Vbg = 1.16697 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154.9calibrated Vbg = 1.17273 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 155.3calibrated Vbg = 1.16374 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 158.6calibrated Vbg = 1.16396 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 148.8calibrated Vbg = 1.17034 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152.9calibrated Vbg = 1.17877 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 159.7calibrated Vbg = 1.17477 :::*/*/*/*/
[11:58:13.970] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 161calibrated Vbg = 1.17485 :::*/*/*/*/
[11:58:13.972] <TB2> INFO: ----------------------------------------------------------------------
[11:58:13.972] <TB2> INFO: PixTestReadback::CalibrateIa()
[11:58:13.972] <TB2> INFO: ----------------------------------------------------------------------
[12:00:54.255] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:00:54.255] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:00:54.255] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:00:54.255] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:00:54.255] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:00:54.255] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:00:54.255] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:00:54.255] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:00:54.255] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:00:54.255] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:00:54.255] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:00:54.255] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:00:54.256] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:00:54.256] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:00:54.256] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:00:54.256] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:00:54.284] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:00:54.285] <TB2> INFO: PixTestReadback::doTest() done
[12:00:54.285] <TB2> INFO: Decoding statistics:
[12:00:54.285] <TB2> INFO: General information:
[12:00:54.285] <TB2> INFO: 16bit words read: 1536
[12:00:54.285] <TB2> INFO: valid events total: 256
[12:00:54.285] <TB2> INFO: empty events: 256
[12:00:54.285] <TB2> INFO: valid events with pixels: 0
[12:00:54.285] <TB2> INFO: valid pixel hits: 0
[12:00:54.285] <TB2> INFO: Event errors: 0
[12:00:54.285] <TB2> INFO: start marker: 0
[12:00:54.285] <TB2> INFO: stop marker: 0
[12:00:54.285] <TB2> INFO: overflow: 0
[12:00:54.285] <TB2> INFO: invalid 5bit words: 0
[12:00:54.285] <TB2> INFO: invalid XOR eye diagram: 0
[12:00:54.285] <TB2> INFO: frame (failed synchr.): 0
[12:00:54.285] <TB2> INFO: idle data (no TBM trl): 0
[12:00:54.285] <TB2> INFO: no data (only TBM hdr): 0
[12:00:54.285] <TB2> INFO: TBM errors: 0
[12:00:54.285] <TB2> INFO: flawed TBM headers: 0
[12:00:54.285] <TB2> INFO: flawed TBM trailers: 0
[12:00:54.285] <TB2> INFO: event ID mismatches: 0
[12:00:54.285] <TB2> INFO: ROC errors: 0
[12:00:54.285] <TB2> INFO: missing ROC header(s): 0
[12:00:54.285] <TB2> INFO: misplaced readback start: 0
[12:00:54.285] <TB2> INFO: Pixel decoding errors: 0
[12:00:54.285] <TB2> INFO: pixel data incomplete: 0
[12:00:54.285] <TB2> INFO: pixel address: 0
[12:00:54.285] <TB2> INFO: pulse height fill bit: 0
[12:00:54.285] <TB2> INFO: buffer corruption: 0
[12:00:54.321] <TB2> INFO: ######################################################################
[12:00:54.321] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:00:54.321] <TB2> INFO: ######################################################################
[12:00:54.324] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:00:54.335] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:00:54.335] <TB2> INFO: run 1 of 1
[12:00:54.567] <TB2> INFO: Expecting 3120000 events.
[12:01:25.376] <TB2> INFO: 682875 events read in total (30217ms).











[12:01:55.975] <TB2> INFO: 1361580 events read in total (60816ms).











[12:02:26.309] <TB2> INFO: 2038185 events read in total (91150ms).











[12:02:56.991] <TB2> INFO: 2714775 events read in total (121832ms).











[12:03:15.263] <TB2> INFO: 3120000 events read in total (140104ms).
[12:03:15.324] <TB2> INFO: Test took 140990ms.
[12:03:40.141] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 165 seconds
[12:03:40.141] <TB2> INFO: number of dead bumps (per ROC): 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0
[12:03:40.142] <TB2> INFO: separation cut (per ROC): 108 125 117 104 109 107 107 112 100 105 105 127 99 108 103 116
[12:03:40.142] <TB2> INFO: Decoding statistics:
[12:03:40.142] <TB2> INFO: General information:
[12:03:40.142] <TB2> INFO: 16bit words read: 0
[12:03:40.142] <TB2> INFO: valid events total: 0
[12:03:40.142] <TB2> INFO: empty events: 0
[12:03:40.142] <TB2> INFO: valid events with pixels: 0
[12:03:40.142] <TB2> INFO: valid pixel hits: 0
[12:03:40.142] <TB2> INFO: Event errors: 0
[12:03:40.142] <TB2> INFO: start marker: 0
[12:03:40.142] <TB2> INFO: stop marker: 0
[12:03:40.142] <TB2> INFO: overflow: 0
[12:03:40.142] <TB2> INFO: invalid 5bit words: 0
[12:03:40.142] <TB2> INFO: invalid XOR eye diagram: 0
[12:03:40.142] <TB2> INFO: frame (failed synchr.): 0
[12:03:40.142] <TB2> INFO: idle data (no TBM trl): 0
[12:03:40.142] <TB2> INFO: no data (only TBM hdr): 0
[12:03:40.142] <TB2> INFO: TBM errors: 0
[12:03:40.142] <TB2> INFO: flawed TBM headers: 0
[12:03:40.142] <TB2> INFO: flawed TBM trailers: 0
[12:03:40.142] <TB2> INFO: event ID mismatches: 0
[12:03:40.142] <TB2> INFO: ROC errors: 0
[12:03:40.142] <TB2> INFO: missing ROC header(s): 0
[12:03:40.142] <TB2> INFO: misplaced readback start: 0
[12:03:40.142] <TB2> INFO: Pixel decoding errors: 0
[12:03:40.142] <TB2> INFO: pixel data incomplete: 0
[12:03:40.142] <TB2> INFO: pixel address: 0
[12:03:40.142] <TB2> INFO: pulse height fill bit: 0
[12:03:40.142] <TB2> INFO: buffer corruption: 0
[12:03:40.191] <TB2> INFO: ######################################################################
[12:03:40.191] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:03:40.191] <TB2> INFO: ######################################################################
[12:03:40.191] <TB2> INFO: ----------------------------------------------------------------------
[12:03:40.191] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:03:40.191] <TB2> INFO: ----------------------------------------------------------------------
[12:03:40.192] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:03:40.201] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[12:03:40.201] <TB2> INFO: run 1 of 1
[12:03:40.435] <TB2> INFO: Expecting 36608000 events.
[12:04:03.666] <TB2> INFO: 698350 events read in total (22640ms).
[12:04:26.445] <TB2> INFO: 1380750 events read in total (45419ms).
[12:04:49.036] <TB2> INFO: 2065450 events read in total (68010ms).
[12:05:11.316] <TB2> INFO: 2745250 events read in total (90290ms).
[12:05:33.858] <TB2> INFO: 3424400 events read in total (112832ms).
[12:05:56.334] <TB2> INFO: 4104700 events read in total (135308ms).
[12:06:18.825] <TB2> INFO: 4784500 events read in total (157799ms).
[12:06:41.485] <TB2> INFO: 5464300 events read in total (180459ms).
[12:07:03.940] <TB2> INFO: 6144700 events read in total (202914ms).
[12:07:26.284] <TB2> INFO: 6823900 events read in total (225258ms).
[12:07:48.675] <TB2> INFO: 7502450 events read in total (247649ms).
[12:08:11.004] <TB2> INFO: 8180050 events read in total (269978ms).
[12:08:33.391] <TB2> INFO: 8858050 events read in total (292365ms).
[12:08:55.751] <TB2> INFO: 9536800 events read in total (314725ms).
[12:09:18.224] <TB2> INFO: 10215200 events read in total (337198ms).
[12:09:40.820] <TB2> INFO: 10893100 events read in total (359794ms).
[12:10:03.379] <TB2> INFO: 11570150 events read in total (382353ms).
[12:10:25.963] <TB2> INFO: 12247150 events read in total (404937ms).
[12:10:48.273] <TB2> INFO: 12924050 events read in total (427247ms).
[12:11:10.632] <TB2> INFO: 13600800 events read in total (449607ms).
[12:11:33.095] <TB2> INFO: 14276650 events read in total (472069ms).
[12:11:55.577] <TB2> INFO: 14953850 events read in total (494551ms).
[12:12:18.279] <TB2> INFO: 15629150 events read in total (517253ms).
[12:12:40.732] <TB2> INFO: 16304850 events read in total (539706ms).
[12:13:03.230] <TB2> INFO: 16980650 events read in total (562204ms).
[12:13:25.929] <TB2> INFO: 17655900 events read in total (584903ms).
[12:13:48.379] <TB2> INFO: 18328500 events read in total (607353ms).
[12:14:10.826] <TB2> INFO: 18999150 events read in total (629800ms).
[12:14:33.477] <TB2> INFO: 19669150 events read in total (652451ms).
[12:14:56.193] <TB2> INFO: 20341000 events read in total (675167ms).
[12:15:18.378] <TB2> INFO: 21010250 events read in total (697352ms).
[12:15:40.779] <TB2> INFO: 21680850 events read in total (719753ms).
[12:16:03.595] <TB2> INFO: 22351000 events read in total (742569ms).
[12:16:25.943] <TB2> INFO: 23023600 events read in total (764917ms).
[12:16:48.140] <TB2> INFO: 23694150 events read in total (787114ms).
[12:17:10.591] <TB2> INFO: 24364750 events read in total (809565ms).
[12:17:33.160] <TB2> INFO: 25034900 events read in total (832134ms).
[12:17:55.346] <TB2> INFO: 25704300 events read in total (854320ms).
[12:18:17.806] <TB2> INFO: 26375300 events read in total (876780ms).
[12:18:40.171] <TB2> INFO: 27044900 events read in total (899145ms).
[12:19:02.679] <TB2> INFO: 27714350 events read in total (921653ms).
[12:19:25.541] <TB2> INFO: 28383500 events read in total (944515ms).
[12:19:47.887] <TB2> INFO: 29051950 events read in total (966861ms).
[12:20:10.260] <TB2> INFO: 29719050 events read in total (989234ms).
[12:20:32.568] <TB2> INFO: 30387450 events read in total (1011542ms).
[12:20:55.161] <TB2> INFO: 31056050 events read in total (1034135ms).
[12:21:17.429] <TB2> INFO: 31724300 events read in total (1056403ms).
[12:21:39.872] <TB2> INFO: 32392400 events read in total (1078846ms).
[12:22:02.115] <TB2> INFO: 33062850 events read in total (1101089ms).
[12:22:24.558] <TB2> INFO: 33732100 events read in total (1123532ms).
[12:22:46.717] <TB2> INFO: 34403400 events read in total (1145691ms).
[12:23:09.263] <TB2> INFO: 35072300 events read in total (1168237ms).
[12:23:31.930] <TB2> INFO: 35743650 events read in total (1190905ms).
[12:23:54.713] <TB2> INFO: 36423450 events read in total (1213687ms).
[12:24:01.257] <TB2> INFO: 36608000 events read in total (1220231ms).
[12:24:01.307] <TB2> INFO: Test took 1221106ms.
[12:24:01.677] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:03.479] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:05.308] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:06.993] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:08.465] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:09.902] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:11.662] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:13.656] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:15.450] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:17.204] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:19.234] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:21.222] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:23.199] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:25.230] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:26.914] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:28.466] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:24:30.073] <TB2> INFO: PixTestScurves::scurves() done
[12:24:30.073] <TB2> INFO: Vcal mean: 127.42 143.53 128.80 120.85 123.44 128.92 122.53 126.78 123.59 132.99 118.89 134.46 109.52 125.43 120.60 133.91
[12:24:30.073] <TB2> INFO: Vcal RMS: 6.51 5.65 6.20 6.36 5.47 6.20 5.90 6.31 5.91 6.70 6.43 6.23 5.09 5.81 5.89 5.91
[12:24:30.073] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1249 seconds
[12:24:30.073] <TB2> INFO: Decoding statistics:
[12:24:30.073] <TB2> INFO: General information:
[12:24:30.073] <TB2> INFO: 16bit words read: 0
[12:24:30.073] <TB2> INFO: valid events total: 0
[12:24:30.073] <TB2> INFO: empty events: 0
[12:24:30.073] <TB2> INFO: valid events with pixels: 0
[12:24:30.073] <TB2> INFO: valid pixel hits: 0
[12:24:30.073] <TB2> INFO: Event errors: 0
[12:24:30.073] <TB2> INFO: start marker: 0
[12:24:30.073] <TB2> INFO: stop marker: 0
[12:24:30.073] <TB2> INFO: overflow: 0
[12:24:30.073] <TB2> INFO: invalid 5bit words: 0
[12:24:30.073] <TB2> INFO: invalid XOR eye diagram: 0
[12:24:30.073] <TB2> INFO: frame (failed synchr.): 0
[12:24:30.073] <TB2> INFO: idle data (no TBM trl): 0
[12:24:30.073] <TB2> INFO: no data (only TBM hdr): 0
[12:24:30.073] <TB2> INFO: TBM errors: 0
[12:24:30.073] <TB2> INFO: flawed TBM headers: 0
[12:24:30.073] <TB2> INFO: flawed TBM trailers: 0
[12:24:30.073] <TB2> INFO: event ID mismatches: 0
[12:24:30.073] <TB2> INFO: ROC errors: 0
[12:24:30.073] <TB2> INFO: missing ROC header(s): 0
[12:24:30.073] <TB2> INFO: misplaced readback start: 0
[12:24:30.073] <TB2> INFO: Pixel decoding errors: 0
[12:24:30.073] <TB2> INFO: pixel data incomplete: 0
[12:24:30.073] <TB2> INFO: pixel address: 0
[12:24:30.073] <TB2> INFO: pulse height fill bit: 0
[12:24:30.073] <TB2> INFO: buffer corruption: 0
[12:24:30.156] <TB2> INFO: ######################################################################
[12:24:30.156] <TB2> INFO: PixTestTrim::doTest()
[12:24:30.156] <TB2> INFO: ######################################################################
[12:24:30.157] <TB2> INFO: ----------------------------------------------------------------------
[12:24:30.157] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:24:30.157] <TB2> INFO: ----------------------------------------------------------------------
[12:24:30.198] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:24:30.198] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:24:30.208] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:24:30.208] <TB2> INFO: run 1 of 1
[12:24:30.439] <TB2> INFO: Expecting 5025280 events.
[12:25:00.925] <TB2> INFO: 833712 events read in total (29891ms).
[12:25:30.970] <TB2> INFO: 1664216 events read in total (59936ms).
[12:26:00.907] <TB2> INFO: 2492864 events read in total (89873ms).
[12:26:31.102] <TB2> INFO: 3318016 events read in total (120068ms).
[12:27:01.150] <TB2> INFO: 4139704 events read in total (150116ms).
[12:27:31.275] <TB2> INFO: 4960536 events read in total (180241ms).
[12:27:34.030] <TB2> INFO: 5025280 events read in total (182996ms).
[12:27:34.070] <TB2> INFO: Test took 183862ms.
[12:27:49.490] <TB2> INFO: ROC 0 VthrComp = 128
[12:27:49.490] <TB2> INFO: ROC 1 VthrComp = 134
[12:27:49.490] <TB2> INFO: ROC 2 VthrComp = 132
[12:27:49.490] <TB2> INFO: ROC 3 VthrComp = 121
[12:27:49.490] <TB2> INFO: ROC 4 VthrComp = 125
[12:27:49.490] <TB2> INFO: ROC 5 VthrComp = 129
[12:27:49.490] <TB2> INFO: ROC 6 VthrComp = 124
[12:27:49.491] <TB2> INFO: ROC 7 VthrComp = 132
[12:27:49.491] <TB2> INFO: ROC 8 VthrComp = 119
[12:27:49.491] <TB2> INFO: ROC 9 VthrComp = 130
[12:27:49.491] <TB2> INFO: ROC 10 VthrComp = 125
[12:27:49.491] <TB2> INFO: ROC 11 VthrComp = 132
[12:27:49.491] <TB2> INFO: ROC 12 VthrComp = 106
[12:27:49.491] <TB2> INFO: ROC 13 VthrComp = 130
[12:27:49.491] <TB2> INFO: ROC 14 VthrComp = 121
[12:27:49.492] <TB2> INFO: ROC 15 VthrComp = 127
[12:27:49.749] <TB2> INFO: Expecting 41600 events.
[12:27:53.289] <TB2> INFO: 41600 events read in total (2948ms).
[12:27:53.290] <TB2> INFO: Test took 3797ms.
[12:27:53.298] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:27:53.298] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:27:53.308] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:27:53.308] <TB2> INFO: run 1 of 1
[12:27:53.587] <TB2> INFO: Expecting 5025280 events.
[12:28:19.887] <TB2> INFO: 592760 events read in total (25709ms).
[12:28:45.359] <TB2> INFO: 1184112 events read in total (51182ms).
[12:29:10.685] <TB2> INFO: 1775376 events read in total (76507ms).
[12:29:35.857] <TB2> INFO: 2366120 events read in total (101679ms).
[12:30:01.238] <TB2> INFO: 2954376 events read in total (127060ms).
[12:30:26.777] <TB2> INFO: 3541208 events read in total (152599ms).
[12:30:52.165] <TB2> INFO: 4126976 events read in total (177987ms).
[12:31:17.537] <TB2> INFO: 4712744 events read in total (203359ms).
[12:31:31.089] <TB2> INFO: 5025280 events read in total (216911ms).
[12:31:31.169] <TB2> INFO: Test took 217861ms.
[12:31:56.932] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 61.4864 for pixel 13/10 mean/min/max = 46.6447/31.5396/61.7498
[12:31:56.933] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 73.5597 for pixel 20/20 mean/min/max = 56.4669/39.0375/73.8962
[12:31:56.933] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 58.5468 for pixel 0/48 mean/min/max = 45.929/33.3044/58.5535
[12:31:56.933] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.6679 for pixel 51/4 mean/min/max = 46.6122/32.5348/60.6896
[12:31:56.934] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 59.6699 for pixel 20/9 mean/min/max = 45.9375/32.0068/59.8683
[12:31:56.934] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 60.8226 for pixel 47/0 mean/min/max = 47.3472/33.7803/60.9141
[12:31:56.934] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 60.8515 for pixel 21/4 mean/min/max = 46.5568/32.1995/60.9142
[12:31:56.935] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 58.697 for pixel 22/7 mean/min/max = 45.8494/32.9353/58.7634
[12:31:56.935] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 60.6186 for pixel 18/11 mean/min/max = 46.6298/32.4775/60.7822
[12:31:56.936] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 62.5325 for pixel 17/65 mean/min/max = 47.3193/32.0873/62.5513
[12:31:56.936] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 60.0226 for pixel 17/0 mean/min/max = 45.2051/30.3683/60.042
[12:31:56.936] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 68.8436 for pixel 17/1 mean/min/max = 52.8879/36.7438/69.032
[12:31:56.937] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 61.827 for pixel 18/2 mean/min/max = 48.7072/35.4252/61.9891
[12:31:56.937] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 59.3577 for pixel 2/9 mean/min/max = 45.773/32.1834/59.3625
[12:31:56.938] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 59.7927 for pixel 3/2 mean/min/max = 46.3444/32.8607/59.828
[12:31:56.938] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 62.855 for pixel 0/53 mean/min/max = 47.7478/32.5657/62.9298
[12:31:56.938] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:31:57.027] <TB2> INFO: Expecting 411648 events.
[12:32:06.294] <TB2> INFO: 411648 events read in total (8676ms).
[12:32:06.301] <TB2> INFO: Expecting 411648 events.
[12:32:15.425] <TB2> INFO: 411648 events read in total (8721ms).
[12:32:15.435] <TB2> INFO: Expecting 411648 events.
[12:32:24.522] <TB2> INFO: 411648 events read in total (8684ms).
[12:32:24.534] <TB2> INFO: Expecting 411648 events.
[12:32:33.612] <TB2> INFO: 411648 events read in total (8675ms).
[12:32:33.626] <TB2> INFO: Expecting 411648 events.
[12:32:42.690] <TB2> INFO: 411648 events read in total (8659ms).
[12:32:42.707] <TB2> INFO: Expecting 411648 events.
[12:32:51.734] <TB2> INFO: 411648 events read in total (8624ms).
[12:32:51.753] <TB2> INFO: Expecting 411648 events.
[12:33:00.794] <TB2> INFO: 411648 events read in total (8638ms).
[12:33:00.823] <TB2> INFO: Expecting 411648 events.
[12:33:09.860] <TB2> INFO: 411648 events read in total (8634ms).
[12:33:09.895] <TB2> INFO: Expecting 411648 events.
[12:33:18.982] <TB2> INFO: 411648 events read in total (8684ms).
[12:33:19.009] <TB2> INFO: Expecting 411648 events.
[12:33:28.063] <TB2> INFO: 411648 events read in total (8651ms).
[12:33:28.097] <TB2> INFO: Expecting 411648 events.
[12:33:37.026] <TB2> INFO: 411648 events read in total (8527ms).
[12:33:37.059] <TB2> INFO: Expecting 411648 events.
[12:33:46.070] <TB2> INFO: 411648 events read in total (8608ms).
[12:33:46.108] <TB2> INFO: Expecting 411648 events.
[12:33:55.136] <TB2> INFO: 411648 events read in total (8625ms).
[12:33:55.176] <TB2> INFO: Expecting 411648 events.
[12:34:04.204] <TB2> INFO: 411648 events read in total (8625ms).
[12:34:04.261] <TB2> INFO: Expecting 411648 events.
[12:34:13.308] <TB2> INFO: 411648 events read in total (8643ms).
[12:34:13.374] <TB2> INFO: Expecting 411648 events.
[12:34:22.381] <TB2> INFO: 411648 events read in total (8604ms).
[12:34:22.431] <TB2> INFO: Test took 145493ms.
[12:34:23.075] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:34:23.086] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:34:23.086] <TB2> INFO: run 1 of 1
[12:34:23.322] <TB2> INFO: Expecting 5025280 events.
[12:34:49.276] <TB2> INFO: 589336 events read in total (25363ms).
[12:35:14.609] <TB2> INFO: 1176888 events read in total (50696ms).
[12:35:40.326] <TB2> INFO: 1764144 events read in total (76413ms).
[12:36:05.787] <TB2> INFO: 2349912 events read in total (101874ms).
[12:36:31.683] <TB2> INFO: 2940880 events read in total (127770ms).
[12:36:57.387] <TB2> INFO: 3531384 events read in total (153474ms).
[12:37:23.066] <TB2> INFO: 4120800 events read in total (179153ms).
[12:37:49.181] <TB2> INFO: 4708712 events read in total (205268ms).
[12:38:03.093] <TB2> INFO: 5025280 events read in total (219180ms).
[12:38:03.239] <TB2> INFO: Test took 220153ms.
[12:38:28.276] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 0.022390 .. 142.148439
[12:38:28.523] <TB2> INFO: Expecting 208000 events.
[12:38:37.978] <TB2> INFO: 208000 events read in total (8864ms).
[12:38:37.979] <TB2> INFO: Test took 9701ms.
[12:38:38.025] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 152 (-1/-1) hits flags = 528 (plus default)
[12:38:38.034] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:38:38.034] <TB2> INFO: run 1 of 1
[12:38:38.312] <TB2> INFO: Expecting 5091840 events.
[12:39:04.396] <TB2> INFO: 587472 events read in total (25493ms).
[12:39:30.335] <TB2> INFO: 1175096 events read in total (51432ms).
[12:39:56.275] <TB2> INFO: 1762512 events read in total (77373ms).
[12:40:21.999] <TB2> INFO: 2350000 events read in total (103096ms).
[12:40:47.684] <TB2> INFO: 2937424 events read in total (128781ms).
[12:41:13.664] <TB2> INFO: 3524560 events read in total (154761ms).
[12:41:39.377] <TB2> INFO: 4110904 events read in total (180474ms).
[12:42:05.004] <TB2> INFO: 4697416 events read in total (206101ms).
[12:42:22.426] <TB2> INFO: 5091840 events read in total (223523ms).
[12:42:22.538] <TB2> INFO: Test took 224505ms.
[12:42:49.738] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 26.544485 .. 44.953064
[12:42:50.048] <TB2> INFO: Expecting 208000 events.
[12:42:59.723] <TB2> INFO: 208000 events read in total (9083ms).
[12:42:59.724] <TB2> INFO: Test took 9985ms.
[12:42:59.790] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 54 (-1/-1) hits flags = 528 (plus default)
[12:42:59.802] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:42:59.802] <TB2> INFO: run 1 of 1
[12:43:00.080] <TB2> INFO: Expecting 1297920 events.
[12:43:28.341] <TB2> INFO: 670216 events read in total (27669ms).
[12:43:54.298] <TB2> INFO: 1297920 events read in total (53626ms).
[12:43:54.330] <TB2> INFO: Test took 54528ms.
[12:44:07.388] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 28.908665 .. 49.863012
[12:44:07.620] <TB2> INFO: Expecting 208000 events.
[12:44:17.250] <TB2> INFO: 208000 events read in total (9038ms).
[12:44:17.251] <TB2> INFO: Test took 9862ms.
[12:44:17.315] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 18 .. 59 (-1/-1) hits flags = 528 (plus default)
[12:44:17.327] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:44:17.327] <TB2> INFO: run 1 of 1
[12:44:17.605] <TB2> INFO: Expecting 1397760 events.
[12:44:45.346] <TB2> INFO: 642616 events read in total (27150ms).
[12:45:11.927] <TB2> INFO: 1284376 events read in total (53732ms).
[12:45:17.019] <TB2> INFO: 1397760 events read in total (58823ms).
[12:45:17.045] <TB2> INFO: Test took 59718ms.
[12:45:31.285] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 25.623414 .. 55.514353
[12:45:31.528] <TB2> INFO: Expecting 208000 events.
[12:45:41.391] <TB2> INFO: 208000 events read in total (9271ms).
[12:45:41.391] <TB2> INFO: Test took 10105ms.
[12:45:41.442] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 65 (-1/-1) hits flags = 528 (plus default)
[12:45:41.452] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:45:41.452] <TB2> INFO: run 1 of 1
[12:45:41.730] <TB2> INFO: Expecting 1697280 events.
[12:46:09.071] <TB2> INFO: 636352 events read in total (26750ms).
[12:46:35.573] <TB2> INFO: 1272872 events read in total (53253ms).
[12:46:53.271] <TB2> INFO: 1697280 events read in total (70950ms).
[12:46:53.308] <TB2> INFO: Test took 71857ms.
[12:47:09.520] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:47:09.520] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:47:09.531] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:47:09.531] <TB2> INFO: run 1 of 1
[12:47:09.764] <TB2> INFO: Expecting 1364480 events.
[12:47:38.006] <TB2> INFO: 668904 events read in total (27651ms).
[12:48:05.491] <TB2> INFO: 1337248 events read in total (55136ms).
[12:48:07.080] <TB2> INFO: 1364480 events read in total (56725ms).
[12:48:07.112] <TB2> INFO: Test took 57582ms.
[12:48:21.135] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C0.dat
[12:48:21.135] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C1.dat
[12:48:21.135] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C2.dat
[12:48:21.135] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C3.dat
[12:48:21.135] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C4.dat
[12:48:21.135] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C5.dat
[12:48:21.135] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C6.dat
[12:48:21.135] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C7.dat
[12:48:21.135] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C8.dat
[12:48:21.136] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C9.dat
[12:48:21.136] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C10.dat
[12:48:21.136] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C11.dat
[12:48:21.136] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C12.dat
[12:48:21.136] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C13.dat
[12:48:21.136] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C14.dat
[12:48:21.136] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C15.dat
[12:48:21.136] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C0.dat
[12:48:21.143] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C1.dat
[12:48:21.149] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C2.dat
[12:48:21.155] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C3.dat
[12:48:21.161] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C4.dat
[12:48:21.167] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C5.dat
[12:48:21.173] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C6.dat
[12:48:21.179] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C7.dat
[12:48:21.185] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C8.dat
[12:48:21.191] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C9.dat
[12:48:21.196] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C10.dat
[12:48:21.202] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C11.dat
[12:48:21.208] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C12.dat
[12:48:21.214] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C13.dat
[12:48:21.220] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C14.dat
[12:48:21.227] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C15.dat
[12:48:21.236] <TB2> INFO: PixTestTrim::trimTest() done
[12:48:21.236] <TB2> INFO: vtrim: 145 200 124 132 148 138 137 143 116 157 149 164 132 123 136 139
[12:48:21.236] <TB2> INFO: vthrcomp: 128 134 132 121 125 129 124 132 119 130 125 132 106 130 121 127
[12:48:21.236] <TB2> INFO: vcal mean: 35.28 36.80 35.00 34.99 35.00 35.10 35.18 35.02 35.06 35.29 34.96 35.53 34.99 35.00 34.95 35.22
[12:48:21.236] <TB2> INFO: vcal RMS: 1.46 3.36 1.01 1.06 1.12 1.21 1.36 1.06 1.34 1.51 1.22 1.75 1.03 1.15 1.02 1.43
[12:48:21.236] <TB2> INFO: bits mean: 10.47 8.86 9.21 9.67 10.30 9.66 9.88 9.91 9.17 9.87 10.70 8.20 8.95 9.70 9.42 9.25
[12:48:21.236] <TB2> INFO: bits RMS: 2.29 2.46 2.70 2.50 2.33 2.36 2.55 2.41 2.84 2.50 2.38 2.37 2.30 2.67 2.65 2.78
[12:48:21.244] <TB2> INFO: ----------------------------------------------------------------------
[12:48:21.244] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:48:21.245] <TB2> INFO: ----------------------------------------------------------------------
[12:48:21.247] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:48:21.257] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:48:21.257] <TB2> INFO: run 1 of 1
[12:48:21.498] <TB2> INFO: Expecting 4160000 events.
[12:48:54.090] <TB2> INFO: 772005 events read in total (32000ms).
[12:49:25.633] <TB2> INFO: 1536905 events read in total (63543ms).
[12:49:56.956] <TB2> INFO: 2296190 events read in total (94866ms).
[12:50:28.675] <TB2> INFO: 3050935 events read in total (126585ms).
[12:50:59.918] <TB2> INFO: 3802715 events read in total (157828ms).
[12:51:14.907] <TB2> INFO: 4160000 events read in total (172817ms).
[12:51:15.026] <TB2> INFO: Test took 173769ms.
[12:51:43.968] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 242 (-1/-1) hits flags = 528 (plus default)
[12:51:43.980] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:51:43.980] <TB2> INFO: run 1 of 1
[12:51:44.241] <TB2> INFO: Expecting 5054400 events.
[12:52:14.837] <TB2> INFO: 696475 events read in total (30004ms).
[12:52:44.845] <TB2> INFO: 1388500 events read in total (60012ms).
[12:53:14.629] <TB2> INFO: 2078440 events read in total (89796ms).
[12:53:44.551] <TB2> INFO: 2765450 events read in total (119718ms).
[12:54:14.457] <TB2> INFO: 3449870 events read in total (149624ms).
[12:54:43.886] <TB2> INFO: 4132860 events read in total (179053ms).
[12:55:14.217] <TB2> INFO: 4815935 events read in total (209384ms).
[12:55:24.880] <TB2> INFO: 5054400 events read in total (220047ms).
[12:55:24.948] <TB2> INFO: Test took 220968ms.
[12:55:56.212] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 216 (-1/-1) hits flags = 528 (plus default)
[12:55:56.222] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:55:56.222] <TB2> INFO: run 1 of 1
[12:55:56.454] <TB2> INFO: Expecting 4513600 events.
[12:56:27.548] <TB2> INFO: 723330 events read in total (30503ms).
[12:56:57.810] <TB2> INFO: 1440955 events read in total (60765ms).
[12:57:28.269] <TB2> INFO: 2156245 events read in total (91224ms).
[12:57:58.584] <TB2> INFO: 2866210 events read in total (121539ms).
[12:58:29.112] <TB2> INFO: 3574330 events read in total (152067ms).
[12:58:59.766] <TB2> INFO: 4281730 events read in total (182721ms).
[12:59:09.800] <TB2> INFO: 4513600 events read in total (192755ms).
[12:59:09.869] <TB2> INFO: Test took 193648ms.
[12:59:36.055] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 218 (-1/-1) hits flags = 528 (plus default)
[12:59:36.065] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:59:36.065] <TB2> INFO: run 1 of 1
[12:59:36.314] <TB2> INFO: Expecting 4555200 events.
[13:00:07.525] <TB2> INFO: 721325 events read in total (30619ms).
[13:00:37.804] <TB2> INFO: 1437115 events read in total (60898ms).
[13:01:07.978] <TB2> INFO: 2150420 events read in total (91072ms).
[13:01:38.364] <TB2> INFO: 2858645 events read in total (121458ms).
[13:02:08.463] <TB2> INFO: 3565155 events read in total (151557ms).
[13:02:39.074] <TB2> INFO: 4270480 events read in total (182168ms).
[13:02:51.483] <TB2> INFO: 4555200 events read in total (194577ms).
[13:02:51.539] <TB2> INFO: Test took 195474ms.
[13:03:20.252] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 215 (-1/-1) hits flags = 528 (plus default)
[13:03:20.262] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:03:20.262] <TB2> INFO: run 1 of 1
[13:03:20.497] <TB2> INFO: Expecting 4492800 events.
[13:03:51.750] <TB2> INFO: 724785 events read in total (30662ms).
[13:04:22.233] <TB2> INFO: 1444250 events read in total (61145ms).
[13:04:52.546] <TB2> INFO: 2161435 events read in total (91458ms).
[13:05:22.939] <TB2> INFO: 2872710 events read in total (121851ms).
[13:05:53.457] <TB2> INFO: 3582110 events read in total (152369ms).
[13:06:24.140] <TB2> INFO: 4290880 events read in total (183052ms).
[13:06:33.098] <TB2> INFO: 4492800 events read in total (192010ms).
[13:06:33.169] <TB2> INFO: Test took 192908ms.
[13:07:01.720] <TB2> INFO: PixTestTrim::trimBitTest() done
[13:07:01.721] <TB2> INFO: PixTestTrim::doTest() done, duration: 2551 seconds
[13:07:01.721] <TB2> INFO: Decoding statistics:
[13:07:01.721] <TB2> INFO: General information:
[13:07:01.721] <TB2> INFO: 16bit words read: 0
[13:07:01.721] <TB2> INFO: valid events total: 0
[13:07:01.721] <TB2> INFO: empty events: 0
[13:07:01.721] <TB2> INFO: valid events with pixels: 0
[13:07:01.721] <TB2> INFO: valid pixel hits: 0
[13:07:01.721] <TB2> INFO: Event errors: 0
[13:07:01.721] <TB2> INFO: start marker: 0
[13:07:01.721] <TB2> INFO: stop marker: 0
[13:07:01.721] <TB2> INFO: overflow: 0
[13:07:01.721] <TB2> INFO: invalid 5bit words: 0
[13:07:01.721] <TB2> INFO: invalid XOR eye diagram: 0
[13:07:01.721] <TB2> INFO: frame (failed synchr.): 0
[13:07:01.721] <TB2> INFO: idle data (no TBM trl): 0
[13:07:01.721] <TB2> INFO: no data (only TBM hdr): 0
[13:07:01.721] <TB2> INFO: TBM errors: 0
[13:07:01.721] <TB2> INFO: flawed TBM headers: 0
[13:07:01.721] <TB2> INFO: flawed TBM trailers: 0
[13:07:01.721] <TB2> INFO: event ID mismatches: 0
[13:07:01.721] <TB2> INFO: ROC errors: 0
[13:07:01.721] <TB2> INFO: missing ROC header(s): 0
[13:07:01.721] <TB2> INFO: misplaced readback start: 0
[13:07:01.721] <TB2> INFO: Pixel decoding errors: 0
[13:07:01.721] <TB2> INFO: pixel data incomplete: 0
[13:07:01.721] <TB2> INFO: pixel address: 0
[13:07:01.721] <TB2> INFO: pulse height fill bit: 0
[13:07:01.721] <TB2> INFO: buffer corruption: 0
[13:07:02.345] <TB2> INFO: ######################################################################
[13:07:02.345] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:07:02.345] <TB2> INFO: ######################################################################
[13:07:02.580] <TB2> INFO: Expecting 41600 events.
[13:07:06.068] <TB2> INFO: 41600 events read in total (2897ms).
[13:07:06.068] <TB2> INFO: Test took 3722ms.
[13:07:06.509] <TB2> INFO: Expecting 41600 events.
[13:07:10.004] <TB2> INFO: 41600 events read in total (2903ms).
[13:07:10.005] <TB2> INFO: Test took 3735ms.
[13:07:10.301] <TB2> INFO: Expecting 41600 events.
[13:07:13.844] <TB2> INFO: 41600 events read in total (2951ms).
[13:07:13.845] <TB2> INFO: Test took 3814ms.
[13:07:14.141] <TB2> INFO: Expecting 41600 events.
[13:07:17.690] <TB2> INFO: 41600 events read in total (2958ms).
[13:07:17.691] <TB2> INFO: Test took 3823ms.
[13:07:17.982] <TB2> INFO: Expecting 41600 events.
[13:07:21.464] <TB2> INFO: 41600 events read in total (2891ms).
[13:07:21.464] <TB2> INFO: Test took 3747ms.
[13:07:21.753] <TB2> INFO: Expecting 41600 events.
[13:07:25.222] <TB2> INFO: 41600 events read in total (2878ms).
[13:07:25.222] <TB2> INFO: Test took 3734ms.
[13:07:25.511] <TB2> INFO: Expecting 41600 events.
[13:07:28.967] <TB2> INFO: 41600 events read in total (2864ms).
[13:07:28.968] <TB2> INFO: Test took 3722ms.
[13:07:29.261] <TB2> INFO: Expecting 41600 events.
[13:07:32.724] <TB2> INFO: 41600 events read in total (2872ms).
[13:07:32.725] <TB2> INFO: Test took 3729ms.
[13:07:33.016] <TB2> INFO: Expecting 41600 events.
[13:07:36.509] <TB2> INFO: 41600 events read in total (2902ms).
[13:07:36.509] <TB2> INFO: Test took 3758ms.
[13:07:36.800] <TB2> INFO: Expecting 41600 events.
[13:07:40.323] <TB2> INFO: 41600 events read in total (2931ms).
[13:07:40.324] <TB2> INFO: Test took 3791ms.
[13:07:40.612] <TB2> INFO: Expecting 41600 events.
[13:07:44.150] <TB2> INFO: 41600 events read in total (2947ms).
[13:07:44.151] <TB2> INFO: Test took 3804ms.
[13:07:44.439] <TB2> INFO: Expecting 41600 events.
[13:07:47.908] <TB2> INFO: 41600 events read in total (2877ms).
[13:07:47.909] <TB2> INFO: Test took 3734ms.
[13:07:48.199] <TB2> INFO: Expecting 41600 events.
[13:07:51.630] <TB2> INFO: 41600 events read in total (2839ms).
[13:07:51.631] <TB2> INFO: Test took 3696ms.
[13:07:51.920] <TB2> INFO: Expecting 41600 events.
[13:07:55.479] <TB2> INFO: 41600 events read in total (2961ms).
[13:07:55.480] <TB2> INFO: Test took 3825ms.
[13:07:55.778] <TB2> INFO: Expecting 41600 events.
[13:07:59.231] <TB2> INFO: 41600 events read in total (2862ms).
[13:07:59.231] <TB2> INFO: Test took 3727ms.
[13:07:59.527] <TB2> INFO: Expecting 41600 events.
[13:08:03.097] <TB2> INFO: 41600 events read in total (2975ms).
[13:08:03.098] <TB2> INFO: Test took 3841ms.
[13:08:03.390] <TB2> INFO: Expecting 41600 events.
[13:08:06.907] <TB2> INFO: 41600 events read in total (2925ms).
[13:08:06.908] <TB2> INFO: Test took 3783ms.
[13:08:07.196] <TB2> INFO: Expecting 41600 events.
[13:08:10.707] <TB2> INFO: 41600 events read in total (2919ms).
[13:08:10.708] <TB2> INFO: Test took 3777ms.
[13:08:11.022] <TB2> INFO: Expecting 41600 events.
[13:08:14.560] <TB2> INFO: 41600 events read in total (2946ms).
[13:08:14.561] <TB2> INFO: Test took 3829ms.
[13:08:14.852] <TB2> INFO: Expecting 41600 events.
[13:08:18.297] <TB2> INFO: 41600 events read in total (2853ms).
[13:08:18.298] <TB2> INFO: Test took 3711ms.
[13:08:18.586] <TB2> INFO: Expecting 41600 events.
[13:08:22.121] <TB2> INFO: 41600 events read in total (2944ms).
[13:08:22.122] <TB2> INFO: Test took 3801ms.
[13:08:22.413] <TB2> INFO: Expecting 41600 events.
[13:08:25.940] <TB2> INFO: 41600 events read in total (2936ms).
[13:08:25.941] <TB2> INFO: Test took 3793ms.
[13:08:26.229] <TB2> INFO: Expecting 41600 events.
[13:08:29.806] <TB2> INFO: 41600 events read in total (2985ms).
[13:08:29.807] <TB2> INFO: Test took 3842ms.
[13:08:30.098] <TB2> INFO: Expecting 41600 events.
[13:08:33.537] <TB2> INFO: 41600 events read in total (2847ms).
[13:08:33.538] <TB2> INFO: Test took 3705ms.
[13:08:33.827] <TB2> INFO: Expecting 41600 events.
[13:08:37.387] <TB2> INFO: 41600 events read in total (2969ms).
[13:08:37.388] <TB2> INFO: Test took 3826ms.
[13:08:37.676] <TB2> INFO: Expecting 41600 events.
[13:08:41.240] <TB2> INFO: 41600 events read in total (2972ms).
[13:08:41.241] <TB2> INFO: Test took 3830ms.
[13:08:41.532] <TB2> INFO: Expecting 41600 events.
[13:08:44.003] <TB2> INFO: 41600 events read in total (2879ms).
[13:08:45.004] <TB2> INFO: Test took 3740ms.
[13:08:45.304] <TB2> INFO: Expecting 41600 events.
[13:08:48.800] <TB2> INFO: 41600 events read in total (2904ms).
[13:08:48.801] <TB2> INFO: Test took 3773ms.
[13:08:49.090] <TB2> INFO: Expecting 2560 events.
[13:08:49.972] <TB2> INFO: 2560 events read in total (291ms).
[13:08:49.972] <TB2> INFO: Test took 1159ms.
[13:08:50.280] <TB2> INFO: Expecting 2560 events.
[13:08:51.165] <TB2> INFO: 2560 events read in total (293ms).
[13:08:51.166] <TB2> INFO: Test took 1194ms.
[13:08:51.474] <TB2> INFO: Expecting 2560 events.
[13:08:52.356] <TB2> INFO: 2560 events read in total (291ms).
[13:08:52.357] <TB2> INFO: Test took 1191ms.
[13:08:52.664] <TB2> INFO: Expecting 2560 events.
[13:08:53.547] <TB2> INFO: 2560 events read in total (291ms).
[13:08:53.547] <TB2> INFO: Test took 1190ms.
[13:08:53.855] <TB2> INFO: Expecting 2560 events.
[13:08:54.733] <TB2> INFO: 2560 events read in total (287ms).
[13:08:54.733] <TB2> INFO: Test took 1185ms.
[13:08:55.041] <TB2> INFO: Expecting 2560 events.
[13:08:55.920] <TB2> INFO: 2560 events read in total (287ms).
[13:08:55.920] <TB2> INFO: Test took 1187ms.
[13:08:56.228] <TB2> INFO: Expecting 2560 events.
[13:08:57.106] <TB2> INFO: 2560 events read in total (287ms).
[13:08:57.106] <TB2> INFO: Test took 1185ms.
[13:08:57.414] <TB2> INFO: Expecting 2560 events.
[13:08:58.292] <TB2> INFO: 2560 events read in total (287ms).
[13:08:58.292] <TB2> INFO: Test took 1186ms.
[13:08:58.600] <TB2> INFO: Expecting 2560 events.
[13:08:59.478] <TB2> INFO: 2560 events read in total (286ms).
[13:08:59.478] <TB2> INFO: Test took 1185ms.
[13:08:59.786] <TB2> INFO: Expecting 2560 events.
[13:09:00.668] <TB2> INFO: 2560 events read in total (290ms).
[13:09:00.669] <TB2> INFO: Test took 1191ms.
[13:09:00.976] <TB2> INFO: Expecting 2560 events.
[13:09:01.853] <TB2> INFO: 2560 events read in total (285ms).
[13:09:01.853] <TB2> INFO: Test took 1184ms.
[13:09:02.161] <TB2> INFO: Expecting 2560 events.
[13:09:03.040] <TB2> INFO: 2560 events read in total (287ms).
[13:09:03.040] <TB2> INFO: Test took 1186ms.
[13:09:03.347] <TB2> INFO: Expecting 2560 events.
[13:09:04.231] <TB2> INFO: 2560 events read in total (292ms).
[13:09:04.232] <TB2> INFO: Test took 1192ms.
[13:09:04.539] <TB2> INFO: Expecting 2560 events.
[13:09:05.424] <TB2> INFO: 2560 events read in total (293ms).
[13:09:05.424] <TB2> INFO: Test took 1192ms.
[13:09:05.732] <TB2> INFO: Expecting 2560 events.
[13:09:06.617] <TB2> INFO: 2560 events read in total (293ms).
[13:09:06.617] <TB2> INFO: Test took 1192ms.
[13:09:06.925] <TB2> INFO: Expecting 2560 events.
[13:09:07.808] <TB2> INFO: 2560 events read in total (291ms).
[13:09:07.808] <TB2> INFO: Test took 1190ms.
[13:09:07.811] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:09:08.117] <TB2> INFO: Expecting 655360 events.
[13:09:22.472] <TB2> INFO: 655360 events read in total (13764ms).
[13:09:22.483] <TB2> INFO: Expecting 655360 events.
[13:09:36.715] <TB2> INFO: 655360 events read in total (13829ms).
[13:09:36.734] <TB2> INFO: Expecting 655360 events.
[13:09:50.809] <TB2> INFO: 655360 events read in total (13672ms).
[13:09:50.827] <TB2> INFO: Expecting 655360 events.
[13:10:04.951] <TB2> INFO: 655360 events read in total (13721ms).
[13:10:04.984] <TB2> INFO: Expecting 655360 events.
[13:10:19.047] <TB2> INFO: 655360 events read in total (13660ms).
[13:10:19.083] <TB2> INFO: Expecting 655360 events.
[13:10:33.128] <TB2> INFO: 655360 events read in total (13642ms).
[13:10:33.159] <TB2> INFO: Expecting 655360 events.
[13:10:47.171] <TB2> INFO: 655360 events read in total (13609ms).
[13:10:47.218] <TB2> INFO: Expecting 655360 events.
[13:11:01.227] <TB2> INFO: 655360 events read in total (13606ms).
[13:11:01.265] <TB2> INFO: Expecting 655360 events.
[13:11:15.393] <TB2> INFO: 655360 events read in total (13725ms).
[13:11:15.439] <TB2> INFO: Expecting 655360 events.
[13:11:29.509] <TB2> INFO: 655360 events read in total (13667ms).
[13:11:29.558] <TB2> INFO: Expecting 655360 events.
[13:11:43.611] <TB2> INFO: 655360 events read in total (13650ms).
[13:11:43.665] <TB2> INFO: Expecting 655360 events.
[13:11:57.768] <TB2> INFO: 655360 events read in total (13700ms).
[13:11:57.845] <TB2> INFO: Expecting 655360 events.
[13:12:11.970] <TB2> INFO: 655360 events read in total (13722ms).
[13:12:12.032] <TB2> INFO: Expecting 655360 events.
[13:12:25.690] <TB2> INFO: 634710 events read in total (13255ms).
[13:12:26.352] <TB2> INFO: 655360 events read in total (13917ms).
[13:12:26.416] <TB2> INFO: Expecting 655360 events.
[13:12:40.454] <TB2> INFO: 655360 events read in total (13629ms).
[13:12:40.547] <TB2> INFO: Expecting 655360 events.
[13:12:54.613] <TB2> INFO: 655360 events read in total (13663ms).
[13:12:54.688] <TB2> INFO: Test took 226877ms.
[13:12:54.768] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:12:55.033] <TB2> INFO: Expecting 655360 events.
[13:13:09.129] <TB2> INFO: 655360 events read in total (13505ms).
[13:13:09.140] <TB2> INFO: Expecting 655360 events.
[13:13:22.713] <TB2> INFO: 655360 events read in total (13170ms).
[13:13:22.732] <TB2> INFO: Expecting 655360 events.
[13:13:36.696] <TB2> INFO: 655360 events read in total (13561ms).
[13:13:36.722] <TB2> INFO: Expecting 655360 events.
[13:13:50.682] <TB2> INFO: 655360 events read in total (13557ms).
[13:13:50.715] <TB2> INFO: Expecting 655360 events.
[13:14:04.683] <TB2> INFO: 655360 events read in total (13561ms).
[13:14:04.710] <TB2> INFO: Expecting 655360 events.
[13:14:18.633] <TB2> INFO: 655360 events read in total (13520ms).
[13:14:18.675] <TB2> INFO: Expecting 655360 events.
[13:14:32.555] <TB2> INFO: 655360 events read in total (13477ms).
[13:14:32.591] <TB2> INFO: Expecting 655360 events.
[13:14:46.571] <TB2> INFO: 655360 events read in total (13577ms).
[13:14:46.610] <TB2> INFO: Expecting 655360 events.
[13:15:00.537] <TB2> INFO: 655360 events read in total (13524ms).
[13:15:00.582] <TB2> INFO: Expecting 655360 events.
[13:15:14.436] <TB2> INFO: 655360 events read in total (13451ms).
[13:15:14.485] <TB2> INFO: Expecting 655360 events.
[13:15:28.429] <TB2> INFO: 655360 events read in total (13542ms).
[13:15:28.484] <TB2> INFO: Expecting 655360 events.
[13:15:42.174] <TB2> INFO: 655360 events read in total (13287ms).
[13:15:42.233] <TB2> INFO: Expecting 655360 events.
[13:15:56.326] <TB2> INFO: 655360 events read in total (13690ms).
[13:15:56.410] <TB2> INFO: Expecting 655360 events.
[13:16:10.398] <TB2> INFO: 655360 events read in total (13585ms).
[13:16:10.462] <TB2> INFO: Expecting 655360 events.
[13:16:24.580] <TB2> INFO: 655360 events read in total (13715ms).
[13:16:24.653] <TB2> INFO: Expecting 655360 events.
[13:16:38.324] <TB2> INFO: 655360 events read in total (13268ms).
[13:16:38.402] <TB2> INFO: Test took 223634ms.
[13:16:38.643] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.650] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.658] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.665] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.673] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:16:38.681] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:16:38.687] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.692] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:16:38.697] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:16:38.702] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.707] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:16:38.712] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.717] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:16:38.721] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:16:38.726] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.731] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.737] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.742] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.748] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.753] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.757] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:16:38.762] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:16:38.767] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:16:38.772] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:16:38.777] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.781] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.786] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:16:38.791] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:16:38.796] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:16:38.800] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:16:38.806] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:16:38.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C0.dat
[13:16:38.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C1.dat
[13:16:38.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C2.dat
[13:16:38.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C3.dat
[13:16:38.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C4.dat
[13:16:38.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C5.dat
[13:16:38.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C6.dat
[13:16:38.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C7.dat
[13:16:38.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C8.dat
[13:16:38.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C9.dat
[13:16:38.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C10.dat
[13:16:38.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C11.dat
[13:16:38.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C12.dat
[13:16:38.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C13.dat
[13:16:38.842] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C14.dat
[13:16:38.842] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C15.dat
[13:16:39.076] <TB2> INFO: Expecting 41600 events.
[13:16:42.177] <TB2> INFO: 41600 events read in total (2510ms).
[13:16:42.178] <TB2> INFO: Test took 3334ms.
[13:16:42.620] <TB2> INFO: Expecting 41600 events.
[13:16:45.627] <TB2> INFO: 41600 events read in total (2415ms).
[13:16:45.628] <TB2> INFO: Test took 3240ms.
[13:16:46.075] <TB2> INFO: Expecting 41600 events.
[13:16:49.154] <TB2> INFO: 41600 events read in total (2488ms).
[13:16:49.155] <TB2> INFO: Test took 3316ms.
[13:16:49.369] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:49.458] <TB2> INFO: Expecting 2560 events.
[13:16:50.340] <TB2> INFO: 2560 events read in total (291ms).
[13:16:50.341] <TB2> INFO: Test took 972ms.
[13:16:50.343] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:50.649] <TB2> INFO: Expecting 2560 events.
[13:16:51.531] <TB2> INFO: 2560 events read in total (291ms).
[13:16:51.532] <TB2> INFO: Test took 1189ms.
[13:16:51.533] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:51.840] <TB2> INFO: Expecting 2560 events.
[13:16:52.723] <TB2> INFO: 2560 events read in total (292ms).
[13:16:52.723] <TB2> INFO: Test took 1190ms.
[13:16:52.725] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:53.031] <TB2> INFO: Expecting 2560 events.
[13:16:53.913] <TB2> INFO: 2560 events read in total (290ms).
[13:16:53.914] <TB2> INFO: Test took 1189ms.
[13:16:53.915] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:54.222] <TB2> INFO: Expecting 2560 events.
[13:16:55.109] <TB2> INFO: 2560 events read in total (295ms).
[13:16:55.109] <TB2> INFO: Test took 1194ms.
[13:16:55.111] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:55.417] <TB2> INFO: Expecting 2560 events.
[13:16:56.304] <TB2> INFO: 2560 events read in total (295ms).
[13:16:56.304] <TB2> INFO: Test took 1194ms.
[13:16:56.306] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:56.613] <TB2> INFO: Expecting 2560 events.
[13:16:57.502] <TB2> INFO: 2560 events read in total (298ms).
[13:16:57.502] <TB2> INFO: Test took 1196ms.
[13:16:57.504] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:57.810] <TB2> INFO: Expecting 2560 events.
[13:16:58.696] <TB2> INFO: 2560 events read in total (294ms).
[13:16:58.696] <TB2> INFO: Test took 1192ms.
[13:16:58.698] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:59.004] <TB2> INFO: Expecting 2560 events.
[13:16:59.883] <TB2> INFO: 2560 events read in total (287ms).
[13:16:59.883] <TB2> INFO: Test took 1185ms.
[13:16:59.885] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:00.191] <TB2> INFO: Expecting 2560 events.
[13:17:01.069] <TB2> INFO: 2560 events read in total (286ms).
[13:17:01.070] <TB2> INFO: Test took 1185ms.
[13:17:01.072] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:01.378] <TB2> INFO: Expecting 2560 events.
[13:17:02.257] <TB2> INFO: 2560 events read in total (288ms).
[13:17:02.258] <TB2> INFO: Test took 1187ms.
[13:17:02.260] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:02.566] <TB2> INFO: Expecting 2560 events.
[13:17:03.443] <TB2> INFO: 2560 events read in total (286ms).
[13:17:03.444] <TB2> INFO: Test took 1184ms.
[13:17:03.446] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:03.752] <TB2> INFO: Expecting 2560 events.
[13:17:04.630] <TB2> INFO: 2560 events read in total (286ms).
[13:17:04.630] <TB2> INFO: Test took 1184ms.
[13:17:04.632] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:04.939] <TB2> INFO: Expecting 2560 events.
[13:17:05.820] <TB2> INFO: 2560 events read in total (290ms).
[13:17:05.820] <TB2> INFO: Test took 1188ms.
[13:17:05.822] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:06.128] <TB2> INFO: Expecting 2560 events.
[13:17:07.009] <TB2> INFO: 2560 events read in total (289ms).
[13:17:07.010] <TB2> INFO: Test took 1189ms.
[13:17:07.012] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:07.317] <TB2> INFO: Expecting 2560 events.
[13:17:08.197] <TB2> INFO: 2560 events read in total (288ms).
[13:17:08.197] <TB2> INFO: Test took 1185ms.
[13:17:08.199] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:08.505] <TB2> INFO: Expecting 2560 events.
[13:17:09.384] <TB2> INFO: 2560 events read in total (287ms).
[13:17:09.384] <TB2> INFO: Test took 1185ms.
[13:17:09.386] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:09.692] <TB2> INFO: Expecting 2560 events.
[13:17:10.572] <TB2> INFO: 2560 events read in total (288ms).
[13:17:10.572] <TB2> INFO: Test took 1186ms.
[13:17:10.574] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:10.880] <TB2> INFO: Expecting 2560 events.
[13:17:11.759] <TB2> INFO: 2560 events read in total (287ms).
[13:17:11.759] <TB2> INFO: Test took 1185ms.
[13:17:11.761] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:12.067] <TB2> INFO: Expecting 2560 events.
[13:17:12.946] <TB2> INFO: 2560 events read in total (287ms).
[13:17:12.946] <TB2> INFO: Test took 1185ms.
[13:17:12.948] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:13.255] <TB2> INFO: Expecting 2560 events.
[13:17:14.133] <TB2> INFO: 2560 events read in total (287ms).
[13:17:14.133] <TB2> INFO: Test took 1185ms.
[13:17:14.135] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:14.442] <TB2> INFO: Expecting 2560 events.
[13:17:15.321] <TB2> INFO: 2560 events read in total (288ms).
[13:17:15.321] <TB2> INFO: Test took 1186ms.
[13:17:15.323] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:15.629] <TB2> INFO: Expecting 2560 events.
[13:17:16.508] <TB2> INFO: 2560 events read in total (287ms).
[13:17:16.508] <TB2> INFO: Test took 1185ms.
[13:17:16.510] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:16.816] <TB2> INFO: Expecting 2560 events.
[13:17:17.695] <TB2> INFO: 2560 events read in total (287ms).
[13:17:17.695] <TB2> INFO: Test took 1185ms.
[13:17:17.698] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:18.003] <TB2> INFO: Expecting 2560 events.
[13:17:18.886] <TB2> INFO: 2560 events read in total (291ms).
[13:17:18.886] <TB2> INFO: Test took 1188ms.
[13:17:18.889] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:19.194] <TB2> INFO: Expecting 2560 events.
[13:17:20.076] <TB2> INFO: 2560 events read in total (291ms).
[13:17:20.076] <TB2> INFO: Test took 1187ms.
[13:17:20.078] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:20.385] <TB2> INFO: Expecting 2560 events.
[13:17:21.271] <TB2> INFO: 2560 events read in total (295ms).
[13:17:21.271] <TB2> INFO: Test took 1193ms.
[13:17:21.273] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:21.579] <TB2> INFO: Expecting 2560 events.
[13:17:22.465] <TB2> INFO: 2560 events read in total (294ms).
[13:17:22.465] <TB2> INFO: Test took 1192ms.
[13:17:22.467] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:22.773] <TB2> INFO: Expecting 2560 events.
[13:17:23.658] <TB2> INFO: 2560 events read in total (293ms).
[13:17:23.659] <TB2> INFO: Test took 1192ms.
[13:17:23.661] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:23.967] <TB2> INFO: Expecting 2560 events.
[13:17:24.853] <TB2> INFO: 2560 events read in total (294ms).
[13:17:24.853] <TB2> INFO: Test took 1192ms.
[13:17:24.855] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:25.162] <TB2> INFO: Expecting 2560 events.
[13:17:26.049] <TB2> INFO: 2560 events read in total (295ms).
[13:17:26.049] <TB2> INFO: Test took 1194ms.
[13:17:26.051] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:17:26.358] <TB2> INFO: Expecting 2560 events.
[13:17:27.245] <TB2> INFO: 2560 events read in total (295ms).
[13:17:27.245] <TB2> INFO: Test took 1194ms.
[13:17:27.717] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 625 seconds
[13:17:27.717] <TB2> INFO: PH scale (per ROC): 29 54 32 37 35 59 48 41 32 37 42 40 43 48 49 36
[13:17:27.717] <TB2> INFO: PH offset (per ROC): 105 124 98 99 100 124 134 97 96 107 97 105 83 118 97 95
[13:17:27.723] <TB2> INFO: Decoding statistics:
[13:17:27.723] <TB2> INFO: General information:
[13:17:27.723] <TB2> INFO: 16bit words read: 127890
[13:17:27.723] <TB2> INFO: valid events total: 20480
[13:17:27.723] <TB2> INFO: empty events: 17975
[13:17:27.723] <TB2> INFO: valid events with pixels: 2505
[13:17:27.723] <TB2> INFO: valid pixel hits: 2505
[13:17:27.723] <TB2> INFO: Event errors: 0
[13:17:27.723] <TB2> INFO: start marker: 0
[13:17:27.723] <TB2> INFO: stop marker: 0
[13:17:27.723] <TB2> INFO: overflow: 0
[13:17:27.723] <TB2> INFO: invalid 5bit words: 0
[13:17:27.723] <TB2> INFO: invalid XOR eye diagram: 0
[13:17:27.723] <TB2> INFO: frame (failed synchr.): 0
[13:17:27.723] <TB2> INFO: idle data (no TBM trl): 0
[13:17:27.724] <TB2> INFO: no data (only TBM hdr): 0
[13:17:27.724] <TB2> INFO: TBM errors: 0
[13:17:27.724] <TB2> INFO: flawed TBM headers: 0
[13:17:27.724] <TB2> INFO: flawed TBM trailers: 0
[13:17:27.724] <TB2> INFO: event ID mismatches: 0
[13:17:27.724] <TB2> INFO: ROC errors: 0
[13:17:27.724] <TB2> INFO: missing ROC header(s): 0
[13:17:27.724] <TB2> INFO: misplaced readback start: 0
[13:17:27.724] <TB2> INFO: Pixel decoding errors: 0
[13:17:27.724] <TB2> INFO: pixel data incomplete: 0
[13:17:27.724] <TB2> INFO: pixel address: 0
[13:17:27.724] <TB2> INFO: pulse height fill bit: 0
[13:17:27.724] <TB2> INFO: buffer corruption: 0
[13:17:28.045] <TB2> INFO: ######################################################################
[13:17:28.045] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:17:28.045] <TB2> INFO: ######################################################################
[13:17:28.058] <TB2> INFO: scanning low vcal = 10
[13:17:28.291] <TB2> INFO: Expecting 41600 events.
[13:17:31.874] <TB2> INFO: 41600 events read in total (2992ms).
[13:17:31.874] <TB2> INFO: Test took 3816ms.
[13:17:31.876] <TB2> INFO: scanning low vcal = 20
[13:17:32.172] <TB2> INFO: Expecting 41600 events.
[13:17:35.749] <TB2> INFO: 41600 events read in total (2985ms).
[13:17:35.749] <TB2> INFO: Test took 3873ms.
[13:17:35.751] <TB2> INFO: scanning low vcal = 30
[13:17:36.047] <TB2> INFO: Expecting 41600 events.
[13:17:39.684] <TB2> INFO: 41600 events read in total (3045ms).
[13:17:39.685] <TB2> INFO: Test took 3934ms.
[13:17:39.687] <TB2> INFO: scanning low vcal = 40
[13:17:39.966] <TB2> INFO: Expecting 41600 events.
[13:17:43.882] <TB2> INFO: 41600 events read in total (3324ms).
[13:17:43.883] <TB2> INFO: Test took 4196ms.
[13:17:43.885] <TB2> INFO: scanning low vcal = 50
[13:17:44.164] <TB2> INFO: Expecting 41600 events.
[13:17:48.123] <TB2> INFO: 41600 events read in total (3367ms).
[13:17:48.124] <TB2> INFO: Test took 4239ms.
[13:17:48.126] <TB2> INFO: scanning low vcal = 60
[13:17:48.403] <TB2> INFO: Expecting 41600 events.
[13:17:52.379] <TB2> INFO: 41600 events read in total (3384ms).
[13:17:52.380] <TB2> INFO: Test took 4254ms.
[13:17:52.382] <TB2> INFO: scanning low vcal = 70
[13:17:52.659] <TB2> INFO: Expecting 41600 events.
[13:17:56.613] <TB2> INFO: 41600 events read in total (3362ms).
[13:17:56.613] <TB2> INFO: Test took 4230ms.
[13:17:56.616] <TB2> INFO: scanning low vcal = 80
[13:17:56.893] <TB2> INFO: Expecting 41600 events.
[13:18:00.817] <TB2> INFO: 41600 events read in total (3333ms).
[13:18:00.818] <TB2> INFO: Test took 4202ms.
[13:18:00.820] <TB2> INFO: scanning low vcal = 90
[13:18:01.097] <TB2> INFO: Expecting 41600 events.
[13:18:05.055] <TB2> INFO: 41600 events read in total (3366ms).
[13:18:05.056] <TB2> INFO: Test took 4235ms.
[13:18:05.059] <TB2> INFO: scanning low vcal = 100
[13:18:05.335] <TB2> INFO: Expecting 41600 events.
[13:18:09.293] <TB2> INFO: 41600 events read in total (3366ms).
[13:18:09.293] <TB2> INFO: Test took 4234ms.
[13:18:09.296] <TB2> INFO: scanning low vcal = 110
[13:18:09.573] <TB2> INFO: Expecting 41600 events.
[13:18:13.496] <TB2> INFO: 41600 events read in total (3332ms).
[13:18:13.496] <TB2> INFO: Test took 4200ms.
[13:18:13.499] <TB2> INFO: scanning low vcal = 120
[13:18:13.775] <TB2> INFO: Expecting 41600 events.
[13:18:17.698] <TB2> INFO: 41600 events read in total (3331ms).
[13:18:17.699] <TB2> INFO: Test took 4200ms.
[13:18:17.702] <TB2> INFO: scanning low vcal = 130
[13:18:17.978] <TB2> INFO: Expecting 41600 events.
[13:18:21.928] <TB2> INFO: 41600 events read in total (3358ms).
[13:18:21.929] <TB2> INFO: Test took 4227ms.
[13:18:21.931] <TB2> INFO: scanning low vcal = 140
[13:18:22.208] <TB2> INFO: Expecting 41600 events.
[13:18:26.170] <TB2> INFO: 41600 events read in total (3371ms).
[13:18:26.171] <TB2> INFO: Test took 4240ms.
[13:18:26.173] <TB2> INFO: scanning low vcal = 150
[13:18:26.450] <TB2> INFO: Expecting 41600 events.
[13:18:30.374] <TB2> INFO: 41600 events read in total (3332ms).
[13:18:30.375] <TB2> INFO: Test took 4201ms.
[13:18:30.377] <TB2> INFO: scanning low vcal = 160
[13:18:30.654] <TB2> INFO: Expecting 41600 events.
[13:18:34.605] <TB2> INFO: 41600 events read in total (3359ms).
[13:18:34.606] <TB2> INFO: Test took 4229ms.
[13:18:34.609] <TB2> INFO: scanning low vcal = 170
[13:18:34.886] <TB2> INFO: Expecting 41600 events.
[13:18:38.820] <TB2> INFO: 41600 events read in total (3343ms).
[13:18:38.821] <TB2> INFO: Test took 4212ms.
[13:18:38.824] <TB2> INFO: scanning low vcal = 180
[13:18:39.101] <TB2> INFO: Expecting 41600 events.
[13:18:43.059] <TB2> INFO: 41600 events read in total (3364ms).
[13:18:43.060] <TB2> INFO: Test took 4236ms.
[13:18:43.063] <TB2> INFO: scanning low vcal = 190
[13:18:43.340] <TB2> INFO: Expecting 41600 events.
[13:18:47.286] <TB2> INFO: 41600 events read in total (3355ms).
[13:18:47.287] <TB2> INFO: Test took 4224ms.
[13:18:47.289] <TB2> INFO: scanning low vcal = 200
[13:18:47.566] <TB2> INFO: Expecting 41600 events.
[13:18:51.513] <TB2> INFO: 41600 events read in total (3355ms).
[13:18:51.514] <TB2> INFO: Test took 4224ms.
[13:18:51.516] <TB2> INFO: scanning low vcal = 210
[13:18:51.793] <TB2> INFO: Expecting 41600 events.
[13:18:55.749] <TB2> INFO: 41600 events read in total (3364ms).
[13:18:55.751] <TB2> INFO: Test took 4234ms.
[13:18:55.753] <TB2> INFO: scanning low vcal = 220
[13:18:56.030] <TB2> INFO: Expecting 41600 events.
[13:18:59.989] <TB2> INFO: 41600 events read in total (3368ms).
[13:18:59.990] <TB2> INFO: Test took 4237ms.
[13:18:59.993] <TB2> INFO: scanning low vcal = 230
[13:19:00.269] <TB2> INFO: Expecting 41600 events.
[13:19:04.219] <TB2> INFO: 41600 events read in total (3358ms).
[13:19:04.220] <TB2> INFO: Test took 4227ms.
[13:19:04.222] <TB2> INFO: scanning low vcal = 240
[13:19:04.499] <TB2> INFO: Expecting 41600 events.
[13:19:08.431] <TB2> INFO: 41600 events read in total (3340ms).
[13:19:08.432] <TB2> INFO: Test took 4210ms.
[13:19:08.434] <TB2> INFO: scanning low vcal = 250
[13:19:08.711] <TB2> INFO: Expecting 41600 events.
[13:19:12.653] <TB2> INFO: 41600 events read in total (3350ms).
[13:19:12.654] <TB2> INFO: Test took 4219ms.
[13:19:12.658] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[13:19:12.934] <TB2> INFO: Expecting 41600 events.
[13:19:16.883] <TB2> INFO: 41600 events read in total (3358ms).
[13:19:16.883] <TB2> INFO: Test took 4225ms.
[13:19:16.886] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[13:19:17.163] <TB2> INFO: Expecting 41600 events.
[13:19:21.101] <TB2> INFO: 41600 events read in total (3347ms).
[13:19:21.102] <TB2> INFO: Test took 4216ms.
[13:19:21.105] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[13:19:21.382] <TB2> INFO: Expecting 41600 events.
[13:19:25.338] <TB2> INFO: 41600 events read in total (3365ms).
[13:19:25.339] <TB2> INFO: Test took 4234ms.
[13:19:25.341] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[13:19:25.618] <TB2> INFO: Expecting 41600 events.
[13:19:29.541] <TB2> INFO: 41600 events read in total (3331ms).
[13:19:29.542] <TB2> INFO: Test took 4201ms.
[13:19:29.545] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:19:29.821] <TB2> INFO: Expecting 41600 events.
[13:19:33.761] <TB2> INFO: 41600 events read in total (3348ms).
[13:19:33.762] <TB2> INFO: Test took 4217ms.
[13:19:34.322] <TB2> INFO: PixTestGainPedestal::measure() done
[13:20:10.848] <TB2> INFO: PixTestGainPedestal::fit() done
[13:20:10.848] <TB2> INFO: non-linearity mean: 0.958 0.983 0.934 0.937 0.916 0.987 0.980 0.921 0.957 0.930 0.948 0.935 0.962 0.982 0.974 0.934
[13:20:10.848] <TB2> INFO: non-linearity RMS: 0.194 0.003 0.179 0.139 0.152 0.002 0.004 0.122 0.148 0.084 0.071 0.090 0.030 0.005 0.011 0.130
[13:20:10.848] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[13:20:10.862] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[13:20:10.875] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[13:20:10.889] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[13:20:10.904] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[13:20:10.917] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[13:20:10.931] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[13:20:10.945] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[13:20:10.959] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[13:20:10.972] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[13:20:10.986] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[13:20:10.999] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[13:20:11.013] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[13:20:11.027] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[13:20:11.041] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[13:20:11.054] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[13:20:11.068] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 163 seconds
[13:20:11.068] <TB2> INFO: Decoding statistics:
[13:20:11.068] <TB2> INFO: General information:
[13:20:11.068] <TB2> INFO: 16bit words read: 3298416
[13:20:11.068] <TB2> INFO: valid events total: 332800
[13:20:11.068] <TB2> INFO: empty events: 923
[13:20:11.068] <TB2> INFO: valid events with pixels: 331877
[13:20:11.068] <TB2> INFO: valid pixel hits: 650808
[13:20:11.068] <TB2> INFO: Event errors: 0
[13:20:11.068] <TB2> INFO: start marker: 0
[13:20:11.068] <TB2> INFO: stop marker: 0
[13:20:11.068] <TB2> INFO: overflow: 0
[13:20:11.068] <TB2> INFO: invalid 5bit words: 0
[13:20:11.068] <TB2> INFO: invalid XOR eye diagram: 0
[13:20:11.068] <TB2> INFO: frame (failed synchr.): 0
[13:20:11.068] <TB2> INFO: idle data (no TBM trl): 0
[13:20:11.068] <TB2> INFO: no data (only TBM hdr): 0
[13:20:11.068] <TB2> INFO: TBM errors: 0
[13:20:11.068] <TB2> INFO: flawed TBM headers: 0
[13:20:11.068] <TB2> INFO: flawed TBM trailers: 0
[13:20:11.068] <TB2> INFO: event ID mismatches: 0
[13:20:11.068] <TB2> INFO: ROC errors: 0
[13:20:11.068] <TB2> INFO: missing ROC header(s): 0
[13:20:11.068] <TB2> INFO: misplaced readback start: 0
[13:20:11.068] <TB2> INFO: Pixel decoding errors: 0
[13:20:11.068] <TB2> INFO: pixel data incomplete: 0
[13:20:11.068] <TB2> INFO: pixel address: 0
[13:20:11.068] <TB2> INFO: pulse height fill bit: 0
[13:20:11.068] <TB2> INFO: buffer corruption: 0
[13:20:11.083] <TB2> INFO: Decoding statistics:
[13:20:11.083] <TB2> INFO: General information:
[13:20:11.083] <TB2> INFO: 16bit words read: 3427842
[13:20:11.083] <TB2> INFO: valid events total: 353536
[13:20:11.083] <TB2> INFO: empty events: 19154
[13:20:11.083] <TB2> INFO: valid events with pixels: 334382
[13:20:11.083] <TB2> INFO: valid pixel hits: 653313
[13:20:11.083] <TB2> INFO: Event errors: 0
[13:20:11.083] <TB2> INFO: start marker: 0
[13:20:11.083] <TB2> INFO: stop marker: 0
[13:20:11.083] <TB2> INFO: overflow: 0
[13:20:11.083] <TB2> INFO: invalid 5bit words: 0
[13:20:11.083] <TB2> INFO: invalid XOR eye diagram: 0
[13:20:11.083] <TB2> INFO: frame (failed synchr.): 0
[13:20:11.083] <TB2> INFO: idle data (no TBM trl): 0
[13:20:11.083] <TB2> INFO: no data (only TBM hdr): 0
[13:20:11.083] <TB2> INFO: TBM errors: 0
[13:20:11.083] <TB2> INFO: flawed TBM headers: 0
[13:20:11.083] <TB2> INFO: flawed TBM trailers: 0
[13:20:11.083] <TB2> INFO: event ID mismatches: 0
[13:20:11.083] <TB2> INFO: ROC errors: 0
[13:20:11.083] <TB2> INFO: missing ROC header(s): 0
[13:20:11.083] <TB2> INFO: misplaced readback start: 0
[13:20:11.083] <TB2> INFO: Pixel decoding errors: 0
[13:20:11.083] <TB2> INFO: pixel data incomplete: 0
[13:20:11.083] <TB2> INFO: pixel address: 0
[13:20:11.083] <TB2> INFO: pulse height fill bit: 0
[13:20:11.083] <TB2> INFO: buffer corruption: 0
[13:20:11.083] <TB2> INFO: enter test to run
[13:20:11.083] <TB2> INFO: test: Trim80 no parameter change
[13:20:11.083] <TB2> INFO: running: trim80
[13:20:11.098] <TB2> INFO: ######################################################################
[13:20:11.099] <TB2> INFO: PixTestTrim80::doTest()
[13:20:11.099] <TB2> INFO: ######################################################################
[13:20:11.100] <TB2> INFO: ----------------------------------------------------------------------
[13:20:11.100] <TB2> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[13:20:11.100] <TB2> INFO: ----------------------------------------------------------------------
[13:20:11.140] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:20:11.140] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:20:11.149] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:20:11.149] <TB2> INFO: run 1 of 1
[13:20:11.397] <TB2> INFO: Expecting 5025280 events.
[13:20:39.082] <TB2> INFO: 685432 events read in total (27093ms).
[13:21:06.399] <TB2> INFO: 1368368 events read in total (54410ms).
[13:21:33.429] <TB2> INFO: 2049552 events read in total (81440ms).
[13:22:00.710] <TB2> INFO: 2727832 events read in total (108721ms).
[13:22:27.862] <TB2> INFO: 3405512 events read in total (135873ms).
[13:22:54.970] <TB2> INFO: 4082256 events read in total (162981ms).
[13:23:21.738] <TB2> INFO: 4757656 events read in total (189749ms).
[13:23:32.553] <TB2> INFO: 5025280 events read in total (200564ms).
[13:23:32.630] <TB2> INFO: Test took 201481ms.
[13:23:55.005] <TB2> INFO: ROC 0 VthrComp = 78
[13:23:55.006] <TB2> INFO: ROC 1 VthrComp = 96
[13:23:55.006] <TB2> INFO: ROC 2 VthrComp = 79
[13:23:55.006] <TB2> INFO: ROC 3 VthrComp = 73
[13:23:55.006] <TB2> INFO: ROC 4 VthrComp = 76
[13:23:55.006] <TB2> INFO: ROC 5 VthrComp = 80
[13:23:55.006] <TB2> INFO: ROC 6 VthrComp = 75
[13:23:55.006] <TB2> INFO: ROC 7 VthrComp = 79
[13:23:55.006] <TB2> INFO: ROC 8 VthrComp = 74
[13:23:55.007] <TB2> INFO: ROC 9 VthrComp = 80
[13:23:55.007] <TB2> INFO: ROC 10 VthrComp = 72
[13:23:55.007] <TB2> INFO: ROC 11 VthrComp = 88
[13:23:55.007] <TB2> INFO: ROC 12 VthrComp = 65
[13:23:55.007] <TB2> INFO: ROC 13 VthrComp = 78
[13:23:55.007] <TB2> INFO: ROC 14 VthrComp = 74
[13:23:55.007] <TB2> INFO: ROC 15 VthrComp = 82
[13:23:55.244] <TB2> INFO: Expecting 41600 events.
[13:23:58.643] <TB2> INFO: 41600 events read in total (2807ms).
[13:23:58.644] <TB2> INFO: Test took 3636ms.
[13:23:58.653] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:23:58.653] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:23:58.662] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:23:58.662] <TB2> INFO: run 1 of 1
[13:23:58.940] <TB2> INFO: Expecting 5025280 events.
[13:24:26.872] <TB2> INFO: 689256 events read in total (27341ms).
[13:24:54.182] <TB2> INFO: 1373464 events read in total (54651ms).
[13:25:21.283] <TB2> INFO: 2057416 events read in total (81752ms).
[13:25:48.543] <TB2> INFO: 2737576 events read in total (109012ms).
[13:26:15.533] <TB2> INFO: 3414768 events read in total (136002ms).
[13:26:42.489] <TB2> INFO: 4091016 events read in total (162958ms).
[13:27:09.133] <TB2> INFO: 4767968 events read in total (189602ms).
[13:27:19.489] <TB2> INFO: 5025280 events read in total (199958ms).
[13:27:19.534] <TB2> INFO: Test took 200872ms.
[13:27:44.579] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 111.633 for pixel 0/38 mean/min/max = 94.5476/77.3877/111.707
[13:27:44.580] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 109.427 for pixel 50/0 mean/min/max = 91.7831/74.1304/109.436
[13:27:44.580] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 110.623 for pixel 11/67 mean/min/max = 94.7002/78.7499/110.65
[13:27:44.581] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 111.076 for pixel 0/35 mean/min/max = 94.383/77.6118/111.154
[13:27:44.581] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 108.957 for pixel 0/6 mean/min/max = 93.9141/78.7039/109.124
[13:27:44.582] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 107.548 for pixel 14/2 mean/min/max = 91.7396/75.699/107.78
[13:27:44.582] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 110.42 for pixel 51/48 mean/min/max = 94.035/77.5922/110.478
[13:27:44.582] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 109.208 for pixel 0/13 mean/min/max = 93.5663/77.5988/109.534
[13:27:44.583] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 110.737 for pixel 4/10 mean/min/max = 94.7068/78.6638/110.75
[13:27:44.583] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 110.423 for pixel 42/79 mean/min/max = 92.8747/75.3114/110.438
[13:27:44.584] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 112.708 for pixel 0/40 mean/min/max = 95.4558/77.7105/113.201
[13:27:44.584] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 109.907 for pixel 0/10 mean/min/max = 92.8328/75.7003/109.965
[13:27:44.584] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 107.542 for pixel 0/37 mean/min/max = 91.2765/74.9635/107.589
[13:27:44.585] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 110.453 for pixel 0/3 mean/min/max = 94.415/78.2739/110.556
[13:27:44.585] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 109.194 for pixel 42/79 mean/min/max = 93.2004/76.8041/109.597
[13:27:44.586] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 107.215 for pixel 0/10 mean/min/max = 90.8881/74.5079/107.268
[13:27:44.586] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:27:44.674] <TB2> INFO: Expecting 411648 events.
[13:27:53.844] <TB2> INFO: 411648 events read in total (8578ms).
[13:27:53.850] <TB2> INFO: Expecting 411648 events.
[13:28:02.971] <TB2> INFO: 411648 events read in total (8718ms).
[13:28:02.982] <TB2> INFO: Expecting 411648 events.
[13:28:12.055] <TB2> INFO: 411648 events read in total (8670ms).
[13:28:12.067] <TB2> INFO: Expecting 411648 events.
[13:28:21.136] <TB2> INFO: 411648 events read in total (8666ms).
[13:28:21.151] <TB2> INFO: Expecting 411648 events.
[13:28:30.218] <TB2> INFO: 411648 events read in total (8664ms).
[13:28:30.240] <TB2> INFO: Expecting 411648 events.
[13:28:39.299] <TB2> INFO: 411648 events read in total (8656ms).
[13:28:39.320] <TB2> INFO: Expecting 411648 events.
[13:28:48.293] <TB2> INFO: 411648 events read in total (8571ms).
[13:28:48.322] <TB2> INFO: Expecting 411648 events.
[13:28:57.374] <TB2> INFO: 411648 events read in total (8650ms).
[13:28:57.398] <TB2> INFO: Expecting 411648 events.
[13:29:06.431] <TB2> INFO: 411648 events read in total (8630ms).
[13:29:06.463] <TB2> INFO: Expecting 411648 events.
[13:29:15.504] <TB2> INFO: 411648 events read in total (8638ms).
[13:29:15.546] <TB2> INFO: Expecting 411648 events.
[13:29:24.653] <TB2> INFO: 411648 events read in total (8704ms).
[13:29:24.687] <TB2> INFO: Expecting 411648 events.
[13:29:33.680] <TB2> INFO: 411648 events read in total (8590ms).
[13:29:33.731] <TB2> INFO: Expecting 411648 events.
[13:29:42.872] <TB2> INFO: 411648 events read in total (8738ms).
[13:29:42.924] <TB2> INFO: Expecting 411648 events.
[13:29:52.026] <TB2> INFO: 411648 events read in total (8699ms).
[13:29:52.084] <TB2> INFO: Expecting 411648 events.
[13:30:01.180] <TB2> INFO: 411648 events read in total (8693ms).
[13:30:01.226] <TB2> INFO: Expecting 411648 events.
[13:30:10.291] <TB2> INFO: 411648 events read in total (8663ms).
[13:30:10.337] <TB2> INFO: Test took 145751ms.
[13:30:11.864] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:30:11.874] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:30:11.874] <TB2> INFO: run 1 of 1
[13:30:12.108] <TB2> INFO: Expecting 5025280 events.
[13:30:39.840] <TB2> INFO: 668752 events read in total (27140ms).
[13:31:06.081] <TB2> INFO: 1334064 events read in total (53381ms).
[13:31:33.083] <TB2> INFO: 1999192 events read in total (80383ms).
[13:31:59.540] <TB2> INFO: 2662728 events read in total (106840ms).
[13:32:26.171] <TB2> INFO: 3322400 events read in total (133471ms).
[13:32:52.474] <TB2> INFO: 3980176 events read in total (159774ms).
[13:33:18.623] <TB2> INFO: 4636248 events read in total (185923ms).
[13:33:34.500] <TB2> INFO: 5025280 events read in total (201800ms).
[13:33:34.549] <TB2> INFO: Test took 202674ms.
[13:33:57.984] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 49.657773 .. 105.875297
[13:33:58.219] <TB2> INFO: Expecting 208000 events.
[13:34:07.848] <TB2> INFO: 208000 events read in total (9038ms).
[13:34:07.849] <TB2> INFO: Test took 9863ms.
[13:34:07.912] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 39 .. 115 (-1/-1) hits flags = 528 (plus default)
[13:34:07.925] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:34:07.925] <TB2> INFO: run 1 of 1
[13:34:08.231] <TB2> INFO: Expecting 2562560 events.
[13:34:37.674] <TB2> INFO: 686064 events read in total (28852ms).
[13:35:05.030] <TB2> INFO: 1370520 events read in total (56208ms).
[13:35:32.395] <TB2> INFO: 2049712 events read in total (83573ms).
[13:35:52.711] <TB2> INFO: 2562560 events read in total (103889ms).
[13:35:52.746] <TB2> INFO: Test took 104821ms.
[13:36:13.124] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 60.631336 .. 93.965122
[13:36:13.360] <TB2> INFO: Expecting 208000 events.
[13:36:23.026] <TB2> INFO: 208000 events read in total (9074ms).
[13:36:23.027] <TB2> INFO: Test took 9901ms.
[13:36:23.087] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 50 .. 103 (-1/-1) hits flags = 528 (plus default)
[13:36:23.099] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:36:23.099] <TB2> INFO: run 1 of 1
[13:36:23.377] <TB2> INFO: Expecting 1797120 events.
[13:36:51.518] <TB2> INFO: 691032 events read in total (27550ms).
[13:37:19.257] <TB2> INFO: 1381672 events read in total (55289ms).
[13:37:36.103] <TB2> INFO: 1797120 events read in total (72135ms).
[13:37:36.138] <TB2> INFO: Test took 73040ms.
[13:37:54.440] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 65.256180 .. 87.400175
[13:37:54.679] <TB2> INFO: Expecting 208000 events.
[13:38:04.335] <TB2> INFO: 208000 events read in total (9065ms).
[13:38:04.336] <TB2> INFO: Test took 9895ms.
[13:38:04.389] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 55 .. 97 (-1/-1) hits flags = 528 (plus default)
[13:38:04.400] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:38:04.400] <TB2> INFO: run 1 of 1
[13:38:04.678] <TB2> INFO: Expecting 1431040 events.
[13:38:33.460] <TB2> INFO: 702240 events read in total (28191ms).
[13:39:01.220] <TB2> INFO: 1403704 events read in total (55951ms).
[13:39:02.794] <TB2> INFO: 1431040 events read in total (57525ms).
[13:39:02.816] <TB2> INFO: Test took 58417ms.
[13:39:19.824] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 67.423292 .. 87.400175
[13:39:20.058] <TB2> INFO: Expecting 208000 events.
[13:39:29.668] <TB2> INFO: 208000 events read in total (9019ms).
[13:39:29.669] <TB2> INFO: Test took 9843ms.
[13:39:29.729] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 57 .. 97 (-1/-1) hits flags = 528 (plus default)
[13:39:29.740] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:39:29.740] <TB2> INFO: run 1 of 1
[13:39:30.018] <TB2> INFO: Expecting 1364480 events.
[13:39:58.489] <TB2> INFO: 696336 events read in total (27879ms).
[13:40:25.118] <TB2> INFO: 1364480 events read in total (54508ms).
[13:40:25.140] <TB2> INFO: Test took 55399ms.
[13:40:42.357] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[13:40:42.357] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[13:40:42.367] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:40:42.367] <TB2> INFO: run 1 of 1
[13:40:42.639] <TB2> INFO: Expecting 1364480 events.
[13:41:10.763] <TB2> INFO: 668336 events read in total (27533ms).
[13:41:38.260] <TB2> INFO: 1336368 events read in total (55030ms).
[13:41:39.816] <TB2> INFO: 1364480 events read in total (56586ms).
[13:41:39.842] <TB2> INFO: Test took 57476ms.
[13:41:56.124] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C0.dat
[13:41:56.124] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C1.dat
[13:41:56.124] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C2.dat
[13:41:56.124] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C3.dat
[13:41:56.124] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C4.dat
[13:41:56.124] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C5.dat
[13:41:56.124] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C6.dat
[13:41:56.124] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C7.dat
[13:41:56.124] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C8.dat
[13:41:56.124] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C9.dat
[13:41:56.125] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C10.dat
[13:41:56.125] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C11.dat
[13:41:56.125] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C12.dat
[13:41:56.125] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C13.dat
[13:41:56.125] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C14.dat
[13:41:56.125] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C15.dat
[13:41:56.125] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C0.dat
[13:41:56.131] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C1.dat
[13:41:56.136] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C2.dat
[13:41:56.142] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C3.dat
[13:41:56.148] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C4.dat
[13:41:56.153] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C5.dat
[13:41:56.161] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C6.dat
[13:41:56.170] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C7.dat
[13:41:56.177] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C8.dat
[13:41:56.186] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C9.dat
[13:41:56.194] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C10.dat
[13:41:56.203] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C11.dat
[13:41:56.212] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C12.dat
[13:41:56.220] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C13.dat
[13:41:56.229] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C14.dat
[13:41:56.238] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1123_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C15.dat
[13:41:56.246] <TB2> INFO: PixTestTrim80::trimTest() done
[13:41:56.246] <TB2> INFO: vtrim: 101 118 125 106 96 97 103 107 109 122 120 113 96 108 120 108
[13:41:56.246] <TB2> INFO: vthrcomp: 78 96 79 73 76 80 75 79 74 80 72 88 65 78 74 82
[13:41:56.246] <TB2> INFO: vcal mean: 79.97 79.92 79.95 80.01 80.03 79.99 80.00 79.98 79.96 79.94 79.98 79.96 79.92 79.99 79.99 79.94
[13:41:56.246] <TB2> INFO: vcal RMS: 0.74 0.82 0.74 0.75 0.72 0.73 0.73 0.71 1.45 0.77 0.74 0.76 0.71 0.73 0.73 0.77
[13:41:56.246] <TB2> INFO: bits mean: 9.20 10.57 9.88 9.49 8.69 10.17 9.36 9.40 9.56 10.13 9.55 10.06 10.47 9.44 10.13 10.30
[13:41:56.247] <TB2> INFO: bits RMS: 2.34 2.19 1.90 2.27 2.39 2.25 2.28 2.23 2.04 2.22 2.15 2.23 2.21 2.15 2.09 2.35
[13:41:56.254] <TB2> INFO: ----------------------------------------------------------------------
[13:41:56.254] <TB2> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:41:56.254] <TB2> INFO: ----------------------------------------------------------------------
[13:41:56.257] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:41:56.270] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:41:56.270] <TB2> INFO: run 1 of 1
[13:41:56.513] <TB2> INFO: Expecting 4160000 events.
[13:42:29.082] <TB2> INFO: 771675 events read in total (31978ms).
[13:43:00.542] <TB2> INFO: 1536250 events read in total (63438ms).
[13:43:32.037] <TB2> INFO: 2295660 events read in total (94933ms).
[13:44:03.285] <TB2> INFO: 3050265 events read in total (126181ms).
[13:44:34.495] <TB2> INFO: 3801690 events read in total (157391ms).
[13:44:49.728] <TB2> INFO: 4160000 events read in total (172624ms).
[13:44:49.779] <TB2> INFO: Test took 173509ms.
[13:45:13.473] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[13:45:13.483] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:45:13.484] <TB2> INFO: run 1 of 1
[13:45:13.730] <TB2> INFO: Expecting 5324800 events.
[13:45:44.722] <TB2> INFO: 685530 events read in total (30400ms).
[13:46:14.225] <TB2> INFO: 1367265 events read in total (59903ms).
[13:46:43.666] <TB2> INFO: 2047230 events read in total (89344ms).
[13:47:13.355] <TB2> INFO: 2725245 events read in total (119033ms).
[13:47:43.236] <TB2> INFO: 3399990 events read in total (148914ms).
[13:48:12.586] <TB2> INFO: 4073675 events read in total (178264ms).
[13:48:42.177] <TB2> INFO: 4746170 events read in total (207855ms).
[13:49:07.773] <TB2> INFO: 5324800 events read in total (233451ms).
[13:49:07.868] <TB2> INFO: Test took 234384ms.
[13:49:42.638] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 218 (-1/-1) hits flags = 528 (plus default)
[13:49:42.650] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:49:42.650] <TB2> INFO: run 1 of 1
[13:49:42.901] <TB2> INFO: Expecting 4555200 events.
[13:50:13.962] <TB2> INFO: 721030 events read in total (30469ms).
[13:50:44.331] <TB2> INFO: 1436300 events read in total (60838ms).
[13:51:14.832] <TB2> INFO: 2149280 events read in total (91339ms).
[13:51:44.953] <TB2> INFO: 2857250 events read in total (121460ms).
[13:52:15.445] <TB2> INFO: 3563370 events read in total (151952ms).
[13:52:45.579] <TB2> INFO: 4268490 events read in total (182086ms).
[13:52:58.237] <TB2> INFO: 4555200 events read in total (194744ms).
[13:52:58.306] <TB2> INFO: Test took 195655ms.
[13:53:28.543] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 213 (-1/-1) hits flags = 528 (plus default)
[13:53:28.554] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:53:28.554] <TB2> INFO: run 1 of 1
[13:53:28.838] <TB2> INFO: Expecting 4451200 events.
[13:54:00.555] <TB2> INFO: 727050 events read in total (31126ms).
[13:54:31.624] <TB2> INFO: 1448555 events read in total (62195ms).
[13:55:02.403] <TB2> INFO: 2167270 events read in total (92974ms).
[13:55:33.028] <TB2> INFO: 2880200 events read in total (123599ms).
[13:56:03.620] <TB2> INFO: 3591785 events read in total (154191ms).
[13:56:34.308] <TB2> INFO: 4302800 events read in total (184879ms).
[13:56:40.812] <TB2> INFO: 4451200 events read in total (191383ms).
[13:56:40.883] <TB2> INFO: Test took 192329ms.
[13:57:09.309] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[13:57:09.320] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:57:09.320] <TB2> INFO: run 1 of 1
[13:57:09.553] <TB2> INFO: Expecting 4472000 events.
[13:57:40.911] <TB2> INFO: 725940 events read in total (30767ms).
[13:58:11.502] <TB2> INFO: 1446200 events read in total (61358ms).
[13:58:42.753] <TB2> INFO: 2164000 events read in total (92609ms).
[13:59:13.735] <TB2> INFO: 2876005 events read in total (123591ms).
[13:59:45.264] <TB2> INFO: 3586250 events read in total (155120ms).
[14:00:16.925] <TB2> INFO: 4296455 events read in total (186781ms).
[14:00:24.904] <TB2> INFO: 4472000 events read in total (194760ms).
[14:00:24.969] <TB2> INFO: Test took 195648ms.
[14:00:49.214] <TB2> INFO: PixTestTrim80::trimBitTest() done
[14:00:49.215] <TB2> INFO: PixTestTrim80::doTest() done, duration: 2438 seconds
[14:00:50.011] <TB2> INFO: enter test to run
[14:00:50.011] <TB2> INFO: test: exit no parameter change
[14:00:50.104] <TB2> QUIET: Connection to board 156 closed.
[14:00:50.105] <TB2> INFO: pXar: this is the end, my friend