[10:14:06.580] <TB1> INFO: *** Welcome to pxar ***
[10:14:06.580] <TB1> INFO: *** Today: 2016/11/03
[10:14:06.587] <TB1> INFO: *** Version: c8ba-dirty
[10:14:06.587] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C15.dat
[10:14:06.587] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//tbmParameters_C1b.dat
[10:14:06.587] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//defaultMaskFile.dat
[10:14:06.587] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters_C15.dat
[10:14:06.642] <TB1> INFO: clk: 4
[10:14:06.642] <TB1> INFO: ctr: 4
[10:14:06.642] <TB1> INFO: sda: 19
[10:14:06.642] <TB1> INFO: tin: 9
[10:14:06.642] <TB1> INFO: level: 15
[10:14:06.642] <TB1> INFO: triggerdelay: 0
[10:14:06.642] <TB1> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[10:14:06.642] <TB1> INFO: Log level: INFO
[10:14:06.651] <TB1> INFO: Found DTB DTB_WXBYFL
[10:14:06.660] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[10:14:06.662] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
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[10:14:06.664] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[10:14:08.148] <TB1> INFO: DUT info:
[10:14:08.148] <TB1> INFO: The DUT currently contains the following objects:
[10:14:08.148] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[10:14:08.148] <TB1> INFO: TBM Core alpha (0): 7 registers set
[10:14:08.148] <TB1> INFO: TBM Core beta (1): 7 registers set
[10:14:08.148] <TB1> INFO: TBM Core alpha (2): 7 registers set
[10:14:08.148] <TB1> INFO: TBM Core beta (3): 7 registers set
[10:14:08.148] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[10:14:08.148] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.148] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[10:14:08.549] <TB1> INFO: enter 'restricted' command line mode
[10:14:08.549] <TB1> INFO: enter test to run
[10:14:08.549] <TB1> INFO: test: pretest no parameter change
[10:14:08.549] <TB1> INFO: running: pretest
[10:14:09.452] <TB1> INFO: ######################################################################
[10:14:09.452] <TB1> INFO: PixTestPretest::doTest()
[10:14:09.452] <TB1> INFO: ######################################################################
[10:14:09.453] <TB1> INFO: ----------------------------------------------------------------------
[10:14:09.453] <TB1> INFO: PixTestPretest::programROC()
[10:14:09.453] <TB1> INFO: ----------------------------------------------------------------------
[10:14:27.466] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[10:14:27.466] <TB1> INFO: IA differences per ROC: 21.7 20.1 16.1 19.3 19.3 19.3 20.9 19.3 16.1 19.3 16.1 19.3 20.1 17.7 18.5 20.9
[10:14:27.502] <TB1> INFO: ----------------------------------------------------------------------
[10:14:27.502] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[10:14:27.502] <TB1> INFO: ----------------------------------------------------------------------
[10:14:48.748] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 385.1 mA = 24.0688 mA/ROC
[10:14:48.748] <TB1> INFO: i(loss) [mA/ROC]: 19.3 19.3 19.3 19.3 18.5 19.3 18.5 20.1 19.3 19.3 19.3 18.5 19.3 19.3 18.5 18.5
[10:14:48.776] <TB1> INFO: ----------------------------------------------------------------------
[10:14:48.776] <TB1> INFO: PixTestPretest::findTiming()
[10:14:48.776] <TB1> INFO: ----------------------------------------------------------------------
[10:14:48.776] <TB1> INFO: PixTestCmd::init()

[10:15:20.138] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 6, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[10:15:20.138] <TB1> INFO: (success/tries = 100/100), width = 3
[10:15:21.640] <TB1> INFO: ----------------------------------------------------------------------
[10:15:21.640] <TB1> INFO: PixTestPretest::findWorkingPixel()
[10:15:21.640] <TB1> INFO: ----------------------------------------------------------------------
[10:15:21.731] <TB1> INFO: Expecting 231680 events.
[10:15:31.393] <TB1> INFO: 231680 events read in total (9070ms).
[10:15:31.399] <TB1> INFO: Test took 9758ms.
[10:15:31.645] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[10:15:31.674] <TB1> INFO: ----------------------------------------------------------------------
[10:15:31.674] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[10:15:31.674] <TB1> INFO: ----------------------------------------------------------------------
[10:15:31.766] <TB1> INFO: Expecting 231680 events.
[10:15:41.398] <TB1> INFO: 231680 events read in total (9041ms).
[10:15:41.406] <TB1> INFO: Test took 9729ms.
[10:15:41.664] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[10:15:41.664] <TB1> INFO: CalDel: 98 110 102 102 108 105 97 114 93 85 104 109 109 92 107 109
[10:15:41.664] <TB1> INFO: VthrComp: 51 52 51 51 51 51 51 51 51 53 51 51 51 51 51 51
[10:15:41.666] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C0.dat
[10:15:41.666] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C1.dat
[10:15:41.666] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C2.dat
[10:15:41.666] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C3.dat
[10:15:41.667] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C4.dat
[10:15:41.667] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C5.dat
[10:15:41.667] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C6.dat
[10:15:41.667] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C7.dat
[10:15:41.667] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C8.dat
[10:15:41.667] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C9.dat
[10:15:41.667] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C10.dat
[10:15:41.667] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C11.dat
[10:15:41.667] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C12.dat
[10:15:41.668] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C13.dat
[10:15:41.668] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C14.dat
[10:15:41.668] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters_C15.dat
[10:15:41.668] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//tbmParameters_C0a.dat
[10:15:41.668] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//tbmParameters_C0b.dat
[10:15:41.668] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//tbmParameters_C1a.dat
[10:15:41.668] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//tbmParameters_C1b.dat
[10:15:41.668] <TB1> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[10:15:41.767] <TB1> INFO: enter test to run
[10:15:41.767] <TB1> INFO: test: FullTest no parameter change
[10:15:41.767] <TB1> INFO: running: fulltest
[10:15:41.767] <TB1> INFO: ######################################################################
[10:15:41.767] <TB1> INFO: PixTestFullTest::doTest()
[10:15:41.767] <TB1> INFO: ######################################################################
[10:15:41.768] <TB1> INFO: ######################################################################
[10:15:41.768] <TB1> INFO: PixTestAlive::doTest()
[10:15:41.769] <TB1> INFO: ######################################################################
[10:15:41.770] <TB1> INFO: ----------------------------------------------------------------------
[10:15:41.770] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:15:41.770] <TB1> INFO: ----------------------------------------------------------------------
[10:15:42.004] <TB1> INFO: Expecting 41600 events.
[10:15:45.459] <TB1> INFO: 41600 events read in total (2863ms).
[10:15:45.460] <TB1> INFO: Test took 3689ms.
[10:15:45.687] <TB1> INFO: PixTestAlive::aliveTest() done
[10:15:45.687] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:15:45.688] <TB1> INFO: ----------------------------------------------------------------------
[10:15:45.688] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:15:45.688] <TB1> INFO: ----------------------------------------------------------------------
[10:15:45.921] <TB1> INFO: Expecting 41600 events.
[10:15:48.819] <TB1> INFO: 41600 events read in total (2306ms).
[10:15:48.819] <TB1> INFO: Test took 3129ms.
[10:15:48.819] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[10:15:49.057] <TB1> INFO: PixTestAlive::maskTest() done
[10:15:49.058] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:15:49.059] <TB1> INFO: ----------------------------------------------------------------------
[10:15:49.059] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:15:49.059] <TB1> INFO: ----------------------------------------------------------------------
[10:15:49.295] <TB1> INFO: Expecting 41600 events.
[10:15:52.835] <TB1> INFO: 41600 events read in total (2948ms).
[10:15:52.835] <TB1> INFO: Test took 3775ms.
[10:15:53.063] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[10:15:53.063] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:15:53.063] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[10:15:53.063] <TB1> INFO: Decoding statistics:
[10:15:53.063] <TB1> INFO: General information:
[10:15:53.063] <TB1> INFO: 16bit words read: 0
[10:15:53.063] <TB1> INFO: valid events total: 0
[10:15:53.063] <TB1> INFO: empty events: 0
[10:15:53.063] <TB1> INFO: valid events with pixels: 0
[10:15:53.063] <TB1> INFO: valid pixel hits: 0
[10:15:53.063] <TB1> INFO: Event errors: 0
[10:15:53.063] <TB1> INFO: start marker: 0
[10:15:53.063] <TB1> INFO: stop marker: 0
[10:15:53.063] <TB1> INFO: overflow: 0
[10:15:53.063] <TB1> INFO: invalid 5bit words: 0
[10:15:53.063] <TB1> INFO: invalid XOR eye diagram: 0
[10:15:53.063] <TB1> INFO: frame (failed synchr.): 0
[10:15:53.063] <TB1> INFO: idle data (no TBM trl): 0
[10:15:53.063] <TB1> INFO: no data (only TBM hdr): 0
[10:15:53.063] <TB1> INFO: TBM errors: 0
[10:15:53.063] <TB1> INFO: flawed TBM headers: 0
[10:15:53.063] <TB1> INFO: flawed TBM trailers: 0
[10:15:53.063] <TB1> INFO: event ID mismatches: 0
[10:15:53.063] <TB1> INFO: ROC errors: 0
[10:15:53.063] <TB1> INFO: missing ROC header(s): 0
[10:15:53.063] <TB1> INFO: misplaced readback start: 0
[10:15:53.063] <TB1> INFO: Pixel decoding errors: 0
[10:15:53.063] <TB1> INFO: pixel data incomplete: 0
[10:15:53.063] <TB1> INFO: pixel address: 0
[10:15:53.063] <TB1> INFO: pulse height fill bit: 0
[10:15:53.063] <TB1> INFO: buffer corruption: 0
[10:15:53.070] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C15.dat
[10:15:53.070] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[10:15:53.070] <TB1> INFO: ######################################################################
[10:15:53.070] <TB1> INFO: PixTestReadback::doTest()
[10:15:53.070] <TB1> INFO: ######################################################################
[10:15:53.070] <TB1> INFO: ----------------------------------------------------------------------
[10:15:53.070] <TB1> INFO: PixTestReadback::CalibrateVd()
[10:15:53.070] <TB1> INFO: ----------------------------------------------------------------------
[10:16:03.041] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C0.dat
[10:16:03.041] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C1.dat
[10:16:03.041] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C2.dat
[10:16:03.041] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C3.dat
[10:16:03.042] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C4.dat
[10:16:03.042] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C5.dat
[10:16:03.042] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C6.dat
[10:16:03.042] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C7.dat
[10:16:03.042] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C8.dat
[10:16:03.042] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C9.dat
[10:16:03.042] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C10.dat
[10:16:03.042] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C11.dat
[10:16:03.042] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C12.dat
[10:16:03.042] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C13.dat
[10:16:03.042] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C14.dat
[10:16:03.042] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C15.dat
[10:16:03.069] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:16:03.069] <TB1> INFO: ----------------------------------------------------------------------
[10:16:03.070] <TB1> INFO: PixTestReadback::CalibrateVa()
[10:16:03.070] <TB1> INFO: ----------------------------------------------------------------------
[10:16:12.962] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C0.dat
[10:16:12.962] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C1.dat
[10:16:12.962] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C2.dat
[10:16:12.962] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C3.dat
[10:16:12.962] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C4.dat
[10:16:12.962] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C5.dat
[10:16:12.962] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C6.dat
[10:16:12.962] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C7.dat
[10:16:12.962] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C8.dat
[10:16:12.962] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C9.dat
[10:16:12.962] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C10.dat
[10:16:12.962] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C11.dat
[10:16:12.962] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C12.dat
[10:16:12.963] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C13.dat
[10:16:12.963] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C14.dat
[10:16:12.963] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C15.dat
[10:16:12.993] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:16:12.993] <TB1> INFO: ----------------------------------------------------------------------
[10:16:12.993] <TB1> INFO: PixTestReadback::readbackVbg()
[10:16:12.993] <TB1> INFO: ----------------------------------------------------------------------
[10:16:20.631] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:16:20.631] <TB1> INFO: ----------------------------------------------------------------------
[10:16:20.631] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[10:16:20.631] <TB1> INFO: ----------------------------------------------------------------------
[10:16:20.631] <TB1> INFO: Vbg will be calibrated using Vd calibration
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 144.8calibrated Vbg = 1.14659 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 155.3calibrated Vbg = 1.1596 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 148.6calibrated Vbg = 1.14928 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 147.4calibrated Vbg = 1.14881 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 156.9calibrated Vbg = 1.1562 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 148.9calibrated Vbg = 1.16085 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 160.1calibrated Vbg = 1.15583 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 154.2calibrated Vbg = 1.15682 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 157.7calibrated Vbg = 1.14388 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154.2calibrated Vbg = 1.14282 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 155.6calibrated Vbg = 1.14713 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 157.5calibrated Vbg = 1.13051 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 148.6calibrated Vbg = 1.14717 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152.5calibrated Vbg = 1.15415 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 159.4calibrated Vbg = 1.14924 :::*/*/*/*/
[10:16:20.631] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 148.9calibrated Vbg = 1.15115 :::*/*/*/*/
[10:16:20.633] <TB1> INFO: ----------------------------------------------------------------------
[10:16:20.633] <TB1> INFO: PixTestReadback::CalibrateIa()
[10:16:20.633] <TB1> INFO: ----------------------------------------------------------------------
[10:19:00.919] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C0.dat
[10:19:00.919] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C1.dat
[10:19:00.919] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C2.dat
[10:19:00.919] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C3.dat
[10:19:00.919] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C4.dat
[10:19:00.919] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C5.dat
[10:19:00.919] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C6.dat
[10:19:00.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C7.dat
[10:19:00.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C8.dat
[10:19:00.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C9.dat
[10:19:00.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C10.dat
[10:19:00.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C11.dat
[10:19:00.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C12.dat
[10:19:00.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C13.dat
[10:19:00.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C14.dat
[10:19:00.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//readbackCal_C15.dat
[10:19:00.948] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:19:00.949] <TB1> INFO: PixTestReadback::doTest() done
[10:19:00.949] <TB1> INFO: Decoding statistics:
[10:19:00.949] <TB1> INFO: General information:
[10:19:00.949] <TB1> INFO: 16bit words read: 1536
[10:19:00.949] <TB1> INFO: valid events total: 256
[10:19:00.949] <TB1> INFO: empty events: 256
[10:19:00.949] <TB1> INFO: valid events with pixels: 0
[10:19:00.949] <TB1> INFO: valid pixel hits: 0
[10:19:00.949] <TB1> INFO: Event errors: 0
[10:19:00.949] <TB1> INFO: start marker: 0
[10:19:00.949] <TB1> INFO: stop marker: 0
[10:19:00.949] <TB1> INFO: overflow: 0
[10:19:00.949] <TB1> INFO: invalid 5bit words: 0
[10:19:00.949] <TB1> INFO: invalid XOR eye diagram: 0
[10:19:00.949] <TB1> INFO: frame (failed synchr.): 0
[10:19:00.949] <TB1> INFO: idle data (no TBM trl): 0
[10:19:00.949] <TB1> INFO: no data (only TBM hdr): 0
[10:19:00.949] <TB1> INFO: TBM errors: 0
[10:19:00.950] <TB1> INFO: flawed TBM headers: 0
[10:19:00.950] <TB1> INFO: flawed TBM trailers: 0
[10:19:00.950] <TB1> INFO: event ID mismatches: 0
[10:19:00.950] <TB1> INFO: ROC errors: 0
[10:19:00.950] <TB1> INFO: missing ROC header(s): 0
[10:19:00.950] <TB1> INFO: misplaced readback start: 0
[10:19:00.950] <TB1> INFO: Pixel decoding errors: 0
[10:19:00.950] <TB1> INFO: pixel data incomplete: 0
[10:19:00.950] <TB1> INFO: pixel address: 0
[10:19:00.950] <TB1> INFO: pulse height fill bit: 0
[10:19:00.950] <TB1> INFO: buffer corruption: 0
[10:19:00.984] <TB1> INFO: ######################################################################
[10:19:00.984] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[10:19:00.984] <TB1> INFO: ######################################################################
[10:19:00.987] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[10:19:00.998] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[10:19:00.998] <TB1> INFO: run 1 of 1
[10:19:01.230] <TB1> INFO: Expecting 3120000 events.
[10:19:31.064] <TB1> INFO: 662120 events read in total (29242ms).











[10:20:00.915] <TB1> INFO: 1321810 events read in total (59093ms).











[10:20:30.636] <TB1> INFO: 1978455 events read in total (88814ms).











[10:21:00.307] <TB1> INFO: 2636760 events read in total (118485ms).











[10:21:22.596] <TB1> INFO: 3120000 events read in total (140774ms).
[10:21:22.652] <TB1> INFO: Test took 141655ms.
[10:21:47.590] <TB1> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 166 seconds
[10:21:47.590] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0
[10:21:47.590] <TB1> INFO: separation cut (per ROC): 108 124 110 115 103 107 110 107 98 107 99 102 107 106 99 99
[10:21:47.590] <TB1> INFO: Decoding statistics:
[10:21:47.590] <TB1> INFO: General information:
[10:21:47.590] <TB1> INFO: 16bit words read: 0
[10:21:47.590] <TB1> INFO: valid events total: 0
[10:21:47.590] <TB1> INFO: empty events: 0
[10:21:47.590] <TB1> INFO: valid events with pixels: 0
[10:21:47.590] <TB1> INFO: valid pixel hits: 0
[10:21:47.590] <TB1> INFO: Event errors: 0
[10:21:47.590] <TB1> INFO: start marker: 0
[10:21:47.590] <TB1> INFO: stop marker: 0
[10:21:47.590] <TB1> INFO: overflow: 0
[10:21:47.590] <TB1> INFO: invalid 5bit words: 0
[10:21:47.590] <TB1> INFO: invalid XOR eye diagram: 0
[10:21:47.590] <TB1> INFO: frame (failed synchr.): 0
[10:21:47.590] <TB1> INFO: idle data (no TBM trl): 0
[10:21:47.590] <TB1> INFO: no data (only TBM hdr): 0
[10:21:47.590] <TB1> INFO: TBM errors: 0
[10:21:47.590] <TB1> INFO: flawed TBM headers: 0
[10:21:47.590] <TB1> INFO: flawed TBM trailers: 0
[10:21:47.590] <TB1> INFO: event ID mismatches: 0
[10:21:47.590] <TB1> INFO: ROC errors: 0
[10:21:47.590] <TB1> INFO: missing ROC header(s): 0
[10:21:47.590] <TB1> INFO: misplaced readback start: 0
[10:21:47.590] <TB1> INFO: Pixel decoding errors: 0
[10:21:47.590] <TB1> INFO: pixel data incomplete: 0
[10:21:47.590] <TB1> INFO: pixel address: 0
[10:21:47.590] <TB1> INFO: pulse height fill bit: 0
[10:21:47.590] <TB1> INFO: buffer corruption: 0
[10:21:47.639] <TB1> INFO: ######################################################################
[10:21:47.639] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:21:47.639] <TB1> INFO: ######################################################################
[10:21:47.640] <TB1> INFO: ----------------------------------------------------------------------
[10:21:47.640] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:21:47.640] <TB1> INFO: ----------------------------------------------------------------------
[10:21:47.640] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[10:21:47.652] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[10:21:47.652] <TB1> INFO: run 1 of 1
[10:21:47.972] <TB1> INFO: Expecting 36608000 events.
[10:22:11.116] <TB1> INFO: 675850 events read in total (22552ms).
[10:22:33.720] <TB1> INFO: 1338300 events read in total (45156ms).
[10:22:56.336] <TB1> INFO: 2001800 events read in total (67772ms).
[10:23:18.675] <TB1> INFO: 2662400 events read in total (90111ms).
[10:23:41.154] <TB1> INFO: 3323700 events read in total (112590ms).
[10:24:03.475] <TB1> INFO: 3983550 events read in total (134911ms).
[10:24:25.974] <TB1> INFO: 4643600 events read in total (157410ms).
[10:24:48.487] <TB1> INFO: 5303150 events read in total (179923ms).
[10:25:10.914] <TB1> INFO: 5962700 events read in total (202350ms).
[10:25:33.523] <TB1> INFO: 6622600 events read in total (224959ms).
[10:25:55.996] <TB1> INFO: 7281450 events read in total (247432ms).
[10:26:18.349] <TB1> INFO: 7939950 events read in total (269785ms).
[10:26:40.658] <TB1> INFO: 8598050 events read in total (292094ms).
[10:27:02.940] <TB1> INFO: 9256250 events read in total (314376ms).
[10:27:25.619] <TB1> INFO: 9913800 events read in total (337055ms).
[10:27:47.974] <TB1> INFO: 10571700 events read in total (359410ms).
[10:28:10.488] <TB1> INFO: 11228400 events read in total (381924ms).
[10:28:32.912] <TB1> INFO: 11886650 events read in total (404348ms).
[10:28:55.316] <TB1> INFO: 12544700 events read in total (426752ms).
[10:29:17.505] <TB1> INFO: 13201300 events read in total (448941ms).
[10:29:39.838] <TB1> INFO: 13858350 events read in total (471274ms).
[10:30:02.124] <TB1> INFO: 14515700 events read in total (493560ms).
[10:30:24.418] <TB1> INFO: 15169950 events read in total (515854ms).
[10:30:46.921] <TB1> INFO: 15825750 events read in total (538357ms).
[10:31:08.994] <TB1> INFO: 16480400 events read in total (560430ms).
[10:31:31.504] <TB1> INFO: 17136450 events read in total (582940ms).
[10:31:53.830] <TB1> INFO: 17791850 events read in total (605266ms).
[10:32:16.331] <TB1> INFO: 18445450 events read in total (627767ms).
[10:32:38.614] <TB1> INFO: 19099450 events read in total (650050ms).
[10:33:00.891] <TB1> INFO: 19750550 events read in total (672327ms).
[10:33:23.412] <TB1> INFO: 20399850 events read in total (694848ms).
[10:33:45.747] <TB1> INFO: 21048700 events read in total (717183ms).
[10:34:07.758] <TB1> INFO: 21697800 events read in total (739194ms).
[10:34:29.898] <TB1> INFO: 22348200 events read in total (761334ms).
[10:34:52.164] <TB1> INFO: 22998400 events read in total (783600ms).
[10:35:14.368] <TB1> INFO: 23647900 events read in total (805804ms).
[10:35:36.559] <TB1> INFO: 24296600 events read in total (827995ms).
[10:35:58.953] <TB1> INFO: 24947300 events read in total (850389ms).
[10:36:20.805] <TB1> INFO: 25598000 events read in total (872241ms).
[10:36:43.045] <TB1> INFO: 26250450 events read in total (894481ms).
[10:37:05.319] <TB1> INFO: 26902150 events read in total (916755ms).
[10:37:27.769] <TB1> INFO: 27552400 events read in total (939205ms).
[10:37:49.763] <TB1> INFO: 28200500 events read in total (961199ms).
[10:38:11.721] <TB1> INFO: 28849300 events read in total (983157ms).
[10:38:34.056] <TB1> INFO: 29495850 events read in total (1005492ms).
[10:38:56.334] <TB1> INFO: 30146200 events read in total (1027770ms).
[10:39:18.511] <TB1> INFO: 30794500 events read in total (1049947ms).
[10:39:40.506] <TB1> INFO: 31442500 events read in total (1071942ms).
[10:40:02.434] <TB1> INFO: 32091450 events read in total (1093870ms).
[10:40:24.780] <TB1> INFO: 32740350 events read in total (1116216ms).
[10:40:46.932] <TB1> INFO: 33390100 events read in total (1138368ms).
[10:41:09.261] <TB1> INFO: 34040050 events read in total (1160697ms).
[10:41:31.448] <TB1> INFO: 34689350 events read in total (1182884ms).
[10:41:53.364] <TB1> INFO: 35337100 events read in total (1204800ms).
[10:42:15.467] <TB1> INFO: 35988550 events read in total (1226903ms).
[10:42:36.690] <TB1> INFO: 36608000 events read in total (1248126ms).
[10:42:36.754] <TB1> INFO: Test took 1249102ms.
[10:42:37.214] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:42:38.746] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:42:40.600] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:42:42.634] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:42:44.642] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:42:46.728] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:42:48.465] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:42:50.407] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:42:52.373] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:42:54.362] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:42:56.545] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:42:58.749] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:43:00.645] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:43:02.448] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:43:04.216] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:43:06.240] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:43:07.951] <TB1> INFO: PixTestScurves::scurves() done
[10:43:07.951] <TB1> INFO: Vcal mean: 113.58 127.51 116.55 114.38 107.52 116.88 119.46 115.30 117.78 117.72 110.23 103.51 116.02 121.42 107.43 109.86
[10:43:07.951] <TB1> INFO: Vcal RMS: 5.55 6.59 6.17 5.05 4.84 5.14 6.13 5.63 5.33 5.98 5.98 5.30 5.49 5.87 4.93 4.70
[10:43:07.951] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1280 seconds
[10:43:07.951] <TB1> INFO: Decoding statistics:
[10:43:07.951] <TB1> INFO: General information:
[10:43:07.951] <TB1> INFO: 16bit words read: 0
[10:43:07.951] <TB1> INFO: valid events total: 0
[10:43:07.951] <TB1> INFO: empty events: 0
[10:43:07.951] <TB1> INFO: valid events with pixels: 0
[10:43:07.951] <TB1> INFO: valid pixel hits: 0
[10:43:07.951] <TB1> INFO: Event errors: 0
[10:43:07.951] <TB1> INFO: start marker: 0
[10:43:07.951] <TB1> INFO: stop marker: 0
[10:43:07.951] <TB1> INFO: overflow: 0
[10:43:07.951] <TB1> INFO: invalid 5bit words: 0
[10:43:07.951] <TB1> INFO: invalid XOR eye diagram: 0
[10:43:07.951] <TB1> INFO: frame (failed synchr.): 0
[10:43:07.951] <TB1> INFO: idle data (no TBM trl): 0
[10:43:07.951] <TB1> INFO: no data (only TBM hdr): 0
[10:43:07.951] <TB1> INFO: TBM errors: 0
[10:43:07.951] <TB1> INFO: flawed TBM headers: 0
[10:43:07.951] <TB1> INFO: flawed TBM trailers: 0
[10:43:07.951] <TB1> INFO: event ID mismatches: 0
[10:43:07.951] <TB1> INFO: ROC errors: 0
[10:43:07.951] <TB1> INFO: missing ROC header(s): 0
[10:43:07.951] <TB1> INFO: misplaced readback start: 0
[10:43:07.951] <TB1> INFO: Pixel decoding errors: 0
[10:43:07.951] <TB1> INFO: pixel data incomplete: 0
[10:43:07.951] <TB1> INFO: pixel address: 0
[10:43:07.951] <TB1> INFO: pulse height fill bit: 0
[10:43:07.951] <TB1> INFO: buffer corruption: 0
[10:43:08.018] <TB1> INFO: ######################################################################
[10:43:08.019] <TB1> INFO: PixTestTrim::doTest()
[10:43:08.019] <TB1> INFO: ######################################################################
[10:43:08.020] <TB1> INFO: ----------------------------------------------------------------------
[10:43:08.020] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[10:43:08.020] <TB1> INFO: ----------------------------------------------------------------------
[10:43:08.062] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[10:43:08.062] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:43:08.070] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:43:08.070] <TB1> INFO: run 1 of 1
[10:43:08.305] <TB1> INFO: Expecting 5025280 events.
[10:43:37.981] <TB1> INFO: 822728 events read in total (29082ms).
[10:44:07.431] <TB1> INFO: 1642696 events read in total (58533ms).
[10:44:36.905] <TB1> INFO: 2459400 events read in total (88006ms).
[10:45:06.291] <TB1> INFO: 3273848 events read in total (117392ms).
[10:45:35.519] <TB1> INFO: 4085656 events read in total (146620ms).
[10:46:04.553] <TB1> INFO: 4896880 events read in total (175654ms).
[10:46:09.583] <TB1> INFO: 5025280 events read in total (180684ms).
[10:46:09.624] <TB1> INFO: Test took 181553ms.
[10:46:30.579] <TB1> INFO: ROC 0 VthrComp = 116
[10:46:30.579] <TB1> INFO: ROC 1 VthrComp = 132
[10:46:30.579] <TB1> INFO: ROC 2 VthrComp = 118
[10:46:30.579] <TB1> INFO: ROC 3 VthrComp = 118
[10:46:30.579] <TB1> INFO: ROC 4 VthrComp = 111
[10:46:30.580] <TB1> INFO: ROC 5 VthrComp = 125
[10:46:30.580] <TB1> INFO: ROC 6 VthrComp = 125
[10:46:30.581] <TB1> INFO: ROC 7 VthrComp = 117
[10:46:30.581] <TB1> INFO: ROC 8 VthrComp = 120
[10:46:30.581] <TB1> INFO: ROC 9 VthrComp = 125
[10:46:30.581] <TB1> INFO: ROC 10 VthrComp = 108
[10:46:30.582] <TB1> INFO: ROC 11 VthrComp = 106
[10:46:30.582] <TB1> INFO: ROC 12 VthrComp = 123
[10:46:30.582] <TB1> INFO: ROC 13 VthrComp = 127
[10:46:30.582] <TB1> INFO: ROC 14 VthrComp = 107
[10:46:30.583] <TB1> INFO: ROC 15 VthrComp = 113
[10:46:30.817] <TB1> INFO: Expecting 41600 events.
[10:46:34.259] <TB1> INFO: 41600 events read in total (2850ms).
[10:46:34.260] <TB1> INFO: Test took 3676ms.
[10:46:34.269] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[10:46:34.269] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:46:34.278] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:46:34.278] <TB1> INFO: run 1 of 1
[10:46:34.555] <TB1> INFO: Expecting 5025280 events.
[10:47:00.377] <TB1> INFO: 590496 events read in total (25230ms).
[10:47:25.647] <TB1> INFO: 1179624 events read in total (50500ms).
[10:47:50.805] <TB1> INFO: 1769336 events read in total (75658ms).
[10:48:16.204] <TB1> INFO: 2358808 events read in total (101057ms).
[10:48:41.592] <TB1> INFO: 2946376 events read in total (126445ms).
[10:49:06.799] <TB1> INFO: 3532512 events read in total (151652ms).
[10:49:31.886] <TB1> INFO: 4118264 events read in total (176739ms).
[10:49:57.077] <TB1> INFO: 4703768 events read in total (201930ms).
[10:50:11.162] <TB1> INFO: 5025280 events read in total (216015ms).
[10:50:11.219] <TB1> INFO: Test took 216941ms.
[10:50:39.719] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 60.9167 for pixel 0/59 mean/min/max = 46.1509/31.2137/61.0881
[10:50:39.719] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 62.5197 for pixel 10/11 mean/min/max = 47.5284/32.5021/62.5546
[10:50:39.719] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 61.3007 for pixel 7/14 mean/min/max = 46.4647/31.6224/61.307
[10:50:39.720] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 58.4325 for pixel 47/6 mean/min/max = 45.2/31.8503/58.5497
[10:50:39.720] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 60.4992 for pixel 15/14 mean/min/max = 47.5326/34.4794/60.5858
[10:50:39.721] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 59.13 for pixel 18/9 mean/min/max = 45.5169/31.8336/59.2003
[10:50:39.721] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 60.7611 for pixel 15/6 mean/min/max = 46.1642/31.4395/60.8889
[10:50:39.721] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 61.9623 for pixel 40/17 mean/min/max = 46.7438/31.3831/62.1045
[10:50:39.722] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 60.2941 for pixel 25/8 mean/min/max = 45.8925/31.4647/60.3204
[10:50:39.722] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 60.126 for pixel 1/15 mean/min/max = 45.6976/31.1604/60.2349
[10:50:39.722] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 66.5523 for pixel 1/2 mean/min/max = 49.8863/33.2003/66.5724
[10:50:39.723] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 61.3027 for pixel 0/1 mean/min/max = 48.1453/34.8527/61.4379
[10:50:39.723] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 59.0154 for pixel 51/5 mean/min/max = 45.529/31.8048/59.2532
[10:50:39.723] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 60.5196 for pixel 8/2 mean/min/max = 46.379/32.2369/60.5211
[10:50:39.724] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 61.9514 for pixel 9/68 mean/min/max = 48.3205/34.6811/61.9599
[10:50:39.724] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 59.1287 for pixel 10/16 mean/min/max = 45.7705/32.3537/59.1874
[10:50:39.724] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:50:39.813] <TB1> INFO: Expecting 411648 events.
[10:50:49.130] <TB1> INFO: 411648 events read in total (8726ms).
[10:50:49.139] <TB1> INFO: Expecting 411648 events.
[10:50:58.207] <TB1> INFO: 411648 events read in total (8665ms).
[10:50:58.216] <TB1> INFO: Expecting 411648 events.
[10:51:07.249] <TB1> INFO: 411648 events read in total (8630ms).
[10:51:07.264] <TB1> INFO: Expecting 411648 events.
[10:51:16.230] <TB1> INFO: 411648 events read in total (8563ms).
[10:51:16.244] <TB1> INFO: Expecting 411648 events.
[10:51:25.225] <TB1> INFO: 411648 events read in total (8578ms).
[10:51:25.247] <TB1> INFO: Expecting 411648 events.
[10:51:34.407] <TB1> INFO: 411648 events read in total (8757ms).
[10:51:34.433] <TB1> INFO: Expecting 411648 events.
[10:51:43.488] <TB1> INFO: 411648 events read in total (8652ms).
[10:51:43.516] <TB1> INFO: Expecting 411648 events.
[10:51:52.550] <TB1> INFO: 411648 events read in total (8631ms).
[10:51:52.583] <TB1> INFO: Expecting 411648 events.
[10:52:01.531] <TB1> INFO: 411648 events read in total (8545ms).
[10:52:01.567] <TB1> INFO: Expecting 411648 events.
[10:52:10.576] <TB1> INFO: 411648 events read in total (8606ms).
[10:52:10.605] <TB1> INFO: Expecting 411648 events.
[10:52:19.637] <TB1> INFO: 411648 events read in total (8629ms).
[10:52:19.668] <TB1> INFO: Expecting 411648 events.
[10:52:28.645] <TB1> INFO: 411648 events read in total (8574ms).
[10:52:28.680] <TB1> INFO: Expecting 411648 events.
[10:52:37.717] <TB1> INFO: 411648 events read in total (8634ms).
[10:52:37.753] <TB1> INFO: Expecting 411648 events.
[10:52:46.829] <TB1> INFO: 411648 events read in total (8673ms).
[10:52:46.885] <TB1> INFO: Expecting 411648 events.
[10:52:55.933] <TB1> INFO: 411648 events read in total (8645ms).
[10:52:55.973] <TB1> INFO: Expecting 411648 events.
[10:53:05.035] <TB1> INFO: 411648 events read in total (8659ms).
[10:53:05.082] <TB1> INFO: Test took 145358ms.
[10:53:05.882] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[10:53:05.893] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:53:05.893] <TB1> INFO: run 1 of 1
[10:53:06.170] <TB1> INFO: Expecting 5025280 events.
[10:53:31.911] <TB1> INFO: 589040 events read in total (25150ms).
[10:53:57.031] <TB1> INFO: 1176144 events read in total (50270ms).
[10:54:22.418] <TB1> INFO: 1765584 events read in total (75657ms).
[10:54:47.949] <TB1> INFO: 2351560 events read in total (101188ms).
[10:55:13.333] <TB1> INFO: 2939432 events read in total (126572ms).
[10:55:38.501] <TB1> INFO: 3523392 events read in total (151740ms).
[10:56:03.537] <TB1> INFO: 4109400 events read in total (176776ms).
[10:56:28.729] <TB1> INFO: 4692336 events read in total (201968ms).
[10:56:43.655] <TB1> INFO: 5025280 events read in total (216894ms).
[10:56:43.771] <TB1> INFO: Test took 217878ms.
[10:57:10.029] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 0.163176 .. 147.967318
[10:57:10.271] <TB1> INFO: Expecting 208000 events.
[10:57:19.607] <TB1> INFO: 208000 events read in total (8745ms).
[10:57:19.608] <TB1> INFO: Test took 9578ms.
[10:57:19.659] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 157 (-1/-1) hits flags = 528 (plus default)
[10:57:19.670] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:57:19.670] <TB1> INFO: run 1 of 1
[10:57:19.948] <TB1> INFO: Expecting 5258240 events.
[10:57:46.125] <TB1> INFO: 585120 events read in total (25585ms).
[10:58:11.498] <TB1> INFO: 1170112 events read in total (50958ms).
[10:58:36.434] <TB1> INFO: 1755488 events read in total (75894ms).
[10:59:01.946] <TB1> INFO: 2340280 events read in total (101407ms).
[10:59:26.901] <TB1> INFO: 2925456 events read in total (126361ms).
[10:59:52.377] <TB1> INFO: 3509592 events read in total (151837ms).
[11:00:17.941] <TB1> INFO: 4093568 events read in total (177401ms).
[11:00:43.528] <TB1> INFO: 4677104 events read in total (202988ms).
[11:01:09.502] <TB1> INFO: 5258240 events read in total (228962ms).
[11:01:09.625] <TB1> INFO: Test took 229955ms.
[11:01:37.566] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.785944 .. 47.076367
[11:01:37.825] <TB1> INFO: Expecting 208000 events.
[11:01:47.376] <TB1> INFO: 208000 events read in total (8960ms).
[11:01:47.377] <TB1> INFO: Test took 9809ms.
[11:01:47.429] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 57 (-1/-1) hits flags = 528 (plus default)
[11:01:47.439] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:01:47.439] <TB1> INFO: run 1 of 1
[11:01:47.716] <TB1> INFO: Expecting 1364480 events.
[11:02:15.708] <TB1> INFO: 650944 events read in total (27400ms).
[11:02:43.255] <TB1> INFO: 1299960 events read in total (54948ms).
[11:02:46.372] <TB1> INFO: 1364480 events read in total (58064ms).
[11:02:46.396] <TB1> INFO: Test took 58958ms.
[11:02:59.716] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 24.991573 .. 47.260020
[11:02:59.949] <TB1> INFO: Expecting 208000 events.
[11:03:09.796] <TB1> INFO: 208000 events read in total (9255ms).
[11:03:09.797] <TB1> INFO: Test took 10080ms.
[11:03:09.860] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 14 .. 57 (-1/-1) hits flags = 528 (plus default)
[11:03:09.870] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:03:09.870] <TB1> INFO: run 1 of 1
[11:03:10.148] <TB1> INFO: Expecting 1464320 events.
[11:03:37.887] <TB1> INFO: 663336 events read in total (27146ms).
[11:04:05.054] <TB1> INFO: 1325504 events read in total (54313ms).
[11:04:11.187] <TB1> INFO: 1464320 events read in total (60447ms).
[11:04:11.212] <TB1> INFO: Test took 61342ms.
[11:04:25.736] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 23.412317 .. 44.452286
[11:04:25.971] <TB1> INFO: Expecting 208000 events.
[11:04:35.645] <TB1> INFO: 208000 events read in total (9083ms).
[11:04:35.646] <TB1> INFO: Test took 9908ms.
[11:04:35.696] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 13 .. 54 (-1/-1) hits flags = 528 (plus default)
[11:04:35.706] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:04:35.706] <TB1> INFO: run 1 of 1
[11:04:35.984] <TB1> INFO: Expecting 1397760 events.
[11:05:04.314] <TB1> INFO: 678904 events read in total (27738ms).
[11:05:32.198] <TB1> INFO: 1357560 events read in total (55622ms).
[11:05:34.271] <TB1> INFO: 1397760 events read in total (57696ms).
[11:05:34.295] <TB1> INFO: Test took 58588ms.
[11:05:47.573] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[11:05:47.573] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[11:05:47.585] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:05:47.585] <TB1> INFO: run 1 of 1
[11:05:47.904] <TB1> INFO: Expecting 1364480 events.
[11:06:16.083] <TB1> INFO: 667360 events read in total (27587ms).
[11:06:43.915] <TB1> INFO: 1333808 events read in total (55420ms).
[11:06:45.555] <TB1> INFO: 1364480 events read in total (57059ms).
[11:06:45.576] <TB1> INFO: Test took 57990ms.
[11:06:59.561] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C0.dat
[11:06:59.561] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C1.dat
[11:06:59.561] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C2.dat
[11:06:59.561] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C3.dat
[11:06:59.561] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C4.dat
[11:06:59.561] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C5.dat
[11:06:59.561] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C6.dat
[11:06:59.561] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C7.dat
[11:06:59.561] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C8.dat
[11:06:59.562] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C9.dat
[11:06:59.562] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C10.dat
[11:06:59.562] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C11.dat
[11:06:59.562] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C12.dat
[11:06:59.562] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C13.dat
[11:06:59.562] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C14.dat
[11:06:59.562] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C15.dat
[11:06:59.562] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C0.dat
[11:06:59.569] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C1.dat
[11:06:59.575] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C2.dat
[11:06:59.580] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C3.dat
[11:06:59.586] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C4.dat
[11:06:59.592] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C5.dat
[11:06:59.598] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C6.dat
[11:06:59.604] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C7.dat
[11:06:59.610] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C8.dat
[11:06:59.616] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C9.dat
[11:06:59.622] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C10.dat
[11:06:59.628] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C11.dat
[11:06:59.634] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C12.dat
[11:06:59.640] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C13.dat
[11:06:59.646] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C14.dat
[11:06:59.652] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//trimParameters35_C15.dat
[11:06:59.658] <TB1> INFO: PixTestTrim::trimTest() done
[11:06:59.658] <TB1> INFO: vtrim: 143 146 118 131 138 143 157 142 137 117 145 133 133 128 134 135
[11:06:59.658] <TB1> INFO: vthrcomp: 116 132 118 118 111 125 125 117 120 125 108 106 123 127 107 113
[11:06:59.658] <TB1> INFO: vcal mean: 34.97 35.00 34.96 34.94 34.97 34.96 34.97 34.99 34.96 34.96 35.09 35.01 34.96 35.02 34.96 34.97
[11:06:59.658] <TB1> INFO: vcal RMS: 1.12 1.02 1.10 0.99 0.98 1.02 1.07 1.10 1.15 1.17 1.22 0.93 1.02 1.16 0.99 1.01
[11:06:59.658] <TB1> INFO: bits mean: 9.84 9.20 9.76 9.84 9.23 9.89 10.22 9.81 10.03 9.69 9.19 8.59 9.73 9.81 8.67 9.87
[11:06:59.658] <TB1> INFO: bits RMS: 2.61 2.62 2.57 2.65 2.40 2.63 2.42 2.58 2.54 2.71 2.42 2.57 2.64 2.52 2.50 2.47
[11:06:59.665] <TB1> INFO: ----------------------------------------------------------------------
[11:06:59.665] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[11:06:59.665] <TB1> INFO: ----------------------------------------------------------------------
[11:06:59.668] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[11:06:59.678] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:06:59.678] <TB1> INFO: run 1 of 1
[11:06:59.928] <TB1> INFO: Expecting 4160000 events.
[11:07:31.401] <TB1> INFO: 745355 events read in total (30881ms).
[11:08:02.339] <TB1> INFO: 1484345 events read in total (61819ms).
[11:08:33.279] <TB1> INFO: 2218610 events read in total (92759ms).
[11:09:04.125] <TB1> INFO: 2945945 events read in total (123605ms).
[11:09:34.784] <TB1> INFO: 3672125 events read in total (154264ms).
[11:09:55.417] <TB1> INFO: 4160000 events read in total (174897ms).
[11:09:55.484] <TB1> INFO: Test took 175806ms.
[11:10:24.082] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[11:10:24.093] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:10:24.093] <TB1> INFO: run 1 of 1
[11:10:24.328] <TB1> INFO: Expecting 4139200 events.
[11:10:55.596] <TB1> INFO: 722090 events read in total (30676ms).
[11:11:25.954] <TB1> INFO: 1438595 events read in total (61034ms).
[11:11:56.313] <TB1> INFO: 2150950 events read in total (91393ms).
[11:12:26.285] <TB1> INFO: 2856185 events read in total (121365ms).
[11:12:56.515] <TB1> INFO: 3561215 events read in total (151595ms).
[11:13:21.544] <TB1> INFO: 4139200 events read in total (176624ms).
[11:13:21.617] <TB1> INFO: Test took 177524ms.
[11:13:52.617] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 195 (-1/-1) hits flags = 528 (plus default)
[11:13:52.627] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:13:52.627] <TB1> INFO: run 1 of 1
[11:13:52.869] <TB1> INFO: Expecting 4076800 events.
[11:14:24.120] <TB1> INFO: 726205 events read in total (30659ms).
[11:14:54.517] <TB1> INFO: 1446570 events read in total (61056ms).
[11:15:24.930] <TB1> INFO: 2162295 events read in total (91469ms).
[11:15:55.395] <TB1> INFO: 2871285 events read in total (121934ms).
[11:16:25.547] <TB1> INFO: 3579515 events read in total (152086ms).
[11:16:46.576] <TB1> INFO: 4076800 events read in total (173115ms).
[11:16:46.645] <TB1> INFO: Test took 174018ms.
[11:17:15.111] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 192 (-1/-1) hits flags = 528 (plus default)
[11:17:15.123] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:17:15.123] <TB1> INFO: run 1 of 1
[11:17:15.417] <TB1> INFO: Expecting 4014400 events.
[11:17:46.679] <TB1> INFO: 730155 events read in total (30670ms).
[11:18:17.199] <TB1> INFO: 1454530 events read in total (61190ms).
[11:18:47.870] <TB1> INFO: 2173870 events read in total (91861ms).
[11:19:18.145] <TB1> INFO: 2886820 events read in total (122136ms).
[11:19:48.454] <TB1> INFO: 3598070 events read in total (152445ms).
[11:20:06.496] <TB1> INFO: 4014400 events read in total (170487ms).
[11:20:06.550] <TB1> INFO: Test took 171426ms.
[11:20:33.489] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 192 (-1/-1) hits flags = 528 (plus default)
[11:20:33.501] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:20:33.501] <TB1> INFO: run 1 of 1
[11:20:33.787] <TB1> INFO: Expecting 4014400 events.
[11:21:05.635] <TB1> INFO: 730150 events read in total (31255ms).
[11:21:36.286] <TB1> INFO: 1454285 events read in total (61906ms).
[11:22:06.836] <TB1> INFO: 2173435 events read in total (92456ms).
[11:22:37.465] <TB1> INFO: 2886325 events read in total (123085ms).
[11:23:07.964] <TB1> INFO: 3597705 events read in total (153584ms).
[11:23:25.670] <TB1> INFO: 4014400 events read in total (171290ms).
[11:23:25.725] <TB1> INFO: Test took 172223ms.
[11:23:53.298] <TB1> INFO: PixTestTrim::trimBitTest() done
[11:23:53.299] <TB1> INFO: PixTestTrim::doTest() done, duration: 2445 seconds
[11:23:53.299] <TB1> INFO: Decoding statistics:
[11:23:53.299] <TB1> INFO: General information:
[11:23:53.299] <TB1> INFO: 16bit words read: 0
[11:23:53.299] <TB1> INFO: valid events total: 0
[11:23:53.299] <TB1> INFO: empty events: 0
[11:23:53.299] <TB1> INFO: valid events with pixels: 0
[11:23:53.299] <TB1> INFO: valid pixel hits: 0
[11:23:53.299] <TB1> INFO: Event errors: 0
[11:23:53.300] <TB1> INFO: start marker: 0
[11:23:53.300] <TB1> INFO: stop marker: 0
[11:23:53.300] <TB1> INFO: overflow: 0
[11:23:53.300] <TB1> INFO: invalid 5bit words: 0
[11:23:53.300] <TB1> INFO: invalid XOR eye diagram: 0
[11:23:53.300] <TB1> INFO: frame (failed synchr.): 0
[11:23:53.300] <TB1> INFO: idle data (no TBM trl): 0
[11:23:53.300] <TB1> INFO: no data (only TBM hdr): 0
[11:23:53.300] <TB1> INFO: TBM errors: 0
[11:23:53.300] <TB1> INFO: flawed TBM headers: 0
[11:23:53.300] <TB1> INFO: flawed TBM trailers: 0
[11:23:53.300] <TB1> INFO: event ID mismatches: 0
[11:23:53.300] <TB1> INFO: ROC errors: 0
[11:23:53.300] <TB1> INFO: missing ROC header(s): 0
[11:23:53.300] <TB1> INFO: misplaced readback start: 0
[11:23:53.300] <TB1> INFO: Pixel decoding errors: 0
[11:23:53.300] <TB1> INFO: pixel data incomplete: 0
[11:23:53.300] <TB1> INFO: pixel address: 0
[11:23:53.300] <TB1> INFO: pulse height fill bit: 0
[11:23:53.300] <TB1> INFO: buffer corruption: 0
[11:23:53.972] <TB1> INFO: ######################################################################
[11:23:53.972] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[11:23:53.972] <TB1> INFO: ######################################################################
[11:23:54.207] <TB1> INFO: Expecting 41600 events.
[11:23:57.660] <TB1> INFO: 41600 events read in total (2862ms).
[11:23:57.661] <TB1> INFO: Test took 3688ms.
[11:23:58.185] <TB1> INFO: Expecting 41600 events.
[11:24:01.774] <TB1> INFO: 41600 events read in total (2993ms).
[11:24:01.775] <TB1> INFO: Test took 3911ms.
[11:24:02.063] <TB1> INFO: Expecting 41600 events.
[11:24:05.611] <TB1> INFO: 41600 events read in total (2956ms).
[11:24:05.612] <TB1> INFO: Test took 3813ms.
[11:24:05.903] <TB1> INFO: Expecting 41600 events.
[11:24:09.454] <TB1> INFO: 41600 events read in total (2960ms).
[11:24:09.455] <TB1> INFO: Test took 3817ms.
[11:24:09.745] <TB1> INFO: Expecting 41600 events.
[11:24:13.326] <TB1> INFO: 41600 events read in total (2990ms).
[11:24:13.327] <TB1> INFO: Test took 3847ms.
[11:24:13.618] <TB1> INFO: Expecting 41600 events.
[11:24:17.224] <TB1> INFO: 41600 events read in total (3014ms).
[11:24:17.224] <TB1> INFO: Test took 3871ms.
[11:24:17.512] <TB1> INFO: Expecting 41600 events.
[11:24:21.040] <TB1> INFO: 41600 events read in total (2936ms).
[11:24:21.041] <TB1> INFO: Test took 3794ms.
[11:24:21.330] <TB1> INFO: Expecting 41600 events.
[11:24:24.953] <TB1> INFO: 41600 events read in total (3032ms).
[11:24:24.954] <TB1> INFO: Test took 3889ms.
[11:24:25.242] <TB1> INFO: Expecting 41600 events.
[11:24:28.729] <TB1> INFO: 41600 events read in total (2895ms).
[11:24:28.730] <TB1> INFO: Test took 3753ms.
[11:24:29.020] <TB1> INFO: Expecting 41600 events.
[11:24:32.608] <TB1> INFO: 41600 events read in total (2996ms).
[11:24:32.609] <TB1> INFO: Test took 3853ms.
[11:24:32.905] <TB1> INFO: Expecting 41600 events.
[11:24:36.514] <TB1> INFO: 41600 events read in total (3017ms).
[11:24:36.515] <TB1> INFO: Test took 3882ms.
[11:24:36.803] <TB1> INFO: Expecting 41600 events.
[11:24:40.355] <TB1> INFO: 41600 events read in total (2960ms).
[11:24:40.356] <TB1> INFO: Test took 3818ms.
[11:24:40.644] <TB1> INFO: Expecting 41600 events.
[11:24:44.163] <TB1> INFO: 41600 events read in total (2928ms).
[11:24:44.165] <TB1> INFO: Test took 3786ms.
[11:24:44.453] <TB1> INFO: Expecting 41600 events.
[11:24:47.988] <TB1> INFO: 41600 events read in total (2943ms).
[11:24:47.988] <TB1> INFO: Test took 3799ms.
[11:24:48.277] <TB1> INFO: Expecting 41600 events.
[11:24:51.803] <TB1> INFO: 41600 events read in total (2935ms).
[11:24:51.804] <TB1> INFO: Test took 3792ms.
[11:24:52.092] <TB1> INFO: Expecting 41600 events.
[11:24:55.557] <TB1> INFO: 41600 events read in total (2874ms).
[11:24:55.558] <TB1> INFO: Test took 3731ms.
[11:24:55.846] <TB1> INFO: Expecting 41600 events.
[11:24:59.349] <TB1> INFO: 41600 events read in total (2911ms).
[11:24:59.350] <TB1> INFO: Test took 3769ms.
[11:24:59.638] <TB1> INFO: Expecting 41600 events.
[11:25:03.278] <TB1> INFO: 41600 events read in total (3049ms).
[11:25:03.279] <TB1> INFO: Test took 3906ms.
[11:25:03.573] <TB1> INFO: Expecting 41600 events.
[11:25:07.034] <TB1> INFO: 41600 events read in total (2869ms).
[11:25:07.035] <TB1> INFO: Test took 3732ms.
[11:25:07.328] <TB1> INFO: Expecting 41600 events.
[11:25:10.890] <TB1> INFO: 41600 events read in total (2971ms).
[11:25:10.891] <TB1> INFO: Test took 3832ms.
[11:25:11.179] <TB1> INFO: Expecting 41600 events.
[11:25:14.720] <TB1> INFO: 41600 events read in total (2950ms).
[11:25:14.720] <TB1> INFO: Test took 3806ms.
[11:25:15.009] <TB1> INFO: Expecting 41600 events.
[11:25:18.622] <TB1> INFO: 41600 events read in total (3021ms).
[11:25:18.622] <TB1> INFO: Test took 3878ms.
[11:25:18.910] <TB1> INFO: Expecting 41600 events.
[11:25:22.524] <TB1> INFO: 41600 events read in total (3022ms).
[11:25:22.525] <TB1> INFO: Test took 3879ms.
[11:25:22.827] <TB1> INFO: Expecting 41600 events.
[11:25:26.427] <TB1> INFO: 41600 events read in total (3009ms).
[11:25:26.428] <TB1> INFO: Test took 3877ms.
[11:25:26.718] <TB1> INFO: Expecting 41600 events.
[11:25:30.226] <TB1> INFO: 41600 events read in total (2917ms).
[11:25:30.227] <TB1> INFO: Test took 3774ms.
[11:25:30.515] <TB1> INFO: Expecting 41600 events.
[11:25:33.963] <TB1> INFO: 41600 events read in total (2856ms).
[11:25:33.964] <TB1> INFO: Test took 3713ms.
[11:25:34.252] <TB1> INFO: Expecting 41600 events.
[11:25:37.823] <TB1> INFO: 41600 events read in total (2979ms).
[11:25:37.824] <TB1> INFO: Test took 3836ms.
[11:25:38.113] <TB1> INFO: Expecting 41600 events.
[11:25:41.740] <TB1> INFO: 41600 events read in total (3035ms).
[11:25:41.740] <TB1> INFO: Test took 3891ms.
[11:25:42.030] <TB1> INFO: Expecting 2560 events.
[11:25:42.914] <TB1> INFO: 2560 events read in total (293ms).
[11:25:42.914] <TB1> INFO: Test took 1161ms.
[11:25:43.222] <TB1> INFO: Expecting 2560 events.
[11:25:44.105] <TB1> INFO: 2560 events read in total (291ms).
[11:25:44.105] <TB1> INFO: Test took 1190ms.
[11:25:44.413] <TB1> INFO: Expecting 2560 events.
[11:25:45.301] <TB1> INFO: 2560 events read in total (296ms).
[11:25:45.301] <TB1> INFO: Test took 1196ms.
[11:25:45.609] <TB1> INFO: Expecting 2560 events.
[11:25:46.494] <TB1> INFO: 2560 events read in total (293ms).
[11:25:46.494] <TB1> INFO: Test took 1192ms.
[11:25:46.802] <TB1> INFO: Expecting 2560 events.
[11:25:47.680] <TB1> INFO: 2560 events read in total (286ms).
[11:25:47.680] <TB1> INFO: Test took 1185ms.
[11:25:47.988] <TB1> INFO: Expecting 2560 events.
[11:25:48.867] <TB1> INFO: 2560 events read in total (287ms).
[11:25:48.867] <TB1> INFO: Test took 1186ms.
[11:25:49.175] <TB1> INFO: Expecting 2560 events.
[11:25:50.053] <TB1> INFO: 2560 events read in total (287ms).
[11:25:50.053] <TB1> INFO: Test took 1186ms.
[11:25:50.361] <TB1> INFO: Expecting 2560 events.
[11:25:51.244] <TB1> INFO: 2560 events read in total (291ms).
[11:25:51.244] <TB1> INFO: Test took 1190ms.
[11:25:51.552] <TB1> INFO: Expecting 2560 events.
[11:25:52.443] <TB1> INFO: 2560 events read in total (300ms).
[11:25:52.443] <TB1> INFO: Test took 1199ms.
[11:25:52.751] <TB1> INFO: Expecting 2560 events.
[11:25:53.631] <TB1> INFO: 2560 events read in total (289ms).
[11:25:53.631] <TB1> INFO: Test took 1187ms.
[11:25:53.939] <TB1> INFO: Expecting 2560 events.
[11:25:54.818] <TB1> INFO: 2560 events read in total (288ms).
[11:25:54.818] <TB1> INFO: Test took 1186ms.
[11:25:55.126] <TB1> INFO: Expecting 2560 events.
[11:25:56.005] <TB1> INFO: 2560 events read in total (287ms).
[11:25:56.005] <TB1> INFO: Test took 1186ms.
[11:25:56.313] <TB1> INFO: Expecting 2560 events.
[11:25:57.195] <TB1> INFO: 2560 events read in total (291ms).
[11:25:57.195] <TB1> INFO: Test took 1189ms.
[11:25:57.503] <TB1> INFO: Expecting 2560 events.
[11:25:58.390] <TB1> INFO: 2560 events read in total (295ms).
[11:25:58.390] <TB1> INFO: Test took 1195ms.
[11:25:58.698] <TB1> INFO: Expecting 2560 events.
[11:25:59.579] <TB1> INFO: 2560 events read in total (290ms).
[11:25:59.580] <TB1> INFO: Test took 1190ms.
[11:25:59.888] <TB1> INFO: Expecting 2560 events.
[11:26:00.771] <TB1> INFO: 2560 events read in total (292ms).
[11:26:00.771] <TB1> INFO: Test took 1191ms.
[11:26:00.774] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:26:01.080] <TB1> INFO: Expecting 655360 events.
[11:26:15.448] <TB1> INFO: 655360 events read in total (13776ms).
[11:26:15.464] <TB1> INFO: Expecting 655360 events.
[11:26:29.694] <TB1> INFO: 655360 events read in total (13827ms).
[11:26:29.708] <TB1> INFO: Expecting 655360 events.
[11:26:43.861] <TB1> INFO: 655360 events read in total (13750ms).
[11:26:43.878] <TB1> INFO: Expecting 655360 events.
[11:26:57.000] <TB1> INFO: 655360 events read in total (13719ms).
[11:26:58.023] <TB1> INFO: Expecting 655360 events.
[11:27:12.201] <TB1> INFO: 655360 events read in total (13775ms).
[11:27:12.240] <TB1> INFO: Expecting 655360 events.
[11:27:26.412] <TB1> INFO: 655360 events read in total (13769ms).
[11:27:26.443] <TB1> INFO: Expecting 655360 events.
[11:27:40.538] <TB1> INFO: 655360 events read in total (13693ms).
[11:27:40.576] <TB1> INFO: Expecting 655360 events.
[11:27:54.715] <TB1> INFO: 655360 events read in total (13736ms).
[11:27:54.756] <TB1> INFO: Expecting 655360 events.
[11:28:08.771] <TB1> INFO: 655360 events read in total (13612ms).
[11:28:08.832] <TB1> INFO: Expecting 655360 events.
[11:28:22.935] <TB1> INFO: 655360 events read in total (13700ms).
[11:28:22.985] <TB1> INFO: Expecting 655360 events.
[11:28:37.134] <TB1> INFO: 655360 events read in total (13746ms).
[11:28:37.187] <TB1> INFO: Expecting 655360 events.
[11:28:51.356] <TB1> INFO: 655360 events read in total (13765ms).
[11:28:51.432] <TB1> INFO: Expecting 655360 events.
[11:29:05.521] <TB1> INFO: 655360 events read in total (13686ms).
[11:29:05.609] <TB1> INFO: Expecting 655360 events.
[11:29:19.762] <TB1> INFO: 655360 events read in total (13750ms).
[11:29:19.859] <TB1> INFO: Expecting 655360 events.
[11:29:34.027] <TB1> INFO: 655360 events read in total (13765ms).
[11:29:34.125] <TB1> INFO: Expecting 655360 events.
[11:29:48.124] <TB1> INFO: 655360 events read in total (13596ms).
[11:29:48.234] <TB1> INFO: Test took 227460ms.
[11:29:48.313] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:29:48.578] <TB1> INFO: Expecting 655360 events.
[11:30:02.587] <TB1> INFO: 655360 events read in total (13418ms).
[11:30:02.597] <TB1> INFO: Expecting 655360 events.
[11:30:16.708] <TB1> INFO: 655360 events read in total (13708ms).
[11:30:16.726] <TB1> INFO: Expecting 655360 events.
[11:30:30.893] <TB1> INFO: 655360 events read in total (13764ms).
[11:30:30.918] <TB1> INFO: Expecting 655360 events.
[11:30:44.997] <TB1> INFO: 655360 events read in total (13676ms).
[11:30:45.026] <TB1> INFO: Expecting 655360 events.
[11:30:58.994] <TB1> INFO: 655360 events read in total (13565ms).
[11:30:59.023] <TB1> INFO: Expecting 655360 events.
[11:31:12.744] <TB1> INFO: 655360 events read in total (13318ms).
[11:31:12.787] <TB1> INFO: Expecting 655360 events.
[11:31:26.696] <TB1> INFO: 655360 events read in total (13506ms).
[11:31:26.733] <TB1> INFO: Expecting 655360 events.
[11:31:40.658] <TB1> INFO: 655360 events read in total (13522ms).
[11:31:40.709] <TB1> INFO: Expecting 655360 events.
[11:31:54.665] <TB1> INFO: 655360 events read in total (13553ms).
[11:31:54.710] <TB1> INFO: Expecting 655360 events.
[11:32:08.579] <TB1> INFO: 655360 events read in total (13466ms).
[11:32:08.644] <TB1> INFO: Expecting 655360 events.
[11:32:22.573] <TB1> INFO: 655360 events read in total (13526ms).
[11:32:22.670] <TB1> INFO: Expecting 655360 events.
[11:32:36.354] <TB1> INFO: 655360 events read in total (13281ms).
[11:32:36.430] <TB1> INFO: Expecting 655360 events.
[11:32:50.580] <TB1> INFO: 655360 events read in total (13747ms).
[11:32:50.674] <TB1> INFO: Expecting 655360 events.
[11:33:04.662] <TB1> INFO: 655360 events read in total (13585ms).
[11:33:04.750] <TB1> INFO: Expecting 655360 events.
[11:33:18.900] <TB1> INFO: 655360 events read in total (13747ms).
[11:33:19.010] <TB1> INFO: Expecting 655360 events.
[11:33:33.073] <TB1> INFO: 655360 events read in total (13660ms).
[11:33:33.190] <TB1> INFO: Test took 224877ms.
[11:33:33.350] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.355] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.359] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.364] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:33:33.368] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:33:33.373] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[11:33:33.378] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[11:33:33.383] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[11:33:33.388] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[11:33:33.393] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[11:33:33.398] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[11:33:33.402] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[11:33:33.407] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.412] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.417] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.423] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.429] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:33:33.435] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:33:33.440] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[11:33:33.445] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[11:33:33.449] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[11:33:33.455] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[11:33:33.460] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[11:33:33.465] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.469] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.474] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.479] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.484] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.488] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.494] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.499] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.504] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:33:33.509] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:33:33.542] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C0.dat
[11:33:33.542] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C1.dat
[11:33:33.542] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C2.dat
[11:33:33.542] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C3.dat
[11:33:33.542] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C4.dat
[11:33:33.542] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C5.dat
[11:33:33.542] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C6.dat
[11:33:33.542] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C7.dat
[11:33:33.542] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C8.dat
[11:33:33.542] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C9.dat
[11:33:33.542] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C10.dat
[11:33:33.542] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C11.dat
[11:33:33.542] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C12.dat
[11:33:33.543] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C13.dat
[11:33:33.543] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C14.dat
[11:33:33.543] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//dacParameters35_C15.dat
[11:33:33.786] <TB1> INFO: Expecting 41600 events.
[11:33:36.894] <TB1> INFO: 41600 events read in total (2516ms).
[11:33:36.895] <TB1> INFO: Test took 3350ms.
[11:33:37.337] <TB1> INFO: Expecting 41600 events.
[11:33:40.375] <TB1> INFO: 41600 events read in total (2446ms).
[11:33:40.376] <TB1> INFO: Test took 3270ms.
[11:33:40.864] <TB1> INFO: Expecting 41600 events.
[11:33:43.933] <TB1> INFO: 41600 events read in total (2477ms).
[11:33:43.934] <TB1> INFO: Test took 3344ms.
[11:33:44.148] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:33:44.236] <TB1> INFO: Expecting 2560 events.
[11:33:45.118] <TB1> INFO: 2560 events read in total (291ms).
[11:33:45.118] <TB1> INFO: Test took 970ms.
[11:33:45.120] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:33:45.427] <TB1> INFO: Expecting 2560 events.
[11:33:46.309] <TB1> INFO: 2560 events read in total (291ms).
[11:33:46.310] <TB1> INFO: Test took 1190ms.
[11:33:46.311] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:33:46.618] <TB1> INFO: Expecting 2560 events.
[11:33:47.501] <TB1> INFO: 2560 events read in total (291ms).
[11:33:47.501] <TB1> INFO: Test took 1190ms.
[11:33:47.503] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:33:47.809] <TB1> INFO: Expecting 2560 events.
[11:33:48.694] <TB1> INFO: 2560 events read in total (293ms).
[11:33:48.695] <TB1> INFO: Test took 1192ms.
[11:33:48.697] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:33:48.003] <TB1> INFO: Expecting 2560 events.
[11:33:49.888] <TB1> INFO: 2560 events read in total (294ms).
[11:33:49.888] <TB1> INFO: Test took 1192ms.
[11:33:49.890] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:33:50.196] <TB1> INFO: Expecting 2560 events.
[11:33:51.082] <TB1> INFO: 2560 events read in total (294ms).
[11:33:51.082] <TB1> INFO: Test took 1192ms.
[11:33:51.084] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:33:51.391] <TB1> INFO: Expecting 2560 events.
[11:33:52.273] <TB1> INFO: 2560 events read in total (291ms).
[11:33:52.273] <TB1> INFO: Test took 1189ms.
[11:33:52.275] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:33:52.582] <TB1> INFO: Expecting 2560 events.
[11:33:53.465] <TB1> INFO: 2560 events read in total (292ms).
[11:33:53.465] <TB1> INFO: Test took 1190ms.
[11:33:53.467] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:33:53.774] <TB1> INFO: Expecting 2560 events.
[11:33:54.652] <TB1> INFO: 2560 events read in total (287ms).
[11:33:54.652] <TB1> INFO: Test took 1185ms.
[11:33:54.654] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:33:54.961] <TB1> INFO: Expecting 2560 events.
[11:33:55.842] <TB1> INFO: 2560 events read in total (290ms).
[11:33:55.842] <TB1> INFO: Test took 1188ms.
[11:33:55.843] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:33:56.151] <TB1> INFO: Expecting 2560 events.
[11:33:57.029] <TB1> INFO: 2560 events read in total (287ms).
[11:33:57.030] <TB1> INFO: Test took 1187ms.
[11:33:57.031] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:33:57.338] <TB1> INFO: Expecting 2560 events.
[11:33:58.220] <TB1> INFO: 2560 events read in total (291ms).
[11:33:58.220] <TB1> INFO: Test took 1189ms.
[11:33:58.222] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:33:58.528] <TB1> INFO: Expecting 2560 events.
[11:33:59.405] <TB1> INFO: 2560 events read in total (285ms).
[11:33:59.405] <TB1> INFO: Test took 1183ms.
[11:33:59.407] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:33:59.714] <TB1> INFO: Expecting 2560 events.
[11:34:00.591] <TB1> INFO: 2560 events read in total (286ms).
[11:34:00.592] <TB1> INFO: Test took 1185ms.
[11:34:00.594] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:00.900] <TB1> INFO: Expecting 2560 events.
[11:34:01.778] <TB1> INFO: 2560 events read in total (287ms).
[11:34:01.778] <TB1> INFO: Test took 1185ms.
[11:34:01.780] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:02.087] <TB1> INFO: Expecting 2560 events.
[11:34:02.965] <TB1> INFO: 2560 events read in total (287ms).
[11:34:02.965] <TB1> INFO: Test took 1185ms.
[11:34:02.968] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:03.274] <TB1> INFO: Expecting 2560 events.
[11:34:04.152] <TB1> INFO: 2560 events read in total (287ms).
[11:34:04.152] <TB1> INFO: Test took 1185ms.
[11:34:04.154] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:04.460] <TB1> INFO: Expecting 2560 events.
[11:34:05.339] <TB1> INFO: 2560 events read in total (287ms).
[11:34:05.339] <TB1> INFO: Test took 1185ms.
[11:34:05.342] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:05.647] <TB1> INFO: Expecting 2560 events.
[11:34:06.526] <TB1> INFO: 2560 events read in total (287ms).
[11:34:06.527] <TB1> INFO: Test took 1185ms.
[11:34:06.528] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:06.835] <TB1> INFO: Expecting 2560 events.
[11:34:07.714] <TB1> INFO: 2560 events read in total (288ms).
[11:34:07.714] <TB1> INFO: Test took 1186ms.
[11:34:07.716] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:08.022] <TB1> INFO: Expecting 2560 events.
[11:34:08.904] <TB1> INFO: 2560 events read in total (290ms).
[11:34:08.904] <TB1> INFO: Test took 1188ms.
[11:34:08.906] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:09.213] <TB1> INFO: Expecting 2560 events.
[11:34:10.091] <TB1> INFO: 2560 events read in total (287ms).
[11:34:10.091] <TB1> INFO: Test took 1185ms.
[11:34:10.093] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:10.399] <TB1> INFO: Expecting 2560 events.
[11:34:11.277] <TB1> INFO: 2560 events read in total (286ms).
[11:34:11.278] <TB1> INFO: Test took 1186ms.
[11:34:11.279] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:11.586] <TB1> INFO: Expecting 2560 events.
[11:34:12.467] <TB1> INFO: 2560 events read in total (289ms).
[11:34:12.467] <TB1> INFO: Test took 1188ms.
[11:34:12.469] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:12.776] <TB1> INFO: Expecting 2560 events.
[11:34:13.658] <TB1> INFO: 2560 events read in total (291ms).
[11:34:13.659] <TB1> INFO: Test took 1190ms.
[11:34:13.661] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:13.967] <TB1> INFO: Expecting 2560 events.
[11:34:14.852] <TB1> INFO: 2560 events read in total (294ms).
[11:34:14.852] <TB1> INFO: Test took 1191ms.
[11:34:14.854] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:15.160] <TB1> INFO: Expecting 2560 events.
[11:34:16.043] <TB1> INFO: 2560 events read in total (291ms).
[11:34:16.043] <TB1> INFO: Test took 1189ms.
[11:34:16.045] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:16.352] <TB1> INFO: Expecting 2560 events.
[11:34:17.235] <TB1> INFO: 2560 events read in total (292ms).
[11:34:17.235] <TB1> INFO: Test took 1190ms.
[11:34:17.237] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:17.544] <TB1> INFO: Expecting 2560 events.
[11:34:18.429] <TB1> INFO: 2560 events read in total (294ms).
[11:34:18.429] <TB1> INFO: Test took 1192ms.
[11:34:18.431] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:18.738] <TB1> INFO: Expecting 2560 events.
[11:34:19.621] <TB1> INFO: 2560 events read in total (292ms).
[11:34:19.622] <TB1> INFO: Test took 1191ms.
[11:34:19.624] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:19.930] <TB1> INFO: Expecting 2560 events.
[11:34:20.813] <TB1> INFO: 2560 events read in total (291ms).
[11:34:20.814] <TB1> INFO: Test took 1191ms.
[11:34:20.816] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:21.122] <TB1> INFO: Expecting 2560 events.
[11:34:22.004] <TB1> INFO: 2560 events read in total (291ms).
[11:34:22.004] <TB1> INFO: Test took 1188ms.
[11:34:22.468] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 628 seconds
[11:34:22.468] <TB1> INFO: PH scale (per ROC): 44 48 50 68 44 51 48 59 43 50 50 40 56 55 58 58
[11:34:22.468] <TB1> INFO: PH offset (per ROC): 110 93 112 120 109 134 101 122 111 108 130 106 117 117 114 131
[11:34:22.474] <TB1> INFO: Decoding statistics:
[11:34:22.474] <TB1> INFO: General information:
[11:34:22.474] <TB1> INFO: 16bit words read: 127878
[11:34:22.474] <TB1> INFO: valid events total: 20480
[11:34:22.474] <TB1> INFO: empty events: 17981
[11:34:22.474] <TB1> INFO: valid events with pixels: 2499
[11:34:22.474] <TB1> INFO: valid pixel hits: 2499
[11:34:22.474] <TB1> INFO: Event errors: 0
[11:34:22.474] <TB1> INFO: start marker: 0
[11:34:22.474] <TB1> INFO: stop marker: 0
[11:34:22.474] <TB1> INFO: overflow: 0
[11:34:22.474] <TB1> INFO: invalid 5bit words: 0
[11:34:22.474] <TB1> INFO: invalid XOR eye diagram: 0
[11:34:22.474] <TB1> INFO: frame (failed synchr.): 0
[11:34:22.474] <TB1> INFO: idle data (no TBM trl): 0
[11:34:22.474] <TB1> INFO: no data (only TBM hdr): 0
[11:34:22.474] <TB1> INFO: TBM errors: 0
[11:34:22.474] <TB1> INFO: flawed TBM headers: 0
[11:34:22.474] <TB1> INFO: flawed TBM trailers: 0
[11:34:22.474] <TB1> INFO: event ID mismatches: 0
[11:34:22.474] <TB1> INFO: ROC errors: 0
[11:34:22.474] <TB1> INFO: missing ROC header(s): 0
[11:34:22.474] <TB1> INFO: misplaced readback start: 0
[11:34:22.474] <TB1> INFO: Pixel decoding errors: 0
[11:34:22.474] <TB1> INFO: pixel data incomplete: 0
[11:34:22.474] <TB1> INFO: pixel address: 0
[11:34:22.474] <TB1> INFO: pulse height fill bit: 0
[11:34:22.474] <TB1> INFO: buffer corruption: 0
[11:34:22.739] <TB1> INFO: ######################################################################
[11:34:22.739] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[11:34:22.739] <TB1> INFO: ######################################################################
[11:34:22.752] <TB1> INFO: scanning low vcal = 10
[11:34:22.984] <TB1> INFO: Expecting 41600 events.
[11:34:26.526] <TB1> INFO: 41600 events read in total (2951ms).
[11:34:26.526] <TB1> INFO: Test took 3774ms.
[11:34:26.528] <TB1> INFO: scanning low vcal = 20
[11:34:26.827] <TB1> INFO: Expecting 41600 events.
[11:34:30.368] <TB1> INFO: 41600 events read in total (2949ms).
[11:34:30.368] <TB1> INFO: Test took 3840ms.
[11:34:30.370] <TB1> INFO: scanning low vcal = 30
[11:34:30.669] <TB1> INFO: Expecting 41600 events.
[11:34:34.296] <TB1> INFO: 41600 events read in total (3035ms).
[11:34:34.297] <TB1> INFO: Test took 3927ms.
[11:34:34.299] <TB1> INFO: scanning low vcal = 40
[11:34:34.578] <TB1> INFO: Expecting 41600 events.
[11:34:38.489] <TB1> INFO: 41600 events read in total (3319ms).
[11:34:38.491] <TB1> INFO: Test took 4192ms.
[11:34:38.493] <TB1> INFO: scanning low vcal = 50
[11:34:38.770] <TB1> INFO: Expecting 41600 events.
[11:34:42.728] <TB1> INFO: 41600 events read in total (3366ms).
[11:34:42.729] <TB1> INFO: Test took 4236ms.
[11:34:42.731] <TB1> INFO: scanning low vcal = 60
[11:34:43.008] <TB1> INFO: Expecting 41600 events.
[11:34:46.954] <TB1> INFO: 41600 events read in total (3354ms).
[11:34:46.955] <TB1> INFO: Test took 4223ms.
[11:34:46.958] <TB1> INFO: scanning low vcal = 70
[11:34:47.234] <TB1> INFO: Expecting 41600 events.
[11:34:51.167] <TB1> INFO: 41600 events read in total (3341ms).
[11:34:51.168] <TB1> INFO: Test took 4210ms.
[11:34:51.171] <TB1> INFO: scanning low vcal = 80
[11:34:51.447] <TB1> INFO: Expecting 41600 events.
[11:34:55.403] <TB1> INFO: 41600 events read in total (3364ms).
[11:34:55.404] <TB1> INFO: Test took 4233ms.
[11:34:55.406] <TB1> INFO: scanning low vcal = 90
[11:34:55.683] <TB1> INFO: Expecting 41600 events.
[11:34:59.622] <TB1> INFO: 41600 events read in total (3347ms).
[11:34:59.623] <TB1> INFO: Test took 4216ms.
[11:34:59.625] <TB1> INFO: scanning low vcal = 100
[11:34:59.902] <TB1> INFO: Expecting 41600 events.
[11:35:03.857] <TB1> INFO: 41600 events read in total (3363ms).
[11:35:03.857] <TB1> INFO: Test took 4232ms.
[11:35:03.860] <TB1> INFO: scanning low vcal = 110
[11:35:04.141] <TB1> INFO: Expecting 41600 events.
[11:35:08.093] <TB1> INFO: 41600 events read in total (3361ms).
[11:35:08.093] <TB1> INFO: Test took 4232ms.
[11:35:08.096] <TB1> INFO: scanning low vcal = 120
[11:35:08.374] <TB1> INFO: Expecting 41600 events.
[11:35:12.304] <TB1> INFO: 41600 events read in total (3338ms).
[11:35:12.305] <TB1> INFO: Test took 4209ms.
[11:35:12.308] <TB1> INFO: scanning low vcal = 130
[11:35:12.584] <TB1> INFO: Expecting 41600 events.
[11:35:16.517] <TB1> INFO: 41600 events read in total (3341ms).
[11:35:16.517] <TB1> INFO: Test took 4209ms.
[11:35:16.520] <TB1> INFO: scanning low vcal = 140
[11:35:16.796] <TB1> INFO: Expecting 41600 events.
[11:35:20.723] <TB1> INFO: 41600 events read in total (3335ms).
[11:35:20.724] <TB1> INFO: Test took 4204ms.
[11:35:20.727] <TB1> INFO: scanning low vcal = 150
[11:35:21.003] <TB1> INFO: Expecting 41600 events.
[11:35:24.950] <TB1> INFO: 41600 events read in total (3355ms).
[11:35:24.951] <TB1> INFO: Test took 4224ms.
[11:35:24.953] <TB1> INFO: scanning low vcal = 160
[11:35:25.230] <TB1> INFO: Expecting 41600 events.
[11:35:29.177] <TB1> INFO: 41600 events read in total (3356ms).
[11:35:29.178] <TB1> INFO: Test took 4224ms.
[11:35:29.181] <TB1> INFO: scanning low vcal = 170
[11:35:29.458] <TB1> INFO: Expecting 41600 events.
[11:35:33.498] <TB1> INFO: 41600 events read in total (3449ms).
[11:35:33.499] <TB1> INFO: Test took 4318ms.
[11:35:33.502] <TB1> INFO: scanning low vcal = 180
[11:35:33.787] <TB1> INFO: Expecting 41600 events.
[11:35:37.786] <TB1> INFO: 41600 events read in total (3408ms).
[11:35:37.787] <TB1> INFO: Test took 4285ms.
[11:35:37.789] <TB1> INFO: scanning low vcal = 190
[11:35:38.066] <TB1> INFO: Expecting 41600 events.
[11:35:42.078] <TB1> INFO: 41600 events read in total (3420ms).
[11:35:42.079] <TB1> INFO: Test took 4290ms.
[11:35:42.081] <TB1> INFO: scanning low vcal = 200
[11:35:42.358] <TB1> INFO: Expecting 41600 events.
[11:35:46.362] <TB1> INFO: 41600 events read in total (3412ms).
[11:35:46.363] <TB1> INFO: Test took 4282ms.
[11:35:46.366] <TB1> INFO: scanning low vcal = 210
[11:35:46.655] <TB1> INFO: Expecting 41600 events.
[11:35:50.664] <TB1> INFO: 41600 events read in total (3417ms).
[11:35:50.665] <TB1> INFO: Test took 4299ms.
[11:35:50.668] <TB1> INFO: scanning low vcal = 220
[11:35:50.944] <TB1> INFO: Expecting 41600 events.
[11:35:55.054] <TB1> INFO: 41600 events read in total (3518ms).
[11:35:55.054] <TB1> INFO: Test took 4386ms.
[11:35:55.057] <TB1> INFO: scanning low vcal = 230
[11:35:55.334] <TB1> INFO: Expecting 41600 events.
[11:35:59.291] <TB1> INFO: 41600 events read in total (3365ms).
[11:35:59.292] <TB1> INFO: Test took 4234ms.
[11:35:59.295] <TB1> INFO: scanning low vcal = 240
[11:35:59.572] <TB1> INFO: Expecting 41600 events.
[11:36:03.552] <TB1> INFO: 41600 events read in total (3389ms).
[11:36:03.553] <TB1> INFO: Test took 4258ms.
[11:36:03.555] <TB1> INFO: scanning low vcal = 250
[11:36:03.832] <TB1> INFO: Expecting 41600 events.
[11:36:07.875] <TB1> INFO: 41600 events read in total (3451ms).
[11:36:07.876] <TB1> INFO: Test took 4320ms.
[11:36:07.880] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[11:36:08.190] <TB1> INFO: Expecting 41600 events.
[11:36:12.160] <TB1> INFO: 41600 events read in total (3378ms).
[11:36:12.160] <TB1> INFO: Test took 4280ms.
[11:36:12.163] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[11:36:12.474] <TB1> INFO: Expecting 41600 events.
[11:36:16.455] <TB1> INFO: 41600 events read in total (3389ms).
[11:36:16.456] <TB1> INFO: Test took 4293ms.
[11:36:16.458] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[11:36:16.735] <TB1> INFO: Expecting 41600 events.
[11:36:20.747] <TB1> INFO: 41600 events read in total (3420ms).
[11:36:20.748] <TB1> INFO: Test took 4289ms.
[11:36:20.751] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[11:36:21.057] <TB1> INFO: Expecting 41600 events.
[11:36:25.042] <TB1> INFO: 41600 events read in total (3393ms).
[11:36:25.043] <TB1> INFO: Test took 4292ms.
[11:36:25.045] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[11:36:25.322] <TB1> INFO: Expecting 41600 events.
[11:36:29.283] <TB1> INFO: 41600 events read in total (3369ms).
[11:36:29.284] <TB1> INFO: Test took 4239ms.
[11:36:29.689] <TB1> INFO: PixTestGainPedestal::measure() done
[11:37:01.771] <TB1> INFO: PixTestGainPedestal::fit() done
[11:37:01.772] <TB1> INFO: non-linearity mean: 0.938 0.944 0.964 0.986 0.918 0.980 0.963 0.984 0.925 0.948 0.977 1.027 0.976 0.983 0.966 0.981
[11:37:01.772] <TB1> INFO: non-linearity RMS: 0.082 0.069 0.022 0.003 0.147 0.005 0.022 0.004 0.129 0.056 0.004 0.161 0.006 0.003 0.022 0.004
[11:37:01.772] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[11:37:01.795] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[11:37:01.818] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[11:37:01.841] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[11:37:01.864] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[11:37:01.887] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[11:37:01.910] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[11:37:01.933] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[11:37:01.956] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[11:37:01.979] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[11:37:01.002] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[11:37:02.025] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[11:37:02.047] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[11:37:02.070] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[11:37:02.093] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[11:37:02.116] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[11:37:02.139] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 159 seconds
[11:37:02.139] <TB1> INFO: Decoding statistics:
[11:37:02.139] <TB1> INFO: General information:
[11:37:02.139] <TB1> INFO: 16bit words read: 3328012
[11:37:02.139] <TB1> INFO: valid events total: 332800
[11:37:02.139] <TB1> INFO: empty events: 0
[11:37:02.139] <TB1> INFO: valid events with pixels: 332800
[11:37:02.139] <TB1> INFO: valid pixel hits: 665606
[11:37:02.139] <TB1> INFO: Event errors: 0
[11:37:02.139] <TB1> INFO: start marker: 0
[11:37:02.139] <TB1> INFO: stop marker: 0
[11:37:02.139] <TB1> INFO: overflow: 0
[11:37:02.139] <TB1> INFO: invalid 5bit words: 0
[11:37:02.139] <TB1> INFO: invalid XOR eye diagram: 0
[11:37:02.139] <TB1> INFO: frame (failed synchr.): 0
[11:37:02.139] <TB1> INFO: idle data (no TBM trl): 0
[11:37:02.139] <TB1> INFO: no data (only TBM hdr): 0
[11:37:02.139] <TB1> INFO: TBM errors: 0
[11:37:02.139] <TB1> INFO: flawed TBM headers: 0
[11:37:02.139] <TB1> INFO: flawed TBM trailers: 0
[11:37:02.139] <TB1> INFO: event ID mismatches: 0
[11:37:02.139] <TB1> INFO: ROC errors: 0
[11:37:02.139] <TB1> INFO: missing ROC header(s): 0
[11:37:02.139] <TB1> INFO: misplaced readback start: 0
[11:37:02.139] <TB1> INFO: Pixel decoding errors: 0
[11:37:02.139] <TB1> INFO: pixel data incomplete: 0
[11:37:02.139] <TB1> INFO: pixel address: 0
[11:37:02.139] <TB1> INFO: pulse height fill bit: 0
[11:37:02.139] <TB1> INFO: buffer corruption: 0
[11:37:02.160] <TB1> INFO: Decoding statistics:
[11:37:02.160] <TB1> INFO: General information:
[11:37:02.160] <TB1> INFO: 16bit words read: 3457426
[11:37:02.160] <TB1> INFO: valid events total: 353536
[11:37:02.160] <TB1> INFO: empty events: 18237
[11:37:02.160] <TB1> INFO: valid events with pixels: 335299
[11:37:02.160] <TB1> INFO: valid pixel hits: 668105
[11:37:02.160] <TB1> INFO: Event errors: 0
[11:37:02.160] <TB1> INFO: start marker: 0
[11:37:02.160] <TB1> INFO: stop marker: 0
[11:37:02.160] <TB1> INFO: overflow: 0
[11:37:02.160] <TB1> INFO: invalid 5bit words: 0
[11:37:02.161] <TB1> INFO: invalid XOR eye diagram: 0
[11:37:02.161] <TB1> INFO: frame (failed synchr.): 0
[11:37:02.161] <TB1> INFO: idle data (no TBM trl): 0
[11:37:02.161] <TB1> INFO: no data (only TBM hdr): 0
[11:37:02.161] <TB1> INFO: TBM errors: 0
[11:37:02.161] <TB1> INFO: flawed TBM headers: 0
[11:37:02.161] <TB1> INFO: flawed TBM trailers: 0
[11:37:02.161] <TB1> INFO: event ID mismatches: 0
[11:37:02.161] <TB1> INFO: ROC errors: 0
[11:37:02.161] <TB1> INFO: missing ROC header(s): 0
[11:37:02.161] <TB1> INFO: misplaced readback start: 0
[11:37:02.161] <TB1> INFO: Pixel decoding errors: 0
[11:37:02.161] <TB1> INFO: pixel data incomplete: 0
[11:37:02.161] <TB1> INFO: pixel address: 0
[11:37:02.161] <TB1> INFO: pulse height fill bit: 0
[11:37:02.161] <TB1> INFO: buffer corruption: 0
[11:37:02.161] <TB1> INFO: enter test to run
[11:37:02.161] <TB1> INFO: test: exit no parameter change
[11:37:02.217] <TB1> QUIET: Connection to board 153 closed.
[11:37:02.218] <TB1> INFO: pXar: this is the end, my friend