[11:56:04.628] <TB1> INFO: *** Welcome to pxar ***
[11:56:04.628] <TB1> INFO: *** Today: 2016/11/03
[11:56:04.635] <TB1> INFO: *** Version: c8ba-dirty
[11:56:04.635] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C15.dat
[11:56:04.636] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[11:56:04.636] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//defaultMaskFile.dat
[11:56:04.636] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters_C15.dat
[11:56:04.733] <TB1> INFO: clk: 4
[11:56:04.733] <TB1> INFO: ctr: 4
[11:56:04.733] <TB1> INFO: sda: 19
[11:56:04.733] <TB1> INFO: tin: 9
[11:56:04.733] <TB1> INFO: level: 15
[11:56:04.733] <TB1> INFO: triggerdelay: 0
[11:56:04.733] <TB1> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[11:56:04.733] <TB1> INFO: Log level: INFO
[11:56:04.744] <TB1> INFO: Found DTB DTB_WXBYFL
[11:56:04.754] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[11:56:04.756] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
------------------------------------------------------
[11:56:04.757] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[11:56:06.240] <TB1> INFO: DUT info:
[11:56:06.240] <TB1> INFO: The DUT currently contains the following objects:
[11:56:06.240] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[11:56:06.240] <TB1> INFO: TBM Core alpha (0): 7 registers set
[11:56:06.240] <TB1> INFO: TBM Core beta (1): 7 registers set
[11:56:06.240] <TB1> INFO: TBM Core alpha (2): 7 registers set
[11:56:06.240] <TB1> INFO: TBM Core beta (3): 7 registers set
[11:56:06.240] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:56:06.240] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.240] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.240] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.240] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.240] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.240] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.240] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.240] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.240] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.240] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.241] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.241] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.241] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.241] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.241] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.241] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:56:06.641] <TB1> INFO: enter 'restricted' command line mode
[11:56:06.641] <TB1> INFO: enter test to run
[11:56:06.641] <TB1> INFO: test: pretest no parameter change
[11:56:06.641] <TB1> INFO: running: pretest
[11:56:07.221] <TB1> INFO: ######################################################################
[11:56:07.221] <TB1> INFO: PixTestPretest::doTest()
[11:56:07.221] <TB1> INFO: ######################################################################
[11:56:07.223] <TB1> INFO: ----------------------------------------------------------------------
[11:56:07.223] <TB1> INFO: PixTestPretest::programROC()
[11:56:07.223] <TB1> INFO: ----------------------------------------------------------------------
[11:56:25.236] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:56:25.236] <TB1> INFO: IA differences per ROC: 20.9 19.3 16.9 19.3 19.3 18.5 20.9 19.3 16.1 18.5 16.9 19.3 20.1 17.7 18.5 20.9
[11:56:25.272] <TB1> INFO: ----------------------------------------------------------------------
[11:56:25.272] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:56:25.272] <TB1> INFO: ----------------------------------------------------------------------
[11:56:33.557] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 386.7 mA = 24.1687 mA/ROC
[11:56:33.557] <TB1> INFO: i(loss) [mA/ROC]: 20.1 20.1 20.1 20.1 19.3 20.1 20.1 19.3 20.1 19.3 20.1 19.3 20.1 20.1 19.3 20.1
[11:56:33.586] <TB1> INFO: ----------------------------------------------------------------------
[11:56:33.586] <TB1> INFO: PixTestPretest::findTiming()
[11:56:33.586] <TB1> INFO: ----------------------------------------------------------------------
[11:56:33.586] <TB1> INFO: PixTestCmd::init()

[11:57:04.908] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 6, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:57:04.908] <TB1> INFO: (success/tries = 100/100), width = 4
[11:57:06.408] <TB1> INFO: ----------------------------------------------------------------------
[11:57:06.409] <TB1> INFO: PixTestPretest::findWorkingPixel()
[11:57:06.409] <TB1> INFO: ----------------------------------------------------------------------
[11:57:06.500] <TB1> INFO: Expecting 231680 events.
[11:57:16.091] <TB1> INFO: 231680 events read in total (8999ms).
[11:57:16.098] <TB1> INFO: Test took 9687ms.
[11:57:16.344] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:57:16.373] <TB1> INFO: ----------------------------------------------------------------------
[11:57:16.373] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[11:57:16.373] <TB1> INFO: ----------------------------------------------------------------------
[11:57:16.465] <TB1> INFO: Expecting 231680 events.
[11:57:26.046] <TB1> INFO: 231680 events read in total (8989ms).
[11:57:26.055] <TB1> INFO: Test took 9678ms.
[11:57:26.311] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[11:57:26.311] <TB1> INFO: CalDel: 88 99 92 91 98 93 88 105 82 78 93 98 96 82 95 97
[11:57:26.311] <TB1> INFO: VthrComp: 51 52 53 51 51 51 53 51 51 55 51 51 51 51 51 51
[11:57:26.314] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C0.dat
[11:57:26.314] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C1.dat
[11:57:26.314] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C2.dat
[11:57:26.314] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C3.dat
[11:57:26.314] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C4.dat
[11:57:26.314] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C5.dat
[11:57:26.314] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C6.dat
[11:57:26.314] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C7.dat
[11:57:26.314] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C8.dat
[11:57:26.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C9.dat
[11:57:26.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C10.dat
[11:57:26.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C11.dat
[11:57:26.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C12.dat
[11:57:26.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C13.dat
[11:57:26.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C14.dat
[11:57:26.315] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters_C15.dat
[11:57:26.315] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[11:57:26.315] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[11:57:26.315] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[11:57:26.315] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[11:57:26.315] <TB1> INFO: PixTestPretest::doTest() done, duration: 79 seconds
[11:57:26.414] <TB1> INFO: enter test to run
[11:57:26.414] <TB1> INFO: test: fulltest no parameter change
[11:57:26.414] <TB1> INFO: running: fulltest
[11:57:26.414] <TB1> INFO: ######################################################################
[11:57:26.414] <TB1> INFO: PixTestFullTest::doTest()
[11:57:26.414] <TB1> INFO: ######################################################################
[11:57:26.415] <TB1> INFO: ######################################################################
[11:57:26.415] <TB1> INFO: PixTestAlive::doTest()
[11:57:26.415] <TB1> INFO: ######################################################################
[11:57:26.416] <TB1> INFO: ----------------------------------------------------------------------
[11:57:26.416] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:57:26.416] <TB1> INFO: ----------------------------------------------------------------------
[11:57:26.650] <TB1> INFO: Expecting 41600 events.
[11:57:30.128] <TB1> INFO: 41600 events read in total (2887ms).
[11:57:30.128] <TB1> INFO: Test took 3710ms.
[11:57:30.356] <TB1> INFO: PixTestAlive::aliveTest() done
[11:57:30.356] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:57:30.357] <TB1> INFO: ----------------------------------------------------------------------
[11:57:30.357] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:57:30.357] <TB1> INFO: ----------------------------------------------------------------------
[11:57:30.592] <TB1> INFO: Expecting 41600 events.
[11:57:33.593] <TB1> INFO: 41600 events read in total (2410ms).
[11:57:33.593] <TB1> INFO: Test took 3235ms.
[11:57:33.593] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:57:33.834] <TB1> INFO: PixTestAlive::maskTest() done
[11:57:33.834] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:57:33.835] <TB1> INFO: ----------------------------------------------------------------------
[11:57:33.835] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:57:33.835] <TB1> INFO: ----------------------------------------------------------------------
[11:57:34.110] <TB1> INFO: Expecting 41600 events.
[11:57:37.666] <TB1> INFO: 41600 events read in total (2964ms).
[11:57:37.666] <TB1> INFO: Test took 3829ms.
[11:57:37.898] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[11:57:37.898] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:57:37.899] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:57:37.899] <TB1> INFO: Decoding statistics:
[11:57:37.899] <TB1> INFO: General information:
[11:57:37.899] <TB1> INFO: 16bit words read: 0
[11:57:37.899] <TB1> INFO: valid events total: 0
[11:57:37.899] <TB1> INFO: empty events: 0
[11:57:37.899] <TB1> INFO: valid events with pixels: 0
[11:57:37.899] <TB1> INFO: valid pixel hits: 0
[11:57:37.899] <TB1> INFO: Event errors: 0
[11:57:37.899] <TB1> INFO: start marker: 0
[11:57:37.899] <TB1> INFO: stop marker: 0
[11:57:37.899] <TB1> INFO: overflow: 0
[11:57:37.899] <TB1> INFO: invalid 5bit words: 0
[11:57:37.899] <TB1> INFO: invalid XOR eye diagram: 0
[11:57:37.899] <TB1> INFO: frame (failed synchr.): 0
[11:57:37.899] <TB1> INFO: idle data (no TBM trl): 0
[11:57:37.899] <TB1> INFO: no data (only TBM hdr): 0
[11:57:37.899] <TB1> INFO: TBM errors: 0
[11:57:37.899] <TB1> INFO: flawed TBM headers: 0
[11:57:37.899] <TB1> INFO: flawed TBM trailers: 0
[11:57:37.899] <TB1> INFO: event ID mismatches: 0
[11:57:37.899] <TB1> INFO: ROC errors: 0
[11:57:37.899] <TB1> INFO: missing ROC header(s): 0
[11:57:37.899] <TB1> INFO: misplaced readback start: 0
[11:57:37.899] <TB1> INFO: Pixel decoding errors: 0
[11:57:37.899] <TB1> INFO: pixel data incomplete: 0
[11:57:37.899] <TB1> INFO: pixel address: 0
[11:57:37.899] <TB1> INFO: pulse height fill bit: 0
[11:57:37.899] <TB1> INFO: buffer corruption: 0
[11:57:37.908] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:57:37.908] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[11:57:37.908] <TB1> INFO: ######################################################################
[11:57:37.908] <TB1> INFO: PixTestReadback::doTest()
[11:57:37.908] <TB1> INFO: ######################################################################
[11:57:37.908] <TB1> INFO: ----------------------------------------------------------------------
[11:57:37.908] <TB1> INFO: PixTestReadback::CalibrateVd()
[11:57:37.908] <TB1> INFO: ----------------------------------------------------------------------
[11:57:47.869] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C0.dat
[11:57:47.869] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C1.dat
[11:57:47.869] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C2.dat
[11:57:47.869] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C3.dat
[11:57:47.869] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C4.dat
[11:57:47.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C5.dat
[11:57:47.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C6.dat
[11:57:47.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C7.dat
[11:57:47.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C8.dat
[11:57:47.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C9.dat
[11:57:47.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C10.dat
[11:57:47.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C11.dat
[11:57:47.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C12.dat
[11:57:47.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C13.dat
[11:57:47.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C14.dat
[11:57:47.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:57:47.897] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:57:47.898] <TB1> INFO: ----------------------------------------------------------------------
[11:57:47.898] <TB1> INFO: PixTestReadback::CalibrateVa()
[11:57:47.898] <TB1> INFO: ----------------------------------------------------------------------
[11:57:57.790] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C0.dat
[11:57:57.790] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C1.dat
[11:57:57.790] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C2.dat
[11:57:57.791] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C3.dat
[11:57:57.791] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C4.dat
[11:57:57.791] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C5.dat
[11:57:57.791] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C6.dat
[11:57:57.791] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C7.dat
[11:57:57.791] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C8.dat
[11:57:57.791] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C9.dat
[11:57:57.791] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C10.dat
[11:57:57.791] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C11.dat
[11:57:57.791] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C12.dat
[11:57:57.791] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C13.dat
[11:57:57.791] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C14.dat
[11:57:57.792] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:57:57.820] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:57:57.820] <TB1> INFO: ----------------------------------------------------------------------
[11:57:57.821] <TB1> INFO: PixTestReadback::readbackVbg()
[11:57:57.821] <TB1> INFO: ----------------------------------------------------------------------
[11:58:05.463] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:58:05.463] <TB1> INFO: ----------------------------------------------------------------------
[11:58:05.463] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[11:58:05.463] <TB1> INFO: ----------------------------------------------------------------------
[11:58:05.463] <TB1> INFO: Vbg will be calibrated using Vd calibration
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 146calibrated Vbg = 1.16608 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 155.5calibrated Vbg = 1.17211 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 149.8calibrated Vbg = 1.16362 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 148.3calibrated Vbg = 1.15774 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 157.4calibrated Vbg = 1.1695 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 150.4calibrated Vbg = 1.17302 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 160.2calibrated Vbg = 1.17275 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 154.8calibrated Vbg = 1.17116 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 158.3calibrated Vbg = 1.16208 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 155.1calibrated Vbg = 1.16135 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 155.8calibrated Vbg = 1.15868 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 157.6calibrated Vbg = 1.15235 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 150.1calibrated Vbg = 1.16508 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 153.1calibrated Vbg = 1.16788 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 159calibrated Vbg = 1.16211 :::*/*/*/*/
[11:58:05.463] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 149.8calibrated Vbg = 1.16473 :::*/*/*/*/
[11:58:05.465] <TB1> INFO: ----------------------------------------------------------------------
[11:58:05.465] <TB1> INFO: PixTestReadback::CalibrateIa()
[11:58:05.465] <TB1> INFO: ----------------------------------------------------------------------
[12:00:45.753] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:00:45.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:00:45.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:00:45.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:00:45.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:00:45.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:00:45.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:00:45.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:00:45.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:00:45.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:00:45.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:00:45.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:00:45.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:00:45.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:00:45.754] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:00:45.755] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:00:45.782] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:00:45.783] <TB1> INFO: PixTestReadback::doTest() done
[12:00:45.783] <TB1> INFO: Decoding statistics:
[12:00:45.784] <TB1> INFO: General information:
[12:00:45.784] <TB1> INFO: 16bit words read: 1536
[12:00:45.784] <TB1> INFO: valid events total: 256
[12:00:45.784] <TB1> INFO: empty events: 256
[12:00:45.784] <TB1> INFO: valid events with pixels: 0
[12:00:45.784] <TB1> INFO: valid pixel hits: 0
[12:00:45.784] <TB1> INFO: Event errors: 0
[12:00:45.784] <TB1> INFO: start marker: 0
[12:00:45.784] <TB1> INFO: stop marker: 0
[12:00:45.784] <TB1> INFO: overflow: 0
[12:00:45.784] <TB1> INFO: invalid 5bit words: 0
[12:00:45.784] <TB1> INFO: invalid XOR eye diagram: 0
[12:00:45.784] <TB1> INFO: frame (failed synchr.): 0
[12:00:45.784] <TB1> INFO: idle data (no TBM trl): 0
[12:00:45.784] <TB1> INFO: no data (only TBM hdr): 0
[12:00:45.784] <TB1> INFO: TBM errors: 0
[12:00:45.784] <TB1> INFO: flawed TBM headers: 0
[12:00:45.784] <TB1> INFO: flawed TBM trailers: 0
[12:00:45.784] <TB1> INFO: event ID mismatches: 0
[12:00:45.784] <TB1> INFO: ROC errors: 0
[12:00:45.784] <TB1> INFO: missing ROC header(s): 0
[12:00:45.784] <TB1> INFO: misplaced readback start: 0
[12:00:45.784] <TB1> INFO: Pixel decoding errors: 0
[12:00:45.784] <TB1> INFO: pixel data incomplete: 0
[12:00:45.784] <TB1> INFO: pixel address: 0
[12:00:45.784] <TB1> INFO: pulse height fill bit: 0
[12:00:45.784] <TB1> INFO: buffer corruption: 0
[12:00:45.831] <TB1> INFO: ######################################################################
[12:00:45.831] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:00:45.831] <TB1> INFO: ######################################################################
[12:00:45.834] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:00:45.846] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:00:45.846] <TB1> INFO: run 1 of 1
[12:00:46.077] <TB1> INFO: Expecting 3120000 events.
[12:01:16.482] <TB1> INFO: 672080 events read in total (29813ms).











[12:01:46.581] <TB1> INFO: 1340160 events read in total (59912ms).
[12:02:16.432] <TB1> INFO: 2004590 events read in total (89763ms).











[12:02:46.587] <TB1> INFO: 2667620 events read in total (119918ms).











[12:03:06.810] <TB1> INFO: 3120000 events read in total (140141ms).
[12:03:06.879] <TB1> INFO: Test took 141034ms.
[12:03:32.400] <TB1> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 166 seconds
[12:03:32.400] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0
[12:03:32.400] <TB1> INFO: separation cut (per ROC): 111 126 116 124 101 110 121 106 101 105 106 107 111 105 101 100
[12:03:32.400] <TB1> INFO: Decoding statistics:
[12:03:32.400] <TB1> INFO: General information:
[12:03:32.400] <TB1> INFO: 16bit words read: 0
[12:03:32.400] <TB1> INFO: valid events total: 0
[12:03:32.400] <TB1> INFO: empty events: 0
[12:03:32.400] <TB1> INFO: valid events with pixels: 0
[12:03:32.400] <TB1> INFO: valid pixel hits: 0
[12:03:32.400] <TB1> INFO: Event errors: 0
[12:03:32.400] <TB1> INFO: start marker: 0
[12:03:32.400] <TB1> INFO: stop marker: 0
[12:03:32.400] <TB1> INFO: overflow: 0
[12:03:32.400] <TB1> INFO: invalid 5bit words: 0
[12:03:32.400] <TB1> INFO: invalid XOR eye diagram: 0
[12:03:32.400] <TB1> INFO: frame (failed synchr.): 0
[12:03:32.400] <TB1> INFO: idle data (no TBM trl): 0
[12:03:32.400] <TB1> INFO: no data (only TBM hdr): 0
[12:03:32.400] <TB1> INFO: TBM errors: 0
[12:03:32.400] <TB1> INFO: flawed TBM headers: 0
[12:03:32.400] <TB1> INFO: flawed TBM trailers: 0
[12:03:32.400] <TB1> INFO: event ID mismatches: 0
[12:03:32.400] <TB1> INFO: ROC errors: 0
[12:03:32.400] <TB1> INFO: missing ROC header(s): 0
[12:03:32.400] <TB1> INFO: misplaced readback start: 0
[12:03:32.400] <TB1> INFO: Pixel decoding errors: 0
[12:03:32.400] <TB1> INFO: pixel data incomplete: 0
[12:03:32.400] <TB1> INFO: pixel address: 0
[12:03:32.400] <TB1> INFO: pulse height fill bit: 0
[12:03:32.400] <TB1> INFO: buffer corruption: 0
[12:03:32.447] <TB1> INFO: ######################################################################
[12:03:32.447] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:03:32.447] <TB1> INFO: ######################################################################
[12:03:32.447] <TB1> INFO: ----------------------------------------------------------------------
[12:03:32.447] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:03:32.447] <TB1> INFO: ----------------------------------------------------------------------
[12:03:32.447] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:03:32.458] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[12:03:32.458] <TB1> INFO: run 1 of 1
[12:03:32.694] <TB1> INFO: Expecting 36608000 events.
[12:03:56.538] <TB1> INFO: 703050 events read in total (23252ms).
[12:04:19.216] <TB1> INFO: 1388550 events read in total (45930ms).
[12:04:41.984] <TB1> INFO: 2074350 events read in total (68698ms).
[12:05:04.519] <TB1> INFO: 2755300 events read in total (91233ms).
[12:05:27.326] <TB1> INFO: 3439250 events read in total (114040ms).
[12:05:49.956] <TB1> INFO: 4119350 events read in total (136670ms).
[12:06:12.603] <TB1> INFO: 4803900 events read in total (159317ms).
[12:06:35.126] <TB1> INFO: 5486750 events read in total (181840ms).
[12:06:57.651] <TB1> INFO: 6167600 events read in total (204365ms).
[12:07:20.115] <TB1> INFO: 6848200 events read in total (226829ms).
[12:07:42.811] <TB1> INFO: 7527900 events read in total (249525ms).
[12:08:05.376] <TB1> INFO: 8207350 events read in total (272090ms).
[12:08:27.943] <TB1> INFO: 8887800 events read in total (294657ms).
[12:08:50.408] <TB1> INFO: 9567450 events read in total (317122ms).
[12:09:12.691] <TB1> INFO: 10248950 events read in total (339405ms).
[12:09:35.399] <TB1> INFO: 10928400 events read in total (362113ms).
[12:09:58.143] <TB1> INFO: 11609350 events read in total (384857ms).
[12:10:20.569] <TB1> INFO: 12288800 events read in total (407283ms).
[12:10:43.340] <TB1> INFO: 12966700 events read in total (430054ms).
[12:11:05.824] <TB1> INFO: 13643000 events read in total (452538ms).
[12:11:28.486] <TB1> INFO: 14320500 events read in total (475200ms).
[12:11:50.864] <TB1> INFO: 14998050 events read in total (497578ms).
[12:12:13.585] <TB1> INFO: 15675700 events read in total (520299ms).
[12:12:35.917] <TB1> INFO: 16352200 events read in total (542631ms).
[12:12:58.283] <TB1> INFO: 17027800 events read in total (564997ms).
[12:13:20.859] <TB1> INFO: 17704900 events read in total (587573ms).
[12:13:43.316] <TB1> INFO: 18380700 events read in total (610030ms).
[12:14:05.949] <TB1> INFO: 19056300 events read in total (632663ms).
[12:14:28.554] <TB1> INFO: 19729500 events read in total (655269ms).
[12:14:51.445] <TB1> INFO: 20403150 events read in total (678159ms).
[12:15:13.854] <TB1> INFO: 21074000 events read in total (700568ms).
[12:15:36.412] <TB1> INFO: 21745750 events read in total (723126ms).
[12:15:58.828] <TB1> INFO: 22418700 events read in total (745542ms).
[12:16:21.460] <TB1> INFO: 23089600 events read in total (768174ms).
[12:16:43.946] <TB1> INFO: 23761200 events read in total (790660ms).
[12:17:06.639] <TB1> INFO: 24433350 events read in total (813353ms).
[12:17:28.992] <TB1> INFO: 25104800 events read in total (835706ms).
[12:17:51.679] <TB1> INFO: 25777850 events read in total (858393ms).
[12:18:14.138] <TB1> INFO: 26449300 events read in total (880852ms).
[12:18:36.739] <TB1> INFO: 27121800 events read in total (903453ms).
[12:18:59.206] <TB1> INFO: 27793900 events read in total (925920ms).
[12:19:22.100] <TB1> INFO: 28464600 events read in total (948814ms).
[12:19:44.414] <TB1> INFO: 29134900 events read in total (971128ms).
[12:20:06.925] <TB1> INFO: 29805300 events read in total (993639ms).
[12:20:29.446] <TB1> INFO: 30476050 events read in total (1016160ms).
[12:20:51.869] <TB1> INFO: 31147700 events read in total (1038583ms).
[12:21:14.383] <TB1> INFO: 31817900 events read in total (1061097ms).
[12:21:37.282] <TB1> INFO: 32487500 events read in total (1083996ms).
[12:22:00.093] <TB1> INFO: 33158500 events read in total (1106807ms).
[12:22:22.729] <TB1> INFO: 33830850 events read in total (1129443ms).
[12:22:45.496] <TB1> INFO: 34502700 events read in total (1152210ms).
[12:23:08.159] <TB1> INFO: 35171650 events read in total (1174873ms).
[12:23:30.802] <TB1> INFO: 35844250 events read in total (1197516ms).
[12:23:53.596] <TB1> INFO: 36526450 events read in total (1220310ms).
[12:23:56.604] <TB1> INFO: 36608000 events read in total (1223318ms).
[12:23:56.674] <TB1> INFO: Test took 1224216ms.
[12:23:57.020] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:23:58.864] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:00.765] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:02.736] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:04.720] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:06.493] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:08.149] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:09.955] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:11.721] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:13.768] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:15.627] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:17.564] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:19.520] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:21.505] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:23.616] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:25.643] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:24:27.550] <TB1> INFO: PixTestScurves::scurves() done
[12:24:27.550] <TB1> INFO: Vcal mean: 124.27 137.65 125.34 125.45 119.81 128.08 128.45 124.00 128.93 124.38 122.40 116.67 128.21 132.36 115.77 122.24
[12:24:27.550] <TB1> INFO: Vcal RMS: 6.66 6.16 6.94 5.65 5.73 5.47 6.55 6.35 5.56 6.50 6.97 5.56 6.42 6.05 5.18 5.82
[12:24:27.550] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1255 seconds
[12:24:27.550] <TB1> INFO: Decoding statistics:
[12:24:27.550] <TB1> INFO: General information:
[12:24:27.550] <TB1> INFO: 16bit words read: 0
[12:24:27.550] <TB1> INFO: valid events total: 0
[12:24:27.550] <TB1> INFO: empty events: 0
[12:24:27.550] <TB1> INFO: valid events with pixels: 0
[12:24:27.550] <TB1> INFO: valid pixel hits: 0
[12:24:27.550] <TB1> INFO: Event errors: 0
[12:24:27.550] <TB1> INFO: start marker: 0
[12:24:27.550] <TB1> INFO: stop marker: 0
[12:24:27.550] <TB1> INFO: overflow: 0
[12:24:27.550] <TB1> INFO: invalid 5bit words: 0
[12:24:27.550] <TB1> INFO: invalid XOR eye diagram: 0
[12:24:27.550] <TB1> INFO: frame (failed synchr.): 0
[12:24:27.550] <TB1> INFO: idle data (no TBM trl): 0
[12:24:27.550] <TB1> INFO: no data (only TBM hdr): 0
[12:24:27.550] <TB1> INFO: TBM errors: 0
[12:24:27.550] <TB1> INFO: flawed TBM headers: 0
[12:24:27.550] <TB1> INFO: flawed TBM trailers: 0
[12:24:27.550] <TB1> INFO: event ID mismatches: 0
[12:24:27.550] <TB1> INFO: ROC errors: 0
[12:24:27.550] <TB1> INFO: missing ROC header(s): 0
[12:24:27.550] <TB1> INFO: misplaced readback start: 0
[12:24:27.550] <TB1> INFO: Pixel decoding errors: 0
[12:24:27.550] <TB1> INFO: pixel data incomplete: 0
[12:24:27.550] <TB1> INFO: pixel address: 0
[12:24:27.550] <TB1> INFO: pulse height fill bit: 0
[12:24:27.550] <TB1> INFO: buffer corruption: 0
[12:24:27.617] <TB1> INFO: ######################################################################
[12:24:27.617] <TB1> INFO: PixTestTrim::doTest()
[12:24:27.617] <TB1> INFO: ######################################################################
[12:24:27.619] <TB1> INFO: ----------------------------------------------------------------------
[12:24:27.620] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:24:27.620] <TB1> INFO: ----------------------------------------------------------------------
[12:24:27.672] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:24:27.672] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:24:27.683] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:24:27.683] <TB1> INFO: run 1 of 1
[12:24:27.955] <TB1> INFO: Expecting 5025280 events.
[12:24:58.416] <TB1> INFO: 831152 events read in total (29864ms).
[12:25:28.347] <TB1> INFO: 1659400 events read in total (59796ms).
[12:25:58.197] <TB1> INFO: 2483880 events read in total (89646ms).
[12:26:27.967] <TB1> INFO: 3305464 events read in total (119415ms).
[12:26:57.587] <TB1> INFO: 4124816 events read in total (149035ms).
[12:27:27.207] <TB1> INFO: 4943832 events read in total (178655ms).
[12:27:30.676] <TB1> INFO: 5025280 events read in total (182124ms).
[12:27:30.713] <TB1> INFO: Test took 183030ms.
[12:27:50.278] <TB1> INFO: ROC 0 VthrComp = 124
[12:27:50.279] <TB1> INFO: ROC 1 VthrComp = 133
[12:27:50.279] <TB1> INFO: ROC 2 VthrComp = 127
[12:27:50.279] <TB1> INFO: ROC 3 VthrComp = 126
[12:27:50.279] <TB1> INFO: ROC 4 VthrComp = 122
[12:27:50.279] <TB1> INFO: ROC 5 VthrComp = 130
[12:27:50.279] <TB1> INFO: ROC 6 VthrComp = 131
[12:27:50.280] <TB1> INFO: ROC 7 VthrComp = 120
[12:27:50.280] <TB1> INFO: ROC 8 VthrComp = 127
[12:27:50.280] <TB1> INFO: ROC 9 VthrComp = 130
[12:27:50.280] <TB1> INFO: ROC 10 VthrComp = 119
[12:27:50.280] <TB1> INFO: ROC 11 VthrComp = 118
[12:27:50.280] <TB1> INFO: ROC 12 VthrComp = 130
[12:27:50.280] <TB1> INFO: ROC 13 VthrComp = 131
[12:27:50.280] <TB1> INFO: ROC 14 VthrComp = 113
[12:27:50.281] <TB1> INFO: ROC 15 VthrComp = 126
[12:27:50.531] <TB1> INFO: Expecting 41600 events.
[12:27:53.948] <TB1> INFO: 41600 events read in total (2825ms).
[12:27:53.948] <TB1> INFO: Test took 3666ms.
[12:27:53.957] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:27:53.957] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:27:53.965] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:27:53.965] <TB1> INFO: run 1 of 1
[12:27:54.243] <TB1> INFO: Expecting 5025280 events.
[12:28:20.737] <TB1> INFO: 591144 events read in total (25902ms).
[12:28:46.181] <TB1> INFO: 1180816 events read in total (51346ms).
[12:29:11.618] <TB1> INFO: 1770528 events read in total (76783ms).
[12:29:36.000] <TB1> INFO: 2359952 events read in total (102165ms).
[12:30:02.390] <TB1> INFO: 2947336 events read in total (127555ms).
[12:30:27.457] <TB1> INFO: 3533208 events read in total (152622ms).
[12:30:53.391] <TB1> INFO: 4118848 events read in total (178556ms).
[12:31:18.552] <TB1> INFO: 4703672 events read in total (203717ms).
[12:31:32.615] <TB1> INFO: 5025280 events read in total (217780ms).
[12:31:32.673] <TB1> INFO: Test took 218707ms.
[12:31:59.820] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 61.6364 for pixel 7/9 mean/min/max = 46.7138/31.6898/61.7377
[12:31:59.821] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 65.0808 for pixel 0/1 mean/min/max = 49.6045/34.0701/65.139
[12:31:59.821] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 60.7985 for pixel 13/20 mean/min/max = 45.9459/31.0624/60.8295
[12:31:59.821] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 58.6039 for pixel 12/10 mean/min/max = 45.4158/32.1117/58.7198
[12:31:59.822] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 59.704 for pixel 8/75 mean/min/max = 46.2793/32.8296/59.729
[12:31:59.822] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 60.1072 for pixel 51/22 mean/min/max = 46.7111/33.2452/60.177
[12:31:59.822] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 62.4337 for pixel 35/5 mean/min/max = 47.5285/32.4654/62.5916
[12:31:59.822] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 64.094 for pixel 2/12 mean/min/max = 48.5218/32.9332/64.1103
[12:31:59.823] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 60.4223 for pixel 24/1 mean/min/max = 46.0983/31.6702/60.5264
[12:31:59.823] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 60.6369 for pixel 30/10 mean/min/max = 46.0751/31.4025/60.7477
[12:31:59.823] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 62.9607 for pixel 1/1 mean/min/max = 46.933/30.5116/63.3544
[12:31:59.824] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 59.1321 for pixel 22/79 mean/min/max = 45.6258/32.0155/59.236
[12:31:59.824] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 60.01 for pixel 0/25 mean/min/max = 46.0755/32.1254/60.0256
[12:31:59.824] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 61.4823 for pixel 6/6 mean/min/max = 47.253/33.0136/61.4924
[12:31:59.824] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 60.379 for pixel 0/15 mean/min/max = 46.6943/32.9795/60.4092
[12:31:59.825] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 58.4965 for pixel 14/8 mean/min/max = 44.8703/31.0151/58.7254
[12:31:59.825] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:31:59.913] <TB1> INFO: Expecting 411648 events.
[12:32:09.235] <TB1> INFO: 411648 events read in total (8730ms).
[12:32:09.242] <TB1> INFO: Expecting 411648 events.
[12:32:18.319] <TB1> INFO: 411648 events read in total (8674ms).
[12:32:18.329] <TB1> INFO: Expecting 411648 events.
[12:32:27.417] <TB1> INFO: 411648 events read in total (8685ms).
[12:32:27.429] <TB1> INFO: Expecting 411648 events.
[12:32:36.508] <TB1> INFO: 411648 events read in total (8676ms).
[12:32:36.523] <TB1> INFO: Expecting 411648 events.
[12:32:45.557] <TB1> INFO: 411648 events read in total (8631ms).
[12:32:45.578] <TB1> INFO: Expecting 411648 events.
[12:32:54.608] <TB1> INFO: 411648 events read in total (8627ms).
[12:32:54.628] <TB1> INFO: Expecting 411648 events.
[12:33:03.644] <TB1> INFO: 411648 events read in total (8613ms).
[12:33:03.675] <TB1> INFO: Expecting 411648 events.
[12:33:12.724] <TB1> INFO: 411648 events read in total (8646ms).
[12:33:12.749] <TB1> INFO: Expecting 411648 events.
[12:33:21.791] <TB1> INFO: 411648 events read in total (8639ms).
[12:33:21.819] <TB1> INFO: Expecting 411648 events.
[12:33:30.847] <TB1> INFO: 411648 events read in total (8625ms).
[12:33:30.888] <TB1> INFO: Expecting 411648 events.
[12:33:39.991] <TB1> INFO: 411648 events read in total (8700ms).
[12:33:40.036] <TB1> INFO: Expecting 411648 events.
[12:33:49.022] <TB1> INFO: 411648 events read in total (8583ms).
[12:33:49.058] <TB1> INFO: Expecting 411648 events.
[12:33:58.062] <TB1> INFO: 411648 events read in total (8601ms).
[12:33:58.101] <TB1> INFO: Expecting 411648 events.
[12:34:07.115] <TB1> INFO: 411648 events read in total (8611ms).
[12:34:07.156] <TB1> INFO: Expecting 411648 events.
[12:34:16.221] <TB1> INFO: 411648 events read in total (8662ms).
[12:34:16.265] <TB1> INFO: Expecting 411648 events.
[12:34:25.314] <TB1> INFO: 411648 events read in total (8646ms).
[12:34:25.361] <TB1> INFO: Test took 145536ms.
[12:34:26.056] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:34:26.066] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:34:26.067] <TB1> INFO: run 1 of 1
[12:34:26.299] <TB1> INFO: Expecting 5025280 events.
[12:34:52.005] <TB1> INFO: 591600 events read in total (25115ms).
[12:35:17.705] <TB1> INFO: 1180720 events read in total (50815ms).
[12:35:43.503] <TB1> INFO: 1771160 events read in total (76613ms).
[12:36:09.045] <TB1> INFO: 2358992 events read in total (102155ms).
[12:36:35.070] <TB1> INFO: 2949184 events read in total (128180ms).
[12:37:00.602] <TB1> INFO: 3535968 events read in total (153712ms).
[12:37:26.117] <TB1> INFO: 4125248 events read in total (179227ms).
[12:37:51.639] <TB1> INFO: 4712304 events read in total (204749ms).
[12:38:05.885] <TB1> INFO: 5025280 events read in total (218995ms).
[12:38:05.996] <TB1> INFO: Test took 219929ms.
[12:38:30.634] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 0.407656 .. 146.769213
[12:38:30.907] <TB1> INFO: Expecting 208000 events.
[12:38:40.155] <TB1> INFO: 208000 events read in total (8656ms).
[12:38:40.156] <TB1> INFO: Test took 9521ms.
[12:38:40.204] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 156 (-1/-1) hits flags = 528 (plus default)
[12:38:40.214] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:38:40.214] <TB1> INFO: run 1 of 1
[12:38:40.492] <TB1> INFO: Expecting 5224960 events.
[12:39:06.971] <TB1> INFO: 586016 events read in total (25888ms).
[12:39:32.340] <TB1> INFO: 1171776 events read in total (51257ms).
[12:39:58.036] <TB1> INFO: 1757816 events read in total (76953ms).
[12:40:23.511] <TB1> INFO: 2343984 events read in total (102428ms).
[12:40:49.291] <TB1> INFO: 2929816 events read in total (128208ms).
[12:41:15.297] <TB1> INFO: 3515040 events read in total (154214ms).
[12:41:41.017] <TB1> INFO: 4099632 events read in total (179934ms).
[12:42:06.767] <TB1> INFO: 4684344 events read in total (205684ms).
[12:42:30.529] <TB1> INFO: 5224960 events read in total (229446ms).
[12:42:30.679] <TB1> INFO: Test took 230465ms.
[12:42:58.931] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.520611 .. 49.099609
[12:42:59.168] <TB1> INFO: Expecting 208000 events.
[12:43:08.665] <TB1> INFO: 208000 events read in total (8905ms).
[12:43:08.665] <TB1> INFO: Test took 9732ms.
[12:43:08.713] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 59 (-1/-1) hits flags = 528 (plus default)
[12:43:08.721] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:43:08.721] <TB1> INFO: run 1 of 1
[12:43:08.999] <TB1> INFO: Expecting 1431040 events.
[12:43:36.417] <TB1> INFO: 645848 events read in total (26826ms).
[12:44:03.536] <TB1> INFO: 1289968 events read in total (53945ms).
[12:44:09.717] <TB1> INFO: 1431040 events read in total (60126ms).
[12:44:09.746] <TB1> INFO: Test took 61025ms.
[12:44:24.669] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 27.650174 .. 47.881751
[12:44:24.944] <TB1> INFO: Expecting 208000 events.
[12:44:34.741] <TB1> INFO: 208000 events read in total (9198ms).
[12:44:34.742] <TB1> INFO: Test took 10072ms.
[12:44:34.790] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 57 (-1/-1) hits flags = 528 (plus default)
[12:44:34.801] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:44:34.801] <TB1> INFO: run 1 of 1
[12:44:35.079] <TB1> INFO: Expecting 1364480 events.
[12:45:02.595] <TB1> INFO: 653192 events read in total (26925ms).
[12:45:30.170] <TB1> INFO: 1304736 events read in total (54500ms).
[12:45:33.053] <TB1> INFO: 1364480 events read in total (57384ms).
[12:45:33.078] <TB1> INFO: Test took 58277ms.
[12:45:47.045] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 25.092760 .. 46.262436
[12:45:47.282] <TB1> INFO: Expecting 208000 events.
[12:45:56.944] <TB1> INFO: 208000 events read in total (9070ms).
[12:45:56.945] <TB1> INFO: Test took 9898ms.
[12:45:57.025] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 56 (-1/-1) hits flags = 528 (plus default)
[12:45:57.036] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:45:57.036] <TB1> INFO: run 1 of 1
[12:45:57.314] <TB1> INFO: Expecting 1397760 events.
[12:46:25.443] <TB1> INFO: 664264 events read in total (27538ms).
[12:46:52.945] <TB1> INFO: 1327872 events read in total (55041ms).
[12:46:56.400] <TB1> INFO: 1397760 events read in total (58495ms).
[12:46:56.423] <TB1> INFO: Test took 59388ms.
[12:47:10.886] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:47:10.886] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:47:10.897] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:47:10.897] <TB1> INFO: run 1 of 1
[12:47:11.173] <TB1> INFO: Expecting 1364480 events.
[12:47:39.622] <TB1> INFO: 668520 events read in total (27858ms).
[12:48:07.612] <TB1> INFO: 1336200 events read in total (55848ms).
[12:48:09.150] <TB1> INFO: 1364480 events read in total (57387ms).
[12:48:09.180] <TB1> INFO: Test took 58284ms.
[12:48:23.793] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C0.dat
[12:48:23.793] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C1.dat
[12:48:23.794] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C2.dat
[12:48:23.794] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C3.dat
[12:48:23.794] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C4.dat
[12:48:23.794] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C5.dat
[12:48:23.794] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C6.dat
[12:48:23.794] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C7.dat
[12:48:23.794] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C8.dat
[12:48:23.794] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C9.dat
[12:48:23.794] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C10.dat
[12:48:23.794] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C11.dat
[12:48:23.794] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C12.dat
[12:48:23.794] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C13.dat
[12:48:23.794] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C14.dat
[12:48:23.794] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C15.dat
[12:48:23.795] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C0.dat
[12:48:23.800] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C1.dat
[12:48:23.806] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C2.dat
[12:48:23.811] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C3.dat
[12:48:23.816] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C4.dat
[12:48:23.822] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C5.dat
[12:48:23.827] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C6.dat
[12:48:23.833] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C7.dat
[12:48:23.838] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C8.dat
[12:48:23.844] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C9.dat
[12:48:23.849] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C10.dat
[12:48:23.854] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C11.dat
[12:48:23.860] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C12.dat
[12:48:23.865] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C13.dat
[12:48:23.871] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C14.dat
[12:48:23.876] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters35_C15.dat
[12:48:23.882] <TB1> INFO: PixTestTrim::trimTest() done
[12:48:23.882] <TB1> INFO: vtrim: 152 142 116 151 125 147 155 150 134 137 131 132 131 134 124 136
[12:48:23.882] <TB1> INFO: vthrcomp: 124 133 127 126 122 130 131 120 127 130 119 118 130 131 113 126
[12:48:23.882] <TB1> INFO: vcal mean: 35.15 35.01 35.07 34.97 34.96 35.03 34.93 35.29 35.14 35.16 35.10 34.97 34.97 35.40 35.00 34.92
[12:48:23.882] <TB1> INFO: vcal RMS: 1.22 1.03 1.32 1.10 0.99 1.06 1.10 1.49 1.43 1.39 1.41 1.05 1.04 1.56 1.04 1.08
[12:48:23.882] <TB1> INFO: bits mean: 10.07 8.21 10.02 10.60 9.31 9.66 9.60 9.82 9.99 10.47 9.86 9.90 9.46 9.88 9.13 10.20
[12:48:23.882] <TB1> INFO: bits RMS: 2.46 2.67 2.64 2.25 2.69 2.49 2.50 2.38 2.60 2.35 2.70 2.62 2.72 2.46 2.70 2.56
[12:48:23.889] <TB1> INFO: ----------------------------------------------------------------------
[12:48:23.889] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:48:23.889] <TB1> INFO: ----------------------------------------------------------------------
[12:48:23.891] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:48:23.901] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:48:23.901] <TB1> INFO: run 1 of 1
[12:48:24.136] <TB1> INFO: Expecting 4160000 events.
[12:48:57.264] <TB1> INFO: 772995 events read in total (32536ms).
[12:49:28.792] <TB1> INFO: 1538655 events read in total (64064ms).
[12:50:00.638] <TB1> INFO: 2299150 events read in total (95910ms).
[12:50:32.409] <TB1> INFO: 3055120 events read in total (127681ms).
[12:51:03.790] <TB1> INFO: 3810040 events read in total (159062ms).
[12:51:18.648] <TB1> INFO: 4160000 events read in total (173920ms).
[12:51:18.728] <TB1> INFO: Test took 174827ms.
[12:51:45.910] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 209 (-1/-1) hits flags = 528 (plus default)
[12:51:45.921] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:51:45.921] <TB1> INFO: run 1 of 1
[12:51:46.197] <TB1> INFO: Expecting 4368000 events.
[12:52:17.899] <TB1> INFO: 733950 events read in total (31111ms).
[12:52:49.018] <TB1> INFO: 1462710 events read in total (62230ms).
[12:53:19.816] <TB1> INFO: 2188055 events read in total (93028ms).
[12:53:50.368] <TB1> INFO: 2909490 events read in total (123580ms).
[12:54:21.346] <TB1> INFO: 3630700 events read in total (154558ms).
[12:54:51.930] <TB1> INFO: 4351765 events read in total (185142ms).
[12:54:52.985] <TB1> INFO: 4368000 events read in total (186197ms).
[12:54:53.048] <TB1> INFO: Test took 187127ms.
[12:55:22.106] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[12:55:22.120] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:55:22.120] <TB1> INFO: run 1 of 1
[12:55:22.367] <TB1> INFO: Expecting 4326400 events.
[12:55:53.970] <TB1> INFO: 737110 events read in total (31011ms).
[12:56:24.652] <TB1> INFO: 1468670 events read in total (61693ms).
[12:56:55.244] <TB1> INFO: 2196905 events read in total (92285ms).
[12:57:26.042] <TB1> INFO: 2921100 events read in total (123083ms).
[12:57:56.872] <TB1> INFO: 3644495 events read in total (153913ms).
[12:58:26.050] <TB1> INFO: 4326400 events read in total (183091ms).
[12:58:26.117] <TB1> INFO: Test took 183997ms.
[12:58:54.693] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[12:58:54.704] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:58:54.704] <TB1> INFO: run 1 of 1
[12:58:54.943] <TB1> INFO: Expecting 4347200 events.
[12:59:27.036] <TB1> INFO: 735760 events read in total (31501ms).
[12:59:58.075] <TB1> INFO: 1466255 events read in total (62540ms).
[13:00:28.698] <TB1> INFO: 2193290 events read in total (93163ms).
[13:00:59.379] <TB1> INFO: 2916335 events read in total (123844ms).
[13:01:30.024] <TB1> INFO: 3638870 events read in total (154489ms).
[13:01:59.952] <TB1> INFO: 4347200 events read in total (184417ms).
[13:02:00.004] <TB1> INFO: Test took 185300ms.
[13:02:26.796] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[13:02:26.807] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:02:26.807] <TB1> INFO: run 1 of 1
[13:02:27.040] <TB1> INFO: Expecting 4326400 events.
[13:02:59.494] <TB1> INFO: 737135 events read in total (31863ms).
[13:03:30.207] <TB1> INFO: 1468710 events read in total (62576ms).
[13:04:00.874] <TB1> INFO: 2197100 events read in total (93243ms).
[13:04:31.664] <TB1> INFO: 2921445 events read in total (124033ms).
[13:05:02.518] <TB1> INFO: 3645165 events read in total (154887ms).
[13:05:31.403] <TB1> INFO: 4326400 events read in total (183772ms).
[13:05:31.470] <TB1> INFO: Test took 184663ms.
[13:06:01.102] <TB1> INFO: PixTestTrim::trimBitTest() done
[13:06:01.103] <TB1> INFO: PixTestTrim::doTest() done, duration: 2493 seconds
[13:06:01.103] <TB1> INFO: Decoding statistics:
[13:06:01.104] <TB1> INFO: General information:
[13:06:01.104] <TB1> INFO: 16bit words read: 0
[13:06:01.104] <TB1> INFO: valid events total: 0
[13:06:01.104] <TB1> INFO: empty events: 0
[13:06:01.104] <TB1> INFO: valid events with pixels: 0
[13:06:01.104] <TB1> INFO: valid pixel hits: 0
[13:06:01.104] <TB1> INFO: Event errors: 0
[13:06:01.104] <TB1> INFO: start marker: 0
[13:06:01.104] <TB1> INFO: stop marker: 0
[13:06:01.104] <TB1> INFO: overflow: 0
[13:06:01.104] <TB1> INFO: invalid 5bit words: 0
[13:06:01.104] <TB1> INFO: invalid XOR eye diagram: 0
[13:06:01.104] <TB1> INFO: frame (failed synchr.): 0
[13:06:01.104] <TB1> INFO: idle data (no TBM trl): 0
[13:06:01.104] <TB1> INFO: no data (only TBM hdr): 0
[13:06:01.104] <TB1> INFO: TBM errors: 0
[13:06:01.104] <TB1> INFO: flawed TBM headers: 0
[13:06:01.104] <TB1> INFO: flawed TBM trailers: 0
[13:06:01.104] <TB1> INFO: event ID mismatches: 0
[13:06:01.104] <TB1> INFO: ROC errors: 0
[13:06:01.104] <TB1> INFO: missing ROC header(s): 0
[13:06:01.104] <TB1> INFO: misplaced readback start: 0
[13:06:01.104] <TB1> INFO: Pixel decoding errors: 0
[13:06:01.104] <TB1> INFO: pixel data incomplete: 0
[13:06:01.104] <TB1> INFO: pixel address: 0
[13:06:01.104] <TB1> INFO: pulse height fill bit: 0
[13:06:01.104] <TB1> INFO: buffer corruption: 0
[13:06:01.833] <TB1> INFO: ######################################################################
[13:06:01.833] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:06:01.833] <TB1> INFO: ######################################################################
[13:06:02.068] <TB1> INFO: Expecting 41600 events.
[13:06:05.566] <TB1> INFO: 41600 events read in total (2906ms).
[13:06:05.567] <TB1> INFO: Test took 3733ms.
[13:06:05.002] <TB1> INFO: Expecting 41600 events.
[13:06:09.643] <TB1> INFO: 41600 events read in total (3049ms).
[13:06:09.644] <TB1> INFO: Test took 3874ms.
[13:06:09.935] <TB1> INFO: Expecting 41600 events.
[13:06:13.426] <TB1> INFO: 41600 events read in total (2900ms).
[13:06:13.428] <TB1> INFO: Test took 3758ms.
[13:06:13.718] <TB1> INFO: Expecting 41600 events.
[13:06:17.316] <TB1> INFO: 41600 events read in total (3006ms).
[13:06:17.317] <TB1> INFO: Test took 3864ms.
[13:06:17.613] <TB1> INFO: Expecting 41600 events.
[13:06:21.347] <TB1> INFO: 41600 events read in total (3143ms).
[13:06:21.348] <TB1> INFO: Test took 4008ms.
[13:06:21.638] <TB1> INFO: Expecting 41600 events.
[13:06:25.561] <TB1> INFO: 41600 events read in total (3331ms).
[13:06:25.562] <TB1> INFO: Test took 4189ms.
[13:06:25.910] <TB1> INFO: Expecting 41600 events.
[13:06:29.419] <TB1> INFO: 41600 events read in total (2917ms).
[13:06:29.420] <TB1> INFO: Test took 3830ms.
[13:06:29.710] <TB1> INFO: Expecting 41600 events.
[13:06:33.264] <TB1> INFO: 41600 events read in total (2962ms).
[13:06:33.267] <TB1> INFO: Test took 3821ms.
[13:06:33.578] <TB1> INFO: Expecting 41600 events.
[13:06:37.187] <TB1> INFO: 41600 events read in total (3017ms).
[13:06:37.188] <TB1> INFO: Test took 3892ms.
[13:06:37.476] <TB1> INFO: Expecting 41600 events.
[13:06:40.938] <TB1> INFO: 41600 events read in total (2870ms).
[13:06:40.939] <TB1> INFO: Test took 3727ms.
[13:06:41.236] <TB1> INFO: Expecting 41600 events.
[13:06:44.793] <TB1> INFO: 41600 events read in total (2965ms).
[13:06:44.793] <TB1> INFO: Test took 3830ms.
[13:06:45.082] <TB1> INFO: Expecting 41600 events.
[13:06:48.628] <TB1> INFO: 41600 events read in total (2955ms).
[13:06:48.629] <TB1> INFO: Test took 3812ms.
[13:06:48.917] <TB1> INFO: Expecting 41600 events.
[13:06:52.374] <TB1> INFO: 41600 events read in total (2865ms).
[13:06:52.375] <TB1> INFO: Test took 3723ms.
[13:06:52.664] <TB1> INFO: Expecting 41600 events.
[13:06:56.314] <TB1> INFO: 41600 events read in total (3059ms).
[13:06:56.315] <TB1> INFO: Test took 3916ms.
[13:06:56.665] <TB1> INFO: Expecting 41600 events.
[13:07:00.145] <TB1> INFO: 41600 events read in total (2889ms).
[13:07:00.146] <TB1> INFO: Test took 3802ms.
[13:07:00.434] <TB1> INFO: Expecting 41600 events.
[13:07:03.958] <TB1> INFO: 41600 events read in total (2933ms).
[13:07:03.958] <TB1> INFO: Test took 3789ms.
[13:07:04.246] <TB1> INFO: Expecting 41600 events.
[13:07:07.784] <TB1> INFO: 41600 events read in total (2946ms).
[13:07:07.785] <TB1> INFO: Test took 3803ms.
[13:07:08.074] <TB1> INFO: Expecting 41600 events.
[13:07:11.652] <TB1> INFO: 41600 events read in total (2987ms).
[13:07:11.653] <TB1> INFO: Test took 3844ms.
[13:07:11.941] <TB1> INFO: Expecting 41600 events.
[13:07:15.396] <TB1> INFO: 41600 events read in total (2863ms).
[13:07:15.397] <TB1> INFO: Test took 3721ms.
[13:07:15.685] <TB1> INFO: Expecting 41600 events.
[13:07:19.177] <TB1> INFO: 41600 events read in total (2900ms).
[13:07:19.178] <TB1> INFO: Test took 3757ms.
[13:07:19.468] <TB1> INFO: Expecting 41600 events.
[13:07:23.065] <TB1> INFO: 41600 events read in total (3005ms).
[13:07:23.066] <TB1> INFO: Test took 3862ms.
[13:07:23.357] <TB1> INFO: Expecting 41600 events.
[13:07:26.907] <TB1> INFO: 41600 events read in total (2959ms).
[13:07:26.908] <TB1> INFO: Test took 3816ms.
[13:07:27.196] <TB1> INFO: Expecting 41600 events.
[13:07:30.642] <TB1> INFO: 41600 events read in total (2855ms).
[13:07:30.643] <TB1> INFO: Test took 3712ms.
[13:07:30.931] <TB1> INFO: Expecting 41600 events.
[13:07:34.499] <TB1> INFO: 41600 events read in total (2976ms).
[13:07:34.500] <TB1> INFO: Test took 3833ms.
[13:07:34.788] <TB1> INFO: Expecting 41600 events.
[13:07:38.309] <TB1> INFO: 41600 events read in total (2929ms).
[13:07:38.310] <TB1> INFO: Test took 3786ms.
[13:07:38.599] <TB1> INFO: Expecting 41600 events.
[13:07:42.133] <TB1> INFO: 41600 events read in total (2942ms).
[13:07:42.134] <TB1> INFO: Test took 3799ms.
[13:07:42.423] <TB1> INFO: Expecting 2560 events.
[13:07:43.306] <TB1> INFO: 2560 events read in total (291ms).
[13:07:43.307] <TB1> INFO: Test took 1161ms.
[13:07:43.614] <TB1> INFO: Expecting 2560 events.
[13:07:44.498] <TB1> INFO: 2560 events read in total (292ms).
[13:07:44.498] <TB1> INFO: Test took 1190ms.
[13:07:44.806] <TB1> INFO: Expecting 2560 events.
[13:07:45.693] <TB1> INFO: 2560 events read in total (296ms).
[13:07:45.693] <TB1> INFO: Test took 1194ms.
[13:07:45.001] <TB1> INFO: Expecting 2560 events.
[13:07:46.884] <TB1> INFO: 2560 events read in total (291ms).
[13:07:46.884] <TB1> INFO: Test took 1191ms.
[13:07:47.192] <TB1> INFO: Expecting 2560 events.
[13:07:48.074] <TB1> INFO: 2560 events read in total (291ms).
[13:07:48.074] <TB1> INFO: Test took 1190ms.
[13:07:48.382] <TB1> INFO: Expecting 2560 events.
[13:07:49.265] <TB1> INFO: 2560 events read in total (291ms).
[13:07:49.265] <TB1> INFO: Test took 1190ms.
[13:07:49.573] <TB1> INFO: Expecting 2560 events.
[13:07:50.451] <TB1> INFO: 2560 events read in total (286ms).
[13:07:50.451] <TB1> INFO: Test took 1185ms.
[13:07:50.759] <TB1> INFO: Expecting 2560 events.
[13:07:51.638] <TB1> INFO: 2560 events read in total (287ms).
[13:07:51.638] <TB1> INFO: Test took 1186ms.
[13:07:51.946] <TB1> INFO: Expecting 2560 events.
[13:07:52.826] <TB1> INFO: 2560 events read in total (289ms).
[13:07:52.827] <TB1> INFO: Test took 1188ms.
[13:07:53.134] <TB1> INFO: Expecting 2560 events.
[13:07:54.014] <TB1> INFO: 2560 events read in total (288ms).
[13:07:54.014] <TB1> INFO: Test took 1187ms.
[13:07:54.322] <TB1> INFO: Expecting 2560 events.
[13:07:55.204] <TB1> INFO: 2560 events read in total (290ms).
[13:07:55.204] <TB1> INFO: Test took 1189ms.
[13:07:55.513] <TB1> INFO: Expecting 2560 events.
[13:07:56.395] <TB1> INFO: 2560 events read in total (290ms).
[13:07:56.395] <TB1> INFO: Test took 1190ms.
[13:07:56.703] <TB1> INFO: Expecting 2560 events.
[13:07:57.589] <TB1> INFO: 2560 events read in total (294ms).
[13:07:57.590] <TB1> INFO: Test took 1194ms.
[13:07:57.897] <TB1> INFO: Expecting 2560 events.
[13:07:58.781] <TB1> INFO: 2560 events read in total (293ms).
[13:07:58.781] <TB1> INFO: Test took 1191ms.
[13:07:59.089] <TB1> INFO: Expecting 2560 events.
[13:07:59.976] <TB1> INFO: 2560 events read in total (296ms).
[13:07:59.976] <TB1> INFO: Test took 1194ms.
[13:08:00.284] <TB1> INFO: Expecting 2560 events.
[13:08:01.170] <TB1> INFO: 2560 events read in total (294ms).
[13:08:01.171] <TB1> INFO: Test took 1194ms.
[13:08:01.173] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:01.479] <TB1> INFO: Expecting 655360 events.
[13:08:15.910] <TB1> INFO: 655360 events read in total (13839ms).
[13:08:15.924] <TB1> INFO: Expecting 655360 events.
[13:08:30.169] <TB1> INFO: 655360 events read in total (13842ms).
[13:08:30.184] <TB1> INFO: Expecting 655360 events.
[13:08:44.381] <TB1> INFO: 655360 events read in total (13794ms).
[13:08:44.407] <TB1> INFO: Expecting 655360 events.
[13:08:58.509] <TB1> INFO: 655360 events read in total (13699ms).
[13:08:58.532] <TB1> INFO: Expecting 655360 events.
[13:09:12.634] <TB1> INFO: 655360 events read in total (13699ms).
[13:09:12.671] <TB1> INFO: Expecting 655360 events.
[13:09:26.678] <TB1> INFO: 655360 events read in total (13604ms).
[13:09:26.708] <TB1> INFO: Expecting 655360 events.
[13:09:40.916] <TB1> INFO: 655360 events read in total (13805ms).
[13:09:40.964] <TB1> INFO: Expecting 655360 events.
[13:09:55.107] <TB1> INFO: 655360 events read in total (13740ms).
[13:09:55.161] <TB1> INFO: Expecting 655360 events.
[13:10:09.267] <TB1> INFO: 655360 events read in total (13703ms).
[13:10:09.313] <TB1> INFO: Expecting 655360 events.
[13:10:23.312] <TB1> INFO: 655360 events read in total (13596ms).
[13:10:23.358] <TB1> INFO: Expecting 655360 events.
[13:10:37.452] <TB1> INFO: 655360 events read in total (13691ms).
[13:10:37.528] <TB1> INFO: Expecting 655360 events.
[13:10:51.459] <TB1> INFO: 655360 events read in total (13528ms).
[13:10:51.537] <TB1> INFO: Expecting 655360 events.
[13:11:05.522] <TB1> INFO: 655360 events read in total (13582ms).
[13:11:05.583] <TB1> INFO: Expecting 655360 events.
[13:11:19.617] <TB1> INFO: 655360 events read in total (13631ms).
[13:11:19.682] <TB1> INFO: Expecting 655360 events.
[13:11:33.779] <TB1> INFO: 655360 events read in total (13694ms).
[13:11:33.848] <TB1> INFO: Expecting 655360 events.
[13:11:47.996] <TB1> INFO: 655360 events read in total (13745ms).
[13:11:48.071] <TB1> INFO: Test took 226898ms.
[13:11:48.149] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:11:48.413] <TB1> INFO: Expecting 655360 events.
[13:12:02.660] <TB1> INFO: 655360 events read in total (13655ms).
[13:12:02.674] <TB1> INFO: Expecting 655360 events.
[13:12:16.562] <TB1> INFO: 655360 events read in total (13485ms).
[13:12:16.576] <TB1> INFO: Expecting 655360 events.
[13:12:30.344] <TB1> INFO: 655360 events read in total (13365ms).
[13:12:30.362] <TB1> INFO: Expecting 655360 events.
[13:12:44.511] <TB1> INFO: 655360 events read in total (13746ms).
[13:12:44.541] <TB1> INFO: Expecting 655360 events.
[13:12:58.574] <TB1> INFO: 655360 events read in total (13630ms).
[13:12:58.610] <TB1> INFO: Expecting 655360 events.
[13:13:12.501] <TB1> INFO: 655360 events read in total (13488ms).
[13:13:12.531] <TB1> INFO: Expecting 655360 events.
[13:13:26.509] <TB1> INFO: 655360 events read in total (13575ms).
[13:13:26.556] <TB1> INFO: Expecting 655360 events.
[13:13:40.565] <TB1> INFO: 655360 events read in total (13606ms).
[13:13:40.603] <TB1> INFO: Expecting 655360 events.
[13:13:54.525] <TB1> INFO: 655360 events read in total (13519ms).
[13:13:54.570] <TB1> INFO: Expecting 655360 events.
[13:14:08.412] <TB1> INFO: 655360 events read in total (13439ms).
[13:14:08.458] <TB1> INFO: Expecting 655360 events.
[13:14:22.500] <TB1> INFO: 655360 events read in total (13639ms).
[13:14:22.554] <TB1> INFO: Expecting 655360 events.
[13:14:36.466] <TB1> INFO: 655360 events read in total (13510ms).
[13:14:36.543] <TB1> INFO: Expecting 655360 events.
[13:14:50.455] <TB1> INFO: 655360 events read in total (13509ms).
[13:14:50.515] <TB1> INFO: Expecting 655360 events.
[13:15:04.598] <TB1> INFO: 655360 events read in total (13680ms).
[13:15:04.663] <TB1> INFO: Expecting 655360 events.
[13:15:18.739] <TB1> INFO: 655360 events read in total (13673ms).
[13:15:18.833] <TB1> INFO: Expecting 655360 events.
[13:15:32.772] <TB1> INFO: 655360 events read in total (13536ms).
[13:15:32.845] <TB1> INFO: Test took 224696ms.
[13:15:32.998] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:32.003] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:15:33.007] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:15:33.012] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:15:33.016] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:15:33.021] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.025] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:15:33.030] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.035] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:15:33.039] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:15:33.044] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:15:33.050] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.056] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.061] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.067] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:15:33.072] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:15:33.077] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:15:33.082] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:15:33.087] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:15:33.092] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[13:15:33.096] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[13:15:33.102] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[13:15:33.107] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[13:15:33.112] <TB1> INFO: safety margin for low PH: adding 10, margin is now 30
[13:15:33.118] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.123] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.128] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.133] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:15:33.138] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:15:33.143] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.148] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.153] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.157] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:15:33.162] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.167] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:15:33.172] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:15:33.177] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:15:33.182] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:15:33.187] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:15:33.192] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[13:15:33.197] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[13:15:33.201] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[13:15:33.207] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[13:15:33.213] <TB1> INFO: safety margin for low PH: adding 10, margin is now 30
[13:15:33.218] <TB1> INFO: safety margin for low PH: adding 11, margin is now 31
[13:15:33.224] <TB1> INFO: safety margin for low PH: adding 12, margin is now 32
[13:15:33.229] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.234] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.239] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:15:33.244] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:15:33.249] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:15:33.254] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:15:33.259] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:15:33.263] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[13:15:33.268] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[13:15:33.273] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:15:33.307] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C0.dat
[13:15:33.308] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C1.dat
[13:15:33.308] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C2.dat
[13:15:33.308] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C3.dat
[13:15:33.308] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C4.dat
[13:15:33.308] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C5.dat
[13:15:33.308] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C6.dat
[13:15:33.308] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C7.dat
[13:15:33.308] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C8.dat
[13:15:33.308] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C9.dat
[13:15:33.308] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C10.dat
[13:15:33.308] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C11.dat
[13:15:33.309] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C12.dat
[13:15:33.309] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C13.dat
[13:15:33.309] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C14.dat
[13:15:33.309] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters35_C15.dat
[13:15:33.542] <TB1> INFO: Expecting 41600 events.
[13:15:36.672] <TB1> INFO: 41600 events read in total (2538ms).
[13:15:36.673] <TB1> INFO: Test took 3362ms.
[13:15:37.116] <TB1> INFO: Expecting 41600 events.
[13:15:40.116] <TB1> INFO: 41600 events read in total (2408ms).
[13:15:40.116] <TB1> INFO: Test took 3233ms.
[13:15:40.597] <TB1> INFO: Expecting 41600 events.
[13:15:43.704] <TB1> INFO: 41600 events read in total (2515ms).
[13:15:43.705] <TB1> INFO: Test took 3377ms.
[13:15:43.920] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:44.009] <TB1> INFO: Expecting 2560 events.
[13:15:44.892] <TB1> INFO: 2560 events read in total (292ms).
[13:15:44.893] <TB1> INFO: Test took 973ms.
[13:15:44.894] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:45.201] <TB1> INFO: Expecting 2560 events.
[13:15:46.084] <TB1> INFO: 2560 events read in total (291ms).
[13:15:46.084] <TB1> INFO: Test took 1190ms.
[13:15:46.086] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:46.393] <TB1> INFO: Expecting 2560 events.
[13:15:47.276] <TB1> INFO: 2560 events read in total (292ms).
[13:15:47.277] <TB1> INFO: Test took 1191ms.
[13:15:47.278] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:47.585] <TB1> INFO: Expecting 2560 events.
[13:15:48.471] <TB1> INFO: 2560 events read in total (294ms).
[13:15:48.471] <TB1> INFO: Test took 1193ms.
[13:15:48.473] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:48.779] <TB1> INFO: Expecting 2560 events.
[13:15:49.662] <TB1> INFO: 2560 events read in total (291ms).
[13:15:49.662] <TB1> INFO: Test took 1189ms.
[13:15:49.665] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:49.971] <TB1> INFO: Expecting 2560 events.
[13:15:50.853] <TB1> INFO: 2560 events read in total (291ms).
[13:15:50.853] <TB1> INFO: Test took 1188ms.
[13:15:50.855] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:51.161] <TB1> INFO: Expecting 2560 events.
[13:15:52.043] <TB1> INFO: 2560 events read in total (290ms).
[13:15:52.044] <TB1> INFO: Test took 1189ms.
[13:15:52.045] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:52.352] <TB1> INFO: Expecting 2560 events.
[13:15:53.234] <TB1> INFO: 2560 events read in total (290ms).
[13:15:53.234] <TB1> INFO: Test took 1189ms.
[13:15:53.236] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:53.543] <TB1> INFO: Expecting 2560 events.
[13:15:54.424] <TB1> INFO: 2560 events read in total (290ms).
[13:15:54.424] <TB1> INFO: Test took 1188ms.
[13:15:54.426] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:54.733] <TB1> INFO: Expecting 2560 events.
[13:15:55.615] <TB1> INFO: 2560 events read in total (291ms).
[13:15:55.616] <TB1> INFO: Test took 1191ms.
[13:15:55.618] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:55.924] <TB1> INFO: Expecting 2560 events.
[13:15:56.805] <TB1> INFO: 2560 events read in total (289ms).
[13:15:56.806] <TB1> INFO: Test took 1188ms.
[13:15:56.808] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:57.114] <TB1> INFO: Expecting 2560 events.
[13:15:57.996] <TB1> INFO: 2560 events read in total (290ms).
[13:15:57.996] <TB1> INFO: Test took 1188ms.
[13:15:57.998] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:58.305] <TB1> INFO: Expecting 2560 events.
[13:15:59.183] <TB1> INFO: 2560 events read in total (287ms).
[13:15:59.184] <TB1> INFO: Test took 1186ms.
[13:15:59.185] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:59.492] <TB1> INFO: Expecting 2560 events.
[13:16:00.377] <TB1> INFO: 2560 events read in total (293ms).
[13:16:00.377] <TB1> INFO: Test took 1192ms.
[13:16:00.379] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:00.685] <TB1> INFO: Expecting 2560 events.
[13:16:01.567] <TB1> INFO: 2560 events read in total (290ms).
[13:16:01.567] <TB1> INFO: Test took 1188ms.
[13:16:01.569] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:01.876] <TB1> INFO: Expecting 2560 events.
[13:16:02.754] <TB1> INFO: 2560 events read in total (287ms).
[13:16:02.754] <TB1> INFO: Test took 1185ms.
[13:16:02.756] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:03.063] <TB1> INFO: Expecting 2560 events.
[13:16:03.941] <TB1> INFO: 2560 events read in total (287ms).
[13:16:03.941] <TB1> INFO: Test took 1185ms.
[13:16:03.943] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:04.250] <TB1> INFO: Expecting 2560 events.
[13:16:05.129] <TB1> INFO: 2560 events read in total (288ms).
[13:16:05.130] <TB1> INFO: Test took 1187ms.
[13:16:05.132] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:05.438] <TB1> INFO: Expecting 2560 events.
[13:16:06.316] <TB1> INFO: 2560 events read in total (287ms).
[13:16:06.316] <TB1> INFO: Test took 1185ms.
[13:16:06.318] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:06.624] <TB1> INFO: Expecting 2560 events.
[13:16:07.503] <TB1> INFO: 2560 events read in total (287ms).
[13:16:07.503] <TB1> INFO: Test took 1185ms.
[13:16:07.505] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:07.811] <TB1> INFO: Expecting 2560 events.
[13:16:08.691] <TB1> INFO: 2560 events read in total (288ms).
[13:16:08.691] <TB1> INFO: Test took 1186ms.
[13:16:08.693] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:08.999] <TB1> INFO: Expecting 2560 events.
[13:16:09.878] <TB1> INFO: 2560 events read in total (287ms).
[13:16:09.878] <TB1> INFO: Test took 1185ms.
[13:16:09.880] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:10.186] <TB1> INFO: Expecting 2560 events.
[13:16:11.066] <TB1> INFO: 2560 events read in total (288ms).
[13:16:11.067] <TB1> INFO: Test took 1187ms.
[13:16:11.068] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:11.375] <TB1> INFO: Expecting 2560 events.
[13:16:12.254] <TB1> INFO: 2560 events read in total (288ms).
[13:16:12.255] <TB1> INFO: Test took 1187ms.
[13:16:12.256] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:12.563] <TB1> INFO: Expecting 2560 events.
[13:16:13.449] <TB1> INFO: 2560 events read in total (294ms).
[13:16:13.449] <TB1> INFO: Test took 1193ms.
[13:16:13.451] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:13.757] <TB1> INFO: Expecting 2560 events.
[13:16:14.640] <TB1> INFO: 2560 events read in total (290ms).
[13:16:14.640] <TB1> INFO: Test took 1189ms.
[13:16:14.642] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:14.949] <TB1> INFO: Expecting 2560 events.
[13:16:15.834] <TB1> INFO: 2560 events read in total (294ms).
[13:16:15.834] <TB1> INFO: Test took 1192ms.
[13:16:15.836] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:16.142] <TB1> INFO: Expecting 2560 events.
[13:16:17.025] <TB1> INFO: 2560 events read in total (291ms).
[13:16:17.025] <TB1> INFO: Test took 1189ms.
[13:16:17.027] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:17.334] <TB1> INFO: Expecting 2560 events.
[13:16:18.219] <TB1> INFO: 2560 events read in total (294ms).
[13:16:18.220] <TB1> INFO: Test took 1193ms.
[13:16:18.221] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:18.528] <TB1> INFO: Expecting 2560 events.
[13:16:19.410] <TB1> INFO: 2560 events read in total (291ms).
[13:16:19.410] <TB1> INFO: Test took 1189ms.
[13:16:19.412] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:19.718] <TB1> INFO: Expecting 2560 events.
[13:16:20.600] <TB1> INFO: 2560 events read in total (290ms).
[13:16:20.600] <TB1> INFO: Test took 1189ms.
[13:16:20.602] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:20.909] <TB1> INFO: Expecting 2560 events.
[13:16:21.791] <TB1> INFO: 2560 events read in total (291ms).
[13:16:21.791] <TB1> INFO: Test took 1189ms.
[13:16:22.251] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 620 seconds
[13:16:22.251] <TB1> INFO: PH scale (per ROC): 33 37 43 47 37 48 44 51 34 43 39 34 50 36 49 49
[13:16:22.251] <TB1> INFO: PH offset (per ROC): 107 91 107 104 104 129 94 115 107 103 115 99 113 102 112 124
[13:16:22.257] <TB1> INFO: Decoding statistics:
[13:16:22.257] <TB1> INFO: General information:
[13:16:22.257] <TB1> INFO: 16bit words read: 127890
[13:16:22.257] <TB1> INFO: valid events total: 20480
[13:16:22.257] <TB1> INFO: empty events: 17975
[13:16:22.257] <TB1> INFO: valid events with pixels: 2505
[13:16:22.257] <TB1> INFO: valid pixel hits: 2505
[13:16:22.257] <TB1> INFO: Event errors: 0
[13:16:22.257] <TB1> INFO: start marker: 0
[13:16:22.257] <TB1> INFO: stop marker: 0
[13:16:22.257] <TB1> INFO: overflow: 0
[13:16:22.257] <TB1> INFO: invalid 5bit words: 0
[13:16:22.257] <TB1> INFO: invalid XOR eye diagram: 0
[13:16:22.257] <TB1> INFO: frame (failed synchr.): 0
[13:16:22.257] <TB1> INFO: idle data (no TBM trl): 0
[13:16:22.257] <TB1> INFO: no data (only TBM hdr): 0
[13:16:22.257] <TB1> INFO: TBM errors: 0
[13:16:22.257] <TB1> INFO: flawed TBM headers: 0
[13:16:22.257] <TB1> INFO: flawed TBM trailers: 0
[13:16:22.257] <TB1> INFO: event ID mismatches: 0
[13:16:22.257] <TB1> INFO: ROC errors: 0
[13:16:22.257] <TB1> INFO: missing ROC header(s): 0
[13:16:22.257] <TB1> INFO: misplaced readback start: 0
[13:16:22.257] <TB1> INFO: Pixel decoding errors: 0
[13:16:22.257] <TB1> INFO: pixel data incomplete: 0
[13:16:22.257] <TB1> INFO: pixel address: 0
[13:16:22.257] <TB1> INFO: pulse height fill bit: 0
[13:16:22.257] <TB1> INFO: buffer corruption: 0
[13:16:22.531] <TB1> INFO: ######################################################################
[13:16:22.531] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:16:22.531] <TB1> INFO: ######################################################################
[13:16:22.542] <TB1> INFO: scanning low vcal = 10
[13:16:22.778] <TB1> INFO: Expecting 41600 events.
[13:16:26.327] <TB1> INFO: 41600 events read in total (2957ms).
[13:16:26.327] <TB1> INFO: Test took 3785ms.
[13:16:26.329] <TB1> INFO: scanning low vcal = 20
[13:16:26.627] <TB1> INFO: Expecting 41600 events.
[13:16:30.205] <TB1> INFO: 41600 events read in total (2986ms).
[13:16:30.206] <TB1> INFO: Test took 3877ms.
[13:16:30.207] <TB1> INFO: scanning low vcal = 30
[13:16:30.506] <TB1> INFO: Expecting 41600 events.
[13:16:34.121] <TB1> INFO: 41600 events read in total (3023ms).
[13:16:34.122] <TB1> INFO: Test took 3915ms.
[13:16:34.125] <TB1> INFO: scanning low vcal = 40
[13:16:34.401] <TB1> INFO: Expecting 41600 events.
[13:16:38.342] <TB1> INFO: 41600 events read in total (3349ms).
[13:16:38.345] <TB1> INFO: Test took 4220ms.
[13:16:38.348] <TB1> INFO: scanning low vcal = 50
[13:16:38.625] <TB1> INFO: Expecting 41600 events.
[13:16:42.623] <TB1> INFO: 41600 events read in total (3406ms).
[13:16:42.623] <TB1> INFO: Test took 4275ms.
[13:16:42.626] <TB1> INFO: scanning low vcal = 60
[13:16:42.903] <TB1> INFO: Expecting 41600 events.
[13:16:46.855] <TB1> INFO: 41600 events read in total (3361ms).
[13:16:46.856] <TB1> INFO: Test took 4230ms.
[13:16:46.859] <TB1> INFO: scanning low vcal = 70
[13:16:47.135] <TB1> INFO: Expecting 41600 events.
[13:16:51.076] <TB1> INFO: 41600 events read in total (3349ms).
[13:16:51.077] <TB1> INFO: Test took 4218ms.
[13:16:51.080] <TB1> INFO: scanning low vcal = 80
[13:16:51.356] <TB1> INFO: Expecting 41600 events.
[13:16:55.328] <TB1> INFO: 41600 events read in total (3380ms).
[13:16:55.329] <TB1> INFO: Test took 4249ms.
[13:16:55.332] <TB1> INFO: scanning low vcal = 90
[13:16:55.608] <TB1> INFO: Expecting 41600 events.
[13:16:59.566] <TB1> INFO: 41600 events read in total (3366ms).
[13:16:59.567] <TB1> INFO: Test took 4235ms.
[13:16:59.569] <TB1> INFO: scanning low vcal = 100
[13:16:59.846] <TB1> INFO: Expecting 41600 events.
[13:17:03.762] <TB1> INFO: 41600 events read in total (3325ms).
[13:17:03.763] <TB1> INFO: Test took 4194ms.
[13:17:03.765] <TB1> INFO: scanning low vcal = 110
[13:17:04.042] <TB1> INFO: Expecting 41600 events.
[13:17:07.972] <TB1> INFO: 41600 events read in total (3339ms).
[13:17:07.973] <TB1> INFO: Test took 4207ms.
[13:17:07.975] <TB1> INFO: scanning low vcal = 120
[13:17:08.252] <TB1> INFO: Expecting 41600 events.
[13:17:12.204] <TB1> INFO: 41600 events read in total (3360ms).
[13:17:12.205] <TB1> INFO: Test took 4229ms.
[13:17:12.207] <TB1> INFO: scanning low vcal = 130
[13:17:12.484] <TB1> INFO: Expecting 41600 events.
[13:17:16.425] <TB1> INFO: 41600 events read in total (3351ms).
[13:17:16.426] <TB1> INFO: Test took 4219ms.
[13:17:16.429] <TB1> INFO: scanning low vcal = 140
[13:17:16.705] <TB1> INFO: Expecting 41600 events.
[13:17:20.672] <TB1> INFO: 41600 events read in total (3375ms).
[13:17:20.673] <TB1> INFO: Test took 4244ms.
[13:17:20.675] <TB1> INFO: scanning low vcal = 150
[13:17:20.952] <TB1> INFO: Expecting 41600 events.
[13:17:24.952] <TB1> INFO: 41600 events read in total (3409ms).
[13:17:24.953] <TB1> INFO: Test took 4278ms.
[13:17:24.956] <TB1> INFO: scanning low vcal = 160
[13:17:25.233] <TB1> INFO: Expecting 41600 events.
[13:17:29.223] <TB1> INFO: 41600 events read in total (3398ms).
[13:17:29.223] <TB1> INFO: Test took 4267ms.
[13:17:29.226] <TB1> INFO: scanning low vcal = 170
[13:17:29.503] <TB1> INFO: Expecting 41600 events.
[13:17:33.438] <TB1> INFO: 41600 events read in total (3344ms).
[13:17:33.439] <TB1> INFO: Test took 4213ms.
[13:17:33.441] <TB1> INFO: scanning low vcal = 180
[13:17:33.718] <TB1> INFO: Expecting 41600 events.
[13:17:37.670] <TB1> INFO: 41600 events read in total (3360ms).
[13:17:37.670] <TB1> INFO: Test took 4229ms.
[13:17:37.673] <TB1> INFO: scanning low vcal = 190
[13:17:37.950] <TB1> INFO: Expecting 41600 events.
[13:17:41.899] <TB1> INFO: 41600 events read in total (3358ms).
[13:17:41.900] <TB1> INFO: Test took 4227ms.
[13:17:41.902] <TB1> INFO: scanning low vcal = 200
[13:17:42.179] <TB1> INFO: Expecting 41600 events.
[13:17:46.115] <TB1> INFO: 41600 events read in total (3344ms).
[13:17:46.115] <TB1> INFO: Test took 4212ms.
[13:17:46.118] <TB1> INFO: scanning low vcal = 210
[13:17:46.394] <TB1> INFO: Expecting 41600 events.
[13:17:50.333] <TB1> INFO: 41600 events read in total (3347ms).
[13:17:50.334] <TB1> INFO: Test took 4216ms.
[13:17:50.336] <TB1> INFO: scanning low vcal = 220
[13:17:50.613] <TB1> INFO: Expecting 41600 events.
[13:17:54.555] <TB1> INFO: 41600 events read in total (3351ms).
[13:17:54.556] <TB1> INFO: Test took 4220ms.
[13:17:54.558] <TB1> INFO: scanning low vcal = 230
[13:17:54.835] <TB1> INFO: Expecting 41600 events.
[13:17:58.771] <TB1> INFO: 41600 events read in total (3345ms).
[13:17:58.772] <TB1> INFO: Test took 4214ms.
[13:17:58.774] <TB1> INFO: scanning low vcal = 240
[13:17:59.051] <TB1> INFO: Expecting 41600 events.
[13:18:03.033] <TB1> INFO: 41600 events read in total (3391ms).
[13:18:03.034] <TB1> INFO: Test took 4260ms.
[13:18:03.036] <TB1> INFO: scanning low vcal = 250
[13:18:03.313] <TB1> INFO: Expecting 41600 events.
[13:18:07.266] <TB1> INFO: 41600 events read in total (3362ms).
[13:18:07.267] <TB1> INFO: Test took 4231ms.
[13:18:07.271] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[13:18:07.547] <TB1> INFO: Expecting 41600 events.
[13:18:11.501] <TB1> INFO: 41600 events read in total (3363ms).
[13:18:11.502] <TB1> INFO: Test took 4231ms.
[13:18:11.504] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[13:18:11.781] <TB1> INFO: Expecting 41600 events.
[13:18:15.738] <TB1> INFO: 41600 events read in total (3365ms).
[13:18:15.739] <TB1> INFO: Test took 4234ms.
[13:18:15.742] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[13:18:16.018] <TB1> INFO: Expecting 41600 events.
[13:18:19.977] <TB1> INFO: 41600 events read in total (3367ms).
[13:18:19.978] <TB1> INFO: Test took 4236ms.
[13:18:19.980] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[13:18:20.257] <TB1> INFO: Expecting 41600 events.
[13:18:24.208] <TB1> INFO: 41600 events read in total (3359ms).
[13:18:24.209] <TB1> INFO: Test took 4228ms.
[13:18:24.212] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:18:24.488] <TB1> INFO: Expecting 41600 events.
[13:18:28.458] <TB1> INFO: 41600 events read in total (3378ms).
[13:18:28.459] <TB1> INFO: Test took 4247ms.
[13:18:28.942] <TB1> INFO: PixTestGainPedestal::measure() done
[13:19:06.639] <TB1> INFO: PixTestGainPedestal::fit() done
[13:19:06.639] <TB1> INFO: non-linearity mean: 0.932 0.938 0.949 0.947 0.925 0.982 0.962 0.985 0.932 0.947 0.958 1.034 0.981 0.925 0.971 0.981
[13:19:06.639] <TB1> INFO: non-linearity RMS: 0.096 0.076 0.050 0.099 0.156 0.003 0.026 0.004 0.144 0.061 0.036 0.165 0.003 0.121 0.012 0.004
[13:19:06.639] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[13:19:06.656] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[13:19:06.670] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[13:19:06.684] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[13:19:06.699] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[13:19:06.713] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[13:19:06.727] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[13:19:06.746] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[13:19:06.768] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[13:19:06.791] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[13:19:06.813] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[13:19:06.835] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[13:19:06.858] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[13:19:06.880] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[13:19:06.902] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[13:19:06.925] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[13:19:06.947] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 164 seconds
[13:19:06.947] <TB1> INFO: Decoding statistics:
[13:19:06.947] <TB1> INFO: General information:
[13:19:06.947] <TB1> INFO: 16bit words read: 3297942
[13:19:06.947] <TB1> INFO: valid events total: 332800
[13:19:06.947] <TB1> INFO: empty events: 783
[13:19:06.947] <TB1> INFO: valid events with pixels: 332017
[13:19:06.947] <TB1> INFO: valid pixel hits: 650571
[13:19:06.947] <TB1> INFO: Event errors: 0
[13:19:06.947] <TB1> INFO: start marker: 0
[13:19:06.947] <TB1> INFO: stop marker: 0
[13:19:06.947] <TB1> INFO: overflow: 0
[13:19:06.947] <TB1> INFO: invalid 5bit words: 0
[13:19:06.947] <TB1> INFO: invalid XOR eye diagram: 0
[13:19:06.947] <TB1> INFO: frame (failed synchr.): 0
[13:19:06.947] <TB1> INFO: idle data (no TBM trl): 0
[13:19:06.947] <TB1> INFO: no data (only TBM hdr): 0
[13:19:06.947] <TB1> INFO: TBM errors: 0
[13:19:06.947] <TB1> INFO: flawed TBM headers: 0
[13:19:06.947] <TB1> INFO: flawed TBM trailers: 0
[13:19:06.947] <TB1> INFO: event ID mismatches: 0
[13:19:06.947] <TB1> INFO: ROC errors: 0
[13:19:06.947] <TB1> INFO: missing ROC header(s): 0
[13:19:06.947] <TB1> INFO: misplaced readback start: 0
[13:19:06.947] <TB1> INFO: Pixel decoding errors: 0
[13:19:06.947] <TB1> INFO: pixel data incomplete: 0
[13:19:06.947] <TB1> INFO: pixel address: 0
[13:19:06.947] <TB1> INFO: pulse height fill bit: 0
[13:19:06.947] <TB1> INFO: buffer corruption: 0
[13:19:06.967] <TB1> INFO: Decoding statistics:
[13:19:06.967] <TB1> INFO: General information:
[13:19:06.967] <TB1> INFO: 16bit words read: 3427368
[13:19:06.967] <TB1> INFO: valid events total: 353536
[13:19:06.967] <TB1> INFO: empty events: 19014
[13:19:06.967] <TB1> INFO: valid events with pixels: 334522
[13:19:06.967] <TB1> INFO: valid pixel hits: 653076
[13:19:06.967] <TB1> INFO: Event errors: 0
[13:19:06.967] <TB1> INFO: start marker: 0
[13:19:06.967] <TB1> INFO: stop marker: 0
[13:19:06.967] <TB1> INFO: overflow: 0
[13:19:06.967] <TB1> INFO: invalid 5bit words: 0
[13:19:06.967] <TB1> INFO: invalid XOR eye diagram: 0
[13:19:06.967] <TB1> INFO: frame (failed synchr.): 0
[13:19:06.967] <TB1> INFO: idle data (no TBM trl): 0
[13:19:06.967] <TB1> INFO: no data (only TBM hdr): 0
[13:19:06.967] <TB1> INFO: TBM errors: 0
[13:19:06.967] <TB1> INFO: flawed TBM headers: 0
[13:19:06.967] <TB1> INFO: flawed TBM trailers: 0
[13:19:06.967] <TB1> INFO: event ID mismatches: 0
[13:19:06.967] <TB1> INFO: ROC errors: 0
[13:19:06.967] <TB1> INFO: missing ROC header(s): 0
[13:19:06.967] <TB1> INFO: misplaced readback start: 0
[13:19:06.967] <TB1> INFO: Pixel decoding errors: 0
[13:19:06.967] <TB1> INFO: pixel data incomplete: 0
[13:19:06.967] <TB1> INFO: pixel address: 0
[13:19:06.967] <TB1> INFO: pulse height fill bit: 0
[13:19:06.967] <TB1> INFO: buffer corruption: 0
[13:19:06.967] <TB1> INFO: enter test to run
[13:19:06.967] <TB1> INFO: test: Trim80 no parameter change
[13:19:06.967] <TB1> INFO: running: trim80
[13:19:06.983] <TB1> INFO: ######################################################################
[13:19:06.983] <TB1> INFO: PixTestTrim80::doTest()
[13:19:06.983] <TB1> INFO: ######################################################################
[13:19:06.984] <TB1> INFO: ----------------------------------------------------------------------
[13:19:06.984] <TB1> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[13:19:06.984] <TB1> INFO: ----------------------------------------------------------------------
[13:19:07.026] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:19:07.026] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:19:07.034] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:19:07.034] <TB1> INFO: run 1 of 1
[13:19:07.266] <TB1> INFO: Expecting 5025280 events.
[13:19:35.181] <TB1> INFO: 685728 events read in total (27324ms).
[13:20:02.422] <TB1> INFO: 1367520 events read in total (54565ms).
[13:20:29.738] <TB1> INFO: 2047160 events read in total (81881ms).
[13:20:57.040] <TB1> INFO: 2725112 events read in total (109183ms).
[13:21:23.917] <TB1> INFO: 3403192 events read in total (136060ms).
[13:21:51.082] <TB1> INFO: 4081160 events read in total (163225ms).
[13:22:18.157] <TB1> INFO: 4759200 events read in total (190300ms).
[13:22:29.050] <TB1> INFO: 5025280 events read in total (201193ms).
[13:22:29.115] <TB1> INFO: Test took 202082ms.
[13:22:53.037] <TB1> INFO: ROC 0 VthrComp = 75
[13:22:53.037] <TB1> INFO: ROC 1 VthrComp = 85
[13:22:53.037] <TB1> INFO: ROC 2 VthrComp = 77
[13:22:53.037] <TB1> INFO: ROC 3 VthrComp = 76
[13:22:53.037] <TB1> INFO: ROC 4 VthrComp = 74
[13:22:53.037] <TB1> INFO: ROC 5 VthrComp = 81
[13:22:53.037] <TB1> INFO: ROC 6 VthrComp = 81
[13:22:53.038] <TB1> INFO: ROC 7 VthrComp = 74
[13:22:53.038] <TB1> INFO: ROC 8 VthrComp = 78
[13:22:53.038] <TB1> INFO: ROC 9 VthrComp = 80
[13:22:53.038] <TB1> INFO: ROC 10 VthrComp = 73
[13:22:53.038] <TB1> INFO: ROC 11 VthrComp = 72
[13:22:53.038] <TB1> INFO: ROC 12 VthrComp = 79
[13:22:53.038] <TB1> INFO: ROC 13 VthrComp = 82
[13:22:53.038] <TB1> INFO: ROC 14 VthrComp = 71
[13:22:53.038] <TB1> INFO: ROC 15 VthrComp = 75
[13:22:53.282] <TB1> INFO: Expecting 41600 events.
[13:22:56.766] <TB1> INFO: 41600 events read in total (2893ms).
[13:22:56.767] <TB1> INFO: Test took 3727ms.
[13:22:56.777] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:22:56.777] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:22:56.786] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:22:56.786] <TB1> INFO: run 1 of 1
[13:22:57.065] <TB1> INFO: Expecting 5025280 events.
[13:23:24.985] <TB1> INFO: 686032 events read in total (27329ms).
[13:23:52.222] <TB1> INFO: 1367360 events read in total (54566ms).
[13:24:18.929] <TB1> INFO: 2049120 events read in total (81273ms).
[13:24:46.019] <TB1> INFO: 2728336 events read in total (108363ms).
[13:25:12.833] <TB1> INFO: 3403792 events read in total (135177ms).
[13:25:39.002] <TB1> INFO: 4079328 events read in total (162346ms).
[13:26:06.878] <TB1> INFO: 4753096 events read in total (189222ms).
[13:26:17.582] <TB1> INFO: 5025280 events read in total (199926ms).
[13:26:17.628] <TB1> INFO: Test took 200841ms.
[13:26:42.615] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 112.903 for pixel 14/79 mean/min/max = 95.3059/77.6429/112.969
[13:26:42.616] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 109.852 for pixel 6/4 mean/min/max = 92.1374/74.4164/109.858
[13:26:42.616] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 112.871 for pixel 51/79 mean/min/max = 95.1308/77.3318/112.93
[13:26:42.617] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 110.441 for pixel 0/18 mean/min/max = 94.6296/78.4757/110.784
[13:26:42.617] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 108.885 for pixel 0/0 mean/min/max = 93.1463/77.3756/108.917
[13:26:42.618] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 105.645 for pixel 19/21 mean/min/max = 90.7014/75.6155/105.787
[13:26:42.618] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 109.564 for pixel 1/12 mean/min/max = 92.4428/75.2532/109.632
[13:26:42.618] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 112.695 for pixel 5/11 mean/min/max = 95.608/78.1788/113.037
[13:26:42.619] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 111.507 for pixel 0/3 mean/min/max = 95.3007/78.9354/111.666
[13:26:42.619] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 108.352 for pixel 16/4 mean/min/max = 91.4182/74.2334/108.603
[13:26:42.620] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 113.806 for pixel 0/73 mean/min/max = 95.4222/77.0364/113.808
[13:26:42.620] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 108.554 for pixel 10/70 mean/min/max = 93.1212/77.4786/108.764
[13:26:42.620] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 108.845 for pixel 0/8 mean/min/max = 93.1661/77.3903/108.942
[13:26:42.621] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 108.08 for pixel 22/75 mean/min/max = 91.4096/74.5293/108.29
[13:26:42.621] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 105.54 for pixel 0/50 mean/min/max = 90.0925/74.3059/105.879
[13:26:42.621] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 107.829 for pixel 0/6 mean/min/max = 93.0044/78.0184/107.99
[13:26:42.622] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:26:42.710] <TB1> INFO: Expecting 411648 events.
[13:26:52.230] <TB1> INFO: 411648 events read in total (8928ms).
[13:26:52.237] <TB1> INFO: Expecting 411648 events.
[13:27:01.434] <TB1> INFO: 411648 events read in total (8790ms).
[13:27:01.445] <TB1> INFO: Expecting 411648 events.
[13:27:10.548] <TB1> INFO: 411648 events read in total (8700ms).
[13:27:10.560] <TB1> INFO: Expecting 411648 events.
[13:27:19.710] <TB1> INFO: 411648 events read in total (8747ms).
[13:27:19.725] <TB1> INFO: Expecting 411648 events.
[13:27:28.815] <TB1> INFO: 411648 events read in total (8686ms).
[13:27:28.832] <TB1> INFO: Expecting 411648 events.
[13:27:38.048] <TB1> INFO: 411648 events read in total (8813ms).
[13:27:38.076] <TB1> INFO: Expecting 411648 events.
[13:27:47.236] <TB1> INFO: 411648 events read in total (8757ms).
[13:27:47.258] <TB1> INFO: Expecting 411648 events.
[13:27:56.248] <TB1> INFO: 411648 events read in total (8587ms).
[13:27:56.284] <TB1> INFO: Expecting 411648 events.
[13:28:05.376] <TB1> INFO: 411648 events read in total (8689ms).
[13:28:05.405] <TB1> INFO: Expecting 411648 events.
[13:28:14.517] <TB1> INFO: 411648 events read in total (8709ms).
[13:28:14.546] <TB1> INFO: Expecting 411648 events.
[13:28:23.601] <TB1> INFO: 411648 events read in total (8652ms).
[13:28:23.634] <TB1> INFO: Expecting 411648 events.
[13:28:32.671] <TB1> INFO: 411648 events read in total (8635ms).
[13:28:32.712] <TB1> INFO: Expecting 411648 events.
[13:28:41.814] <TB1> INFO: 411648 events read in total (8699ms).
[13:28:41.854] <TB1> INFO: Expecting 411648 events.
[13:28:50.936] <TB1> INFO: 411648 events read in total (8679ms).
[13:28:50.977] <TB1> INFO: Expecting 411648 events.
[13:29:00.078] <TB1> INFO: 411648 events read in total (8699ms).
[13:29:00.140] <TB1> INFO: Expecting 411648 events.
[13:29:09.217] <TB1> INFO: 411648 events read in total (8674ms).
[13:29:09.264] <TB1> INFO: Test took 146642ms.
[13:29:10.832] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:29:10.843] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:29:10.843] <TB1> INFO: run 1 of 1
[13:29:11.075] <TB1> INFO: Expecting 5025280 events.
[13:29:38.081] <TB1> INFO: 666448 events read in total (26415ms).
[13:30:04.314] <TB1> INFO: 1330336 events read in total (52648ms).
[13:30:30.001] <TB1> INFO: 1994384 events read in total (79335ms).
[13:30:57.542] <TB1> INFO: 2655784 events read in total (105876ms).
[13:31:24.146] <TB1> INFO: 3312208 events read in total (132480ms).
[13:31:50.974] <TB1> INFO: 3967336 events read in total (159308ms).
[13:32:17.522] <TB1> INFO: 4621904 events read in total (185856ms).
[13:32:34.066] <TB1> INFO: 5025280 events read in total (202400ms).
[13:32:34.125] <TB1> INFO: Test took 203282ms.
[13:32:59.517] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 52.224839 .. 103.332434
[13:32:59.752] <TB1> INFO: Expecting 208000 events.
[13:33:09.469] <TB1> INFO: 208000 events read in total (9125ms).
[13:33:09.470] <TB1> INFO: Test took 9951ms.
[13:33:09.516] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 42 .. 113 (-1/-1) hits flags = 528 (plus default)
[13:33:09.526] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:33:09.526] <TB1> INFO: run 1 of 1
[13:33:09.804] <TB1> INFO: Expecting 2396160 events.
[13:33:37.957] <TB1> INFO: 683904 events read in total (27561ms).
[13:34:05.304] <TB1> INFO: 1366216 events read in total (54908ms).
[13:34:32.410] <TB1> INFO: 2041776 events read in total (82014ms).
[13:34:46.649] <TB1> INFO: 2396160 events read in total (96253ms).
[13:34:46.681] <TB1> INFO: Test took 97155ms.
[13:35:04.509] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 62.999825 .. 92.831775
[13:35:04.743] <TB1> INFO: Expecting 208000 events.
[13:35:14.545] <TB1> INFO: 208000 events read in total (9210ms).
[13:35:14.546] <TB1> INFO: Test took 10036ms.
[13:35:14.594] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 52 .. 102 (-1/-1) hits flags = 528 (plus default)
[13:35:14.603] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:35:14.603] <TB1> INFO: run 1 of 1
[13:35:14.880] <TB1> INFO: Expecting 1697280 events.
[13:35:43.319] <TB1> INFO: 689176 events read in total (27847ms).
[13:36:11.873] <TB1> INFO: 1377592 events read in total (56402ms).
[13:36:24.735] <TB1> INFO: 1697280 events read in total (69263ms).
[13:36:24.764] <TB1> INFO: Test took 70161ms.
[13:36:43.624] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 66.326655 .. 91.018996
[13:36:43.893] <TB1> INFO: Expecting 208000 events.
[13:36:53.411] <TB1> INFO: 208000 events read in total (8927ms).
[13:36:53.412] <TB1> INFO: Test took 9787ms.
[13:36:53.457] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 56 .. 101 (-1/-1) hits flags = 528 (plus default)
[13:36:53.467] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:36:53.467] <TB1> INFO: run 1 of 1
[13:36:53.745] <TB1> INFO: Expecting 1530880 events.
[13:37:21.813] <TB1> INFO: 680016 events read in total (27476ms).
[13:37:49.267] <TB1> INFO: 1359176 events read in total (54930ms).
[13:37:56.552] <TB1> INFO: 1530880 events read in total (62216ms).
[13:37:56.577] <TB1> INFO: Test took 63110ms.
[13:38:13.962] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 69.620994 .. 94.107483
[13:38:14.234] <TB1> INFO: Expecting 208000 events.
[13:38:24.130] <TB1> INFO: 208000 events read in total (9304ms).
[13:38:24.130] <TB1> INFO: Test took 10167ms.
[13:38:24.179] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 59 .. 104 (-1/-1) hits flags = 528 (plus default)
[13:38:24.190] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:38:24.190] <TB1> INFO: run 1 of 1
[13:38:24.468] <TB1> INFO: Expecting 1530880 events.
[13:38:52.046] <TB1> INFO: 659208 events read in total (26987ms).
[13:39:19.387] <TB1> INFO: 1317824 events read in total (54328ms).
[13:39:28.490] <TB1> INFO: 1530880 events read in total (63431ms).
[13:39:28.516] <TB1> INFO: Test took 64326ms.
[13:39:47.550] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[13:39:47.550] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[13:39:47.561] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:39:47.561] <TB1> INFO: run 1 of 1
[13:39:47.825] <TB1> INFO: Expecting 1364480 events.
[13:40:17.130] <TB1> INFO: 668744 events read in total (28714ms).
[13:40:44.411] <TB1> INFO: 1336128 events read in total (55995ms).
[13:40:45.999] <TB1> INFO: 1364480 events read in total (57583ms).
[13:40:46.018] <TB1> INFO: Test took 58456ms.
[13:41:03.108] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C0.dat
[13:41:03.108] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C1.dat
[13:41:03.108] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C2.dat
[13:41:03.108] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C3.dat
[13:41:03.108] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C4.dat
[13:41:03.108] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C5.dat
[13:41:03.109] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C6.dat
[13:41:03.109] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C7.dat
[13:41:03.109] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C8.dat
[13:41:03.109] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C9.dat
[13:41:03.109] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C10.dat
[13:41:03.109] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C11.dat
[13:41:03.109] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C12.dat
[13:41:03.109] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C13.dat
[13:41:03.109] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C14.dat
[13:41:03.109] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//dacParameters80_C15.dat
[13:41:03.110] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C0.dat
[13:41:03.118] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C1.dat
[13:41:03.126] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C2.dat
[13:41:03.134] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C3.dat
[13:41:03.143] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C4.dat
[13:41:03.151] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C5.dat
[13:41:03.159] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C6.dat
[13:41:03.167] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C7.dat
[13:41:03.176] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C8.dat
[13:41:03.184] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C9.dat
[13:41:03.193] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C10.dat
[13:41:03.202] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C11.dat
[13:41:03.209] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C12.dat
[13:41:03.214] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C13.dat
[13:41:03.220] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C14.dat
[13:41:03.225] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_09h16m_1478161005//003_FulltestTrim80_p17//trimParameters80_C15.dat
[13:41:03.231] <TB1> INFO: PixTestTrim80::trimTest() done
[13:41:03.231] <TB1> INFO: vtrim: 133 117 108 110 104 107 118 118 119 104 110 102 119 98 97 103
[13:41:03.231] <TB1> INFO: vthrcomp: 75 85 77 76 74 81 81 74 78 80 73 72 79 82 71 75
[13:41:03.231] <TB1> INFO: vcal mean: 79.96 79.94 79.98 79.98 79.99 79.96 79.99 79.99 80.01 79.98 79.95 79.96 79.99 79.95 79.97 79.95
[13:41:03.231] <TB1> INFO: vcal RMS: 0.78 0.76 0.76 0.69 0.68 0.69 0.80 0.75 0.78 0.77 0.77 0.68 0.75 0.75 0.78 0.69
[13:41:03.231] <TB1> INFO: bits mean: 9.96 10.48 9.75 9.25 9.69 10.24 10.32 9.69 9.73 10.65 9.33 9.57 10.09 10.37 10.66 9.36
[13:41:03.231] <TB1> INFO: bits RMS: 1.97 2.21 2.07 2.17 2.19 2.29 2.21 2.05 1.93 2.14 2.33 2.25 2.04 2.25 2.25 2.27
[13:41:03.238] <TB1> INFO: ----------------------------------------------------------------------
[13:41:03.238] <TB1> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:41:03.238] <TB1> INFO: ----------------------------------------------------------------------
[13:41:03.240] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:41:03.251] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:41:03.251] <TB1> INFO: run 1 of 1
[13:41:03.484] <TB1> INFO: Expecting 4160000 events.
[13:41:35.543] <TB1> INFO: 772645 events read in total (31468ms).
[13:42:07.631] <TB1> INFO: 1537735 events read in total (63556ms).
[13:42:39.330] <TB1> INFO: 2297865 events read in total (95255ms).
[13:43:10.897] <TB1> INFO: 3053395 events read in total (126822ms).
[13:43:42.345] <TB1> INFO: 3808630 events read in total (158270ms).
[13:43:57.006] <TB1> INFO: 4160000 events read in total (172931ms).
[13:43:57.050] <TB1> INFO: Test took 173799ms.
[13:44:23.130] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[13:44:23.140] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:44:23.140] <TB1> INFO: run 1 of 1
[13:44:23.373] <TB1> INFO: Expecting 4326400 events.
[13:44:55.102] <TB1> INFO: 736595 events read in total (31137ms).
[13:45:25.952] <TB1> INFO: 1467795 events read in total (61987ms).
[13:45:57.055] <TB1> INFO: 2195490 events read in total (93090ms).
[13:46:27.671] <TB1> INFO: 2919370 events read in total (123706ms).
[13:46:58.345] <TB1> INFO: 3642670 events read in total (154380ms).
[13:47:27.188] <TB1> INFO: 4326400 events read in total (183223ms).
[13:47:27.250] <TB1> INFO: Test took 184110ms.
[13:47:54.630] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[13:47:54.640] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:47:54.640] <TB1> INFO: run 1 of 1
[13:47:54.896] <TB1> INFO: Expecting 4305600 events.
[13:48:26.537] <TB1> INFO: 738310 events read in total (31049ms).
[13:48:57.608] <TB1> INFO: 1471200 events read in total (62120ms).
[13:49:28.917] <TB1> INFO: 2200470 events read in total (93429ms).
[13:50:00.360] <TB1> INFO: 2925955 events read in total (124872ms).
[13:50:31.199] <TB1> INFO: 3651090 events read in total (155711ms).
[13:50:59.169] <TB1> INFO: 4305600 events read in total (183681ms).
[13:50:59.229] <TB1> INFO: Test took 184587ms.
[13:51:24.634] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[13:51:24.645] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:51:24.645] <TB1> INFO: run 1 of 1
[13:51:24.877] <TB1> INFO: Expecting 4305600 events.
[13:51:56.314] <TB1> INFO: 738560 events read in total (30846ms).
[13:52:27.413] <TB1> INFO: 1471450 events read in total (61945ms).
[13:52:58.587] <TB1> INFO: 2200735 events read in total (93120ms).
[13:53:31.127] <TB1> INFO: 2926365 events read in total (125659ms).
[13:54:02.496] <TB1> INFO: 3651395 events read in total (157028ms).
[13:54:30.458] <TB1> INFO: 4305600 events read in total (184990ms).
[13:54:30.513] <TB1> INFO: Test took 185868ms.
[13:54:55.805] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 209 (-1/-1) hits flags = 528 (plus default)
[13:54:55.815] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:54:55.815] <TB1> INFO: run 1 of 1
[13:54:56.055] <TB1> INFO: Expecting 4368000 events.
[13:55:27.959] <TB1> INFO: 734455 events read in total (31312ms).
[13:55:59.107] <TB1> INFO: 1463640 events read in total (62460ms).
[13:56:29.881] <TB1> INFO: 2189405 events read in total (93234ms).
[13:57:01.873] <TB1> INFO: 2911160 events read in total (125226ms).
[13:57:32.640] <TB1> INFO: 3632790 events read in total (155993ms).
[13:58:03.391] <TB1> INFO: 4354270 events read in total (186744ms).
[13:58:04.392] <TB1> INFO: 4368000 events read in total (187745ms).
[13:58:04.443] <TB1> INFO: Test took 188627ms.
[13:58:30.840] <TB1> INFO: PixTestTrim80::trimBitTest() done
[13:58:30.842] <TB1> INFO: PixTestTrim80::doTest() done, duration: 2363 seconds
[13:58:31.594] <TB1> INFO: enter test to run
[13:58:31.594] <TB1> INFO: test: exit no parameter change
[13:58:31.703] <TB1> QUIET: Connection to board 153 closed.
[13:58:31.705] <TB1> INFO: pXar: this is the end, my friend