[11:32:16.392] <TB3> INFO: *** Welcome to pxar ***
[11:32:16.392] <TB3> INFO: *** Today: 2016/11/03
[11:32:16.399] <TB3> INFO: *** Version: c8ba-dirty
[11:32:16.399] <TB3> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C15.dat
[11:32:16.400] <TB3> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[11:32:16.400] <TB3> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//defaultMaskFile.dat
[11:32:16.400] <TB3> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters_C15.dat
[11:32:16.462] <TB3> INFO: clk: 4
[11:32:16.462] <TB3> INFO: ctr: 4
[11:32:16.462] <TB3> INFO: sda: 19
[11:32:16.462] <TB3> INFO: tin: 9
[11:32:16.462] <TB3> INFO: level: 15
[11:32:16.462] <TB3> INFO: triggerdelay: 0
[11:32:16.463] <TB3> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[11:32:16.463] <TB3> INFO: Log level: INFO
[11:32:16.472] <TB3> INFO: Found DTB DTB_WWVASW
[11:32:16.481] <TB3> QUIET: Connection to board DTB_WWVASW opened.
[11:32:16.483] <TB3> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 126
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWVASW
MAC address: 40D85511807E
Hostname: pixelDTB126
Comment:
------------------------------------------------------
[11:32:16.484] <TB3> INFO: RPC call hashes of host and DTB match: 486171790
[11:32:17.003] <TB3> INFO: DUT info:
[11:32:17.003] <TB3> INFO: The DUT currently contains the following objects:
[11:32:17.003] <TB3> INFO: 4 TBM Cores tbm10c (4 ON)
[11:32:17.003] <TB3> INFO: TBM Core alpha (0): 7 registers set
[11:32:17.003] <TB3> INFO: TBM Core beta (1): 7 registers set
[11:32:17.003] <TB3> INFO: TBM Core alpha (2): 7 registers set
[11:32:18.003] <TB3> INFO: TBM Core beta (3): 7 registers set
[11:32:18.003] <TB3> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:32:18.003] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.003] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:18.404] <TB3> INFO: enter 'restricted' command line mode
[11:32:18.404] <TB3> INFO: enter test to run
[11:32:18.404] <TB3> INFO: test: pretest no parameter change
[11:32:18.404] <TB3> INFO: running: pretest
[11:32:18.410] <TB3> INFO: ######################################################################
[11:32:18.410] <TB3> INFO: PixTestPretest::doTest()
[11:32:18.410] <TB3> INFO: ######################################################################
[11:32:18.411] <TB3> INFO: ----------------------------------------------------------------------
[11:32:18.411] <TB3> INFO: PixTestPretest::programROC()
[11:32:18.411] <TB3> INFO: ----------------------------------------------------------------------
[11:32:36.424] <TB3> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:32:36.424] <TB3> INFO: IA differences per ROC: 16.1 19.3 16.1 16.1 19.3 18.5 20.1 20.1 19.3 18.5 20.1 19.3 18.5 16.1 19.3 19.3
[11:32:36.487] <TB3> INFO: ----------------------------------------------------------------------
[11:32:36.487] <TB3> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:32:36.487] <TB3> INFO: ----------------------------------------------------------------------
[11:32:57.740] <TB3> INFO: PixTestPretest::setVana() done, Module Ia 389.1 mA = 24.3188 mA/ROC
[11:32:57.740] <TB3> INFO: i(loss) [mA/ROC]: 19.3 19.3 19.3 19.3 20.1 19.3 19.3 19.3 20.1 18.5 20.1 19.3 20.1 19.3 19.3 19.3
[11:32:57.768] <TB3> INFO: ----------------------------------------------------------------------
[11:32:57.768] <TB3> INFO: PixTestPretest::findTiming()
[11:32:57.768] <TB3> INFO: ----------------------------------------------------------------------
[11:32:57.769] <TB3> INFO: PixTestCmd::init()

[11:33:29.071] <TB3> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:33:29.071] <TB3> INFO: (success/tries = 100/100), width = 4
[11:33:30.577] <TB3> INFO: ----------------------------------------------------------------------
[11:33:30.577] <TB3> INFO: PixTestPretest::findWorkingPixel()
[11:33:30.577] <TB3> INFO: ----------------------------------------------------------------------
[11:33:30.670] <TB3> INFO: Expecting 231680 events.
[11:33:40.367] <TB3> INFO: 231680 events read in total (9106ms).
[11:33:40.376] <TB3> INFO: Test took 9796ms.
[11:33:40.616] <TB3> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:33:40.644] <TB3> INFO: ----------------------------------------------------------------------
[11:33:40.644] <TB3> INFO: PixTestPretest::setVthrCompCalDel()
[11:33:40.644] <TB3> INFO: ----------------------------------------------------------------------
[11:33:40.737] <TB3> INFO: Expecting 231680 events.
[11:33:50.381] <TB3> INFO: 231680 events read in total (9052ms).
[11:33:50.393] <TB3> INFO: Test took 9745ms.
[11:33:50.645] <TB3> INFO: PixTestPretest::setVthrCompCalDel() done
[11:33:50.645] <TB3> INFO: CalDel: 83 96 80 75 99 88 74 84 85 92 74 90 85 75 81 90
[11:33:50.645] <TB3> INFO: VthrComp: 51 51 51 51 51 51 51 52 51 51 53 51 51 51 51 51
[11:33:50.647] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C0.dat
[11:33:50.648] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C1.dat
[11:33:50.648] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C2.dat
[11:33:50.648] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C3.dat
[11:33:50.648] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C4.dat
[11:33:50.648] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C5.dat
[11:33:50.648] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C6.dat
[11:33:50.648] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C7.dat
[11:33:50.648] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C8.dat
[11:33:50.648] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C9.dat
[11:33:50.648] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C10.dat
[11:33:50.649] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C11.dat
[11:33:50.649] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C12.dat
[11:33:50.649] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C13.dat
[11:33:50.649] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C14.dat
[11:33:50.649] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C15.dat
[11:33:50.649] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[11:33:50.649] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[11:33:50.649] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[11:33:50.649] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[11:33:50.649] <TB3> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[11:33:50.701] <TB3> INFO: enter test to run
[11:33:50.701] <TB3> INFO: test: fulltest no parameter change
[11:33:50.701] <TB3> INFO: running: fulltest
[11:33:50.701] <TB3> INFO: ######################################################################
[11:33:50.701] <TB3> INFO: PixTestFullTest::doTest()
[11:33:50.701] <TB3> INFO: ######################################################################
[11:33:50.702] <TB3> INFO: ######################################################################
[11:33:50.702] <TB3> INFO: PixTestAlive::doTest()
[11:33:50.702] <TB3> INFO: ######################################################################
[11:33:50.703] <TB3> INFO: ----------------------------------------------------------------------
[11:33:50.703] <TB3> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:33:50.703] <TB3> INFO: ----------------------------------------------------------------------
[11:33:50.942] <TB3> INFO: Expecting 41600 events.
[11:33:54.454] <TB3> INFO: 41600 events read in total (2920ms).
[11:33:54.455] <TB3> INFO: Test took 3750ms.
[11:33:54.688] <TB3> INFO: PixTestAlive::aliveTest() done
[11:33:54.688] <TB3> INFO: number of dead pixels (per ROC): 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1
[11:33:54.689] <TB3> INFO: ----------------------------------------------------------------------
[11:33:54.689] <TB3> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:33:54.689] <TB3> INFO: ----------------------------------------------------------------------
[11:33:54.927] <TB3> INFO: Expecting 41600 events.
[11:33:57.862] <TB3> INFO: 41600 events read in total (2343ms).
[11:33:57.862] <TB3> INFO: Test took 3171ms.
[11:33:57.863] <TB3> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:33:58.102] <TB3> INFO: PixTestAlive::maskTest() done
[11:33:58.102] <TB3> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:33:58.104] <TB3> INFO: ----------------------------------------------------------------------
[11:33:58.104] <TB3> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:33:58.104] <TB3> INFO: ----------------------------------------------------------------------
[11:33:58.374] <TB3> INFO: Expecting 41600 events.
[11:34:01.917] <TB3> INFO: 41600 events read in total (2952ms).
[11:34:01.918] <TB3> INFO: Test took 3813ms.
[11:34:02.146] <TB3> INFO: PixTestAlive::addressDecodingTest() done
[11:34:02.146] <TB3> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:34:02.146] <TB3> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:34:02.146] <TB3> INFO: Decoding statistics:
[11:34:02.146] <TB3> INFO: General information:
[11:34:02.146] <TB3> INFO: 16bit words read: 0
[11:34:02.146] <TB3> INFO: valid events total: 0
[11:34:02.146] <TB3> INFO: empty events: 0
[11:34:02.146] <TB3> INFO: valid events with pixels: 0
[11:34:02.146] <TB3> INFO: valid pixel hits: 0
[11:34:02.146] <TB3> INFO: Event errors: 0
[11:34:02.146] <TB3> INFO: start marker: 0
[11:34:02.146] <TB3> INFO: stop marker: 0
[11:34:02.146] <TB3> INFO: overflow: 0
[11:34:02.146] <TB3> INFO: invalid 5bit words: 0
[11:34:02.146] <TB3> INFO: invalid XOR eye diagram: 0
[11:34:02.146] <TB3> INFO: frame (failed synchr.): 0
[11:34:02.146] <TB3> INFO: idle data (no TBM trl): 0
[11:34:02.146] <TB3> INFO: no data (only TBM hdr): 0
[11:34:02.146] <TB3> INFO: TBM errors: 0
[11:34:02.146] <TB3> INFO: flawed TBM headers: 0
[11:34:02.146] <TB3> INFO: flawed TBM trailers: 0
[11:34:02.146] <TB3> INFO: event ID mismatches: 0
[11:34:02.146] <TB3> INFO: ROC errors: 0
[11:34:02.146] <TB3> INFO: missing ROC header(s): 0
[11:34:02.146] <TB3> INFO: misplaced readback start: 0
[11:34:02.146] <TB3> INFO: Pixel decoding errors: 0
[11:34:02.147] <TB3> INFO: pixel data incomplete: 0
[11:34:02.147] <TB3> INFO: pixel address: 0
[11:34:02.147] <TB3> INFO: pulse height fill bit: 0
[11:34:02.147] <TB3> INFO: buffer corruption: 0
[11:34:02.154] <TB3> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:34:02.155] <TB3> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[11:34:02.155] <TB3> INFO: ######################################################################
[11:34:02.155] <TB3> INFO: PixTestReadback::doTest()
[11:34:02.155] <TB3> INFO: ######################################################################
[11:34:02.155] <TB3> INFO: ----------------------------------------------------------------------
[11:34:02.155] <TB3> INFO: PixTestReadback::CalibrateVd()
[11:34:02.155] <TB3> INFO: ----------------------------------------------------------------------
[11:34:12.077] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C0.dat
[11:34:12.077] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C1.dat
[11:34:12.077] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C2.dat
[11:34:12.077] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C3.dat
[11:34:12.077] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C4.dat
[11:34:12.077] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C5.dat
[11:34:12.077] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C6.dat
[11:34:12.077] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C7.dat
[11:34:12.077] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C8.dat
[11:34:12.077] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C9.dat
[11:34:12.077] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C10.dat
[11:34:12.078] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C11.dat
[11:34:12.078] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C12.dat
[11:34:12.078] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C13.dat
[11:34:12.078] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C14.dat
[11:34:12.078] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:34:12.106] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[11:34:12.106] <TB3> INFO: ----------------------------------------------------------------------
[11:34:12.106] <TB3> INFO: PixTestReadback::CalibrateVa()
[11:34:12.106] <TB3> INFO: ----------------------------------------------------------------------
[11:34:21.998] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C0.dat
[11:34:21.998] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C1.dat
[11:34:21.998] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C2.dat
[11:34:21.998] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C3.dat
[11:34:21.998] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C4.dat
[11:34:21.999] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C5.dat
[11:34:21.999] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C6.dat
[11:34:21.999] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C7.dat
[11:34:21.999] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C8.dat
[11:34:21.999] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C9.dat
[11:34:21.999] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C10.dat
[11:34:21.999] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C11.dat
[11:34:21.999] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C12.dat
[11:34:21.999] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C13.dat
[11:34:21.999] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C14.dat
[11:34:21.999] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:34:22.027] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[11:34:22.027] <TB3> INFO: ----------------------------------------------------------------------
[11:34:22.027] <TB3> INFO: PixTestReadback::readbackVbg()
[11:34:22.027] <TB3> INFO: ----------------------------------------------------------------------
[11:34:29.673] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[11:34:29.673] <TB3> INFO: ----------------------------------------------------------------------
[11:34:29.673] <TB3> INFO: PixTestReadback::getCalibratedVbg()
[11:34:29.673] <TB3> INFO: ----------------------------------------------------------------------
[11:34:29.673] <TB3> INFO: Vbg will be calibrated using Vd calibration
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 161.1calibrated Vbg = 1.2212 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 151.8calibrated Vbg = 1.21924 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 150.5calibrated Vbg = 1.20725 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 152.2calibrated Vbg = 1.20258 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 158.1calibrated Vbg = 1.21622 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 152.7calibrated Vbg = 1.22214 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 161.9calibrated Vbg = 1.21705 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 157calibrated Vbg = 1.21605 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 163.8calibrated Vbg = 1.21631 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 158.9calibrated Vbg = 1.21465 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 156.8calibrated Vbg = 1.20046 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 155calibrated Vbg = 1.20402 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 148.5calibrated Vbg = 1.2101 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 153.1calibrated Vbg = 1.20727 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 163.1calibrated Vbg = 1.21292 :::*/*/*/*/
[11:34:29.673] <TB3> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 161.7calibrated Vbg = 1.2128 :::*/*/*/*/
[11:34:29.676] <TB3> INFO: ----------------------------------------------------------------------
[11:34:29.676] <TB3> INFO: PixTestReadback::CalibrateIa()
[11:34:29.676] <TB3> INFO: ----------------------------------------------------------------------
[11:37:10.012] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C0.dat
[11:37:10.012] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C1.dat
[11:37:10.012] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C2.dat
[11:37:10.012] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C3.dat
[11:37:10.012] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C4.dat
[11:37:10.012] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C5.dat
[11:37:10.012] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C6.dat
[11:37:10.012] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C7.dat
[11:37:10.013] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C8.dat
[11:37:10.013] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C9.dat
[11:37:10.013] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C10.dat
[11:37:10.013] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C11.dat
[11:37:10.013] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C12.dat
[11:37:10.013] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C13.dat
[11:37:10.013] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C14.dat
[11:37:10.013] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:37:10.039] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[11:37:10.041] <TB3> INFO: PixTestReadback::doTest() done
[11:37:10.041] <TB3> INFO: Decoding statistics:
[11:37:10.041] <TB3> INFO: General information:
[11:37:10.041] <TB3> INFO: 16bit words read: 1536
[11:37:10.041] <TB3> INFO: valid events total: 256
[11:37:10.041] <TB3> INFO: empty events: 256
[11:37:10.041] <TB3> INFO: valid events with pixels: 0
[11:37:10.041] <TB3> INFO: valid pixel hits: 0
[11:37:10.041] <TB3> INFO: Event errors: 0
[11:37:10.041] <TB3> INFO: start marker: 0
[11:37:10.041] <TB3> INFO: stop marker: 0
[11:37:10.041] <TB3> INFO: overflow: 0
[11:37:10.041] <TB3> INFO: invalid 5bit words: 0
[11:37:10.041] <TB3> INFO: invalid XOR eye diagram: 0
[11:37:10.041] <TB3> INFO: frame (failed synchr.): 0
[11:37:10.041] <TB3> INFO: idle data (no TBM trl): 0
[11:37:10.041] <TB3> INFO: no data (only TBM hdr): 0
[11:37:10.041] <TB3> INFO: TBM errors: 0
[11:37:10.041] <TB3> INFO: flawed TBM headers: 0
[11:37:10.041] <TB3> INFO: flawed TBM trailers: 0
[11:37:10.041] <TB3> INFO: event ID mismatches: 0
[11:37:10.041] <TB3> INFO: ROC errors: 0
[11:37:10.041] <TB3> INFO: missing ROC header(s): 0
[11:37:10.041] <TB3> INFO: misplaced readback start: 0
[11:37:10.041] <TB3> INFO: Pixel decoding errors: 0
[11:37:10.041] <TB3> INFO: pixel data incomplete: 0
[11:37:10.041] <TB3> INFO: pixel address: 0
[11:37:10.041] <TB3> INFO: pulse height fill bit: 0
[11:37:10.041] <TB3> INFO: buffer corruption: 0
[11:37:10.103] <TB3> INFO: ######################################################################
[11:37:10.103] <TB3> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:37:10.103] <TB3> INFO: ######################################################################
[11:37:10.107] <TB3> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:37:10.129] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[11:37:10.129] <TB3> INFO: run 1 of 1
[11:37:10.380] <TB3> INFO: Expecting 3120000 events.
[11:37:41.731] <TB3> INFO: 672435 events read in total (30759ms).











[11:38:12.297] <TB3> INFO: 1341480 events read in total (61325ms).











[11:38:42.558] <TB3> INFO: 2007330 events read in total (91586ms).











[11:39:12.951] <TB3> INFO: 2673020 events read in total (121979ms).











[11:39:35.268] <TB3> INFO: 3120000 events read in total (144296ms).
[11:39:35.389] <TB3> INFO: Test took 145261ms.
[11:40:03.819] <TB3> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 173 seconds
[11:40:03.819] <TB3> INFO: number of dead bumps (per ROC): 1 0 1 1 1 0 0 1 1 15 0 0 1 4 12 21
[11:40:03.819] <TB3> INFO: separation cut (per ROC): 102 102 106 103 103 112 120 121 105 107 127 111 98 108 113 106
[11:40:03.819] <TB3> INFO: Decoding statistics:
[11:40:03.819] <TB3> INFO: General information:
[11:40:03.819] <TB3> INFO: 16bit words read: 0
[11:40:03.819] <TB3> INFO: valid events total: 0
[11:40:03.819] <TB3> INFO: empty events: 0
[11:40:03.819] <TB3> INFO: valid events with pixels: 0
[11:40:03.819] <TB3> INFO: valid pixel hits: 0
[11:40:03.819] <TB3> INFO: Event errors: 0
[11:40:03.819] <TB3> INFO: start marker: 0
[11:40:03.819] <TB3> INFO: stop marker: 0
[11:40:03.819] <TB3> INFO: overflow: 0
[11:40:03.819] <TB3> INFO: invalid 5bit words: 0
[11:40:03.819] <TB3> INFO: invalid XOR eye diagram: 0
[11:40:03.819] <TB3> INFO: frame (failed synchr.): 0
[11:40:03.819] <TB3> INFO: idle data (no TBM trl): 0
[11:40:03.819] <TB3> INFO: no data (only TBM hdr): 0
[11:40:03.819] <TB3> INFO: TBM errors: 0
[11:40:03.819] <TB3> INFO: flawed TBM headers: 0
[11:40:03.820] <TB3> INFO: flawed TBM trailers: 0
[11:40:03.820] <TB3> INFO: event ID mismatches: 0
[11:40:03.820] <TB3> INFO: ROC errors: 0
[11:40:03.820] <TB3> INFO: missing ROC header(s): 0
[11:40:03.820] <TB3> INFO: misplaced readback start: 0
[11:40:03.820] <TB3> INFO: Pixel decoding errors: 0
[11:40:03.820] <TB3> INFO: pixel data incomplete: 0
[11:40:03.820] <TB3> INFO: pixel address: 0
[11:40:03.820] <TB3> INFO: pulse height fill bit: 0
[11:40:03.820] <TB3> INFO: buffer corruption: 0
[11:40:03.879] <TB3> INFO: ######################################################################
[11:40:03.879] <TB3> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:40:03.879] <TB3> INFO: ######################################################################
[11:40:03.879] <TB3> INFO: ----------------------------------------------------------------------
[11:40:03.879] <TB3> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:40:03.879] <TB3> INFO: ----------------------------------------------------------------------
[11:40:03.879] <TB3> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[11:40:03.895] <TB3> INFO: dacScan split into 1 runs with ntrig = 50
[11:40:03.895] <TB3> INFO: run 1 of 1
[11:40:04.183] <TB3> INFO: Expecting 36608000 events.
[11:40:29.079] <TB3> INFO: 696850 events read in total (24288ms).
[11:40:53.059] <TB3> INFO: 1379700 events read in total (48268ms).
[11:41:16.773] <TB3> INFO: 2059300 events read in total (71982ms).
[11:41:40.650] <TB3> INFO: 2740700 events read in total (95859ms).
[11:42:04.528] <TB3> INFO: 3420300 events read in total (119738ms).
[11:42:28.458] <TB3> INFO: 4098750 events read in total (143667ms).
[11:42:52.313] <TB3> INFO: 4778150 events read in total (167522ms).
[11:43:16.376] <TB3> INFO: 5458350 events read in total (191585ms).
[11:43:40.472] <TB3> INFO: 6136600 events read in total (215681ms).
[11:44:03.998] <TB3> INFO: 6815700 events read in total (239207ms).
[11:44:27.666] <TB3> INFO: 7492100 events read in total (262875ms).
[11:44:51.554] <TB3> INFO: 8168550 events read in total (286763ms).
[11:45:15.564] <TB3> INFO: 8847300 events read in total (310773ms).
[11:45:38.002] <TB3> INFO: 9526550 events read in total (334211ms).
[11:46:02.927] <TB3> INFO: 10204850 events read in total (358136ms).
[11:46:26.868] <TB3> INFO: 10882000 events read in total (382077ms).
[11:46:50.715] <TB3> INFO: 11558900 events read in total (405924ms).
[11:47:14.374] <TB3> INFO: 12231450 events read in total (429583ms).
[11:47:37.515] <TB3> INFO: 12907300 events read in total (452724ms).
[11:48:01.446] <TB3> INFO: 13583400 events read in total (476655ms).
[11:48:25.029] <TB3> INFO: 14256850 events read in total (500238ms).
[11:48:48.308] <TB3> INFO: 14930900 events read in total (523517ms).
[11:49:11.718] <TB3> INFO: 15605500 events read in total (546927ms).
[11:49:35.708] <TB3> INFO: 16278500 events read in total (570917ms).
[11:49:58.977] <TB3> INFO: 16952200 events read in total (594186ms).
[11:50:22.546] <TB3> INFO: 17625800 events read in total (617755ms).
[11:50:46.844] <TB3> INFO: 18298400 events read in total (642053ms).
[11:51:10.785] <TB3> INFO: 18967350 events read in total (665994ms).
[11:51:34.145] <TB3> INFO: 19635800 events read in total (689354ms).
[11:51:57.799] <TB3> INFO: 20305950 events read in total (713008ms).
[11:52:21.351] <TB3> INFO: 20975850 events read in total (736560ms).
[11:52:44.569] <TB3> INFO: 21643700 events read in total (759778ms).
[11:53:08.539] <TB3> INFO: 22311750 events read in total (783748ms).
[11:53:32.095] <TB3> INFO: 22979750 events read in total (807304ms).
[11:53:55.833] <TB3> INFO: 23647850 events read in total (831042ms).
[11:54:19.539] <TB3> INFO: 24315500 events read in total (854748ms).
[11:54:43.150] <TB3> INFO: 24983050 events read in total (878359ms).
[11:55:06.791] <TB3> INFO: 25651200 events read in total (902000ms).
[11:55:30.016] <TB3> INFO: 26318450 events read in total (925225ms).
[11:55:53.689] <TB3> INFO: 26986150 events read in total (948898ms).
[11:56:17.399] <TB3> INFO: 27654750 events read in total (972608ms).
[11:56:40.876] <TB3> INFO: 28321100 events read in total (996085ms).
[11:57:04.016] <TB3> INFO: 28987100 events read in total (1019225ms).
[11:57:27.180] <TB3> INFO: 29652400 events read in total (1042389ms).
[11:57:50.891] <TB3> INFO: 30316650 events read in total (1066100ms).
[11:58:14.166] <TB3> INFO: 30981500 events read in total (1089375ms).
[11:58:37.592] <TB3> INFO: 31644450 events read in total (1112801ms).
[11:59:00.969] <TB3> INFO: 32307950 events read in total (1136178ms).
[11:59:24.967] <TB3> INFO: 32973750 events read in total (1160176ms).
[11:59:48.680] <TB3> INFO: 33640850 events read in total (1183889ms).
[12:00:12.152] <TB3> INFO: 34309050 events read in total (1207361ms).
[12:00:35.715] <TB3> INFO: 34974750 events read in total (1230924ms).
[12:00:59.343] <TB3> INFO: 35643250 events read in total (1254553ms).
[12:01:25.117] <TB3> INFO: 36320500 events read in total (1280326ms).
[12:01:35.343] <TB3> INFO: 36608000 events read in total (1290552ms).
[12:01:35.512] <TB3> INFO: Test took 1291617ms.
[12:01:36.067] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:01:38.158] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:01:39.724] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:01:41.386] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:01:43.302] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:01:45.304] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:01:47.195] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:01:48.875] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:01:50.484] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:01:52.630] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:01:54.772] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:01:56.617] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:01:58.647] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:02:00.425] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:02:01.985] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:02:03.438] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:02:05.057] <TB3> INFO: PixTestScurves::scurves() done
[12:02:05.058] <TB3> INFO: Vcal mean: 121.33 111.99 122.46 122.50 126.96 129.53 128.70 128.80 116.01 119.13 132.99 124.66 128.16 124.84 122.10 118.77
[12:02:05.058] <TB3> INFO: Vcal RMS: 6.44 4.55 6.07 6.37 7.20 7.08 5.58 6.82 6.29 6.01 6.44 6.55 5.86 6.06 5.66 6.48
[12:02:05.058] <TB3> INFO: PixTestScurves::fullTest() done, duration: 1321 seconds
[12:02:05.058] <TB3> INFO: Decoding statistics:
[12:02:05.058] <TB3> INFO: General information:
[12:02:05.058] <TB3> INFO: 16bit words read: 0
[12:02:05.058] <TB3> INFO: valid events total: 0
[12:02:05.058] <TB3> INFO: empty events: 0
[12:02:05.058] <TB3> INFO: valid events with pixels: 0
[12:02:05.058] <TB3> INFO: valid pixel hits: 0
[12:02:05.058] <TB3> INFO: Event errors: 0
[12:02:05.058] <TB3> INFO: start marker: 0
[12:02:05.058] <TB3> INFO: stop marker: 0
[12:02:05.058] <TB3> INFO: overflow: 0
[12:02:05.058] <TB3> INFO: invalid 5bit words: 0
[12:02:05.058] <TB3> INFO: invalid XOR eye diagram: 0
[12:02:05.058] <TB3> INFO: frame (failed synchr.): 0
[12:02:05.058] <TB3> INFO: idle data (no TBM trl): 0
[12:02:05.058] <TB3> INFO: no data (only TBM hdr): 0
[12:02:05.058] <TB3> INFO: TBM errors: 0
[12:02:05.058] <TB3> INFO: flawed TBM headers: 0
[12:02:05.058] <TB3> INFO: flawed TBM trailers: 0
[12:02:05.058] <TB3> INFO: event ID mismatches: 0
[12:02:05.058] <TB3> INFO: ROC errors: 0
[12:02:05.058] <TB3> INFO: missing ROC header(s): 0
[12:02:05.058] <TB3> INFO: misplaced readback start: 0
[12:02:05.058] <TB3> INFO: Pixel decoding errors: 0
[12:02:05.058] <TB3> INFO: pixel data incomplete: 0
[12:02:05.058] <TB3> INFO: pixel address: 0
[12:02:05.058] <TB3> INFO: pulse height fill bit: 0
[12:02:05.058] <TB3> INFO: buffer corruption: 0
[12:02:05.125] <TB3> INFO: ######################################################################
[12:02:05.125] <TB3> INFO: PixTestTrim::doTest()
[12:02:05.125] <TB3> INFO: ######################################################################
[12:02:05.126] <TB3> INFO: ----------------------------------------------------------------------
[12:02:05.126] <TB3> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:02:05.126] <TB3> INFO: ----------------------------------------------------------------------
[12:02:05.168] <TB3> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:02:05.168] <TB3> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:02:05.182] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:02:05.182] <TB3> INFO: run 1 of 1
[12:02:05.424] <TB3> INFO: Expecting 5025280 events.
[12:02:36.624] <TB3> INFO: 828208 events read in total (30603ms).
[12:03:07.937] <TB3> INFO: 1653296 events read in total (61916ms).
[12:03:38.790] <TB3> INFO: 2475048 events read in total (92769ms).
[12:04:09.494] <TB3> INFO: 3294304 events read in total (123473ms).
[12:04:40.274] <TB3> INFO: 4109816 events read in total (154253ms).
[12:05:12.082] <TB3> INFO: 4924328 events read in total (186061ms).
[12:05:16.271] <TB3> INFO: 5025280 events read in total (190250ms).
[12:05:16.327] <TB3> INFO: Test took 191146ms.
[12:05:36.628] <TB3> INFO: ROC 0 VthrComp = 121
[12:05:36.628] <TB3> INFO: ROC 1 VthrComp = 112
[12:05:36.628] <TB3> INFO: ROC 2 VthrComp = 125
[12:05:36.628] <TB3> INFO: ROC 3 VthrComp = 120
[12:05:36.628] <TB3> INFO: ROC 4 VthrComp = 118
[12:05:36.628] <TB3> INFO: ROC 5 VthrComp = 125
[12:05:36.628] <TB3> INFO: ROC 6 VthrComp = 131
[12:05:36.628] <TB3> INFO: ROC 7 VthrComp = 129
[12:05:36.629] <TB3> INFO: ROC 8 VthrComp = 117
[12:05:36.629] <TB3> INFO: ROC 9 VthrComp = 115
[12:05:36.629] <TB3> INFO: ROC 10 VthrComp = 137
[12:05:36.629] <TB3> INFO: ROC 11 VthrComp = 126
[12:05:36.629] <TB3> INFO: ROC 12 VthrComp = 124
[12:05:36.629] <TB3> INFO: ROC 13 VthrComp = 131
[12:05:36.629] <TB3> INFO: ROC 14 VthrComp = 128
[12:05:36.629] <TB3> INFO: ROC 15 VthrComp = 124
[12:05:36.883] <TB3> INFO: Expecting 41600 events.
[12:05:40.609] <TB3> INFO: 41600 events read in total (3134ms).
[12:05:40.610] <TB3> INFO: Test took 3979ms.
[12:05:40.621] <TB3> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:05:40.621] <TB3> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:05:40.634] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:05:40.634] <TB3> INFO: run 1 of 1
[12:05:40.915] <TB3> INFO: Expecting 5025280 events.
[12:06:08.438] <TB3> INFO: 592560 events read in total (26931ms).
[12:06:34.578] <TB3> INFO: 1183096 events read in total (53071ms).
[12:07:00.824] <TB3> INFO: 1773696 events read in total (79317ms).
[12:07:27.780] <TB3> INFO: 2363176 events read in total (106273ms).
[12:07:54.423] <TB3> INFO: 2950248 events read in total (132916ms).
[12:08:21.533] <TB3> INFO: 3535536 events read in total (160026ms).
[12:08:48.261] <TB3> INFO: 4119576 events read in total (186754ms).
[12:09:15.939] <TB3> INFO: 4703440 events read in total (214432ms).
[12:09:31.461] <TB3> INFO: 5025280 events read in total (229954ms).
[12:09:31.572] <TB3> INFO: Test took 230937ms.
[12:09:57.677] <TB3> INFO: roc 0 with ID = 0 has maximal Vcal 62.2012 for pixel 25/1 mean/min/max = 47.4725/32.6035/62.3415
[12:09:57.677] <TB3> INFO: roc 1 with ID = 1 has maximal Vcal 58.369 for pixel 34/60 mean/min/max = 46.2096/34.0138/58.4054
[12:09:57.677] <TB3> INFO: roc 2 with ID = 2 has maximal Vcal 59.2216 for pixel 9/0 mean/min/max = 46.0957/32.8811/59.3103
[12:09:57.678] <TB3> INFO: roc 3 with ID = 3 has maximal Vcal 60.4968 for pixel 9/28 mean/min/max = 47.4512/34.39/60.5124
[12:09:57.678] <TB3> INFO: roc 4 with ID = 4 has maximal Vcal 63.9477 for pixel 20/5 mean/min/max = 48.2876/32.1712/64.4039
[12:09:57.678] <TB3> INFO: roc 5 with ID = 5 has maximal Vcal 63.428 for pixel 19/79 mean/min/max = 47.9485/31.9877/63.9093
[12:09:57.679] <TB3> INFO: roc 6 with ID = 6 has maximal Vcal 61.0154 for pixel 22/35 mean/min/max = 48.353/35.5926/61.1134
[12:09:57.679] <TB3> INFO: roc 7 with ID = 7 has maximal Vcal 61.1648 for pixel 0/6 mean/min/max = 45.9721/30.7049/61.2392
[12:09:57.679] <TB3> INFO: roc 8 with ID = 8 has maximal Vcal 60.6251 for pixel 8/28 mean/min/max = 46.3832/32.0236/60.7428
[12:09:57.680] <TB3> INFO: roc 9 with ID = 9 has maximal Vcal 63.1375 for pixel 6/2 mean/min/max = 47.7113/31.6796/63.7431
[12:09:57.680] <TB3> INFO: roc 10 with ID = 10 has maximal Vcal 63.0511 for pixel 49/5 mean/min/max = 50.1486/37.0618/63.2355
[12:09:57.681] <TB3> INFO: roc 11 with ID = 11 has maximal Vcal 60.0931 for pixel 5/77 mean/min/max = 45.5699/30.9445/60.1954
[12:09:57.681] <TB3> INFO: roc 12 with ID = 12 has maximal Vcal 60.225 for pixel 13/77 mean/min/max = 47.5783/34.8754/60.2812
[12:09:57.681] <TB3> INFO: roc 13 with ID = 13 has maximal Vcal 58.4024 for pixel 0/36 mean/min/max = 45.0003/31.5682/58.4325
[12:09:57.682] <TB3> INFO: roc 14 with ID = 14 has maximal Vcal 56.7869 for pixel 4/74 mean/min/max = 44.7224/32.3352/57.1096
[12:09:57.682] <TB3> INFO: roc 15 with ID = 15 has maximal Vcal 59.5908 for pixel 11/24 mean/min/max = 46.0014/31.868/60.1347
[12:09:57.682] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:09:57.771] <TB3> INFO: Expecting 411648 events.
[12:10:07.143] <TB3> INFO: 411648 events read in total (8781ms).
[12:10:07.151] <TB3> INFO: Expecting 411648 events.
[12:10:16.320] <TB3> INFO: 411648 events read in total (8766ms).
[12:10:16.333] <TB3> INFO: Expecting 411648 events.
[12:10:25.487] <TB3> INFO: 411648 events read in total (8751ms).
[12:10:25.506] <TB3> INFO: Expecting 411648 events.
[12:10:34.667] <TB3> INFO: 411648 events read in total (8758ms).
[12:10:34.688] <TB3> INFO: Expecting 411648 events.
[12:10:43.854] <TB3> INFO: 411648 events read in total (8763ms).
[12:10:43.874] <TB3> INFO: Expecting 411648 events.
[12:10:53.049] <TB3> INFO: 411648 events read in total (8772ms).
[12:10:53.078] <TB3> INFO: Expecting 411648 events.
[12:11:02.201] <TB3> INFO: 411648 events read in total (8719ms).
[12:11:02.233] <TB3> INFO: Expecting 411648 events.
[12:11:11.450] <TB3> INFO: 411648 events read in total (8812ms).
[12:11:11.494] <TB3> INFO: Expecting 411648 events.
[12:11:20.569] <TB3> INFO: 411648 events read in total (8672ms).
[12:11:20.603] <TB3> INFO: Expecting 411648 events.
[12:11:29.790] <TB3> INFO: 411648 events read in total (8784ms).
[12:11:29.824] <TB3> INFO: Expecting 411648 events.
[12:11:39.078] <TB3> INFO: 411648 events read in total (8847ms).
[12:11:39.125] <TB3> INFO: Expecting 411648 events.
[12:11:48.282] <TB3> INFO: 411648 events read in total (8754ms).
[12:11:48.322] <TB3> INFO: Expecting 411648 events.
[12:11:57.498] <TB3> INFO: 411648 events read in total (8773ms).
[12:11:57.548] <TB3> INFO: Expecting 411648 events.
[12:12:06.710] <TB3> INFO: 411648 events read in total (8759ms).
[12:12:06.763] <TB3> INFO: Expecting 411648 events.
[12:12:15.983] <TB3> INFO: 411648 events read in total (8817ms).
[12:12:16.044] <TB3> INFO: Expecting 411648 events.
[12:12:25.333] <TB3> INFO: 411648 events read in total (8886ms).
[12:12:25.439] <TB3> INFO: Test took 147757ms.
[12:12:26.228] <TB3> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:12:26.243] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:12:26.243] <TB3> INFO: run 1 of 1
[12:12:26.535] <TB3> INFO: Expecting 5025280 events.
[12:12:53.505] <TB3> INFO: 587016 events read in total (26378ms).
[12:13:19.772] <TB3> INFO: 1173840 events read in total (52645ms).
[12:13:46.605] <TB3> INFO: 1759536 events read in total (79479ms).
[12:14:14.016] <TB3> INFO: 2344400 events read in total (106889ms).
[12:14:41.556] <TB3> INFO: 2930440 events read in total (134430ms).
[12:15:08.529] <TB3> INFO: 3517920 events read in total (161402ms).
[12:15:36.214] <TB3> INFO: 4107504 events read in total (189087ms).
[12:16:04.314] <TB3> INFO: 4696592 events read in total (217188ms).
[12:16:20.178] <TB3> INFO: 5025280 events read in total (233051ms).
[12:16:20.377] <TB3> INFO: Test took 234135ms.
[12:16:47.002] <TB3> INFO: ---> TrimStepCorr4 extremal thresholds: 8.001389 .. 145.721589
[12:16:48.279] <TB3> INFO: Expecting 208000 events.
[12:16:58.461] <TB3> INFO: 208000 events read in total (9591ms).
[12:16:58.461] <TB3> INFO: Test took 10457ms.
[12:16:58.510] <TB3> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 8 .. 155 (-1/-1) hits flags = 528 (plus default)
[12:16:58.525] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:16:58.525] <TB3> INFO: run 1 of 1
[12:16:58.803] <TB3> INFO: Expecting 4925440 events.
[12:17:25.628] <TB3> INFO: 575232 events read in total (26233ms).
[12:17:52.670] <TB3> INFO: 1150760 events read in total (53275ms).
[12:18:18.780] <TB3> INFO: 1725816 events read in total (79386ms).
[12:18:44.789] <TB3> INFO: 2301264 events read in total (105394ms).
[12:19:11.173] <TB3> INFO: 2876216 events read in total (131778ms).
[12:19:37.428] <TB3> INFO: 3450944 events read in total (158033ms).
[12:20:04.482] <TB3> INFO: 4025112 events read in total (185087ms).
[12:20:31.102] <TB3> INFO: 4598512 events read in total (211707ms).
[12:20:47.531] <TB3> INFO: 4925440 events read in total (228136ms).
[12:20:47.714] <TB3> INFO: Test took 229190ms.
[12:21:17.461] <TB3> INFO: ---> TrimStepCorr2 extremal thresholds: 26.804247 .. 47.035531
[12:21:17.713] <TB3> INFO: Expecting 208000 events.
[12:21:27.961] <TB3> INFO: 208000 events read in total (9656ms).
[12:21:27.962] <TB3> INFO: Test took 10499ms.
[12:21:28.012] <TB3> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[12:21:28.025] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:21:28.025] <TB3> INFO: run 1 of 1
[12:21:28.305] <TB3> INFO: Expecting 1397760 events.
[12:21:56.822] <TB3> INFO: 656296 events read in total (27925ms).
[12:22:25.000] <TB3> INFO: 1311344 events read in total (57104ms).
[12:22:30.058] <TB3> INFO: 1397760 events read in total (61162ms).
[12:22:30.094] <TB3> INFO: Test took 62069ms.
[12:22:46.182] <TB3> INFO: ---> TrimStepCorr1a extremal thresholds: 27.270774 .. 48.711027
[12:22:46.420] <TB3> INFO: Expecting 208000 events.
[12:22:56.566] <TB3> INFO: 208000 events read in total (9554ms).
[12:22:56.567] <TB3> INFO: Test took 10384ms.
[12:22:56.631] <TB3> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 58 (-1/-1) hits flags = 528 (plus default)
[12:22:56.646] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:22:56.646] <TB3> INFO: run 1 of 1
[12:22:56.942] <TB3> INFO: Expecting 1397760 events.
[12:23:25.847] <TB3> INFO: 649120 events read in total (28313ms).
[12:23:55.286] <TB3> INFO: 1297280 events read in total (57752ms).
[12:23:59.960] <TB3> INFO: 1397760 events read in total (62426ms).
[12:24:00.005] <TB3> INFO: Test took 63359ms.
[12:24:15.023] <TB3> INFO: ---> TrimStepCorr1b extremal thresholds: 25.108458 .. 46.879788
[12:24:15.268] <TB3> INFO: Expecting 208000 events.
[12:24:25.568] <TB3> INFO: 208000 events read in total (9707ms).
[12:24:25.569] <TB3> INFO: Test took 10544ms.
[12:24:25.622] <TB3> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 56 (-1/-1) hits flags = 528 (plus default)
[12:24:25.637] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:24:25.637] <TB3> INFO: run 1 of 1
[12:24:25.949] <TB3> INFO: Expecting 1397760 events.
[12:24:55.076] <TB3> INFO: 664024 events read in total (28535ms).
[12:25:25.738] <TB3> INFO: 1327832 events read in total (59198ms).
[12:25:29.170] <TB3> INFO: 1397760 events read in total (62629ms).
[12:25:29.200] <TB3> INFO: Test took 63564ms.
[12:25:41.997] <TB3> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:25:41.997] <TB3> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:25:42.011] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:25:42.011] <TB3> INFO: run 1 of 1
[12:25:42.286] <TB3> INFO: Expecting 1364480 events.
[12:26:12.434] <TB3> INFO: 668448 events read in total (29556ms).
[12:26:42.051] <TB3> INFO: 1336168 events read in total (59173ms).
[12:26:43.676] <TB3> INFO: 1364480 events read in total (60799ms).
[12:26:43.717] <TB3> INFO: Test took 61706ms.
[12:26:57.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C0.dat
[12:26:57.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C1.dat
[12:26:57.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C2.dat
[12:26:57.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C3.dat
[12:26:57.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C4.dat
[12:26:57.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C5.dat
[12:26:57.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C6.dat
[12:26:57.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C7.dat
[12:26:57.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C8.dat
[12:26:57.547] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C9.dat
[12:26:57.548] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C10.dat
[12:26:57.548] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C11.dat
[12:26:57.548] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C12.dat
[12:26:57.549] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C13.dat
[12:26:57.549] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C14.dat
[12:26:57.549] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C15.dat
[12:26:57.550] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C0.dat
[12:26:57.557] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C1.dat
[12:26:57.564] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C2.dat
[12:26:57.572] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C3.dat
[12:26:57.579] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C4.dat
[12:26:57.587] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C5.dat
[12:26:57.594] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C6.dat
[12:26:57.602] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C7.dat
[12:26:57.609] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C8.dat
[12:26:57.616] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C9.dat
[12:26:57.624] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C10.dat
[12:26:57.631] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C11.dat
[12:26:57.639] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C12.dat
[12:26:57.646] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C13.dat
[12:26:57.653] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C14.dat
[12:26:57.661] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C15.dat
[12:26:57.668] <TB3> INFO: PixTestTrim::trimTest() done
[12:26:57.668] <TB3> INFO: vtrim: 148 128 120 118 139 140 134 127 127 141 152 128 121 117 116 128
[12:26:57.668] <TB3> INFO: vthrcomp: 121 112 125 120 118 125 131 129 117 115 137 126 124 131 128 124
[12:26:57.668] <TB3> INFO: vcal mean: 35.28 35.01 34.93 35.06 35.54 35.21 35.23 34.95 34.99 35.01 35.06 34.89 35.16 34.94 34.96 34.94
[12:26:57.668] <TB3> INFO: vcal RMS: 1.38 1.00 1.07 1.27 1.98 1.27 1.31 1.08 1.10 1.08 1.18 1.14 1.33 1.04 1.01 1.17
[12:26:57.668] <TB3> INFO: bits mean: 9.65 9.34 9.20 8.80 9.80 9.09 8.51 9.32 9.14 9.33 8.01 9.67 8.71 9.58 9.43 9.44
[12:26:57.668] <TB3> INFO: bits RMS: 2.58 2.52 2.77 2.65 2.58 2.86 2.53 2.99 2.81 2.74 2.26 2.77 2.72 2.85 2.81 2.75
[12:26:57.677] <TB3> INFO: ----------------------------------------------------------------------
[12:26:57.677] <TB3> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:26:57.677] <TB3> INFO: ----------------------------------------------------------------------
[12:26:57.680] <TB3> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:26:57.695] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[12:26:57.695] <TB3> INFO: run 1 of 1
[12:26:57.986] <TB3> INFO: Expecting 4160000 events.
[12:27:31.272] <TB3> INFO: 768980 events read in total (32696ms).
[12:28:03.127] <TB3> INFO: 1531395 events read in total (64550ms).
[12:28:35.260] <TB3> INFO: 2287465 events read in total (96683ms).
[12:29:07.535] <TB3> INFO: 3038625 events read in total (128958ms).
[12:29:40.243] <TB3> INFO: 3786805 events read in total (161666ms).
[12:29:57.577] <TB3> INFO: 4160000 events read in total (179000ms).
[12:29:57.657] <TB3> INFO: Test took 179962ms.
[12:30:28.714] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[12:30:28.727] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[12:30:28.727] <TB3> INFO: run 1 of 1
[12:30:28.964] <TB3> INFO: Expecting 4305600 events.
[12:31:01.087] <TB3> INFO: 735080 events read in total (31531ms).
[12:31:32.840] <TB3> INFO: 1464955 events read in total (63284ms).
[12:32:04.009] <TB3> INFO: 2191130 events read in total (94453ms).
[12:32:35.318] <TB3> INFO: 2912390 events read in total (125762ms).
[12:33:07.617] <TB3> INFO: 3631070 events read in total (158061ms).
[12:33:38.455] <TB3> INFO: 4305600 events read in total (188899ms).
[12:33:38.533] <TB3> INFO: Test took 189805ms.
[12:34:11.884] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[12:34:11.898] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[12:34:11.898] <TB3> INFO: run 1 of 1
[12:34:12.135] <TB3> INFO: Expecting 4097600 events.
[12:34:45.596] <TB3> INFO: 750275 events read in total (32869ms).
[12:35:18.203] <TB3> INFO: 1494970 events read in total (65476ms).
[12:35:50.506] <TB3> INFO: 2234275 events read in total (97779ms).
[12:36:22.695] <TB3> INFO: 2968870 events read in total (129968ms).
[12:36:54.967] <TB3> INFO: 3700475 events read in total (162240ms).
[12:37:13.792] <TB3> INFO: 4097600 events read in total (181065ms).
[12:37:13.879] <TB3> INFO: Test took 181981ms.
[12:37:45.914] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[12:37:45.929] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[12:37:45.929] <TB3> INFO: run 1 of 1
[12:37:46.177] <TB3> INFO: Expecting 4097600 events.
[12:38:18.981] <TB3> INFO: 750505 events read in total (32212ms).
[12:38:51.659] <TB3> INFO: 1495305 events read in total (64890ms).
[12:39:23.507] <TB3> INFO: 2234900 events read in total (96738ms).
[12:39:55.074] <TB3> INFO: 2969840 events read in total (128305ms).
[12:40:27.004] <TB3> INFO: 3701605 events read in total (160236ms).
[12:40:44.608] <TB3> INFO: 4097600 events read in total (177839ms).
[12:40:44.680] <TB3> INFO: Test took 178751ms.
[12:41:19.720] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[12:41:19.735] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[12:41:19.735] <TB3> INFO: run 1 of 1
[12:41:20.066] <TB3> INFO: Expecting 4139200 events.
[12:41:53.579] <TB3> INFO: 747720 events read in total (32921ms).
[12:42:25.512] <TB3> INFO: 1489485 events read in total (64854ms).
[12:42:57.923] <TB3> INFO: 2226700 events read in total (97265ms).
[12:43:30.510] <TB3> INFO: 2959160 events read in total (129852ms).
[12:44:02.050] <TB3> INFO: 3688135 events read in total (161392ms).
[12:44:22.756] <TB3> INFO: 4139200 events read in total (182098ms).
[12:44:22.836] <TB3> INFO: Test took 183101ms.
[12:44:54.694] <TB3> INFO: PixTestTrim::trimBitTest() done
[12:44:54.695] <TB3> INFO: PixTestTrim::doTest() done, duration: 2569 seconds
[12:44:54.695] <TB3> INFO: Decoding statistics:
[12:44:54.695] <TB3> INFO: General information:
[12:44:54.695] <TB3> INFO: 16bit words read: 0
[12:44:54.695] <TB3> INFO: valid events total: 0
[12:44:54.695] <TB3> INFO: empty events: 0
[12:44:54.695] <TB3> INFO: valid events with pixels: 0
[12:44:54.695] <TB3> INFO: valid pixel hits: 0
[12:44:54.695] <TB3> INFO: Event errors: 0
[12:44:54.695] <TB3> INFO: start marker: 0
[12:44:54.695] <TB3> INFO: stop marker: 0
[12:44:54.695] <TB3> INFO: overflow: 0
[12:44:54.695] <TB3> INFO: invalid 5bit words: 0
[12:44:54.695] <TB3> INFO: invalid XOR eye diagram: 0
[12:44:54.695] <TB3> INFO: frame (failed synchr.): 0
[12:44:54.695] <TB3> INFO: idle data (no TBM trl): 0
[12:44:54.695] <TB3> INFO: no data (only TBM hdr): 0
[12:44:54.695] <TB3> INFO: TBM errors: 0
[12:44:54.695] <TB3> INFO: flawed TBM headers: 0
[12:44:54.695] <TB3> INFO: flawed TBM trailers: 0
[12:44:54.695] <TB3> INFO: event ID mismatches: 0
[12:44:54.695] <TB3> INFO: ROC errors: 0
[12:44:54.695] <TB3> INFO: missing ROC header(s): 0
[12:44:54.695] <TB3> INFO: misplaced readback start: 0
[12:44:54.696] <TB3> INFO: Pixel decoding errors: 0
[12:44:54.696] <TB3> INFO: pixel data incomplete: 0
[12:44:54.696] <TB3> INFO: pixel address: 0
[12:44:54.696] <TB3> INFO: pulse height fill bit: 0
[12:44:54.696] <TB3> INFO: buffer corruption: 0
[12:44:55.527] <TB3> INFO: ######################################################################
[12:44:55.527] <TB3> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:44:55.527] <TB3> INFO: ######################################################################
[12:44:55.841] <TB3> INFO: Expecting 41600 events.
[12:44:59.308] <TB3> INFO: 41600 events read in total (2875ms).
[12:44:59.309] <TB3> INFO: Test took 3779ms.
[12:44:59.829] <TB3> INFO: Expecting 41600 events.
[12:45:03.528] <TB3> INFO: 41600 events read in total (3101ms).
[12:45:03.530] <TB3> INFO: Test took 4015ms.
[12:45:03.820] <TB3> INFO: Expecting 41600 events.
[12:45:07.481] <TB3> INFO: 41600 events read in total (3070ms).
[12:45:07.483] <TB3> INFO: Test took 3928ms.
[12:45:07.838] <TB3> INFO: Expecting 41600 events.
[12:45:11.504] <TB3> INFO: 41600 events read in total (3074ms).
[12:45:11.505] <TB3> INFO: Test took 3993ms.
[12:45:11.842] <TB3> INFO: Expecting 41600 events.
[12:45:15.662] <TB3> INFO: 41600 events read in total (3228ms).
[12:45:15.663] <TB3> INFO: Test took 4131ms.
[12:45:15.954] <TB3> INFO: Expecting 41600 events.
[12:45:19.643] <TB3> INFO: 41600 events read in total (3098ms).
[12:45:19.644] <TB3> INFO: Test took 3956ms.
[12:45:20.017] <TB3> INFO: Expecting 41600 events.
[12:45:23.817] <TB3> INFO: 41600 events read in total (3208ms).
[12:45:23.818] <TB3> INFO: Test took 4144ms.
[12:45:24.131] <TB3> INFO: Expecting 41600 events.
[12:45:27.787] <TB3> INFO: 41600 events read in total (3059ms).
[12:45:27.789] <TB3> INFO: Test took 3944ms.
[12:45:28.105] <TB3> INFO: Expecting 41600 events.
[12:45:31.727] <TB3> INFO: 41600 events read in total (3030ms).
[12:45:31.729] <TB3> INFO: Test took 3911ms.
[12:45:32.021] <TB3> INFO: Expecting 41600 events.
[12:45:35.571] <TB3> INFO: 41600 events read in total (2958ms).
[12:45:35.572] <TB3> INFO: Test took 3816ms.
[12:45:35.862] <TB3> INFO: Expecting 41600 events.
[12:45:39.411] <TB3> INFO: 41600 events read in total (2957ms).
[12:45:39.412] <TB3> INFO: Test took 3815ms.
[12:45:39.708] <TB3> INFO: Expecting 41600 events.
[12:45:43.255] <TB3> INFO: 41600 events read in total (2955ms).
[12:45:43.256] <TB3> INFO: Test took 3820ms.
[12:45:43.606] <TB3> INFO: Expecting 41600 events.
[12:45:47.104] <TB3> INFO: 41600 events read in total (2906ms).
[12:45:47.106] <TB3> INFO: Test took 3826ms.
[12:45:47.397] <TB3> INFO: Expecting 41600 events.
[12:45:50.897] <TB3> INFO: 41600 events read in total (2909ms).
[12:45:50.899] <TB3> INFO: Test took 3768ms.
[12:45:51.197] <TB3> INFO: Expecting 41600 events.
[12:45:54.819] <TB3> INFO: 41600 events read in total (3031ms).
[12:45:54.820] <TB3> INFO: Test took 3896ms.
[12:45:55.112] <TB3> INFO: Expecting 41600 events.
[12:45:58.679] <TB3> INFO: 41600 events read in total (2975ms).
[12:45:58.680] <TB3> INFO: Test took 3833ms.
[12:45:58.970] <TB3> INFO: Expecting 41600 events.
[12:46:02.458] <TB3> INFO: 41600 events read in total (2896ms).
[12:46:02.460] <TB3> INFO: Test took 3755ms.
[12:46:02.751] <TB3> INFO: Expecting 41600 events.
[12:46:06.236] <TB3> INFO: 41600 events read in total (2893ms).
[12:46:06.238] <TB3> INFO: Test took 3752ms.
[12:46:06.530] <TB3> INFO: Expecting 41600 events.
[12:46:10.138] <TB3> INFO: 41600 events read in total (3016ms).
[12:46:10.139] <TB3> INFO: Test took 3874ms.
[12:46:10.453] <TB3> INFO: Expecting 41600 events.
[12:46:14.008] <TB3> INFO: 41600 events read in total (2963ms).
[12:46:14.009] <TB3> INFO: Test took 3838ms.
[12:46:14.298] <TB3> INFO: Expecting 41600 events.
[12:46:17.960] <TB3> INFO: 41600 events read in total (3070ms).
[12:46:17.961] <TB3> INFO: Test took 3927ms.
[12:46:18.254] <TB3> INFO: Expecting 41600 events.
[12:46:21.860] <TB3> INFO: 41600 events read in total (3014ms).
[12:46:21.861] <TB3> INFO: Test took 3876ms.
[12:46:22.152] <TB3> INFO: Expecting 41600 events.
[12:46:25.658] <TB3> INFO: 41600 events read in total (2910ms).
[12:46:25.660] <TB3> INFO: Test took 3772ms.
[12:46:25.952] <TB3> INFO: Expecting 41600 events.
[12:46:29.463] <TB3> INFO: 41600 events read in total (2919ms).
[12:46:29.464] <TB3> INFO: Test took 3777ms.
[12:46:29.753] <TB3> INFO: Expecting 41600 events.
[12:46:33.267] <TB3> INFO: 41600 events read in total (2922ms).
[12:46:33.268] <TB3> INFO: Test took 3780ms.
[12:46:33.589] <TB3> INFO: Expecting 41600 events.
[12:46:37.244] <TB3> INFO: 41600 events read in total (3064ms).
[12:46:37.245] <TB3> INFO: Test took 3949ms.
[12:46:37.535] <TB3> INFO: Expecting 41600 events.
[12:46:41.052] <TB3> INFO: 41600 events read in total (2925ms).
[12:46:41.053] <TB3> INFO: Test took 3783ms.
[12:46:41.353] <TB3> INFO: Expecting 41600 events.
[12:46:44.854] <TB3> INFO: 41600 events read in total (2910ms).
[12:46:44.854] <TB3> INFO: Test took 3774ms.
[12:46:45.151] <TB3> INFO: Expecting 41600 events.
[12:46:48.663] <TB3> INFO: 41600 events read in total (2920ms).
[12:46:48.664] <TB3> INFO: Test took 3778ms.
[12:46:48.954] <TB3> INFO: Expecting 2560 events.
[12:46:49.839] <TB3> INFO: 2560 events read in total (293ms).
[12:46:49.839] <TB3> INFO: Test took 1162ms.
[12:46:50.147] <TB3> INFO: Expecting 2560 events.
[12:46:51.030] <TB3> INFO: 2560 events read in total (291ms).
[12:46:51.031] <TB3> INFO: Test took 1191ms.
[12:46:51.338] <TB3> INFO: Expecting 2560 events.
[12:46:52.225] <TB3> INFO: 2560 events read in total (295ms).
[12:46:52.225] <TB3> INFO: Test took 1194ms.
[12:46:52.532] <TB3> INFO: Expecting 2560 events.
[12:46:53.418] <TB3> INFO: 2560 events read in total (294ms).
[12:46:53.418] <TB3> INFO: Test took 1192ms.
[12:46:53.725] <TB3> INFO: Expecting 2560 events.
[12:46:54.606] <TB3> INFO: 2560 events read in total (289ms).
[12:46:54.606] <TB3> INFO: Test took 1186ms.
[12:46:54.914] <TB3> INFO: Expecting 2560 events.
[12:46:55.796] <TB3> INFO: 2560 events read in total (290ms).
[12:46:55.796] <TB3> INFO: Test took 1189ms.
[12:46:56.104] <TB3> INFO: Expecting 2560 events.
[12:46:56.983] <TB3> INFO: 2560 events read in total (287ms).
[12:46:56.983] <TB3> INFO: Test took 1187ms.
[12:46:57.291] <TB3> INFO: Expecting 2560 events.
[12:46:58.179] <TB3> INFO: 2560 events read in total (296ms).
[12:46:58.179] <TB3> INFO: Test took 1196ms.
[12:46:58.488] <TB3> INFO: Expecting 2560 events.
[12:46:59.369] <TB3> INFO: 2560 events read in total (289ms).
[12:46:59.369] <TB3> INFO: Test took 1190ms.
[12:46:59.677] <TB3> INFO: Expecting 2560 events.
[12:47:00.556] <TB3> INFO: 2560 events read in total (288ms).
[12:47:00.557] <TB3> INFO: Test took 1187ms.
[12:47:00.864] <TB3> INFO: Expecting 2560 events.
[12:47:01.745] <TB3> INFO: 2560 events read in total (289ms).
[12:47:01.745] <TB3> INFO: Test took 1188ms.
[12:47:02.053] <TB3> INFO: Expecting 2560 events.
[12:47:02.932] <TB3> INFO: 2560 events read in total (287ms).
[12:47:02.933] <TB3> INFO: Test took 1188ms.
[12:47:03.240] <TB3> INFO: Expecting 2560 events.
[12:47:04.124] <TB3> INFO: 2560 events read in total (292ms).
[12:47:04.124] <TB3> INFO: Test took 1191ms.
[12:47:04.431] <TB3> INFO: Expecting 2560 events.
[12:47:05.316] <TB3> INFO: 2560 events read in total (293ms).
[12:47:05.317] <TB3> INFO: Test took 1193ms.
[12:47:05.624] <TB3> INFO: Expecting 2560 events.
[12:47:06.516] <TB3> INFO: 2560 events read in total (300ms).
[12:47:06.517] <TB3> INFO: Test took 1200ms.
[12:47:06.825] <TB3> INFO: Expecting 2560 events.
[12:47:07.709] <TB3> INFO: 2560 events read in total (293ms).
[12:47:07.709] <TB3> INFO: Test took 1192ms.
[12:47:07.712] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:08.018] <TB3> INFO: Expecting 655360 events.
[12:47:22.684] <TB3> INFO: 655360 events read in total (14075ms).
[12:47:22.701] <TB3> INFO: Expecting 655360 events.
[12:47:37.055] <TB3> INFO: 655360 events read in total (13951ms).
[12:47:37.078] <TB3> INFO: Expecting 655360 events.
[12:47:51.299] <TB3> INFO: 655360 events read in total (13818ms).
[12:47:51.327] <TB3> INFO: Expecting 655360 events.
[12:48:05.624] <TB3> INFO: 655360 events read in total (13894ms).
[12:48:05.650] <TB3> INFO: Expecting 655360 events.
[12:48:20.080] <TB3> INFO: 655360 events read in total (14028ms).
[12:48:20.114] <TB3> INFO: Expecting 655360 events.
[12:48:34.449] <TB3> INFO: 655360 events read in total (13933ms).
[12:48:34.489] <TB3> INFO: Expecting 655360 events.
[12:48:48.717] <TB3> INFO: 655360 events read in total (13825ms).
[12:48:48.756] <TB3> INFO: Expecting 655360 events.
[12:49:02.951] <TB3> INFO: 655360 events read in total (13792ms).
[12:49:02.995] <TB3> INFO: Expecting 655360 events.
[12:49:17.394] <TB3> INFO: 655360 events read in total (13996ms).
[12:49:17.441] <TB3> INFO: Expecting 655360 events.
[12:49:31.666] <TB3> INFO: 655360 events read in total (13822ms).
[12:49:31.718] <TB3> INFO: Expecting 655360 events.
[12:49:46.007] <TB3> INFO: 655360 events read in total (13886ms).
[12:49:46.072] <TB3> INFO: Expecting 655360 events.
[12:50:00.420] <TB3> INFO: 655360 events read in total (13945ms).
[12:50:00.507] <TB3> INFO: Expecting 655360 events.
[12:50:14.686] <TB3> INFO: 655360 events read in total (13776ms).
[12:50:14.875] <TB3> INFO: Expecting 655360 events.
[12:50:29.197] <TB3> INFO: 655360 events read in total (13919ms).
[12:50:29.293] <TB3> INFO: Expecting 655360 events.
[12:50:43.733] <TB3> INFO: 655360 events read in total (14037ms).
[12:50:43.855] <TB3> INFO: Expecting 655360 events.
[12:50:58.203] <TB3> INFO: 655360 events read in total (13945ms).
[12:50:58.287] <TB3> INFO: Test took 230575ms.
[12:50:58.382] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:50:58.641] <TB3> INFO: Expecting 655360 events.
[12:51:12.825] <TB3> INFO: 655360 events read in total (13592ms).
[12:51:12.840] <TB3> INFO: Expecting 655360 events.
[12:51:27.053] <TB3> INFO: 655360 events read in total (13810ms).
[12:51:27.074] <TB3> INFO: Expecting 655360 events.
[12:51:41.300] <TB3> INFO: 655360 events read in total (13823ms).
[12:51:41.325] <TB3> INFO: Expecting 655360 events.
[12:51:55.796] <TB3> INFO: 655360 events read in total (14068ms).
[12:51:55.822] <TB3> INFO: Expecting 655360 events.
[12:52:10.045] <TB3> INFO: 655360 events read in total (13820ms).
[12:52:10.077] <TB3> INFO: Expecting 655360 events.
[12:52:24.294] <TB3> INFO: 655360 events read in total (13800ms).
[12:52:24.337] <TB3> INFO: Expecting 655360 events.
[12:52:38.729] <TB3> INFO: 655360 events read in total (13989ms).
[12:52:38.771] <TB3> INFO: Expecting 655360 events.
[12:52:53.179] <TB3> INFO: 655360 events read in total (14004ms).
[12:52:53.223] <TB3> INFO: Expecting 655360 events.
[12:53:07.500] <TB3> INFO: 655360 events read in total (13874ms).
[12:53:07.548] <TB3> INFO: Expecting 655360 events.
[12:53:21.772] <TB3> INFO: 655360 events read in total (13819ms).
[12:53:21.829] <TB3> INFO: Expecting 655360 events.
[12:53:35.855] <TB3> INFO: 655360 events read in total (13616ms).
[12:53:35.922] <TB3> INFO: Expecting 655360 events.
[12:53:49.944] <TB3> INFO: 655360 events read in total (13619ms).
[12:53:50.009] <TB3> INFO: Expecting 655360 events.
[12:54:04.076] <TB3> INFO: 655360 events read in total (13664ms).
[12:54:04.188] <TB3> INFO: Expecting 655360 events.
[12:54:18.463] <TB3> INFO: 655360 events read in total (13872ms).
[12:54:18.557] <TB3> INFO: Expecting 655360 events.
[12:54:32.864] <TB3> INFO: 655360 events read in total (13904ms).
[12:54:32.965] <TB3> INFO: Expecting 655360 events.
[12:54:47.100] <TB3> INFO: 655360 events read in total (13732ms).
[12:54:47.238] <TB3> INFO: Test took 228856ms.
[12:54:47.457] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.463] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.469] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.475] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[12:54:47.481] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.487] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.493] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.498] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.504] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[12:54:47.510] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[12:54:47.517] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[12:54:47.527] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.535] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.543] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.549] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[12:54:47.555] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[12:54:47.560] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[12:54:47.566] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[12:54:47.571] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[12:54:47.577] <TB3> INFO: safety margin for low PH: adding 6, margin is now 26
[12:54:47.582] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.588] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.594] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[12:54:47.600] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.605] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[12:54:47.611] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[12:54:47.617] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[12:54:47.623] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[12:54:47.629] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[12:54:47.635] <TB3> INFO: safety margin for low PH: adding 6, margin is now 26
[12:54:47.641] <TB3> INFO: safety margin for low PH: adding 7, margin is now 27
[12:54:47.647] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.653] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.658] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[12:54:47.664] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[12:54:47.670] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[12:54:47.675] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:47.681] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[12:54:47.714] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C0.dat
[12:54:47.714] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C1.dat
[12:54:47.714] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C2.dat
[12:54:47.715] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C3.dat
[12:54:47.715] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C4.dat
[12:54:47.715] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C5.dat
[12:54:47.715] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C6.dat
[12:54:47.715] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C7.dat
[12:54:47.715] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C8.dat
[12:54:47.715] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C9.dat
[12:54:47.715] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C10.dat
[12:54:47.715] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C11.dat
[12:54:47.716] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C12.dat
[12:54:47.716] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C13.dat
[12:54:47.716] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C14.dat
[12:54:47.716] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C15.dat
[12:54:47.956] <TB3> INFO: Expecting 41600 events.
[12:54:51.050] <TB3> INFO: 41600 events read in total (2503ms).
[12:54:51.051] <TB3> INFO: Test took 3332ms.
[12:54:51.551] <TB3> INFO: Expecting 41600 events.
[12:54:54.594] <TB3> INFO: 41600 events read in total (2451ms).
[12:54:54.595] <TB3> INFO: Test took 3334ms.
[12:54:55.049] <TB3> INFO: Expecting 41600 events.
[12:54:58.141] <TB3> INFO: 41600 events read in total (2501ms).
[12:54:58.141] <TB3> INFO: Test took 3333ms.
[12:54:58.357] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:58.446] <TB3> INFO: Expecting 2560 events.
[12:54:59.331] <TB3> INFO: 2560 events read in total (293ms).
[12:54:59.331] <TB3> INFO: Test took 974ms.
[12:54:59.335] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:59.640] <TB3> INFO: Expecting 2560 events.
[12:55:00.524] <TB3> INFO: 2560 events read in total (292ms).
[12:55:00.524] <TB3> INFO: Test took 1189ms.
[12:55:00.527] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:00.832] <TB3> INFO: Expecting 2560 events.
[12:55:01.715] <TB3> INFO: 2560 events read in total (291ms).
[12:55:01.716] <TB3> INFO: Test took 1189ms.
[12:55:01.718] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:02.024] <TB3> INFO: Expecting 2560 events.
[12:55:02.910] <TB3> INFO: 2560 events read in total (294ms).
[12:55:02.911] <TB3> INFO: Test took 1193ms.
[12:55:02.913] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:03.220] <TB3> INFO: Expecting 2560 events.
[12:55:04.104] <TB3> INFO: 2560 events read in total (293ms).
[12:55:04.105] <TB3> INFO: Test took 1192ms.
[12:55:04.107] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:04.415] <TB3> INFO: Expecting 2560 events.
[12:55:05.300] <TB3> INFO: 2560 events read in total (294ms).
[12:55:05.300] <TB3> INFO: Test took 1193ms.
[12:55:05.305] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:05.608] <TB3> INFO: Expecting 2560 events.
[12:55:06.492] <TB3> INFO: 2560 events read in total (292ms).
[12:55:06.493] <TB3> INFO: Test took 1188ms.
[12:55:06.495] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:06.801] <TB3> INFO: Expecting 2560 events.
[12:55:07.685] <TB3> INFO: 2560 events read in total (292ms).
[12:55:07.685] <TB3> INFO: Test took 1190ms.
[12:55:07.687] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:07.993] <TB3> INFO: Expecting 2560 events.
[12:55:08.870] <TB3> INFO: 2560 events read in total (285ms).
[12:55:08.871] <TB3> INFO: Test took 1184ms.
[12:55:08.873] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:09.179] <TB3> INFO: Expecting 2560 events.
[12:55:10.058] <TB3> INFO: 2560 events read in total (287ms).
[12:55:10.058] <TB3> INFO: Test took 1186ms.
[12:55:10.060] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:10.367] <TB3> INFO: Expecting 2560 events.
[12:55:11.246] <TB3> INFO: 2560 events read in total (288ms).
[12:55:11.246] <TB3> INFO: Test took 1186ms.
[12:55:11.249] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:11.556] <TB3> INFO: Expecting 2560 events.
[12:55:12.435] <TB3> INFO: 2560 events read in total (287ms).
[12:55:12.436] <TB3> INFO: Test took 1188ms.
[12:55:12.438] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:12.744] <TB3> INFO: Expecting 2560 events.
[12:55:13.623] <TB3> INFO: 2560 events read in total (287ms).
[12:55:13.623] <TB3> INFO: Test took 1185ms.
[12:55:13.627] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:13.932] <TB3> INFO: Expecting 2560 events.
[12:55:14.811] <TB3> INFO: 2560 events read in total (287ms).
[12:55:14.811] <TB3> INFO: Test took 1184ms.
[12:55:14.813] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:15.120] <TB3> INFO: Expecting 2560 events.
[12:55:15.999] <TB3> INFO: 2560 events read in total (287ms).
[12:55:15.999] <TB3> INFO: Test took 1186ms.
[12:55:15.002] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:16.308] <TB3> INFO: Expecting 2560 events.
[12:55:17.190] <TB3> INFO: 2560 events read in total (291ms).
[12:55:17.190] <TB3> INFO: Test took 1188ms.
[12:55:17.192] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:17.498] <TB3> INFO: Expecting 2560 events.
[12:55:18.376] <TB3> INFO: 2560 events read in total (286ms).
[12:55:18.376] <TB3> INFO: Test took 1184ms.
[12:55:18.378] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:18.685] <TB3> INFO: Expecting 2560 events.
[12:55:19.568] <TB3> INFO: 2560 events read in total (291ms).
[12:55:19.568] <TB3> INFO: Test took 1190ms.
[12:55:19.570] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:19.877] <TB3> INFO: Expecting 2560 events.
[12:55:20.757] <TB3> INFO: 2560 events read in total (289ms).
[12:55:20.757] <TB3> INFO: Test took 1187ms.
[12:55:20.759] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:21.065] <TB3> INFO: Expecting 2560 events.
[12:55:21.945] <TB3> INFO: 2560 events read in total (288ms).
[12:55:21.946] <TB3> INFO: Test took 1187ms.
[12:55:21.949] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:22.254] <TB3> INFO: Expecting 2560 events.
[12:55:23.136] <TB3> INFO: 2560 events read in total (291ms).
[12:55:23.136] <TB3> INFO: Test took 1187ms.
[12:55:23.141] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:23.444] <TB3> INFO: Expecting 2560 events.
[12:55:24.326] <TB3> INFO: 2560 events read in total (291ms).
[12:55:24.326] <TB3> INFO: Test took 1185ms.
[12:55:24.328] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:24.634] <TB3> INFO: Expecting 2560 events.
[12:55:25.514] <TB3> INFO: 2560 events read in total (288ms).
[12:55:25.514] <TB3> INFO: Test took 1186ms.
[12:55:25.516] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:25.823] <TB3> INFO: Expecting 2560 events.
[12:55:26.702] <TB3> INFO: 2560 events read in total (288ms).
[12:55:26.702] <TB3> INFO: Test took 1186ms.
[12:55:26.705] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:27.011] <TB3> INFO: Expecting 2560 events.
[12:55:27.896] <TB3> INFO: 2560 events read in total (293ms).
[12:55:27.897] <TB3> INFO: Test took 1193ms.
[12:55:27.899] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:28.205] <TB3> INFO: Expecting 2560 events.
[12:55:29.088] <TB3> INFO: 2560 events read in total (291ms).
[12:55:29.088] <TB3> INFO: Test took 1189ms.
[12:55:29.092] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:29.397] <TB3> INFO: Expecting 2560 events.
[12:55:30.281] <TB3> INFO: 2560 events read in total (292ms).
[12:55:30.281] <TB3> INFO: Test took 1189ms.
[12:55:30.284] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:30.589] <TB3> INFO: Expecting 2560 events.
[12:55:31.474] <TB3> INFO: 2560 events read in total (293ms).
[12:55:31.474] <TB3> INFO: Test took 1190ms.
[12:55:31.477] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:31.782] <TB3> INFO: Expecting 2560 events.
[12:55:32.668] <TB3> INFO: 2560 events read in total (294ms).
[12:55:32.669] <TB3> INFO: Test took 1193ms.
[12:55:32.672] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:32.977] <TB3> INFO: Expecting 2560 events.
[12:55:33.860] <TB3> INFO: 2560 events read in total (291ms).
[12:55:33.861] <TB3> INFO: Test took 1189ms.
[12:55:33.864] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:34.169] <TB3> INFO: Expecting 2560 events.
[12:55:35.058] <TB3> INFO: 2560 events read in total (297ms).
[12:55:35.059] <TB3> INFO: Test took 1195ms.
[12:55:35.061] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:35.366] <TB3> INFO: Expecting 2560 events.
[12:55:36.252] <TB3> INFO: 2560 events read in total (294ms).
[12:55:36.253] <TB3> INFO: Test took 1192ms.
[12:55:36.716] <TB3> INFO: PixTestPhOptimization::doTest() done, duration: 641 seconds
[12:55:36.716] <TB3> INFO: PH scale (per ROC): 50 53 36 50 42 36 43 33 46 34 43 42 31 43 48 50
[12:55:36.716] <TB3> INFO: PH offset (per ROC): 112 123 93 132 105 100 101 93 108 95 90 110 112 104 127 120
[12:55:36.722] <TB3> INFO: Decoding statistics:
[12:55:36.722] <TB3> INFO: General information:
[12:55:36.722] <TB3> INFO: 16bit words read: 127888
[12:55:36.723] <TB3> INFO: valid events total: 20480
[12:55:36.723] <TB3> INFO: empty events: 17976
[12:55:36.723] <TB3> INFO: valid events with pixels: 2504
[12:55:36.723] <TB3> INFO: valid pixel hits: 2504
[12:55:36.723] <TB3> INFO: Event errors: 0
[12:55:36.723] <TB3> INFO: start marker: 0
[12:55:36.723] <TB3> INFO: stop marker: 0
[12:55:36.723] <TB3> INFO: overflow: 0
[12:55:36.723] <TB3> INFO: invalid 5bit words: 0
[12:55:36.723] <TB3> INFO: invalid XOR eye diagram: 0
[12:55:36.723] <TB3> INFO: frame (failed synchr.): 0
[12:55:36.723] <TB3> INFO: idle data (no TBM trl): 0
[12:55:36.723] <TB3> INFO: no data (only TBM hdr): 0
[12:55:36.723] <TB3> INFO: TBM errors: 0
[12:55:36.723] <TB3> INFO: flawed TBM headers: 0
[12:55:36.723] <TB3> INFO: flawed TBM trailers: 0
[12:55:36.723] <TB3> INFO: event ID mismatches: 0
[12:55:36.723] <TB3> INFO: ROC errors: 0
[12:55:36.723] <TB3> INFO: missing ROC header(s): 0
[12:55:36.723] <TB3> INFO: misplaced readback start: 0
[12:55:36.723] <TB3> INFO: Pixel decoding errors: 0
[12:55:36.723] <TB3> INFO: pixel data incomplete: 0
[12:55:36.723] <TB3> INFO: pixel address: 0
[12:55:36.723] <TB3> INFO: pulse height fill bit: 0
[12:55:36.723] <TB3> INFO: buffer corruption: 0
[12:55:36.889] <TB3> INFO: ######################################################################
[12:55:36.889] <TB3> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[12:55:36.889] <TB3> INFO: ######################################################################
[12:55:36.905] <TB3> INFO: scanning low vcal = 10
[12:55:37.184] <TB3> INFO: Expecting 41600 events.
[12:55:40.764] <TB3> INFO: 41600 events read in total (2989ms).
[12:55:40.764] <TB3> INFO: Test took 3858ms.
[12:55:40.766] <TB3> INFO: scanning low vcal = 20
[12:55:41.060] <TB3> INFO: Expecting 41600 events.
[12:55:44.640] <TB3> INFO: 41600 events read in total (2988ms).
[12:55:44.641] <TB3> INFO: Test took 3875ms.
[12:55:44.642] <TB3> INFO: scanning low vcal = 30
[12:55:44.938] <TB3> INFO: Expecting 41600 events.
[12:55:48.553] <TB3> INFO: 41600 events read in total (3023ms).
[12:55:48.554] <TB3> INFO: Test took 3913ms.
[12:55:48.557] <TB3> INFO: scanning low vcal = 40
[12:55:48.836] <TB3> INFO: Expecting 41600 events.
[12:55:52.756] <TB3> INFO: 41600 events read in total (3328ms).
[12:55:52.757] <TB3> INFO: Test took 4199ms.
[12:55:52.761] <TB3> INFO: scanning low vcal = 50
[12:55:53.037] <TB3> INFO: Expecting 41600 events.
[12:55:56.972] <TB3> INFO: 41600 events read in total (3343ms).
[12:55:56.973] <TB3> INFO: Test took 4212ms.
[12:55:56.978] <TB3> INFO: scanning low vcal = 60
[12:55:57.253] <TB3> INFO: Expecting 41600 events.
[12:56:01.193] <TB3> INFO: 41600 events read in total (3346ms).
[12:56:01.194] <TB3> INFO: Test took 4216ms.
[12:56:01.197] <TB3> INFO: scanning low vcal = 70
[12:56:01.474] <TB3> INFO: Expecting 41600 events.
[12:56:05.400] <TB3> INFO: 41600 events read in total (3334ms).
[12:56:05.401] <TB3> INFO: Test took 4204ms.
[12:56:05.404] <TB3> INFO: scanning low vcal = 80
[12:56:05.680] <TB3> INFO: Expecting 41600 events.
[12:56:09.634] <TB3> INFO: 41600 events read in total (3362ms).
[12:56:09.635] <TB3> INFO: Test took 4231ms.
[12:56:09.638] <TB3> INFO: scanning low vcal = 90
[12:56:09.915] <TB3> INFO: Expecting 41600 events.
[12:56:13.900] <TB3> INFO: 41600 events read in total (3394ms).
[12:56:13.901] <TB3> INFO: Test took 4263ms.
[12:56:13.906] <TB3> INFO: scanning low vcal = 100
[12:56:14.220] <TB3> INFO: Expecting 41600 events.
[12:56:18.152] <TB3> INFO: 41600 events read in total (3340ms).
[12:56:18.153] <TB3> INFO: Test took 4247ms.
[12:56:18.157] <TB3> INFO: scanning low vcal = 110
[12:56:18.434] <TB3> INFO: Expecting 41600 events.
[12:56:22.361] <TB3> INFO: 41600 events read in total (3336ms).
[12:56:22.362] <TB3> INFO: Test took 4205ms.
[12:56:22.365] <TB3> INFO: scanning low vcal = 120
[12:56:22.642] <TB3> INFO: Expecting 41600 events.
[12:56:26.663] <TB3> INFO: 41600 events read in total (3430ms).
[12:56:26.664] <TB3> INFO: Test took 4299ms.
[12:56:26.667] <TB3> INFO: scanning low vcal = 130
[12:56:26.945] <TB3> INFO: Expecting 41600 events.
[12:56:31.026] <TB3> INFO: 41600 events read in total (3489ms).
[12:56:31.027] <TB3> INFO: Test took 4360ms.
[12:56:31.030] <TB3> INFO: scanning low vcal = 140
[12:56:31.318] <TB3> INFO: Expecting 41600 events.
[12:56:35.294] <TB3> INFO: 41600 events read in total (3381ms).
[12:56:35.295] <TB3> INFO: Test took 4265ms.
[12:56:35.298] <TB3> INFO: scanning low vcal = 150
[12:56:35.579] <TB3> INFO: Expecting 41600 events.
[12:56:39.576] <TB3> INFO: 41600 events read in total (3405ms).
[12:56:39.577] <TB3> INFO: Test took 4279ms.
[12:56:39.581] <TB3> INFO: scanning low vcal = 160
[12:56:39.857] <TB3> INFO: Expecting 41600 events.
[12:56:43.801] <TB3> INFO: 41600 events read in total (3352ms).
[12:56:43.802] <TB3> INFO: Test took 4221ms.
[12:56:43.805] <TB3> INFO: scanning low vcal = 170
[12:56:44.082] <TB3> INFO: Expecting 41600 events.
[12:56:48.018] <TB3> INFO: 41600 events read in total (3344ms).
[12:56:48.019] <TB3> INFO: Test took 4213ms.
[12:56:48.025] <TB3> INFO: scanning low vcal = 180
[12:56:48.299] <TB3> INFO: Expecting 41600 events.
[12:56:52.269] <TB3> INFO: 41600 events read in total (3378ms).
[12:56:52.270] <TB3> INFO: Test took 4245ms.
[12:56:52.275] <TB3> INFO: scanning low vcal = 190
[12:56:52.574] <TB3> INFO: Expecting 41600 events.
[12:56:56.522] <TB3> INFO: 41600 events read in total (3356ms).
[12:56:56.523] <TB3> INFO: Test took 4248ms.
[12:56:56.526] <TB3> INFO: scanning low vcal = 200
[12:56:56.803] <TB3> INFO: Expecting 41600 events.
[12:57:00.810] <TB3> INFO: 41600 events read in total (3415ms).
[12:57:00.812] <TB3> INFO: Test took 4285ms.
[12:57:00.816] <TB3> INFO: scanning low vcal = 210
[12:57:01.092] <TB3> INFO: Expecting 41600 events.
[12:57:05.167] <TB3> INFO: 41600 events read in total (3483ms).
[12:57:05.169] <TB3> INFO: Test took 4353ms.
[12:57:05.172] <TB3> INFO: scanning low vcal = 220
[12:57:05.508] <TB3> INFO: Expecting 41600 events.
[12:57:09.581] <TB3> INFO: 41600 events read in total (3482ms).
[12:57:09.582] <TB3> INFO: Test took 4409ms.
[12:57:09.586] <TB3> INFO: scanning low vcal = 230
[12:57:09.932] <TB3> INFO: Expecting 41600 events.
[12:57:13.923] <TB3> INFO: 41600 events read in total (3399ms).
[12:57:13.924] <TB3> INFO: Test took 4338ms.
[12:57:13.928] <TB3> INFO: scanning low vcal = 240
[12:57:14.204] <TB3> INFO: Expecting 41600 events.
[12:57:18.146] <TB3> INFO: 41600 events read in total (3350ms).
[12:57:18.147] <TB3> INFO: Test took 4219ms.
[12:57:18.150] <TB3> INFO: scanning low vcal = 250
[12:57:18.461] <TB3> INFO: Expecting 41600 events.
[12:57:22.434] <TB3> INFO: 41600 events read in total (3381ms).
[12:57:22.435] <TB3> INFO: Test took 4285ms.
[12:57:22.439] <TB3> INFO: scanning high vcal = 30 (= 210 in low range)
[12:57:22.769] <TB3> INFO: Expecting 41600 events.
[12:57:26.716] <TB3> INFO: 41600 events read in total (3356ms).
[12:57:26.717] <TB3> INFO: Test took 4278ms.
[12:57:26.721] <TB3> INFO: scanning high vcal = 50 (= 350 in low range)
[12:57:26.997] <TB3> INFO: Expecting 41600 events.
[12:57:30.978] <TB3> INFO: 41600 events read in total (3389ms).
[12:57:30.979] <TB3> INFO: Test took 4258ms.
[12:57:30.983] <TB3> INFO: scanning high vcal = 70 (= 490 in low range)
[12:57:31.259] <TB3> INFO: Expecting 41600 events.
[12:57:35.200] <TB3> INFO: 41600 events read in total (3349ms).
[12:57:35.201] <TB3> INFO: Test took 4218ms.
[12:57:35.204] <TB3> INFO: scanning high vcal = 90 (= 630 in low range)
[12:57:35.480] <TB3> INFO: Expecting 41600 events.
[12:57:39.413] <TB3> INFO: 41600 events read in total (3341ms).
[12:57:39.415] <TB3> INFO: Test took 4211ms.
[12:57:39.419] <TB3> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:57:39.695] <TB3> INFO: Expecting 41600 events.
[12:57:43.698] <TB3> INFO: 41600 events read in total (3412ms).
[12:57:43.701] <TB3> INFO: Test took 4282ms.
[12:57:44.402] <TB3> INFO: PixTestGainPedestal::measure() done
[12:58:37.676] <TB3> INFO: PixTestGainPedestal::fit() done
[12:58:37.677] <TB3> INFO: non-linearity mean: 0.984 0.983 0.955 0.978 0.958 0.948 0.921 0.910 0.943 0.947 0.924 0.946 0.929 0.916 0.978 0.979
[12:58:37.677] <TB3> INFO: non-linearity RMS: 0.003 0.004 0.172 0.004 0.031 0.039 0.118 0.146 0.068 0.190 0.095 0.044 0.126 0.104 0.006 0.005
[12:58:37.677] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[12:58:37.698] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[12:58:37.719] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[12:58:37.741] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[12:58:37.762] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[12:58:37.784] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[12:58:37.805] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[12:58:37.827] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[12:58:37.848] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[12:58:37.870] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[12:58:37.891] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[12:58:37.913] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[12:58:37.934] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[12:58:37.956] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[12:58:37.977] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[12:58:37.999] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[12:58:38.020] <TB3> INFO: PixTestGainPedestal::fullTest() done, duration: 181 seconds
[12:58:38.020] <TB3> INFO: Decoding statistics:
[12:58:38.020] <TB3> INFO: General information:
[12:58:38.020] <TB3> INFO: 16bit words read: 3294128
[12:58:38.020] <TB3> INFO: valid events total: 332800
[12:58:38.020] <TB3> INFO: empty events: 726
[12:58:38.020] <TB3> INFO: valid events with pixels: 332074
[12:58:38.020] <TB3> INFO: valid pixel hits: 648664
[12:58:38.020] <TB3> INFO: Event errors: 0
[12:58:38.020] <TB3> INFO: start marker: 0
[12:58:38.020] <TB3> INFO: stop marker: 0
[12:58:38.020] <TB3> INFO: overflow: 0
[12:58:38.020] <TB3> INFO: invalid 5bit words: 0
[12:58:38.020] <TB3> INFO: invalid XOR eye diagram: 0
[12:58:38.020] <TB3> INFO: frame (failed synchr.): 0
[12:58:38.020] <TB3> INFO: idle data (no TBM trl): 0
[12:58:38.020] <TB3> INFO: no data (only TBM hdr): 0
[12:58:38.020] <TB3> INFO: TBM errors: 0
[12:58:38.020] <TB3> INFO: flawed TBM headers: 0
[12:58:38.021] <TB3> INFO: flawed TBM trailers: 0
[12:58:38.021] <TB3> INFO: event ID mismatches: 0
[12:58:38.021] <TB3> INFO: ROC errors: 0
[12:58:38.021] <TB3> INFO: missing ROC header(s): 0
[12:58:38.021] <TB3> INFO: misplaced readback start: 0
[12:58:38.021] <TB3> INFO: Pixel decoding errors: 0
[12:58:38.021] <TB3> INFO: pixel data incomplete: 0
[12:58:38.021] <TB3> INFO: pixel address: 0
[12:58:38.021] <TB3> INFO: pulse height fill bit: 0
[12:58:38.021] <TB3> INFO: buffer corruption: 0
[12:58:38.047] <TB3> INFO: Decoding statistics:
[12:58:38.047] <TB3> INFO: General information:
[12:58:38.047] <TB3> INFO: 16bit words read: 3423552
[12:58:38.047] <TB3> INFO: valid events total: 353536
[12:58:38.047] <TB3> INFO: empty events: 18958
[12:58:38.047] <TB3> INFO: valid events with pixels: 334578
[12:58:38.047] <TB3> INFO: valid pixel hits: 651168
[12:58:38.047] <TB3> INFO: Event errors: 0
[12:58:38.047] <TB3> INFO: start marker: 0
[12:58:38.047] <TB3> INFO: stop marker: 0
[12:58:38.047] <TB3> INFO: overflow: 0
[12:58:38.047] <TB3> INFO: invalid 5bit words: 0
[12:58:38.047] <TB3> INFO: invalid XOR eye diagram: 0
[12:58:38.047] <TB3> INFO: frame (failed synchr.): 0
[12:58:38.047] <TB3> INFO: idle data (no TBM trl): 0
[12:58:38.047] <TB3> INFO: no data (only TBM hdr): 0
[12:58:38.047] <TB3> INFO: TBM errors: 0
[12:58:38.047] <TB3> INFO: flawed TBM headers: 0
[12:58:38.047] <TB3> INFO: flawed TBM trailers: 0
[12:58:38.047] <TB3> INFO: event ID mismatches: 0
[12:58:38.047] <TB3> INFO: ROC errors: 0
[12:58:38.047] <TB3> INFO: missing ROC header(s): 0
[12:58:38.047] <TB3> INFO: misplaced readback start: 0
[12:58:38.047] <TB3> INFO: Pixel decoding errors: 0
[12:58:38.047] <TB3> INFO: pixel data incomplete: 0
[12:58:38.047] <TB3> INFO: pixel address: 0
[12:58:38.047] <TB3> INFO: pulse height fill bit: 0
[12:58:38.047] <TB3> INFO: buffer corruption: 0
[12:58:38.047] <TB3> INFO: enter test to run
[12:58:38.047] <TB3> INFO: test: trim80 no parameter change
[12:58:38.047] <TB3> INFO: running: trim80
[12:58:38.049] <TB3> INFO: ######################################################################
[12:58:38.049] <TB3> INFO: PixTestTrim80::doTest()
[12:58:38.049] <TB3> INFO: ######################################################################
[12:58:38.050] <TB3> INFO: ----------------------------------------------------------------------
[12:58:38.050] <TB3> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[12:58:38.050] <TB3> INFO: ----------------------------------------------------------------------
[12:58:38.118] <TB3> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:58:38.118] <TB3> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:58:38.132] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:58:38.132] <TB3> INFO: run 1 of 1
[12:58:38.483] <TB3> INFO: Expecting 5025280 events.
[12:59:06.700] <TB3> INFO: 679424 events read in total (27625ms).
[12:59:34.801] <TB3> INFO: 1354760 events read in total (55726ms).
[13:00:02.491] <TB3> INFO: 2028848 events read in total (83417ms).
[13:00:30.799] <TB3> INFO: 2702312 events read in total (111724ms).
[13:00:58.540] <TB3> INFO: 3375952 events read in total (139465ms).
[13:01:26.108] <TB3> INFO: 4047752 events read in total (167033ms).
[13:01:54.231] <TB3> INFO: 4719680 events read in total (195156ms).
[13:02:07.658] <TB3> INFO: 5025280 events read in total (208583ms).
[13:02:07.764] <TB3> INFO: Test took 209631ms.
[13:02:37.650] <TB3> INFO: ROC 0 VthrComp = 73
[13:02:37.650] <TB3> INFO: ROC 1 VthrComp = 69
[13:02:37.650] <TB3> INFO: ROC 2 VthrComp = 74
[13:02:37.650] <TB3> INFO: ROC 3 VthrComp = 73
[13:02:37.650] <TB3> INFO: ROC 4 VthrComp = 75
[13:02:37.650] <TB3> INFO: ROC 5 VthrComp = 77
[13:02:37.650] <TB3> INFO: ROC 6 VthrComp = 81
[13:02:37.651] <TB3> INFO: ROC 7 VthrComp = 78
[13:02:37.651] <TB3> INFO: ROC 8 VthrComp = 71
[13:02:37.651] <TB3> INFO: ROC 9 VthrComp = 72
[13:02:37.651] <TB3> INFO: ROC 10 VthrComp = 87
[13:02:37.651] <TB3> INFO: ROC 11 VthrComp = 75
[13:02:37.651] <TB3> INFO: ROC 12 VthrComp = 78
[13:02:37.651] <TB3> INFO: ROC 13 VthrComp = 77
[13:02:37.651] <TB3> INFO: ROC 14 VthrComp = 76
[13:02:37.652] <TB3> INFO: ROC 15 VthrComp = 73
[13:02:37.890] <TB3> INFO: Expecting 41600 events.
[13:02:41.457] <TB3> INFO: 41600 events read in total (2975ms).
[13:02:41.458] <TB3> INFO: Test took 3805ms.
[13:02:41.470] <TB3> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:02:41.470] <TB3> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:02:41.484] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:02:41.484] <TB3> INFO: run 1 of 1
[13:02:41.762] <TB3> INFO: Expecting 5025280 events.
[13:03:10.695] <TB3> INFO: 689456 events read in total (28341ms).
[13:03:38.421] <TB3> INFO: 1375544 events read in total (56067ms).
[13:04:06.772] <TB3> INFO: 2059760 events read in total (84418ms).
[13:04:35.089] <TB3> INFO: 2740560 events read in total (112735ms).
[13:05:03.031] <TB3> INFO: 3417368 events read in total (140677ms).
[13:05:31.798] <TB3> INFO: 4091120 events read in total (169444ms).
[13:05:59.983] <TB3> INFO: 4762576 events read in total (197629ms).
[13:06:11.188] <TB3> INFO: 5025280 events read in total (208834ms).
[13:06:11.269] <TB3> INFO: Test took 209784ms.
[13:06:43.933] <TB3> INFO: roc 0 with ID = 0 has maximal Vcal 112.254 for pixel 0/41 mean/min/max = 95.1104/77.6547/112.566
[13:06:43.933] <TB3> INFO: roc 1 with ID = 1 has maximal Vcal 103.307 for pixel 0/18 mean/min/max = 88.8402/74.3006/103.38
[13:06:43.934] <TB3> INFO: roc 2 with ID = 2 has maximal Vcal 109.944 for pixel 0/10 mean/min/max = 94.6058/79.2137/109.998
[13:06:43.934] <TB3> INFO: roc 3 with ID = 3 has maximal Vcal 110.543 for pixel 6/48 mean/min/max = 93.9844/77.217/110.752
[13:06:43.935] <TB3> INFO: roc 4 with ID = 4 has maximal Vcal 114.001 for pixel 6/72 mean/min/max = 95.7532/77.4585/114.048
[13:06:43.935] <TB3> INFO: roc 5 with ID = 5 has maximal Vcal 113.488 for pixel 8/79 mean/min/max = 95.8167/77.9733/113.66
[13:06:43.936] <TB3> INFO: roc 6 with ID = 6 has maximal Vcal 105.898 for pixel 26/4 mean/min/max = 91.0519/76.1709/105.933
[13:06:43.937] <TB3> INFO: roc 7 with ID = 7 has maximal Vcal 114.461 for pixel 5/79 mean/min/max = 96.2661/77.9633/114.569
[13:06:43.937] <TB3> INFO: roc 8 with ID = 8 has maximal Vcal 107.707 for pixel 2/69 mean/min/max = 90.6377/73.3433/107.932
[13:06:43.938] <TB3> INFO: roc 9 with ID = 9 has maximal Vcal 111.438 for pixel 2/4 mean/min/max = 93.992/76.4727/111.511
[13:06:43.938] <TB3> INFO: roc 10 with ID = 10 has maximal Vcal 106.069 for pixel 12/74 mean/min/max = 90.5643/75.042/106.087
[13:06:43.939] <TB3> INFO: roc 11 with ID = 11 has maximal Vcal 109.715 for pixel 0/76 mean/min/max = 93.6996/77.6099/109.789
[13:06:43.940] <TB3> INFO: roc 12 with ID = 12 has maximal Vcal 108.089 for pixel 0/21 mean/min/max = 93.2096/78.2612/108.158
[13:06:43.940] <TB3> INFO: roc 13 with ID = 13 has maximal Vcal 109.891 for pixel 0/6 mean/min/max = 94.2064/78.5164/109.896
[13:06:43.941] <TB3> INFO: roc 14 with ID = 14 has maximal Vcal 108.17 for pixel 0/67 mean/min/max = 93.2658/78.3356/108.196
[13:06:43.941] <TB3> INFO: roc 15 with ID = 15 has maximal Vcal 109.297 for pixel 0/41 mean/min/max = 92.9046/76.4705/109.339
[13:06:43.942] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:06:44.031] <TB3> INFO: Expecting 411648 events.
[13:06:53.499] <TB3> INFO: 411648 events read in total (8877ms).
[13:06:53.510] <TB3> INFO: Expecting 411648 events.
[13:07:02.680] <TB3> INFO: 411648 events read in total (8767ms).
[13:07:02.692] <TB3> INFO: Expecting 411648 events.
[13:07:11.978] <TB3> INFO: 411648 events read in total (8883ms).
[13:07:11.993] <TB3> INFO: Expecting 411648 events.
[13:07:21.220] <TB3> INFO: 411648 events read in total (8823ms).
[13:07:21.237] <TB3> INFO: Expecting 411648 events.
[13:07:30.568] <TB3> INFO: 411648 events read in total (8923ms).
[13:07:30.588] <TB3> INFO: Expecting 411648 events.
[13:07:39.864] <TB3> INFO: 411648 events read in total (8873ms).
[13:07:39.892] <TB3> INFO: Expecting 411648 events.
[13:07:49.152] <TB3> INFO: 411648 events read in total (8857ms).
[13:07:49.184] <TB3> INFO: Expecting 411648 events.
[13:07:58.541] <TB3> INFO: 411648 events read in total (8954ms).
[13:07:58.568] <TB3> INFO: Expecting 411648 events.
[13:08:07.802] <TB3> INFO: 411648 events read in total (8830ms).
[13:08:07.833] <TB3> INFO: Expecting 411648 events.
[13:08:17.008] <TB3> INFO: 411648 events read in total (8772ms).
[13:08:17.056] <TB3> INFO: Expecting 411648 events.
[13:08:26.209] <TB3> INFO: 411648 events read in total (8750ms).
[13:08:26.249] <TB3> INFO: Expecting 411648 events.
[13:08:35.575] <TB3> INFO: 411648 events read in total (8923ms).
[13:08:35.625] <TB3> INFO: Expecting 411648 events.
[13:08:44.797] <TB3> INFO: 411648 events read in total (8769ms).
[13:08:44.843] <TB3> INFO: Expecting 411648 events.
[13:08:53.963] <TB3> INFO: 411648 events read in total (8717ms).
[13:08:54.017] <TB3> INFO: Expecting 411648 events.
[13:09:03.275] <TB3> INFO: 411648 events read in total (8855ms).
[13:09:03.375] <TB3> INFO: Expecting 411648 events.
[13:09:12.503] <TB3> INFO: 411648 events read in total (8725ms).
[13:09:12.569] <TB3> INFO: Test took 148627ms.
[13:09:14.093] <TB3> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:09:14.108] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:09:14.108] <TB3> INFO: run 1 of 1
[13:09:14.352] <TB3> INFO: Expecting 5025280 events.
[13:09:42.960] <TB3> INFO: 673096 events read in total (28016ms).
[13:10:10.348] <TB3> INFO: 1342696 events read in total (55404ms).
[13:10:38.325] <TB3> INFO: 2009824 events read in total (83381ms).
[13:11:06.187] <TB3> INFO: 2674376 events read in total (111243ms).
[13:11:34.600] <TB3> INFO: 3333528 events read in total (139656ms).
[13:12:02.291] <TB3> INFO: 3990824 events read in total (167347ms).
[13:12:29.911] <TB3> INFO: 4645672 events read in total (194967ms).
[13:12:46.223] <TB3> INFO: 5025280 events read in total (211279ms).
[13:12:46.318] <TB3> INFO: Test took 212210ms.
[13:13:14.989] <TB3> INFO: ---> TrimStepCorr4 extremal thresholds: 53.123332 .. 100.318105
[13:13:15.227] <TB3> INFO: Expecting 208000 events.
[13:13:25.194] <TB3> INFO: 208000 events read in total (9370ms).
[13:13:25.194] <TB3> INFO: Test took 10203ms.
[13:13:25.244] <TB3> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 43 .. 110 (-1/-1) hits flags = 528 (plus default)
[13:13:25.259] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:13:25.259] <TB3> INFO: run 1 of 1
[13:13:25.537] <TB3> INFO: Expecting 2263040 events.
[13:13:55.167] <TB3> INFO: 691000 events read in total (29038ms).
[13:14:23.703] <TB3> INFO: 1379848 events read in total (57575ms).
[13:14:52.626] <TB3> INFO: 2059104 events read in total (86497ms).
[13:15:01.531] <TB3> INFO: 2263040 events read in total (95402ms).
[13:15:01.569] <TB3> INFO: Test took 96311ms.
[13:15:24.073] <TB3> INFO: ---> TrimStepCorr2 extremal thresholds: 63.364832 .. 90.788223
[13:15:24.312] <TB3> INFO: Expecting 208000 events.
[13:15:34.737] <TB3> INFO: 208000 events read in total (9834ms).
[13:15:34.738] <TB3> INFO: Test took 10663ms.
[13:15:34.789] <TB3> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 53 .. 100 (-1/-1) hits flags = 528 (plus default)
[13:15:34.805] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:15:34.805] <TB3> INFO: run 1 of 1
[13:15:35.083] <TB3> INFO: Expecting 1597440 events.
[13:16:04.908] <TB3> INFO: 694664 events read in total (29229ms).
[13:16:34.588] <TB3> INFO: 1388848 events read in total (58911ms).
[13:16:43.709] <TB3> INFO: 1597440 events read in total (68030ms).
[13:16:43.747] <TB3> INFO: Test took 68943ms.
[13:17:05.411] <TB3> INFO: ---> TrimStepCorr1a extremal thresholds: 66.412007 .. 86.852564
[13:17:05.739] <TB3> INFO: Expecting 208000 events.
[13:17:15.696] <TB3> INFO: 208000 events read in total (9365ms).
[13:17:15.698] <TB3> INFO: Test took 10284ms.
[13:17:15.749] <TB3> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 56 .. 96 (-1/-1) hits flags = 528 (plus default)
[13:17:15.765] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:17:15.765] <TB3> INFO: run 1 of 1
[13:17:16.103] <TB3> INFO: Expecting 1364480 events.
[13:17:46.136] <TB3> INFO: 703760 events read in total (29442ms).
[13:18:13.947] <TB3> INFO: 1364480 events read in total (57254ms).
[13:18:13.977] <TB3> INFO: Test took 58211ms.
[13:18:33.876] <TB3> INFO: ---> TrimStepCorr1b extremal thresholds: 68.887388 .. 86.475617
[13:18:34.180] <TB3> INFO: Expecting 208000 events.
[13:18:44.897] <TB3> INFO: 208000 events read in total (10125ms).
[13:18:44.898] <TB3> INFO: Test took 11016ms.
[13:18:44.947] <TB3> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 58 .. 96 (-1/-1) hits flags = 528 (plus default)
[13:18:44.961] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:18:44.961] <TB3> INFO: run 1 of 1
[13:18:45.239] <TB3> INFO: Expecting 1297920 events.
[13:19:15.022] <TB3> INFO: 697600 events read in total (29191ms).
[13:19:40.174] <TB3> INFO: 1297920 events read in total (54343ms).
[13:19:40.212] <TB3> INFO: Test took 55252ms.
[13:20:00.733] <TB3> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[13:20:00.733] <TB3> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[13:20:00.748] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:20:00.748] <TB3> INFO: run 1 of 1
[13:20:00.993] <TB3> INFO: Expecting 1364480 events.
[13:20:30.172] <TB3> INFO: 668952 events read in total (28587ms).
[13:20:58.234] <TB3> INFO: 1337200 events read in total (56650ms).
[13:20:59.840] <TB3> INFO: 1364480 events read in total (58255ms).
[13:20:59.864] <TB3> INFO: Test took 59117ms.
[13:21:20.029] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C0.dat
[13:21:20.029] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C1.dat
[13:21:20.029] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C2.dat
[13:21:20.029] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C3.dat
[13:21:20.029] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C4.dat
[13:21:20.030] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C5.dat
[13:21:20.030] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C6.dat
[13:21:20.030] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C7.dat
[13:21:20.030] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C8.dat
[13:21:20.030] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C9.dat
[13:21:20.030] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C10.dat
[13:21:20.030] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C11.dat
[13:21:20.030] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C12.dat
[13:21:20.030] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C13.dat
[13:21:20.030] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C14.dat
[13:21:20.030] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C15.dat
[13:21:20.031] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C0.dat
[13:21:20.038] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C1.dat
[13:21:20.045] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C2.dat
[13:21:20.051] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C3.dat
[13:21:20.058] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C4.dat
[13:21:20.065] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C5.dat
[13:21:20.071] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C6.dat
[13:21:20.078] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C7.dat
[13:21:20.085] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C8.dat
[13:21:20.091] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C9.dat
[13:21:20.098] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C10.dat
[13:21:20.105] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C11.dat
[13:21:20.112] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C12.dat
[13:21:20.118] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C13.dat
[13:21:20.124] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C14.dat
[13:21:20.130] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1120_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C15.dat
[13:21:20.137] <TB3> INFO: PixTestTrim80::trimTest() done
[13:21:20.137] <TB3> INFO: vtrim: 117 83 98 101 123 127 96 127 96 110 100 100 100 97 99 98
[13:21:20.137] <TB3> INFO: vthrcomp: 73 69 74 73 75 77 81 78 71 72 87 75 78 77 76 73
[13:21:20.137] <TB3> INFO: vcal mean: 79.99 79.95 79.92 79.94 79.96 79.98 79.97 79.97 79.95 79.98 79.95 79.98 79.99 79.99 80.02 80.04
[13:21:20.137] <TB3> INFO: vcal RMS: 0.77 0.72 0.70 1.43 0.76 0.76 0.71 0.74 1.45 0.76 1.41 0.71 0.73 0.69 0.68 1.44
[13:21:20.137] <TB3> INFO: bits mean: 9.28 10.32 8.80 9.55 9.75 9.37 9.79 9.45 10.31 9.71 10.10 8.87 9.19 8.82 9.07 9.33
[13:21:20.137] <TB3> INFO: bits RMS: 2.29 2.53 2.31 2.22 2.11 2.23 2.41 2.18 2.54 2.31 2.41 2.54 2.32 2.42 2.34 2.55
[13:21:20.151] <TB3> INFO: ----------------------------------------------------------------------
[13:21:20.151] <TB3> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:21:20.151] <TB3> INFO: ----------------------------------------------------------------------
[13:21:20.154] <TB3> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:21:20.172] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:21:20.172] <TB3> INFO: run 1 of 1
[13:21:20.442] <TB3> INFO: Expecting 4160000 events.
[13:21:53.922] <TB3> INFO: 768610 events read in total (32888ms).
[13:22:26.476] <TB3> INFO: 1530675 events read in total (65442ms).
[13:22:58.927] <TB3> INFO: 2286510 events read in total (97893ms).
[13:23:31.198] <TB3> INFO: 3037195 events read in total (130164ms).
[13:24:03.556] <TB3> INFO: 3785030 events read in total (162522ms).
[13:24:20.046] <TB3> INFO: 4160000 events read in total (179012ms).
[13:24:20.149] <TB3> INFO: Test took 179977ms.
[13:24:52.521] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[13:24:52.536] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:24:52.536] <TB3> INFO: run 1 of 1
[13:24:52.840] <TB3> INFO: Expecting 4326400 events.
[13:25:25.731] <TB3> INFO: 733845 events read in total (32299ms).
[13:25:57.438] <TB3> INFO: 1462540 events read in total (64006ms).
[13:26:28.724] <TB3> INFO: 2188000 events read in total (95292ms).
[13:27:00.234] <TB3> INFO: 2908010 events read in total (126802ms).
[13:27:31.483] <TB3> INFO: 3626050 events read in total (158051ms).
[13:28:01.803] <TB3> INFO: 4326400 events read in total (188371ms).
[13:28:01.920] <TB3> INFO: Test took 189384ms.
[13:28:34.172] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[13:28:34.186] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:28:34.186] <TB3> INFO: run 1 of 1
[13:28:34.428] <TB3> INFO: Expecting 4097600 events.
[13:29:07.391] <TB3> INFO: 750345 events read in total (32372ms).
[13:29:40.683] <TB3> INFO: 1494865 events read in total (65664ms).
[13:30:12.634] <TB3> INFO: 2234150 events read in total (97615ms).
[13:30:44.478] <TB3> INFO: 2968760 events read in total (129459ms).
[13:31:16.312] <TB3> INFO: 3700180 events read in total (161293ms).
[13:31:33.750] <TB3> INFO: 4097600 events read in total (178731ms).
[13:31:33.823] <TB3> INFO: Test took 179637ms.
[13:32:04.908] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 197 (-1/-1) hits flags = 528 (plus default)
[13:32:04.922] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:32:04.922] <TB3> INFO: run 1 of 1
[13:32:05.175] <TB3> INFO: Expecting 4118400 events.
[13:32:38.363] <TB3> INFO: 748840 events read in total (32597ms).
[13:33:10.787] <TB3> INFO: 1491890 events read in total (65021ms).
[13:33:42.813] <TB3> INFO: 2230235 events read in total (97047ms).
[13:34:14.430] <TB3> INFO: 2963805 events read in total (128664ms).
[13:34:46.283] <TB3> INFO: 3693610 events read in total (160517ms).
[13:35:04.733] <TB3> INFO: 4118400 events read in total (178967ms).
[13:35:04.835] <TB3> INFO: Test took 179914ms.
[13:35:36.226] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 197 (-1/-1) hits flags = 528 (plus default)
[13:35:36.241] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:35:36.241] <TB3> INFO: run 1 of 1
[13:35:36.498] <TB3> INFO: Expecting 4118400 events.
[13:36:09.227] <TB3> INFO: 749110 events read in total (32138ms).
[13:36:41.510] <TB3> INFO: 1492380 events read in total (64421ms).
[13:37:13.887] <TB3> INFO: 2230650 events read in total (96798ms).
[13:37:45.948] <TB3> INFO: 2964430 events read in total (128859ms).
[13:38:17.924] <TB3> INFO: 3694505 events read in total (160835ms).
[13:38:36.123] <TB3> INFO: 4118400 events read in total (179034ms).
[13:38:36.197] <TB3> INFO: Test took 179956ms.
[13:39:06.297] <TB3> INFO: PixTestTrim80::trimBitTest() done
[13:39:06.299] <TB3> INFO: PixTestTrim80::doTest() done, duration: 2428 seconds
[13:39:07.182] <TB3> INFO: enter test to run
[13:39:07.183] <TB3> INFO: test: exit no parameter change
[13:39:07.461] <TB3> QUIET: Connection to board 126 closed.
[13:39:07.467] <TB3> INFO: pXar: this is the end, my friend