[09:55:28.777] <TB2> INFO: *** Welcome to pxar ***
[09:55:28.777] <TB2> INFO: *** Today: 2016/11/03
[09:55:28.786] <TB2> INFO: *** Version: c8ba-dirty
[09:55:28.786] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C15.dat
[09:55:28.787] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//tbmParameters_C1b.dat
[09:55:28.787] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//defaultMaskFile.dat
[09:55:28.787] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters_C15.dat
[09:55:28.882] <TB2> INFO: clk: 4
[09:55:28.882] <TB2> INFO: ctr: 4
[09:55:28.882] <TB2> INFO: sda: 19
[09:55:28.882] <TB2> INFO: tin: 9
[09:55:28.882] <TB2> INFO: level: 15
[09:55:28.882] <TB2> INFO: triggerdelay: 0
[09:55:28.882] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[09:55:28.882] <TB2> INFO: Log level: INFO
[09:55:28.892] <TB2> INFO: Found DTB DTB_WWXUD2
[09:55:28.899] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[09:55:28.901] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[09:55:28.903] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[09:55:30.393] <TB2> INFO: DUT info:
[09:55:30.393] <TB2> INFO: The DUT currently contains the following objects:
[09:55:30.393] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[09:55:30.393] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:55:30.393] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:55:30.394] <TB2> INFO: TBM Core alpha (2): 7 registers set
[09:55:30.394] <TB2> INFO: TBM Core beta (3): 7 registers set
[09:55:30.395] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[09:55:30.395] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.395] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[09:55:30.796] <TB2> INFO: enter 'restricted' command line mode
[09:55:30.796] <TB2> INFO: enter test to run
[09:55:30.796] <TB2> INFO: test: pretest no parameter change
[09:55:30.796] <TB2> INFO: running: pretest
[09:55:30.800] <TB2> INFO: ######################################################################
[09:55:30.800] <TB2> INFO: PixTestPretest::doTest()
[09:55:30.800] <TB2> INFO: ######################################################################
[09:55:30.801] <TB2> INFO: ----------------------------------------------------------------------
[09:55:30.801] <TB2> INFO: PixTestPretest::programROC()
[09:55:30.801] <TB2> INFO: ----------------------------------------------------------------------
[09:55:48.821] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[09:55:48.821] <TB2> INFO: IA differences per ROC: 17.7 20.1 18.5 20.1 17.7 19.3 18.5 19.3 17.7 18.5 21.7 19.3 19.3 19.3 19.3 19.3
[09:55:48.897] <TB2> INFO: ----------------------------------------------------------------------
[09:55:48.897] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[09:55:48.897] <TB2> INFO: ----------------------------------------------------------------------
[09:56:10.150] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 389.1 mA = 24.3188 mA/ROC
[09:56:10.150] <TB2> INFO: i(loss) [mA/ROC]: 20.9 20.1 20.9 19.3 19.3 20.9 20.9 20.1 21.7 20.1 18.5 19.3 20.9 19.3 19.3 19.3
[09:56:10.177] <TB2> INFO: ----------------------------------------------------------------------
[09:56:10.177] <TB2> INFO: PixTestPretest::findTiming()
[09:56:10.177] <TB2> INFO: ----------------------------------------------------------------------
[09:56:10.177] <TB2> INFO: PixTestCmd::init()

[09:56:41.447] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 6, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[09:56:41.447] <TB2> INFO: (success/tries = 100/100), width = 3
[09:56:42.939] <TB2> INFO: ----------------------------------------------------------------------
[09:56:42.939] <TB2> INFO: PixTestPretest::findWorkingPixel()
[09:56:42.939] <TB2> INFO: ----------------------------------------------------------------------
[09:56:43.031] <TB2> INFO: Expecting 231680 events.
[09:56:52.735] <TB2> INFO: 231680 events read in total (9112ms).
[09:56:52.751] <TB2> INFO: Test took 9810ms.
[09:56:53.009] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[09:56:53.038] <TB2> INFO: ----------------------------------------------------------------------
[09:56:53.038] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[09:56:53.038] <TB2> INFO: ----------------------------------------------------------------------
[09:56:53.131] <TB2> INFO: Expecting 231680 events.
[09:57:02.938] <TB2> INFO: 231680 events read in total (9215ms).
[09:57:02.953] <TB2> INFO: Test took 9910ms.
[09:57:03.205] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[09:57:03.205] <TB2> INFO: CalDel: 94 89 89 92 97 81 96 101 107 94 98 122 97 90 102 121
[09:57:03.205] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[09:57:03.207] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C0.dat
[09:57:03.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C1.dat
[09:57:03.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C2.dat
[09:57:03.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C3.dat
[09:57:03.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C4.dat
[09:57:03.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C5.dat
[09:57:03.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C6.dat
[09:57:03.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C7.dat
[09:57:03.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C8.dat
[09:57:03.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C9.dat
[09:57:03.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C10.dat
[09:57:03.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C11.dat
[09:57:03.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C12.dat
[09:57:03.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C13.dat
[09:57:03.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C14.dat
[09:57:03.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters_C15.dat
[09:57:03.209] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//tbmParameters_C0a.dat
[09:57:03.209] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//tbmParameters_C0b.dat
[09:57:03.209] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//tbmParameters_C1a.dat
[09:57:03.209] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//tbmParameters_C1b.dat
[09:57:03.209] <TB2> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[09:57:03.260] <TB2> INFO: enter test to run
[09:57:03.260] <TB2> INFO: test: FullTest no parameter change
[09:57:03.260] <TB2> INFO: running: fulltest
[09:57:03.260] <TB2> INFO: ######################################################################
[09:57:03.260] <TB2> INFO: PixTestFullTest::doTest()
[09:57:03.260] <TB2> INFO: ######################################################################
[09:57:03.262] <TB2> INFO: ######################################################################
[09:57:03.262] <TB2> INFO: PixTestAlive::doTest()
[09:57:03.262] <TB2> INFO: ######################################################################
[09:57:03.263] <TB2> INFO: ----------------------------------------------------------------------
[09:57:03.264] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:57:03.264] <TB2> INFO: ----------------------------------------------------------------------
[09:57:03.503] <TB2> INFO: Expecting 41600 events.
[09:57:06.965] <TB2> INFO: 41600 events read in total (2871ms).
[09:57:06.966] <TB2> INFO: Test took 3700ms.
[09:57:07.193] <TB2> INFO: PixTestAlive::aliveTest() done
[09:57:07.193] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
[09:57:07.194] <TB2> INFO: ----------------------------------------------------------------------
[09:57:07.194] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:57:07.194] <TB2> INFO: ----------------------------------------------------------------------
[09:57:07.433] <TB2> INFO: Expecting 41600 events.
[09:57:10.379] <TB2> INFO: 41600 events read in total (2354ms).
[09:57:10.379] <TB2> INFO: Test took 3183ms.
[09:57:10.380] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[09:57:10.616] <TB2> INFO: PixTestAlive::maskTest() done
[09:57:10.616] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:57:10.617] <TB2> INFO: ----------------------------------------------------------------------
[09:57:10.617] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:57:10.617] <TB2> INFO: ----------------------------------------------------------------------
[09:57:10.857] <TB2> INFO: Expecting 41600 events.
[09:57:14.516] <TB2> INFO: 41600 events read in total (3068ms).
[09:57:14.517] <TB2> INFO: Test took 3898ms.
[09:57:14.743] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[09:57:14.743] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:57:14.743] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[09:57:14.743] <TB2> INFO: Decoding statistics:
[09:57:14.743] <TB2> INFO: General information:
[09:57:14.743] <TB2> INFO: 16bit words read: 0
[09:57:14.743] <TB2> INFO: valid events total: 0
[09:57:14.743] <TB2> INFO: empty events: 0
[09:57:14.743] <TB2> INFO: valid events with pixels: 0
[09:57:14.743] <TB2> INFO: valid pixel hits: 0
[09:57:14.743] <TB2> INFO: Event errors: 0
[09:57:14.744] <TB2> INFO: start marker: 0
[09:57:14.744] <TB2> INFO: stop marker: 0
[09:57:14.744] <TB2> INFO: overflow: 0
[09:57:14.744] <TB2> INFO: invalid 5bit words: 0
[09:57:14.744] <TB2> INFO: invalid XOR eye diagram: 0
[09:57:14.744] <TB2> INFO: frame (failed synchr.): 0
[09:57:14.744] <TB2> INFO: idle data (no TBM trl): 0
[09:57:14.744] <TB2> INFO: no data (only TBM hdr): 0
[09:57:14.744] <TB2> INFO: TBM errors: 0
[09:57:14.744] <TB2> INFO: flawed TBM headers: 0
[09:57:14.744] <TB2> INFO: flawed TBM trailers: 0
[09:57:14.744] <TB2> INFO: event ID mismatches: 0
[09:57:14.744] <TB2> INFO: ROC errors: 0
[09:57:14.744] <TB2> INFO: missing ROC header(s): 0
[09:57:14.744] <TB2> INFO: misplaced readback start: 0
[09:57:14.744] <TB2> INFO: Pixel decoding errors: 0
[09:57:14.744] <TB2> INFO: pixel data incomplete: 0
[09:57:14.744] <TB2> INFO: pixel address: 0
[09:57:14.744] <TB2> INFO: pulse height fill bit: 0
[09:57:14.744] <TB2> INFO: buffer corruption: 0
[09:57:14.749] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C15.dat
[09:57:14.750] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[09:57:14.750] <TB2> INFO: ######################################################################
[09:57:14.750] <TB2> INFO: PixTestReadback::doTest()
[09:57:14.750] <TB2> INFO: ######################################################################
[09:57:14.750] <TB2> INFO: ----------------------------------------------------------------------
[09:57:14.750] <TB2> INFO: PixTestReadback::CalibrateVd()
[09:57:14.750] <TB2> INFO: ----------------------------------------------------------------------
[09:57:24.674] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C0.dat
[09:57:24.674] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C1.dat
[09:57:24.674] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C2.dat
[09:57:24.674] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C3.dat
[09:57:24.674] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C4.dat
[09:57:24.674] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C5.dat
[09:57:24.674] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C6.dat
[09:57:24.674] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C7.dat
[09:57:24.674] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C8.dat
[09:57:24.674] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C9.dat
[09:57:24.675] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C10.dat
[09:57:24.675] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C11.dat
[09:57:24.675] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C12.dat
[09:57:24.675] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C13.dat
[09:57:24.675] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C14.dat
[09:57:24.675] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C15.dat
[09:57:24.705] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[09:57:24.705] <TB2> INFO: ----------------------------------------------------------------------
[09:57:24.705] <TB2> INFO: PixTestReadback::CalibrateVa()
[09:57:24.705] <TB2> INFO: ----------------------------------------------------------------------
[09:57:34.597] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C0.dat
[09:57:34.597] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C1.dat
[09:57:34.597] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C2.dat
[09:57:34.597] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C3.dat
[09:57:34.597] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C4.dat
[09:57:34.598] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C5.dat
[09:57:34.598] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C6.dat
[09:57:34.598] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C7.dat
[09:57:34.598] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C8.dat
[09:57:34.598] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C9.dat
[09:57:34.598] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C10.dat
[09:57:34.598] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C11.dat
[09:57:34.598] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C12.dat
[09:57:34.598] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C13.dat
[09:57:34.598] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C14.dat
[09:57:34.598] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C15.dat
[09:57:34.636] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[09:57:34.636] <TB2> INFO: ----------------------------------------------------------------------
[09:57:34.636] <TB2> INFO: PixTestReadback::readbackVbg()
[09:57:34.636] <TB2> INFO: ----------------------------------------------------------------------
[09:57:42.280] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[09:57:42.280] <TB2> INFO: ----------------------------------------------------------------------
[09:57:42.280] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[09:57:42.280] <TB2> INFO: ----------------------------------------------------------------------
[09:57:42.280] <TB2> INFO: Vbg will be calibrated using Vd calibration
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 148.1calibrated Vbg = 1.18212 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 157.6calibrated Vbg = 1.18252 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 154calibrated Vbg = 1.18031 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 154calibrated Vbg = 1.17653 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 159.7calibrated Vbg = 1.17896 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 152calibrated Vbg = 1.17878 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 159.5calibrated Vbg = 1.1797 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 153.4calibrated Vbg = 1.18279 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 152.8calibrated Vbg = 1.1793 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 147.5calibrated Vbg = 1.1749 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 145.4calibrated Vbg = 1.17371 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 149.5calibrated Vbg = 1.17179 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 154.4calibrated Vbg = 1.17152 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 150.5calibrated Vbg = 1.16956 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 155.6calibrated Vbg = 1.18461 :::*/*/*/*/
[09:57:42.280] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 161.2calibrated Vbg = 1.18445 :::*/*/*/*/
[09:57:42.282] <TB2> INFO: ----------------------------------------------------------------------
[09:57:42.282] <TB2> INFO: PixTestReadback::CalibrateIa()
[09:57:42.282] <TB2> INFO: ----------------------------------------------------------------------
[10:00:22.663] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C0.dat
[10:00:22.663] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C1.dat
[10:00:22.663] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C2.dat
[10:00:22.663] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C3.dat
[10:00:22.663] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C4.dat
[10:00:22.664] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C5.dat
[10:00:22.664] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C6.dat
[10:00:22.664] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C7.dat
[10:00:22.664] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C8.dat
[10:00:22.664] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C9.dat
[10:00:22.664] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C10.dat
[10:00:22.664] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C11.dat
[10:00:22.664] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C12.dat
[10:00:22.664] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C13.dat
[10:00:22.664] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C14.dat
[10:00:22.664] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//readbackCal_C15.dat
[10:00:22.692] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:00:22.693] <TB2> INFO: PixTestReadback::doTest() done
[10:00:22.693] <TB2> INFO: Decoding statistics:
[10:00:22.694] <TB2> INFO: General information:
[10:00:22.694] <TB2> INFO: 16bit words read: 1536
[10:00:22.694] <TB2> INFO: valid events total: 256
[10:00:22.694] <TB2> INFO: empty events: 256
[10:00:22.694] <TB2> INFO: valid events with pixels: 0
[10:00:22.694] <TB2> INFO: valid pixel hits: 0
[10:00:22.694] <TB2> INFO: Event errors: 0
[10:00:22.694] <TB2> INFO: start marker: 0
[10:00:22.694] <TB2> INFO: stop marker: 0
[10:00:22.694] <TB2> INFO: overflow: 0
[10:00:22.694] <TB2> INFO: invalid 5bit words: 0
[10:00:22.694] <TB2> INFO: invalid XOR eye diagram: 0
[10:00:22.694] <TB2> INFO: frame (failed synchr.): 0
[10:00:22.694] <TB2> INFO: idle data (no TBM trl): 0
[10:00:22.694] <TB2> INFO: no data (only TBM hdr): 0
[10:00:22.694] <TB2> INFO: TBM errors: 0
[10:00:22.694] <TB2> INFO: flawed TBM headers: 0
[10:00:22.694] <TB2> INFO: flawed TBM trailers: 0
[10:00:22.694] <TB2> INFO: event ID mismatches: 0
[10:00:22.694] <TB2> INFO: ROC errors: 0
[10:00:22.694] <TB2> INFO: missing ROC header(s): 0
[10:00:22.694] <TB2> INFO: misplaced readback start: 0
[10:00:22.694] <TB2> INFO: Pixel decoding errors: 0
[10:00:22.694] <TB2> INFO: pixel data incomplete: 0
[10:00:22.694] <TB2> INFO: pixel address: 0
[10:00:22.694] <TB2> INFO: pulse height fill bit: 0
[10:00:22.694] <TB2> INFO: buffer corruption: 0
[10:00:22.748] <TB2> INFO: ######################################################################
[10:00:22.748] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[10:00:22.748] <TB2> INFO: ######################################################################
[10:00:22.750] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[10:00:22.778] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[10:00:22.778] <TB2> INFO: run 1 of 1
[10:00:23.014] <TB2> INFO: Expecting 3120000 events.
[10:00:54.446] <TB2> INFO: 671980 events read in total (30840ms).











[10:01:25.246] <TB2> INFO: 1338030 events read in total (61640ms).











[10:01:55.739] <TB2> INFO: 2001470 events read in total (92133ms).











[10:02:27.030] <TB2> INFO: 2662945 events read in total (123424ms).











[10:02:48.649] <TB2> INFO: 3120000 events read in total (145043ms).
[10:02:48.757] <TB2> INFO: Test took 145981ms.
[10:03:18.693] <TB2> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 175 seconds
[10:03:18.693] <TB2> INFO: number of dead bumps (per ROC): 0 0 1 0 0 0 2 0 0 0 2 0 0 0 0 0
[10:03:18.693] <TB2> INFO: separation cut (per ROC): 107 108 117 105 116 118 123 94 110 111 105 98 118 104 113 104
[10:03:18.693] <TB2> INFO: Decoding statistics:
[10:03:18.693] <TB2> INFO: General information:
[10:03:18.693] <TB2> INFO: 16bit words read: 0
[10:03:18.693] <TB2> INFO: valid events total: 0
[10:03:18.693] <TB2> INFO: empty events: 0
[10:03:18.693] <TB2> INFO: valid events with pixels: 0
[10:03:18.693] <TB2> INFO: valid pixel hits: 0
[10:03:18.693] <TB2> INFO: Event errors: 0
[10:03:18.693] <TB2> INFO: start marker: 0
[10:03:18.693] <TB2> INFO: stop marker: 0
[10:03:18.693] <TB2> INFO: overflow: 0
[10:03:18.693] <TB2> INFO: invalid 5bit words: 0
[10:03:18.693] <TB2> INFO: invalid XOR eye diagram: 0
[10:03:18.693] <TB2> INFO: frame (failed synchr.): 0
[10:03:18.693] <TB2> INFO: idle data (no TBM trl): 0
[10:03:18.693] <TB2> INFO: no data (only TBM hdr): 0
[10:03:18.693] <TB2> INFO: TBM errors: 0
[10:03:18.693] <TB2> INFO: flawed TBM headers: 0
[10:03:18.693] <TB2> INFO: flawed TBM trailers: 0
[10:03:18.693] <TB2> INFO: event ID mismatches: 0
[10:03:18.693] <TB2> INFO: ROC errors: 0
[10:03:18.693] <TB2> INFO: missing ROC header(s): 0
[10:03:18.693] <TB2> INFO: misplaced readback start: 0
[10:03:18.693] <TB2> INFO: Pixel decoding errors: 0
[10:03:18.693] <TB2> INFO: pixel data incomplete: 0
[10:03:18.693] <TB2> INFO: pixel address: 0
[10:03:18.693] <TB2> INFO: pulse height fill bit: 0
[10:03:18.693] <TB2> INFO: buffer corruption: 0
[10:03:18.744] <TB2> INFO: ######################################################################
[10:03:18.744] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:03:18.744] <TB2> INFO: ######################################################################
[10:03:18.744] <TB2> INFO: ----------------------------------------------------------------------
[10:03:18.744] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:03:18.744] <TB2> INFO: ----------------------------------------------------------------------
[10:03:18.744] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[10:03:18.760] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[10:03:18.760] <TB2> INFO: run 1 of 1
[10:03:19.017] <TB2> INFO: Expecting 36608000 events.
[10:03:43.018] <TB2> INFO: 677800 events read in total (23402ms).
[10:04:06.566] <TB2> INFO: 1342800 events read in total (46950ms).
[10:04:30.198] <TB2> INFO: 2006900 events read in total (70582ms).
[10:04:53.655] <TB2> INFO: 2670450 events read in total (94039ms).
[10:05:16.862] <TB2> INFO: 3334450 events read in total (117246ms).
[10:05:40.176] <TB2> INFO: 3998700 events read in total (140560ms).
[10:06:03.532] <TB2> INFO: 4661250 events read in total (163916ms).
[10:06:26.870] <TB2> INFO: 5323400 events read in total (187254ms).
[10:06:50.088] <TB2> INFO: 5985000 events read in total (210472ms).
[10:07:14.044] <TB2> INFO: 6648550 events read in total (234428ms).
[10:07:37.479] <TB2> INFO: 7309700 events read in total (257863ms).
[10:08:01.115] <TB2> INFO: 7970450 events read in total (281499ms).
[10:08:24.732] <TB2> INFO: 8631600 events read in total (305116ms).
[10:08:48.084] <TB2> INFO: 9293700 events read in total (328468ms).
[10:09:12.180] <TB2> INFO: 9955000 events read in total (352564ms).
[10:09:35.608] <TB2> INFO: 10616550 events read in total (375992ms).
[10:09:59.352] <TB2> INFO: 11276800 events read in total (399736ms).
[10:10:23.278] <TB2> INFO: 11935850 events read in total (423662ms).
[10:10:47.268] <TB2> INFO: 12594100 events read in total (447652ms).
[10:11:11.160] <TB2> INFO: 13254250 events read in total (471544ms).
[10:11:34.936] <TB2> INFO: 13914000 events read in total (495320ms).
[10:11:58.485] <TB2> INFO: 14573450 events read in total (518869ms).
[10:12:22.063] <TB2> INFO: 15231950 events read in total (542448ms).
[10:12:46.699] <TB2> INFO: 15890550 events read in total (567083ms).
[10:13:10.054] <TB2> INFO: 16550050 events read in total (590438ms).
[10:13:33.974] <TB2> INFO: 17209500 events read in total (614358ms).
[10:13:58.307] <TB2> INFO: 17867500 events read in total (638691ms).
[10:14:22.388] <TB2> INFO: 18525900 events read in total (662772ms).
[10:14:46.159] <TB2> INFO: 19187350 events read in total (686543ms).
[10:15:09.938] <TB2> INFO: 19845150 events read in total (710322ms).
[10:15:33.833] <TB2> INFO: 20505300 events read in total (734217ms).
[10:15:57.703] <TB2> INFO: 21165100 events read in total (758087ms).
[10:16:21.105] <TB2> INFO: 21821050 events read in total (781489ms).
[10:16:44.726] <TB2> INFO: 22476350 events read in total (805110ms).
[10:17:08.486] <TB2> INFO: 23133050 events read in total (828870ms).
[10:17:31.995] <TB2> INFO: 23790950 events read in total (852379ms).
[10:17:55.683] <TB2> INFO: 24444750 events read in total (876067ms).
[10:18:19.578] <TB2> INFO: 25099050 events read in total (899962ms).
[10:18:43.883] <TB2> INFO: 25754750 events read in total (924267ms).
[10:19:07.617] <TB2> INFO: 26408650 events read in total (948001ms).
[10:19:30.969] <TB2> INFO: 27064550 events read in total (971353ms).
[10:19:54.456] <TB2> INFO: 27720900 events read in total (994840ms).
[10:20:18.138] <TB2> INFO: 28378300 events read in total (1018522ms).
[10:20:41.871] <TB2> INFO: 29035000 events read in total (1042255ms).
[10:21:05.505] <TB2> INFO: 29688450 events read in total (1065889ms).
[10:21:28.851] <TB2> INFO: 30342700 events read in total (1089235ms).
[10:21:52.368] <TB2> INFO: 30998000 events read in total (1112752ms).
[10:22:15.859] <TB2> INFO: 31651600 events read in total (1136243ms).
[10:22:39.106] <TB2> INFO: 32303800 events read in total (1159490ms).
[10:23:02.646] <TB2> INFO: 32960500 events read in total (1183030ms).
[10:23:26.555] <TB2> INFO: 33615900 events read in total (1206939ms).
[10:23:50.093] <TB2> INFO: 34273250 events read in total (1230478ms).
[10:24:13.156] <TB2> INFO: 34931200 events read in total (1253540ms).
[10:24:36.809] <TB2> INFO: 35591950 events read in total (1277193ms).
[10:25:01.700] <TB2> INFO: 36257550 events read in total (1302084ms).
[10:25:15.150] <TB2> INFO: 36608000 events read in total (1315534ms).
[10:25:15.238] <TB2> INFO: Test took 1316478ms.
[10:25:15.683] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:17.259] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:19.350] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:21.325] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:23.560] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:25.479] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:27.372] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:29.232] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:31.456] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:33.937] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:35.720] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:37.367] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:38.910] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:40.897] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:43.090] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:45.265] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:25:47.399] <TB2> INFO: PixTestScurves::scurves() done
[10:25:47.399] <TB2> INFO: Vcal mean: 111.00 117.04 117.15 107.31 121.67 115.06 119.53 99.42 116.07 117.36 117.87 104.13 123.05 110.33 123.40 100.64
[10:25:47.399] <TB2> INFO: Vcal RMS: 5.01 5.73 5.34 5.34 6.19 4.83 5.91 5.13 5.82 5.60 5.84 5.06 6.10 5.29 6.25 5.15
[10:25:47.399] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1348 seconds
[10:25:47.399] <TB2> INFO: Decoding statistics:
[10:25:47.399] <TB2> INFO: General information:
[10:25:47.399] <TB2> INFO: 16bit words read: 0
[10:25:47.399] <TB2> INFO: valid events total: 0
[10:25:47.399] <TB2> INFO: empty events: 0
[10:25:47.399] <TB2> INFO: valid events with pixels: 0
[10:25:47.399] <TB2> INFO: valid pixel hits: 0
[10:25:47.399] <TB2> INFO: Event errors: 0
[10:25:47.399] <TB2> INFO: start marker: 0
[10:25:47.399] <TB2> INFO: stop marker: 0
[10:25:47.399] <TB2> INFO: overflow: 0
[10:25:47.399] <TB2> INFO: invalid 5bit words: 0
[10:25:47.399] <TB2> INFO: invalid XOR eye diagram: 0
[10:25:47.399] <TB2> INFO: frame (failed synchr.): 0
[10:25:47.399] <TB2> INFO: idle data (no TBM trl): 0
[10:25:47.399] <TB2> INFO: no data (only TBM hdr): 0
[10:25:47.399] <TB2> INFO: TBM errors: 0
[10:25:47.399] <TB2> INFO: flawed TBM headers: 0
[10:25:47.399] <TB2> INFO: flawed TBM trailers: 0
[10:25:47.399] <TB2> INFO: event ID mismatches: 0
[10:25:47.399] <TB2> INFO: ROC errors: 0
[10:25:47.399] <TB2> INFO: missing ROC header(s): 0
[10:25:47.399] <TB2> INFO: misplaced readback start: 0
[10:25:47.399] <TB2> INFO: Pixel decoding errors: 0
[10:25:47.399] <TB2> INFO: pixel data incomplete: 0
[10:25:47.399] <TB2> INFO: pixel address: 0
[10:25:47.399] <TB2> INFO: pulse height fill bit: 0
[10:25:47.399] <TB2> INFO: buffer corruption: 0
[10:25:47.479] <TB2> INFO: ######################################################################
[10:25:47.479] <TB2> INFO: PixTestTrim::doTest()
[10:25:47.479] <TB2> INFO: ######################################################################
[10:25:47.480] <TB2> INFO: ----------------------------------------------------------------------
[10:25:47.480] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[10:25:47.480] <TB2> INFO: ----------------------------------------------------------------------
[10:25:47.543] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[10:25:47.543] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:25:47.558] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:25:47.558] <TB2> INFO: run 1 of 1
[10:25:47.817] <TB2> INFO: Expecting 5025280 events.
[10:26:18.955] <TB2> INFO: 829024 events read in total (30535ms).
[10:26:49.391] <TB2> INFO: 1654744 events read in total (60971ms).
[10:27:20.576] <TB2> INFO: 2477640 events read in total (92156ms).
[10:27:50.669] <TB2> INFO: 3295320 events read in total (122249ms).
[10:28:21.261] <TB2> INFO: 4108640 events read in total (152842ms).
[10:28:52.965] <TB2> INFO: 4920352 events read in total (184545ms).
[10:28:57.478] <TB2> INFO: 5025280 events read in total (189058ms).
[10:28:57.557] <TB2> INFO: Test took 189999ms.
[10:29:18.440] <TB2> INFO: ROC 0 VthrComp = 122
[10:29:18.441] <TB2> INFO: ROC 1 VthrComp = 126
[10:29:18.441] <TB2> INFO: ROC 2 VthrComp = 131
[10:29:18.441] <TB2> INFO: ROC 3 VthrComp = 117
[10:29:18.441] <TB2> INFO: ROC 4 VthrComp = 125
[10:29:18.441] <TB2> INFO: ROC 5 VthrComp = 131
[10:29:18.441] <TB2> INFO: ROC 6 VthrComp = 131
[10:29:18.441] <TB2> INFO: ROC 7 VthrComp = 103
[10:29:18.442] <TB2> INFO: ROC 8 VthrComp = 124
[10:29:18.442] <TB2> INFO: ROC 9 VthrComp = 127
[10:29:18.442] <TB2> INFO: ROC 10 VthrComp = 122
[10:29:18.443] <TB2> INFO: ROC 11 VthrComp = 103
[10:29:18.444] <TB2> INFO: ROC 12 VthrComp = 132
[10:29:18.444] <TB2> INFO: ROC 13 VthrComp = 113
[10:29:18.444] <TB2> INFO: ROC 14 VthrComp = 126
[10:29:18.444] <TB2> INFO: ROC 15 VthrComp = 104
[10:29:18.690] <TB2> INFO: Expecting 41600 events.
[10:29:22.234] <TB2> INFO: 41600 events read in total (2952ms).
[10:29:22.235] <TB2> INFO: Test took 3789ms.
[10:29:22.245] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[10:29:22.245] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:29:22.259] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:29:22.259] <TB2> INFO: run 1 of 1
[10:29:22.541] <TB2> INFO: Expecting 5025280 events.
[10:29:49.161] <TB2> INFO: 590528 events read in total (26029ms).
[10:30:15.477] <TB2> INFO: 1179672 events read in total (52345ms).
[10:30:42.338] <TB2> INFO: 1768808 events read in total (79206ms).
[10:31:08.969] <TB2> INFO: 2356680 events read in total (105837ms).
[10:31:34.733] <TB2> INFO: 2941520 events read in total (131601ms).
[10:32:00.640] <TB2> INFO: 3525232 events read in total (157508ms).
[10:32:27.558] <TB2> INFO: 4108832 events read in total (184426ms).
[10:32:54.211] <TB2> INFO: 4692000 events read in total (211079ms).
[10:33:10.377] <TB2> INFO: 5025280 events read in total (227245ms).
[10:33:10.564] <TB2> INFO: Test took 228306ms.
[10:33:38.690] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 58.8237 for pixel 0/9 mean/min/max = 45.2888/31.6787/58.8989
[10:33:38.691] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 59.9084 for pixel 0/10 mean/min/max = 46.0399/32.0457/60.034
[10:33:38.691] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 58.0275 for pixel 17/78 mean/min/max = 44.7636/31.4301/58.097
[10:33:38.692] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 58.3525 for pixel 8/54 mean/min/max = 45.1036/31.7382/58.4691
[10:33:38.692] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 60.9675 for pixel 0/73 mean/min/max = 46.012/30.8809/61.1431
[10:33:38.693] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 56.3923 for pixel 3/3 mean/min/max = 43.9243/31.4288/56.4199
[10:33:38.693] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 57.554 for pixel 18/2 mean/min/max = 44.5502/31.4025/57.6978
[10:33:38.694] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 59.443 for pixel 0/39 mean/min/max = 46.1672/32.7617/59.5727
[10:33:38.694] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 61.3972 for pixel 0/14 mean/min/max = 45.8142/30.2137/61.4147
[10:33:38.695] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 58.0347 for pixel 0/79 mean/min/max = 44.3805/30.707/58.0539
[10:33:38.695] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 60.3932 for pixel 1/10 mean/min/max = 46.1993/31.9946/60.4041
[10:33:38.696] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 62.2603 for pixel 38/4 mean/min/max = 47.9496/33.6255/62.2738
[10:33:38.696] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 59.7726 for pixel 11/65 mean/min/max = 46.8284/33.878/59.7787
[10:33:38.697] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 59.9241 for pixel 0/73 mean/min/max = 46.2268/32.4383/60.0153
[10:33:38.697] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 63.5085 for pixel 38/79 mean/min/max = 47.0689/30.0278/64.11
[10:33:38.697] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 61.9515 for pixel 1/1 mean/min/max = 48.0265/34.0842/61.9689
[10:33:38.698] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:33:38.787] <TB2> INFO: Expecting 411648 events.
[10:33:48.293] <TB2> INFO: 411648 events read in total (8914ms).
[10:33:48.303] <TB2> INFO: Expecting 411648 events.
[10:33:57.922] <TB2> INFO: 411648 events read in total (9216ms).
[10:33:57.934] <TB2> INFO: Expecting 411648 events.
[10:34:07.087] <TB2> INFO: 411648 events read in total (8750ms).
[10:34:07.100] <TB2> INFO: Expecting 411648 events.
[10:34:16.322] <TB2> INFO: 411648 events read in total (8819ms).
[10:34:16.342] <TB2> INFO: Expecting 411648 events.
[10:34:25.578] <TB2> INFO: 411648 events read in total (8833ms).
[10:34:25.607] <TB2> INFO: Expecting 411648 events.
[10:34:34.764] <TB2> INFO: 411648 events read in total (8754ms).
[10:34:34.787] <TB2> INFO: Expecting 411648 events.
[10:34:44.023] <TB2> INFO: 411648 events read in total (8833ms).
[10:34:44.048] <TB2> INFO: Expecting 411648 events.
[10:34:53.139] <TB2> INFO: 411648 events read in total (8685ms).
[10:34:53.167] <TB2> INFO: Expecting 411648 events.
[10:35:02.276] <TB2> INFO: 411648 events read in total (8706ms).
[10:35:02.306] <TB2> INFO: Expecting 411648 events.
[10:35:11.448] <TB2> INFO: 411648 events read in total (8738ms).
[10:35:11.481] <TB2> INFO: Expecting 411648 events.
[10:35:20.668] <TB2> INFO: 411648 events read in total (8781ms).
[10:35:20.706] <TB2> INFO: Expecting 411648 events.
[10:35:29.852] <TB2> INFO: 411648 events read in total (8743ms).
[10:35:29.890] <TB2> INFO: Expecting 411648 events.
[10:35:39.107] <TB2> INFO: 411648 events read in total (8814ms).
[10:35:39.151] <TB2> INFO: Expecting 411648 events.
[10:35:48.309] <TB2> INFO: 411648 events read in total (8755ms).
[10:35:48.383] <TB2> INFO: Expecting 411648 events.
[10:35:57.595] <TB2> INFO: 411648 events read in total (8809ms).
[10:35:57.669] <TB2> INFO: Expecting 411648 events.
[10:36:06.945] <TB2> INFO: 411648 events read in total (8873ms).
[10:36:07.011] <TB2> INFO: Test took 148314ms.
[10:36:07.886] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[10:36:07.905] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:36:07.905] <TB2> INFO: run 1 of 1
[10:36:08.178] <TB2> INFO: Expecting 5025280 events.
[10:36:34.717] <TB2> INFO: 585144 events read in total (25949ms).
[10:37:00.863] <TB2> INFO: 1169976 events read in total (52094ms).
[10:37:27.519] <TB2> INFO: 1755088 events read in total (78750ms).
[10:37:53.755] <TB2> INFO: 2338168 events read in total (104986ms).
[10:38:20.648] <TB2> INFO: 2922064 events read in total (131880ms).
[10:38:47.443] <TB2> INFO: 3506344 events read in total (158674ms).
[10:39:14.264] <TB2> INFO: 4088304 events read in total (185495ms).
[10:39:41.289] <TB2> INFO: 4671664 events read in total (212520ms).
[10:39:58.689] <TB2> INFO: 5025280 events read in total (229920ms).
[10:39:58.813] <TB2> INFO: Test took 230909ms.
[10:40:24.739] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 9.677028 .. 145.370737
[10:40:24.984] <TB2> INFO: Expecting 208000 events.
[10:40:34.864] <TB2> INFO: 208000 events read in total (9288ms).
[10:40:34.866] <TB2> INFO: Test took 10124ms.
[10:40:34.919] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 9 .. 155 (-1/-1) hits flags = 528 (plus default)
[10:40:34.933] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:40:34.933] <TB2> INFO: run 1 of 1
[10:40:35.211] <TB2> INFO: Expecting 4892160 events.
[10:41:02.477] <TB2> INFO: 573384 events read in total (26674ms).
[10:41:28.638] <TB2> INFO: 1146840 events read in total (52835ms).
[10:41:55.435] <TB2> INFO: 1720288 events read in total (79632ms).
[10:42:21.662] <TB2> INFO: 2292976 events read in total (105859ms).
[10:42:48.158] <TB2> INFO: 2866416 events read in total (132355ms).
[10:43:14.885] <TB2> INFO: 3439336 events read in total (159082ms).
[10:43:41.943] <TB2> INFO: 4011720 events read in total (186140ms).
[10:44:08.860] <TB2> INFO: 4583880 events read in total (213057ms).
[10:44:23.362] <TB2> INFO: 4892160 events read in total (227559ms).
[10:44:23.487] <TB2> INFO: Test took 228555ms.
[10:44:54.387] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.708376 .. 48.063232
[10:44:54.635] <TB2> INFO: Expecting 208000 events.
[10:45:05.418] <TB2> INFO: 208000 events read in total (10191ms).
[10:45:05.419] <TB2> INFO: Test took 11030ms.
[10:45:05.484] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 58 (-1/-1) hits flags = 528 (plus default)
[10:45:05.499] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:45:05.499] <TB2> INFO: run 1 of 1
[10:45:05.813] <TB2> INFO: Expecting 1397760 events.
[10:45:34.471] <TB2> INFO: 646936 events read in total (28065ms).
[10:46:03.146] <TB2> INFO: 1289800 events read in total (56740ms).
[10:46:08.125] <TB2> INFO: 1397760 events read in total (61719ms).
[10:46:08.171] <TB2> INFO: Test took 62673ms.
[10:46:26.065] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 25.444844 .. 45.456022
[10:46:26.306] <TB2> INFO: Expecting 208000 events.
[10:46:36.531] <TB2> INFO: 208000 events read in total (9634ms).
[10:46:36.532] <TB2> INFO: Test took 10465ms.
[10:46:36.580] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[10:46:36.593] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:46:36.593] <TB2> INFO: run 1 of 1
[10:46:36.876] <TB2> INFO: Expecting 1364480 events.
[10:47:06.188] <TB2> INFO: 666568 events read in total (28720ms).
[10:47:35.449] <TB2> INFO: 1333072 events read in total (57983ms).
[10:47:37.186] <TB2> INFO: 1364480 events read in total (59718ms).
[10:47:37.217] <TB2> INFO: Test took 60624ms.
[10:47:54.621] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 22.933579 .. 45.089359
[10:47:54.865] <TB2> INFO: Expecting 208000 events.
[10:48:05.222] <TB2> INFO: 208000 events read in total (9765ms).
[10:48:05.223] <TB2> INFO: Test took 10601ms.
[10:48:05.287] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 12 .. 55 (-1/-1) hits flags = 528 (plus default)
[10:48:05.302] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:48:05.302] <TB2> INFO: run 1 of 1
[10:48:05.585] <TB2> INFO: Expecting 1464320 events.
[10:48:35.027] <TB2> INFO: 681880 events read in total (28850ms).
[10:49:03.925] <TB2> INFO: 1361336 events read in total (57748ms).
[10:49:08.836] <TB2> INFO: 1464320 events read in total (62659ms).
[10:49:08.865] <TB2> INFO: Test took 63564ms.
[10:49:25.054] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[10:49:25.054] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[10:49:25.069] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:49:25.069] <TB2> INFO: run 1 of 1
[10:49:25.319] <TB2> INFO: Expecting 1364480 events.
[10:49:54.767] <TB2> INFO: 666456 events read in total (28856ms).
[10:50:23.207] <TB2> INFO: 1331240 events read in total (57296ms).
[10:50:25.134] <TB2> INFO: 1364480 events read in total (59223ms).
[10:50:25.168] <TB2> INFO: Test took 60099ms.
[10:50:42.182] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C0.dat
[10:50:42.182] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C1.dat
[10:50:42.182] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C2.dat
[10:50:42.182] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C3.dat
[10:50:42.182] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C4.dat
[10:50:42.183] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C5.dat
[10:50:42.183] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C6.dat
[10:50:42.183] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C7.dat
[10:50:42.183] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C8.dat
[10:50:42.183] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C9.dat
[10:50:42.183] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C10.dat
[10:50:42.183] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C11.dat
[10:50:42.183] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C12.dat
[10:50:42.183] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C13.dat
[10:50:42.183] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C14.dat
[10:50:42.183] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C15.dat
[10:50:42.184] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C0.dat
[10:50:42.191] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C1.dat
[10:50:42.198] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C2.dat
[10:50:42.206] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C3.dat
[10:50:42.212] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C4.dat
[10:50:42.219] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C5.dat
[10:50:42.226] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C6.dat
[10:50:42.233] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C7.dat
[10:50:42.240] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C8.dat
[10:50:42.246] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C9.dat
[10:50:42.252] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C10.dat
[10:50:42.259] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C11.dat
[10:50:42.264] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C12.dat
[10:50:42.270] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C13.dat
[10:50:42.277] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C14.dat
[10:50:42.283] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//trimParameters35_C15.dat
[10:50:42.288] <TB2> INFO: PixTestTrim::trimTest() done
[10:50:42.288] <TB2> INFO: vtrim: 132 119 123 127 127 115 145 119 127 125 120 132 139 128 138 118
[10:50:42.288] <TB2> INFO: vthrcomp: 122 126 131 117 125 131 131 103 124 127 122 103 132 113 126 104
[10:50:42.288] <TB2> INFO: vcal mean: 34.80 34.85 34.78 34.84 34.77 34.81 34.79 34.81 34.79 34.77 34.84 34.78 34.86 34.83 34.87 34.83
[10:50:42.288] <TB2> INFO: vcal RMS: 0.98 0.96 1.01 0.97 1.04 0.96 1.14 0.92 1.07 1.05 1.03 1.08 1.00 0.96 1.09 0.94
[10:50:42.289] <TB2> INFO: bits mean: 9.35 8.97 9.79 9.87 9.47 10.04 10.54 9.14 9.29 9.40 9.01 9.34 8.92 8.90 9.44 8.53
[10:50:42.289] <TB2> INFO: bits RMS: 2.78 2.89 2.63 2.52 2.82 2.59 2.30 2.70 3.00 2.98 2.85 2.48 2.58 2.88 2.90 2.65
[10:50:42.296] <TB2> INFO: ----------------------------------------------------------------------
[10:50:42.296] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[10:50:42.296] <TB2> INFO: ----------------------------------------------------------------------
[10:50:42.299] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[10:50:42.313] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[10:50:42.313] <TB2> INFO: run 1 of 1
[10:50:42.554] <TB2> INFO: Expecting 4160000 events.
[10:51:15.510] <TB2> INFO: 748605 events read in total (32364ms).
[10:51:47.113] <TB2> INFO: 1490130 events read in total (63967ms).
[10:52:19.429] <TB2> INFO: 2230560 events read in total (96283ms).
[10:52:51.530] <TB2> INFO: 2968175 events read in total (128384ms).
[10:53:23.970] <TB2> INFO: 3701130 events read in total (160824ms).
[10:53:44.441] <TB2> INFO: 4160000 events read in total (181295ms).
[10:53:44.558] <TB2> INFO: Test took 182245ms.
[10:54:17.095] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[10:54:17.111] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[10:54:17.112] <TB2> INFO: run 1 of 1
[10:54:17.359] <TB2> INFO: Expecting 4284800 events.
[10:54:49.605] <TB2> INFO: 716360 events read in total (31654ms).
[10:55:21.473] <TB2> INFO: 1427500 events read in total (63522ms).
[10:55:52.947] <TB2> INFO: 2135725 events read in total (94996ms).
[10:56:23.963] <TB2> INFO: 2841205 events read in total (126012ms).
[10:56:55.087] <TB2> INFO: 3544665 events read in total (157136ms).
[10:57:26.884] <TB2> INFO: 4248590 events read in total (188933ms).
[10:57:28.851] <TB2> INFO: 4284800 events read in total (190900ms).
[10:57:28.965] <TB2> INFO: Test took 191853ms.
[10:58:05.910] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 189 (-1/-1) hits flags = 528 (plus default)
[10:58:05.924] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[10:58:05.925] <TB2> INFO: run 1 of 1
[10:58:06.164] <TB2> INFO: Expecting 3952000 events.
[10:58:39.173] <TB2> INFO: 741095 events read in total (32418ms).
[10:59:11.561] <TB2> INFO: 1475675 events read in total (64806ms).
[10:59:43.446] <TB2> INFO: 2206045 events read in total (96691ms).
[11:00:15.316] <TB2> INFO: 2932390 events read in total (128561ms).
[11:00:48.112] <TB2> INFO: 3655225 events read in total (161357ms).
[11:01:02.560] <TB2> INFO: 3952000 events read in total (175805ms).
[11:01:02.651] <TB2> INFO: Test took 176726ms.
[11:01:31.997] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 191 (-1/-1) hits flags = 528 (plus default)
[11:01:32.008] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:01:32.009] <TB2> INFO: run 1 of 1
[11:01:32.352] <TB2> INFO: Expecting 3993600 events.
[11:02:05.273] <TB2> INFO: 735350 events read in total (32329ms).
[11:02:36.804] <TB2> INFO: 1464690 events read in total (63860ms).
[11:03:09.333] <TB2> INFO: 2190655 events read in total (96389ms).
[11:03:40.616] <TB2> INFO: 2914045 events read in total (127672ms).
[11:04:13.046] <TB2> INFO: 3633845 events read in total (160102ms).
[11:04:29.706] <TB2> INFO: 3993600 events read in total (176762ms).
[11:04:29.810] <TB2> INFO: Test took 177801ms.
[11:04:59.495] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 189 (-1/-1) hits flags = 528 (plus default)
[11:04:59.510] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:04:59.510] <TB2> INFO: run 1 of 1
[11:04:59.792] <TB2> INFO: Expecting 3952000 events.
[11:05:31.712] <TB2> INFO: 738735 events read in total (31328ms).
[11:06:03.416] <TB2> INFO: 1471170 events read in total (63032ms).
[11:06:35.441] <TB2> INFO: 2200310 events read in total (95057ms).
[11:07:07.317] <TB2> INFO: 2926085 events read in total (126933ms).
[11:07:40.698] <TB2> INFO: 3650735 events read in total (160314ms).
[11:07:54.562] <TB2> INFO: 3952000 events read in total (174178ms).
[11:07:54.668] <TB2> INFO: Test took 175158ms.
[11:08:23.189] <TB2> INFO: PixTestTrim::trimBitTest() done
[11:08:23.190] <TB2> INFO: PixTestTrim::doTest() done, duration: 2555 seconds
[11:08:23.190] <TB2> INFO: Decoding statistics:
[11:08:23.190] <TB2> INFO: General information:
[11:08:23.190] <TB2> INFO: 16bit words read: 0
[11:08:23.190] <TB2> INFO: valid events total: 0
[11:08:23.190] <TB2> INFO: empty events: 0
[11:08:23.190] <TB2> INFO: valid events with pixels: 0
[11:08:23.190] <TB2> INFO: valid pixel hits: 0
[11:08:23.190] <TB2> INFO: Event errors: 0
[11:08:23.190] <TB2> INFO: start marker: 0
[11:08:23.190] <TB2> INFO: stop marker: 0
[11:08:23.190] <TB2> INFO: overflow: 0
[11:08:23.190] <TB2> INFO: invalid 5bit words: 0
[11:08:23.190] <TB2> INFO: invalid XOR eye diagram: 0
[11:08:23.190] <TB2> INFO: frame (failed synchr.): 0
[11:08:23.190] <TB2> INFO: idle data (no TBM trl): 0
[11:08:23.190] <TB2> INFO: no data (only TBM hdr): 0
[11:08:23.191] <TB2> INFO: TBM errors: 0
[11:08:23.191] <TB2> INFO: flawed TBM headers: 0
[11:08:23.191] <TB2> INFO: flawed TBM trailers: 0
[11:08:23.191] <TB2> INFO: event ID mismatches: 0
[11:08:23.191] <TB2> INFO: ROC errors: 0
[11:08:23.191] <TB2> INFO: missing ROC header(s): 0
[11:08:23.191] <TB2> INFO: misplaced readback start: 0
[11:08:23.191] <TB2> INFO: Pixel decoding errors: 0
[11:08:23.191] <TB2> INFO: pixel data incomplete: 0
[11:08:23.191] <TB2> INFO: pixel address: 0
[11:08:23.191] <TB2> INFO: pulse height fill bit: 0
[11:08:23.191] <TB2> INFO: buffer corruption: 0
[11:08:23.806] <TB2> INFO: ######################################################################
[11:08:23.806] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[11:08:23.806] <TB2> INFO: ######################################################################
[11:08:24.072] <TB2> INFO: Expecting 41600 events.
[11:08:27.520] <TB2> INFO: 41600 events read in total (2856ms).
[11:08:27.521] <TB2> INFO: Test took 3713ms.
[11:08:28.016] <TB2> INFO: Expecting 41600 events.
[11:08:31.566] <TB2> INFO: 41600 events read in total (2958ms).
[11:08:31.567] <TB2> INFO: Test took 3843ms.
[11:08:31.856] <TB2> INFO: Expecting 41600 events.
[11:08:35.324] <TB2> INFO: 41600 events read in total (2876ms).
[11:08:35.325] <TB2> INFO: Test took 3734ms.
[11:08:35.617] <TB2> INFO: Expecting 41600 events.
[11:08:39.090] <TB2> INFO: 41600 events read in total (2881ms).
[11:08:39.091] <TB2> INFO: Test took 3739ms.
[11:08:39.380] <TB2> INFO: Expecting 41600 events.
[11:08:42.868] <TB2> INFO: 41600 events read in total (2896ms).
[11:08:42.869] <TB2> INFO: Test took 3754ms.
[11:08:43.158] <TB2> INFO: Expecting 41600 events.
[11:08:46.685] <TB2> INFO: 41600 events read in total (2935ms).
[11:08:46.686] <TB2> INFO: Test took 3793ms.
[11:08:46.975] <TB2> INFO: Expecting 41600 events.
[11:08:50.508] <TB2> INFO: 41600 events read in total (2941ms).
[11:08:50.509] <TB2> INFO: Test took 3799ms.
[11:08:50.798] <TB2> INFO: Expecting 41600 events.
[11:08:54.275] <TB2> INFO: 41600 events read in total (2886ms).
[11:08:54.276] <TB2> INFO: Test took 3743ms.
[11:08:54.565] <TB2> INFO: Expecting 41600 events.
[11:08:58.116] <TB2> INFO: 41600 events read in total (2959ms).
[11:08:58.117] <TB2> INFO: Test took 3817ms.
[11:08:58.460] <TB2> INFO: Expecting 41600 events.
[11:09:02.326] <TB2> INFO: 41600 events read in total (3275ms).
[11:09:02.327] <TB2> INFO: Test took 4186ms.
[11:09:02.621] <TB2> INFO: Expecting 41600 events.
[11:09:06.160] <TB2> INFO: 41600 events read in total (2948ms).
[11:09:06.161] <TB2> INFO: Test took 3805ms.
[11:09:06.452] <TB2> INFO: Expecting 41600 events.
[11:09:10.007] <TB2> INFO: 41600 events read in total (2963ms).
[11:09:10.008] <TB2> INFO: Test took 3821ms.
[11:09:10.297] <TB2> INFO: Expecting 41600 events.
[11:09:13.787] <TB2> INFO: 41600 events read in total (2899ms).
[11:09:13.789] <TB2> INFO: Test took 3757ms.
[11:09:14.081] <TB2> INFO: Expecting 41600 events.
[11:09:17.611] <TB2> INFO: 41600 events read in total (2938ms).
[11:09:17.612] <TB2> INFO: Test took 3796ms.
[11:09:17.905] <TB2> INFO: Expecting 41600 events.
[11:09:21.411] <TB2> INFO: 41600 events read in total (2915ms).
[11:09:21.412] <TB2> INFO: Test took 3772ms.
[11:09:21.705] <TB2> INFO: Expecting 41600 events.
[11:09:25.259] <TB2> INFO: 41600 events read in total (2963ms).
[11:09:25.261] <TB2> INFO: Test took 3821ms.
[11:09:25.550] <TB2> INFO: Expecting 41600 events.
[11:09:29.128] <TB2> INFO: 41600 events read in total (2986ms).
[11:09:29.129] <TB2> INFO: Test took 3845ms.
[11:09:29.420] <TB2> INFO: Expecting 41600 events.
[11:09:32.991] <TB2> INFO: 41600 events read in total (2980ms).
[11:09:32.992] <TB2> INFO: Test took 3837ms.
[11:09:33.288] <TB2> INFO: Expecting 41600 events.
[11:09:36.968] <TB2> INFO: 41600 events read in total (3088ms).
[11:09:36.969] <TB2> INFO: Test took 3946ms.
[11:09:37.258] <TB2> INFO: Expecting 41600 events.
[11:09:40.920] <TB2> INFO: 41600 events read in total (3071ms).
[11:09:40.921] <TB2> INFO: Test took 3928ms.
[11:09:41.213] <TB2> INFO: Expecting 41600 events.
[11:09:44.715] <TB2> INFO: 41600 events read in total (2910ms).
[11:09:44.716] <TB2> INFO: Test took 3768ms.
[11:09:45.120] <TB2> INFO: Expecting 41600 events.
[11:09:48.624] <TB2> INFO: 41600 events read in total (2912ms).
[11:09:48.625] <TB2> INFO: Test took 3878ms.
[11:09:48.990] <TB2> INFO: Expecting 41600 events.
[11:09:52.487] <TB2> INFO: 41600 events read in total (2905ms).
[11:09:52.488] <TB2> INFO: Test took 3839ms.
[11:09:52.778] <TB2> INFO: Expecting 41600 events.
[11:09:56.281] <TB2> INFO: 41600 events read in total (2912ms).
[11:09:56.282] <TB2> INFO: Test took 3769ms.
[11:09:56.571] <TB2> INFO: Expecting 41600 events.
[11:10:00.039] <TB2> INFO: 41600 events read in total (2876ms).
[11:10:00.040] <TB2> INFO: Test took 3734ms.
[11:10:00.329] <TB2> INFO: Expecting 41600 events.
[11:10:03.835] <TB2> INFO: 41600 events read in total (2914ms).
[11:10:03.836] <TB2> INFO: Test took 3772ms.
[11:10:04.126] <TB2> INFO: Expecting 41600 events.
[11:10:07.608] <TB2> INFO: 41600 events read in total (2891ms).
[11:10:07.609] <TB2> INFO: Test took 3748ms.
[11:10:07.898] <TB2> INFO: Expecting 41600 events.
[11:10:11.370] <TB2> INFO: 41600 events read in total (2881ms).
[11:10:11.370] <TB2> INFO: Test took 3737ms.
[11:10:11.712] <TB2> INFO: Expecting 41600 events.
[11:10:15.191] <TB2> INFO: 41600 events read in total (2886ms).
[11:10:15.192] <TB2> INFO: Test took 3797ms.
[11:10:15.481] <TB2> INFO: Expecting 41600 events.
[11:10:18.997] <TB2> INFO: 41600 events read in total (2924ms).
[11:10:18.997] <TB2> INFO: Test took 3780ms.
[11:10:19.287] <TB2> INFO: Expecting 41600 events.
[11:10:22.757] <TB2> INFO: 41600 events read in total (2878ms).
[11:10:22.758] <TB2> INFO: Test took 3736ms.
[11:10:23.050] <TB2> INFO: Expecting 41600 events.
[11:10:26.540] <TB2> INFO: 41600 events read in total (2899ms).
[11:10:26.541] <TB2> INFO: Test took 3756ms.
[11:10:26.830] <TB2> INFO: Expecting 41600 events.
[11:10:30.340] <TB2> INFO: 41600 events read in total (2918ms).
[11:10:30.342] <TB2> INFO: Test took 3777ms.
[11:10:30.631] <TB2> INFO: Expecting 41600 events.
[11:10:34.132] <TB2> INFO: 41600 events read in total (2908ms).
[11:10:34.133] <TB2> INFO: Test took 3766ms.
[11:10:34.422] <TB2> INFO: Expecting 41600 events.
[11:10:38.054] <TB2> INFO: 41600 events read in total (3040ms).
[11:10:38.056] <TB2> INFO: Test took 3898ms.
[11:10:38.348] <TB2> INFO: Expecting 41600 events.
[11:10:41.996] <TB2> INFO: 41600 events read in total (3056ms).
[11:10:41.997] <TB2> INFO: Test took 3914ms.
[11:10:42.289] <TB2> INFO: Expecting 41600 events.
[11:10:46.051] <TB2> INFO: 41600 events read in total (3170ms).
[11:10:46.051] <TB2> INFO: Test took 4028ms.
[11:10:46.401] <TB2> INFO: Expecting 41600 events.
[11:10:49.897] <TB2> INFO: 41600 events read in total (2904ms).
[11:10:49.898] <TB2> INFO: Test took 3819ms.
[11:10:50.289] <TB2> INFO: Expecting 41600 events.
[11:10:53.801] <TB2> INFO: 41600 events read in total (2920ms).
[11:10:53.802] <TB2> INFO: Test took 3873ms.
[11:10:54.092] <TB2> INFO: Expecting 41600 events.
[11:10:57.571] <TB2> INFO: 41600 events read in total (2887ms).
[11:10:57.572] <TB2> INFO: Test took 3745ms.
[11:10:57.861] <TB2> INFO: Expecting 41600 events.
[11:11:01.429] <TB2> INFO: 41600 events read in total (2976ms).
[11:11:01.430] <TB2> INFO: Test took 3833ms.
[11:11:01.722] <TB2> INFO: Expecting 41600 events.
[11:11:05.249] <TB2> INFO: 41600 events read in total (2935ms).
[11:11:05.249] <TB2> INFO: Test took 3792ms.
[11:11:05.539] <TB2> INFO: Expecting 41600 events.
[11:11:09.232] <TB2> INFO: 41600 events read in total (3101ms).
[11:11:09.233] <TB2> INFO: Test took 3959ms.
[11:11:09.521] <TB2> INFO: Expecting 41600 events.
[11:11:13.123] <TB2> INFO: 41600 events read in total (3010ms).
[11:11:13.124] <TB2> INFO: Test took 3867ms.
[11:11:13.413] <TB2> INFO: Expecting 41600 events.
[11:11:17.006] <TB2> INFO: 41600 events read in total (3001ms).
[11:11:17.007] <TB2> INFO: Test took 3858ms.
[11:11:17.297] <TB2> INFO: Expecting 41600 events.
[11:11:20.003] <TB2> INFO: 41600 events read in total (3114ms).
[11:11:21.004] <TB2> INFO: Test took 3972ms.
[11:11:21.294] <TB2> INFO: Expecting 41600 events.
[11:11:24.841] <TB2> INFO: 41600 events read in total (2956ms).
[11:11:24.842] <TB2> INFO: Test took 3813ms.
[11:11:25.131] <TB2> INFO: Expecting 41600 events.
[11:11:28.726] <TB2> INFO: 41600 events read in total (3003ms).
[11:11:28.727] <TB2> INFO: Test took 3861ms.
[11:11:29.018] <TB2> INFO: Expecting 41600 events.
[11:11:32.830] <TB2> INFO: 41600 events read in total (3221ms).
[11:11:32.831] <TB2> INFO: Test took 4078ms.
[11:11:33.120] <TB2> INFO: Expecting 41600 events.
[11:11:36.673] <TB2> INFO: 41600 events read in total (2961ms).
[11:11:36.674] <TB2> INFO: Test took 3818ms.
[11:11:36.963] <TB2> INFO: Expecting 41600 events.
[11:11:40.481] <TB2> INFO: 41600 events read in total (2925ms).
[11:11:40.482] <TB2> INFO: Test took 3783ms.
[11:11:40.774] <TB2> INFO: Expecting 41600 events.
[11:11:44.247] <TB2> INFO: 41600 events read in total (2882ms).
[11:11:44.248] <TB2> INFO: Test took 3739ms.
[11:11:44.538] <TB2> INFO: Expecting 41600 events.
[11:11:48.153] <TB2> INFO: 41600 events read in total (3022ms).
[11:11:48.154] <TB2> INFO: Test took 3881ms.
[11:11:48.450] <TB2> INFO: Expecting 41600 events.
[11:11:51.995] <TB2> INFO: 41600 events read in total (2953ms).
[11:11:51.996] <TB2> INFO: Test took 3797ms.
[11:11:52.286] <TB2> INFO: Expecting 2560 events.
[11:11:53.171] <TB2> INFO: 2560 events read in total (293ms).
[11:11:53.171] <TB2> INFO: Test took 1162ms.
[11:11:53.479] <TB2> INFO: Expecting 2560 events.
[11:11:54.366] <TB2> INFO: 2560 events read in total (296ms).
[11:11:54.366] <TB2> INFO: Test took 1194ms.
[11:11:54.674] <TB2> INFO: Expecting 2560 events.
[11:11:55.561] <TB2> INFO: 2560 events read in total (295ms).
[11:11:55.561] <TB2> INFO: Test took 1194ms.
[11:11:55.869] <TB2> INFO: Expecting 2560 events.
[11:11:56.753] <TB2> INFO: 2560 events read in total (292ms).
[11:11:56.753] <TB2> INFO: Test took 1191ms.
[11:11:57.061] <TB2> INFO: Expecting 2560 events.
[11:11:57.942] <TB2> INFO: 2560 events read in total (290ms).
[11:11:57.943] <TB2> INFO: Test took 1189ms.
[11:11:58.254] <TB2> INFO: Expecting 2560 events.
[11:11:59.136] <TB2> INFO: 2560 events read in total (291ms).
[11:11:59.137] <TB2> INFO: Test took 1194ms.
[11:11:59.445] <TB2> INFO: Expecting 2560 events.
[11:12:00.323] <TB2> INFO: 2560 events read in total (287ms).
[11:12:00.324] <TB2> INFO: Test took 1187ms.
[11:12:00.632] <TB2> INFO: Expecting 2560 events.
[11:12:01.512] <TB2> INFO: 2560 events read in total (288ms).
[11:12:01.512] <TB2> INFO: Test took 1188ms.
[11:12:01.820] <TB2> INFO: Expecting 2560 events.
[11:12:02.698] <TB2> INFO: 2560 events read in total (286ms).
[11:12:02.698] <TB2> INFO: Test took 1185ms.
[11:12:03.006] <TB2> INFO: Expecting 2560 events.
[11:12:03.896] <TB2> INFO: 2560 events read in total (298ms).
[11:12:03.896] <TB2> INFO: Test took 1197ms.
[11:12:04.203] <TB2> INFO: Expecting 2560 events.
[11:12:05.083] <TB2> INFO: 2560 events read in total (288ms).
[11:12:05.083] <TB2> INFO: Test took 1187ms.
[11:12:05.391] <TB2> INFO: Expecting 2560 events.
[11:12:06.271] <TB2> INFO: 2560 events read in total (289ms).
[11:12:06.271] <TB2> INFO: Test took 1188ms.
[11:12:06.579] <TB2> INFO: Expecting 2560 events.
[11:12:07.469] <TB2> INFO: 2560 events read in total (298ms).
[11:12:07.469] <TB2> INFO: Test took 1198ms.
[11:12:07.776] <TB2> INFO: Expecting 2560 events.
[11:12:08.664] <TB2> INFO: 2560 events read in total (296ms).
[11:12:08.664] <TB2> INFO: Test took 1195ms.
[11:12:08.972] <TB2> INFO: Expecting 2560 events.
[11:12:09.858] <TB2> INFO: 2560 events read in total (294ms).
[11:12:09.858] <TB2> INFO: Test took 1193ms.
[11:12:10.165] <TB2> INFO: Expecting 2560 events.
[11:12:11.048] <TB2> INFO: 2560 events read in total (291ms).
[11:12:11.049] <TB2> INFO: Test took 1190ms.
[11:12:11.358] <TB2> INFO: Expecting 655360 events.
[11:12:32.037] <TB2> INFO: 531260 events read in total (20088ms).
[11:12:36.968] <TB2> INFO: 655360 events read in total (25019ms).
[11:12:36.985] <TB2> INFO: Test took 25933ms.
[11:12:37.019] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:12:37.274] <TB2> INFO: Expecting 655360 events.
[11:12:51.840] <TB2> INFO: 655360 events read in total (13974ms).
[11:12:51.857] <TB2> INFO: Expecting 655360 events.
[11:13:06.040] <TB2> INFO: 655360 events read in total (13780ms).
[11:13:06.057] <TB2> INFO: Expecting 655360 events.
[11:13:20.321] <TB2> INFO: 655360 events read in total (13861ms).
[11:13:20.345] <TB2> INFO: Expecting 655360 events.
[11:13:34.578] <TB2> INFO: 655360 events read in total (13830ms).
[11:13:34.603] <TB2> INFO: Expecting 655360 events.
[11:13:48.780] <TB2> INFO: 655360 events read in total (13774ms).
[11:13:48.809] <TB2> INFO: Expecting 655360 events.
[11:14:03.134] <TB2> INFO: 655360 events read in total (13922ms).
[11:14:03.177] <TB2> INFO: Expecting 655360 events.
[11:14:17.461] <TB2> INFO: 655360 events read in total (13881ms).
[11:14:17.510] <TB2> INFO: Expecting 655360 events.
[11:14:31.635] <TB2> INFO: 655360 events read in total (13722ms).
[11:14:31.677] <TB2> INFO: Expecting 655360 events.
[11:14:45.912] <TB2> INFO: 655360 events read in total (13832ms).
[11:14:45.990] <TB2> INFO: Expecting 655360 events.
[11:15:00.271] <TB2> INFO: 655360 events read in total (13877ms).
[11:15:00.338] <TB2> INFO: Expecting 655360 events.
[11:15:14.372] <TB2> INFO: 655360 events read in total (13631ms).
[11:15:14.444] <TB2> INFO: Expecting 655360 events.
[11:15:28.680] <TB2> INFO: 655360 events read in total (13832ms).
[11:15:28.762] <TB2> INFO: Expecting 655360 events.
[11:15:43.101] <TB2> INFO: 655360 events read in total (13935ms).
[11:15:43.193] <TB2> INFO: Expecting 655360 events.
[11:15:57.362] <TB2> INFO: 655360 events read in total (13766ms).
[11:15:57.491] <TB2> INFO: Expecting 655360 events.
[11:16:12.004] <TB2> INFO: 655360 events read in total (14110ms).
[11:16:12.155] <TB2> INFO: Expecting 655360 events.
[11:16:26.473] <TB2> INFO: 655360 events read in total (13915ms).
[11:16:26.580] <TB2> INFO: Test took 229562ms.
[11:16:26.812] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:26.820] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:26.829] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:16:26.838] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:16:26.846] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[11:16:26.855] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[11:16:26.864] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[11:16:26.872] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:26.881] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:16:26.889] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:16:26.899] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[11:16:26.908] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[11:16:26.916] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[11:16:26.924] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[11:16:26.932] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:26.940] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:26.948] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:26.955] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:16:26.963] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:16:26.970] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[11:16:26.978] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[11:16:26.986] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[11:16:26.994] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[11:16:26.001] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[11:16:27.009] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[11:16:27.019] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:27.028] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:27.036] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:27.044] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:16:27.051] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:16:27.059] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:27.067] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:27.075] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:16:27.083] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:16:27.091] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[11:16:27.098] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[11:16:27.103] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[11:16:27.109] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[11:16:27.115] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[11:16:27.121] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[11:16:27.128] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[11:16:27.133] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[11:16:27.139] <TB2> INFO: safety margin for low PH: adding 11, margin is now 31
[11:16:27.145] <TB2> INFO: safety margin for low PH: adding 12, margin is now 32
[11:16:27.150] <TB2> INFO: safety margin for low PH: adding 13, margin is now 33
[11:16:27.157] <TB2> INFO: safety margin for low PH: adding 14, margin is now 34
[11:16:27.163] <TB2> INFO: safety margin for low PH: adding 15, margin is now 35
[11:16:27.168] <TB2> INFO: safety margin for low PH: adding 16, margin is now 36
[11:16:27.175] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:27.181] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:27.186] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:16:27.193] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:27.199] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:27.204] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:16:27.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C0.dat
[11:16:27.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C1.dat
[11:16:27.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C2.dat
[11:16:27.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C3.dat
[11:16:27.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C4.dat
[11:16:27.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C5.dat
[11:16:27.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C6.dat
[11:16:27.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C7.dat
[11:16:27.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C8.dat
[11:16:27.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C9.dat
[11:16:27.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C10.dat
[11:16:27.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C11.dat
[11:16:27.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C12.dat
[11:16:27.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C13.dat
[11:16:27.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C14.dat
[11:16:27.242] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//dacParameters35_C15.dat
[11:16:27.505] <TB2> INFO: Expecting 41600 events.
[11:16:30.675] <TB2> INFO: 41600 events read in total (2579ms).
[11:16:30.675] <TB2> INFO: Test took 3430ms.
[11:16:31.122] <TB2> INFO: Expecting 41600 events.
[11:16:34.223] <TB2> INFO: 41600 events read in total (2509ms).
[11:16:34.224] <TB2> INFO: Test took 3338ms.
[11:16:34.672] <TB2> INFO: Expecting 41600 events.
[11:16:37.807] <TB2> INFO: 41600 events read in total (2544ms).
[11:16:37.807] <TB2> INFO: Test took 3373ms.
[11:16:38.023] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:38.111] <TB2> INFO: Expecting 2560 events.
[11:16:38.996] <TB2> INFO: 2560 events read in total (293ms).
[11:16:38.996] <TB2> INFO: Test took 973ms.
[11:16:38.999] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:39.305] <TB2> INFO: Expecting 2560 events.
[11:16:40.194] <TB2> INFO: 2560 events read in total (298ms).
[11:16:40.194] <TB2> INFO: Test took 1195ms.
[11:16:40.198] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:40.502] <TB2> INFO: Expecting 2560 events.
[11:16:41.396] <TB2> INFO: 2560 events read in total (302ms).
[11:16:41.396] <TB2> INFO: Test took 1198ms.
[11:16:41.400] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:41.705] <TB2> INFO: Expecting 2560 events.
[11:16:42.589] <TB2> INFO: 2560 events read in total (292ms).
[11:16:42.590] <TB2> INFO: Test took 1191ms.
[11:16:42.593] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:42.897] <TB2> INFO: Expecting 2560 events.
[11:16:43.782] <TB2> INFO: 2560 events read in total (293ms).
[11:16:43.782] <TB2> INFO: Test took 1189ms.
[11:16:43.785] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:44.090] <TB2> INFO: Expecting 2560 events.
[11:16:44.973] <TB2> INFO: 2560 events read in total (291ms).
[11:16:44.974] <TB2> INFO: Test took 1190ms.
[11:16:44.976] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:45.282] <TB2> INFO: Expecting 2560 events.
[11:16:46.165] <TB2> INFO: 2560 events read in total (292ms).
[11:16:46.165] <TB2> INFO: Test took 1189ms.
[11:16:46.168] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:46.474] <TB2> INFO: Expecting 2560 events.
[11:16:47.366] <TB2> INFO: 2560 events read in total (300ms).
[11:16:47.366] <TB2> INFO: Test took 1198ms.
[11:16:47.376] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:47.674] <TB2> INFO: Expecting 2560 events.
[11:16:48.553] <TB2> INFO: 2560 events read in total (287ms).
[11:16:48.553] <TB2> INFO: Test took 1177ms.
[11:16:48.557] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:48.866] <TB2> INFO: Expecting 2560 events.
[11:16:49.747] <TB2> INFO: 2560 events read in total (288ms).
[11:16:49.747] <TB2> INFO: Test took 1190ms.
[11:16:49.749] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:50.056] <TB2> INFO: Expecting 2560 events.
[11:16:50.934] <TB2> INFO: 2560 events read in total (287ms).
[11:16:50.934] <TB2> INFO: Test took 1185ms.
[11:16:50.937] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:51.242] <TB2> INFO: Expecting 2560 events.
[11:16:52.127] <TB2> INFO: 2560 events read in total (293ms).
[11:16:52.127] <TB2> INFO: Test took 1190ms.
[11:16:52.130] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:52.436] <TB2> INFO: Expecting 2560 events.
[11:16:53.321] <TB2> INFO: 2560 events read in total (292ms).
[11:16:53.322] <TB2> INFO: Test took 1192ms.
[11:16:53.324] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:53.630] <TB2> INFO: Expecting 2560 events.
[11:16:54.514] <TB2> INFO: 2560 events read in total (292ms).
[11:16:54.514] <TB2> INFO: Test took 1190ms.
[11:16:54.516] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:54.823] <TB2> INFO: Expecting 2560 events.
[11:16:55.707] <TB2> INFO: 2560 events read in total (293ms).
[11:16:55.707] <TB2> INFO: Test took 1191ms.
[11:16:55.710] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:56.016] <TB2> INFO: Expecting 2560 events.
[11:16:56.893] <TB2> INFO: 2560 events read in total (285ms).
[11:16:56.893] <TB2> INFO: Test took 1184ms.
[11:16:56.896] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:57.212] <TB2> INFO: Expecting 2560 events.
[11:16:58.093] <TB2> INFO: 2560 events read in total (289ms).
[11:16:58.094] <TB2> INFO: Test took 1199ms.
[11:16:58.096] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:58.402] <TB2> INFO: Expecting 2560 events.
[11:16:59.281] <TB2> INFO: 2560 events read in total (288ms).
[11:16:59.281] <TB2> INFO: Test took 1185ms.
[11:16:59.284] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:59.590] <TB2> INFO: Expecting 2560 events.
[11:17:00.474] <TB2> INFO: 2560 events read in total (293ms).
[11:17:00.475] <TB2> INFO: Test took 1192ms.
[11:17:00.477] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:17:00.783] <TB2> INFO: Expecting 2560 events.
[11:17:01.662] <TB2> INFO: 2560 events read in total (288ms).
[11:17:01.662] <TB2> INFO: Test took 1185ms.
[11:17:01.664] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:17:01.971] <TB2> INFO: Expecting 2560 events.
[11:17:02.852] <TB2> INFO: 2560 events read in total (289ms).
[11:17:02.852] <TB2> INFO: Test took 1188ms.
[11:17:02.854] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:17:03.161] <TB2> INFO: Expecting 2560 events.
[11:17:04.056] <TB2> INFO: 2560 events read in total (295ms).
[11:17:04.056] <TB2> INFO: Test took 1202ms.
[11:17:04.059] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:17:04.364] <TB2> INFO: Expecting 2560 events.
[11:17:05.244] <TB2> INFO: 2560 events read in total (289ms).
[11:17:05.245] <TB2> INFO: Test took 1186ms.
[11:17:05.250] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:17:05.553] <TB2> INFO: Expecting 2560 events.
[11:17:06.432] <TB2> INFO: 2560 events read in total (287ms).
[11:17:06.433] <TB2> INFO: Test took 1183ms.
[11:17:06.435] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:17:06.744] <TB2> INFO: Expecting 2560 events.
[11:17:07.628] <TB2> INFO: 2560 events read in total (292ms).
[11:17:07.628] <TB2> INFO: Test took 1193ms.
[11:17:07.632] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:17:07.937] <TB2> INFO: Expecting 2560 events.
[11:17:08.821] <TB2> INFO: 2560 events read in total (292ms).
[11:17:08.821] <TB2> INFO: Test took 1189ms.
[11:17:08.823] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:17:09.130] <TB2> INFO: Expecting 2560 events.
[11:17:10.030] <TB2> INFO: 2560 events read in total (309ms).
[11:17:10.030] <TB2> INFO: Test took 1207ms.
[11:17:10.033] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:17:10.338] <TB2> INFO: Expecting 2560 events.
[11:17:11.225] <TB2> INFO: 2560 events read in total (295ms).
[11:17:11.225] <TB2> INFO: Test took 1192ms.
[11:17:11.227] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:17:11.534] <TB2> INFO: Expecting 2560 events.
[11:17:12.418] <TB2> INFO: 2560 events read in total (293ms).
[11:17:12.419] <TB2> INFO: Test took 1192ms.
[11:17:12.422] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:17:12.726] <TB2> INFO: Expecting 2560 events.
[11:17:13.610] <TB2> INFO: 2560 events read in total (292ms).
[11:17:13.610] <TB2> INFO: Test took 1188ms.
[11:17:13.612] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:17:13.919] <TB2> INFO: Expecting 2560 events.
[11:17:14.810] <TB2> INFO: 2560 events read in total (299ms).
[11:17:14.811] <TB2> INFO: Test took 1199ms.
[11:17:14.814] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:17:15.119] <TB2> INFO: Expecting 2560 events.
[11:17:15.001] <TB2> INFO: 2560 events read in total (290ms).
[11:17:15.001] <TB2> INFO: Test took 1187ms.
[11:17:16.467] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 532 seconds
[11:17:16.467] <TB2> INFO: PH scale (per ROC): 45 51 48 49 43 48 55 38 43 45 49 39 38 65 60 61
[11:17:16.467] <TB2> INFO: PH offset (per ROC): 139 125 125 127 109 139 130 109 83 103 144 113 105 127 116 123
[11:17:16.476] <TB2> INFO: Decoding statistics:
[11:17:16.476] <TB2> INFO: General information:
[11:17:16.476] <TB2> INFO: 16bit words read: 127890
[11:17:16.476] <TB2> INFO: valid events total: 20480
[11:17:16.476] <TB2> INFO: empty events: 17975
[11:17:16.476] <TB2> INFO: valid events with pixels: 2505
[11:17:16.476] <TB2> INFO: valid pixel hits: 2505
[11:17:16.476] <TB2> INFO: Event errors: 0
[11:17:16.476] <TB2> INFO: start marker: 0
[11:17:16.476] <TB2> INFO: stop marker: 0
[11:17:16.476] <TB2> INFO: overflow: 0
[11:17:16.476] <TB2> INFO: invalid 5bit words: 0
[11:17:16.476] <TB2> INFO: invalid XOR eye diagram: 0
[11:17:16.476] <TB2> INFO: frame (failed synchr.): 0
[11:17:16.476] <TB2> INFO: idle data (no TBM trl): 0
[11:17:16.476] <TB2> INFO: no data (only TBM hdr): 0
[11:17:16.476] <TB2> INFO: TBM errors: 0
[11:17:16.476] <TB2> INFO: flawed TBM headers: 0
[11:17:16.476] <TB2> INFO: flawed TBM trailers: 0
[11:17:16.476] <TB2> INFO: event ID mismatches: 0
[11:17:16.476] <TB2> INFO: ROC errors: 0
[11:17:16.476] <TB2> INFO: missing ROC header(s): 0
[11:17:16.476] <TB2> INFO: misplaced readback start: 0
[11:17:16.476] <TB2> INFO: Pixel decoding errors: 0
[11:17:16.476] <TB2> INFO: pixel data incomplete: 0
[11:17:16.476] <TB2> INFO: pixel address: 0
[11:17:16.476] <TB2> INFO: pulse height fill bit: 0
[11:17:16.476] <TB2> INFO: buffer corruption: 0
[11:17:16.646] <TB2> INFO: ######################################################################
[11:17:16.646] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[11:17:16.646] <TB2> INFO: ######################################################################
[11:17:16.661] <TB2> INFO: scanning low vcal = 10
[11:17:16.920] <TB2> INFO: Expecting 41600 events.
[11:17:20.509] <TB2> INFO: 41600 events read in total (2998ms).
[11:17:20.509] <TB2> INFO: Test took 3847ms.
[11:17:20.512] <TB2> INFO: scanning low vcal = 20
[11:17:20.810] <TB2> INFO: Expecting 41600 events.
[11:17:24.401] <TB2> INFO: 41600 events read in total (3000ms).
[11:17:24.401] <TB2> INFO: Test took 3889ms.
[11:17:24.405] <TB2> INFO: scanning low vcal = 30
[11:17:24.701] <TB2> INFO: Expecting 41600 events.
[11:17:28.348] <TB2> INFO: 41600 events read in total (3055ms).
[11:17:28.349] <TB2> INFO: Test took 3944ms.
[11:17:28.352] <TB2> INFO: scanning low vcal = 40
[11:17:28.629] <TB2> INFO: Expecting 41600 events.
[11:17:32.618] <TB2> INFO: 41600 events read in total (3397ms).
[11:17:32.620] <TB2> INFO: Test took 4267ms.
[11:17:32.625] <TB2> INFO: scanning low vcal = 50
[11:17:32.901] <TB2> INFO: Expecting 41600 events.
[11:17:36.859] <TB2> INFO: 41600 events read in total (3366ms).
[11:17:36.860] <TB2> INFO: Test took 4235ms.
[11:17:36.864] <TB2> INFO: scanning low vcal = 60
[11:17:37.177] <TB2> INFO: Expecting 41600 events.
[11:17:41.179] <TB2> INFO: 41600 events read in total (3410ms).
[11:17:41.179] <TB2> INFO: Test took 4315ms.
[11:17:41.182] <TB2> INFO: scanning low vcal = 70
[11:17:41.459] <TB2> INFO: Expecting 41600 events.
[11:17:45.410] <TB2> INFO: 41600 events read in total (3359ms).
[11:17:45.411] <TB2> INFO: Test took 4228ms.
[11:17:45.414] <TB2> INFO: scanning low vcal = 80
[11:17:45.691] <TB2> INFO: Expecting 41600 events.
[11:17:49.738] <TB2> INFO: 41600 events read in total (3456ms).
[11:17:49.740] <TB2> INFO: Test took 4325ms.
[11:17:49.743] <TB2> INFO: scanning low vcal = 90
[11:17:50.032] <TB2> INFO: Expecting 41600 events.
[11:17:54.010] <TB2> INFO: 41600 events read in total (3386ms).
[11:17:54.011] <TB2> INFO: Test took 4268ms.
[11:17:54.015] <TB2> INFO: scanning low vcal = 100
[11:17:54.291] <TB2> INFO: Expecting 41600 events.
[11:17:58.231] <TB2> INFO: 41600 events read in total (3348ms).
[11:17:58.232] <TB2> INFO: Test took 4217ms.
[11:17:58.235] <TB2> INFO: scanning low vcal = 110
[11:17:58.512] <TB2> INFO: Expecting 41600 events.
[11:18:02.508] <TB2> INFO: 41600 events read in total (3404ms).
[11:18:02.509] <TB2> INFO: Test took 4274ms.
[11:18:02.512] <TB2> INFO: scanning low vcal = 120
[11:18:02.805] <TB2> INFO: Expecting 41600 events.
[11:18:06.741] <TB2> INFO: 41600 events read in total (3344ms).
[11:18:06.743] <TB2> INFO: Test took 4231ms.
[11:18:06.746] <TB2> INFO: scanning low vcal = 130
[11:18:07.023] <TB2> INFO: Expecting 41600 events.
[11:18:10.975] <TB2> INFO: 41600 events read in total (3361ms).
[11:18:10.976] <TB2> INFO: Test took 4230ms.
[11:18:10.981] <TB2> INFO: scanning low vcal = 140
[11:18:11.259] <TB2> INFO: Expecting 41600 events.
[11:18:15.192] <TB2> INFO: 41600 events read in total (3342ms).
[11:18:15.193] <TB2> INFO: Test took 4212ms.
[11:18:15.197] <TB2> INFO: scanning low vcal = 150
[11:18:15.473] <TB2> INFO: Expecting 41600 events.
[11:18:19.426] <TB2> INFO: 41600 events read in total (3361ms).
[11:18:19.426] <TB2> INFO: Test took 4229ms.
[11:18:19.430] <TB2> INFO: scanning low vcal = 160
[11:18:19.706] <TB2> INFO: Expecting 41600 events.
[11:18:23.758] <TB2> INFO: 41600 events read in total (3454ms).
[11:18:23.759] <TB2> INFO: Test took 4329ms.
[11:18:23.762] <TB2> INFO: scanning low vcal = 170
[11:18:24.039] <TB2> INFO: Expecting 41600 events.
[11:18:27.990] <TB2> INFO: 41600 events read in total (3360ms).
[11:18:27.991] <TB2> INFO: Test took 4229ms.
[11:18:27.998] <TB2> INFO: scanning low vcal = 180
[11:18:28.271] <TB2> INFO: Expecting 41600 events.
[11:18:32.218] <TB2> INFO: 41600 events read in total (3355ms).
[11:18:32.219] <TB2> INFO: Test took 4221ms.
[11:18:32.222] <TB2> INFO: scanning low vcal = 190
[11:18:32.498] <TB2> INFO: Expecting 41600 events.
[11:18:36.488] <TB2> INFO: 41600 events read in total (3396ms).
[11:18:36.490] <TB2> INFO: Test took 4268ms.
[11:18:36.493] <TB2> INFO: scanning low vcal = 200
[11:18:36.770] <TB2> INFO: Expecting 41600 events.
[11:18:40.768] <TB2> INFO: 41600 events read in total (3407ms).
[11:18:40.769] <TB2> INFO: Test took 4276ms.
[11:18:40.772] <TB2> INFO: scanning low vcal = 210
[11:18:41.048] <TB2> INFO: Expecting 41600 events.
[11:18:45.004] <TB2> INFO: 41600 events read in total (3363ms).
[11:18:45.005] <TB2> INFO: Test took 4233ms.
[11:18:45.008] <TB2> INFO: scanning low vcal = 220
[11:18:45.284] <TB2> INFO: Expecting 41600 events.
[11:18:49.248] <TB2> INFO: 41600 events read in total (3372ms).
[11:18:49.249] <TB2> INFO: Test took 4241ms.
[11:18:49.252] <TB2> INFO: scanning low vcal = 230
[11:18:49.529] <TB2> INFO: Expecting 41600 events.
[11:18:53.462] <TB2> INFO: 41600 events read in total (3342ms).
[11:18:53.464] <TB2> INFO: Test took 4212ms.
[11:18:53.467] <TB2> INFO: scanning low vcal = 240
[11:18:53.743] <TB2> INFO: Expecting 41600 events.
[11:18:57.698] <TB2> INFO: 41600 events read in total (3363ms).
[11:18:57.699] <TB2> INFO: Test took 4232ms.
[11:18:57.702] <TB2> INFO: scanning low vcal = 250
[11:18:57.981] <TB2> INFO: Expecting 41600 events.
[11:19:01.939] <TB2> INFO: 41600 events read in total (3366ms).
[11:19:01.941] <TB2> INFO: Test took 4239ms.
[11:19:01.945] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[11:19:02.221] <TB2> INFO: Expecting 41600 events.
[11:19:06.177] <TB2> INFO: 41600 events read in total (3365ms).
[11:19:06.178] <TB2> INFO: Test took 4233ms.
[11:19:06.183] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[11:19:06.458] <TB2> INFO: Expecting 41600 events.
[11:19:10.414] <TB2> INFO: 41600 events read in total (3364ms).
[11:19:10.415] <TB2> INFO: Test took 4232ms.
[11:19:10.419] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[11:19:10.695] <TB2> INFO: Expecting 41600 events.
[11:19:14.705] <TB2> INFO: 41600 events read in total (3419ms).
[11:19:14.706] <TB2> INFO: Test took 4287ms.
[11:19:14.710] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[11:19:14.986] <TB2> INFO: Expecting 41600 events.
[11:19:18.936] <TB2> INFO: 41600 events read in total (3358ms).
[11:19:18.937] <TB2> INFO: Test took 4227ms.
[11:19:18.943] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[11:19:19.218] <TB2> INFO: Expecting 41600 events.
[11:19:23.252] <TB2> INFO: 41600 events read in total (3442ms).
[11:19:23.253] <TB2> INFO: Test took 4310ms.
[11:19:23.713] <TB2> INFO: PixTestGainPedestal::measure() done
[11:20:00.112] <TB2> INFO: PixTestGainPedestal::fit() done
[11:20:00.112] <TB2> INFO: non-linearity mean: 0.959 0.975 0.972 0.968 0.867 0.964 0.969 0.908 0.951 0.921 0.980 0.905 0.897 0.981 0.982 0.979
[11:20:00.112] <TB2> INFO: non-linearity RMS: 0.008 0.004 0.004 0.005 0.143 0.006 0.005 0.121 0.176 0.063 0.003 0.122 0.080 0.002 0.004 0.003
[11:20:00.112] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[11:20:00.126] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[11:20:00.140] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[11:20:00.154] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[11:20:00.168] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[11:20:00.181] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[11:20:00.195] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[11:20:00.208] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[11:20:00.221] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[11:20:00.234] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[11:20:00.247] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[11:20:00.260] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[11:20:00.273] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[11:20:00.286] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[11:20:00.299] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[11:20:00.311] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1119_FullQualification_2016-11-03_09h01m_1478160071//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[11:20:00.324] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 163 seconds
[11:20:00.324] <TB2> INFO: Decoding statistics:
[11:20:00.324] <TB2> INFO: General information:
[11:20:00.324] <TB2> INFO: 16bit words read: 3327952
[11:20:00.324] <TB2> INFO: valid events total: 332800
[11:20:00.324] <TB2> INFO: empty events: 0
[11:20:00.324] <TB2> INFO: valid events with pixels: 332800
[11:20:00.324] <TB2> INFO: valid pixel hits: 665576
[11:20:00.324] <TB2> INFO: Event errors: 0
[11:20:00.324] <TB2> INFO: start marker: 0
[11:20:00.324] <TB2> INFO: stop marker: 0
[11:20:00.324] <TB2> INFO: overflow: 0
[11:20:00.324] <TB2> INFO: invalid 5bit words: 0
[11:20:00.324] <TB2> INFO: invalid XOR eye diagram: 0
[11:20:00.324] <TB2> INFO: frame (failed synchr.): 0
[11:20:00.324] <TB2> INFO: idle data (no TBM trl): 0
[11:20:00.324] <TB2> INFO: no data (only TBM hdr): 0
[11:20:00.324] <TB2> INFO: TBM errors: 0
[11:20:00.324] <TB2> INFO: flawed TBM headers: 0
[11:20:00.324] <TB2> INFO: flawed TBM trailers: 0
[11:20:00.325] <TB2> INFO: event ID mismatches: 0
[11:20:00.325] <TB2> INFO: ROC errors: 0
[11:20:00.325] <TB2> INFO: missing ROC header(s): 0
[11:20:00.325] <TB2> INFO: misplaced readback start: 0
[11:20:00.325] <TB2> INFO: Pixel decoding errors: 0
[11:20:00.325] <TB2> INFO: pixel data incomplete: 0
[11:20:00.325] <TB2> INFO: pixel address: 0
[11:20:00.325] <TB2> INFO: pulse height fill bit: 0
[11:20:00.325] <TB2> INFO: buffer corruption: 0
[11:20:00.345] <TB2> INFO: Decoding statistics:
[11:20:00.345] <TB2> INFO: General information:
[11:20:00.345] <TB2> INFO: 16bit words read: 3457378
[11:20:00.345] <TB2> INFO: valid events total: 353536
[11:20:00.345] <TB2> INFO: empty events: 18231
[11:20:00.345] <TB2> INFO: valid events with pixels: 335305
[11:20:00.345] <TB2> INFO: valid pixel hits: 668081
[11:20:00.345] <TB2> INFO: Event errors: 0
[11:20:00.345] <TB2> INFO: start marker: 0
[11:20:00.345] <TB2> INFO: stop marker: 0
[11:20:00.345] <TB2> INFO: overflow: 0
[11:20:00.345] <TB2> INFO: invalid 5bit words: 0
[11:20:00.345] <TB2> INFO: invalid XOR eye diagram: 0
[11:20:00.345] <TB2> INFO: frame (failed synchr.): 0
[11:20:00.345] <TB2> INFO: idle data (no TBM trl): 0
[11:20:00.345] <TB2> INFO: no data (only TBM hdr): 0
[11:20:00.345] <TB2> INFO: TBM errors: 0
[11:20:00.345] <TB2> INFO: flawed TBM headers: 0
[11:20:00.345] <TB2> INFO: flawed TBM trailers: 0
[11:20:00.345] <TB2> INFO: event ID mismatches: 0
[11:20:00.345] <TB2> INFO: ROC errors: 0
[11:20:00.345] <TB2> INFO: missing ROC header(s): 0
[11:20:00.345] <TB2> INFO: misplaced readback start: 0
[11:20:00.345] <TB2> INFO: Pixel decoding errors: 0
[11:20:00.345] <TB2> INFO: pixel data incomplete: 0
[11:20:00.345] <TB2> INFO: pixel address: 0
[11:20:00.345] <TB2> INFO: pulse height fill bit: 0
[11:20:00.345] <TB2> INFO: buffer corruption: 0
[11:20:00.346] <TB2> INFO: enter test to run
[11:20:00.346] <TB2> INFO: test: exit no parameter change
[11:20:00.502] <TB2> QUIET: Connection to board 149 closed.
[11:20:00.503] <TB2> INFO: pXar: this is the end, my friend