[11:31:45.990] <TB0> INFO: *** Welcome to pxar ***
[11:31:45.990] <TB0> INFO: *** Today: 2016/11/03
[11:31:45.997] <TB0> INFO: *** Version: c8ba-dirty
[11:31:45.997] <TB0> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C15.dat
[11:31:45.997] <TB0> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[11:31:45.997] <TB0> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//defaultMaskFile.dat
[11:31:45.997] <TB0> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters_C15.dat
[11:31:46.058] <TB0> INFO: clk: 4
[11:31:46.058] <TB0> INFO: ctr: 4
[11:31:46.058] <TB0> INFO: sda: 19
[11:31:46.058] <TB0> INFO: tin: 9
[11:31:46.058] <TB0> INFO: level: 15
[11:31:46.058] <TB0> INFO: triggerdelay: 0
[11:31:46.058] <TB0> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[11:31:46.058] <TB0> INFO: Log level: INFO
[11:31:46.067] <TB0> INFO: Found DTB DTB_WRQ4OZ
[11:31:46.077] <TB0> QUIET: Connection to board DTB_WRQ4OZ opened.
[11:31:46.079] <TB0> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 71
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WRQ4OZ
MAC address: 40D855118047
Hostname: pixelDTB071
Comment:
------------------------------------------------------
[11:31:46.081] <TB0> INFO: RPC call hashes of host and DTB match: 486171790
[11:31:47.569] <TB0> INFO: DUT info:
[11:31:47.569] <TB0> INFO: The DUT currently contains the following objects:
[11:31:47.569] <TB0> INFO: 4 TBM Cores tbm10c (4 ON)
[11:31:47.569] <TB0> INFO: TBM Core alpha (0): 7 registers set
[11:31:47.569] <TB0> INFO: TBM Core beta (1): 7 registers set
[11:31:47.569] <TB0> INFO: TBM Core alpha (2): 7 registers set
[11:31:47.569] <TB0> INFO: TBM Core beta (3): 7 registers set
[11:31:47.569] <TB0> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:31:47.569] <TB0> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.570] <TB0> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:31:47.971] <TB0> INFO: enter 'restricted' command line mode
[11:31:47.971] <TB0> INFO: enter test to run
[11:31:47.971] <TB0> INFO: test: pretest no parameter change
[11:31:47.971] <TB0> INFO: running: pretest
[11:31:47.975] <TB0> INFO: ######################################################################
[11:31:47.975] <TB0> INFO: PixTestPretest::doTest()
[11:31:47.975] <TB0> INFO: ######################################################################
[11:31:47.976] <TB0> INFO: ----------------------------------------------------------------------
[11:31:47.976] <TB0> INFO: PixTestPretest::programROC()
[11:31:47.976] <TB0> INFO: ----------------------------------------------------------------------
[11:32:05.990] <TB0> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:32:05.990] <TB0> INFO: IA differences per ROC: 18.5 19.3 21.7 19.3 18.5 20.1 18.5 17.7 21.7 20.9 19.3 19.3 20.1 19.3 23.3 19.3
[11:32:06.071] <TB0> INFO: ----------------------------------------------------------------------
[11:32:06.071] <TB0> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:32:06.071] <TB0> INFO: ----------------------------------------------------------------------
[11:32:12.648] <TB0> INFO: PixTestPretest::setVana() done, Module Ia 384.3 mA = 24.0187 mA/ROC
[11:32:12.648] <TB0> INFO: i(loss) [mA/ROC]: 19.3 20.1 19.3 19.3 19.3 18.5 19.3 19.3 19.3 19.3 19.3 19.3 19.3 18.5 18.5 18.5
[11:32:12.675] <TB0> INFO: ----------------------------------------------------------------------
[11:32:12.675] <TB0> INFO: PixTestPretest::findTiming()
[11:32:12.675] <TB0> INFO: ----------------------------------------------------------------------
[11:32:12.675] <TB0> INFO: PixTestCmd::init()

[11:32:44.412] <TB0> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:32:44.412] <TB0> INFO: (success/tries = 100/100), width = 4
[11:32:45.914] <TB0> INFO: ----------------------------------------------------------------------
[11:32:45.914] <TB0> INFO: PixTestPretest::findWorkingPixel()
[11:32:45.914] <TB0> INFO: ----------------------------------------------------------------------
[11:32:46.007] <TB0> INFO: Expecting 231680 events.
[11:32:56.028] <TB0> INFO: 231680 events read in total (9430ms).
[11:32:56.037] <TB0> INFO: Test took 10120ms.
[11:32:56.276] <TB0> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:32:56.308] <TB0> INFO: ----------------------------------------------------------------------
[11:32:56.308] <TB0> INFO: PixTestPretest::setVthrCompCalDel()
[11:32:56.308] <TB0> INFO: ----------------------------------------------------------------------
[11:32:56.402] <TB0> INFO: Expecting 231680 events.
[11:33:06.122] <TB0> INFO: 231680 events read in total (9128ms).
[11:33:06.134] <TB0> INFO: Test took 9820ms.
[11:33:06.388] <TB0> INFO: PixTestPretest::setVthrCompCalDel() done
[11:33:06.388] <TB0> INFO: CalDel: 91 96 99 90 79 81 78 81 82 78 85 100 95 94 96 82
[11:33:06.388] <TB0> INFO: VthrComp: 51 51 51 51 53 51 52 51 51 51 51 51 51 51 51 51
[11:33:06.391] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C0.dat
[11:33:06.391] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C1.dat
[11:33:06.392] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C2.dat
[11:33:06.392] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C3.dat
[11:33:06.392] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C4.dat
[11:33:06.392] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C5.dat
[11:33:06.392] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C6.dat
[11:33:06.392] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C7.dat
[11:33:06.392] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C8.dat
[11:33:06.392] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C9.dat
[11:33:06.392] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C10.dat
[11:33:06.392] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C11.dat
[11:33:06.393] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C12.dat
[11:33:06.393] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C13.dat
[11:33:06.393] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C14.dat
[11:33:06.393] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters_C15.dat
[11:33:06.393] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[11:33:06.393] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[11:33:06.393] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[11:33:06.393] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[11:33:06.393] <TB0> INFO: PixTestPretest::doTest() done, duration: 78 seconds
[11:33:06.461] <TB0> INFO: enter test to run
[11:33:06.461] <TB0> INFO: test: fulltest no parameter change
[11:33:06.461] <TB0> INFO: running: fulltest
[11:33:06.461] <TB0> INFO: ######################################################################
[11:33:06.461] <TB0> INFO: PixTestFullTest::doTest()
[11:33:06.461] <TB0> INFO: ######################################################################
[11:33:06.463] <TB0> INFO: ######################################################################
[11:33:06.463] <TB0> INFO: PixTestAlive::doTest()
[11:33:06.463] <TB0> INFO: ######################################################################
[11:33:06.464] <TB0> INFO: ----------------------------------------------------------------------
[11:33:06.464] <TB0> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:33:06.464] <TB0> INFO: ----------------------------------------------------------------------
[11:33:06.709] <TB0> INFO: Expecting 41600 events.
[11:33:10.423] <TB0> INFO: 41600 events read in total (3122ms).
[11:33:10.424] <TB0> INFO: Test took 3958ms.
[11:33:10.655] <TB0> INFO: PixTestAlive::aliveTest() done
[11:33:10.655] <TB0> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:33:10.657] <TB0> INFO: ----------------------------------------------------------------------
[11:33:10.657] <TB0> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:33:10.657] <TB0> INFO: ----------------------------------------------------------------------
[11:33:10.906] <TB0> INFO: Expecting 41600 events.
[11:33:13.866] <TB0> INFO: 41600 events read in total (2368ms).
[11:33:13.867] <TB0> INFO: Test took 3208ms.
[11:33:13.868] <TB0> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:33:14.106] <TB0> INFO: PixTestAlive::maskTest() done
[11:33:14.107] <TB0> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:33:14.108] <TB0> INFO: ----------------------------------------------------------------------
[11:33:14.108] <TB0> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:33:14.108] <TB0> INFO: ----------------------------------------------------------------------
[11:33:14.345] <TB0> INFO: Expecting 41600 events.
[11:33:17.807] <TB0> INFO: 41600 events read in total (2871ms).
[11:33:17.808] <TB0> INFO: Test took 3699ms.
[11:33:18.037] <TB0> INFO: PixTestAlive::addressDecodingTest() done
[11:33:18.037] <TB0> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:33:18.037] <TB0> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:33:18.037] <TB0> INFO: Decoding statistics:
[11:33:18.037] <TB0> INFO: General information:
[11:33:18.037] <TB0> INFO: 16bit words read: 0
[11:33:18.037] <TB0> INFO: valid events total: 0
[11:33:18.037] <TB0> INFO: empty events: 0
[11:33:18.037] <TB0> INFO: valid events with pixels: 0
[11:33:18.037] <TB0> INFO: valid pixel hits: 0
[11:33:18.037] <TB0> INFO: Event errors: 0
[11:33:18.037] <TB0> INFO: start marker: 0
[11:33:18.037] <TB0> INFO: stop marker: 0
[11:33:18.037] <TB0> INFO: overflow: 0
[11:33:18.037] <TB0> INFO: invalid 5bit words: 0
[11:33:18.038] <TB0> INFO: invalid XOR eye diagram: 0
[11:33:18.038] <TB0> INFO: frame (failed synchr.): 0
[11:33:18.038] <TB0> INFO: idle data (no TBM trl): 0
[11:33:18.038] <TB0> INFO: no data (only TBM hdr): 0
[11:33:18.038] <TB0> INFO: TBM errors: 0
[11:33:18.038] <TB0> INFO: flawed TBM headers: 0
[11:33:18.038] <TB0> INFO: flawed TBM trailers: 0
[11:33:18.038] <TB0> INFO: event ID mismatches: 0
[11:33:18.038] <TB0> INFO: ROC errors: 0
[11:33:18.038] <TB0> INFO: missing ROC header(s): 0
[11:33:18.038] <TB0> INFO: misplaced readback start: 0
[11:33:18.038] <TB0> INFO: Pixel decoding errors: 0
[11:33:18.038] <TB0> INFO: pixel data incomplete: 0
[11:33:18.038] <TB0> INFO: pixel address: 0
[11:33:18.038] <TB0> INFO: pulse height fill bit: 0
[11:33:18.038] <TB0> INFO: buffer corruption: 0
[11:33:18.042] <TB0> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:33:18.043] <TB0> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[11:33:18.043] <TB0> INFO: ######################################################################
[11:33:18.043] <TB0> INFO: PixTestReadback::doTest()
[11:33:18.043] <TB0> INFO: ######################################################################
[11:33:18.043] <TB0> INFO: ----------------------------------------------------------------------
[11:33:18.043] <TB0> INFO: PixTestReadback::CalibrateVd()
[11:33:18.043] <TB0> INFO: ----------------------------------------------------------------------
[11:33:27.971] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C0.dat
[11:33:27.971] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C1.dat
[11:33:27.971] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C2.dat
[11:33:27.971] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C3.dat
[11:33:27.971] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C4.dat
[11:33:27.971] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C5.dat
[11:33:27.971] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C6.dat
[11:33:27.971] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C7.dat
[11:33:27.971] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C8.dat
[11:33:27.971] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C9.dat
[11:33:27.972] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C10.dat
[11:33:27.972] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C11.dat
[11:33:27.972] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C12.dat
[11:33:27.972] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C13.dat
[11:33:27.972] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C14.dat
[11:33:27.972] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:33:27.999] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[11:33:27.999] <TB0> INFO: ----------------------------------------------------------------------
[11:33:27.999] <TB0> INFO: PixTestReadback::CalibrateVa()
[11:33:27.999] <TB0> INFO: ----------------------------------------------------------------------
[11:33:37.905] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C0.dat
[11:33:37.905] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C1.dat
[11:33:37.905] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C2.dat
[11:33:37.905] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C3.dat
[11:33:37.905] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C4.dat
[11:33:37.905] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C5.dat
[11:33:37.905] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C6.dat
[11:33:37.905] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C7.dat
[11:33:37.905] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C8.dat
[11:33:37.906] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C9.dat
[11:33:37.906] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C10.dat
[11:33:37.906] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C11.dat
[11:33:37.906] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C12.dat
[11:33:37.906] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C13.dat
[11:33:37.906] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C14.dat
[11:33:37.906] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:33:37.933] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[11:33:37.933] <TB0> INFO: ----------------------------------------------------------------------
[11:33:37.933] <TB0> INFO: PixTestReadback::readbackVbg()
[11:33:37.933] <TB0> INFO: ----------------------------------------------------------------------
[11:33:45.580] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[11:33:45.580] <TB0> INFO: ----------------------------------------------------------------------
[11:33:45.580] <TB0> INFO: PixTestReadback::getCalibratedVbg()
[11:33:45.580] <TB0> INFO: ----------------------------------------------------------------------
[11:33:45.580] <TB0> INFO: Vbg will be calibrated using Vd calibration
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 153.3calibrated Vbg = 1.18725 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 153.7calibrated Vbg = 1.18813 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 160.3calibrated Vbg = 1.18249 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 160.9calibrated Vbg = 1.1744 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 149.4calibrated Vbg = 1.1802 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 148.6calibrated Vbg = 1.18751 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 163.5calibrated Vbg = 1.1948 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 160.3calibrated Vbg = 1.18067 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 160.7calibrated Vbg = 1.18798 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 142.7calibrated Vbg = 1.18344 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 150.7calibrated Vbg = 1.17257 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 143calibrated Vbg = 1.17885 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 157.9calibrated Vbg = 1.18239 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 167.3calibrated Vbg = 1.19063 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 163.8calibrated Vbg = 1.19023 :::*/*/*/*/
[11:33:45.580] <TB0> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 149.3calibrated Vbg = 1.18018 :::*/*/*/*/
[11:33:45.582] <TB0> INFO: ----------------------------------------------------------------------
[11:33:45.582] <TB0> INFO: PixTestReadback::CalibrateIa()
[11:33:45.582] <TB0> INFO: ----------------------------------------------------------------------
[11:36:25.939] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C0.dat
[11:36:25.939] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C1.dat
[11:36:25.939] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C2.dat
[11:36:25.940] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C3.dat
[11:36:25.940] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C4.dat
[11:36:25.940] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C5.dat
[11:36:25.940] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C6.dat
[11:36:25.940] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C7.dat
[11:36:25.940] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C8.dat
[11:36:25.940] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C9.dat
[11:36:25.940] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C10.dat
[11:36:25.940] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C11.dat
[11:36:25.940] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C12.dat
[11:36:25.940] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C13.dat
[11:36:25.940] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C14.dat
[11:36:25.940] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//readbackCal_C15.dat
[11:36:25.969] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[11:36:25.970] <TB0> INFO: PixTestReadback::doTest() done
[11:36:25.970] <TB0> INFO: Decoding statistics:
[11:36:25.970] <TB0> INFO: General information:
[11:36:25.970] <TB0> INFO: 16bit words read: 1536
[11:36:25.970] <TB0> INFO: valid events total: 256
[11:36:25.970] <TB0> INFO: empty events: 256
[11:36:25.970] <TB0> INFO: valid events with pixels: 0
[11:36:25.970] <TB0> INFO: valid pixel hits: 0
[11:36:25.970] <TB0> INFO: Event errors: 0
[11:36:25.970] <TB0> INFO: start marker: 0
[11:36:25.970] <TB0> INFO: stop marker: 0
[11:36:25.970] <TB0> INFO: overflow: 0
[11:36:25.970] <TB0> INFO: invalid 5bit words: 0
[11:36:25.970] <TB0> INFO: invalid XOR eye diagram: 0
[11:36:25.970] <TB0> INFO: frame (failed synchr.): 0
[11:36:25.970] <TB0> INFO: idle data (no TBM trl): 0
[11:36:25.970] <TB0> INFO: no data (only TBM hdr): 0
[11:36:25.970] <TB0> INFO: TBM errors: 0
[11:36:25.970] <TB0> INFO: flawed TBM headers: 0
[11:36:25.970] <TB0> INFO: flawed TBM trailers: 0
[11:36:25.970] <TB0> INFO: event ID mismatches: 0
[11:36:25.970] <TB0> INFO: ROC errors: 0
[11:36:25.970] <TB0> INFO: missing ROC header(s): 0
[11:36:25.970] <TB0> INFO: misplaced readback start: 0
[11:36:25.970] <TB0> INFO: Pixel decoding errors: 0
[11:36:25.970] <TB0> INFO: pixel data incomplete: 0
[11:36:25.970] <TB0> INFO: pixel address: 0
[11:36:25.970] <TB0> INFO: pulse height fill bit: 0
[11:36:25.970] <TB0> INFO: buffer corruption: 0
[11:36:26.022] <TB0> INFO: ######################################################################
[11:36:26.023] <TB0> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:36:26.023] <TB0> INFO: ######################################################################
[11:36:26.025] <TB0> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:36:26.242] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[11:36:26.242] <TB0> INFO: run 1 of 1
[11:36:26.481] <TB0> INFO: Expecting 3120000 events.
[11:36:56.993] <TB0> INFO: 664665 events read in total (29920ms).











[11:37:27.656] <TB0> INFO: 1327395 events read in total (60583ms).











[11:37:58.173] <TB0> INFO: 1991075 events read in total (91100ms).











[11:38:29.312] <TB0> INFO: 2656565 events read in total (122239ms).











[11:38:50.719] <TB0> INFO: 3120000 events read in total (143646ms).
[11:38:50.851] <TB0> INFO: Test took 144609ms.
[11:39:17.659] <TB0> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 171 seconds
[11:39:17.659] <TB0> INFO: number of dead bumps (per ROC): 0 0 6 0 0 0 0 0 0 0 0 0 0 1 1 0
[11:39:17.659] <TB0> INFO: separation cut (per ROC): 103 102 111 113 104 109 121 109 118 107 109 104 103 98 101 107
[11:39:17.660] <TB0> INFO: Decoding statistics:
[11:39:17.660] <TB0> INFO: General information:
[11:39:17.660] <TB0> INFO: 16bit words read: 0
[11:39:17.660] <TB0> INFO: valid events total: 0
[11:39:17.660] <TB0> INFO: empty events: 0
[11:39:17.660] <TB0> INFO: valid events with pixels: 0
[11:39:17.660] <TB0> INFO: valid pixel hits: 0
[11:39:17.660] <TB0> INFO: Event errors: 0
[11:39:17.660] <TB0> INFO: start marker: 0
[11:39:17.660] <TB0> INFO: stop marker: 0
[11:39:17.660] <TB0> INFO: overflow: 0
[11:39:17.660] <TB0> INFO: invalid 5bit words: 0
[11:39:17.660] <TB0> INFO: invalid XOR eye diagram: 0
[11:39:17.660] <TB0> INFO: frame (failed synchr.): 0
[11:39:17.660] <TB0> INFO: idle data (no TBM trl): 0
[11:39:17.660] <TB0> INFO: no data (only TBM hdr): 0
[11:39:17.660] <TB0> INFO: TBM errors: 0
[11:39:17.660] <TB0> INFO: flawed TBM headers: 0
[11:39:17.660] <TB0> INFO: flawed TBM trailers: 0
[11:39:17.660] <TB0> INFO: event ID mismatches: 0
[11:39:17.660] <TB0> INFO: ROC errors: 0
[11:39:17.660] <TB0> INFO: missing ROC header(s): 0
[11:39:17.660] <TB0> INFO: misplaced readback start: 0
[11:39:17.660] <TB0> INFO: Pixel decoding errors: 0
[11:39:17.660] <TB0> INFO: pixel data incomplete: 0
[11:39:17.660] <TB0> INFO: pixel address: 0
[11:39:17.660] <TB0> INFO: pulse height fill bit: 0
[11:39:17.660] <TB0> INFO: buffer corruption: 0
[11:39:17.724] <TB0> INFO: ######################################################################
[11:39:17.724] <TB0> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:39:17.724] <TB0> INFO: ######################################################################
[11:39:17.724] <TB0> INFO: ----------------------------------------------------------------------
[11:39:17.724] <TB0> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:39:17.724] <TB0> INFO: ----------------------------------------------------------------------
[11:39:17.724] <TB0> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[11:39:17.741] <TB0> INFO: dacScan split into 1 runs with ntrig = 50
[11:39:17.741] <TB0> INFO: run 1 of 1
[11:39:18.072] <TB0> INFO: Expecting 36608000 events.
[11:39:43.435] <TB0> INFO: 681100 events read in total (24766ms).
[11:40:07.443] <TB0> INFO: 1344600 events read in total (48774ms).
[11:40:31.374] <TB0> INFO: 2010600 events read in total (72705ms).
[11:40:55.150] <TB0> INFO: 2672700 events read in total (96481ms).
[11:41:18.575] <TB0> INFO: 3337700 events read in total (119906ms).
[11:41:41.949] <TB0> INFO: 4000150 events read in total (143280ms).
[11:42:05.392] <TB0> INFO: 4663150 events read in total (166723ms).
[11:42:29.209] <TB0> INFO: 5324600 events read in total (190540ms).
[11:42:52.407] <TB0> INFO: 5984850 events read in total (213738ms).
[11:43:16.083] <TB0> INFO: 6644500 events read in total (237414ms).
[11:43:39.938] <TB0> INFO: 7303800 events read in total (261269ms).
[11:44:03.497] <TB0> INFO: 7964750 events read in total (284828ms).
[11:44:27.047] <TB0> INFO: 8624750 events read in total (308378ms).
[11:44:50.411] <TB0> INFO: 9285850 events read in total (331742ms).
[11:45:13.531] <TB0> INFO: 9944800 events read in total (354862ms).
[11:45:37.005] <TB0> INFO: 10602800 events read in total (378336ms).
[11:46:00.245] <TB0> INFO: 11258550 events read in total (401576ms).
[11:46:23.215] <TB0> INFO: 11914750 events read in total (424546ms).
[11:46:46.145] <TB0> INFO: 12570750 events read in total (447476ms).
[11:47:09.270] <TB0> INFO: 13225800 events read in total (470601ms).
[11:47:32.290] <TB0> INFO: 13880250 events read in total (493621ms).
[11:47:55.784] <TB0> INFO: 14534900 events read in total (517115ms).
[11:48:19.170] <TB0> INFO: 15189500 events read in total (540501ms).
[11:48:42.313] <TB0> INFO: 15845550 events read in total (563644ms).
[11:49:05.227] <TB0> INFO: 16500250 events read in total (586558ms).
[11:49:28.339] <TB0> INFO: 17154850 events read in total (609670ms).
[11:49:51.393] <TB0> INFO: 17807750 events read in total (632724ms).
[11:50:14.409] <TB0> INFO: 18458750 events read in total (655740ms).
[11:50:37.204] <TB0> INFO: 19110650 events read in total (678535ms).
[11:51:00.321] <TB0> INFO: 19758900 events read in total (701652ms).
[11:51:23.469] <TB0> INFO: 20407600 events read in total (724800ms).
[11:51:46.689] <TB0> INFO: 21055800 events read in total (748020ms).
[11:52:09.599] <TB0> INFO: 21706450 events read in total (770931ms).
[11:52:32.566] <TB0> INFO: 22356550 events read in total (793897ms).
[11:52:55.440] <TB0> INFO: 23004350 events read in total (816771ms).
[11:53:18.485] <TB0> INFO: 23652000 events read in total (839816ms).
[11:53:41.342] <TB0> INFO: 24299500 events read in total (862673ms).
[11:54:04.536] <TB0> INFO: 24945650 events read in total (885867ms).
[11:54:27.671] <TB0> INFO: 25591650 events read in total (909002ms).
[11:54:50.530] <TB0> INFO: 26237200 events read in total (931861ms).
[11:55:13.580] <TB0> INFO: 26880900 events read in total (954911ms).
[11:55:36.567] <TB0> INFO: 27526400 events read in total (977898ms).
[11:55:59.544] <TB0> INFO: 28170200 events read in total (1000875ms).
[11:56:22.613] <TB0> INFO: 28817050 events read in total (1023944ms).
[11:56:45.859] <TB0> INFO: 29461550 events read in total (1047190ms).
[11:57:08.724] <TB0> INFO: 30107450 events read in total (1070055ms).
[11:57:31.588] <TB0> INFO: 30752600 events read in total (1092919ms).
[11:57:54.410] <TB0> INFO: 31397400 events read in total (1115741ms).
[11:58:17.257] <TB0> INFO: 32042650 events read in total (1138588ms).
[11:58:40.264] <TB0> INFO: 32687150 events read in total (1161595ms).
[11:59:03.045] <TB0> INFO: 33331850 events read in total (1184376ms).
[11:59:26.379] <TB0> INFO: 33976250 events read in total (1207710ms).
[11:59:49.181] <TB0> INFO: 34623000 events read in total (1230512ms).
[12:00:12.429] <TB0> INFO: 35266800 events read in total (1253760ms).
[12:00:35.473] <TB0> INFO: 35914550 events read in total (1276804ms).
[12:00:58.810] <TB0> INFO: 36569900 events read in total (1300141ms).
[12:01:00.644] <TB0> INFO: 36608000 events read in total (1301975ms).
[12:01:00.757] <TB0> INFO: Test took 1303015ms.
[12:01:01.308] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:03.226] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:05.353] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:07.707] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:09.951] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:12.223] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:14.458] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:16.579] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:18.676] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:20.764] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:23.066] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:24.993] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:27.392] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:29.497] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:31.064] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:33.118] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:01:35.107] <TB0> INFO: PixTestScurves::scurves() done
[12:01:35.107] <TB0> INFO: Vcal mean: 119.27 114.75 128.98 123.05 121.02 118.10 126.54 127.41 122.92 112.41 118.25 113.42 108.62 103.48 109.94 114.21
[12:01:35.107] <TB0> INFO: Vcal RMS: 6.47 5.07 6.61 5.74 5.56 6.16 6.75 6.69 6.18 5.12 6.12 5.13 4.49 7.62 7.29 5.02
[12:01:35.107] <TB0> INFO: PixTestScurves::fullTest() done, duration: 1337 seconds
[12:01:35.107] <TB0> INFO: Decoding statistics:
[12:01:35.107] <TB0> INFO: General information:
[12:01:35.107] <TB0> INFO: 16bit words read: 0
[12:01:35.107] <TB0> INFO: valid events total: 0
[12:01:35.107] <TB0> INFO: empty events: 0
[12:01:35.107] <TB0> INFO: valid events with pixels: 0
[12:01:35.107] <TB0> INFO: valid pixel hits: 0
[12:01:35.107] <TB0> INFO: Event errors: 0
[12:01:35.107] <TB0> INFO: start marker: 0
[12:01:35.107] <TB0> INFO: stop marker: 0
[12:01:35.107] <TB0> INFO: overflow: 0
[12:01:35.107] <TB0> INFO: invalid 5bit words: 0
[12:01:35.107] <TB0> INFO: invalid XOR eye diagram: 0
[12:01:35.107] <TB0> INFO: frame (failed synchr.): 0
[12:01:35.107] <TB0> INFO: idle data (no TBM trl): 0
[12:01:35.107] <TB0> INFO: no data (only TBM hdr): 0
[12:01:35.107] <TB0> INFO: TBM errors: 0
[12:01:35.107] <TB0> INFO: flawed TBM headers: 0
[12:01:35.107] <TB0> INFO: flawed TBM trailers: 0
[12:01:35.107] <TB0> INFO: event ID mismatches: 0
[12:01:35.107] <TB0> INFO: ROC errors: 0
[12:01:35.108] <TB0> INFO: missing ROC header(s): 0
[12:01:35.108] <TB0> INFO: misplaced readback start: 0
[12:01:35.108] <TB0> INFO: Pixel decoding errors: 0
[12:01:35.108] <TB0> INFO: pixel data incomplete: 0
[12:01:35.108] <TB0> INFO: pixel address: 0
[12:01:35.108] <TB0> INFO: pulse height fill bit: 0
[12:01:35.108] <TB0> INFO: buffer corruption: 0
[12:01:35.180] <TB0> INFO: ######################################################################
[12:01:35.181] <TB0> INFO: PixTestTrim::doTest()
[12:01:35.181] <TB0> INFO: ######################################################################
[12:01:35.182] <TB0> INFO: ----------------------------------------------------------------------
[12:01:35.182] <TB0> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:01:35.182] <TB0> INFO: ----------------------------------------------------------------------
[12:01:35.261] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:01:35.261] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:01:35.280] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:01:35.280] <TB0> INFO: run 1 of 1
[12:01:35.571] <TB0> INFO: Expecting 5025280 events.
[12:02:07.054] <TB0> INFO: 816128 events read in total (30878ms).
[12:02:37.391] <TB0> INFO: 1627248 events read in total (61216ms).
[12:03:07.633] <TB0> INFO: 2435224 events read in total (91458ms).
[12:03:38.285] <TB0> INFO: 3240736 events read in total (122109ms).
[12:04:08.516] <TB0> INFO: 4041248 events read in total (152340ms).
[12:04:39.328] <TB0> INFO: 4840808 events read in total (183152ms).
[12:04:46.958] <TB0> INFO: 5025280 events read in total (190782ms).
[12:04:47.022] <TB0> INFO: Test took 191743ms.
[12:05:08.997] <TB0> INFO: ROC 0 VthrComp = 120
[12:05:08.997] <TB0> INFO: ROC 1 VthrComp = 121
[12:05:08.997] <TB0> INFO: ROC 2 VthrComp = 127
[12:05:08.997] <TB0> INFO: ROC 3 VthrComp = 125
[12:05:08.997] <TB0> INFO: ROC 4 VthrComp = 127
[12:05:08.997] <TB0> INFO: ROC 5 VthrComp = 122
[12:05:08.998] <TB0> INFO: ROC 6 VthrComp = 129
[12:05:08.998] <TB0> INFO: ROC 7 VthrComp = 124
[12:05:08.998] <TB0> INFO: ROC 8 VthrComp = 131
[12:05:08.000] <TB0> INFO: ROC 9 VthrComp = 121
[12:05:08.000] <TB0> INFO: ROC 10 VthrComp = 122
[12:05:08.000] <TB0> INFO: ROC 11 VthrComp = 113
[12:05:08.000] <TB0> INFO: ROC 12 VthrComp = 114
[12:05:08.001] <TB0> INFO: ROC 13 VthrComp = 105
[12:05:08.001] <TB0> INFO: ROC 14 VthrComp = 110
[12:05:08.001] <TB0> INFO: ROC 15 VthrComp = 121
[12:05:09.247] <TB0> INFO: Expecting 41600 events.
[12:05:12.951] <TB0> INFO: 41600 events read in total (3107ms).
[12:05:12.951] <TB0> INFO: Test took 3949ms.
[12:05:12.960] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:05:12.960] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:05:12.973] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:05:12.973] <TB0> INFO: run 1 of 1
[12:05:13.251] <TB0> INFO: Expecting 5025280 events.
[12:05:40.404] <TB0> INFO: 592120 events read in total (26561ms).
[12:06:06.314] <TB0> INFO: 1183256 events read in total (52471ms).
[12:06:33.269] <TB0> INFO: 1774360 events read in total (79426ms).
[12:06:59.934] <TB0> INFO: 2364472 events read in total (106091ms).
[12:07:26.685] <TB0> INFO: 2952520 events read in total (132842ms).
[12:07:53.351] <TB0> INFO: 3538680 events read in total (159508ms).
[12:08:19.881] <TB0> INFO: 4123680 events read in total (186038ms).
[12:08:46.177] <TB0> INFO: 4708000 events read in total (212334ms).
[12:09:00.676] <TB0> INFO: 5025280 events read in total (226833ms).
[12:09:00.802] <TB0> INFO: Test took 227829ms.
[12:09:30.261] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 60.7717 for pixel 16/71 mean/min/max = 46.8478/32.8821/60.8134
[12:09:30.262] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 57.1349 for pixel 11/50 mean/min/max = 45.3971/33.5605/57.2336
[12:09:30.262] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 62.4371 for pixel 0/47 mean/min/max = 46.7505/30.8774/62.6235
[12:09:30.262] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 59.4683 for pixel 1/2 mean/min/max = 45.9429/32.3487/59.5372
[12:09:30.263] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 58.5522 for pixel 0/58 mean/min/max = 45.1763/31.7514/58.6013
[12:09:30.263] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 61.2535 for pixel 15/4 mean/min/max = 46.7507/32.2233/61.2781
[12:09:30.264] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 59.8819 for pixel 12/11 mean/min/max = 46.0069/32.0032/60.0106
[12:09:30.264] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 62.9959 for pixel 1/4 mean/min/max = 48.2531/32.6025/63.9038
[12:09:30.265] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 61.815 for pixel 0/60 mean/min/max = 48.4208/35.0238/61.8177
[12:09:30.265] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 57.7732 for pixel 0/3 mean/min/max = 45.6596/33.5221/57.797
[12:09:30.266] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 59.6038 for pixel 4/72 mean/min/max = 45.9992/32.0593/59.9391
[12:09:30.266] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 57.8786 for pixel 21/71 mean/min/max = 45.9531/33.9133/57.9929
[12:09:30.266] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 57.9819 for pixel 28/0 mean/min/max = 45.6397/33.1851/58.0942
[12:09:30.267] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 67.7234 for pixel 0/53 mean/min/max = 49.9936/32.0318/67.9554
[12:09:30.267] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 68.6491 for pixel 5/0 mean/min/max = 50.3404/32.0286/68.6522
[12:09:30.267] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 57.0631 for pixel 21/79 mean/min/max = 45.5313/33.861/57.2017
[12:09:30.268] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:09:30.356] <TB0> INFO: Expecting 411648 events.
[12:09:39.886] <TB0> INFO: 411648 events read in total (8938ms).
[12:09:39.894] <TB0> INFO: Expecting 411648 events.
[12:09:49.226] <TB0> INFO: 411648 events read in total (8927ms).
[12:09:49.239] <TB0> INFO: Expecting 411648 events.
[12:09:58.587] <TB0> INFO: 411648 events read in total (8945ms).
[12:09:58.604] <TB0> INFO: Expecting 411648 events.
[12:10:07.741] <TB0> INFO: 411648 events read in total (8733ms).
[12:10:07.757] <TB0> INFO: Expecting 411648 events.
[12:10:16.857] <TB0> INFO: 411648 events read in total (8697ms).
[12:10:16.887] <TB0> INFO: Expecting 411648 events.
[12:10:26.168] <TB0> INFO: 411648 events read in total (8879ms).
[12:10:26.190] <TB0> INFO: Expecting 411648 events.
[12:10:35.393] <TB0> INFO: 411648 events read in total (8800ms).
[12:10:35.424] <TB0> INFO: Expecting 411648 events.
[12:10:44.634] <TB0> INFO: 411648 events read in total (8807ms).
[12:10:44.662] <TB0> INFO: Expecting 411648 events.
[12:10:53.808] <TB0> INFO: 411648 events read in total (8743ms).
[12:10:53.837] <TB0> INFO: Expecting 411648 events.
[12:11:02.863] <TB0> INFO: 411648 events read in total (8623ms).
[12:11:02.905] <TB0> INFO: Expecting 411648 events.
[12:11:12.193] <TB0> INFO: 411648 events read in total (8885ms).
[12:11:12.237] <TB0> INFO: Expecting 411648 events.
[12:11:21.277] <TB0> INFO: 411648 events read in total (8637ms).
[12:11:21.321] <TB0> INFO: Expecting 411648 events.
[12:11:30.589] <TB0> INFO: 411648 events read in total (8865ms).
[12:11:30.640] <TB0> INFO: Expecting 411648 events.
[12:11:39.883] <TB0> INFO: 411648 events read in total (8840ms).
[12:11:39.944] <TB0> INFO: Expecting 411648 events.
[12:11:49.251] <TB0> INFO: 411648 events read in total (8903ms).
[12:11:49.307] <TB0> INFO: Expecting 411648 events.
[12:11:58.676] <TB0> INFO: 411648 events read in total (8965ms).
[12:11:58.805] <TB0> INFO: Test took 148537ms.
[12:11:59.578] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:11:59.595] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:11:59.596] <TB0> INFO: run 1 of 1
[12:11:59.884] <TB0> INFO: Expecting 5025280 events.
[12:12:27.105] <TB0> INFO: 587984 events read in total (26629ms).
[12:12:53.635] <TB0> INFO: 1174104 events read in total (53159ms).
[12:13:20.470] <TB0> INFO: 1759288 events read in total (79994ms).
[12:13:47.155] <TB0> INFO: 2343000 events read in total (106679ms).
[12:14:13.957] <TB0> INFO: 2926080 events read in total (133481ms).
[12:14:40.715] <TB0> INFO: 3509432 events read in total (160239ms).
[12:15:07.615] <TB0> INFO: 4091408 events read in total (187139ms).
[12:15:34.180] <TB0> INFO: 4674208 events read in total (213704ms).
[12:15:50.766] <TB0> INFO: 5025280 events read in total (230290ms).
[12:15:50.945] <TB0> INFO: Test took 231350ms.
[12:16:19.921] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 10.336256 .. 143.997141
[12:16:20.271] <TB0> INFO: Expecting 208000 events.
[12:16:30.523] <TB0> INFO: 208000 events read in total (9661ms).
[12:16:30.525] <TB0> INFO: Test took 10603ms.
[12:16:30.573] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 153 (-1/-1) hits flags = 528 (plus default)
[12:16:30.587] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:16:30.587] <TB0> INFO: run 1 of 1
[12:16:30.865] <TB0> INFO: Expecting 5125120 events.
[12:16:58.078] <TB0> INFO: 585544 events read in total (26619ms).
[12:17:24.625] <TB0> INFO: 1171040 events read in total (53166ms).
[12:17:51.882] <TB0> INFO: 1756848 events read in total (80423ms).
[12:18:18.784] <TB0> INFO: 2343256 events read in total (107326ms).
[12:18:45.976] <TB0> INFO: 2929656 events read in total (134517ms).
[12:19:12.646] <TB0> INFO: 3515480 events read in total (161187ms).
[12:19:39.367] <TB0> INFO: 4101112 events read in total (187908ms).
[12:20:06.260] <TB0> INFO: 4685840 events read in total (214801ms).
[12:20:26.381] <TB0> INFO: 5125120 events read in total (234922ms).
[12:20:26.564] <TB0> INFO: Test took 235977ms.
[12:20:59.029] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 27.154852 .. 46.566576
[12:20:59.356] <TB0> INFO: Expecting 208000 events.
[12:21:09.654] <TB0> INFO: 208000 events read in total (9703ms).
[12:21:09.655] <TB0> INFO: Test took 10624ms.
[12:21:09.704] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[12:21:09.718] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:21:09.718] <TB0> INFO: run 1 of 1
[12:21:09.996] <TB0> INFO: Expecting 1331200 events.
[12:21:38.886] <TB0> INFO: 655928 events read in total (28297ms).
[12:22:07.019] <TB0> INFO: 1311024 events read in total (56430ms).
[12:22:08.404] <TB0> INFO: 1331200 events read in total (57816ms).
[12:22:08.439] <TB0> INFO: Test took 58722ms.
[12:22:23.658] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 26.180205 .. 47.626153
[12:22:23.907] <TB0> INFO: Expecting 208000 events.
[12:22:34.348] <TB0> INFO: 208000 events read in total (9849ms).
[12:22:34.350] <TB0> INFO: Test took 10691ms.
[12:22:34.399] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[12:22:34.414] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:22:34.415] <TB0> INFO: run 1 of 1
[12:22:34.696] <TB0> INFO: Expecting 1397760 events.
[12:23:03.741] <TB0> INFO: 656120 events read in total (28454ms).
[12:23:31.870] <TB0> INFO: 1312640 events read in total (56583ms).
[12:23:35.940] <TB0> INFO: 1397760 events read in total (60653ms).
[12:23:35.976] <TB0> INFO: Test took 61562ms.
[12:23:52.691] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 26.367353 .. 49.532134
[12:23:52.930] <TB0> INFO: Expecting 208000 events.
[12:24:03.283] <TB0> INFO: 208000 events read in total (9761ms).
[12:24:03.284] <TB0> INFO: Test took 10592ms.
[12:24:03.364] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 59 (-1/-1) hits flags = 528 (plus default)
[12:24:03.379] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:24:03.379] <TB0> INFO: run 1 of 1
[12:24:03.703] <TB0> INFO: Expecting 1464320 events.
[12:24:32.209] <TB0> INFO: 649016 events read in total (27914ms).
[12:24:59.951] <TB0> INFO: 1297992 events read in total (55656ms).
[12:25:07.539] <TB0> INFO: 1464320 events read in total (63244ms).
[12:25:07.577] <TB0> INFO: Test took 64199ms.
[12:25:23.777] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:25:23.778] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:25:23.792] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:25:23.792] <TB0> INFO: run 1 of 1
[12:25:24.117] <TB0> INFO: Expecting 1364480 events.
[12:25:54.388] <TB0> INFO: 668024 events read in total (29679ms).
[12:26:23.377] <TB0> INFO: 1335704 events read in total (58668ms).
[12:26:25.034] <TB0> INFO: 1364480 events read in total (60326ms).
[12:26:25.067] <TB0> INFO: Test took 61275ms.
[12:26:42.455] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C0.dat
[12:26:42.456] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C1.dat
[12:26:42.456] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C2.dat
[12:26:42.456] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C3.dat
[12:26:42.456] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C4.dat
[12:26:42.456] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C5.dat
[12:26:42.456] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C6.dat
[12:26:42.456] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C7.dat
[12:26:42.457] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C8.dat
[12:26:42.457] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C9.dat
[12:26:42.457] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C10.dat
[12:26:42.457] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C11.dat
[12:26:42.457] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C12.dat
[12:26:42.457] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C13.dat
[12:26:42.457] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C14.dat
[12:26:42.457] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C15.dat
[12:26:42.457] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C0.dat
[12:26:42.464] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C1.dat
[12:26:42.469] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C2.dat
[12:26:42.474] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C3.dat
[12:26:42.480] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C4.dat
[12:26:42.485] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C5.dat
[12:26:42.490] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C6.dat
[12:26:42.496] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C7.dat
[12:26:42.501] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C8.dat
[12:26:42.506] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C9.dat
[12:26:42.511] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C10.dat
[12:26:42.516] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C11.dat
[12:26:42.521] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C12.dat
[12:26:42.525] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C13.dat
[12:26:42.530] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C14.dat
[12:26:42.535] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters35_C15.dat
[12:26:42.540] <TB0> INFO: PixTestTrim::trimTest() done
[12:26:42.540] <TB0> INFO: vtrim: 116 121 129 117 123 143 130 131 119 104 138 118 116 142 179 127
[12:26:42.540] <TB0> INFO: vthrcomp: 120 121 127 125 127 122 129 124 131 121 122 113 114 105 110 121
[12:26:42.540] <TB0> INFO: vcal mean: 35.01 34.95 35.58 35.14 35.06 35.02 34.98 35.28 34.99 34.91 35.00 35.02 35.01 34.99 35.05 34.96
[12:26:42.540] <TB0> INFO: vcal RMS: 1.11 1.01 1.73 1.29 1.21 1.09 1.07 1.55 0.93 0.98 1.06 1.12 0.96 1.02 1.23 0.97
[12:26:42.540] <TB0> INFO: bits mean: 9.24 9.34 9.57 9.43 9.57 9.84 9.63 9.29 7.89 8.56 9.67 9.65 9.34 8.48 9.44 9.47
[12:26:42.540] <TB0> INFO: bits RMS: 2.67 2.63 3.01 2.77 2.83 2.56 2.66 2.73 2.75 2.95 2.65 2.42 2.72 2.87 2.53 2.51
[12:26:42.548] <TB0> INFO: ----------------------------------------------------------------------
[12:26:42.548] <TB0> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:26:42.548] <TB0> INFO: ----------------------------------------------------------------------
[12:26:42.550] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:26:42.564] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:26:42.564] <TB0> INFO: run 1 of 1
[12:26:42.805] <TB0> INFO: Expecting 4160000 events.
[12:27:15.550] <TB0> INFO: 744510 events read in total (32153ms).
[12:27:47.203] <TB0> INFO: 1480025 events read in total (63806ms).
[12:28:19.187] <TB0> INFO: 2208820 events read in total (95790ms).
[12:28:51.479] <TB0> INFO: 2930640 events read in total (128082ms).
[12:29:23.239] <TB0> INFO: 3648530 events read in total (159842ms).
[12:29:45.267] <TB0> INFO: 4160000 events read in total (181870ms).
[12:29:45.345] <TB0> INFO: Test took 182781ms.
[12:30:20.159] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 202 (-1/-1) hits flags = 528 (plus default)
[12:30:20.173] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:30:20.173] <TB0> INFO: run 1 of 1
[12:30:20.432] <TB0> INFO: Expecting 4222400 events.
[12:30:52.285] <TB0> INFO: 717180 events read in total (31261ms).
[12:31:23.025] <TB0> INFO: 1426535 events read in total (62001ms).
[12:31:54.171] <TB0> INFO: 2130280 events read in total (93147ms).
[12:32:25.158] <TB0> INFO: 2828360 events read in total (124134ms).
[12:32:55.701] <TB0> INFO: 3522405 events read in total (154677ms).
[12:33:27.032] <TB0> INFO: 4217845 events read in total (186008ms).
[12:33:27.662] <TB0> INFO: 4222400 events read in total (186638ms).
[12:33:27.755] <TB0> INFO: Test took 187582ms.
[12:34:01.807] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:34:01.823] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:34:01.823] <TB0> INFO: run 1 of 1
[12:34:02.126] <TB0> INFO: Expecting 4160000 events.
[12:34:33.892] <TB0> INFO: 720940 events read in total (31174ms).
[12:35:04.986] <TB0> INFO: 1433720 events read in total (62268ms).
[12:35:36.081] <TB0> INFO: 2140875 events read in total (93363ms).
[12:36:06.787] <TB0> INFO: 2841810 events read in total (124069ms).
[12:36:37.133] <TB0> INFO: 3538665 events read in total (154415ms).
[12:37:05.471] <TB0> INFO: 4160000 events read in total (182753ms).
[12:37:05.565] <TB0> INFO: Test took 183742ms.
[12:37:39.867] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:37:39.884] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:37:39.884] <TB0> INFO: run 1 of 1
[12:37:40.210] <TB0> INFO: Expecting 4160000 events.
[12:38:11.000] <TB0> INFO: 720700 events read in total (31198ms).
[12:38:42.914] <TB0> INFO: 1432985 events read in total (62112ms).
[12:39:13.000] <TB0> INFO: 2139855 events read in total (93198ms).
[12:39:45.409] <TB0> INFO: 2840470 events read in total (124607ms).
[12:40:15.955] <TB0> INFO: 3536985 events read in total (155153ms).
[12:40:44.232] <TB0> INFO: 4160000 events read in total (183430ms).
[12:40:44.340] <TB0> INFO: Test took 184456ms.
[12:41:21.114] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 192 (-1/-1) hits flags = 528 (plus default)
[12:41:21.131] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:41:21.131] <TB0> INFO: run 1 of 1
[12:41:21.410] <TB0> INFO: Expecting 4014400 events.
[12:41:53.799] <TB0> INFO: 729670 events read in total (31798ms).
[12:42:24.822] <TB0> INFO: 1450325 events read in total (62821ms).
[12:42:56.330] <TB0> INFO: 2164725 events read in total (94329ms).
[12:43:27.239] <TB0> INFO: 2872535 events read in total (125238ms).
[12:43:57.791] <TB0> INFO: 3576665 events read in total (155790ms).
[12:44:17.605] <TB0> INFO: 4014400 events read in total (175604ms).
[12:44:17.749] <TB0> INFO: Test took 176618ms.
[12:44:54.911] <TB0> INFO: PixTestTrim::trimBitTest() done
[12:44:54.912] <TB0> INFO: PixTestTrim::doTest() done, duration: 2599 seconds
[12:44:54.912] <TB0> INFO: Decoding statistics:
[12:44:54.912] <TB0> INFO: General information:
[12:44:54.912] <TB0> INFO: 16bit words read: 0
[12:44:54.912] <TB0> INFO: valid events total: 0
[12:44:54.912] <TB0> INFO: empty events: 0
[12:44:54.912] <TB0> INFO: valid events with pixels: 0
[12:44:54.912] <TB0> INFO: valid pixel hits: 0
[12:44:54.912] <TB0> INFO: Event errors: 0
[12:44:54.912] <TB0> INFO: start marker: 0
[12:44:54.912] <TB0> INFO: stop marker: 0
[12:44:54.912] <TB0> INFO: overflow: 0
[12:44:54.912] <TB0> INFO: invalid 5bit words: 0
[12:44:54.912] <TB0> INFO: invalid XOR eye diagram: 0
[12:44:54.912] <TB0> INFO: frame (failed synchr.): 0
[12:44:54.912] <TB0> INFO: idle data (no TBM trl): 0
[12:44:54.912] <TB0> INFO: no data (only TBM hdr): 0
[12:44:54.912] <TB0> INFO: TBM errors: 0
[12:44:54.912] <TB0> INFO: flawed TBM headers: 0
[12:44:54.912] <TB0> INFO: flawed TBM trailers: 0
[12:44:54.912] <TB0> INFO: event ID mismatches: 0
[12:44:54.912] <TB0> INFO: ROC errors: 0
[12:44:54.912] <TB0> INFO: missing ROC header(s): 0
[12:44:54.912] <TB0> INFO: misplaced readback start: 0
[12:44:54.912] <TB0> INFO: Pixel decoding errors: 0
[12:44:54.912] <TB0> INFO: pixel data incomplete: 0
[12:44:54.912] <TB0> INFO: pixel address: 0
[12:44:54.913] <TB0> INFO: pulse height fill bit: 0
[12:44:54.913] <TB0> INFO: buffer corruption: 0
[12:44:55.791] <TB0> INFO: ######################################################################
[12:44:55.791] <TB0> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:44:55.791] <TB0> INFO: ######################################################################
[12:44:56.104] <TB0> INFO: Expecting 41600 events.
[12:44:59.585] <TB0> INFO: 41600 events read in total (2889ms).
[12:44:59.586] <TB0> INFO: Test took 3794ms.
[12:45:00.039] <TB0> INFO: Expecting 41600 events.
[12:45:03.766] <TB0> INFO: 41600 events read in total (3133ms).
[12:45:03.767] <TB0> INFO: Test took 3973ms.
[12:45:04.062] <TB0> INFO: Expecting 41600 events.
[12:45:07.663] <TB0> INFO: 41600 events read in total (3009ms).
[12:45:07.663] <TB0> INFO: Test took 3871ms.
[12:45:07.953] <TB0> INFO: Expecting 41600 events.
[12:45:11.582] <TB0> INFO: 41600 events read in total (3038ms).
[12:45:11.583] <TB0> INFO: Test took 3895ms.
[12:45:11.891] <TB0> INFO: Expecting 41600 events.
[12:45:15.693] <TB0> INFO: 41600 events read in total (3211ms).
[12:45:15.695] <TB0> INFO: Test took 4083ms.
[12:45:16.069] <TB0> INFO: Expecting 41600 events.
[12:45:19.821] <TB0> INFO: 41600 events read in total (3160ms).
[12:45:19.822] <TB0> INFO: Test took 4094ms.
[12:45:20.135] <TB0> INFO: Expecting 41600 events.
[12:45:23.791] <TB0> INFO: 41600 events read in total (3064ms).
[12:45:23.792] <TB0> INFO: Test took 3941ms.
[12:45:24.112] <TB0> INFO: Expecting 41600 events.
[12:45:27.792] <TB0> INFO: 41600 events read in total (3089ms).
[12:45:27.793] <TB0> INFO: Test took 3971ms.
[12:45:28.086] <TB0> INFO: Expecting 41600 events.
[12:45:31.616] <TB0> INFO: 41600 events read in total (2939ms).
[12:45:31.617] <TB0> INFO: Test took 3796ms.
[12:45:31.906] <TB0> INFO: Expecting 41600 events.
[12:45:35.499] <TB0> INFO: 41600 events read in total (3001ms).
[12:45:35.500] <TB0> INFO: Test took 3859ms.
[12:45:35.818] <TB0> INFO: Expecting 41600 events.
[12:45:39.352] <TB0> INFO: 41600 events read in total (2942ms).
[12:45:39.354] <TB0> INFO: Test took 3826ms.
[12:45:39.692] <TB0> INFO: Expecting 41600 events.
[12:45:43.549] <TB0> INFO: 41600 events read in total (3266ms).
[12:45:43.550] <TB0> INFO: Test took 4170ms.
[12:45:43.839] <TB0> INFO: Expecting 41600 events.
[12:45:47.416] <TB0> INFO: 41600 events read in total (2985ms).
[12:45:47.417] <TB0> INFO: Test took 3842ms.
[12:45:47.706] <TB0> INFO: Expecting 41600 events.
[12:45:51.232] <TB0> INFO: 41600 events read in total (2934ms).
[12:45:51.233] <TB0> INFO: Test took 3792ms.
[12:45:51.522] <TB0> INFO: Expecting 41600 events.
[12:45:55.136] <TB0> INFO: 41600 events read in total (3022ms).
[12:45:55.137] <TB0> INFO: Test took 3880ms.
[12:45:55.499] <TB0> INFO: Expecting 41600 events.
[12:45:59.198] <TB0> INFO: 41600 events read in total (3108ms).
[12:45:59.199] <TB0> INFO: Test took 4037ms.
[12:45:59.488] <TB0> INFO: Expecting 41600 events.
[12:46:03.015] <TB0> INFO: 41600 events read in total (2934ms).
[12:46:03.016] <TB0> INFO: Test took 3793ms.
[12:46:03.307] <TB0> INFO: Expecting 41600 events.
[12:46:06.816] <TB0> INFO: 41600 events read in total (2917ms).
[12:46:06.818] <TB0> INFO: Test took 3776ms.
[12:46:07.108] <TB0> INFO: Expecting 41600 events.
[12:46:10.664] <TB0> INFO: 41600 events read in total (2965ms).
[12:46:10.665] <TB0> INFO: Test took 3822ms.
[12:46:10.956] <TB0> INFO: Expecting 41600 events.
[12:46:14.658] <TB0> INFO: 41600 events read in total (3111ms).
[12:46:14.659] <TB0> INFO: Test took 3968ms.
[12:46:14.951] <TB0> INFO: Expecting 41600 events.
[12:46:18.619] <TB0> INFO: 41600 events read in total (3076ms).
[12:46:18.620] <TB0> INFO: Test took 3934ms.
[12:46:19.033] <TB0> INFO: Expecting 41600 events.
[12:46:22.528] <TB0> INFO: 41600 events read in total (2903ms).
[12:46:22.529] <TB0> INFO: Test took 3877ms.
[12:46:22.826] <TB0> INFO: Expecting 41600 events.
[12:46:26.395] <TB0> INFO: 41600 events read in total (2977ms).
[12:46:26.395] <TB0> INFO: Test took 3839ms.
[12:46:26.698] <TB0> INFO: Expecting 41600 events.
[12:46:30.320] <TB0> INFO: 41600 events read in total (3030ms).
[12:46:30.320] <TB0> INFO: Test took 3900ms.
[12:46:30.610] <TB0> INFO: Expecting 41600 events.
[12:46:34.164] <TB0> INFO: 41600 events read in total (2962ms).
[12:46:34.165] <TB0> INFO: Test took 3820ms.
[12:46:34.455] <TB0> INFO: Expecting 41600 events.
[12:46:38.191] <TB0> INFO: 41600 events read in total (3144ms).
[12:46:38.192] <TB0> INFO: Test took 4002ms.
[12:46:38.532] <TB0> INFO: Expecting 41600 events.
[12:46:42.119] <TB0> INFO: 41600 events read in total (2994ms).
[12:46:42.120] <TB0> INFO: Test took 3898ms.
[12:46:42.413] <TB0> INFO: Expecting 41600 events.
[12:46:46.029] <TB0> INFO: 41600 events read in total (3025ms).
[12:46:46.030] <TB0> INFO: Test took 3882ms.
[12:46:46.323] <TB0> INFO: Expecting 2560 events.
[12:46:47.208] <TB0> INFO: 2560 events read in total (292ms).
[12:46:47.208] <TB0> INFO: Test took 1162ms.
[12:46:47.516] <TB0> INFO: Expecting 2560 events.
[12:46:48.402] <TB0> INFO: 2560 events read in total (294ms).
[12:46:48.402] <TB0> INFO: Test took 1193ms.
[12:46:48.710] <TB0> INFO: Expecting 2560 events.
[12:46:49.593] <TB0> INFO: 2560 events read in total (291ms).
[12:46:49.593] <TB0> INFO: Test took 1191ms.
[12:46:49.901] <TB0> INFO: Expecting 2560 events.
[12:46:50.793] <TB0> INFO: 2560 events read in total (300ms).
[12:46:50.793] <TB0> INFO: Test took 1199ms.
[12:46:51.101] <TB0> INFO: Expecting 2560 events.
[12:46:51.984] <TB0> INFO: 2560 events read in total (292ms).
[12:46:51.984] <TB0> INFO: Test took 1191ms.
[12:46:52.292] <TB0> INFO: Expecting 2560 events.
[12:46:53.174] <TB0> INFO: 2560 events read in total (290ms).
[12:46:53.174] <TB0> INFO: Test took 1189ms.
[12:46:53.482] <TB0> INFO: Expecting 2560 events.
[12:46:54.362] <TB0> INFO: 2560 events read in total (288ms).
[12:46:54.362] <TB0> INFO: Test took 1187ms.
[12:46:54.670] <TB0> INFO: Expecting 2560 events.
[12:46:55.549] <TB0> INFO: 2560 events read in total (288ms).
[12:46:55.549] <TB0> INFO: Test took 1186ms.
[12:46:55.857] <TB0> INFO: Expecting 2560 events.
[12:46:56.736] <TB0> INFO: 2560 events read in total (288ms).
[12:46:56.736] <TB0> INFO: Test took 1186ms.
[12:46:57.044] <TB0> INFO: Expecting 2560 events.
[12:46:57.923] <TB0> INFO: 2560 events read in total (286ms).
[12:46:57.924] <TB0> INFO: Test took 1187ms.
[12:46:58.232] <TB0> INFO: Expecting 2560 events.
[12:46:59.112] <TB0> INFO: 2560 events read in total (289ms).
[12:46:59.112] <TB0> INFO: Test took 1187ms.
[12:46:59.420] <TB0> INFO: Expecting 2560 events.
[12:47:00.299] <TB0> INFO: 2560 events read in total (287ms).
[12:47:00.299] <TB0> INFO: Test took 1186ms.
[12:47:00.607] <TB0> INFO: Expecting 2560 events.
[12:47:01.494] <TB0> INFO: 2560 events read in total (295ms).
[12:47:01.494] <TB0> INFO: Test took 1195ms.
[12:47:01.802] <TB0> INFO: Expecting 2560 events.
[12:47:02.688] <TB0> INFO: 2560 events read in total (294ms).
[12:47:02.688] <TB0> INFO: Test took 1193ms.
[12:47:02.996] <TB0> INFO: Expecting 2560 events.
[12:47:03.880] <TB0> INFO: 2560 events read in total (292ms).
[12:47:03.881] <TB0> INFO: Test took 1192ms.
[12:47:04.189] <TB0> INFO: Expecting 2560 events.
[12:47:05.073] <TB0> INFO: 2560 events read in total (292ms).
[12:47:05.073] <TB0> INFO: Test took 1192ms.
[12:47:05.076] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:05.382] <TB0> INFO: Expecting 655360 events.
[12:47:19.976] <TB0> INFO: 655360 events read in total (14003ms).
[12:47:19.993] <TB0> INFO: Expecting 655360 events.
[12:47:34.443] <TB0> INFO: 655360 events read in total (14047ms).
[12:47:34.468] <TB0> INFO: Expecting 655360 events.
[12:47:48.823] <TB0> INFO: 655360 events read in total (13952ms).
[12:47:48.849] <TB0> INFO: Expecting 655360 events.
[12:48:03.243] <TB0> INFO: 655360 events read in total (13989ms).
[12:48:03.273] <TB0> INFO: Expecting 655360 events.
[12:48:17.615] <TB0> INFO: 655360 events read in total (13939ms).
[12:48:17.654] <TB0> INFO: Expecting 655360 events.
[12:48:32.017] <TB0> INFO: 655360 events read in total (13960ms).
[12:48:32.077] <TB0> INFO: Expecting 655360 events.
[12:48:46.468] <TB0> INFO: 655360 events read in total (13987ms).
[12:48:46.524] <TB0> INFO: Expecting 655360 events.
[12:49:00.743] <TB0> INFO: 655360 events read in total (13816ms).
[12:49:00.798] <TB0> INFO: Expecting 655360 events.
[12:49:14.988] <TB0> INFO: 655360 events read in total (13787ms).
[12:49:15.050] <TB0> INFO: Expecting 655360 events.
[12:49:29.470] <TB0> INFO: 655360 events read in total (14016ms).
[12:49:29.560] <TB0> INFO: Expecting 655360 events.
[12:49:43.844] <TB0> INFO: 655360 events read in total (13881ms).
[12:49:43.937] <TB0> INFO: Expecting 655360 events.
[12:49:58.175] <TB0> INFO: 655360 events read in total (13835ms).
[12:49:58.264] <TB0> INFO: Expecting 655360 events.
[12:50:12.573] <TB0> INFO: 655360 events read in total (13906ms).
[12:50:12.662] <TB0> INFO: Expecting 655360 events.
[12:50:26.905] <TB0> INFO: 655360 events read in total (13840ms).
[12:50:27.026] <TB0> INFO: Expecting 655360 events.
[12:50:41.368] <TB0> INFO: 655360 events read in total (13939ms).
[12:50:41.517] <TB0> INFO: Expecting 655360 events.
[12:50:55.859] <TB0> INFO: 655360 events read in total (13939ms).
[12:50:55.990] <TB0> INFO: Test took 230914ms.
[12:50:56.102] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:50:56.354] <TB0> INFO: Expecting 655360 events.
[12:51:10.755] <TB0> INFO: 655360 events read in total (13807ms).
[12:51:10.773] <TB0> INFO: Expecting 655360 events.
[12:51:24.795] <TB0> INFO: 655360 events read in total (13619ms).
[12:51:24.816] <TB0> INFO: Expecting 655360 events.
[12:51:39.061] <TB0> INFO: 655360 events read in total (13842ms).
[12:51:39.085] <TB0> INFO: Expecting 655360 events.
[12:51:53.153] <TB0> INFO: 655360 events read in total (13665ms).
[12:51:53.190] <TB0> INFO: Expecting 655360 events.
[12:52:07.235] <TB0> INFO: 655360 events read in total (13642ms).
[12:52:07.269] <TB0> INFO: Expecting 655360 events.
[12:52:21.465] <TB0> INFO: 655360 events read in total (13793ms).
[12:52:21.503] <TB0> INFO: Expecting 655360 events.
[12:52:35.839] <TB0> INFO: 655360 events read in total (13933ms).
[12:52:35.885] <TB0> INFO: Expecting 655360 events.
[12:52:50.118] <TB0> INFO: 655360 events read in total (13825ms).
[12:52:50.193] <TB0> INFO: Expecting 655360 events.
[12:53:04.528] <TB0> INFO: 655360 events read in total (13932ms).
[12:53:04.592] <TB0> INFO: Expecting 655360 events.
[12:53:18.689] <TB0> INFO: 655360 events read in total (13694ms).
[12:53:18.816] <TB0> INFO: Expecting 655360 events.
[12:53:33.249] <TB0> INFO: 655360 events read in total (14030ms).
[12:53:33.367] <TB0> INFO: Expecting 655360 events.
[12:53:47.690] <TB0> INFO: 655360 events read in total (13920ms).
[12:53:47.782] <TB0> INFO: Expecting 655360 events.
[12:54:02.095] <TB0> INFO: 655360 events read in total (13910ms).
[12:54:02.226] <TB0> INFO: Expecting 655360 events.
[12:54:16.558] <TB0> INFO: 655360 events read in total (13929ms).
[12:54:16.662] <TB0> INFO: Expecting 655360 events.
[12:54:30.664] <TB0> INFO: 655360 events read in total (13599ms).
[12:54:30.790] <TB0> INFO: Expecting 655360 events.
[12:54:45.031] <TB0> INFO: 655360 events read in total (13838ms).
[12:54:45.138] <TB0> INFO: Test took 229037ms.
[12:54:45.329] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.335] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[12:54:45.341] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[12:54:45.347] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.353] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[12:54:45.360] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[12:54:45.367] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.374] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.381] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.387] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.393] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.399] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.405] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.411] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[12:54:45.417] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[12:54:45.423] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[12:54:45.429] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[12:54:45.435] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[12:54:45.441] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[12:54:45.447] <TB0> INFO: safety margin for low PH: adding 7, margin is now 27
[12:54:45.453] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.459] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.464] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.470] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[12:54:45.476] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[12:54:45.482] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[12:54:45.487] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.493] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.498] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[12:54:45.504] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[12:54:45.510] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[12:54:45.515] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[12:54:45.521] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.527] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:45.558] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C0.dat
[12:54:45.559] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C1.dat
[12:54:45.559] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C2.dat
[12:54:45.559] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C3.dat
[12:54:45.559] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C4.dat
[12:54:45.559] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C5.dat
[12:54:45.559] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C6.dat
[12:54:45.560] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C7.dat
[12:54:45.560] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C8.dat
[12:54:45.560] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C9.dat
[12:54:45.560] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C10.dat
[12:54:45.560] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C11.dat
[12:54:45.560] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C12.dat
[12:54:45.560] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C13.dat
[12:54:45.560] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C14.dat
[12:54:45.560] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters35_C15.dat
[12:54:45.800] <TB0> INFO: Expecting 41600 events.
[12:54:48.944] <TB0> INFO: 41600 events read in total (2552ms).
[12:54:48.945] <TB0> INFO: Test took 3382ms.
[12:54:49.394] <TB0> INFO: Expecting 41600 events.
[12:54:52.409] <TB0> INFO: 41600 events read in total (2423ms).
[12:54:52.410] <TB0> INFO: Test took 3253ms.
[12:54:52.866] <TB0> INFO: Expecting 41600 events.
[12:54:56.023] <TB0> INFO: 41600 events read in total (2565ms).
[12:54:56.025] <TB0> INFO: Test took 3402ms.
[12:54:56.242] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:56.339] <TB0> INFO: Expecting 2560 events.
[12:54:57.226] <TB0> INFO: 2560 events read in total (296ms).
[12:54:57.227] <TB0> INFO: Test took 985ms.
[12:54:57.229] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:57.535] <TB0> INFO: Expecting 2560 events.
[12:54:58.421] <TB0> INFO: 2560 events read in total (294ms).
[12:54:58.422] <TB0> INFO: Test took 1193ms.
[12:54:58.424] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:58.729] <TB0> INFO: Expecting 2560 events.
[12:54:59.612] <TB0> INFO: 2560 events read in total (291ms).
[12:54:59.613] <TB0> INFO: Test took 1189ms.
[12:54:59.615] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:59.921] <TB0> INFO: Expecting 2560 events.
[12:55:00.804] <TB0> INFO: 2560 events read in total (292ms).
[12:55:00.805] <TB0> INFO: Test took 1190ms.
[12:55:00.808] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:01.113] <TB0> INFO: Expecting 2560 events.
[12:55:01.000] <TB0> INFO: 2560 events read in total (295ms).
[12:55:01.000] <TB0> INFO: Test took 1192ms.
[12:55:02.005] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:02.308] <TB0> INFO: Expecting 2560 events.
[12:55:03.192] <TB0> INFO: 2560 events read in total (292ms).
[12:55:03.192] <TB0> INFO: Test took 1187ms.
[12:55:03.196] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:03.501] <TB0> INFO: Expecting 2560 events.
[12:55:04.385] <TB0> INFO: 2560 events read in total (293ms).
[12:55:04.385] <TB0> INFO: Test took 1189ms.
[12:55:04.391] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:04.693] <TB0> INFO: Expecting 2560 events.
[12:55:05.579] <TB0> INFO: 2560 events read in total (294ms).
[12:55:05.580] <TB0> INFO: Test took 1189ms.
[12:55:05.583] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:05.888] <TB0> INFO: Expecting 2560 events.
[12:55:06.767] <TB0> INFO: 2560 events read in total (287ms).
[12:55:06.768] <TB0> INFO: Test took 1185ms.
[12:55:06.770] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:07.076] <TB0> INFO: Expecting 2560 events.
[12:55:07.958] <TB0> INFO: 2560 events read in total (291ms).
[12:55:07.958] <TB0> INFO: Test took 1188ms.
[12:55:07.960] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:08.267] <TB0> INFO: Expecting 2560 events.
[12:55:09.145] <TB0> INFO: 2560 events read in total (287ms).
[12:55:09.146] <TB0> INFO: Test took 1186ms.
[12:55:09.148] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:09.454] <TB0> INFO: Expecting 2560 events.
[12:55:10.333] <TB0> INFO: 2560 events read in total (287ms).
[12:55:10.333] <TB0> INFO: Test took 1186ms.
[12:55:10.336] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:10.642] <TB0> INFO: Expecting 2560 events.
[12:55:11.521] <TB0> INFO: 2560 events read in total (288ms).
[12:55:11.521] <TB0> INFO: Test took 1185ms.
[12:55:11.524] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:11.829] <TB0> INFO: Expecting 2560 events.
[12:55:12.708] <TB0> INFO: 2560 events read in total (287ms).
[12:55:12.709] <TB0> INFO: Test took 1185ms.
[12:55:12.711] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:13.017] <TB0> INFO: Expecting 2560 events.
[12:55:13.899] <TB0> INFO: 2560 events read in total (290ms).
[12:55:13.900] <TB0> INFO: Test took 1190ms.
[12:55:13.902] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:14.207] <TB0> INFO: Expecting 2560 events.
[12:55:15.089] <TB0> INFO: 2560 events read in total (290ms).
[12:55:15.089] <TB0> INFO: Test took 1187ms.
[12:55:15.091] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:15.398] <TB0> INFO: Expecting 2560 events.
[12:55:16.277] <TB0> INFO: 2560 events read in total (288ms).
[12:55:16.278] <TB0> INFO: Test took 1187ms.
[12:55:16.281] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:16.586] <TB0> INFO: Expecting 2560 events.
[12:55:17.466] <TB0> INFO: 2560 events read in total (288ms).
[12:55:17.466] <TB0> INFO: Test took 1186ms.
[12:55:17.468] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:17.778] <TB0> INFO: Expecting 2560 events.
[12:55:18.656] <TB0> INFO: 2560 events read in total (287ms).
[12:55:18.657] <TB0> INFO: Test took 1189ms.
[12:55:18.660] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:18.965] <TB0> INFO: Expecting 2560 events.
[12:55:19.846] <TB0> INFO: 2560 events read in total (289ms).
[12:55:19.846] <TB0> INFO: Test took 1186ms.
[12:55:19.848] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:20.155] <TB0> INFO: Expecting 2560 events.
[12:55:21.033] <TB0> INFO: 2560 events read in total (286ms).
[12:55:21.034] <TB0> INFO: Test took 1186ms.
[12:55:21.036] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:21.342] <TB0> INFO: Expecting 2560 events.
[12:55:22.221] <TB0> INFO: 2560 events read in total (287ms).
[12:55:22.221] <TB0> INFO: Test took 1186ms.
[12:55:22.223] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:22.530] <TB0> INFO: Expecting 2560 events.
[12:55:23.413] <TB0> INFO: 2560 events read in total (291ms).
[12:55:23.413] <TB0> INFO: Test took 1190ms.
[12:55:23.415] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:23.721] <TB0> INFO: Expecting 2560 events.
[12:55:24.600] <TB0> INFO: 2560 events read in total (287ms).
[12:55:24.600] <TB0> INFO: Test took 1185ms.
[12:55:24.602] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:24.909] <TB0> INFO: Expecting 2560 events.
[12:55:25.794] <TB0> INFO: 2560 events read in total (293ms).
[12:55:25.794] <TB0> INFO: Test took 1192ms.
[12:55:25.796] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:26.102] <TB0> INFO: Expecting 2560 events.
[12:55:26.986] <TB0> INFO: 2560 events read in total (292ms).
[12:55:26.986] <TB0> INFO: Test took 1190ms.
[12:55:26.989] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:27.295] <TB0> INFO: Expecting 2560 events.
[12:55:28.181] <TB0> INFO: 2560 events read in total (295ms).
[12:55:28.181] <TB0> INFO: Test took 1192ms.
[12:55:28.183] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:28.490] <TB0> INFO: Expecting 2560 events.
[12:55:29.376] <TB0> INFO: 2560 events read in total (295ms).
[12:55:29.376] <TB0> INFO: Test took 1193ms.
[12:55:29.378] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:29.685] <TB0> INFO: Expecting 2560 events.
[12:55:30.568] <TB0> INFO: 2560 events read in total (292ms).
[12:55:30.568] <TB0> INFO: Test took 1190ms.
[12:55:30.571] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:30.876] <TB0> INFO: Expecting 2560 events.
[12:55:31.760] <TB0> INFO: 2560 events read in total (292ms).
[12:55:31.760] <TB0> INFO: Test took 1189ms.
[12:55:31.763] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:32.069] <TB0> INFO: Expecting 2560 events.
[12:55:32.953] <TB0> INFO: 2560 events read in total (292ms).
[12:55:32.954] <TB0> INFO: Test took 1191ms.
[12:55:32.956] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:33.264] <TB0> INFO: Expecting 2560 events.
[12:55:34.146] <TB0> INFO: 2560 events read in total (290ms).
[12:55:34.146] <TB0> INFO: Test took 1190ms.
[12:55:34.613] <TB0> INFO: PixTestPhOptimization::doTest() done, duration: 638 seconds
[12:55:34.613] <TB0> INFO: PH scale (per ROC): 48 34 48 42 44 45 44 43 48 55 43 42 47 40 40 41
[12:55:34.613] <TB0> INFO: PH offset (per ROC): 93 95 111 108 82 111 99 84 90 129 108 101 98 97 88 94
[12:55:34.622] <TB0> INFO: Decoding statistics:
[12:55:34.622] <TB0> INFO: General information:
[12:55:34.622] <TB0> INFO: 16bit words read: 127880
[12:55:34.622] <TB0> INFO: valid events total: 20480
[12:55:34.622] <TB0> INFO: empty events: 17980
[12:55:34.622] <TB0> INFO: valid events with pixels: 2500
[12:55:34.622] <TB0> INFO: valid pixel hits: 2500
[12:55:34.622] <TB0> INFO: Event errors: 0
[12:55:34.622] <TB0> INFO: start marker: 0
[12:55:34.622] <TB0> INFO: stop marker: 0
[12:55:34.622] <TB0> INFO: overflow: 0
[12:55:34.622] <TB0> INFO: invalid 5bit words: 0
[12:55:34.622] <TB0> INFO: invalid XOR eye diagram: 0
[12:55:34.622] <TB0> INFO: frame (failed synchr.): 0
[12:55:34.622] <TB0> INFO: idle data (no TBM trl): 0
[12:55:34.622] <TB0> INFO: no data (only TBM hdr): 0
[12:55:34.622] <TB0> INFO: TBM errors: 0
[12:55:34.622] <TB0> INFO: flawed TBM headers: 0
[12:55:34.622] <TB0> INFO: flawed TBM trailers: 0
[12:55:34.622] <TB0> INFO: event ID mismatches: 0
[12:55:34.622] <TB0> INFO: ROC errors: 0
[12:55:34.622] <TB0> INFO: missing ROC header(s): 0
[12:55:34.622] <TB0> INFO: misplaced readback start: 0
[12:55:34.622] <TB0> INFO: Pixel decoding errors: 0
[12:55:34.622] <TB0> INFO: pixel data incomplete: 0
[12:55:34.622] <TB0> INFO: pixel address: 0
[12:55:34.622] <TB0> INFO: pulse height fill bit: 0
[12:55:34.622] <TB0> INFO: buffer corruption: 0
[12:55:34.784] <TB0> INFO: ######################################################################
[12:55:34.785] <TB0> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[12:55:34.785] <TB0> INFO: ######################################################################
[12:55:34.800] <TB0> INFO: scanning low vcal = 10
[12:55:35.055] <TB0> INFO: Expecting 41600 events.
[12:55:38.631] <TB0> INFO: 41600 events read in total (2984ms).
[12:55:38.631] <TB0> INFO: Test took 3831ms.
[12:55:38.633] <TB0> INFO: scanning low vcal = 20
[12:55:38.929] <TB0> INFO: Expecting 41600 events.
[12:55:42.498] <TB0> INFO: 41600 events read in total (2978ms).
[12:55:42.498] <TB0> INFO: Test took 3865ms.
[12:55:42.500] <TB0> INFO: scanning low vcal = 30
[12:55:42.798] <TB0> INFO: Expecting 41600 events.
[12:55:46.465] <TB0> INFO: 41600 events read in total (3075ms).
[12:55:46.466] <TB0> INFO: Test took 3966ms.
[12:55:46.469] <TB0> INFO: scanning low vcal = 40
[12:55:46.758] <TB0> INFO: Expecting 41600 events.
[12:55:50.688] <TB0> INFO: 41600 events read in total (3338ms).
[12:55:50.690] <TB0> INFO: Test took 4221ms.
[12:55:50.694] <TB0> INFO: scanning low vcal = 50
[12:55:50.974] <TB0> INFO: Expecting 41600 events.
[12:55:54.951] <TB0> INFO: 41600 events read in total (3386ms).
[12:55:54.952] <TB0> INFO: Test took 4258ms.
[12:55:54.956] <TB0> INFO: scanning low vcal = 60
[12:55:55.233] <TB0> INFO: Expecting 41600 events.
[12:55:59.208] <TB0> INFO: 41600 events read in total (3384ms).
[12:55:59.209] <TB0> INFO: Test took 4253ms.
[12:55:59.212] <TB0> INFO: scanning low vcal = 70
[12:55:59.489] <TB0> INFO: Expecting 41600 events.
[12:56:03.471] <TB0> INFO: 41600 events read in total (3391ms).
[12:56:03.472] <TB0> INFO: Test took 4260ms.
[12:56:03.475] <TB0> INFO: scanning low vcal = 80
[12:56:03.752] <TB0> INFO: Expecting 41600 events.
[12:56:07.721] <TB0> INFO: 41600 events read in total (3377ms).
[12:56:07.722] <TB0> INFO: Test took 4247ms.
[12:56:07.725] <TB0> INFO: scanning low vcal = 90
[12:56:07.002] <TB0> INFO: Expecting 41600 events.
[12:56:12.010] <TB0> INFO: 41600 events read in total (3417ms).
[12:56:12.011] <TB0> INFO: Test took 4285ms.
[12:56:12.015] <TB0> INFO: scanning low vcal = 100
[12:56:12.291] <TB0> INFO: Expecting 41600 events.
[12:56:16.257] <TB0> INFO: 41600 events read in total (3374ms).
[12:56:16.258] <TB0> INFO: Test took 4243ms.
[12:56:16.262] <TB0> INFO: scanning low vcal = 110
[12:56:16.538] <TB0> INFO: Expecting 41600 events.
[12:56:20.481] <TB0> INFO: 41600 events read in total (3351ms).
[12:56:20.482] <TB0> INFO: Test took 4220ms.
[12:56:20.485] <TB0> INFO: scanning low vcal = 120
[12:56:20.762] <TB0> INFO: Expecting 41600 events.
[12:56:24.833] <TB0> INFO: 41600 events read in total (3479ms).
[12:56:24.834] <TB0> INFO: Test took 4349ms.
[12:56:24.837] <TB0> INFO: scanning low vcal = 130
[12:56:25.139] <TB0> INFO: Expecting 41600 events.
[12:56:29.268] <TB0> INFO: 41600 events read in total (3537ms).
[12:56:29.270] <TB0> INFO: Test took 4433ms.
[12:56:29.273] <TB0> INFO: scanning low vcal = 140
[12:56:29.552] <TB0> INFO: Expecting 41600 events.
[12:56:33.628] <TB0> INFO: 41600 events read in total (3484ms).
[12:56:33.628] <TB0> INFO: Test took 4355ms.
[12:56:33.635] <TB0> INFO: scanning low vcal = 150
[12:56:33.968] <TB0> INFO: Expecting 41600 events.
[12:56:37.915] <TB0> INFO: 41600 events read in total (3355ms).
[12:56:37.915] <TB0> INFO: Test took 4280ms.
[12:56:37.919] <TB0> INFO: scanning low vcal = 160
[12:56:38.195] <TB0> INFO: Expecting 41600 events.
[12:56:42.170] <TB0> INFO: 41600 events read in total (3383ms).
[12:56:42.171] <TB0> INFO: Test took 4252ms.
[12:56:42.174] <TB0> INFO: scanning low vcal = 170
[12:56:42.451] <TB0> INFO: Expecting 41600 events.
[12:56:46.460] <TB0> INFO: 41600 events read in total (3417ms).
[12:56:46.461] <TB0> INFO: Test took 4287ms.
[12:56:46.466] <TB0> INFO: scanning low vcal = 180
[12:56:46.840] <TB0> INFO: Expecting 41600 events.
[12:56:50.866] <TB0> INFO: 41600 events read in total (3434ms).
[12:56:50.867] <TB0> INFO: Test took 4400ms.
[12:56:50.871] <TB0> INFO: scanning low vcal = 190
[12:56:51.241] <TB0> INFO: Expecting 41600 events.
[12:56:55.204] <TB0> INFO: 41600 events read in total (3371ms).
[12:56:55.205] <TB0> INFO: Test took 4334ms.
[12:56:55.208] <TB0> INFO: scanning low vcal = 200
[12:56:55.485] <TB0> INFO: Expecting 41600 events.
[12:56:59.435] <TB0> INFO: 41600 events read in total (3359ms).
[12:56:59.436] <TB0> INFO: Test took 4228ms.
[12:56:59.440] <TB0> INFO: scanning low vcal = 210
[12:56:59.717] <TB0> INFO: Expecting 41600 events.
[12:57:03.675] <TB0> INFO: 41600 events read in total (3367ms).
[12:57:03.676] <TB0> INFO: Test took 4236ms.
[12:57:03.681] <TB0> INFO: scanning low vcal = 220
[12:57:03.956] <TB0> INFO: Expecting 41600 events.
[12:57:07.921] <TB0> INFO: 41600 events read in total (3372ms).
[12:57:07.922] <TB0> INFO: Test took 4241ms.
[12:57:07.925] <TB0> INFO: scanning low vcal = 230
[12:57:08.202] <TB0> INFO: Expecting 41600 events.
[12:57:12.198] <TB0> INFO: 41600 events read in total (3404ms).
[12:57:12.199] <TB0> INFO: Test took 4274ms.
[12:57:12.202] <TB0> INFO: scanning low vcal = 240
[12:57:12.479] <TB0> INFO: Expecting 41600 events.
[12:57:16.435] <TB0> INFO: 41600 events read in total (3365ms).
[12:57:16.436] <TB0> INFO: Test took 4233ms.
[12:57:16.440] <TB0> INFO: scanning low vcal = 250
[12:57:16.716] <TB0> INFO: Expecting 41600 events.
[12:57:20.699] <TB0> INFO: 41600 events read in total (3391ms).
[12:57:20.700] <TB0> INFO: Test took 4260ms.
[12:57:20.704] <TB0> INFO: scanning high vcal = 30 (= 210 in low range)
[12:57:20.982] <TB0> INFO: Expecting 41600 events.
[12:57:24.937] <TB0> INFO: 41600 events read in total (3363ms).
[12:57:24.938] <TB0> INFO: Test took 4234ms.
[12:57:24.941] <TB0> INFO: scanning high vcal = 50 (= 350 in low range)
[12:57:25.218] <TB0> INFO: Expecting 41600 events.
[12:57:29.166] <TB0> INFO: 41600 events read in total (3357ms).
[12:57:29.167] <TB0> INFO: Test took 4226ms.
[12:57:29.170] <TB0> INFO: scanning high vcal = 70 (= 490 in low range)
[12:57:29.446] <TB0> INFO: Expecting 41600 events.
[12:57:33.449] <TB0> INFO: 41600 events read in total (3411ms).
[12:57:33.450] <TB0> INFO: Test took 4280ms.
[12:57:33.453] <TB0> INFO: scanning high vcal = 90 (= 630 in low range)
[12:57:33.729] <TB0> INFO: Expecting 41600 events.
[12:57:37.663] <TB0> INFO: 41600 events read in total (3342ms).
[12:57:37.664] <TB0> INFO: Test took 4211ms.
[12:57:37.668] <TB0> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:57:37.944] <TB0> INFO: Expecting 41600 events.
[12:57:41.885] <TB0> INFO: 41600 events read in total (3349ms).
[12:57:41.886] <TB0> INFO: Test took 4218ms.
[12:57:42.297] <TB0> INFO: PixTestGainPedestal::measure() done
[12:58:30.734] <TB0> INFO: PixTestGainPedestal::fit() done
[12:58:30.734] <TB0> INFO: non-linearity mean: 0.959 0.963 0.955 0.943 0.928 0.937 0.950 0.936 0.960 0.980 0.919 0.927 0.948 0.906 0.921 0.913
[12:58:30.734] <TB0> INFO: non-linearity RMS: 0.053 0.190 0.051 0.078 0.099 0.081 0.067 0.119 0.033 0.003 0.103 0.175 0.057 0.098 0.108 0.090
[12:58:30.734] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[12:58:30.756] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[12:58:30.778] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[12:58:30.799] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[12:58:30.821] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[12:58:30.842] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[12:58:30.864] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[12:58:30.885] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[12:58:30.907] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[12:58:30.928] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[12:58:30.950] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[12:58:30.971] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[12:58:30.993] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[12:58:31.015] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[12:58:31.036] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[12:58:31.058] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[12:58:31.079] <TB0> INFO: PixTestGainPedestal::fullTest() done, duration: 176 seconds
[12:58:31.079] <TB0> INFO: Decoding statistics:
[12:58:31.079] <TB0> INFO: General information:
[12:58:31.079] <TB0> INFO: 16bit words read: 3289114
[12:58:31.079] <TB0> INFO: valid events total: 332800
[12:58:31.079] <TB0> INFO: empty events: 2143
[12:58:31.079] <TB0> INFO: valid events with pixels: 330657
[12:58:31.079] <TB0> INFO: valid pixel hits: 646157
[12:58:31.079] <TB0> INFO: Event errors: 0
[12:58:31.079] <TB0> INFO: start marker: 0
[12:58:31.079] <TB0> INFO: stop marker: 0
[12:58:31.080] <TB0> INFO: overflow: 0
[12:58:31.080] <TB0> INFO: invalid 5bit words: 0
[12:58:31.080] <TB0> INFO: invalid XOR eye diagram: 0
[12:58:31.080] <TB0> INFO: frame (failed synchr.): 0
[12:58:31.080] <TB0> INFO: idle data (no TBM trl): 0
[12:58:31.080] <TB0> INFO: no data (only TBM hdr): 0
[12:58:31.080] <TB0> INFO: TBM errors: 0
[12:58:31.080] <TB0> INFO: flawed TBM headers: 0
[12:58:31.080] <TB0> INFO: flawed TBM trailers: 0
[12:58:31.080] <TB0> INFO: event ID mismatches: 0
[12:58:31.080] <TB0> INFO: ROC errors: 0
[12:58:31.080] <TB0> INFO: missing ROC header(s): 0
[12:58:31.080] <TB0> INFO: misplaced readback start: 0
[12:58:31.080] <TB0> INFO: Pixel decoding errors: 0
[12:58:31.080] <TB0> INFO: pixel data incomplete: 0
[12:58:31.080] <TB0> INFO: pixel address: 0
[12:58:31.080] <TB0> INFO: pulse height fill bit: 0
[12:58:31.080] <TB0> INFO: buffer corruption: 0
[12:58:31.102] <TB0> INFO: Decoding statistics:
[12:58:31.102] <TB0> INFO: General information:
[12:58:31.102] <TB0> INFO: 16bit words read: 3418530
[12:58:31.102] <TB0> INFO: valid events total: 353536
[12:58:31.102] <TB0> INFO: empty events: 20379
[12:58:31.102] <TB0> INFO: valid events with pixels: 333157
[12:58:31.102] <TB0> INFO: valid pixel hits: 648657
[12:58:31.102] <TB0> INFO: Event errors: 0
[12:58:31.102] <TB0> INFO: start marker: 0
[12:58:31.102] <TB0> INFO: stop marker: 0
[12:58:31.102] <TB0> INFO: overflow: 0
[12:58:31.102] <TB0> INFO: invalid 5bit words: 0
[12:58:31.102] <TB0> INFO: invalid XOR eye diagram: 0
[12:58:31.102] <TB0> INFO: frame (failed synchr.): 0
[12:58:31.102] <TB0> INFO: idle data (no TBM trl): 0
[12:58:31.102] <TB0> INFO: no data (only TBM hdr): 0
[12:58:31.102] <TB0> INFO: TBM errors: 0
[12:58:31.102] <TB0> INFO: flawed TBM headers: 0
[12:58:31.102] <TB0> INFO: flawed TBM trailers: 0
[12:58:31.102] <TB0> INFO: event ID mismatches: 0
[12:58:31.102] <TB0> INFO: ROC errors: 0
[12:58:31.102] <TB0> INFO: missing ROC header(s): 0
[12:58:31.102] <TB0> INFO: misplaced readback start: 0
[12:58:31.102] <TB0> INFO: Pixel decoding errors: 0
[12:58:31.102] <TB0> INFO: pixel data incomplete: 0
[12:58:31.102] <TB0> INFO: pixel address: 0
[12:58:31.103] <TB0> INFO: pulse height fill bit: 0
[12:58:31.103] <TB0> INFO: buffer corruption: 0
[12:58:31.103] <TB0> INFO: enter test to run
[12:58:31.103] <TB0> INFO: test: trim80 no parameter change
[12:58:31.103] <TB0> INFO: running: trim80
[12:58:31.107] <TB0> INFO: ######################################################################
[12:58:31.107] <TB0> INFO: PixTestTrim80::doTest()
[12:58:31.107] <TB0> INFO: ######################################################################
[12:58:31.109] <TB0> INFO: ----------------------------------------------------------------------
[12:58:31.109] <TB0> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[12:58:31.109] <TB0> INFO: ----------------------------------------------------------------------
[12:58:31.154] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:58:31.155] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:58:31.169] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:58:31.169] <TB0> INFO: run 1 of 1
[12:58:31.413] <TB0> INFO: Expecting 5025280 events.
[12:58:59.048] <TB0> INFO: 669712 events read in total (27043ms).
[12:59:26.639] <TB0> INFO: 1336432 events read in total (54634ms).
[12:59:55.007] <TB0> INFO: 2001072 events read in total (83002ms).
[13:00:23.006] <TB0> INFO: 2665464 events read in total (111001ms).
[13:00:50.320] <TB0> INFO: 3331288 events read in total (138315ms).
[13:01:17.838] <TB0> INFO: 3994800 events read in total (165833ms).
[13:01:45.324] <TB0> INFO: 4659536 events read in total (193319ms).
[13:02:00.806] <TB0> INFO: 5025280 events read in total (208801ms).
[13:02:00.912] <TB0> INFO: Test took 209742ms.
[13:02:29.122] <TB0> INFO: ROC 0 VthrComp = 72
[13:02:29.122] <TB0> INFO: ROC 1 VthrComp = 72
[13:02:29.122] <TB0> INFO: ROC 2 VthrComp = 79
[13:02:29.122] <TB0> INFO: ROC 3 VthrComp = 75
[13:02:29.123] <TB0> INFO: ROC 4 VthrComp = 76
[13:02:29.123] <TB0> INFO: ROC 5 VthrComp = 73
[13:02:29.123] <TB0> INFO: ROC 6 VthrComp = 77
[13:02:29.123] <TB0> INFO: ROC 7 VthrComp = 77
[13:02:29.123] <TB0> INFO: ROC 8 VthrComp = 77
[13:02:29.123] <TB0> INFO: ROC 9 VthrComp = 71
[13:02:29.123] <TB0> INFO: ROC 10 VthrComp = 72
[13:02:29.123] <TB0> INFO: ROC 11 VthrComp = 70
[13:02:29.124] <TB0> INFO: ROC 12 VthrComp = 67
[13:02:29.124] <TB0> INFO: ROC 13 VthrComp = 58
[13:02:29.126] <TB0> INFO: ROC 14 VthrComp = 63
[13:02:29.126] <TB0> INFO: ROC 15 VthrComp = 71
[13:02:29.376] <TB0> INFO: Expecting 41600 events.
[13:02:32.997] <TB0> INFO: 41600 events read in total (3029ms).
[13:02:32.998] <TB0> INFO: Test took 3869ms.
[13:02:33.013] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:02:33.013] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:02:33.030] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:02:33.030] <TB0> INFO: run 1 of 1
[13:02:33.363] <TB0> INFO: Expecting 5025280 events.
[13:03:02.111] <TB0> INFO: 687192 events read in total (28154ms).
[13:03:30.374] <TB0> INFO: 1370784 events read in total (56417ms).
[13:03:59.558] <TB0> INFO: 2052216 events read in total (85601ms).
[13:04:27.669] <TB0> INFO: 2730328 events read in total (113712ms).
[13:04:55.746] <TB0> INFO: 3404448 events read in total (141789ms).
[13:05:23.688] <TB0> INFO: 4077192 events read in total (169731ms).
[13:05:51.900] <TB0> INFO: 4748472 events read in total (197943ms).
[13:06:03.959] <TB0> INFO: 5025280 events read in total (210002ms).
[13:06:04.049] <TB0> INFO: Test took 211019ms.
[13:06:32.792] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 111.461 for pixel 4/79 mean/min/max = 94.0312/76.5916/111.471
[13:06:32.794] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 105.892 for pixel 14/16 mean/min/max = 91.1633/76.2822/106.045
[13:06:32.794] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 112.103 for pixel 0/6 mean/min/max = 94.8387/77.528/112.149
[13:06:32.795] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 110.104 for pixel 12/66 mean/min/max = 94.298/78.4681/110.128
[13:06:32.795] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 109 for pixel 12/76 mean/min/max = 93.6091/78.1165/109.102
[13:06:32.796] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 110.548 for pixel 0/6 mean/min/max = 93.3234/76.0968/110.55
[13:06:32.797] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 110.644 for pixel 0/23 mean/min/max = 94.8168/78.7666/110.867
[13:06:32.797] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 112.392 for pixel 0/1 mean/min/max = 95.1829/77.6136/112.752
[13:06:32.798] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 109.087 for pixel 0/4 mean/min/max = 93.2678/77.4387/109.097
[13:06:32.798] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 104.063 for pixel 20/79 mean/min/max = 88.692/73.2805/104.103
[13:06:32.799] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 109.635 for pixel 0/9 mean/min/max = 93.2201/76.7821/109.658
[13:06:32.800] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 103.544 for pixel 17/75 mean/min/max = 88.871/74.1617/103.58
[13:06:32.800] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 104.248 for pixel 0/18 mean/min/max = 89.673/75.0194/104.326
[13:06:32.801] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 118.246 for pixel 0/42 mean/min/max = 95.7567/73.2666/118.247
[13:06:32.801] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 117.888 for pixel 0/15 mean/min/max = 95.1514/72.4027/117.9
[13:06:32.802] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 103.737 for pixel 0/65 mean/min/max = 89.2228/74.4207/104.025
[13:06:32.803] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:06:32.894] <TB0> INFO: Expecting 411648 events.
[13:06:42.611] <TB0> INFO: 411648 events read in total (9126ms).
[13:06:42.626] <TB0> INFO: Expecting 411648 events.
[13:06:51.880] <TB0> INFO: 411648 events read in total (8849ms).
[13:06:51.891] <TB0> INFO: Expecting 411648 events.
[13:07:01.091] <TB0> INFO: 411648 events read in total (8797ms).
[13:07:01.105] <TB0> INFO: Expecting 411648 events.
[13:07:10.286] <TB0> INFO: 411648 events read in total (8778ms).
[13:07:10.304] <TB0> INFO: Expecting 411648 events.
[13:07:19.521] <TB0> INFO: 411648 events read in total (8816ms).
[13:07:19.545] <TB0> INFO: Expecting 411648 events.
[13:07:28.714] <TB0> INFO: 411648 events read in total (8766ms).
[13:07:28.744] <TB0> INFO: Expecting 411648 events.
[13:07:37.938] <TB0> INFO: 411648 events read in total (8791ms).
[13:07:37.972] <TB0> INFO: Expecting 411648 events.
[13:07:47.449] <TB0> INFO: 411648 events read in total (9073ms).
[13:07:47.479] <TB0> INFO: Expecting 411648 events.
[13:07:56.919] <TB0> INFO: 411648 events read in total (9037ms).
[13:07:56.977] <TB0> INFO: Expecting 411648 events.
[13:08:06.264] <TB0> INFO: 411648 events read in total (8883ms).
[13:08:06.304] <TB0> INFO: Expecting 411648 events.
[13:08:15.508] <TB0> INFO: 411648 events read in total (8801ms).
[13:08:15.562] <TB0> INFO: Expecting 411648 events.
[13:08:24.703] <TB0> INFO: 411648 events read in total (8738ms).
[13:08:24.755] <TB0> INFO: Expecting 411648 events.
[13:08:33.872] <TB0> INFO: 411648 events read in total (8714ms).
[13:08:33.932] <TB0> INFO: Expecting 411648 events.
[13:08:43.074] <TB0> INFO: 411648 events read in total (8727ms).
[13:08:43.159] <TB0> INFO: Expecting 411648 events.
[13:08:52.374] <TB0> INFO: 411648 events read in total (8812ms).
[13:08:52.436] <TB0> INFO: Expecting 411648 events.
[13:09:01.744] <TB0> INFO: 411648 events read in total (8905ms).
[13:09:01.849] <TB0> INFO: Test took 149047ms.
[13:09:03.856] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:09:03.876] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:09:03.876] <TB0> INFO: run 1 of 1
[13:09:04.250] <TB0> INFO: Expecting 5025280 events.
[13:09:32.222] <TB0> INFO: 671568 events read in total (27380ms).
[13:09:59.527] <TB0> INFO: 1340432 events read in total (54685ms).
[13:10:26.985] <TB0> INFO: 2007064 events read in total (82143ms).
[13:10:54.674] <TB0> INFO: 2669912 events read in total (109832ms).
[13:11:21.964] <TB0> INFO: 3328200 events read in total (137122ms).
[13:11:49.815] <TB0> INFO: 3983544 events read in total (164973ms).
[13:12:17.545] <TB0> INFO: 4637120 events read in total (192703ms).
[13:12:33.690] <TB0> INFO: 5025280 events read in total (208848ms).
[13:12:33.769] <TB0> INFO: Test took 209893ms.
[13:13:04.646] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 51.184046 .. 103.235495
[13:13:04.982] <TB0> INFO: Expecting 208000 events.
[13:13:15.646] <TB0> INFO: 208000 events read in total (10072ms).
[13:13:15.648] <TB0> INFO: Test took 11001ms.
[13:13:15.709] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 41 .. 113 (-1/-1) hits flags = 528 (plus default)
[13:13:15.723] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:13:15.723] <TB0> INFO: run 1 of 1
[13:13:15.001] <TB0> INFO: Expecting 2429440 events.
[13:13:44.930] <TB0> INFO: 684856 events read in total (28337ms).
[13:14:13.833] <TB0> INFO: 1368800 events read in total (57240ms).
[13:14:42.209] <TB0> INFO: 2044544 events read in total (85616ms).
[13:14:58.678] <TB0> INFO: 2429440 events read in total (102085ms).
[13:14:58.727] <TB0> INFO: Test took 103004ms.
[13:15:22.440] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 62.297294 .. 92.678442
[13:15:22.766] <TB0> INFO: Expecting 208000 events.
[13:15:32.726] <TB0> INFO: 208000 events read in total (9368ms).
[13:15:32.728] <TB0> INFO: Test took 10286ms.
[13:15:32.794] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 52 .. 102 (-1/-1) hits flags = 528 (plus default)
[13:15:32.809] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:15:32.809] <TB0> INFO: run 1 of 1
[13:15:33.087] <TB0> INFO: Expecting 1697280 events.
[13:16:03.377] <TB0> INFO: 689776 events read in total (29698ms).
[13:16:33.204] <TB0> INFO: 1378744 events read in total (59525ms).
[13:16:47.401] <TB0> INFO: 1697280 events read in total (73722ms).
[13:16:47.440] <TB0> INFO: Test took 74632ms.
[13:17:07.208] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 66.692979 .. 88.085491
[13:17:07.448] <TB0> INFO: Expecting 208000 events.
[13:17:17.657] <TB0> INFO: 208000 events read in total (9617ms).
[13:17:17.657] <TB0> INFO: Test took 10446ms.
[13:17:17.716] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 56 .. 98 (-1/-1) hits flags = 528 (plus default)
[13:17:17.730] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:17:17.730] <TB0> INFO: run 1 of 1
[13:17:18.008] <TB0> INFO: Expecting 1431040 events.
[13:17:47.928] <TB0> INFO: 692688 events read in total (29328ms).
[13:18:18.145] <TB0> INFO: 1385592 events read in total (59545ms).
[13:18:20.727] <TB0> INFO: 1431040 events read in total (62127ms).
[13:18:20.757] <TB0> INFO: Test took 63028ms.
[13:18:41.591] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 68.605504 .. 87.143880
[13:18:41.920] <TB0> INFO: Expecting 208000 events.
[13:18:52.419] <TB0> INFO: 208000 events read in total (9908ms).
[13:18:52.420] <TB0> INFO: Test took 10826ms.
[13:18:52.474] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 58 .. 97 (-1/-1) hits flags = 528 (plus default)
[13:18:52.488] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:18:52.488] <TB0> INFO: run 1 of 1
[13:18:52.765] <TB0> INFO: Expecting 1331200 events.
[13:19:22.612] <TB0> INFO: 692632 events read in total (29255ms).
[13:19:50.687] <TB0> INFO: 1331200 events read in total (57330ms).
[13:19:50.721] <TB0> INFO: Test took 58234ms.
[13:20:10.424] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[13:20:10.424] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[13:20:10.438] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:20:10.438] <TB0> INFO: run 1 of 1
[13:20:10.679] <TB0> INFO: Expecting 1364480 events.
[13:20:39.852] <TB0> INFO: 668744 events read in total (28582ms).
[13:21:09.393] <TB0> INFO: 1336536 events read in total (58123ms).
[13:21:11.029] <TB0> INFO: 1364480 events read in total (59759ms).
[13:21:11.057] <TB0> INFO: Test took 60619ms.
[13:21:33.182] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C0.dat
[13:21:33.182] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C1.dat
[13:21:33.182] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C2.dat
[13:21:33.182] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C3.dat
[13:21:33.182] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C4.dat
[13:21:33.182] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C5.dat
[13:21:33.183] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C6.dat
[13:21:33.183] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C7.dat
[13:21:33.183] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C8.dat
[13:21:33.183] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C9.dat
[13:21:33.183] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C10.dat
[13:21:33.183] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C11.dat
[13:21:33.183] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C12.dat
[13:21:33.183] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C13.dat
[13:21:33.183] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C14.dat
[13:21:33.183] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//dacParameters80_C15.dat
[13:21:33.184] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C0.dat
[13:21:33.192] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C1.dat
[13:21:33.201] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C2.dat
[13:21:33.209] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C3.dat
[13:21:33.218] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C4.dat
[13:21:33.227] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C5.dat
[13:21:33.235] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C6.dat
[13:21:33.243] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C7.dat
[13:21:33.252] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C8.dat
[13:21:33.260] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C9.dat
[13:21:33.269] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C10.dat
[13:21:33.277] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C11.dat
[13:21:33.285] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C12.dat
[13:21:33.290] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C13.dat
[13:21:33.296] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C14.dat
[13:21:33.302] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1117_FullQualification_2016-11-03_09h01m_1478160071//003_FulltestTrim80_p17//trimParameters80_C15.dat
[13:21:33.307] <TB0> INFO: PixTestTrim80::trimTest() done
[13:21:33.307] <TB0> INFO: vtrim: 98 89 117 104 110 106 103 110 95 86 105 83 82 115 124 89
[13:21:33.307] <TB0> INFO: vthrcomp: 72 72 79 75 76 73 77 77 77 71 72 70 67 58 63 71
[13:21:33.307] <TB0> INFO: vcal mean: 79.96 79.98 79.94 79.94 79.94 79.94 79.95 79.94 79.94 79.91 79.94 79.88 79.94 79.92 79.94 79.91
[13:21:33.307] <TB0> INFO: vcal RMS: 0.77 0.69 0.77 0.73 0.74 0.74 0.72 0.77 0.72 0.75 0.72 0.75 0.68 0.81 0.79 0.71
[13:21:33.307] <TB0> INFO: bits mean: 9.58 9.49 9.19 9.15 9.37 9.73 8.74 9.33 9.30 10.81 9.37 10.65 10.38 9.91 10.00 10.42
[13:21:33.307] <TB0> INFO: bits RMS: 2.31 2.47 2.38 2.26 2.22 2.37 2.37 2.29 2.38 2.40 2.45 2.34 2.34 2.52 2.56 2.46
[13:21:33.314] <TB0> INFO: ----------------------------------------------------------------------
[13:21:33.314] <TB0> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:21:33.314] <TB0> INFO: ----------------------------------------------------------------------
[13:21:33.319] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:21:33.333] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:21:33.333] <TB0> INFO: run 1 of 1
[13:21:33.576] <TB0> INFO: Expecting 4160000 events.
[13:22:06.154] <TB0> INFO: 744440 events read in total (31986ms).
[13:22:38.297] <TB0> INFO: 1479895 events read in total (64129ms).
[13:23:09.081] <TB0> INFO: 2208515 events read in total (94913ms).
[13:23:39.484] <TB0> INFO: 2930170 events read in total (125316ms).
[13:24:10.463] <TB0> INFO: 3648080 events read in total (156295ms).
[13:24:33.222] <TB0> INFO: 4160000 events read in total (179054ms).
[13:24:33.308] <TB0> INFO: Test took 179974ms.
[13:25:05.285] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 201 (-1/-1) hits flags = 528 (plus default)
[13:25:05.299] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:25:05.299] <TB0> INFO: run 1 of 1
[13:25:05.544] <TB0> INFO: Expecting 4201600 events.
[13:25:37.451] <TB0> INFO: 718590 events read in total (31315ms).
[13:26:08.719] <TB0> INFO: 1429400 events read in total (62583ms).
[13:26:39.789] <TB0> INFO: 2134665 events read in total (93653ms).
[13:27:10.546] <TB0> INFO: 2833745 events read in total (124410ms).
[13:27:41.754] <TB0> INFO: 3529050 events read in total (155618ms).
[13:28:11.826] <TB0> INFO: 4201600 events read in total (185690ms).
[13:28:11.948] <TB0> INFO: Test took 186648ms.
[13:28:43.359] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[13:28:43.374] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:28:43.374] <TB0> INFO: run 1 of 1
[13:28:43.667] <TB0> INFO: Expecting 4097600 events.
[13:29:15.387] <TB0> INFO: 724640 events read in total (31127ms).
[13:29:47.232] <TB0> INFO: 1440815 events read in total (62972ms).
[13:30:18.753] <TB0> INFO: 2151195 events read in total (94493ms).
[13:30:49.891] <TB0> INFO: 2855175 events read in total (125631ms).
[13:31:20.841] <TB0> INFO: 3555590 events read in total (156581ms).
[13:31:44.872] <TB0> INFO: 4097600 events read in total (180612ms).
[13:31:44.984] <TB0> INFO: Test took 181610ms.
[13:32:14.007] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:32:15.022] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:32:15.023] <TB0> INFO: run 1 of 1
[13:32:15.397] <TB0> INFO: Expecting 4160000 events.
[13:32:47.514] <TB0> INFO: 720830 events read in total (31526ms).
[13:33:18.877] <TB0> INFO: 1433715 events read in total (62889ms).
[13:33:50.032] <TB0> INFO: 2140770 events read in total (94044ms).
[13:34:21.063] <TB0> INFO: 2841520 events read in total (125075ms).
[13:34:51.860] <TB0> INFO: 3538075 events read in total (155872ms).
[13:35:19.395] <TB0> INFO: 4160000 events read in total (183407ms).
[13:35:19.514] <TB0> INFO: Test took 184491ms.
[13:35:51.158] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[13:35:51.173] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:35:51.173] <TB0> INFO: run 1 of 1
[13:35:51.421] <TB0> INFO: Expecting 4139200 events.
[13:36:23.161] <TB0> INFO: 721990 events read in total (31149ms).
[13:36:54.277] <TB0> INFO: 1435735 events read in total (62265ms).
[13:37:26.318] <TB0> INFO: 2143855 events read in total (94306ms).
[13:37:57.494] <TB0> INFO: 2845160 events read in total (125482ms).
[13:38:28.426] <TB0> INFO: 3542760 events read in total (156414ms).
[13:38:55.218] <TB0> INFO: 4139200 events read in total (183206ms).
[13:38:55.323] <TB0> INFO: Test took 184151ms.
[13:39:23.616] <TB0> INFO: PixTestTrim80::trimBitTest() done
[13:39:23.618] <TB0> INFO: PixTestTrim80::doTest() done, duration: 2452 seconds
[13:39:24.433] <TB0> INFO: enter test to run
[13:39:24.434] <TB0> INFO: test: exit no parameter change
[13:39:24.825] <TB0> QUIET: Connection to board 71 closed.
[13:39:24.827] <TB0> INFO: pXar: this is the end, my friend