[18:07:49.854] <TB1> INFO: *** Welcome to pxar ***
[18:07:49.854] <TB1> INFO: *** Today: 2016/11/02
[18:07:49.860] <TB1> INFO: *** Version: c8ba-dirty
[18:07:49.860] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C15.dat
[18:07:49.861] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[18:07:49.861] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//defaultMaskFile.dat
[18:07:49.861] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters_C15.dat
[18:07:49.919] <TB1> INFO: clk: 4
[18:07:49.919] <TB1> INFO: ctr: 4
[18:07:49.919] <TB1> INFO: sda: 19
[18:07:49.919] <TB1> INFO: tin: 9
[18:07:49.919] <TB1> INFO: level: 15
[18:07:49.919] <TB1> INFO: triggerdelay: 0
[18:07:49.919] <TB1> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[18:07:49.919] <TB1> INFO: Log level: INFO
[18:07:49.928] <TB1> INFO: Found DTB DTB_WXBYFL
[18:07:49.937] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[18:07:49.939] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
------------------------------------------------------
[18:07:49.941] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[18:07:51.491] <TB1> INFO: DUT info:
[18:07:51.491] <TB1> INFO: The DUT currently contains the following objects:
[18:07:51.491] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[18:07:51.491] <TB1> INFO: TBM Core alpha (0): 7 registers set
[18:07:51.491] <TB1> INFO: TBM Core beta (1): 7 registers set
[18:07:51.491] <TB1> INFO: TBM Core alpha (2): 7 registers set
[18:07:51.491] <TB1> INFO: TBM Core beta (3): 7 registers set
[18:07:51.491] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[18:07:51.491] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.491] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[18:07:51.892] <TB1> INFO: enter 'restricted' command line mode
[18:07:51.892] <TB1> INFO: enter test to run
[18:07:51.892] <TB1> INFO: test: pretest no parameter change
[18:07:51.892] <TB1> INFO: running: pretest
[18:07:52.429] <TB1> INFO: ######################################################################
[18:07:52.429] <TB1> INFO: PixTestPretest::doTest()
[18:07:52.429] <TB1> INFO: ######################################################################
[18:07:52.430] <TB1> INFO: ----------------------------------------------------------------------
[18:07:52.430] <TB1> INFO: PixTestPretest::programROC()
[18:07:52.430] <TB1> INFO: ----------------------------------------------------------------------
[18:08:10.443] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[18:08:10.443] <TB1> INFO: IA differences per ROC: 18.5 20.1 18.5 17.7 18.5 18.5 18.5 16.9 17.7 18.5 19.3 18.5 18.5 16.9 18.5 19.3
[18:08:10.478] <TB1> INFO: ----------------------------------------------------------------------
[18:08:10.478] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[18:08:10.478] <TB1> INFO: ----------------------------------------------------------------------
[18:08:31.718] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 387.5 mA = 24.2188 mA/ROC
[18:08:31.719] <TB1> INFO: i(loss) [mA/ROC]: 19.3 20.9 20.1 20.1 19.3 20.1 20.1 19.3 20.1 19.3 20.1 19.3 19.3 19.3 19.3 19.3
[18:08:31.747] <TB1> INFO: ----------------------------------------------------------------------
[18:08:31.747] <TB1> INFO: PixTestPretest::findTiming()
[18:08:31.747] <TB1> INFO: ----------------------------------------------------------------------
[18:08:31.747] <TB1> INFO: PixTestCmd::init()

[18:09:03.090] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[18:09:03.090] <TB1> INFO: (success/tries = 100/100), width = 4
[18:09:04.605] <TB1> INFO: ----------------------------------------------------------------------
[18:09:04.605] <TB1> INFO: PixTestPretest::findWorkingPixel()
[18:09:04.605] <TB1> INFO: ----------------------------------------------------------------------
[18:09:04.697] <TB1> INFO: Expecting 231680 events.
[18:09:14.308] <TB1> INFO: 231680 events read in total (9019ms).
[18:09:14.316] <TB1> INFO: Test took 9708ms.
[18:09:14.564] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[18:09:14.592] <TB1> INFO: ----------------------------------------------------------------------
[18:09:14.592] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[18:09:14.592] <TB1> INFO: ----------------------------------------------------------------------
[18:09:14.684] <TB1> INFO: Expecting 231680 events.
[18:09:24.260] <TB1> INFO: 231680 events read in total (8984ms).
[18:09:24.267] <TB1> INFO: Test took 9671ms.
[18:09:24.525] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[18:09:24.525] <TB1> INFO: CalDel: 87 87 87 82 89 92 87 80 77 90 94 89 80 81 87 91
[18:09:24.525] <TB1> INFO: VthrComp: 51 51 51 51 51 51 51 52 51 51 51 51 54 51 51 51
[18:09:24.527] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C0.dat
[18:09:24.527] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C1.dat
[18:09:24.528] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C2.dat
[18:09:24.528] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C3.dat
[18:09:24.528] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C4.dat
[18:09:24.528] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C5.dat
[18:09:24.528] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C6.dat
[18:09:24.528] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C7.dat
[18:09:24.528] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C8.dat
[18:09:24.528] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C9.dat
[18:09:24.528] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C10.dat
[18:09:24.528] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C11.dat
[18:09:24.528] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C12.dat
[18:09:24.528] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C13.dat
[18:09:24.529] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C14.dat
[18:09:24.529] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters_C15.dat
[18:09:24.529] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[18:09:24.529] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[18:09:24.529] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[18:09:24.529] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[18:09:24.529] <TB1> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[18:09:24.638] <TB1> INFO: enter test to run
[18:09:24.638] <TB1> INFO: test: fulltest no parameter change
[18:09:24.639] <TB1> INFO: running: fulltest
[18:09:24.639] <TB1> INFO: ######################################################################
[18:09:24.639] <TB1> INFO: PixTestFullTest::doTest()
[18:09:24.639] <TB1> INFO: ######################################################################
[18:09:24.640] <TB1> INFO: ######################################################################
[18:09:24.640] <TB1> INFO: PixTestAlive::doTest()
[18:09:24.640] <TB1> INFO: ######################################################################
[18:09:24.641] <TB1> INFO: ----------------------------------------------------------------------
[18:09:24.641] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[18:09:24.641] <TB1> INFO: ----------------------------------------------------------------------
[18:09:24.879] <TB1> INFO: Expecting 41600 events.
[18:09:28.394] <TB1> INFO: 41600 events read in total (2923ms).
[18:09:28.394] <TB1> INFO: Test took 3751ms.
[18:09:28.620] <TB1> INFO: PixTestAlive::aliveTest() done
[18:09:28.620] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0
[18:09:28.621] <TB1> INFO: ----------------------------------------------------------------------
[18:09:28.621] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[18:09:28.621] <TB1> INFO: ----------------------------------------------------------------------
[18:09:28.896] <TB1> INFO: Expecting 41600 events.
[18:09:31.803] <TB1> INFO: 41600 events read in total (2315ms).
[18:09:31.804] <TB1> INFO: Test took 3181ms.
[18:09:31.804] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[18:09:32.043] <TB1> INFO: PixTestAlive::maskTest() done
[18:09:32.043] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[18:09:32.044] <TB1> INFO: ----------------------------------------------------------------------
[18:09:32.044] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[18:09:32.044] <TB1> INFO: ----------------------------------------------------------------------
[18:09:32.293] <TB1> INFO: Expecting 41600 events.
[18:09:35.718] <TB1> INFO: 41600 events read in total (2833ms).
[18:09:35.719] <TB1> INFO: Test took 3673ms.
[18:09:35.945] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[18:09:35.945] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[18:09:35.945] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[18:09:35.945] <TB1> INFO: Decoding statistics:
[18:09:35.945] <TB1> INFO: General information:
[18:09:35.945] <TB1> INFO: 16bit words read: 0
[18:09:35.945] <TB1> INFO: valid events total: 0
[18:09:35.945] <TB1> INFO: empty events: 0
[18:09:35.945] <TB1> INFO: valid events with pixels: 0
[18:09:35.945] <TB1> INFO: valid pixel hits: 0
[18:09:35.945] <TB1> INFO: Event errors: 0
[18:09:35.945] <TB1> INFO: start marker: 0
[18:09:35.945] <TB1> INFO: stop marker: 0
[18:09:35.945] <TB1> INFO: overflow: 0
[18:09:35.945] <TB1> INFO: invalid 5bit words: 0
[18:09:35.945] <TB1> INFO: invalid XOR eye diagram: 0
[18:09:35.945] <TB1> INFO: frame (failed synchr.): 0
[18:09:35.945] <TB1> INFO: idle data (no TBM trl): 0
[18:09:35.945] <TB1> INFO: no data (only TBM hdr): 0
[18:09:35.945] <TB1> INFO: TBM errors: 0
[18:09:35.945] <TB1> INFO: flawed TBM headers: 0
[18:09:35.945] <TB1> INFO: flawed TBM trailers: 0
[18:09:35.945] <TB1> INFO: event ID mismatches: 0
[18:09:35.945] <TB1> INFO: ROC errors: 0
[18:09:35.945] <TB1> INFO: missing ROC header(s): 0
[18:09:35.945] <TB1> INFO: misplaced readback start: 0
[18:09:35.945] <TB1> INFO: Pixel decoding errors: 0
[18:09:35.945] <TB1> INFO: pixel data incomplete: 0
[18:09:35.946] <TB1> INFO: pixel address: 0
[18:09:35.946] <TB1> INFO: pulse height fill bit: 0
[18:09:35.946] <TB1> INFO: buffer corruption: 0
[18:09:35.953] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C15.dat
[18:09:35.953] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[18:09:35.953] <TB1> INFO: ######################################################################
[18:09:35.953] <TB1> INFO: PixTestReadback::doTest()
[18:09:35.953] <TB1> INFO: ######################################################################
[18:09:35.953] <TB1> INFO: ----------------------------------------------------------------------
[18:09:35.953] <TB1> INFO: PixTestReadback::CalibrateVd()
[18:09:35.953] <TB1> INFO: ----------------------------------------------------------------------
[18:09:45.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C0.dat
[18:09:45.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C1.dat
[18:09:45.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C2.dat
[18:09:45.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C3.dat
[18:09:45.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C4.dat
[18:09:45.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C5.dat
[18:09:45.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C6.dat
[18:09:45.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C7.dat
[18:09:45.920] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C8.dat
[18:09:45.921] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C9.dat
[18:09:45.921] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C10.dat
[18:09:45.921] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C11.dat
[18:09:45.921] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C12.dat
[18:09:45.921] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C13.dat
[18:09:45.921] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C14.dat
[18:09:45.921] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C15.dat
[18:09:45.951] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[18:09:45.951] <TB1> INFO: ----------------------------------------------------------------------
[18:09:45.951] <TB1> INFO: PixTestReadback::CalibrateVa()
[18:09:45.951] <TB1> INFO: ----------------------------------------------------------------------
[18:09:55.838] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C0.dat
[18:09:55.838] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C1.dat
[18:09:55.838] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C2.dat
[18:09:55.838] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C3.dat
[18:09:55.838] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C4.dat
[18:09:55.838] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C5.dat
[18:09:55.838] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C6.dat
[18:09:55.838] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C7.dat
[18:09:55.838] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C8.dat
[18:09:55.839] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C9.dat
[18:09:55.839] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C10.dat
[18:09:55.839] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C11.dat
[18:09:55.839] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C12.dat
[18:09:55.839] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C13.dat
[18:09:55.839] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C14.dat
[18:09:55.839] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C15.dat
[18:09:55.866] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[18:09:55.866] <TB1> INFO: ----------------------------------------------------------------------
[18:09:55.866] <TB1> INFO: PixTestReadback::readbackVbg()
[18:09:55.866] <TB1> INFO: ----------------------------------------------------------------------
[18:10:03.510] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[18:10:03.510] <TB1> INFO: ----------------------------------------------------------------------
[18:10:03.510] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[18:10:03.510] <TB1> INFO: ----------------------------------------------------------------------
[18:10:03.510] <TB1> INFO: Vbg will be calibrated using Vd calibration
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 150.5calibrated Vbg = 1.15905 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 162.1calibrated Vbg = 1.1646 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 155.8calibrated Vbg = 1.15447 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 149.6calibrated Vbg = 1.15599 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 151.2calibrated Vbg = 1.15403 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 151.7calibrated Vbg = 1.1581 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 149.9calibrated Vbg = 1.15605 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 158.9calibrated Vbg = 1.15918 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 147.2calibrated Vbg = 1.15328 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 162.1calibrated Vbg = 1.15801 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 165calibrated Vbg = 1.14862 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 157.2calibrated Vbg = 1.1474 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 154.7calibrated Vbg = 1.14882 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 157.5calibrated Vbg = 1.15015 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 144.4calibrated Vbg = 1.15013 :::*/*/*/*/
[18:10:03.510] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 157.3calibrated Vbg = 1.15656 :::*/*/*/*/
[18:10:03.512] <TB1> INFO: ----------------------------------------------------------------------
[18:10:03.512] <TB1> INFO: PixTestReadback::CalibrateIa()
[18:10:03.512] <TB1> INFO: ----------------------------------------------------------------------
[18:12:43.811] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C0.dat
[18:12:43.811] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C1.dat
[18:12:43.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C2.dat
[18:12:43.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C3.dat
[18:12:43.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C4.dat
[18:12:43.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C5.dat
[18:12:43.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C6.dat
[18:12:43.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C7.dat
[18:12:43.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C8.dat
[18:12:43.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C9.dat
[18:12:43.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C10.dat
[18:12:43.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C11.dat
[18:12:43.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C12.dat
[18:12:43.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C13.dat
[18:12:43.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C14.dat
[18:12:43.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//readbackCal_C15.dat
[18:12:43.842] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[18:12:43.843] <TB1> INFO: PixTestReadback::doTest() done
[18:12:43.843] <TB1> INFO: Decoding statistics:
[18:12:43.843] <TB1> INFO: General information:
[18:12:43.843] <TB1> INFO: 16bit words read: 1536
[18:12:43.843] <TB1> INFO: valid events total: 256
[18:12:43.843] <TB1> INFO: empty events: 256
[18:12:43.843] <TB1> INFO: valid events with pixels: 0
[18:12:43.843] <TB1> INFO: valid pixel hits: 0
[18:12:43.843] <TB1> INFO: Event errors: 0
[18:12:43.843] <TB1> INFO: start marker: 0
[18:12:43.843] <TB1> INFO: stop marker: 0
[18:12:43.843] <TB1> INFO: overflow: 0
[18:12:43.843] <TB1> INFO: invalid 5bit words: 0
[18:12:43.843] <TB1> INFO: invalid XOR eye diagram: 0
[18:12:43.843] <TB1> INFO: frame (failed synchr.): 0
[18:12:43.843] <TB1> INFO: idle data (no TBM trl): 0
[18:12:43.843] <TB1> INFO: no data (only TBM hdr): 0
[18:12:43.843] <TB1> INFO: TBM errors: 0
[18:12:43.843] <TB1> INFO: flawed TBM headers: 0
[18:12:43.843] <TB1> INFO: flawed TBM trailers: 0
[18:12:43.843] <TB1> INFO: event ID mismatches: 0
[18:12:43.843] <TB1> INFO: ROC errors: 0
[18:12:43.843] <TB1> INFO: missing ROC header(s): 0
[18:12:43.843] <TB1> INFO: misplaced readback start: 0
[18:12:43.843] <TB1> INFO: Pixel decoding errors: 0
[18:12:43.843] <TB1> INFO: pixel data incomplete: 0
[18:12:43.843] <TB1> INFO: pixel address: 0
[18:12:43.843] <TB1> INFO: pulse height fill bit: 0
[18:12:43.843] <TB1> INFO: buffer corruption: 0
[18:12:43.879] <TB1> INFO: ######################################################################
[18:12:43.879] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[18:12:43.879] <TB1> INFO: ######################################################################
[18:12:43.881] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[18:12:43.892] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[18:12:43.892] <TB1> INFO: run 1 of 1
[18:12:44.123] <TB1> INFO: Expecting 3120000 events.
[18:13:14.426] <TB1> INFO: 673230 events read in total (29712ms).




















[18:13:43.731] <TB1> INFO: 1336685 events read in total (59016ms).











[18:14:13.079] <TB1> INFO: 1994540 events read in total (88364ms).











[18:14:42.055] <TB1> INFO: 2652485 events read in total (117340ms).











[18:15:03.114] <TB1> INFO: 3120000 events read in total (138399ms).
[18:15:03.170] <TB1> INFO: Test took 139279ms.
[18:15:30.376] <TB1> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 166 seconds
[18:15:30.376] <TB1> INFO: number of dead bumps (per ROC): 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 0
[18:15:30.376] <TB1> INFO: separation cut (per ROC): 102 119 101 111 104 107 115 110 108 108 125 102 107 108 99 106
[18:15:30.376] <TB1> INFO: Decoding statistics:
[18:15:30.376] <TB1> INFO: General information:
[18:15:30.376] <TB1> INFO: 16bit words read: 0
[18:15:30.376] <TB1> INFO: valid events total: 0
[18:15:30.376] <TB1> INFO: empty events: 0
[18:15:30.376] <TB1> INFO: valid events with pixels: 0
[18:15:30.376] <TB1> INFO: valid pixel hits: 0
[18:15:30.376] <TB1> INFO: Event errors: 0
[18:15:30.376] <TB1> INFO: start marker: 0
[18:15:30.376] <TB1> INFO: stop marker: 0
[18:15:30.376] <TB1> INFO: overflow: 0
[18:15:30.376] <TB1> INFO: invalid 5bit words: 0
[18:15:30.376] <TB1> INFO: invalid XOR eye diagram: 0
[18:15:30.376] <TB1> INFO: frame (failed synchr.): 0
[18:15:30.376] <TB1> INFO: idle data (no TBM trl): 0
[18:15:30.376] <TB1> INFO: no data (only TBM hdr): 0
[18:15:30.376] <TB1> INFO: TBM errors: 0
[18:15:30.376] <TB1> INFO: flawed TBM headers: 0
[18:15:30.376] <TB1> INFO: flawed TBM trailers: 0
[18:15:30.376] <TB1> INFO: event ID mismatches: 0
[18:15:30.376] <TB1> INFO: ROC errors: 0
[18:15:30.377] <TB1> INFO: missing ROC header(s): 0
[18:15:30.377] <TB1> INFO: misplaced readback start: 0
[18:15:30.377] <TB1> INFO: Pixel decoding errors: 0
[18:15:30.377] <TB1> INFO: pixel data incomplete: 0
[18:15:30.377] <TB1> INFO: pixel address: 0
[18:15:30.377] <TB1> INFO: pulse height fill bit: 0
[18:15:30.377] <TB1> INFO: buffer corruption: 0
[18:15:30.428] <TB1> INFO: ######################################################################
[18:15:30.428] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[18:15:30.428] <TB1> INFO: ######################################################################
[18:15:30.428] <TB1> INFO: ----------------------------------------------------------------------
[18:15:30.428] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[18:15:30.428] <TB1> INFO: ----------------------------------------------------------------------
[18:15:30.428] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[18:15:30.440] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[18:15:30.440] <TB1> INFO: run 1 of 1
[18:15:30.761] <TB1> INFO: Expecting 36608000 events.
[18:15:54.131] <TB1> INFO: 699250 events read in total (22776ms).
[18:16:16.799] <TB1> INFO: 1380800 events read in total (45444ms).
[18:16:39.493] <TB1> INFO: 2062000 events read in total (68138ms).
[18:17:02.216] <TB1> INFO: 2741150 events read in total (90861ms).
[18:17:24.883] <TB1> INFO: 3421700 events read in total (113528ms).
[18:17:47.267] <TB1> INFO: 4100600 events read in total (135912ms).
[18:18:09.758] <TB1> INFO: 4780350 events read in total (158403ms).
[18:18:32.013] <TB1> INFO: 5459350 events read in total (180658ms).
[18:18:54.422] <TB1> INFO: 6136550 events read in total (203067ms).
[18:19:16.723] <TB1> INFO: 6812850 events read in total (225369ms).
[18:19:39.288] <TB1> INFO: 7491250 events read in total (247933ms).
[18:20:01.812] <TB1> INFO: 8168150 events read in total (270457ms).
[18:20:24.229] <TB1> INFO: 8845800 events read in total (292874ms).
[18:20:46.883] <TB1> INFO: 9524100 events read in total (315528ms).
[18:21:09.214] <TB1> INFO: 10200100 events read in total (337859ms).
[18:21:31.453] <TB1> INFO: 10876400 events read in total (360098ms).
[18:21:54.003] <TB1> INFO: 11552750 events read in total (382648ms).
[18:22:16.632] <TB1> INFO: 12229300 events read in total (405277ms).
[18:22:39.054] <TB1> INFO: 12907150 events read in total (427699ms).
[18:23:01.651] <TB1> INFO: 13585600 events read in total (450296ms).
[18:23:24.132] <TB1> INFO: 14263050 events read in total (472777ms).
[18:23:46.479] <TB1> INFO: 14939450 events read in total (495124ms).
[18:24:09.028] <TB1> INFO: 15614100 events read in total (517673ms).
[18:24:31.670] <TB1> INFO: 16286950 events read in total (540315ms).
[18:24:53.999] <TB1> INFO: 16961450 events read in total (562644ms).
[18:25:16.342] <TB1> INFO: 17635250 events read in total (584987ms).
[18:25:38.764] <TB1> INFO: 18309500 events read in total (607409ms).
[18:26:01.257] <TB1> INFO: 18979800 events read in total (629902ms).
[18:26:23.873] <TB1> INFO: 19649200 events read in total (652518ms).
[18:26:46.463] <TB1> INFO: 20319100 events read in total (675108ms).
[18:27:08.804] <TB1> INFO: 20989400 events read in total (697449ms).
[18:27:31.171] <TB1> INFO: 21659800 events read in total (719816ms).
[18:27:53.678] <TB1> INFO: 22329850 events read in total (742323ms).
[18:28:16.230] <TB1> INFO: 22999900 events read in total (764875ms).
[18:28:38.560] <TB1> INFO: 23669900 events read in total (787205ms).
[18:29:00.998] <TB1> INFO: 24340350 events read in total (809643ms).
[18:29:23.468] <TB1> INFO: 25009600 events read in total (832113ms).
[18:29:45.911] <TB1> INFO: 25679750 events read in total (854556ms).
[18:30:08.235] <TB1> INFO: 26348500 events read in total (876880ms).
[18:30:30.736] <TB1> INFO: 27016500 events read in total (899381ms).
[18:30:53.204] <TB1> INFO: 27684500 events read in total (921849ms).
[18:31:15.648] <TB1> INFO: 28352400 events read in total (944293ms).
[18:31:37.001] <TB1> INFO: 29018650 events read in total (966646ms).
[18:31:59.945] <TB1> INFO: 29682400 events read in total (988590ms).
[18:32:22.102] <TB1> INFO: 30349300 events read in total (1010747ms).
[18:32:44.339] <TB1> INFO: 31015750 events read in total (1032984ms).
[18:33:06.618] <TB1> INFO: 31679250 events read in total (1055263ms).
[18:33:28.781] <TB1> INFO: 32342800 events read in total (1077426ms).
[18:33:50.927] <TB1> INFO: 33006250 events read in total (1099572ms).
[18:34:13.265] <TB1> INFO: 33669800 events read in total (1121910ms).
[18:34:35.643] <TB1> INFO: 34339150 events read in total (1144288ms).
[18:34:58.067] <TB1> INFO: 35007450 events read in total (1166712ms).
[18:35:20.239] <TB1> INFO: 35675050 events read in total (1188884ms).
[18:35:42.691] <TB1> INFO: 36350650 events read in total (1211336ms).
[18:35:51.346] <TB1> INFO: 36608000 events read in total (1219991ms).
[18:35:51.397] <TB1> INFO: Test took 1220956ms.
[18:35:51.728] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:35:53.146] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:35:54.851] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:35:56.477] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:35:58.323] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:35:59.980] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:36:01.603] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:36:03.555] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:36:05.455] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:36:07.490] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:36:09.403] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:36:11.379] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:36:13.274] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:36:15.332] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:36:17.350] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:36:19.302] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[18:36:21.375] <TB1> INFO: PixTestScurves::scurves() done
[18:36:21.375] <TB1> INFO: Vcal mean: 123.05 136.73 123.06 119.73 123.82 125.94 121.12 125.81 124.21 129.76 132.23 108.11 129.45 132.12 108.23 125.34
[18:36:21.375] <TB1> INFO: Vcal RMS: 6.06 5.74 6.39 5.31 6.88 5.91 5.88 6.53 7.59 6.90 6.39 4.78 5.83 6.06 5.00 5.62
[18:36:21.375] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1250 seconds
[18:36:21.375] <TB1> INFO: Decoding statistics:
[18:36:21.375] <TB1> INFO: General information:
[18:36:21.375] <TB1> INFO: 16bit words read: 0
[18:36:21.375] <TB1> INFO: valid events total: 0
[18:36:21.375] <TB1> INFO: empty events: 0
[18:36:21.375] <TB1> INFO: valid events with pixels: 0
[18:36:21.375] <TB1> INFO: valid pixel hits: 0
[18:36:21.375] <TB1> INFO: Event errors: 0
[18:36:21.375] <TB1> INFO: start marker: 0
[18:36:21.375] <TB1> INFO: stop marker: 0
[18:36:21.375] <TB1> INFO: overflow: 0
[18:36:21.375] <TB1> INFO: invalid 5bit words: 0
[18:36:21.375] <TB1> INFO: invalid XOR eye diagram: 0
[18:36:21.375] <TB1> INFO: frame (failed synchr.): 0
[18:36:21.375] <TB1> INFO: idle data (no TBM trl): 0
[18:36:21.375] <TB1> INFO: no data (only TBM hdr): 0
[18:36:21.375] <TB1> INFO: TBM errors: 0
[18:36:21.375] <TB1> INFO: flawed TBM headers: 0
[18:36:21.375] <TB1> INFO: flawed TBM trailers: 0
[18:36:21.375] <TB1> INFO: event ID mismatches: 0
[18:36:21.375] <TB1> INFO: ROC errors: 0
[18:36:21.375] <TB1> INFO: missing ROC header(s): 0
[18:36:21.375] <TB1> INFO: misplaced readback start: 0
[18:36:21.375] <TB1> INFO: Pixel decoding errors: 0
[18:36:21.375] <TB1> INFO: pixel data incomplete: 0
[18:36:21.375] <TB1> INFO: pixel address: 0
[18:36:21.375] <TB1> INFO: pulse height fill bit: 0
[18:36:21.375] <TB1> INFO: buffer corruption: 0
[18:36:21.446] <TB1> INFO: ######################################################################
[18:36:21.446] <TB1> INFO: PixTestTrim::doTest()
[18:36:21.446] <TB1> INFO: ######################################################################
[18:36:21.448] <TB1> INFO: ----------------------------------------------------------------------
[18:36:21.448] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[18:36:21.448] <TB1> INFO: ----------------------------------------------------------------------
[18:36:21.500] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[18:36:21.500] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[18:36:21.509] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:36:21.509] <TB1> INFO: run 1 of 1
[18:36:21.759] <TB1> INFO: Expecting 5025280 events.
[18:36:52.128] <TB1> INFO: 834872 events read in total (29774ms).
[18:37:21.828] <TB1> INFO: 1668104 events read in total (59474ms).
[18:37:51.654] <TB1> INFO: 2497296 events read in total (89300ms).
[18:38:21.331] <TB1> INFO: 3322560 events read in total (118977ms).
[18:38:51.095] <TB1> INFO: 4143616 events read in total (148742ms).
[18:39:20.323] <TB1> INFO: 4961888 events read in total (177969ms).
[18:39:22.994] <TB1> INFO: 5025280 events read in total (180641ms).
[18:39:23.034] <TB1> INFO: Test took 181525ms.
[18:39:40.170] <TB1> INFO: ROC 0 VthrComp = 126
[18:39:40.170] <TB1> INFO: ROC 1 VthrComp = 135
[18:39:40.170] <TB1> INFO: ROC 2 VthrComp = 123
[18:39:40.170] <TB1> INFO: ROC 3 VthrComp = 125
[18:39:40.170] <TB1> INFO: ROC 4 VthrComp = 126
[18:39:40.170] <TB1> INFO: ROC 5 VthrComp = 131
[18:39:40.170] <TB1> INFO: ROC 6 VthrComp = 129
[18:39:40.171] <TB1> INFO: ROC 7 VthrComp = 126
[18:39:40.171] <TB1> INFO: ROC 8 VthrComp = 129
[18:39:40.171] <TB1> INFO: ROC 9 VthrComp = 126
[18:39:40.171] <TB1> INFO: ROC 10 VthrComp = 132
[18:39:40.171] <TB1> INFO: ROC 11 VthrComp = 113
[18:39:40.171] <TB1> INFO: ROC 12 VthrComp = 134
[18:39:40.171] <TB1> INFO: ROC 13 VthrComp = 133
[18:39:40.171] <TB1> INFO: ROC 14 VthrComp = 113
[18:39:40.171] <TB1> INFO: ROC 15 VthrComp = 132
[18:39:40.423] <TB1> INFO: Expecting 41600 events.
[18:39:43.881] <TB1> INFO: 41600 events read in total (2866ms).
[18:39:43.882] <TB1> INFO: Test took 3709ms.
[18:39:43.890] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[18:39:43.891] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[18:39:43.900] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:39:43.900] <TB1> INFO: run 1 of 1
[18:39:44.177] <TB1> INFO: Expecting 5025280 events.
[18:40:10.445] <TB1> INFO: 591976 events read in total (25676ms).
[18:40:35.715] <TB1> INFO: 1182416 events read in total (50946ms).
[18:41:01.314] <TB1> INFO: 1772424 events read in total (76545ms).
[18:41:26.654] <TB1> INFO: 2361168 events read in total (101885ms).
[18:41:51.654] <TB1> INFO: 2947592 events read in total (126886ms).
[18:42:16.830] <TB1> INFO: 3532712 events read in total (152061ms).
[18:42:41.813] <TB1> INFO: 4116496 events read in total (177044ms).
[18:43:07.414] <TB1> INFO: 4699456 events read in total (202645ms).
[18:43:21.973] <TB1> INFO: 5025280 events read in total (217204ms).
[18:43:22.030] <TB1> INFO: Test took 218130ms.
[18:43:48.310] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 57.7116 for pixel 48/71 mean/min/max = 45.3705/32.9879/57.7532
[18:43:48.311] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 63.5446 for pixel 0/17 mean/min/max = 50.093/36.5166/63.6694
[18:43:48.312] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 60.3242 for pixel 2/37 mean/min/max = 46.5537/32.6189/60.4885
[18:43:48.313] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 58.016 for pixel 14/75 mean/min/max = 45.7759/33.5266/58.0252
[18:43:48.314] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 58.5478 for pixel 0/10 mean/min/max = 45.339/32.0912/58.5868
[18:43:48.315] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 59.6639 for pixel 0/28 mean/min/max = 46.5349/33.2978/59.7719
[18:43:48.315] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 55.9384 for pixel 3/73 mean/min/max = 43.7981/31.1961/56.4001
[18:43:48.316] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 60.9992 for pixel 7/5 mean/min/max = 46.3985/31.6551/61.1419
[18:43:48.317] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 63.4808 for pixel 6/50 mean/min/max = 47.2672/30.9639/63.5705
[18:43:48.317] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 66.9754 for pixel 0/3 mean/min/max = 48.8104/30.5412/67.0795
[18:43:48.318] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 67.1225 for pixel 0/14 mean/min/max = 52.1172/37.0659/67.1685
[18:43:48.319] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 56.2836 for pixel 20/69 mean/min/max = 44.64/32.8019/56.4781
[18:43:48.319] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 60.7901 for pixel 13/21 mean/min/max = 48.4267/35.9604/60.8931
[18:43:48.320] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 60.4475 for pixel 24/2 mean/min/max = 47.8096/35.0826/60.5366
[18:43:48.320] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 57.0711 for pixel 20/77 mean/min/max = 44.9821/32.8332/57.1309
[18:43:48.321] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 59.3755 for pixel 19/11 mean/min/max = 46.5394/33.5153/59.5636
[18:43:48.321] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:43:48.410] <TB1> INFO: Expecting 411648 events.
[18:43:57.916] <TB1> INFO: 411648 events read in total (8914ms).
[18:43:57.926] <TB1> INFO: Expecting 411648 events.
[18:44:07.145] <TB1> INFO: 411648 events read in total (8816ms).
[18:44:07.157] <TB1> INFO: Expecting 411648 events.
[18:44:16.412] <TB1> INFO: 411648 events read in total (8852ms).
[18:44:16.425] <TB1> INFO: Expecting 411648 events.
[18:44:25.498] <TB1> INFO: 411648 events read in total (8670ms).
[18:44:25.514] <TB1> INFO: Expecting 411648 events.
[18:44:34.511] <TB1> INFO: 411648 events read in total (8594ms).
[18:44:34.535] <TB1> INFO: Expecting 411648 events.
[18:44:43.573] <TB1> INFO: 411648 events read in total (8635ms).
[18:44:43.597] <TB1> INFO: Expecting 411648 events.
[18:44:52.676] <TB1> INFO: 411648 events read in total (8676ms).
[18:44:52.698] <TB1> INFO: Expecting 411648 events.
[18:45:01.714] <TB1> INFO: 411648 events read in total (8613ms).
[18:45:01.745] <TB1> INFO: Expecting 411648 events.
[18:45:10.816] <TB1> INFO: 411648 events read in total (8668ms).
[18:45:10.847] <TB1> INFO: Expecting 411648 events.
[18:45:19.901] <TB1> INFO: 411648 events read in total (8651ms).
[18:45:19.941] <TB1> INFO: Expecting 411648 events.
[18:45:28.954] <TB1> INFO: 411648 events read in total (8610ms).
[18:45:28.986] <TB1> INFO: Expecting 411648 events.
[18:45:37.969] <TB1> INFO: 411648 events read in total (8580ms).
[18:45:37.003] <TB1> INFO: Expecting 411648 events.
[18:45:47.063] <TB1> INFO: 411648 events read in total (8658ms).
[18:45:47.100] <TB1> INFO: Expecting 411648 events.
[18:45:56.157] <TB1> INFO: 411648 events read in total (8654ms).
[18:45:56.211] <TB1> INFO: Expecting 411648 events.
[18:46:05.207] <TB1> INFO: 411648 events read in total (8593ms).
[18:46:05.249] <TB1> INFO: Expecting 411648 events.
[18:46:14.289] <TB1> INFO: 411648 events read in total (8637ms).
[18:46:14.333] <TB1> INFO: Test took 146012ms.
[18:46:14.993] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[18:46:15.003] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:46:15.003] <TB1> INFO: run 1 of 1
[18:46:15.235] <TB1> INFO: Expecting 5025280 events.
[18:46:41.208] <TB1> INFO: 588024 events read in total (25381ms).
[18:47:06.955] <TB1> INFO: 1173768 events read in total (51128ms).
[18:47:32.313] <TB1> INFO: 1758040 events read in total (76486ms).
[18:47:58.019] <TB1> INFO: 2340560 events read in total (102192ms).
[18:48:23.591] <TB1> INFO: 2925400 events read in total (127764ms).
[18:48:49.399] <TB1> INFO: 3509936 events read in total (153572ms).
[18:49:14.688] <TB1> INFO: 4093608 events read in total (178861ms).
[18:49:39.961] <TB1> INFO: 4678096 events read in total (204134ms).
[18:49:55.407] <TB1> INFO: 5025280 events read in total (219580ms).
[18:49:55.539] <TB1> INFO: Test took 220537ms.
[18:50:20.978] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 11.589819 .. 143.693582
[18:50:21.213] <TB1> INFO: Expecting 208000 events.
[18:50:31.324] <TB1> INFO: 208000 events read in total (9520ms).
[18:50:31.325] <TB1> INFO: Test took 10346ms.
[18:50:31.392] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 153 (-1/-1) hits flags = 528 (plus default)
[18:50:31.403] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:50:31.403] <TB1> INFO: run 1 of 1
[18:50:31.685] <TB1> INFO: Expecting 5091840 events.
[18:50:57.753] <TB1> INFO: 584608 events read in total (25476ms).
[18:51:23.078] <TB1> INFO: 1169336 events read in total (50802ms).
[18:51:48.196] <TB1> INFO: 1753832 events read in total (75920ms).
[18:52:13.717] <TB1> INFO: 2338952 events read in total (101440ms).
[18:52:39.082] <TB1> INFO: 2924272 events read in total (126805ms).
[18:53:04.282] <TB1> INFO: 3508576 events read in total (152005ms).
[18:53:29.743] <TB1> INFO: 4092320 events read in total (177466ms).
[18:53:55.800] <TB1> INFO: 4675336 events read in total (203523ms).
[18:54:13.985] <TB1> INFO: 5091840 events read in total (221708ms).
[18:54:14.096] <TB1> INFO: Test took 222694ms.
[18:54:39.160] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.382685 .. 45.871673
[18:54:39.401] <TB1> INFO: Expecting 208000 events.
[18:54:49.892] <TB1> INFO: 208000 events read in total (9900ms).
[18:54:49.893] <TB1> INFO: Test took 10731ms.
[18:54:49.955] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 55 (-1/-1) hits flags = 528 (plus default)
[18:54:49.964] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:54:49.964] <TB1> INFO: run 1 of 1
[18:54:50.242] <TB1> INFO: Expecting 1297920 events.
[18:55:18.098] <TB1> INFO: 659856 events read in total (27264ms).
[18:55:44.770] <TB1> INFO: 1297920 events read in total (53937ms).
[18:55:44.805] <TB1> INFO: Test took 54841ms.
[18:55:58.947] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 26.360714 .. 47.704594
[18:55:59.204] <TB1> INFO: Expecting 208000 events.
[18:56:09.107] <TB1> INFO: 208000 events read in total (9312ms).
[18:56:09.108] <TB1> INFO: Test took 10160ms.
[18:56:09.159] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[18:56:09.169] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:56:09.169] <TB1> INFO: run 1 of 1
[18:56:09.447] <TB1> INFO: Expecting 1397760 events.
[18:56:37.240] <TB1> INFO: 656784 events read in total (27201ms).
[18:57:04.406] <TB1> INFO: 1312304 events read in total (54367ms).
[18:57:08.385] <TB1> INFO: 1397760 events read in total (58347ms).
[18:57:08.411] <TB1> INFO: Test took 59242ms.
[18:57:23.491] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 24.149810 .. 47.995589
[18:57:23.724] <TB1> INFO: Expecting 208000 events.
[18:57:33.427] <TB1> INFO: 208000 events read in total (9112ms).
[18:57:33.428] <TB1> INFO: Test took 9936ms.
[18:57:33.474] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 57 (-1/-1) hits flags = 528 (plus default)
[18:57:33.482] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:57:33.482] <TB1> INFO: run 1 of 1
[18:57:33.760] <TB1> INFO: Expecting 1464320 events.
[18:58:01.508] <TB1> INFO: 664224 events read in total (27156ms).
[18:58:28.867] <TB1> INFO: 1328072 events read in total (54515ms).
[18:58:34.742] <TB1> INFO: 1464320 events read in total (60390ms).
[18:58:34.776] <TB1> INFO: Test took 61294ms.
[18:58:48.485] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[18:58:48.485] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[18:58:48.497] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:58:48.497] <TB1> INFO: run 1 of 1
[18:58:48.769] <TB1> INFO: Expecting 1364480 events.
[18:59:17.396] <TB1> INFO: 668456 events read in total (28036ms).
[18:59:45.026] <TB1> INFO: 1336096 events read in total (55666ms).
[18:59:46.600] <TB1> INFO: 1364480 events read in total (57241ms).
[18:59:46.622] <TB1> INFO: Test took 58126ms.
[18:59:58.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C0.dat
[18:59:58.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C1.dat
[18:59:58.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C2.dat
[18:59:58.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C3.dat
[18:59:58.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C4.dat
[18:59:58.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C5.dat
[18:59:58.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C6.dat
[18:59:58.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C7.dat
[18:59:58.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C8.dat
[18:59:58.501] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C9.dat
[18:59:58.501] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C10.dat
[18:59:58.501] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C11.dat
[18:59:58.501] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C12.dat
[18:59:58.501] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C13.dat
[18:59:58.501] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C14.dat
[18:59:58.501] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C15.dat
[18:59:58.501] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C0.dat
[18:59:58.509] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C1.dat
[18:59:58.516] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C2.dat
[18:59:58.523] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C3.dat
[18:59:58.531] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C4.dat
[18:59:58.538] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C5.dat
[18:59:58.546] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C6.dat
[18:59:58.553] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C7.dat
[18:59:58.561] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C8.dat
[18:59:58.569] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C9.dat
[18:59:58.577] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C10.dat
[18:59:58.583] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C11.dat
[18:59:58.589] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C12.dat
[18:59:58.595] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C13.dat
[18:59:58.603] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C14.dat
[18:59:58.610] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters35_C15.dat
[18:59:58.617] <TB1> INFO: PixTestTrim::trimTest() done
[18:59:58.617] <TB1> INFO: vtrim: 113 145 164 141 140 131 127 129 152 165 168 116 140 158 140 141
[18:59:58.617] <TB1> INFO: vthrcomp: 126 135 123 125 126 131 129 126 129 126 132 113 134 133 113 132
[18:59:58.617] <TB1> INFO: vcal mean: 35.04 35.00 35.20 34.85 34.92 35.01 34.94 35.31 35.09 35.29 35.04 34.95 35.26 35.23 35.03 35.01
[18:59:58.617] <TB1> INFO: vcal RMS: 1.14 1.14 1.33 1.03 1.39 1.01 0.99 1.41 1.19 1.55 1.06 1.04 1.35 1.25 1.08 1.04
[18:59:58.617] <TB1> INFO: bits mean: 9.53 7.48 10.40 9.50 9.94 8.91 10.51 10.40 9.66 9.70 7.60 10.03 9.17 9.65 10.43 9.84
[18:59:58.617] <TB1> INFO: bits RMS: 2.64 2.54 2.24 2.51 2.51 2.77 2.46 2.38 2.65 2.67 2.33 2.43 2.25 2.20 2.19 2.32
[18:59:58.625] <TB1> INFO: ----------------------------------------------------------------------
[18:59:58.625] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[18:59:58.625] <TB1> INFO: ----------------------------------------------------------------------
[18:59:58.628] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[18:59:58.638] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[18:59:58.638] <TB1> INFO: run 1 of 1
[18:59:58.893] <TB1> INFO: Expecting 4160000 events.
[19:00:30.950] <TB1> INFO: 766810 events read in total (31466ms).
[19:01:02.288] <TB1> INFO: 1527295 events read in total (62804ms).
[19:01:33.693] <TB1> INFO: 2282445 events read in total (94209ms).
[19:02:05.013] <TB1> INFO: 3032870 events read in total (125529ms).
[19:02:36.277] <TB1> INFO: 3777125 events read in total (156793ms).
[19:02:52.665] <TB1> INFO: 4160000 events read in total (173181ms).
[19:02:52.730] <TB1> INFO: Test took 174091ms.
[19:03:18.682] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[19:03:18.692] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:03:18.692] <TB1> INFO: run 1 of 1
[19:03:18.925] <TB1> INFO: Expecting 4305600 events.
[19:03:50.262] <TB1> INFO: 730525 events read in total (30745ms).
[19:04:20.957] <TB1> INFO: 1455155 events read in total (61440ms).
[19:04:51.347] <TB1> INFO: 2177985 events read in total (91830ms).
[19:05:21.770] <TB1> INFO: 2895505 events read in total (122253ms).
[19:05:51.865] <TB1> INFO: 3609585 events read in total (152348ms).
[19:06:21.348] <TB1> INFO: 4305600 events read in total (181831ms).
[19:06:21.402] <TB1> INFO: Test took 182709ms.
[19:06:47.976] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 202 (-1/-1) hits flags = 528 (plus default)
[19:06:47.987] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:06:47.987] <TB1> INFO: run 1 of 1
[19:06:48.221] <TB1> INFO: Expecting 4222400 events.
[19:07:20.409] <TB1> INFO: 736300 events read in total (31597ms).
[19:07:51.096] <TB1> INFO: 1466550 events read in total (62284ms).
[19:08:21.657] <TB1> INFO: 2194275 events read in total (92845ms).
[19:08:52.244] <TB1> INFO: 2916865 events read in total (123432ms).
[19:09:22.777] <TB1> INFO: 3635645 events read in total (153965ms).
[19:09:47.514] <TB1> INFO: 4222400 events read in total (178702ms).
[19:09:47.572] <TB1> INFO: Test took 179585ms.
[19:10:15.203] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 202 (-1/-1) hits flags = 528 (plus default)
[19:10:15.213] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:10:15.213] <TB1> INFO: run 1 of 1
[19:10:15.447] <TB1> INFO: Expecting 4222400 events.
[19:10:48.032] <TB1> INFO: 736525 events read in total (31994ms).
[19:11:18.870] <TB1> INFO: 1466910 events read in total (62832ms).
[19:11:49.699] <TB1> INFO: 2194845 events read in total (93661ms).
[19:12:20.455] <TB1> INFO: 2917525 events read in total (124417ms).
[19:12:51.134] <TB1> INFO: 3636440 events read in total (155096ms).
[19:13:16.283] <TB1> INFO: 4222400 events read in total (180245ms).
[19:13:16.363] <TB1> INFO: Test took 181150ms.
[19:13:44.109] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[19:13:44.121] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:13:44.121] <TB1> INFO: run 1 of 1
[19:13:44.425] <TB1> INFO: Expecting 4243200 events.
[19:14:15.806] <TB1> INFO: 735285 events read in total (30789ms).
[19:14:46.735] <TB1> INFO: 1464495 events read in total (61718ms).
[19:15:17.279] <TB1> INFO: 2191020 events read in total (92262ms).
[19:15:48.013] <TB1> INFO: 2912470 events read in total (122996ms).
[19:16:18.643] <TB1> INFO: 3630375 events read in total (153626ms).
[19:16:44.880] <TB1> INFO: 4243200 events read in total (179863ms).
[19:16:44.954] <TB1> INFO: Test took 180833ms.
[19:17:13.049] <TB1> INFO: PixTestTrim::trimBitTest() done
[19:17:13.050] <TB1> INFO: PixTestTrim::doTest() done, duration: 2451 seconds
[19:17:13.050] <TB1> INFO: Decoding statistics:
[19:17:13.050] <TB1> INFO: General information:
[19:17:13.050] <TB1> INFO: 16bit words read: 0
[19:17:13.050] <TB1> INFO: valid events total: 0
[19:17:13.050] <TB1> INFO: empty events: 0
[19:17:13.050] <TB1> INFO: valid events with pixels: 0
[19:17:13.050] <TB1> INFO: valid pixel hits: 0
[19:17:13.050] <TB1> INFO: Event errors: 0
[19:17:13.050] <TB1> INFO: start marker: 0
[19:17:13.050] <TB1> INFO: stop marker: 0
[19:17:13.050] <TB1> INFO: overflow: 0
[19:17:13.050] <TB1> INFO: invalid 5bit words: 0
[19:17:13.050] <TB1> INFO: invalid XOR eye diagram: 0
[19:17:13.050] <TB1> INFO: frame (failed synchr.): 0
[19:17:13.050] <TB1> INFO: idle data (no TBM trl): 0
[19:17:13.050] <TB1> INFO: no data (only TBM hdr): 0
[19:17:13.050] <TB1> INFO: TBM errors: 0
[19:17:13.050] <TB1> INFO: flawed TBM headers: 0
[19:17:13.050] <TB1> INFO: flawed TBM trailers: 0
[19:17:13.050] <TB1> INFO: event ID mismatches: 0
[19:17:13.050] <TB1> INFO: ROC errors: 0
[19:17:13.050] <TB1> INFO: missing ROC header(s): 0
[19:17:13.050] <TB1> INFO: misplaced readback start: 0
[19:17:13.050] <TB1> INFO: Pixel decoding errors: 0
[19:17:13.050] <TB1> INFO: pixel data incomplete: 0
[19:17:13.050] <TB1> INFO: pixel address: 0
[19:17:13.050] <TB1> INFO: pulse height fill bit: 0
[19:17:13.050] <TB1> INFO: buffer corruption: 0
[19:17:13.811] <TB1> INFO: ######################################################################
[19:17:13.811] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[19:17:13.811] <TB1> INFO: ######################################################################
[19:17:14.060] <TB1> INFO: Expecting 41600 events.
[19:17:17.810] <TB1> INFO: 41600 events read in total (3159ms).
[19:17:17.811] <TB1> INFO: Test took 3999ms.
[19:17:18.280] <TB1> INFO: Expecting 41600 events.
[19:17:21.818] <TB1> INFO: 41600 events read in total (2946ms).
[19:17:21.819] <TB1> INFO: Test took 3805ms.
[19:17:22.107] <TB1> INFO: Expecting 41600 events.
[19:17:25.637] <TB1> INFO: 41600 events read in total (2938ms).
[19:17:25.638] <TB1> INFO: Test took 3795ms.
[19:17:25.926] <TB1> INFO: Expecting 41600 events.
[19:17:29.473] <TB1> INFO: 41600 events read in total (2955ms).
[19:17:29.474] <TB1> INFO: Test took 3812ms.
[19:17:29.764] <TB1> INFO: Expecting 41600 events.
[19:17:33.501] <TB1> INFO: 41600 events read in total (3145ms).
[19:17:33.502] <TB1> INFO: Test took 4003ms.
[19:17:33.790] <TB1> INFO: Expecting 41600 events.
[19:17:37.251] <TB1> INFO: 41600 events read in total (2870ms).
[19:17:37.252] <TB1> INFO: Test took 3727ms.
[19:17:37.540] <TB1> INFO: Expecting 41600 events.
[19:17:41.021] <TB1> INFO: 41600 events read in total (2890ms).
[19:17:41.022] <TB1> INFO: Test took 3747ms.
[19:17:41.310] <TB1> INFO: Expecting 41600 events.
[19:17:44.935] <TB1> INFO: 41600 events read in total (3033ms).
[19:17:44.936] <TB1> INFO: Test took 3890ms.
[19:17:45.224] <TB1> INFO: Expecting 41600 events.
[19:17:48.713] <TB1> INFO: 41600 events read in total (2897ms).
[19:17:48.714] <TB1> INFO: Test took 3754ms.
[19:17:49.005] <TB1> INFO: Expecting 41600 events.
[19:17:52.561] <TB1> INFO: 41600 events read in total (2965ms).
[19:17:52.562] <TB1> INFO: Test took 3822ms.
[19:17:52.850] <TB1> INFO: Expecting 41600 events.
[19:17:56.318] <TB1> INFO: 41600 events read in total (2876ms).
[19:17:56.319] <TB1> INFO: Test took 3734ms.
[19:17:56.618] <TB1> INFO: Expecting 41600 events.
[19:18:00.141] <TB1> INFO: 41600 events read in total (2931ms).
[19:18:00.141] <TB1> INFO: Test took 3796ms.
[19:18:00.429] <TB1> INFO: Expecting 41600 events.
[19:18:03.945] <TB1> INFO: 41600 events read in total (2924ms).
[19:18:03.946] <TB1> INFO: Test took 3782ms.
[19:18:04.242] <TB1> INFO: Expecting 41600 events.
[19:18:07.722] <TB1> INFO: 41600 events read in total (2888ms).
[19:18:07.722] <TB1> INFO: Test took 3752ms.
[19:18:08.013] <TB1> INFO: Expecting 41600 events.
[19:18:11.483] <TB1> INFO: 41600 events read in total (2879ms).
[19:18:11.484] <TB1> INFO: Test took 3736ms.
[19:18:11.772] <TB1> INFO: Expecting 41600 events.
[19:18:15.299] <TB1> INFO: 41600 events read in total (2935ms).
[19:18:15.300] <TB1> INFO: Test took 3793ms.
[19:18:15.588] <TB1> INFO: Expecting 41600 events.
[19:18:19.038] <TB1> INFO: 41600 events read in total (2858ms).
[19:18:19.038] <TB1> INFO: Test took 3715ms.
[19:18:19.327] <TB1> INFO: Expecting 41600 events.
[19:18:22.837] <TB1> INFO: 41600 events read in total (2919ms).
[19:18:22.837] <TB1> INFO: Test took 3775ms.
[19:18:23.125] <TB1> INFO: Expecting 41600 events.
[19:18:26.745] <TB1> INFO: 41600 events read in total (3028ms).
[19:18:26.746] <TB1> INFO: Test took 3885ms.
[19:18:27.037] <TB1> INFO: Expecting 41600 events.
[19:18:30.596] <TB1> INFO: 41600 events read in total (2968ms).
[19:18:30.597] <TB1> INFO: Test took 3825ms.
[19:18:30.885] <TB1> INFO: Expecting 41600 events.
[19:18:34.492] <TB1> INFO: 41600 events read in total (3015ms).
[19:18:34.493] <TB1> INFO: Test took 3873ms.
[19:18:34.781] <TB1> INFO: Expecting 41600 events.
[19:18:38.411] <TB1> INFO: 41600 events read in total (3039ms).
[19:18:38.412] <TB1> INFO: Test took 3896ms.
[19:18:38.700] <TB1> INFO: Expecting 41600 events.
[19:18:42.174] <TB1> INFO: 41600 events read in total (2882ms).
[19:18:42.175] <TB1> INFO: Test took 3740ms.
[19:18:42.465] <TB1> INFO: Expecting 41600 events.
[19:18:45.923] <TB1> INFO: 41600 events read in total (2865ms).
[19:18:45.924] <TB1> INFO: Test took 3723ms.
[19:18:46.212] <TB1> INFO: Expecting 41600 events.
[19:18:49.771] <TB1> INFO: 41600 events read in total (2967ms).
[19:18:49.772] <TB1> INFO: Test took 3825ms.
[19:18:50.061] <TB1> INFO: Expecting 41600 events.
[19:18:53.672] <TB1> INFO: 41600 events read in total (3020ms).
[19:18:53.672] <TB1> INFO: Test took 3876ms.
[19:18:53.962] <TB1> INFO: Expecting 41600 events.
[19:18:57.429] <TB1> INFO: 41600 events read in total (2876ms).
[19:18:57.430] <TB1> INFO: Test took 3733ms.
[19:18:57.719] <TB1> INFO: Expecting 2560 events.
[19:18:58.607] <TB1> INFO: 2560 events read in total (297ms).
[19:18:58.607] <TB1> INFO: Test took 1165ms.
[19:18:58.915] <TB1> INFO: Expecting 2560 events.
[19:18:59.801] <TB1> INFO: 2560 events read in total (294ms).
[19:18:59.802] <TB1> INFO: Test took 1195ms.
[19:19:00.110] <TB1> INFO: Expecting 2560 events.
[19:19:00.995] <TB1> INFO: 2560 events read in total (294ms).
[19:19:00.995] <TB1> INFO: Test took 1193ms.
[19:19:01.303] <TB1> INFO: Expecting 2560 events.
[19:19:02.186] <TB1> INFO: 2560 events read in total (291ms).
[19:19:02.186] <TB1> INFO: Test took 1190ms.
[19:19:02.494] <TB1> INFO: Expecting 2560 events.
[19:19:03.374] <TB1> INFO: 2560 events read in total (288ms).
[19:19:03.374] <TB1> INFO: Test took 1187ms.
[19:19:03.682] <TB1> INFO: Expecting 2560 events.
[19:19:04.560] <TB1> INFO: 2560 events read in total (287ms).
[19:19:04.560] <TB1> INFO: Test took 1186ms.
[19:19:04.868] <TB1> INFO: Expecting 2560 events.
[19:19:05.746] <TB1> INFO: 2560 events read in total (286ms).
[19:19:05.746] <TB1> INFO: Test took 1185ms.
[19:19:06.054] <TB1> INFO: Expecting 2560 events.
[19:19:06.934] <TB1> INFO: 2560 events read in total (289ms).
[19:19:06.935] <TB1> INFO: Test took 1189ms.
[19:19:07.242] <TB1> INFO: Expecting 2560 events.
[19:19:08.121] <TB1> INFO: 2560 events read in total (287ms).
[19:19:08.121] <TB1> INFO: Test took 1186ms.
[19:19:08.429] <TB1> INFO: Expecting 2560 events.
[19:19:09.306] <TB1> INFO: 2560 events read in total (285ms).
[19:19:09.306] <TB1> INFO: Test took 1184ms.
[19:19:09.613] <TB1> INFO: Expecting 2560 events.
[19:19:10.496] <TB1> INFO: 2560 events read in total (291ms).
[19:19:10.496] <TB1> INFO: Test took 1190ms.
[19:19:10.804] <TB1> INFO: Expecting 2560 events.
[19:19:11.683] <TB1> INFO: 2560 events read in total (288ms).
[19:19:11.683] <TB1> INFO: Test took 1187ms.
[19:19:11.991] <TB1> INFO: Expecting 2560 events.
[19:19:12.876] <TB1> INFO: 2560 events read in total (293ms).
[19:19:12.876] <TB1> INFO: Test took 1192ms.
[19:19:13.185] <TB1> INFO: Expecting 2560 events.
[19:19:14.067] <TB1> INFO: 2560 events read in total (291ms).
[19:19:14.067] <TB1> INFO: Test took 1190ms.
[19:19:14.376] <TB1> INFO: Expecting 2560 events.
[19:19:15.259] <TB1> INFO: 2560 events read in total (292ms).
[19:19:15.259] <TB1> INFO: Test took 1191ms.
[19:19:15.567] <TB1> INFO: Expecting 2560 events.
[19:19:16.450] <TB1> INFO: 2560 events read in total (291ms).
[19:19:16.450] <TB1> INFO: Test took 1190ms.
[19:19:16.453] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:19:16.759] <TB1> INFO: Expecting 655360 events.
[19:19:31.006] <TB1> INFO: 655360 events read in total (13655ms).
[19:19:31.017] <TB1> INFO: Expecting 655360 events.
[19:19:45.150] <TB1> INFO: 655360 events read in total (13730ms).
[19:19:45.165] <TB1> INFO: Expecting 655360 events.
[19:19:59.360] <TB1> INFO: 655360 events read in total (13792ms).
[19:19:59.379] <TB1> INFO: Expecting 655360 events.
[19:20:13.448] <TB1> INFO: 655360 events read in total (13666ms).
[19:20:13.472] <TB1> INFO: Expecting 655360 events.
[19:20:27.615] <TB1> INFO: 655360 events read in total (13740ms).
[19:20:27.652] <TB1> INFO: Expecting 655360 events.
[19:20:41.623] <TB1> INFO: 655360 events read in total (13568ms).
[19:20:41.657] <TB1> INFO: Expecting 655360 events.
[19:20:55.849] <TB1> INFO: 655360 events read in total (13789ms).
[19:20:55.899] <TB1> INFO: Expecting 655360 events.
[19:21:09.900] <TB1> INFO: 655360 events read in total (13598ms).
[19:21:09.942] <TB1> INFO: Expecting 655360 events.
[19:21:23.736] <TB1> INFO: 655360 events read in total (13391ms).
[19:21:23.781] <TB1> INFO: Expecting 655360 events.
[19:21:37.773] <TB1> INFO: 655360 events read in total (13589ms).
[19:21:37.819] <TB1> INFO: Expecting 655360 events.
[19:21:51.861] <TB1> INFO: 655360 events read in total (13639ms).
[19:21:51.919] <TB1> INFO: Expecting 655360 events.
[19:22:05.950] <TB1> INFO: 655360 events read in total (13628ms).
[19:22:06.008] <TB1> INFO: Expecting 655360 events.
[19:22:20.005] <TB1> INFO: 655360 events read in total (13594ms).
[19:22:20.086] <TB1> INFO: Expecting 655360 events.
[19:22:34.298] <TB1> INFO: 655360 events read in total (13809ms).
[19:22:34.365] <TB1> INFO: Expecting 655360 events.
[19:22:48.462] <TB1> INFO: 655360 events read in total (13694ms).
[19:22:48.554] <TB1> INFO: Expecting 655360 events.
[19:23:02.520] <TB1> INFO: 655360 events read in total (13563ms).
[19:23:02.602] <TB1> INFO: Test took 226149ms.
[19:23:02.681] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:23:02.946] <TB1> INFO: Expecting 655360 events.
[19:23:16.832] <TB1> INFO: 655360 events read in total (13295ms).
[19:23:16.842] <TB1> INFO: Expecting 655360 events.
[19:23:30.765] <TB1> INFO: 655360 events read in total (13520ms).
[19:23:30.784] <TB1> INFO: Expecting 655360 events.
[19:23:44.732] <TB1> INFO: 655360 events read in total (13546ms).
[19:23:44.759] <TB1> INFO: Expecting 655360 events.
[19:23:58.776] <TB1> INFO: 655360 events read in total (13614ms).
[19:23:58.800] <TB1> INFO: Expecting 655360 events.
[19:24:12.742] <TB1> INFO: 655360 events read in total (13539ms).
[19:24:12.769] <TB1> INFO: Expecting 655360 events.
[19:24:26.807] <TB1> INFO: 655360 events read in total (13635ms).
[19:24:26.847] <TB1> INFO: Expecting 655360 events.
[19:24:40.787] <TB1> INFO: 655360 events read in total (13537ms).
[19:24:40.821] <TB1> INFO: Expecting 655360 events.
[19:24:54.764] <TB1> INFO: 655360 events read in total (13540ms).
[19:24:54.802] <TB1> INFO: Expecting 655360 events.
[19:25:08.711] <TB1> INFO: 655360 events read in total (13506ms).
[19:25:08.755] <TB1> INFO: Expecting 655360 events.
[19:25:22.593] <TB1> INFO: 655360 events read in total (13435ms).
[19:25:22.640] <TB1> INFO: Expecting 655360 events.
[19:25:36.633] <TB1> INFO: 655360 events read in total (13590ms).
[19:25:36.686] <TB1> INFO: Expecting 655360 events.
[19:25:50.619] <TB1> INFO: 655360 events read in total (13531ms).
[19:25:50.675] <TB1> INFO: Expecting 655360 events.
[19:26:04.557] <TB1> INFO: 655360 events read in total (13479ms).
[19:26:04.618] <TB1> INFO: Expecting 655360 events.
[19:26:18.211] <TB1> INFO: 655360 events read in total (13191ms).
[19:26:18.299] <TB1> INFO: Expecting 655360 events.
[19:26:32.153] <TB1> INFO: 655360 events read in total (13452ms).
[19:26:32.248] <TB1> INFO: Expecting 655360 events.
[19:26:46.012] <TB1> INFO: 655360 events read in total (13361ms).
[19:26:46.087] <TB1> INFO: Test took 223406ms.
[19:26:46.242] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.247] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.251] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.256] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.260] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.265] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[19:26:46.269] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[19:26:46.274] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[19:26:46.278] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[19:26:46.283] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[19:26:46.287] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[19:26:46.292] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[19:26:46.296] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[19:26:46.301] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.305] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[19:26:46.310] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[19:26:46.314] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.319] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.323] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.328] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[19:26:46.333] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[19:26:46.338] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[19:26:46.343] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[19:26:46.348] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.353] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.357] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.362] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[19:26:46.367] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[19:26:46.371] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[19:26:46.376] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[19:26:46.381] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[19:26:46.385] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[19:26:46.390] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[19:26:46.395] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[19:26:46.399] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[19:26:46.404] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.408] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[19:26:46.413] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[19:26:46.417] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[19:26:46.422] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[19:26:46.426] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.431] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.435] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[19:26:46.469] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C0.dat
[19:26:46.469] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C1.dat
[19:26:46.469] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C2.dat
[19:26:46.469] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C3.dat
[19:26:46.469] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C4.dat
[19:26:46.469] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C5.dat
[19:26:46.469] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C6.dat
[19:26:46.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C7.dat
[19:26:46.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C8.dat
[19:26:46.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C9.dat
[19:26:46.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C10.dat
[19:26:46.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C11.dat
[19:26:46.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C12.dat
[19:26:46.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C13.dat
[19:26:46.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C14.dat
[19:26:46.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters35_C15.dat
[19:26:46.706] <TB1> INFO: Expecting 41600 events.
[19:26:49.787] <TB1> INFO: 41600 events read in total (2490ms).
[19:26:49.788] <TB1> INFO: Test took 3314ms.
[19:26:50.237] <TB1> INFO: Expecting 41600 events.
[19:26:53.256] <TB1> INFO: 41600 events read in total (2427ms).
[19:26:53.256] <TB1> INFO: Test took 3257ms.
[19:26:53.700] <TB1> INFO: Expecting 41600 events.
[19:26:56.806] <TB1> INFO: 41600 events read in total (2515ms).
[19:26:56.807] <TB1> INFO: Test took 3340ms.
[19:26:57.025] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:26:57.113] <TB1> INFO: Expecting 2560 events.
[19:26:57.996] <TB1> INFO: 2560 events read in total (291ms).
[19:26:57.996] <TB1> INFO: Test took 972ms.
[19:26:57.998] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:26:58.304] <TB1> INFO: Expecting 2560 events.
[19:26:59.186] <TB1> INFO: 2560 events read in total (291ms).
[19:26:59.187] <TB1> INFO: Test took 1189ms.
[19:26:59.189] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:26:59.495] <TB1> INFO: Expecting 2560 events.
[19:27:00.379] <TB1> INFO: 2560 events read in total (292ms).
[19:27:00.379] <TB1> INFO: Test took 1190ms.
[19:27:00.380] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:00.687] <TB1> INFO: Expecting 2560 events.
[19:27:01.570] <TB1> INFO: 2560 events read in total (291ms).
[19:27:01.570] <TB1> INFO: Test took 1190ms.
[19:27:01.572] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:01.878] <TB1> INFO: Expecting 2560 events.
[19:27:02.762] <TB1> INFO: 2560 events read in total (292ms).
[19:27:02.762] <TB1> INFO: Test took 1190ms.
[19:27:02.764] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:03.071] <TB1> INFO: Expecting 2560 events.
[19:27:03.954] <TB1> INFO: 2560 events read in total (292ms).
[19:27:03.954] <TB1> INFO: Test took 1190ms.
[19:27:03.956] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:04.262] <TB1> INFO: Expecting 2560 events.
[19:27:05.145] <TB1> INFO: 2560 events read in total (291ms).
[19:27:05.145] <TB1> INFO: Test took 1189ms.
[19:27:05.147] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:05.453] <TB1> INFO: Expecting 2560 events.
[19:27:06.337] <TB1> INFO: 2560 events read in total (292ms).
[19:27:06.337] <TB1> INFO: Test took 1191ms.
[19:27:06.339] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:06.645] <TB1> INFO: Expecting 2560 events.
[19:27:07.523] <TB1> INFO: 2560 events read in total (286ms).
[19:27:07.523] <TB1> INFO: Test took 1184ms.
[19:27:07.525] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:07.832] <TB1> INFO: Expecting 2560 events.
[19:27:08.709] <TB1> INFO: 2560 events read in total (286ms).
[19:27:08.709] <TB1> INFO: Test took 1184ms.
[19:27:08.711] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:09.018] <TB1> INFO: Expecting 2560 events.
[19:27:09.896] <TB1> INFO: 2560 events read in total (287ms).
[19:27:09.896] <TB1> INFO: Test took 1185ms.
[19:27:09.898] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:10.204] <TB1> INFO: Expecting 2560 events.
[19:27:11.084] <TB1> INFO: 2560 events read in total (288ms).
[19:27:11.084] <TB1> INFO: Test took 1186ms.
[19:27:11.086] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:11.393] <TB1> INFO: Expecting 2560 events.
[19:27:12.274] <TB1> INFO: 2560 events read in total (290ms).
[19:27:12.274] <TB1> INFO: Test took 1188ms.
[19:27:12.276] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:12.582] <TB1> INFO: Expecting 2560 events.
[19:27:13.460] <TB1> INFO: 2560 events read in total (286ms).
[19:27:13.460] <TB1> INFO: Test took 1184ms.
[19:27:13.462] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:13.769] <TB1> INFO: Expecting 2560 events.
[19:27:14.646] <TB1> INFO: 2560 events read in total (286ms).
[19:27:14.646] <TB1> INFO: Test took 1184ms.
[19:27:14.648] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:14.955] <TB1> INFO: Expecting 2560 events.
[19:27:15.836] <TB1> INFO: 2560 events read in total (289ms).
[19:27:15.836] <TB1> INFO: Test took 1188ms.
[19:27:15.838] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:16.144] <TB1> INFO: Expecting 2560 events.
[19:27:17.021] <TB1> INFO: 2560 events read in total (286ms).
[19:27:17.022] <TB1> INFO: Test took 1184ms.
[19:27:17.024] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:17.330] <TB1> INFO: Expecting 2560 events.
[19:27:18.208] <TB1> INFO: 2560 events read in total (286ms).
[19:27:18.208] <TB1> INFO: Test took 1184ms.
[19:27:18.210] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:18.516] <TB1> INFO: Expecting 2560 events.
[19:27:19.393] <TB1> INFO: 2560 events read in total (285ms).
[19:27:19.393] <TB1> INFO: Test took 1184ms.
[19:27:19.395] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:19.702] <TB1> INFO: Expecting 2560 events.
[19:27:20.579] <TB1> INFO: 2560 events read in total (286ms).
[19:27:20.580] <TB1> INFO: Test took 1185ms.
[19:27:20.582] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:20.888] <TB1> INFO: Expecting 2560 events.
[19:27:21.766] <TB1> INFO: 2560 events read in total (286ms).
[19:27:21.767] <TB1> INFO: Test took 1186ms.
[19:27:21.768] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:22.075] <TB1> INFO: Expecting 2560 events.
[19:27:22.956] <TB1> INFO: 2560 events read in total (289ms).
[19:27:22.956] <TB1> INFO: Test took 1188ms.
[19:27:22.958] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:23.264] <TB1> INFO: Expecting 2560 events.
[19:27:24.142] <TB1> INFO: 2560 events read in total (286ms).
[19:27:24.143] <TB1> INFO: Test took 1185ms.
[19:27:24.145] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:24.451] <TB1> INFO: Expecting 2560 events.
[19:27:25.328] <TB1> INFO: 2560 events read in total (286ms).
[19:27:25.329] <TB1> INFO: Test took 1184ms.
[19:27:25.330] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:25.637] <TB1> INFO: Expecting 2560 events.
[19:27:26.521] <TB1> INFO: 2560 events read in total (292ms).
[19:27:26.522] <TB1> INFO: Test took 1192ms.
[19:27:26.523] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:26.830] <TB1> INFO: Expecting 2560 events.
[19:27:27.712] <TB1> INFO: 2560 events read in total (290ms).
[19:27:27.713] <TB1> INFO: Test took 1190ms.
[19:27:27.714] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:28.021] <TB1> INFO: Expecting 2560 events.
[19:27:28.904] <TB1> INFO: 2560 events read in total (291ms).
[19:27:28.904] <TB1> INFO: Test took 1190ms.
[19:27:28.907] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:29.212] <TB1> INFO: Expecting 2560 events.
[19:27:30.098] <TB1> INFO: 2560 events read in total (294ms).
[19:27:30.099] <TB1> INFO: Test took 1193ms.
[19:27:30.100] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:30.407] <TB1> INFO: Expecting 2560 events.
[19:27:31.292] <TB1> INFO: 2560 events read in total (293ms).
[19:27:31.293] <TB1> INFO: Test took 1193ms.
[19:27:31.296] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:31.601] <TB1> INFO: Expecting 2560 events.
[19:27:32.483] <TB1> INFO: 2560 events read in total (290ms).
[19:27:32.483] <TB1> INFO: Test took 1187ms.
[19:27:32.485] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:32.792] <TB1> INFO: Expecting 2560 events.
[19:27:33.674] <TB1> INFO: 2560 events read in total (291ms).
[19:27:33.674] <TB1> INFO: Test took 1189ms.
[19:27:33.676] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:27:33.983] <TB1> INFO: Expecting 2560 events.
[19:27:34.872] <TB1> INFO: 2560 events read in total (297ms).
[19:27:34.873] <TB1> INFO: Test took 1197ms.
[19:27:35.341] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 621 seconds
[19:27:35.341] <TB1> INFO: PH scale (per ROC): 54 55 40 50 48 50 49 35 44 34 42 45 39 41 42 56
[19:27:35.341] <TB1> INFO: PH offset (per ROC): 126 126 95 123 91 127 126 92 95 102 99 112 99 96 106 114
[19:27:35.346] <TB1> INFO: Decoding statistics:
[19:27:35.346] <TB1> INFO: General information:
[19:27:35.346] <TB1> INFO: 16bit words read: 127892
[19:27:35.346] <TB1> INFO: valid events total: 20480
[19:27:35.346] <TB1> INFO: empty events: 17974
[19:27:35.346] <TB1> INFO: valid events with pixels: 2506
[19:27:35.346] <TB1> INFO: valid pixel hits: 2506
[19:27:35.346] <TB1> INFO: Event errors: 0
[19:27:35.346] <TB1> INFO: start marker: 0
[19:27:35.346] <TB1> INFO: stop marker: 0
[19:27:35.346] <TB1> INFO: overflow: 0
[19:27:35.346] <TB1> INFO: invalid 5bit words: 0
[19:27:35.346] <TB1> INFO: invalid XOR eye diagram: 0
[19:27:35.346] <TB1> INFO: frame (failed synchr.): 0
[19:27:35.346] <TB1> INFO: idle data (no TBM trl): 0
[19:27:35.346] <TB1> INFO: no data (only TBM hdr): 0
[19:27:35.347] <TB1> INFO: TBM errors: 0
[19:27:35.347] <TB1> INFO: flawed TBM headers: 0
[19:27:35.347] <TB1> INFO: flawed TBM trailers: 0
[19:27:35.347] <TB1> INFO: event ID mismatches: 0
[19:27:35.347] <TB1> INFO: ROC errors: 0
[19:27:35.347] <TB1> INFO: missing ROC header(s): 0
[19:27:35.347] <TB1> INFO: misplaced readback start: 0
[19:27:35.347] <TB1> INFO: Pixel decoding errors: 0
[19:27:35.347] <TB1> INFO: pixel data incomplete: 0
[19:27:35.347] <TB1> INFO: pixel address: 0
[19:27:35.347] <TB1> INFO: pulse height fill bit: 0
[19:27:35.347] <TB1> INFO: buffer corruption: 0
[19:27:35.646] <TB1> INFO: ######################################################################
[19:27:35.646] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[19:27:35.646] <TB1> INFO: ######################################################################
[19:27:35.660] <TB1> INFO: scanning low vcal = 10
[19:27:35.923] <TB1> INFO: Expecting 41600 events.
[19:27:39.490] <TB1> INFO: 41600 events read in total (2976ms).
[19:27:39.491] <TB1> INFO: Test took 3831ms.
[19:27:39.492] <TB1> INFO: scanning low vcal = 20
[19:27:39.792] <TB1> INFO: Expecting 41600 events.
[19:27:43.411] <TB1> INFO: 41600 events read in total (3028ms).
[19:27:43.411] <TB1> INFO: Test took 3918ms.
[19:27:43.413] <TB1> INFO: scanning low vcal = 30
[19:27:43.733] <TB1> INFO: Expecting 41600 events.
[19:27:47.370] <TB1> INFO: 41600 events read in total (3045ms).
[19:27:47.371] <TB1> INFO: Test took 3958ms.
[19:27:47.374] <TB1> INFO: scanning low vcal = 40
[19:27:47.653] <TB1> INFO: Expecting 41600 events.
[19:27:51.581] <TB1> INFO: 41600 events read in total (3337ms).
[19:27:51.582] <TB1> INFO: Test took 4208ms.
[19:27:51.585] <TB1> INFO: scanning low vcal = 50
[19:27:51.862] <TB1> INFO: Expecting 41600 events.
[19:27:55.799] <TB1> INFO: 41600 events read in total (3346ms).
[19:27:55.799] <TB1> INFO: Test took 4214ms.
[19:27:55.802] <TB1> INFO: scanning low vcal = 60
[19:27:56.079] <TB1> INFO: Expecting 41600 events.
[19:28:00.068] <TB1> INFO: 41600 events read in total (3398ms).
[19:28:00.069] <TB1> INFO: Test took 4267ms.
[19:28:00.071] <TB1> INFO: scanning low vcal = 70
[19:28:00.348] <TB1> INFO: Expecting 41600 events.
[19:28:04.324] <TB1> INFO: 41600 events read in total (3384ms).
[19:28:04.325] <TB1> INFO: Test took 4253ms.
[19:28:04.327] <TB1> INFO: scanning low vcal = 80
[19:28:04.604] <TB1> INFO: Expecting 41600 events.
[19:28:08.541] <TB1> INFO: 41600 events read in total (3345ms).
[19:28:08.542] <TB1> INFO: Test took 4215ms.
[19:28:08.545] <TB1> INFO: scanning low vcal = 90
[19:28:08.821] <TB1> INFO: Expecting 41600 events.
[19:28:12.772] <TB1> INFO: 41600 events read in total (3359ms).
[19:28:12.773] <TB1> INFO: Test took 4228ms.
[19:28:12.775] <TB1> INFO: scanning low vcal = 100
[19:28:13.053] <TB1> INFO: Expecting 41600 events.
[19:28:17.011] <TB1> INFO: 41600 events read in total (3366ms).
[19:28:17.012] <TB1> INFO: Test took 4236ms.
[19:28:17.015] <TB1> INFO: scanning low vcal = 110
[19:28:17.291] <TB1> INFO: Expecting 41600 events.
[19:28:21.215] <TB1> INFO: 41600 events read in total (3332ms).
[19:28:21.215] <TB1> INFO: Test took 4200ms.
[19:28:21.218] <TB1> INFO: scanning low vcal = 120
[19:28:21.495] <TB1> INFO: Expecting 41600 events.
[19:28:25.425] <TB1> INFO: 41600 events read in total (3339ms).
[19:28:25.425] <TB1> INFO: Test took 4207ms.
[19:28:25.428] <TB1> INFO: scanning low vcal = 130
[19:28:25.705] <TB1> INFO: Expecting 41600 events.
[19:28:29.692] <TB1> INFO: 41600 events read in total (3396ms).
[19:28:29.693] <TB1> INFO: Test took 4265ms.
[19:28:29.695] <TB1> INFO: scanning low vcal = 140
[19:28:29.972] <TB1> INFO: Expecting 41600 events.
[19:28:33.906] <TB1> INFO: 41600 events read in total (3342ms).
[19:28:33.906] <TB1> INFO: Test took 4210ms.
[19:28:33.909] <TB1> INFO: scanning low vcal = 150
[19:28:34.186] <TB1> INFO: Expecting 41600 events.
[19:28:38.111] <TB1> INFO: 41600 events read in total (3334ms).
[19:28:38.111] <TB1> INFO: Test took 4202ms.
[19:28:38.114] <TB1> INFO: scanning low vcal = 160
[19:28:38.390] <TB1> INFO: Expecting 41600 events.
[19:28:42.331] <TB1> INFO: 41600 events read in total (3349ms).
[19:28:42.332] <TB1> INFO: Test took 4218ms.
[19:28:42.334] <TB1> INFO: scanning low vcal = 170
[19:28:42.611] <TB1> INFO: Expecting 41600 events.
[19:28:46.575] <TB1> INFO: 41600 events read in total (3372ms).
[19:28:46.576] <TB1> INFO: Test took 4241ms.
[19:28:46.580] <TB1> INFO: scanning low vcal = 180
[19:28:46.855] <TB1> INFO: Expecting 41600 events.
[19:28:50.840] <TB1> INFO: 41600 events read in total (3393ms).
[19:28:50.841] <TB1> INFO: Test took 4261ms.
[19:28:50.844] <TB1> INFO: scanning low vcal = 190
[19:28:51.120] <TB1> INFO: Expecting 41600 events.
[19:28:55.059] <TB1> INFO: 41600 events read in total (3347ms).
[19:28:55.060] <TB1> INFO: Test took 4216ms.
[19:28:55.063] <TB1> INFO: scanning low vcal = 200
[19:28:55.339] <TB1> INFO: Expecting 41600 events.
[19:28:59.268] <TB1> INFO: 41600 events read in total (3337ms).
[19:28:59.268] <TB1> INFO: Test took 4205ms.
[19:28:59.270] <TB1> INFO: scanning low vcal = 210
[19:28:59.547] <TB1> INFO: Expecting 41600 events.
[19:29:03.477] <TB1> INFO: 41600 events read in total (3338ms).
[19:29:03.478] <TB1> INFO: Test took 4207ms.
[19:29:03.481] <TB1> INFO: scanning low vcal = 220
[19:29:03.759] <TB1> INFO: Expecting 41600 events.
[19:29:07.703] <TB1> INFO: 41600 events read in total (3352ms).
[19:29:07.703] <TB1> INFO: Test took 4222ms.
[19:29:07.706] <TB1> INFO: scanning low vcal = 230
[19:29:07.982] <TB1> INFO: Expecting 41600 events.
[19:29:11.927] <TB1> INFO: 41600 events read in total (3353ms).
[19:29:11.928] <TB1> INFO: Test took 4222ms.
[19:29:11.930] <TB1> INFO: scanning low vcal = 240
[19:29:12.207] <TB1> INFO: Expecting 41600 events.
[19:29:16.137] <TB1> INFO: 41600 events read in total (3339ms).
[19:29:16.137] <TB1> INFO: Test took 4207ms.
[19:29:16.140] <TB1> INFO: scanning low vcal = 250
[19:29:16.416] <TB1> INFO: Expecting 41600 events.
[19:29:20.386] <TB1> INFO: 41600 events read in total (3378ms).
[19:29:20.387] <TB1> INFO: Test took 4247ms.
[19:29:20.390] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[19:29:20.666] <TB1> INFO: Expecting 41600 events.
[19:29:24.618] <TB1> INFO: 41600 events read in total (3360ms).
[19:29:24.619] <TB1> INFO: Test took 4228ms.
[19:29:24.621] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[19:29:24.898] <TB1> INFO: Expecting 41600 events.
[19:29:28.899] <TB1> INFO: 41600 events read in total (3410ms).
[19:29:28.900] <TB1> INFO: Test took 4279ms.
[19:29:28.903] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[19:29:29.180] <TB1> INFO: Expecting 41600 events.
[19:29:33.109] <TB1> INFO: 41600 events read in total (3337ms).
[19:29:33.109] <TB1> INFO: Test took 4206ms.
[19:29:33.112] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[19:29:33.389] <TB1> INFO: Expecting 41600 events.
[19:29:37.360] <TB1> INFO: 41600 events read in total (3380ms).
[19:29:37.361] <TB1> INFO: Test took 4249ms.
[19:29:37.364] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[19:29:37.641] <TB1> INFO: Expecting 41600 events.
[19:29:41.585] <TB1> INFO: 41600 events read in total (3353ms).
[19:29:41.586] <TB1> INFO: Test took 4222ms.
[19:29:42.027] <TB1> INFO: PixTestGainPedestal::measure() done
[19:30:15.337] <TB1> INFO: PixTestGainPedestal::fit() done
[19:30:15.337] <TB1> INFO: non-linearity mean: 0.980 0.980 0.934 0.979 0.972 0.977 0.977 0.926 0.917 0.921 0.923 0.948 0.928 0.921 0.921 0.981
[19:30:15.337] <TB1> INFO: non-linearity RMS: 0.003 0.004 0.106 0.005 0.008 0.005 0.005 0.128 0.128 0.178 0.084 0.058 0.112 0.097 0.090 0.004
[19:30:15.337] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[19:30:15.352] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[19:30:15.366] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[19:30:15.380] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[19:30:15.394] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[19:30:15.409] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[19:30:15.423] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[19:30:15.437] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[19:30:15.451] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[19:30:15.465] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[19:30:15.479] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[19:30:15.493] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[19:30:15.507] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[19:30:15.521] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[19:30:15.535] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[19:30:15.549] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[19:30:15.563] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 159 seconds
[19:30:15.563] <TB1> INFO: Decoding statistics:
[19:30:15.563] <TB1> INFO: General information:
[19:30:15.563] <TB1> INFO: 16bit words read: 3289070
[19:30:15.563] <TB1> INFO: valid events total: 332800
[19:30:15.563] <TB1> INFO: empty events: 444
[19:30:15.563] <TB1> INFO: valid events with pixels: 332356
[19:30:15.563] <TB1> INFO: valid pixel hits: 646135
[19:30:15.563] <TB1> INFO: Event errors: 0
[19:30:15.563] <TB1> INFO: start marker: 0
[19:30:15.563] <TB1> INFO: stop marker: 0
[19:30:15.563] <TB1> INFO: overflow: 0
[19:30:15.563] <TB1> INFO: invalid 5bit words: 0
[19:30:15.563] <TB1> INFO: invalid XOR eye diagram: 0
[19:30:15.563] <TB1> INFO: frame (failed synchr.): 0
[19:30:15.563] <TB1> INFO: idle data (no TBM trl): 0
[19:30:15.563] <TB1> INFO: no data (only TBM hdr): 0
[19:30:15.563] <TB1> INFO: TBM errors: 0
[19:30:15.563] <TB1> INFO: flawed TBM headers: 0
[19:30:15.563] <TB1> INFO: flawed TBM trailers: 0
[19:30:15.563] <TB1> INFO: event ID mismatches: 0
[19:30:15.563] <TB1> INFO: ROC errors: 0
[19:30:15.563] <TB1> INFO: missing ROC header(s): 0
[19:30:15.563] <TB1> INFO: misplaced readback start: 0
[19:30:15.563] <TB1> INFO: Pixel decoding errors: 0
[19:30:15.563] <TB1> INFO: pixel data incomplete: 0
[19:30:15.563] <TB1> INFO: pixel address: 0
[19:30:15.563] <TB1> INFO: pulse height fill bit: 0
[19:30:15.563] <TB1> INFO: buffer corruption: 0
[19:30:15.577] <TB1> INFO: Decoding statistics:
[19:30:15.577] <TB1> INFO: General information:
[19:30:15.577] <TB1> INFO: 16bit words read: 3418498
[19:30:15.577] <TB1> INFO: valid events total: 353536
[19:30:15.578] <TB1> INFO: empty events: 18674
[19:30:15.578] <TB1> INFO: valid events with pixels: 334862
[19:30:15.578] <TB1> INFO: valid pixel hits: 648641
[19:30:15.578] <TB1> INFO: Event errors: 0
[19:30:15.578] <TB1> INFO: start marker: 0
[19:30:15.578] <TB1> INFO: stop marker: 0
[19:30:15.578] <TB1> INFO: overflow: 0
[19:30:15.578] <TB1> INFO: invalid 5bit words: 0
[19:30:15.578] <TB1> INFO: invalid XOR eye diagram: 0
[19:30:15.578] <TB1> INFO: frame (failed synchr.): 0
[19:30:15.578] <TB1> INFO: idle data (no TBM trl): 0
[19:30:15.578] <TB1> INFO: no data (only TBM hdr): 0
[19:30:15.578] <TB1> INFO: TBM errors: 0
[19:30:15.578] <TB1> INFO: flawed TBM headers: 0
[19:30:15.578] <TB1> INFO: flawed TBM trailers: 0
[19:30:15.578] <TB1> INFO: event ID mismatches: 0
[19:30:15.578] <TB1> INFO: ROC errors: 0
[19:30:15.578] <TB1> INFO: missing ROC header(s): 0
[19:30:15.578] <TB1> INFO: misplaced readback start: 0
[19:30:15.578] <TB1> INFO: Pixel decoding errors: 0
[19:30:15.578] <TB1> INFO: pixel data incomplete: 0
[19:30:15.578] <TB1> INFO: pixel address: 0
[19:30:15.578] <TB1> INFO: pulse height fill bit: 0
[19:30:15.578] <TB1> INFO: buffer corruption: 0
[19:30:15.578] <TB1> INFO: enter test to run
[19:30:15.578] <TB1> INFO: test: Trim80 no parameter change
[19:30:15.578] <TB1> INFO: running: trim80
[19:30:15.593] <TB1> INFO: ######################################################################
[19:30:15.593] <TB1> INFO: PixTestTrim80::doTest()
[19:30:15.593] <TB1> INFO: ######################################################################
[19:30:15.594] <TB1> INFO: ----------------------------------------------------------------------
[19:30:15.594] <TB1> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[19:30:15.594] <TB1> INFO: ----------------------------------------------------------------------
[19:30:15.652] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[19:30:15.652] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[19:30:15.663] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:30:15.663] <TB1> INFO: run 1 of 1
[19:30:15.920] <TB1> INFO: Expecting 5025280 events.
[19:30:44.959] <TB1> INFO: 683320 events read in total (28448ms).
[19:31:12.664] <TB1> INFO: 1361264 events read in total (56153ms).
[19:31:39.846] <TB1> INFO: 2038640 events read in total (83335ms).
[19:32:07.021] <TB1> INFO: 2714192 events read in total (110510ms).
[19:32:34.037] <TB1> INFO: 3387256 events read in total (137526ms).
[19:33:01.267] <TB1> INFO: 4058728 events read in total (164756ms).
[19:33:28.153] <TB1> INFO: 4728024 events read in total (191642ms).
[19:33:40.258] <TB1> INFO: 5025280 events read in total (203747ms).
[19:33:40.341] <TB1> INFO: Test took 204678ms.
[19:34:03.474] <TB1> INFO: ROC 0 VthrComp = 75
[19:34:03.474] <TB1> INFO: ROC 1 VthrComp = 87
[19:34:03.475] <TB1> INFO: ROC 2 VthrComp = 74
[19:34:03.475] <TB1> INFO: ROC 3 VthrComp = 75
[19:34:03.475] <TB1> INFO: ROC 4 VthrComp = 75
[19:34:03.475] <TB1> INFO: ROC 5 VthrComp = 78
[19:34:03.475] <TB1> INFO: ROC 6 VthrComp = 75
[19:34:03.475] <TB1> INFO: ROC 7 VthrComp = 77
[19:34:03.475] <TB1> INFO: ROC 8 VthrComp = 75
[19:34:03.475] <TB1> INFO: ROC 9 VthrComp = 77
[19:34:03.475] <TB1> INFO: ROC 10 VthrComp = 85
[19:34:03.476] <TB1> INFO: ROC 11 VthrComp = 65
[19:34:03.476] <TB1> INFO: ROC 12 VthrComp = 85
[19:34:03.477] <TB1> INFO: ROC 13 VthrComp = 84
[19:34:03.477] <TB1> INFO: ROC 14 VthrComp = 66
[19:34:03.477] <TB1> INFO: ROC 15 VthrComp = 79
[19:34:03.711] <TB1> INFO: Expecting 41600 events.
[19:34:07.269] <TB1> INFO: 41600 events read in total (2967ms).
[19:34:07.270] <TB1> INFO: Test took 3791ms.
[19:34:07.279] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[19:34:07.279] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[19:34:07.287] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:34:07.287] <TB1> INFO: run 1 of 1
[19:34:07.565] <TB1> INFO: Expecting 5025280 events.
[19:34:35.496] <TB1> INFO: 682032 events read in total (27339ms).
[19:35:02.214] <TB1> INFO: 1360880 events read in total (54057ms).
[19:35:29.088] <TB1> INFO: 2040064 events read in total (80931ms).
[19:35:55.847] <TB1> INFO: 2716760 events read in total (107690ms).
[19:36:22.956] <TB1> INFO: 3390496 events read in total (134799ms).
[19:36:49.531] <TB1> INFO: 4061512 events read in total (161374ms).
[19:37:16.346] <TB1> INFO: 4732640 events read in total (188189ms).
[19:37:28.131] <TB1> INFO: 5025280 events read in total (199974ms).
[19:37:28.196] <TB1> INFO: Test took 200908ms.
[19:37:50.821] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 108.483 for pixel 17/72 mean/min/max = 93.4967/78.4166/108.577
[19:37:50.822] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 106.269 for pixel 0/64 mean/min/max = 90.6842/75.0478/106.321
[19:37:50.822] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 110.571 for pixel 0/40 mean/min/max = 94.3745/78.1611/110.588
[19:37:50.822] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 107.152 for pixel 51/68 mean/min/max = 92.2081/77.2413/107.175
[19:37:50.823] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 109.998 for pixel 0/48 mean/min/max = 94.126/78.0973/110.155
[19:37:50.823] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 109.525 for pixel 20/77 mean/min/max = 93.6093/77.6836/109.535
[19:37:50.823] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 107.966 for pixel 0/32 mean/min/max = 92.6486/77.3123/107.985
[19:37:50.824] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 112.048 for pixel 0/77 mean/min/max = 95.2924/78.471/112.114
[19:37:50.824] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 115.248 for pixel 0/42 mean/min/max = 95.5176/75.4304/115.605
[19:37:50.824] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 115.389 for pixel 0/6 mean/min/max = 95.7705/76.1471/115.394
[19:37:50.825] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 106.951 for pixel 0/20 mean/min/max = 90.5773/73.9577/107.197
[19:37:50.825] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 104.824 for pixel 0/4 mean/min/max = 90.2569/75.5295/104.984
[19:37:50.825] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 105.049 for pixel 51/39 mean/min/max = 89.9316/74.6343/105.229
[19:37:50.826] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 106.268 for pixel 0/10 mean/min/max = 90.5909/74.9055/106.276
[19:37:50.826] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 104.65 for pixel 0/33 mean/min/max = 89.533/74.2198/104.846
[19:37:50.826] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 108.713 for pixel 18/47 mean/min/max = 93.0689/77.4095/108.728
[19:37:50.827] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:37:50.915] <TB1> INFO: Expecting 411648 events.
[19:38:00.221] <TB1> INFO: 411648 events read in total (8714ms).
[19:38:00.229] <TB1> INFO: Expecting 411648 events.
[19:38:09.429] <TB1> INFO: 411648 events read in total (8797ms).
[19:38:09.439] <TB1> INFO: Expecting 411648 events.
[19:38:18.708] <TB1> INFO: 411648 events read in total (8866ms).
[19:38:18.724] <TB1> INFO: Expecting 411648 events.
[19:38:28.221] <TB1> INFO: 411648 events read in total (9094ms).
[19:38:28.240] <TB1> INFO: Expecting 411648 events.
[19:38:37.531] <TB1> INFO: 411648 events read in total (8888ms).
[19:38:37.549] <TB1> INFO: Expecting 411648 events.
[19:38:46.542] <TB1> INFO: 411648 events read in total (8590ms).
[19:38:46.563] <TB1> INFO: Expecting 411648 events.
[19:38:55.618] <TB1> INFO: 411648 events read in total (8652ms).
[19:38:55.647] <TB1> INFO: Expecting 411648 events.
[19:39:04.716] <TB1> INFO: 411648 events read in total (8666ms).
[19:39:04.744] <TB1> INFO: Expecting 411648 events.
[19:39:13.763] <TB1> INFO: 411648 events read in total (8616ms).
[19:39:13.792] <TB1> INFO: Expecting 411648 events.
[19:39:22.831] <TB1> INFO: 411648 events read in total (8636ms).
[19:39:22.868] <TB1> INFO: Expecting 411648 events.
[19:39:31.892] <TB1> INFO: 411648 events read in total (8621ms).
[19:39:31.926] <TB1> INFO: Expecting 411648 events.
[19:39:40.972] <TB1> INFO: 411648 events read in total (8640ms).
[19:39:41.021] <TB1> INFO: Expecting 411648 events.
[19:39:49.992] <TB1> INFO: 411648 events read in total (8568ms).
[19:39:50.044] <TB1> INFO: Expecting 411648 events.
[19:39:59.142] <TB1> INFO: 411648 events read in total (8695ms).
[19:39:59.184] <TB1> INFO: Expecting 411648 events.
[19:40:08.288] <TB1> INFO: 411648 events read in total (8701ms).
[19:40:08.337] <TB1> INFO: Expecting 411648 events.
[19:40:17.311] <TB1> INFO: 411648 events read in total (8571ms).
[19:40:17.357] <TB1> INFO: Test took 146531ms.
[19:40:18.992] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[19:40:18.003] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:40:18.003] <TB1> INFO: run 1 of 1
[19:40:19.234] <TB1> INFO: Expecting 5025280 events.
[19:40:46.130] <TB1> INFO: 663936 events read in total (26305ms).
[19:41:12.563] <TB1> INFO: 1325640 events read in total (52738ms).
[19:41:39.094] <TB1> INFO: 1987856 events read in total (79269ms).
[19:42:05.403] <TB1> INFO: 2648544 events read in total (105578ms).
[19:42:31.807] <TB1> INFO: 3307056 events read in total (131982ms).
[19:42:58.358] <TB1> INFO: 3963040 events read in total (158533ms).
[19:43:24.469] <TB1> INFO: 4614624 events read in total (184644ms).
[19:43:41.012] <TB1> INFO: 5025280 events read in total (201187ms).
[19:43:41.119] <TB1> INFO: Test took 202117ms.
[19:44:06.397] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 54.468638 .. 99.545618
[19:44:06.631] <TB1> INFO: Expecting 208000 events.
[19:44:16.595] <TB1> INFO: 208000 events read in total (9372ms).
[19:44:16.596] <TB1> INFO: Test took 10198ms.
[19:44:16.641] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 44 .. 109 (-1/-1) hits flags = 528 (plus default)
[19:44:16.651] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:44:16.651] <TB1> INFO: run 1 of 1
[19:44:16.929] <TB1> INFO: Expecting 2196480 events.
[19:44:45.794] <TB1> INFO: 688640 events read in total (28273ms).
[19:45:12.841] <TB1> INFO: 1374056 events read in total (55321ms).
[19:45:39.826] <TB1> INFO: 2054664 events read in total (82305ms).
[19:45:45.833] <TB1> INFO: 2196480 events read in total (88312ms).
[19:45:45.864] <TB1> INFO: Test took 89213ms.
[19:46:03.165] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 63.917298 .. 91.124458
[19:46:03.415] <TB1> INFO: Expecting 208000 events.
[19:46:13.231] <TB1> INFO: 208000 events read in total (9224ms).
[19:46:13.231] <TB1> INFO: Test took 10064ms.
[19:46:13.293] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 53 .. 101 (-1/-1) hits flags = 528 (plus default)
[19:46:13.305] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:46:13.305] <TB1> INFO: run 1 of 1
[19:46:13.583] <TB1> INFO: Expecting 1630720 events.
[19:46:42.152] <TB1> INFO: 689904 events read in total (27978ms).
[19:47:09.738] <TB1> INFO: 1379184 events read in total (55564ms).
[19:47:20.024] <TB1> INFO: 1630720 events read in total (65850ms).
[19:47:20.056] <TB1> INFO: Test took 66752ms.
[19:47:35.777] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 67.895591 .. 85.614475
[19:47:36.013] <TB1> INFO: Expecting 208000 events.
[19:47:45.689] <TB1> INFO: 208000 events read in total (9084ms).
[19:47:45.690] <TB1> INFO: Test took 9911ms.
[19:47:45.749] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 57 .. 95 (-1/-1) hits flags = 528 (plus default)
[19:47:45.759] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:47:45.759] <TB1> INFO: run 1 of 1
[19:47:46.037] <TB1> INFO: Expecting 1297920 events.
[19:48:15.894] <TB1> INFO: 706000 events read in total (29266ms).
[19:48:39.425] <TB1> INFO: 1297920 events read in total (52797ms).
[19:48:39.447] <TB1> INFO: Test took 53689ms.
[19:48:54.776] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 69.967989 .. 85.614475
[19:48:55.026] <TB1> INFO: Expecting 208000 events.
[19:49:04.606] <TB1> INFO: 208000 events read in total (8989ms).
[19:49:04.607] <TB1> INFO: Test took 9830ms.
[19:49:04.652] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 59 .. 95 (-1/-1) hits flags = 528 (plus default)
[19:49:04.663] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:49:04.663] <TB1> INFO: run 1 of 1
[19:49:04.940] <TB1> INFO: Expecting 1231360 events.
[19:49:33.730] <TB1> INFO: 699960 events read in total (28198ms).
[19:49:55.032] <TB1> INFO: 1231360 events read in total (49500ms).
[19:49:55.063] <TB1> INFO: Test took 50401ms.
[19:50:12.204] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[19:50:12.204] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[19:50:12.214] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:50:12.214] <TB1> INFO: run 1 of 1
[19:50:12.445] <TB1> INFO: Expecting 1364480 events.
[19:50:40.784] <TB1> INFO: 668408 events read in total (27747ms).
[19:51:08.618] <TB1> INFO: 1336528 events read in total (55581ms).
[19:51:10.166] <TB1> INFO: 1364480 events read in total (57129ms).
[19:51:10.190] <TB1> INFO: Test took 57976ms.
[19:51:27.878] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C0.dat
[19:51:27.878] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C1.dat
[19:51:27.878] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C2.dat
[19:51:27.878] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C3.dat
[19:51:27.878] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C4.dat
[19:51:27.878] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C5.dat
[19:51:27.878] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C6.dat
[19:51:27.878] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C7.dat
[19:51:27.878] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C8.dat
[19:51:27.878] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C9.dat
[19:51:27.879] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C10.dat
[19:51:27.879] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C11.dat
[19:51:27.879] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C12.dat
[19:51:27.879] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C13.dat
[19:51:27.879] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C14.dat
[19:51:27.879] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//dacParameters80_C15.dat
[19:51:27.879] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C0.dat
[19:51:27.885] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C1.dat
[19:51:27.890] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C2.dat
[19:51:27.896] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C3.dat
[19:51:27.902] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C4.dat
[19:51:27.910] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C5.dat
[19:51:27.918] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C6.dat
[19:51:27.925] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C7.dat
[19:51:27.932] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C8.dat
[19:51:27.939] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C9.dat
[19:51:27.947] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C10.dat
[19:51:27.954] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C11.dat
[19:51:27.961] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C12.dat
[19:51:27.969] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C13.dat
[19:51:27.976] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C14.dat
[19:51:27.984] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1113_FullQualification_2016-11-02_15h29m_1478096993//003_FulltestTrim80_p17//trimParameters80_C15.dat
[19:51:27.992] <TB1> INFO: PixTestTrim80::trimTest() done
[19:51:27.992] <TB1> INFO: vtrim: 96 104 114 113 102 132 101 103 124 129 101 82 101 112 90 103
[19:51:27.992] <TB1> INFO: vthrcomp: 75 87 74 75 75 78 75 77 75 77 85 65 85 84 66 79
[19:51:27.992] <TB1> INFO: vcal mean: 79.96 79.99 79.97 79.96 79.91 79.94 80.00 79.93 79.95 80.01 79.96 79.97 79.95 79.97 79.96 79.97
[19:51:27.992] <TB1> INFO: vcal RMS: 0.68 0.79 0.74 0.70 2.26 0.78 0.70 0.74 0.81 0.85 0.75 0.71 0.80 0.75 0.74 0.73
[19:51:27.992] <TB1> INFO: bits mean: 9.25 9.87 9.25 9.95 8.81 10.39 9.63 9.50 9.77 9.65 9.94 10.03 10.82 10.68 10.46 9.86
[19:51:27.992] <TB1> INFO: bits RMS: 2.21 2.51 2.27 2.13 2.39 1.86 2.26 2.09 2.27 2.27 2.63 2.36 2.14 2.12 2.37 2.11
[19:51:27.998] <TB1> INFO: ----------------------------------------------------------------------
[19:51:27.998] <TB1> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[19:51:27.998] <TB1> INFO: ----------------------------------------------------------------------
[19:51:27.001] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[19:51:28.011] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:51:28.011] <TB1> INFO: run 1 of 1
[19:51:28.246] <TB1> INFO: Expecting 4160000 events.
[19:52:00.314] <TB1> INFO: 766785 events read in total (31476ms).
[19:52:32.602] <TB1> INFO: 1527185 events read in total (63764ms).
[19:53:03.980] <TB1> INFO: 2282470 events read in total (95142ms).
[19:53:35.595] <TB1> INFO: 3033180 events read in total (126757ms).
[19:54:07.104] <TB1> INFO: 3777575 events read in total (158266ms).
[19:54:23.079] <TB1> INFO: 4160000 events read in total (174241ms).
[19:54:23.138] <TB1> INFO: Test took 175126ms.
[19:54:49.883] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[19:54:49.894] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:54:49.894] <TB1> INFO: run 1 of 1
[19:54:50.169] <TB1> INFO: Expecting 4326400 events.
[19:55:21.691] <TB1> INFO: 729240 events read in total (30931ms).
[19:55:53.304] <TB1> INFO: 1452600 events read in total (62544ms).
[19:56:24.095] <TB1> INFO: 2174315 events read in total (93335ms).
[19:56:54.964] <TB1> INFO: 2890360 events read in total (124204ms).
[19:57:25.383] <TB1> INFO: 3603550 events read in total (154623ms).
[19:57:55.901] <TB1> INFO: 4316450 events read in total (185141ms).
[19:57:56.759] <TB1> INFO: 4326400 events read in total (185999ms).
[19:57:56.885] <TB1> INFO: Test took 186991ms.
[19:58:24.278] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 202 (-1/-1) hits flags = 528 (plus default)
[19:58:24.290] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:58:24.290] <TB1> INFO: run 1 of 1
[19:58:24.563] <TB1> INFO: Expecting 4222400 events.
[19:58:56.199] <TB1> INFO: 736295 events read in total (31045ms).
[19:59:27.921] <TB1> INFO: 1466625 events read in total (62767ms).
[19:59:59.059] <TB1> INFO: 2194445 events read in total (93905ms).
[20:00:29.927] <TB1> INFO: 2917010 events read in total (124773ms).
[20:01:00.784] <TB1> INFO: 3635870 events read in total (155630ms).
[20:01:25.885] <TB1> INFO: 4222400 events read in total (180731ms).
[20:01:26.004] <TB1> INFO: Test took 181714ms.
[20:01:53.473] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[20:01:53.484] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[20:01:53.484] <TB1> INFO: run 1 of 1
[20:01:53.735] <TB1> INFO: Expecting 4243200 events.
[20:02:25.257] <TB1> INFO: 735125 events read in total (30931ms).
[20:02:56.351] <TB1> INFO: 1463980 events read in total (62025ms).
[20:03:27.313] <TB1> INFO: 2190575 events read in total (92987ms).
[20:03:58.023] <TB1> INFO: 2911890 events read in total (123697ms).
[20:04:28.763] <TB1> INFO: 3629960 events read in total (154437ms).
[20:04:55.222] <TB1> INFO: 4243200 events read in total (180896ms).
[20:04:55.338] <TB1> INFO: Test took 181854ms.
[20:05:20.937] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[20:05:20.947] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[20:05:20.947] <TB1> INFO: run 1 of 1
[20:05:21.211] <TB1> INFO: Expecting 4243200 events.
[20:05:53.197] <TB1> INFO: 735250 events read in total (31395ms).
[20:06:24.095] <TB1> INFO: 1464495 events read in total (62293ms).
[20:06:55.088] <TB1> INFO: 2191080 events read in total (93286ms).
[20:07:26.135] <TB1> INFO: 2912710 events read in total (124333ms).
[20:07:56.935] <TB1> INFO: 3630805 events read in total (155133ms).
[20:08:23.245] <TB1> INFO: 4243200 events read in total (181443ms).
[20:08:23.343] <TB1> INFO: Test took 182397ms.
[20:08:50.236] <TB1> INFO: PixTestTrim80::trimBitTest() done
[20:08:50.238] <TB1> INFO: PixTestTrim80::doTest() done, duration: 2314 seconds
[20:08:50.990] <TB1> INFO: enter test to run
[20:08:50.990] <TB1> INFO: test: exit no parameter change
[20:08:51.085] <TB1> QUIET: Connection to board 153 closed.
[20:08:51.086] <TB1> INFO: pXar: this is the end, my friend