[16:10:32.479] <TB2> INFO: *** Welcome to pxar ***
[16:10:32.479] <TB2> INFO: *** Today: 2016/11/02
[16:10:32.486] <TB2> INFO: *** Version: c8ba-dirty
[16:10:32.487] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C15.dat
[16:10:32.487] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//tbmParameters_C1b.dat
[16:10:32.487] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//defaultMaskFile.dat
[16:10:32.487] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters_C15.dat
[16:10:32.578] <TB2> INFO: clk: 4
[16:10:32.578] <TB2> INFO: ctr: 4
[16:10:32.578] <TB2> INFO: sda: 19
[16:10:32.578] <TB2> INFO: tin: 9
[16:10:32.578] <TB2> INFO: level: 15
[16:10:32.578] <TB2> INFO: triggerdelay: 0
[16:10:32.578] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[16:10:32.578] <TB2> INFO: Log level: INFO
[16:10:32.586] <TB2> INFO: Found DTB DTB_WWXUD2
[16:10:32.593] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[16:10:32.595] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[16:10:32.597] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[16:10:34.090] <TB2> INFO: DUT info:
[16:10:34.090] <TB2> INFO: The DUT currently contains the following objects:
[16:10:34.090] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[16:10:34.090] <TB2> INFO: TBM Core alpha (0): 7 registers set
[16:10:34.090] <TB2> INFO: TBM Core beta (1): 7 registers set
[16:10:34.090] <TB2> INFO: TBM Core alpha (2): 7 registers set
[16:10:34.090] <TB2> INFO: TBM Core beta (3): 7 registers set
[16:10:34.090] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[16:10:34.090] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.090] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.090] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.090] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.090] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.090] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.090] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.090] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.090] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.090] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.090] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.090] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.090] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.090] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.090] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.091] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[16:10:34.491] <TB2> INFO: enter 'restricted' command line mode
[16:10:34.491] <TB2> INFO: enter test to run
[16:10:34.491] <TB2> INFO: test: pretest no parameter change
[16:10:34.491] <TB2> INFO: running: pretest
[16:10:34.497] <TB2> INFO: ######################################################################
[16:10:34.497] <TB2> INFO: PixTestPretest::doTest()
[16:10:34.497] <TB2> INFO: ######################################################################
[16:10:34.499] <TB2> INFO: ----------------------------------------------------------------------
[16:10:34.499] <TB2> INFO: PixTestPretest::programROC()
[16:10:34.499] <TB2> INFO: ----------------------------------------------------------------------
[16:10:52.513] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[16:10:52.513] <TB2> INFO: IA differences per ROC: 16.9 19.3 19.3 16.9 16.9 19.3 16.9 18.5 19.3 19.3 19.3 20.1 19.3 19.3 19.3 20.1
[16:10:52.585] <TB2> INFO: ----------------------------------------------------------------------
[16:10:52.585] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[16:10:52.585] <TB2> INFO: ----------------------------------------------------------------------
[16:11:13.887] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 390.7 mA = 24.4187 mA/ROC
[16:11:13.887] <TB2> INFO: i(loss) [mA/ROC]: 20.9 20.1 20.1 20.9 19.3 19.3 20.1 20.1 20.1 20.1 20.1 20.1 20.1 20.1 20.1 20.1
[16:11:13.916] <TB2> INFO: ----------------------------------------------------------------------
[16:11:13.916] <TB2> INFO: PixTestPretest::findTiming()
[16:11:13.916] <TB2> INFO: ----------------------------------------------------------------------
[16:11:13.916] <TB2> INFO: PixTestCmd::init()

[16:11:46.006] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 6, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[16:11:46.006] <TB2> INFO: (success/tries = 100/100), width = 3
[16:11:47.515] <TB2> INFO: ----------------------------------------------------------------------
[16:11:47.515] <TB2> INFO: PixTestPretest::findWorkingPixel()
[16:11:47.515] <TB2> INFO: ----------------------------------------------------------------------
[16:11:47.607] <TB2> INFO: Expecting 231680 events.
[16:11:57.603] <TB2> INFO: 231680 events read in total (9404ms).
[16:11:57.611] <TB2> INFO: Test took 10093ms.
[16:11:57.861] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[16:11:57.897] <TB2> INFO: ----------------------------------------------------------------------
[16:11:57.897] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[16:11:57.897] <TB2> INFO: ----------------------------------------------------------------------
[16:11:57.992] <TB2> INFO: Expecting 231680 events.
[16:12:07.977] <TB2> INFO: 231680 events read in total (9394ms).
[16:12:07.988] <TB2> INFO: Test took 10086ms.
[16:12:08.244] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[16:12:08.244] <TB2> INFO: CalDel: 93 105 93 93 92 106 103 98 105 93 90 109 112 101 103 92
[16:12:08.244] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[16:12:08.247] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C0.dat
[16:12:08.247] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C1.dat
[16:12:08.247] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C2.dat
[16:12:08.247] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C3.dat
[16:12:08.247] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C4.dat
[16:12:08.247] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C5.dat
[16:12:08.248] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C6.dat
[16:12:08.248] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C7.dat
[16:12:08.248] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C8.dat
[16:12:08.248] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C9.dat
[16:12:08.248] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C10.dat
[16:12:08.248] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C11.dat
[16:12:08.248] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C12.dat
[16:12:08.248] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C13.dat
[16:12:08.248] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C14.dat
[16:12:08.248] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters_C15.dat
[16:12:08.248] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//tbmParameters_C0a.dat
[16:12:08.249] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//tbmParameters_C0b.dat
[16:12:08.249] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//tbmParameters_C1a.dat
[16:12:08.249] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//tbmParameters_C1b.dat
[16:12:08.249] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[16:12:08.301] <TB2> INFO: enter test to run
[16:12:08.301] <TB2> INFO: test: FullTest no parameter change
[16:12:08.301] <TB2> INFO: running: fulltest
[16:12:08.301] <TB2> INFO: ######################################################################
[16:12:08.301] <TB2> INFO: PixTestFullTest::doTest()
[16:12:08.301] <TB2> INFO: ######################################################################
[16:12:08.302] <TB2> INFO: ######################################################################
[16:12:08.302] <TB2> INFO: PixTestAlive::doTest()
[16:12:08.302] <TB2> INFO: ######################################################################
[16:12:08.304] <TB2> INFO: ----------------------------------------------------------------------
[16:12:08.304] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:12:08.304] <TB2> INFO: ----------------------------------------------------------------------
[16:12:08.548] <TB2> INFO: Expecting 41600 events.
[16:12:12.049] <TB2> INFO: 41600 events read in total (2906ms).
[16:12:12.050] <TB2> INFO: Test took 3744ms.
[16:12:12.279] <TB2> INFO: PixTestAlive::aliveTest() done
[16:12:12.279] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[16:12:12.280] <TB2> INFO: ----------------------------------------------------------------------
[16:12:12.280] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:12:12.280] <TB2> INFO: ----------------------------------------------------------------------
[16:12:12.563] <TB2> INFO: Expecting 41600 events.
[16:12:15.518] <TB2> INFO: 41600 events read in total (2363ms).
[16:12:15.519] <TB2> INFO: Test took 3237ms.
[16:12:15.519] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[16:12:15.765] <TB2> INFO: PixTestAlive::maskTest() done
[16:12:15.765] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[16:12:15.767] <TB2> INFO: ----------------------------------------------------------------------
[16:12:15.767] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:12:15.767] <TB2> INFO: ----------------------------------------------------------------------
[16:12:16.051] <TB2> INFO: Expecting 41600 events.
[16:12:19.586] <TB2> INFO: 41600 events read in total (2943ms).
[16:12:19.587] <TB2> INFO: Test took 3818ms.
[16:12:19.823] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[16:12:19.823] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[16:12:19.824] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[16:12:19.824] <TB2> INFO: Decoding statistics:
[16:12:19.824] <TB2> INFO: General information:
[16:12:19.824] <TB2> INFO: 16bit words read: 0
[16:12:19.824] <TB2> INFO: valid events total: 0
[16:12:19.824] <TB2> INFO: empty events: 0
[16:12:19.824] <TB2> INFO: valid events with pixels: 0
[16:12:19.824] <TB2> INFO: valid pixel hits: 0
[16:12:19.824] <TB2> INFO: Event errors: 0
[16:12:19.824] <TB2> INFO: start marker: 0
[16:12:19.824] <TB2> INFO: stop marker: 0
[16:12:19.824] <TB2> INFO: overflow: 0
[16:12:19.824] <TB2> INFO: invalid 5bit words: 0
[16:12:19.824] <TB2> INFO: invalid XOR eye diagram: 0
[16:12:19.824] <TB2> INFO: frame (failed synchr.): 0
[16:12:19.824] <TB2> INFO: idle data (no TBM trl): 0
[16:12:19.824] <TB2> INFO: no data (only TBM hdr): 0
[16:12:19.824] <TB2> INFO: TBM errors: 0
[16:12:19.824] <TB2> INFO: flawed TBM headers: 0
[16:12:19.824] <TB2> INFO: flawed TBM trailers: 0
[16:12:19.824] <TB2> INFO: event ID mismatches: 0
[16:12:19.824] <TB2> INFO: ROC errors: 0
[16:12:19.824] <TB2> INFO: missing ROC header(s): 0
[16:12:19.824] <TB2> INFO: misplaced readback start: 0
[16:12:19.824] <TB2> INFO: Pixel decoding errors: 0
[16:12:19.824] <TB2> INFO: pixel data incomplete: 0
[16:12:19.824] <TB2> INFO: pixel address: 0
[16:12:19.824] <TB2> INFO: pulse height fill bit: 0
[16:12:19.824] <TB2> INFO: buffer corruption: 0
[16:12:19.831] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C15.dat
[16:12:19.832] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[16:12:19.832] <TB2> INFO: ######################################################################
[16:12:19.832] <TB2> INFO: PixTestReadback::doTest()
[16:12:19.832] <TB2> INFO: ######################################################################
[16:12:19.832] <TB2> INFO: ----------------------------------------------------------------------
[16:12:19.832] <TB2> INFO: PixTestReadback::CalibrateVd()
[16:12:19.832] <TB2> INFO: ----------------------------------------------------------------------
[16:12:29.812] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C0.dat
[16:12:29.812] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C1.dat
[16:12:29.813] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C2.dat
[16:12:29.813] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C3.dat
[16:12:29.813] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C4.dat
[16:12:29.813] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C5.dat
[16:12:29.813] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C6.dat
[16:12:29.813] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C7.dat
[16:12:29.813] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C8.dat
[16:12:29.813] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C9.dat
[16:12:29.813] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C10.dat
[16:12:29.813] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C11.dat
[16:12:29.813] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C12.dat
[16:12:29.813] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C13.dat
[16:12:29.814] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C14.dat
[16:12:29.814] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C15.dat
[16:12:29.847] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:12:29.847] <TB2> INFO: ----------------------------------------------------------------------
[16:12:29.847] <TB2> INFO: PixTestReadback::CalibrateVa()
[16:12:29.847] <TB2> INFO: ----------------------------------------------------------------------
[16:12:39.795] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C0.dat
[16:12:39.795] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C1.dat
[16:12:39.795] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C2.dat
[16:12:39.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C3.dat
[16:12:39.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C4.dat
[16:12:39.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C5.dat
[16:12:39.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C6.dat
[16:12:39.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C7.dat
[16:12:39.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C8.dat
[16:12:39.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C9.dat
[16:12:39.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C10.dat
[16:12:39.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C11.dat
[16:12:39.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C12.dat
[16:12:39.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C13.dat
[16:12:39.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C14.dat
[16:12:39.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C15.dat
[16:12:39.827] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:12:39.827] <TB2> INFO: ----------------------------------------------------------------------
[16:12:39.827] <TB2> INFO: PixTestReadback::readbackVbg()
[16:12:39.827] <TB2> INFO: ----------------------------------------------------------------------
[16:12:47.502] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:12:47.502] <TB2> INFO: ----------------------------------------------------------------------
[16:12:47.502] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[16:12:47.502] <TB2> INFO: ----------------------------------------------------------------------
[16:12:47.502] <TB2> INFO: Vbg will be calibrated using Vd calibration
[16:12:47.502] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 153.1calibrated Vbg = 1.18661 :::*/*/*/*/
[16:12:47.502] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 147.2calibrated Vbg = 1.18566 :::*/*/*/*/
[16:12:47.502] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 153.5calibrated Vbg = 1.17993 :::*/*/*/*/
[16:12:47.502] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 159calibrated Vbg = 1.1812 :::*/*/*/*/
[16:12:47.502] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 160.2calibrated Vbg = 1.17818 :::*/*/*/*/
[16:12:47.502] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 143.7calibrated Vbg = 1.17745 :::*/*/*/*/
[16:12:47.502] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 144.6calibrated Vbg = 1.17606 :::*/*/*/*/
[16:12:47.503] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 152.7calibrated Vbg = 1.18876 :::*/*/*/*/
[16:12:47.503] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 149.8calibrated Vbg = 1.18617 :::*/*/*/*/
[16:12:47.503] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 153.3calibrated Vbg = 1.18585 :::*/*/*/*/
[16:12:47.503] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 152.1calibrated Vbg = 1.17234 :::*/*/*/*/
[16:12:47.503] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 158.8calibrated Vbg = 1.17001 :::*/*/*/*/
[16:12:47.503] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 150calibrated Vbg = 1.17589 :::*/*/*/*/
[16:12:47.503] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 164.2calibrated Vbg = 1.18348 :::*/*/*/*/
[16:12:47.503] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 157.6calibrated Vbg = 1.18129 :::*/*/*/*/
[16:12:47.503] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 153calibrated Vbg = 1.1793 :::*/*/*/*/
[16:12:47.506] <TB2> INFO: ----------------------------------------------------------------------
[16:12:47.507] <TB2> INFO: PixTestReadback::CalibrateIa()
[16:12:47.507] <TB2> INFO: ----------------------------------------------------------------------
[16:15:28.304] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C0.dat
[16:15:28.304] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C1.dat
[16:15:28.304] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C2.dat
[16:15:28.304] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C3.dat
[16:15:28.304] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C4.dat
[16:15:28.304] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C5.dat
[16:15:28.304] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C6.dat
[16:15:28.304] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C7.dat
[16:15:28.304] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C8.dat
[16:15:28.304] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C9.dat
[16:15:28.305] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C10.dat
[16:15:28.305] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C11.dat
[16:15:28.305] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C12.dat
[16:15:28.305] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C13.dat
[16:15:28.305] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C14.dat
[16:15:28.305] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//readbackCal_C15.dat
[16:15:28.331] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:15:28.332] <TB2> INFO: PixTestReadback::doTest() done
[16:15:28.332] <TB2> INFO: Decoding statistics:
[16:15:28.332] <TB2> INFO: General information:
[16:15:28.332] <TB2> INFO: 16bit words read: 1536
[16:15:28.332] <TB2> INFO: valid events total: 256
[16:15:28.332] <TB2> INFO: empty events: 256
[16:15:28.332] <TB2> INFO: valid events with pixels: 0
[16:15:28.332] <TB2> INFO: valid pixel hits: 0
[16:15:28.332] <TB2> INFO: Event errors: 0
[16:15:28.332] <TB2> INFO: start marker: 0
[16:15:28.332] <TB2> INFO: stop marker: 0
[16:15:28.332] <TB2> INFO: overflow: 0
[16:15:28.332] <TB2> INFO: invalid 5bit words: 0
[16:15:28.332] <TB2> INFO: invalid XOR eye diagram: 0
[16:15:28.332] <TB2> INFO: frame (failed synchr.): 0
[16:15:28.332] <TB2> INFO: idle data (no TBM trl): 0
[16:15:28.332] <TB2> INFO: no data (only TBM hdr): 0
[16:15:28.332] <TB2> INFO: TBM errors: 0
[16:15:28.332] <TB2> INFO: flawed TBM headers: 0
[16:15:28.333] <TB2> INFO: flawed TBM trailers: 0
[16:15:28.333] <TB2> INFO: event ID mismatches: 0
[16:15:28.333] <TB2> INFO: ROC errors: 0
[16:15:28.333] <TB2> INFO: missing ROC header(s): 0
[16:15:28.333] <TB2> INFO: misplaced readback start: 0
[16:15:28.333] <TB2> INFO: Pixel decoding errors: 0
[16:15:28.333] <TB2> INFO: pixel data incomplete: 0
[16:15:28.333] <TB2> INFO: pixel address: 0
[16:15:28.333] <TB2> INFO: pulse height fill bit: 0
[16:15:28.333] <TB2> INFO: buffer corruption: 0
[16:15:28.383] <TB2> INFO: ######################################################################
[16:15:28.383] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[16:15:28.383] <TB2> INFO: ######################################################################
[16:15:28.385] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[16:15:28.415] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:15:28.415] <TB2> INFO: run 1 of 1
[16:15:28.651] <TB2> INFO: Expecting 3120000 events.
[16:15:59.442] <TB2> INFO: 656560 events read in total (30199ms).











[16:16:29.481] <TB2> INFO: 1312315 events read in total (60239ms).
[16:16:59.401] <TB2> INFO: 1964870 events read in total (90158ms).











[16:17:29.576] <TB2> INFO: 2617615 events read in total (120333ms).











[16:17:53.489] <TB2> INFO: 3120000 events read in total (144246ms).
[16:17:53.639] <TB2> INFO: Test took 145225ms.
[16:18:17.376] <TB2> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 168 seconds
[16:18:17.376] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 0 1 0 0 0 2 1 0 0 0 0 0 0
[16:18:17.376] <TB2> INFO: separation cut (per ROC): 102 94 105 100 101 95 96 107 103 103 105 108 104 114 103 104
[16:18:17.377] <TB2> INFO: Decoding statistics:
[16:18:17.377] <TB2> INFO: General information:
[16:18:17.377] <TB2> INFO: 16bit words read: 0
[16:18:17.377] <TB2> INFO: valid events total: 0
[16:18:17.377] <TB2> INFO: empty events: 0
[16:18:17.377] <TB2> INFO: valid events with pixels: 0
[16:18:17.377] <TB2> INFO: valid pixel hits: 0
[16:18:17.377] <TB2> INFO: Event errors: 0
[16:18:17.377] <TB2> INFO: start marker: 0
[16:18:17.377] <TB2> INFO: stop marker: 0
[16:18:17.377] <TB2> INFO: overflow: 0
[16:18:17.377] <TB2> INFO: invalid 5bit words: 0
[16:18:17.377] <TB2> INFO: invalid XOR eye diagram: 0
[16:18:17.377] <TB2> INFO: frame (failed synchr.): 0
[16:18:17.377] <TB2> INFO: idle data (no TBM trl): 0
[16:18:17.377] <TB2> INFO: no data (only TBM hdr): 0
[16:18:17.377] <TB2> INFO: TBM errors: 0
[16:18:17.377] <TB2> INFO: flawed TBM headers: 0
[16:18:17.377] <TB2> INFO: flawed TBM trailers: 0
[16:18:17.377] <TB2> INFO: event ID mismatches: 0
[16:18:17.377] <TB2> INFO: ROC errors: 0
[16:18:17.377] <TB2> INFO: missing ROC header(s): 0
[16:18:17.377] <TB2> INFO: misplaced readback start: 0
[16:18:17.377] <TB2> INFO: Pixel decoding errors: 0
[16:18:17.377] <TB2> INFO: pixel data incomplete: 0
[16:18:17.377] <TB2> INFO: pixel address: 0
[16:18:17.377] <TB2> INFO: pulse height fill bit: 0
[16:18:17.377] <TB2> INFO: buffer corruption: 0
[16:18:17.413] <TB2> INFO: ######################################################################
[16:18:17.413] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:18:17.413] <TB2> INFO: ######################################################################
[16:18:17.413] <TB2> INFO: ----------------------------------------------------------------------
[16:18:17.413] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:18:17.413] <TB2> INFO: ----------------------------------------------------------------------
[16:18:17.414] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[16:18:17.428] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[16:18:17.428] <TB2> INFO: run 1 of 1
[16:18:17.727] <TB2> INFO: Expecting 36608000 events.
[16:18:40.955] <TB2> INFO: 661250 events read in total (22636ms).
[16:19:03.721] <TB2> INFO: 1311200 events read in total (45402ms).
[16:19:26.325] <TB2> INFO: 1959750 events read in total (68006ms).
[16:19:48.901] <TB2> INFO: 2607800 events read in total (90582ms).
[16:20:11.451] <TB2> INFO: 3255450 events read in total (113132ms).
[16:20:34.238] <TB2> INFO: 3904700 events read in total (135919ms).
[16:20:57.182] <TB2> INFO: 4552650 events read in total (158863ms).
[16:21:19.767] <TB2> INFO: 5199100 events read in total (181448ms).
[16:21:42.432] <TB2> INFO: 5846700 events read in total (204113ms).
[16:22:05.115] <TB2> INFO: 6492850 events read in total (226796ms).
[16:22:27.721] <TB2> INFO: 7140100 events read in total (249402ms).
[16:22:50.125] <TB2> INFO: 7784100 events read in total (271806ms).
[16:23:12.633] <TB2> INFO: 8428900 events read in total (294314ms).
[16:23:35.270] <TB2> INFO: 9072350 events read in total (316951ms).
[16:23:57.624] <TB2> INFO: 9717700 events read in total (339305ms).
[16:24:20.209] <TB2> INFO: 10363150 events read in total (361890ms).
[16:24:42.575] <TB2> INFO: 11008200 events read in total (384256ms).
[16:25:04.983] <TB2> INFO: 11653500 events read in total (406664ms).
[16:25:27.238] <TB2> INFO: 12299250 events read in total (428919ms).
[16:25:49.670] <TB2> INFO: 12943600 events read in total (451351ms).
[16:26:12.306] <TB2> INFO: 13587450 events read in total (473987ms).
[16:26:34.583] <TB2> INFO: 14231200 events read in total (496264ms).
[16:26:56.946] <TB2> INFO: 14873250 events read in total (518627ms).
[16:27:19.394] <TB2> INFO: 15513900 events read in total (541075ms).
[16:27:41.714] <TB2> INFO: 16155100 events read in total (563395ms).
[16:28:04.148] <TB2> INFO: 16795300 events read in total (585829ms).
[16:28:26.729] <TB2> INFO: 17438300 events read in total (608410ms).
[16:28:49.460] <TB2> INFO: 18081600 events read in total (631141ms).
[16:29:11.895] <TB2> INFO: 18724750 events read in total (653576ms).
[16:29:34.586] <TB2> INFO: 19365850 events read in total (676267ms).
[16:29:57.119] <TB2> INFO: 20006600 events read in total (698800ms).
[16:30:19.590] <TB2> INFO: 20645350 events read in total (721271ms).
[16:30:42.188] <TB2> INFO: 21285350 events read in total (743869ms).
[16:31:04.585] <TB2> INFO: 21926250 events read in total (766266ms).
[16:31:27.275] <TB2> INFO: 22565100 events read in total (788956ms).
[16:31:49.865] <TB2> INFO: 23204450 events read in total (811546ms).
[16:32:12.383] <TB2> INFO: 23843200 events read in total (834064ms).
[16:32:34.970] <TB2> INFO: 24480800 events read in total (856651ms).
[16:32:57.434] <TB2> INFO: 25119850 events read in total (879115ms).
[16:33:20.093] <TB2> INFO: 25759900 events read in total (901774ms).
[16:33:42.368] <TB2> INFO: 26398950 events read in total (924049ms).
[16:34:04.853] <TB2> INFO: 27038700 events read in total (946534ms).
[16:34:27.511] <TB2> INFO: 27678400 events read in total (969192ms).
[16:34:49.003] <TB2> INFO: 28317250 events read in total (991684ms).
[16:35:12.460] <TB2> INFO: 28956700 events read in total (1014141ms).
[16:35:35.060] <TB2> INFO: 29595350 events read in total (1036741ms).
[16:35:57.663] <TB2> INFO: 30233450 events read in total (1059344ms).
[16:36:20.128] <TB2> INFO: 30870200 events read in total (1081809ms).
[16:36:42.436] <TB2> INFO: 31509550 events read in total (1104117ms).
[16:37:05.115] <TB2> INFO: 32147600 events read in total (1126796ms).
[16:37:27.598] <TB2> INFO: 32786500 events read in total (1149279ms).
[16:37:50.046] <TB2> INFO: 33424950 events read in total (1171727ms).
[16:38:12.782] <TB2> INFO: 34063450 events read in total (1194463ms).
[16:38:35.322] <TB2> INFO: 34703100 events read in total (1217003ms).
[16:38:57.760] <TB2> INFO: 35341050 events read in total (1239441ms).
[16:39:20.521] <TB2> INFO: 35983750 events read in total (1262202ms).
[16:39:43.480] <TB2> INFO: 36608000 events read in total (1285161ms).
[16:39:43.669] <TB2> INFO: Test took 1286241ms.
[16:39:44.186] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:39:45.634] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:39:47.077] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:39:48.580] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:39:50.101] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:39:51.616] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:39:53.319] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:39:55.128] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:39:56.748] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:39:58.611] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:40:00.362] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:40:02.071] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:40:03.582] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:40:05.156] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:40:07.023] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:40:08.996] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:40:10.707] <TB2> INFO: PixTestScurves::scurves() done
[16:40:10.707] <TB2> INFO: Vcal mean: 109.44 96.96 111.07 114.60 106.86 93.76 106.64 111.80 110.82 111.82 108.99 114.38 110.27 114.16 105.21 107.95
[16:40:10.707] <TB2> INFO: Vcal RMS: 5.26 5.43 4.87 6.44 4.86 5.35 4.83 5.29 4.95 5.40 5.98 5.95 5.25 5.42 4.76 5.19
[16:40:10.707] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1313 seconds
[16:40:10.707] <TB2> INFO: Decoding statistics:
[16:40:10.707] <TB2> INFO: General information:
[16:40:10.707] <TB2> INFO: 16bit words read: 0
[16:40:10.707] <TB2> INFO: valid events total: 0
[16:40:10.707] <TB2> INFO: empty events: 0
[16:40:10.707] <TB2> INFO: valid events with pixels: 0
[16:40:10.707] <TB2> INFO: valid pixel hits: 0
[16:40:10.707] <TB2> INFO: Event errors: 0
[16:40:10.707] <TB2> INFO: start marker: 0
[16:40:10.707] <TB2> INFO: stop marker: 0
[16:40:10.707] <TB2> INFO: overflow: 0
[16:40:10.707] <TB2> INFO: invalid 5bit words: 0
[16:40:10.707] <TB2> INFO: invalid XOR eye diagram: 0
[16:40:10.707] <TB2> INFO: frame (failed synchr.): 0
[16:40:10.707] <TB2> INFO: idle data (no TBM trl): 0
[16:40:10.707] <TB2> INFO: no data (only TBM hdr): 0
[16:40:10.707] <TB2> INFO: TBM errors: 0
[16:40:10.708] <TB2> INFO: flawed TBM headers: 0
[16:40:10.708] <TB2> INFO: flawed TBM trailers: 0
[16:40:10.708] <TB2> INFO: event ID mismatches: 0
[16:40:10.708] <TB2> INFO: ROC errors: 0
[16:40:10.708] <TB2> INFO: missing ROC header(s): 0
[16:40:10.708] <TB2> INFO: misplaced readback start: 0
[16:40:10.708] <TB2> INFO: Pixel decoding errors: 0
[16:40:10.708] <TB2> INFO: pixel data incomplete: 0
[16:40:10.708] <TB2> INFO: pixel address: 0
[16:40:10.708] <TB2> INFO: pulse height fill bit: 0
[16:40:10.708] <TB2> INFO: buffer corruption: 0
[16:40:10.800] <TB2> INFO: ######################################################################
[16:40:10.800] <TB2> INFO: PixTestTrim::doTest()
[16:40:10.800] <TB2> INFO: ######################################################################
[16:40:10.801] <TB2> INFO: ----------------------------------------------------------------------
[16:40:10.801] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[16:40:10.801] <TB2> INFO: ----------------------------------------------------------------------
[16:40:10.841] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[16:40:10.841] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:40:10.854] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:40:10.854] <TB2> INFO: run 1 of 1
[16:40:11.089] <TB2> INFO: Expecting 5025280 events.
[16:40:41.544] <TB2> INFO: 809328 events read in total (29851ms).
[16:41:11.363] <TB2> INFO: 1615776 events read in total (59670ms).
[16:41:41.513] <TB2> INFO: 2419632 events read in total (89820ms).
[16:42:11.459] <TB2> INFO: 3222544 events read in total (119766ms).
[16:42:41.155] <TB2> INFO: 4021720 events read in total (149462ms).
[16:43:11.529] <TB2> INFO: 4818016 events read in total (179836ms).
[16:43:19.336] <TB2> INFO: 5025280 events read in total (187643ms).
[16:43:19.399] <TB2> INFO: Test took 188545ms.
[16:43:38.832] <TB2> INFO: ROC 0 VthrComp = 117
[16:43:38.832] <TB2> INFO: ROC 1 VthrComp = 107
[16:43:38.832] <TB2> INFO: ROC 2 VthrComp = 128
[16:43:38.832] <TB2> INFO: ROC 3 VthrComp = 119
[16:43:38.832] <TB2> INFO: ROC 4 VthrComp = 112
[16:43:38.832] <TB2> INFO: ROC 5 VthrComp = 101
[16:43:38.832] <TB2> INFO: ROC 6 VthrComp = 110
[16:43:38.832] <TB2> INFO: ROC 7 VthrComp = 121
[16:43:38.832] <TB2> INFO: ROC 8 VthrComp = 117
[16:43:38.833] <TB2> INFO: ROC 9 VthrComp = 115
[16:43:38.833] <TB2> INFO: ROC 10 VthrComp = 112
[16:43:38.833] <TB2> INFO: ROC 11 VthrComp = 118
[16:43:38.833] <TB2> INFO: ROC 12 VthrComp = 112
[16:43:38.833] <TB2> INFO: ROC 13 VthrComp = 121
[16:43:38.833] <TB2> INFO: ROC 14 VthrComp = 111
[16:43:38.833] <TB2> INFO: ROC 15 VthrComp = 116
[16:43:39.074] <TB2> INFO: Expecting 41600 events.
[16:43:42.614] <TB2> INFO: 41600 events read in total (2948ms).
[16:43:42.615] <TB2> INFO: Test took 3780ms.
[16:43:42.624] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[16:43:42.625] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:43:42.636] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:43:42.636] <TB2> INFO: run 1 of 1
[16:43:42.914] <TB2> INFO: Expecting 5025280 events.
[16:44:09.492] <TB2> INFO: 591088 events read in total (25986ms).
[16:44:35.494] <TB2> INFO: 1180360 events read in total (51988ms).
[16:45:01.282] <TB2> INFO: 1769360 events read in total (77776ms).
[16:45:26.886] <TB2> INFO: 2356888 events read in total (103380ms).
[16:45:52.298] <TB2> INFO: 2942584 events read in total (128792ms).
[16:46:17.906] <TB2> INFO: 3527200 events read in total (154400ms).
[16:46:43.545] <TB2> INFO: 4110120 events read in total (180039ms).
[16:47:09.564] <TB2> INFO: 4692560 events read in total (206058ms).
[16:47:24.641] <TB2> INFO: 5025280 events read in total (221135ms).
[16:47:24.794] <TB2> INFO: Test took 222158ms.
[16:47:48.342] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 60.6004 for pixel 15/1 mean/min/max = 45.9919/31.3137/60.67
[16:47:48.342] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 58.424 for pixel 18/1 mean/min/max = 46.085/33.7447/58.4253
[16:47:48.343] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 55.9994 for pixel 20/10 mean/min/max = 43.9255/31.5924/56.2587
[16:47:48.343] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 63.0632 for pixel 1/79 mean/min/max = 46.4024/29.5357/63.269
[16:47:48.344] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 57.0782 for pixel 34/32 mean/min/max = 44.9757/32.4424/57.509
[16:47:48.344] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 57.5652 for pixel 0/54 mean/min/max = 45.5263/33.4183/57.6342
[16:47:48.345] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 58.9321 for pixel 46/65 mean/min/max = 46.8789/34.7504/59.0075
[16:47:48.346] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 58.7086 for pixel 13/16 mean/min/max = 45.0576/31.3649/58.7503
[16:47:48.346] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 58.0801 for pixel 11/71 mean/min/max = 44.8507/31.4558/58.2457
[16:47:48.347] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 59.4417 for pixel 14/42 mean/min/max = 45.5986/31.7246/59.4726
[16:47:48.347] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 62.3361 for pixel 0/13 mean/min/max = 46.7381/31.0443/62.4318
[16:47:48.348] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 61.5422 for pixel 0/50 mean/min/max = 46.3871/31.0307/61.7434
[16:47:48.348] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 60.1293 for pixel 3/2 mean/min/max = 46.5005/32.4205/60.5806
[16:47:48.348] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 58.3184 for pixel 13/61 mean/min/max = 45.4354/32.4528/58.4179
[16:47:48.349] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 58.2509 for pixel 3/2 mean/min/max = 46.5907/34.8328/58.3486
[16:47:48.349] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 58.8049 for pixel 7/4 mean/min/max = 45.4442/31.9957/58.8926
[16:47:48.350] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:47:48.438] <TB2> INFO: Expecting 411648 events.
[16:47:58.022] <TB2> INFO: 411648 events read in total (8992ms).
[16:47:58.029] <TB2> INFO: Expecting 411648 events.
[16:48:07.455] <TB2> INFO: 411648 events read in total (9023ms).
[16:48:07.465] <TB2> INFO: Expecting 411648 events.
[16:48:16.897] <TB2> INFO: 411648 events read in total (9029ms).
[16:48:16.913] <TB2> INFO: Expecting 411648 events.
[16:48:26.320] <TB2> INFO: 411648 events read in total (9004ms).
[16:48:26.337] <TB2> INFO: Expecting 411648 events.
[16:48:35.715] <TB2> INFO: 411648 events read in total (8975ms).
[16:48:35.735] <TB2> INFO: Expecting 411648 events.
[16:48:45.039] <TB2> INFO: 411648 events read in total (8901ms).
[16:48:45.060] <TB2> INFO: Expecting 411648 events.
[16:48:54.430] <TB2> INFO: 411648 events read in total (8967ms).
[16:48:54.455] <TB2> INFO: Expecting 411648 events.
[16:49:03.881] <TB2> INFO: 411648 events read in total (9022ms).
[16:49:03.910] <TB2> INFO: Expecting 411648 events.
[16:49:13.257] <TB2> INFO: 411648 events read in total (8944ms).
[16:49:13.288] <TB2> INFO: Expecting 411648 events.
[16:49:22.684] <TB2> INFO: 411648 events read in total (8993ms).
[16:49:22.718] <TB2> INFO: Expecting 411648 events.
[16:49:32.098] <TB2> INFO: 411648 events read in total (8977ms).
[16:49:32.136] <TB2> INFO: Expecting 411648 events.
[16:49:41.541] <TB2> INFO: 411648 events read in total (9002ms).
[16:49:41.582] <TB2> INFO: Expecting 411648 events.
[16:49:50.934] <TB2> INFO: 411648 events read in total (8949ms).
[16:49:50.977] <TB2> INFO: Expecting 411648 events.
[16:50:00.490] <TB2> INFO: 411648 events read in total (9110ms).
[16:50:00.565] <TB2> INFO: Expecting 411648 events.
[16:50:09.803] <TB2> INFO: 411648 events read in total (8834ms).
[16:50:09.854] <TB2> INFO: Expecting 411648 events.
[16:50:19.113] <TB2> INFO: 411648 events read in total (8856ms).
[16:50:19.176] <TB2> INFO: Test took 150826ms.
[16:50:20.143] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[16:50:20.156] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:50:20.156] <TB2> INFO: run 1 of 1
[16:50:20.435] <TB2> INFO: Expecting 5025280 events.
[16:50:46.528] <TB2> INFO: 585864 events read in total (25501ms).
[16:51:12.340] <TB2> INFO: 1169544 events read in total (51313ms).
[16:51:38.630] <TB2> INFO: 1753520 events read in total (77603ms).
[16:52:04.918] <TB2> INFO: 2337584 events read in total (103891ms).
[16:52:30.904] <TB2> INFO: 2919272 events read in total (129878ms).
[16:52:56.901] <TB2> INFO: 3501800 events read in total (155874ms).
[16:53:23.188] <TB2> INFO: 4083648 events read in total (182161ms).
[16:53:49.321] <TB2> INFO: 4663952 events read in total (208294ms).
[16:54:06.077] <TB2> INFO: 5025280 events read in total (225050ms).
[16:54:06.221] <TB2> INFO: Test took 226067ms.
[16:54:28.295] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 3.500000 .. 145.493688
[16:54:28.534] <TB2> INFO: Expecting 208000 events.
[16:54:38.521] <TB2> INFO: 208000 events read in total (9395ms).
[16:54:38.522] <TB2> INFO: Test took 10225ms.
[16:54:38.572] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 3 .. 155 (-1/-1) hits flags = 528 (plus default)
[16:54:38.585] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:54:38.585] <TB2> INFO: run 1 of 1
[16:54:38.863] <TB2> INFO: Expecting 5091840 events.
[16:55:05.474] <TB2> INFO: 581328 events read in total (26019ms).
[16:55:30.990] <TB2> INFO: 1163168 events read in total (51535ms).
[16:55:56.560] <TB2> INFO: 1744904 events read in total (77105ms).
[16:56:22.709] <TB2> INFO: 2326592 events read in total (103255ms).
[16:56:48.475] <TB2> INFO: 2908120 events read in total (129020ms).
[16:57:13.969] <TB2> INFO: 3489448 events read in total (154514ms).
[16:57:39.729] <TB2> INFO: 4070120 events read in total (180274ms).
[16:58:06.280] <TB2> INFO: 4649736 events read in total (206825ms).
[16:58:26.598] <TB2> INFO: 5091840 events read in total (227143ms).
[16:58:26.692] <TB2> INFO: Test took 228107ms.
[16:58:48.801] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.097865 .. 46.915717
[16:58:49.043] <TB2> INFO: Expecting 208000 events.
[16:58:58.992] <TB2> INFO: 208000 events read in total (9358ms).
[16:58:58.994] <TB2> INFO: Test took 10191ms.
[16:58:59.043] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[16:58:59.056] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:58:59.056] <TB2> INFO: run 1 of 1
[16:58:59.334] <TB2> INFO: Expecting 1331200 events.
[16:59:27.989] <TB2> INFO: 654992 events read in total (28063ms).
[16:59:55.955] <TB2> INFO: 1307896 events read in total (56029ms).
[16:59:57.364] <TB2> INFO: 1331200 events read in total (57438ms).
[16:59:57.393] <TB2> INFO: Test took 58337ms.
[17:00:09.334] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 25.554086 .. 44.880698
[17:00:09.580] <TB2> INFO: Expecting 208000 events.
[17:00:19.419] <TB2> INFO: 208000 events read in total (9247ms).
[17:00:19.421] <TB2> INFO: Test took 10086ms.
[17:00:19.490] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 54 (-1/-1) hits flags = 528 (plus default)
[17:00:19.504] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:00:19.504] <TB2> INFO: run 1 of 1
[17:00:19.782] <TB2> INFO: Expecting 1331200 events.
[17:00:48.626] <TB2> INFO: 672184 events read in total (28253ms).
[17:01:16.532] <TB2> INFO: 1331200 events read in total (56159ms).
[17:01:16.572] <TB2> INFO: Test took 57069ms.
[17:01:28.683] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 22.283730 .. 43.110343
[17:01:28.919] <TB2> INFO: Expecting 208000 events.
[17:01:39.035] <TB2> INFO: 208000 events read in total (9524ms).
[17:01:39.036] <TB2> INFO: Test took 10352ms.
[17:01:39.085] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 12 .. 53 (-1/-1) hits flags = 528 (plus default)
[17:01:39.098] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:01:39.098] <TB2> INFO: run 1 of 1
[17:01:39.384] <TB2> INFO: Expecting 1397760 events.
[17:02:07.940] <TB2> INFO: 688256 events read in total (27964ms).
[17:02:36.860] <TB2> INFO: 1375904 events read in total (56884ms).
[17:02:38.186] <TB2> INFO: 1397760 events read in total (58211ms).
[17:02:38.220] <TB2> INFO: Test took 59123ms.
[17:02:52.441] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[17:02:52.441] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[17:02:52.459] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:02:52.459] <TB2> INFO: run 1 of 1
[17:02:52.728] <TB2> INFO: Expecting 1364480 events.
[17:03:21.169] <TB2> INFO: 667720 events read in total (27849ms).
[17:03:49.209] <TB2> INFO: 1334728 events read in total (55889ms).
[17:03:50.950] <TB2> INFO: 1364480 events read in total (57630ms).
[17:03:50.986] <TB2> INFO: Test took 58527ms.
[17:04:05.635] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C0.dat
[17:04:05.635] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C1.dat
[17:04:05.635] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C2.dat
[17:04:05.635] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C3.dat
[17:04:05.635] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C4.dat
[17:04:05.635] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C5.dat
[17:04:05.635] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C6.dat
[17:04:05.635] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C7.dat
[17:04:05.635] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C8.dat
[17:04:05.635] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C9.dat
[17:04:05.635] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C10.dat
[17:04:05.635] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C11.dat
[17:04:05.636] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C12.dat
[17:04:05.636] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C13.dat
[17:04:05.636] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C14.dat
[17:04:05.636] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C15.dat
[17:04:05.636] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C0.dat
[17:04:05.641] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C1.dat
[17:04:05.646] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C2.dat
[17:04:05.651] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C3.dat
[17:04:05.656] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C4.dat
[17:04:05.661] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C5.dat
[17:04:05.666] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C6.dat
[17:04:05.670] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C7.dat
[17:04:05.675] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C8.dat
[17:04:05.680] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C9.dat
[17:04:05.685] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C10.dat
[17:04:05.690] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C11.dat
[17:04:05.695] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C12.dat
[17:04:05.699] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C13.dat
[17:04:05.704] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C14.dat
[17:04:05.709] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//trimParameters35_C15.dat
[17:04:05.714] <TB2> INFO: PixTestTrim::trimTest() done
[17:04:05.714] <TB2> INFO: vtrim: 127 130 123 147 136 100 120 133 137 124 132 119 114 135 135 130
[17:04:05.714] <TB2> INFO: vthrcomp: 117 107 128 119 112 101 110 121 117 115 112 118 112 121 111 116
[17:04:05.714] <TB2> INFO: vcal mean: 35.02 34.95 34.96 34.94 34.96 34.97 35.02 34.85 34.97 34.97 34.95 35.01 34.97 34.94 34.96 34.95
[17:04:05.714] <TB2> INFO: vcal RMS: 1.04 0.93 0.98 1.21 1.01 0.88 0.98 1.04 0.99 0.95 1.04 1.15 0.98 0.99 0.95 0.97
[17:04:05.714] <TB2> INFO: bits mean: 9.58 9.56 9.90 9.60 9.81 8.66 8.90 9.72 9.94 9.82 9.31 9.12 9.21 9.93 8.82 9.48
[17:04:05.714] <TB2> INFO: bits RMS: 2.76 2.41 2.60 2.86 2.50 2.88 2.50 2.76 2.64 2.60 2.83 2.96 2.75 2.44 2.53 2.73
[17:04:05.722] <TB2> INFO: ----------------------------------------------------------------------
[17:04:05.722] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[17:04:05.722] <TB2> INFO: ----------------------------------------------------------------------
[17:04:05.724] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[17:04:05.738] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:04:05.738] <TB2> INFO: run 1 of 1
[17:04:06.018] <TB2> INFO: Expecting 4160000 events.
[17:04:38.122] <TB2> INFO: 727635 events read in total (31512ms).
[17:05:09.528] <TB2> INFO: 1448820 events read in total (62918ms).
[17:05:40.863] <TB2> INFO: 2165780 events read in total (94253ms).
[17:06:11.849] <TB2> INFO: 2878570 events read in total (125239ms).
[17:06:42.981] <TB2> INFO: 3590190 events read in total (156371ms).
[17:07:08.555] <TB2> INFO: 4160000 events read in total (181945ms).
[17:07:08.666] <TB2> INFO: Test took 182928ms.
[17:07:34.133] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 189 (-1/-1) hits flags = 528 (plus default)
[17:07:34.147] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:07:34.147] <TB2> INFO: run 1 of 1
[17:07:34.410] <TB2> INFO: Expecting 3952000 events.
[17:08:06.156] <TB2> INFO: 716665 events read in total (31154ms).
[17:08:37.033] <TB2> INFO: 1428195 events read in total (62031ms).
[17:09:07.938] <TB2> INFO: 2135790 events read in total (92936ms).
[17:09:38.555] <TB2> INFO: 2840130 events read in total (123553ms).
[17:10:10.478] <TB2> INFO: 3543210 events read in total (155476ms).
[17:10:29.186] <TB2> INFO: 3952000 events read in total (174184ms).
[17:10:29.266] <TB2> INFO: Test took 175119ms.
[17:10:56.384] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 177 (-1/-1) hits flags = 528 (plus default)
[17:10:56.398] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:10:56.398] <TB2> INFO: run 1 of 1
[17:10:56.633] <TB2> INFO: Expecting 3702400 events.
[17:11:28.717] <TB2> INFO: 733705 events read in total (31493ms).
[17:12:00.047] <TB2> INFO: 1461255 events read in total (62823ms).
[17:12:31.315] <TB2> INFO: 2184170 events read in total (94091ms).
[17:13:02.394] <TB2> INFO: 2904220 events read in total (125170ms).
[17:13:33.626] <TB2> INFO: 3623145 events read in total (156402ms).
[17:13:37.338] <TB2> INFO: 3702400 events read in total (160114ms).
[17:13:37.403] <TB2> INFO: Test took 161005ms.
[17:14:04.812] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 176 (-1/-1) hits flags = 528 (plus default)
[17:14:04.828] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:14:04.828] <TB2> INFO: run 1 of 1
[17:14:05.071] <TB2> INFO: Expecting 3681600 events.
[17:14:36.943] <TB2> INFO: 735300 events read in total (31280ms).
[17:15:08.402] <TB2> INFO: 1464170 events read in total (62739ms).
[17:15:39.871] <TB2> INFO: 2188375 events read in total (94208ms).
[17:16:11.033] <TB2> INFO: 2909435 events read in total (125370ms).
[17:16:42.634] <TB2> INFO: 3630160 events read in total (156971ms).
[17:16:45.168] <TB2> INFO: 3681600 events read in total (159505ms).
[17:16:45.229] <TB2> INFO: Test took 160401ms.
[17:17:10.689] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 176 (-1/-1) hits flags = 528 (plus default)
[17:17:10.702] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:17:10.702] <TB2> INFO: run 1 of 1
[17:17:10.938] <TB2> INFO: Expecting 3681600 events.
[17:17:42.467] <TB2> INFO: 735345 events read in total (30937ms).
[17:18:13.880] <TB2> INFO: 1464485 events read in total (62350ms).
[17:18:45.441] <TB2> INFO: 2188930 events read in total (93911ms).
[17:19:16.443] <TB2> INFO: 2910090 events read in total (124913ms).
[17:19:47.813] <TB2> INFO: 3631075 events read in total (156283ms).
[17:19:50.463] <TB2> INFO: 3681600 events read in total (158933ms).
[17:19:50.534] <TB2> INFO: Test took 159832ms.
[17:20:12.494] <TB2> INFO: PixTestTrim::trimBitTest() done
[17:20:12.495] <TB2> INFO: PixTestTrim::doTest() done, duration: 2401 seconds
[17:20:12.495] <TB2> INFO: Decoding statistics:
[17:20:12.495] <TB2> INFO: General information:
[17:20:12.495] <TB2> INFO: 16bit words read: 0
[17:20:12.495] <TB2> INFO: valid events total: 0
[17:20:12.495] <TB2> INFO: empty events: 0
[17:20:12.495] <TB2> INFO: valid events with pixels: 0
[17:20:12.495] <TB2> INFO: valid pixel hits: 0
[17:20:12.495] <TB2> INFO: Event errors: 0
[17:20:12.495] <TB2> INFO: start marker: 0
[17:20:12.495] <TB2> INFO: stop marker: 0
[17:20:12.495] <TB2> INFO: overflow: 0
[17:20:12.495] <TB2> INFO: invalid 5bit words: 0
[17:20:12.495] <TB2> INFO: invalid XOR eye diagram: 0
[17:20:12.495] <TB2> INFO: frame (failed synchr.): 0
[17:20:12.495] <TB2> INFO: idle data (no TBM trl): 0
[17:20:12.496] <TB2> INFO: no data (only TBM hdr): 0
[17:20:12.496] <TB2> INFO: TBM errors: 0
[17:20:12.496] <TB2> INFO: flawed TBM headers: 0
[17:20:12.496] <TB2> INFO: flawed TBM trailers: 0
[17:20:12.496] <TB2> INFO: event ID mismatches: 0
[17:20:12.496] <TB2> INFO: ROC errors: 0
[17:20:12.496] <TB2> INFO: missing ROC header(s): 0
[17:20:12.496] <TB2> INFO: misplaced readback start: 0
[17:20:12.496] <TB2> INFO: Pixel decoding errors: 0
[17:20:12.496] <TB2> INFO: pixel data incomplete: 0
[17:20:12.496] <TB2> INFO: pixel address: 0
[17:20:12.496] <TB2> INFO: pulse height fill bit: 0
[17:20:12.496] <TB2> INFO: buffer corruption: 0
[17:20:13.123] <TB2> INFO: ######################################################################
[17:20:13.123] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[17:20:13.123] <TB2> INFO: ######################################################################
[17:20:13.362] <TB2> INFO: Expecting 41600 events.
[17:20:16.967] <TB2> INFO: 41600 events read in total (3013ms).
[17:20:16.968] <TB2> INFO: Test took 3844ms.
[17:20:17.415] <TB2> INFO: Expecting 41600 events.
[17:20:20.947] <TB2> INFO: 41600 events read in total (2940ms).
[17:20:20.948] <TB2> INFO: Test took 3778ms.
[17:20:21.237] <TB2> INFO: Expecting 41600 events.
[17:20:24.807] <TB2> INFO: 41600 events read in total (2978ms).
[17:20:24.808] <TB2> INFO: Test took 3835ms.
[17:20:25.100] <TB2> INFO: Expecting 41600 events.
[17:20:28.687] <TB2> INFO: 41600 events read in total (2995ms).
[17:20:28.688] <TB2> INFO: Test took 3855ms.
[17:20:29.007] <TB2> INFO: Expecting 41600 events.
[17:20:32.477] <TB2> INFO: 41600 events read in total (2879ms).
[17:20:32.478] <TB2> INFO: Test took 3766ms.
[17:20:32.767] <TB2> INFO: Expecting 41600 events.
[17:20:36.309] <TB2> INFO: 41600 events read in total (2950ms).
[17:20:36.310] <TB2> INFO: Test took 3808ms.
[17:20:36.599] <TB2> INFO: Expecting 41600 events.
[17:20:40.137] <TB2> INFO: 41600 events read in total (2946ms).
[17:20:40.137] <TB2> INFO: Test took 3803ms.
[17:20:40.429] <TB2> INFO: Expecting 41600 events.
[17:20:43.955] <TB2> INFO: 41600 events read in total (2934ms).
[17:20:43.956] <TB2> INFO: Test took 3792ms.
[17:20:44.247] <TB2> INFO: Expecting 41600 events.
[17:20:47.742] <TB2> INFO: 41600 events read in total (2904ms).
[17:20:47.744] <TB2> INFO: Test took 3762ms.
[17:20:48.050] <TB2> INFO: Expecting 41600 events.
[17:20:51.582] <TB2> INFO: 41600 events read in total (2941ms).
[17:20:51.583] <TB2> INFO: Test took 3815ms.
[17:20:51.874] <TB2> INFO: Expecting 41600 events.
[17:20:55.384] <TB2> INFO: 41600 events read in total (2918ms).
[17:20:55.385] <TB2> INFO: Test took 3776ms.
[17:20:55.689] <TB2> INFO: Expecting 41600 events.
[17:20:59.210] <TB2> INFO: 41600 events read in total (2929ms).
[17:20:59.211] <TB2> INFO: Test took 3800ms.
[17:20:59.511] <TB2> INFO: Expecting 41600 events.
[17:21:03.004] <TB2> INFO: 41600 events read in total (2902ms).
[17:21:03.005] <TB2> INFO: Test took 3768ms.
[17:21:03.294] <TB2> INFO: Expecting 41600 events.
[17:21:06.791] <TB2> INFO: 41600 events read in total (2906ms).
[17:21:06.792] <TB2> INFO: Test took 3763ms.
[17:21:07.081] <TB2> INFO: Expecting 41600 events.
[17:21:10.550] <TB2> INFO: 41600 events read in total (2878ms).
[17:21:10.550] <TB2> INFO: Test took 3734ms.
[17:21:10.839] <TB2> INFO: Expecting 41600 events.
[17:21:14.310] <TB2> INFO: 41600 events read in total (2879ms).
[17:21:14.311] <TB2> INFO: Test took 3736ms.
[17:21:14.600] <TB2> INFO: Expecting 41600 events.
[17:21:18.153] <TB2> INFO: 41600 events read in total (2961ms).
[17:21:18.154] <TB2> INFO: Test took 3819ms.
[17:21:18.456] <TB2> INFO: Expecting 41600 events.
[17:21:21.945] <TB2> INFO: 41600 events read in total (2897ms).
[17:21:21.946] <TB2> INFO: Test took 3767ms.
[17:21:22.236] <TB2> INFO: Expecting 41600 events.
[17:21:25.769] <TB2> INFO: 41600 events read in total (2942ms).
[17:21:25.770] <TB2> INFO: Test took 3799ms.
[17:21:26.062] <TB2> INFO: Expecting 41600 events.
[17:21:29.697] <TB2> INFO: 41600 events read in total (3043ms).
[17:21:29.698] <TB2> INFO: Test took 3902ms.
[17:21:29.987] <TB2> INFO: Expecting 41600 events.
[17:21:33.545] <TB2> INFO: 41600 events read in total (2966ms).
[17:21:33.546] <TB2> INFO: Test took 3824ms.
[17:21:33.837] <TB2> INFO: Expecting 41600 events.
[17:21:37.375] <TB2> INFO: 41600 events read in total (2946ms).
[17:21:37.376] <TB2> INFO: Test took 3805ms.
[17:21:37.687] <TB2> INFO: Expecting 41600 events.
[17:21:41.228] <TB2> INFO: 41600 events read in total (2949ms).
[17:21:41.228] <TB2> INFO: Test took 3828ms.
[17:21:41.518] <TB2> INFO: Expecting 41600 events.
[17:21:45.076] <TB2> INFO: 41600 events read in total (2966ms).
[17:21:45.077] <TB2> INFO: Test took 3825ms.
[17:21:45.368] <TB2> INFO: Expecting 41600 events.
[17:21:48.908] <TB2> INFO: 41600 events read in total (2948ms).
[17:21:48.909] <TB2> INFO: Test took 3806ms.
[17:21:49.199] <TB2> INFO: Expecting 41600 events.
[17:21:52.827] <TB2> INFO: 41600 events read in total (3037ms).
[17:21:52.827] <TB2> INFO: Test took 3894ms.
[17:21:53.118] <TB2> INFO: Expecting 41600 events.
[17:21:56.672] <TB2> INFO: 41600 events read in total (2960ms).
[17:21:56.673] <TB2> INFO: Test took 3820ms.
[17:21:56.978] <TB2> INFO: Expecting 41600 events.
[17:22:00.580] <TB2> INFO: 41600 events read in total (3010ms).
[17:22:00.581] <TB2> INFO: Test took 3884ms.
[17:22:00.872] <TB2> INFO: Expecting 41600 events.
[17:22:04.560] <TB2> INFO: 41600 events read in total (3096ms).
[17:22:04.561] <TB2> INFO: Test took 3954ms.
[17:22:04.852] <TB2> INFO: Expecting 2560 events.
[17:22:05.741] <TB2> INFO: 2560 events read in total (297ms).
[17:22:05.741] <TB2> INFO: Test took 1164ms.
[17:22:06.049] <TB2> INFO: Expecting 2560 events.
[17:22:06.937] <TB2> INFO: 2560 events read in total (296ms).
[17:22:06.937] <TB2> INFO: Test took 1193ms.
[17:22:07.244] <TB2> INFO: Expecting 2560 events.
[17:22:08.129] <TB2> INFO: 2560 events read in total (294ms).
[17:22:08.129] <TB2> INFO: Test took 1191ms.
[17:22:08.436] <TB2> INFO: Expecting 2560 events.
[17:22:09.327] <TB2> INFO: 2560 events read in total (298ms).
[17:22:09.327] <TB2> INFO: Test took 1197ms.
[17:22:09.634] <TB2> INFO: Expecting 2560 events.
[17:22:10.522] <TB2> INFO: 2560 events read in total (296ms).
[17:22:10.522] <TB2> INFO: Test took 1195ms.
[17:22:10.831] <TB2> INFO: Expecting 2560 events.
[17:22:11.718] <TB2> INFO: 2560 events read in total (295ms).
[17:22:11.718] <TB2> INFO: Test took 1196ms.
[17:22:12.026] <TB2> INFO: Expecting 2560 events.
[17:22:12.919] <TB2> INFO: 2560 events read in total (302ms).
[17:22:12.919] <TB2> INFO: Test took 1200ms.
[17:22:13.226] <TB2> INFO: Expecting 2560 events.
[17:22:14.107] <TB2> INFO: 2560 events read in total (289ms).
[17:22:14.107] <TB2> INFO: Test took 1188ms.
[17:22:14.414] <TB2> INFO: Expecting 2560 events.
[17:22:15.304] <TB2> INFO: 2560 events read in total (298ms).
[17:22:15.304] <TB2> INFO: Test took 1196ms.
[17:22:15.612] <TB2> INFO: Expecting 2560 events.
[17:22:16.499] <TB2> INFO: 2560 events read in total (295ms).
[17:22:16.500] <TB2> INFO: Test took 1195ms.
[17:22:16.807] <TB2> INFO: Expecting 2560 events.
[17:22:17.688] <TB2> INFO: 2560 events read in total (290ms).
[17:22:17.688] <TB2> INFO: Test took 1187ms.
[17:22:17.996] <TB2> INFO: Expecting 2560 events.
[17:22:18.881] <TB2> INFO: 2560 events read in total (294ms).
[17:22:18.881] <TB2> INFO: Test took 1186ms.
[17:22:19.188] <TB2> INFO: Expecting 2560 events.
[17:22:20.078] <TB2> INFO: 2560 events read in total (298ms).
[17:22:20.078] <TB2> INFO: Test took 1196ms.
[17:22:20.387] <TB2> INFO: Expecting 2560 events.
[17:22:21.269] <TB2> INFO: 2560 events read in total (291ms).
[17:22:21.269] <TB2> INFO: Test took 1190ms.
[17:22:21.577] <TB2> INFO: Expecting 2560 events.
[17:22:22.469] <TB2> INFO: 2560 events read in total (300ms).
[17:22:22.469] <TB2> INFO: Test took 1200ms.
[17:22:22.777] <TB2> INFO: Expecting 2560 events.
[17:22:23.667] <TB2> INFO: 2560 events read in total (298ms).
[17:22:23.667] <TB2> INFO: Test took 1198ms.
[17:22:23.673] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:22:23.975] <TB2> INFO: Expecting 655360 events.
[17:22:38.871] <TB2> INFO: 655360 events read in total (14304ms).
[17:22:38.883] <TB2> INFO: Expecting 655360 events.
[17:22:53.447] <TB2> INFO: 655360 events read in total (14161ms).
[17:22:53.464] <TB2> INFO: Expecting 655360 events.
[17:23:08.087] <TB2> INFO: 655360 events read in total (14220ms).
[17:23:08.114] <TB2> INFO: Expecting 655360 events.
[17:23:22.890] <TB2> INFO: 655360 events read in total (14373ms).
[17:23:22.915] <TB2> INFO: Expecting 655360 events.
[17:23:37.533] <TB2> INFO: 655360 events read in total (14215ms).
[17:23:37.563] <TB2> INFO: Expecting 655360 events.
[17:23:52.146] <TB2> INFO: 655360 events read in total (14180ms).
[17:23:52.193] <TB2> INFO: Expecting 655360 events.
[17:24:06.770] <TB2> INFO: 655360 events read in total (14174ms).
[17:24:06.824] <TB2> INFO: Expecting 655360 events.
[17:24:21.505] <TB2> INFO: 655360 events read in total (14278ms).
[17:24:21.547] <TB2> INFO: Expecting 655360 events.
[17:24:36.102] <TB2> INFO: 655360 events read in total (14152ms).
[17:24:36.152] <TB2> INFO: Expecting 655360 events.
[17:24:50.691] <TB2> INFO: 655360 events read in total (14136ms).
[17:24:50.760] <TB2> INFO: Expecting 655360 events.
[17:25:05.524] <TB2> INFO: 655360 events read in total (14361ms).
[17:25:05.591] <TB2> INFO: Expecting 655360 events.
[17:25:20.155] <TB2> INFO: 655360 events read in total (14161ms).
[17:25:20.218] <TB2> INFO: Expecting 655360 events.
[17:25:34.902] <TB2> INFO: 655360 events read in total (14281ms).
[17:25:34.995] <TB2> INFO: Expecting 655360 events.
[17:25:49.575] <TB2> INFO: 655360 events read in total (14177ms).
[17:25:49.734] <TB2> INFO: Expecting 655360 events.
[17:26:04.274] <TB2> INFO: 655360 events read in total (14137ms).
[17:26:04.426] <TB2> INFO: Expecting 655360 events.
[17:26:18.887] <TB2> INFO: 655360 events read in total (14058ms).
[17:26:19.065] <TB2> INFO: Test took 235392ms.
[17:26:19.162] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:26:19.419] <TB2> INFO: Expecting 655360 events.
[17:26:33.992] <TB2> INFO: 655360 events read in total (13981ms).
[17:26:34.004] <TB2> INFO: Expecting 655360 events.
[17:26:48.516] <TB2> INFO: 655360 events read in total (14109ms).
[17:26:48.537] <TB2> INFO: Expecting 655360 events.
[17:27:02.787] <TB2> INFO: 655360 events read in total (13847ms).
[17:27:02.808] <TB2> INFO: Expecting 655360 events.
[17:27:17.253] <TB2> INFO: 655360 events read in total (14042ms).
[17:27:17.278] <TB2> INFO: Expecting 655360 events.
[17:27:31.532] <TB2> INFO: 655360 events read in total (13850ms).
[17:27:31.560] <TB2> INFO: Expecting 655360 events.
[17:27:46.174] <TB2> INFO: 655360 events read in total (14211ms).
[17:27:46.211] <TB2> INFO: Expecting 655360 events.
[17:28:00.748] <TB2> INFO: 655360 events read in total (14134ms).
[17:28:00.796] <TB2> INFO: Expecting 655360 events.
[17:28:15.080] <TB2> INFO: 655360 events read in total (13880ms).
[17:28:15.123] <TB2> INFO: Expecting 655360 events.
[17:28:29.621] <TB2> INFO: 655360 events read in total (14095ms).
[17:28:29.670] <TB2> INFO: Expecting 655360 events.
[17:28:44.215] <TB2> INFO: 655360 events read in total (14141ms).
[17:28:44.265] <TB2> INFO: Expecting 655360 events.
[17:28:58.818] <TB2> INFO: 655360 events read in total (14150ms).
[17:28:58.949] <TB2> INFO: Expecting 655360 events.
[17:29:13.481] <TB2> INFO: 655360 events read in total (14129ms).
[17:29:13.545] <TB2> INFO: Expecting 655360 events.
[17:29:28.220] <TB2> INFO: 655360 events read in total (14272ms).
[17:29:28.351] <TB2> INFO: Expecting 655360 events.
[17:29:42.895] <TB2> INFO: 655360 events read in total (14141ms).
[17:29:43.019] <TB2> INFO: Expecting 655360 events.
[17:29:57.678] <TB2> INFO: 655360 events read in total (14256ms).
[17:29:57.821] <TB2> INFO: Expecting 655360 events.
[17:30:12.696] <TB2> INFO: 655360 events read in total (14472ms).
[17:30:12.850] <TB2> INFO: Test took 233688ms.
[17:30:13.019] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.026] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:30:13.031] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[17:30:13.037] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[17:30:13.043] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[17:30:13.049] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[17:30:13.054] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[17:30:13.060] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.066] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.071] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:30:13.077] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[17:30:13.083] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[17:30:13.088] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.094] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:30:13.100] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[17:30:13.106] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.112] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.118] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:30:13.123] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[17:30:13.130] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[17:30:13.136] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[17:30:13.142] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.148] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.154] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.160] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.167] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.172] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:30:13.179] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[17:30:13.185] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[17:30:13.191] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[17:30:13.197] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.203] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.209] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.216] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.222] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:30:13.260] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C0.dat
[17:30:13.260] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C1.dat
[17:30:13.260] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C2.dat
[17:30:13.260] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C3.dat
[17:30:13.260] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C4.dat
[17:30:13.260] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C5.dat
[17:30:13.261] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C6.dat
[17:30:13.261] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C7.dat
[17:30:13.261] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C8.dat
[17:30:13.261] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C9.dat
[17:30:13.261] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C10.dat
[17:30:13.261] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C11.dat
[17:30:13.261] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C12.dat
[17:30:13.262] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C13.dat
[17:30:13.262] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C14.dat
[17:30:13.262] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//dacParameters35_C15.dat
[17:30:13.508] <TB2> INFO: Expecting 41600 events.
[17:30:16.684] <TB2> INFO: 41600 events read in total (2584ms).
[17:30:16.685] <TB2> INFO: Test took 3419ms.
[17:30:17.148] <TB2> INFO: Expecting 41600 events.
[17:30:20.252] <TB2> INFO: 41600 events read in total (2512ms).
[17:30:20.253] <TB2> INFO: Test took 3352ms.
[17:30:20.705] <TB2> INFO: Expecting 41600 events.
[17:30:23.851] <TB2> INFO: 41600 events read in total (2554ms).
[17:30:23.851] <TB2> INFO: Test took 3386ms.
[17:30:24.067] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:24.156] <TB2> INFO: Expecting 2560 events.
[17:30:25.049] <TB2> INFO: 2560 events read in total (302ms).
[17:30:25.049] <TB2> INFO: Test took 982ms.
[17:30:25.053] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:25.357] <TB2> INFO: Expecting 2560 events.
[17:30:26.250] <TB2> INFO: 2560 events read in total (301ms).
[17:30:26.250] <TB2> INFO: Test took 1197ms.
[17:30:26.253] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:26.558] <TB2> INFO: Expecting 2560 events.
[17:30:27.443] <TB2> INFO: 2560 events read in total (293ms).
[17:30:27.444] <TB2> INFO: Test took 1191ms.
[17:30:27.447] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:27.752] <TB2> INFO: Expecting 2560 events.
[17:30:28.648] <TB2> INFO: 2560 events read in total (304ms).
[17:30:28.648] <TB2> INFO: Test took 1201ms.
[17:30:28.651] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:28.956] <TB2> INFO: Expecting 2560 events.
[17:30:29.849] <TB2> INFO: 2560 events read in total (301ms).
[17:30:29.850] <TB2> INFO: Test took 1199ms.
[17:30:29.852] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:30.157] <TB2> INFO: Expecting 2560 events.
[17:30:31.045] <TB2> INFO: 2560 events read in total (296ms).
[17:30:31.045] <TB2> INFO: Test took 1193ms.
[17:30:31.049] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:31.354] <TB2> INFO: Expecting 2560 events.
[17:30:32.245] <TB2> INFO: 2560 events read in total (299ms).
[17:30:32.245] <TB2> INFO: Test took 1196ms.
[17:30:32.250] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:32.554] <TB2> INFO: Expecting 2560 events.
[17:30:33.438] <TB2> INFO: 2560 events read in total (292ms).
[17:30:33.439] <TB2> INFO: Test took 1189ms.
[17:30:33.441] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:33.747] <TB2> INFO: Expecting 2560 events.
[17:30:34.635] <TB2> INFO: 2560 events read in total (296ms).
[17:30:34.636] <TB2> INFO: Test took 1195ms.
[17:30:34.640] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:34.944] <TB2> INFO: Expecting 2560 events.
[17:30:35.831] <TB2> INFO: 2560 events read in total (296ms).
[17:30:35.831] <TB2> INFO: Test took 1191ms.
[17:30:35.833] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:36.140] <TB2> INFO: Expecting 2560 events.
[17:30:37.019] <TB2> INFO: 2560 events read in total (288ms).
[17:30:37.019] <TB2> INFO: Test took 1186ms.
[17:30:37.021] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:37.328] <TB2> INFO: Expecting 2560 events.
[17:30:38.213] <TB2> INFO: 2560 events read in total (293ms).
[17:30:38.213] <TB2> INFO: Test took 1192ms.
[17:30:38.215] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:38.522] <TB2> INFO: Expecting 2560 events.
[17:30:39.402] <TB2> INFO: 2560 events read in total (288ms).
[17:30:39.403] <TB2> INFO: Test took 1188ms.
[17:30:39.405] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:39.712] <TB2> INFO: Expecting 2560 events.
[17:30:40.598] <TB2> INFO: 2560 events read in total (294ms).
[17:30:40.599] <TB2> INFO: Test took 1194ms.
[17:30:40.601] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:40.906] <TB2> INFO: Expecting 2560 events.
[17:30:41.801] <TB2> INFO: 2560 events read in total (304ms).
[17:30:41.801] <TB2> INFO: Test took 1200ms.
[17:30:41.805] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:42.110] <TB2> INFO: Expecting 2560 events.
[17:30:42.001] <TB2> INFO: 2560 events read in total (299ms).
[17:30:42.002] <TB2> INFO: Test took 1197ms.
[17:30:43.005] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:43.309] <TB2> INFO: Expecting 2560 events.
[17:30:44.200] <TB2> INFO: 2560 events read in total (299ms).
[17:30:44.200] <TB2> INFO: Test took 1195ms.
[17:30:44.203] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:44.508] <TB2> INFO: Expecting 2560 events.
[17:30:45.393] <TB2> INFO: 2560 events read in total (293ms).
[17:30:45.394] <TB2> INFO: Test took 1191ms.
[17:30:45.398] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:45.702] <TB2> INFO: Expecting 2560 events.
[17:30:46.592] <TB2> INFO: 2560 events read in total (298ms).
[17:30:46.593] <TB2> INFO: Test took 1195ms.
[17:30:46.597] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:46.901] <TB2> INFO: Expecting 2560 events.
[17:30:47.789] <TB2> INFO: 2560 events read in total (296ms).
[17:30:47.789] <TB2> INFO: Test took 1192ms.
[17:30:47.792] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:48.097] <TB2> INFO: Expecting 2560 events.
[17:30:48.975] <TB2> INFO: 2560 events read in total (286ms).
[17:30:48.975] <TB2> INFO: Test took 1183ms.
[17:30:48.978] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:49.284] <TB2> INFO: Expecting 2560 events.
[17:30:50.169] <TB2> INFO: 2560 events read in total (293ms).
[17:30:50.169] <TB2> INFO: Test took 1192ms.
[17:30:50.173] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:50.478] <TB2> INFO: Expecting 2560 events.
[17:30:51.359] <TB2> INFO: 2560 events read in total (290ms).
[17:30:51.359] <TB2> INFO: Test took 1187ms.
[17:30:51.362] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:51.668] <TB2> INFO: Expecting 2560 events.
[17:30:52.553] <TB2> INFO: 2560 events read in total (293ms).
[17:30:52.553] <TB2> INFO: Test took 1191ms.
[17:30:52.556] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:52.862] <TB2> INFO: Expecting 2560 events.
[17:30:53.752] <TB2> INFO: 2560 events read in total (298ms).
[17:30:53.754] <TB2> INFO: Test took 1198ms.
[17:30:53.756] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:54.061] <TB2> INFO: Expecting 2560 events.
[17:30:54.953] <TB2> INFO: 2560 events read in total (300ms).
[17:30:54.953] <TB2> INFO: Test took 1197ms.
[17:30:54.958] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:55.262] <TB2> INFO: Expecting 2560 events.
[17:30:56.153] <TB2> INFO: 2560 events read in total (299ms).
[17:30:56.153] <TB2> INFO: Test took 1196ms.
[17:30:56.157] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:56.462] <TB2> INFO: Expecting 2560 events.
[17:30:57.356] <TB2> INFO: 2560 events read in total (302ms).
[17:30:57.356] <TB2> INFO: Test took 1199ms.
[17:30:57.360] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:57.664] <TB2> INFO: Expecting 2560 events.
[17:30:58.558] <TB2> INFO: 2560 events read in total (302ms).
[17:30:58.559] <TB2> INFO: Test took 1199ms.
[17:30:58.564] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:30:58.867] <TB2> INFO: Expecting 2560 events.
[17:30:59.761] <TB2> INFO: 2560 events read in total (304ms).
[17:30:59.762] <TB2> INFO: Test took 1199ms.
[17:30:59.765] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:31:00.070] <TB2> INFO: Expecting 2560 events.
[17:31:00.965] <TB2> INFO: 2560 events read in total (303ms).
[17:31:00.966] <TB2> INFO: Test took 1202ms.
[17:31:00.969] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:31:01.273] <TB2> INFO: Expecting 2560 events.
[17:31:02.158] <TB2> INFO: 2560 events read in total (294ms).
[17:31:02.158] <TB2> INFO: Test took 1190ms.
[17:31:02.639] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 649 seconds
[17:31:02.639] <TB2> INFO: PH scale (per ROC): 61 61 65 45 49 54 59 38 59 46 58 42 48 40 37 47
[17:31:02.639] <TB2> INFO: PH offset (per ROC): 128 129 122 111 101 112 130 103 128 103 109 100 127 102 100 93
[17:31:02.648] <TB2> INFO: Decoding statistics:
[17:31:02.648] <TB2> INFO: General information:
[17:31:02.648] <TB2> INFO: 16bit words read: 127882
[17:31:02.648] <TB2> INFO: valid events total: 20480
[17:31:02.648] <TB2> INFO: empty events: 17979
[17:31:02.648] <TB2> INFO: valid events with pixels: 2501
[17:31:02.648] <TB2> INFO: valid pixel hits: 2501
[17:31:02.648] <TB2> INFO: Event errors: 0
[17:31:02.648] <TB2> INFO: start marker: 0
[17:31:02.648] <TB2> INFO: stop marker: 0
[17:31:02.648] <TB2> INFO: overflow: 0
[17:31:02.648] <TB2> INFO: invalid 5bit words: 0
[17:31:02.648] <TB2> INFO: invalid XOR eye diagram: 0
[17:31:02.648] <TB2> INFO: frame (failed synchr.): 0
[17:31:02.648] <TB2> INFO: idle data (no TBM trl): 0
[17:31:02.648] <TB2> INFO: no data (only TBM hdr): 0
[17:31:02.648] <TB2> INFO: TBM errors: 0
[17:31:02.648] <TB2> INFO: flawed TBM headers: 0
[17:31:02.648] <TB2> INFO: flawed TBM trailers: 0
[17:31:02.648] <TB2> INFO: event ID mismatches: 0
[17:31:02.648] <TB2> INFO: ROC errors: 0
[17:31:02.648] <TB2> INFO: missing ROC header(s): 0
[17:31:02.648] <TB2> INFO: misplaced readback start: 0
[17:31:02.648] <TB2> INFO: Pixel decoding errors: 0
[17:31:02.648] <TB2> INFO: pixel data incomplete: 0
[17:31:02.648] <TB2> INFO: pixel address: 0
[17:31:02.648] <TB2> INFO: pulse height fill bit: 0
[17:31:02.648] <TB2> INFO: buffer corruption: 0
[17:31:02.807] <TB2> INFO: ######################################################################
[17:31:02.807] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[17:31:02.807] <TB2> INFO: ######################################################################
[17:31:02.821] <TB2> INFO: scanning low vcal = 10
[17:31:03.059] <TB2> INFO: Expecting 41600 events.
[17:31:06.622] <TB2> INFO: 41600 events read in total (2971ms).
[17:31:06.623] <TB2> INFO: Test took 3801ms.
[17:31:06.625] <TB2> INFO: scanning low vcal = 20
[17:31:06.923] <TB2> INFO: Expecting 41600 events.
[17:31:10.510] <TB2> INFO: 41600 events read in total (2996ms).
[17:31:10.510] <TB2> INFO: Test took 3885ms.
[17:31:10.512] <TB2> INFO: scanning low vcal = 30
[17:31:10.804] <TB2> INFO: Expecting 41600 events.
[17:31:14.478] <TB2> INFO: 41600 events read in total (3083ms).
[17:31:14.479] <TB2> INFO: Test took 3966ms.
[17:31:14.482] <TB2> INFO: scanning low vcal = 40
[17:31:14.759] <TB2> INFO: Expecting 41600 events.
[17:31:18.737] <TB2> INFO: 41600 events read in total (3387ms).
[17:31:18.738] <TB2> INFO: Test took 4256ms.
[17:31:18.742] <TB2> INFO: scanning low vcal = 50
[17:31:19.019] <TB2> INFO: Expecting 41600 events.
[17:31:23.042] <TB2> INFO: 41600 events read in total (3432ms).
[17:31:23.043] <TB2> INFO: Test took 4301ms.
[17:31:23.047] <TB2> INFO: scanning low vcal = 60
[17:31:23.324] <TB2> INFO: Expecting 41600 events.
[17:31:27.344] <TB2> INFO: 41600 events read in total (3428ms).
[17:31:27.345] <TB2> INFO: Test took 4298ms.
[17:31:27.348] <TB2> INFO: scanning low vcal = 70
[17:31:27.625] <TB2> INFO: Expecting 41600 events.
[17:31:31.646] <TB2> INFO: 41600 events read in total (3429ms).
[17:31:31.647] <TB2> INFO: Test took 4299ms.
[17:31:31.651] <TB2> INFO: scanning low vcal = 80
[17:31:31.928] <TB2> INFO: Expecting 41600 events.
[17:31:35.919] <TB2> INFO: 41600 events read in total (3399ms).
[17:31:35.920] <TB2> INFO: Test took 4269ms.
[17:31:35.924] <TB2> INFO: scanning low vcal = 90
[17:31:36.201] <TB2> INFO: Expecting 41600 events.
[17:31:40.178] <TB2> INFO: 41600 events read in total (3385ms).
[17:31:40.179] <TB2> INFO: Test took 4255ms.
[17:31:40.183] <TB2> INFO: scanning low vcal = 100
[17:31:40.460] <TB2> INFO: Expecting 41600 events.
[17:31:44.438] <TB2> INFO: 41600 events read in total (3387ms).
[17:31:44.439] <TB2> INFO: Test took 4256ms.
[17:31:44.443] <TB2> INFO: scanning low vcal = 110
[17:31:44.719] <TB2> INFO: Expecting 41600 events.
[17:31:48.747] <TB2> INFO: 41600 events read in total (3436ms).
[17:31:48.748] <TB2> INFO: Test took 4305ms.
[17:31:48.751] <TB2> INFO: scanning low vcal = 120
[17:31:49.029] <TB2> INFO: Expecting 41600 events.
[17:31:53.036] <TB2> INFO: 41600 events read in total (3415ms).
[17:31:53.037] <TB2> INFO: Test took 4286ms.
[17:31:53.040] <TB2> INFO: scanning low vcal = 130
[17:31:53.317] <TB2> INFO: Expecting 41600 events.
[17:31:57.273] <TB2> INFO: 41600 events read in total (3364ms).
[17:31:57.274] <TB2> INFO: Test took 4234ms.
[17:31:57.278] <TB2> INFO: scanning low vcal = 140
[17:31:57.554] <TB2> INFO: Expecting 41600 events.
[17:32:01.486] <TB2> INFO: 41600 events read in total (3340ms).
[17:32:01.487] <TB2> INFO: Test took 4208ms.
[17:32:01.491] <TB2> INFO: scanning low vcal = 150
[17:32:01.767] <TB2> INFO: Expecting 41600 events.
[17:32:05.730] <TB2> INFO: 41600 events read in total (3372ms).
[17:32:05.731] <TB2> INFO: Test took 4240ms.
[17:32:05.735] <TB2> INFO: scanning low vcal = 160
[17:32:06.011] <TB2> INFO: Expecting 41600 events.
[17:32:09.949] <TB2> INFO: 41600 events read in total (3346ms).
[17:32:09.950] <TB2> INFO: Test took 4215ms.
[17:32:09.954] <TB2> INFO: scanning low vcal = 170
[17:32:10.230] <TB2> INFO: Expecting 41600 events.
[17:32:14.174] <TB2> INFO: 41600 events read in total (3352ms).
[17:32:14.175] <TB2> INFO: Test took 4221ms.
[17:32:14.180] <TB2> INFO: scanning low vcal = 180
[17:32:14.455] <TB2> INFO: Expecting 41600 events.
[17:32:18.389] <TB2> INFO: 41600 events read in total (3343ms).
[17:32:18.390] <TB2> INFO: Test took 4210ms.
[17:32:18.393] <TB2> INFO: scanning low vcal = 190
[17:32:18.670] <TB2> INFO: Expecting 41600 events.
[17:32:22.628] <TB2> INFO: 41600 events read in total (3367ms).
[17:32:22.629] <TB2> INFO: Test took 4236ms.
[17:32:22.632] <TB2> INFO: scanning low vcal = 200
[17:32:22.909] <TB2> INFO: Expecting 41600 events.
[17:32:26.850] <TB2> INFO: 41600 events read in total (3350ms).
[17:32:26.851] <TB2> INFO: Test took 4219ms.
[17:32:26.855] <TB2> INFO: scanning low vcal = 210
[17:32:27.131] <TB2> INFO: Expecting 41600 events.
[17:32:31.248] <TB2> INFO: 41600 events read in total (3525ms).
[17:32:31.249] <TB2> INFO: Test took 4394ms.
[17:32:31.252] <TB2> INFO: scanning low vcal = 220
[17:32:31.529] <TB2> INFO: Expecting 41600 events.
[17:32:35.583] <TB2> INFO: 41600 events read in total (3462ms).
[17:32:35.584] <TB2> INFO: Test took 4332ms.
[17:32:35.588] <TB2> INFO: scanning low vcal = 230
[17:32:35.884] <TB2> INFO: Expecting 41600 events.
[17:32:39.919] <TB2> INFO: 41600 events read in total (3443ms).
[17:32:39.920] <TB2> INFO: Test took 4332ms.
[17:32:39.923] <TB2> INFO: scanning low vcal = 240
[17:32:40.200] <TB2> INFO: Expecting 41600 events.
[17:32:44.187] <TB2> INFO: 41600 events read in total (3395ms).
[17:32:44.188] <TB2> INFO: Test took 4264ms.
[17:32:44.191] <TB2> INFO: scanning low vcal = 250
[17:32:44.468] <TB2> INFO: Expecting 41600 events.
[17:32:48.432] <TB2> INFO: 41600 events read in total (3373ms).
[17:32:48.433] <TB2> INFO: Test took 4242ms.
[17:32:48.437] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[17:32:48.713] <TB2> INFO: Expecting 41600 events.
[17:32:52.687] <TB2> INFO: 41600 events read in total (3383ms).
[17:32:52.688] <TB2> INFO: Test took 4250ms.
[17:32:52.691] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[17:32:52.967] <TB2> INFO: Expecting 41600 events.
[17:32:56.986] <TB2> INFO: 41600 events read in total (3427ms).
[17:32:56.986] <TB2> INFO: Test took 4295ms.
[17:32:56.990] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[17:32:57.266] <TB2> INFO: Expecting 41600 events.
[17:33:01.276] <TB2> INFO: 41600 events read in total (3418ms).
[17:33:01.276] <TB2> INFO: Test took 4286ms.
[17:33:01.281] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[17:33:01.556] <TB2> INFO: Expecting 41600 events.
[17:33:05.565] <TB2> INFO: 41600 events read in total (3419ms).
[17:33:05.566] <TB2> INFO: Test took 4284ms.
[17:33:05.570] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[17:33:05.846] <TB2> INFO: Expecting 41600 events.
[17:33:09.832] <TB2> INFO: 41600 events read in total (3395ms).
[17:33:09.832] <TB2> INFO: Test took 4262ms.
[17:33:10.236] <TB2> INFO: PixTestGainPedestal::measure() done
[17:33:42.929] <TB2> INFO: PixTestGainPedestal::fit() done
[17:33:42.929] <TB2> INFO: non-linearity mean: 0.981 0.979 0.983 0.912 0.943 0.945 0.979 0.934 0.982 0.925 0.967 0.923 0.976 0.940 1.042 0.921
[17:33:42.929] <TB2> INFO: non-linearity RMS: 0.003 0.004 0.002 0.109 0.057 0.062 0.004 0.209 0.004 0.090 0.027 0.059 0.004 0.169 0.183 0.104
[17:33:42.929] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[17:33:42.943] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[17:33:42.956] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[17:33:42.968] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[17:33:42.981] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[17:33:42.994] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[17:33:43.007] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[17:33:43.020] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[17:33:43.033] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[17:33:43.047] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[17:33:43.060] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[17:33:43.073] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[17:33:43.087] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[17:33:43.100] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[17:33:43.114] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[17:33:43.128] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[17:33:43.141] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 160 seconds
[17:33:43.141] <TB2> INFO: Decoding statistics:
[17:33:43.141] <TB2> INFO: General information:
[17:33:43.141] <TB2> INFO: 16bit words read: 3327958
[17:33:43.141] <TB2> INFO: valid events total: 332800
[17:33:43.141] <TB2> INFO: empty events: 0
[17:33:43.141] <TB2> INFO: valid events with pixels: 332800
[17:33:43.141] <TB2> INFO: valid pixel hits: 665579
[17:33:43.141] <TB2> INFO: Event errors: 0
[17:33:43.141] <TB2> INFO: start marker: 0
[17:33:43.141] <TB2> INFO: stop marker: 0
[17:33:43.141] <TB2> INFO: overflow: 0
[17:33:43.141] <TB2> INFO: invalid 5bit words: 0
[17:33:43.141] <TB2> INFO: invalid XOR eye diagram: 0
[17:33:43.141] <TB2> INFO: frame (failed synchr.): 0
[17:33:43.141] <TB2> INFO: idle data (no TBM trl): 0
[17:33:43.141] <TB2> INFO: no data (only TBM hdr): 0
[17:33:43.141] <TB2> INFO: TBM errors: 0
[17:33:43.141] <TB2> INFO: flawed TBM headers: 0
[17:33:43.141] <TB2> INFO: flawed TBM trailers: 0
[17:33:43.141] <TB2> INFO: event ID mismatches: 0
[17:33:43.141] <TB2> INFO: ROC errors: 0
[17:33:43.141] <TB2> INFO: missing ROC header(s): 0
[17:33:43.141] <TB2> INFO: misplaced readback start: 0
[17:33:43.141] <TB2> INFO: Pixel decoding errors: 0
[17:33:43.141] <TB2> INFO: pixel data incomplete: 0
[17:33:43.141] <TB2> INFO: pixel address: 0
[17:33:43.141] <TB2> INFO: pulse height fill bit: 0
[17:33:43.141] <TB2> INFO: buffer corruption: 0
[17:33:43.159] <TB2> INFO: Decoding statistics:
[17:33:43.159] <TB2> INFO: General information:
[17:33:43.159] <TB2> INFO: 16bit words read: 3457376
[17:33:43.159] <TB2> INFO: valid events total: 353536
[17:33:43.159] <TB2> INFO: empty events: 18235
[17:33:43.159] <TB2> INFO: valid events with pixels: 335301
[17:33:43.159] <TB2> INFO: valid pixel hits: 668080
[17:33:43.159] <TB2> INFO: Event errors: 0
[17:33:43.159] <TB2> INFO: start marker: 0
[17:33:43.159] <TB2> INFO: stop marker: 0
[17:33:43.159] <TB2> INFO: overflow: 0
[17:33:43.159] <TB2> INFO: invalid 5bit words: 0
[17:33:43.159] <TB2> INFO: invalid XOR eye diagram: 0
[17:33:43.159] <TB2> INFO: frame (failed synchr.): 0
[17:33:43.159] <TB2> INFO: idle data (no TBM trl): 0
[17:33:43.159] <TB2> INFO: no data (only TBM hdr): 0
[17:33:43.159] <TB2> INFO: TBM errors: 0
[17:33:43.159] <TB2> INFO: flawed TBM headers: 0
[17:33:43.159] <TB2> INFO: flawed TBM trailers: 0
[17:33:43.159] <TB2> INFO: event ID mismatches: 0
[17:33:43.159] <TB2> INFO: ROC errors: 0
[17:33:43.159] <TB2> INFO: missing ROC header(s): 0
[17:33:43.159] <TB2> INFO: misplaced readback start: 0
[17:33:43.159] <TB2> INFO: Pixel decoding errors: 0
[17:33:43.159] <TB2> INFO: pixel data incomplete: 0
[17:33:43.159] <TB2> INFO: pixel address: 0
[17:33:43.159] <TB2> INFO: pulse height fill bit: 0
[17:33:43.159] <TB2> INFO: buffer corruption: 0
[17:33:43.159] <TB2> INFO: enter test to run
[17:33:43.159] <TB2> INFO: test: exit no parameter change
[17:33:43.290] <TB2> QUIET: Connection to board 149 closed.
[17:33:43.291] <TB2> INFO: pXar: this is the end, my friend