[17:45:01.823] <TB2> INFO: *** Welcome to pxar ***
[17:45:01.823] <TB2> INFO: *** Today: 2016/11/02
[17:45:01.830] <TB2> INFO: *** Version: c8ba-dirty
[17:45:01.830] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C15.dat
[17:45:01.831] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[17:45:01.831] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//defaultMaskFile.dat
[17:45:01.831] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters_C15.dat
[17:45:01.926] <TB2> INFO: clk: 4
[17:45:01.926] <TB2> INFO: ctr: 4
[17:45:01.926] <TB2> INFO: sda: 19
[17:45:01.926] <TB2> INFO: tin: 9
[17:45:01.926] <TB2> INFO: level: 15
[17:45:01.926] <TB2> INFO: triggerdelay: 0
[17:45:01.926] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[17:45:01.926] <TB2> INFO: Log level: INFO
[17:45:01.936] <TB2> INFO: Found DTB DTB_WWXUD2
[17:45:01.943] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[17:45:01.945] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
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[17:45:01.947] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[17:45:03.495] <TB2> INFO: DUT info:
[17:45:03.495] <TB2> INFO: The DUT currently contains the following objects:
[17:45:03.495] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[17:45:03.495] <TB2> INFO: TBM Core alpha (0): 7 registers set
[17:45:03.496] <TB2> INFO: TBM Core beta (1): 7 registers set
[17:45:03.496] <TB2> INFO: TBM Core alpha (2): 7 registers set
[17:45:03.496] <TB2> INFO: TBM Core beta (3): 7 registers set
[17:45:03.496] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[17:45:03.496] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.496] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[17:45:03.897] <TB2> INFO: enter 'restricted' command line mode
[17:45:03.897] <TB2> INFO: enter test to run
[17:45:03.897] <TB2> INFO: test: pretest no parameter change
[17:45:03.898] <TB2> INFO: running: pretest
[17:45:03.904] <TB2> INFO: ######################################################################
[17:45:03.904] <TB2> INFO: PixTestPretest::doTest()
[17:45:03.904] <TB2> INFO: ######################################################################
[17:45:03.906] <TB2> INFO: ----------------------------------------------------------------------
[17:45:03.906] <TB2> INFO: PixTestPretest::programROC()
[17:45:03.906] <TB2> INFO: ----------------------------------------------------------------------
[17:45:21.920] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[17:45:21.920] <TB2> INFO: IA differences per ROC: 17.7 19.3 19.3 17.7 18.5 20.1 18.5 19.3 20.1 20.1 20.1 20.9 20.1 20.1 20.1 20.9
[17:45:21.983] <TB2> INFO: ----------------------------------------------------------------------
[17:45:21.984] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[17:45:21.984] <TB2> INFO: ----------------------------------------------------------------------
[17:45:43.270] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 379.4 mA = 23.7125 mA/ROC
[17:45:43.270] <TB2> INFO: i(loss) [mA/ROC]: 19.3 20.1 19.3 18.4 20.9 19.3 19.3 19.3 19.3 19.3 19.3 19.3 20.1 19.3 19.3 19.3
[17:45:43.304] <TB2> INFO: ----------------------------------------------------------------------
[17:45:43.304] <TB2> INFO: PixTestPretest::findTiming()
[17:45:43.304] <TB2> INFO: ----------------------------------------------------------------------
[17:45:43.305] <TB2> INFO: PixTestCmd::init()

[17:46:15.241] <TB2> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[17:46:15.241] <TB2> INFO: (success/tries = 100/100), width = 3
[17:46:16.747] <TB2> INFO: ----------------------------------------------------------------------
[17:46:16.748] <TB2> INFO: PixTestPretest::findWorkingPixel()
[17:46:16.748] <TB2> INFO: ----------------------------------------------------------------------
[17:46:16.843] <TB2> INFO: Expecting 231680 events.
[17:46:26.851] <TB2> INFO: 231680 events read in total (9417ms).
[17:46:26.861] <TB2> INFO: Test took 10108ms.
[17:46:27.108] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[17:46:27.142] <TB2> INFO: ----------------------------------------------------------------------
[17:46:27.142] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[17:46:27.142] <TB2> INFO: ----------------------------------------------------------------------
[17:46:27.238] <TB2> INFO: Expecting 231680 events.
[17:46:37.242] <TB2> INFO: 231680 events read in total (9413ms).
[17:46:37.255] <TB2> INFO: Test took 10107ms.
[17:46:37.522] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[17:46:37.522] <TB2> INFO: CalDel: 82 93 81 83 82 93 93 88 95 82 80 95 99 88 93 82
[17:46:37.522] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[17:46:37.527] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C0.dat
[17:46:37.527] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C1.dat
[17:46:37.527] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C2.dat
[17:46:37.528] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C3.dat
[17:46:37.528] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C4.dat
[17:46:37.528] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C5.dat
[17:46:37.528] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C6.dat
[17:46:37.528] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C7.dat
[17:46:37.529] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C8.dat
[17:46:37.529] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C9.dat
[17:46:37.529] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C10.dat
[17:46:37.529] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C11.dat
[17:46:37.529] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C12.dat
[17:46:37.529] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C13.dat
[17:46:37.530] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C14.dat
[17:46:37.530] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters_C15.dat
[17:46:37.530] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[17:46:37.530] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[17:46:37.530] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[17:46:37.530] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[17:46:37.531] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[17:46:37.582] <TB2> INFO: enter test to run
[17:46:37.582] <TB2> INFO: test: fulltest no parameter change
[17:46:37.582] <TB2> INFO: running: fulltest
[17:46:37.582] <TB2> INFO: ######################################################################
[17:46:37.582] <TB2> INFO: PixTestFullTest::doTest()
[17:46:37.582] <TB2> INFO: ######################################################################
[17:46:37.583] <TB2> INFO: ######################################################################
[17:46:37.584] <TB2> INFO: PixTestAlive::doTest()
[17:46:37.584] <TB2> INFO: ######################################################################
[17:46:37.585] <TB2> INFO: ----------------------------------------------------------------------
[17:46:37.585] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[17:46:37.585] <TB2> INFO: ----------------------------------------------------------------------
[17:46:37.827] <TB2> INFO: Expecting 41600 events.
[17:46:41.458] <TB2> INFO: 41600 events read in total (3040ms).
[17:46:41.458] <TB2> INFO: Test took 3872ms.
[17:46:41.691] <TB2> INFO: PixTestAlive::aliveTest() done
[17:46:41.691] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[17:46:41.693] <TB2> INFO: ----------------------------------------------------------------------
[17:46:41.693] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[17:46:41.693] <TB2> INFO: ----------------------------------------------------------------------
[17:46:41.937] <TB2> INFO: Expecting 41600 events.
[17:46:44.947] <TB2> INFO: 41600 events read in total (2418ms).
[17:46:44.947] <TB2> INFO: Test took 3252ms.
[17:46:44.948] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[17:46:45.184] <TB2> INFO: PixTestAlive::maskTest() done
[17:46:45.184] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[17:46:45.185] <TB2> INFO: ----------------------------------------------------------------------
[17:46:45.185] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[17:46:45.185] <TB2> INFO: ----------------------------------------------------------------------
[17:46:45.428] <TB2> INFO: Expecting 41600 events.
[17:46:48.976] <TB2> INFO: 41600 events read in total (2956ms).
[17:46:48.976] <TB2> INFO: Test took 3788ms.
[17:46:49.211] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[17:46:49.211] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[17:46:49.212] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[17:46:49.212] <TB2> INFO: Decoding statistics:
[17:46:49.212] <TB2> INFO: General information:
[17:46:49.212] <TB2> INFO: 16bit words read: 0
[17:46:49.212] <TB2> INFO: valid events total: 0
[17:46:49.212] <TB2> INFO: empty events: 0
[17:46:49.212] <TB2> INFO: valid events with pixels: 0
[17:46:49.212] <TB2> INFO: valid pixel hits: 0
[17:46:49.212] <TB2> INFO: Event errors: 0
[17:46:49.212] <TB2> INFO: start marker: 0
[17:46:49.212] <TB2> INFO: stop marker: 0
[17:46:49.212] <TB2> INFO: overflow: 0
[17:46:49.212] <TB2> INFO: invalid 5bit words: 0
[17:46:49.212] <TB2> INFO: invalid XOR eye diagram: 0
[17:46:49.212] <TB2> INFO: frame (failed synchr.): 0
[17:46:49.212] <TB2> INFO: idle data (no TBM trl): 0
[17:46:49.212] <TB2> INFO: no data (only TBM hdr): 0
[17:46:49.212] <TB2> INFO: TBM errors: 0
[17:46:49.212] <TB2> INFO: flawed TBM headers: 0
[17:46:49.212] <TB2> INFO: flawed TBM trailers: 0
[17:46:49.212] <TB2> INFO: event ID mismatches: 0
[17:46:49.212] <TB2> INFO: ROC errors: 0
[17:46:49.212] <TB2> INFO: missing ROC header(s): 0
[17:46:49.212] <TB2> INFO: misplaced readback start: 0
[17:46:49.212] <TB2> INFO: Pixel decoding errors: 0
[17:46:49.212] <TB2> INFO: pixel data incomplete: 0
[17:46:49.212] <TB2> INFO: pixel address: 0
[17:46:49.212] <TB2> INFO: pulse height fill bit: 0
[17:46:49.212] <TB2> INFO: buffer corruption: 0
[17:46:49.220] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C15.dat
[17:46:49.220] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[17:46:49.220] <TB2> INFO: ######################################################################
[17:46:49.220] <TB2> INFO: PixTestReadback::doTest()
[17:46:49.220] <TB2> INFO: ######################################################################
[17:46:49.220] <TB2> INFO: ----------------------------------------------------------------------
[17:46:49.220] <TB2> INFO: PixTestReadback::CalibrateVd()
[17:46:49.220] <TB2> INFO: ----------------------------------------------------------------------
[17:46:59.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C0.dat
[17:46:59.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C1.dat
[17:46:59.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C2.dat
[17:46:59.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C3.dat
[17:46:59.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C4.dat
[17:46:59.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C5.dat
[17:46:59.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C6.dat
[17:46:59.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C7.dat
[17:46:59.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C8.dat
[17:46:59.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C9.dat
[17:46:59.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C10.dat
[17:46:59.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C11.dat
[17:46:59.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C12.dat
[17:46:59.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C13.dat
[17:46:59.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C14.dat
[17:46:59.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C15.dat
[17:46:59.244] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[17:46:59.244] <TB2> INFO: ----------------------------------------------------------------------
[17:46:59.244] <TB2> INFO: PixTestReadback::CalibrateVa()
[17:46:59.244] <TB2> INFO: ----------------------------------------------------------------------
[17:47:09.193] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C0.dat
[17:47:09.193] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C1.dat
[17:47:09.193] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C2.dat
[17:47:09.193] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C3.dat
[17:47:09.194] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C4.dat
[17:47:09.194] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C5.dat
[17:47:09.194] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C6.dat
[17:47:09.194] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C7.dat
[17:47:09.194] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C8.dat
[17:47:09.194] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C9.dat
[17:47:09.194] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C10.dat
[17:47:09.194] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C11.dat
[17:47:09.194] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C12.dat
[17:47:09.194] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C13.dat
[17:47:09.194] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C14.dat
[17:47:09.194] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C15.dat
[17:47:09.226] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[17:47:09.226] <TB2> INFO: ----------------------------------------------------------------------
[17:47:09.226] <TB2> INFO: PixTestReadback::readbackVbg()
[17:47:09.226] <TB2> INFO: ----------------------------------------------------------------------
[17:47:16.896] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[17:47:16.896] <TB2> INFO: ----------------------------------------------------------------------
[17:47:16.896] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[17:47:16.896] <TB2> INFO: ----------------------------------------------------------------------
[17:47:16.896] <TB2> INFO: Vbg will be calibrated using Vd calibration
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 154calibrated Vbg = 1.20567 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 148.6calibrated Vbg = 1.20174 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 154.6calibrated Vbg = 1.19808 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 159.6calibrated Vbg = 1.19795 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 160.4calibrated Vbg = 1.19629 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 145.1calibrated Vbg = 1.19859 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 145.9calibrated Vbg = 1.20152 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 153.1calibrated Vbg = 1.20253 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 150calibrated Vbg = 1.20004 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154.1calibrated Vbg = 1.20171 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 153.7calibrated Vbg = 1.19024 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 158.8calibrated Vbg = 1.18501 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 151.3calibrated Vbg = 1.19504 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 163.9calibrated Vbg = 1.19852 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 157.7calibrated Vbg = 1.19827 :::*/*/*/*/
[17:47:16.896] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 154.7calibrated Vbg = 1.20097 :::*/*/*/*/
[17:47:16.899] <TB2> INFO: ----------------------------------------------------------------------
[17:47:16.899] <TB2> INFO: PixTestReadback::CalibrateIa()
[17:47:16.899] <TB2> INFO: ----------------------------------------------------------------------
[17:49:57.704] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C0.dat
[17:49:57.704] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C1.dat
[17:49:57.704] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C2.dat
[17:49:57.704] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C3.dat
[17:49:57.704] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C4.dat
[17:49:57.704] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C5.dat
[17:49:57.704] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C6.dat
[17:49:57.704] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C7.dat
[17:49:57.705] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C8.dat
[17:49:57.705] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C9.dat
[17:49:57.705] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C10.dat
[17:49:57.705] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C11.dat
[17:49:57.705] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C12.dat
[17:49:57.705] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C13.dat
[17:49:57.705] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C14.dat
[17:49:57.705] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//readbackCal_C15.dat
[17:49:57.732] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[17:49:57.733] <TB2> INFO: PixTestReadback::doTest() done
[17:49:57.733] <TB2> INFO: Decoding statistics:
[17:49:57.733] <TB2> INFO: General information:
[17:49:57.733] <TB2> INFO: 16bit words read: 1536
[17:49:57.733] <TB2> INFO: valid events total: 256
[17:49:57.733] <TB2> INFO: empty events: 256
[17:49:57.733] <TB2> INFO: valid events with pixels: 0
[17:49:57.733] <TB2> INFO: valid pixel hits: 0
[17:49:57.733] <TB2> INFO: Event errors: 0
[17:49:57.733] <TB2> INFO: start marker: 0
[17:49:57.733] <TB2> INFO: stop marker: 0
[17:49:57.733] <TB2> INFO: overflow: 0
[17:49:57.733] <TB2> INFO: invalid 5bit words: 0
[17:49:57.733] <TB2> INFO: invalid XOR eye diagram: 0
[17:49:57.733] <TB2> INFO: frame (failed synchr.): 0
[17:49:57.733] <TB2> INFO: idle data (no TBM trl): 0
[17:49:57.733] <TB2> INFO: no data (only TBM hdr): 0
[17:49:57.733] <TB2> INFO: TBM errors: 0
[17:49:57.733] <TB2> INFO: flawed TBM headers: 0
[17:49:57.733] <TB2> INFO: flawed TBM trailers: 0
[17:49:57.733] <TB2> INFO: event ID mismatches: 0
[17:49:57.733] <TB2> INFO: ROC errors: 0
[17:49:57.733] <TB2> INFO: missing ROC header(s): 0
[17:49:57.733] <TB2> INFO: misplaced readback start: 0
[17:49:57.733] <TB2> INFO: Pixel decoding errors: 0
[17:49:57.733] <TB2> INFO: pixel data incomplete: 0
[17:49:57.733] <TB2> INFO: pixel address: 0
[17:49:57.733] <TB2> INFO: pulse height fill bit: 0
[17:49:57.733] <TB2> INFO: buffer corruption: 0
[17:49:57.780] <TB2> INFO: ######################################################################
[17:49:57.780] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[17:49:57.780] <TB2> INFO: ######################################################################
[17:49:57.787] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[17:49:57.854] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:49:57.854] <TB2> INFO: run 1 of 1
[17:49:58.132] <TB2> INFO: Expecting 3120000 events.
[17:50:28.822] <TB2> INFO: 668780 events read in total (30098ms).











[17:50:58.928] <TB2> INFO: 1333970 events read in total (60204ms).











[17:51:29.388] <TB2> INFO: 1998360 events read in total (90664ms).











[17:52:00.344] <TB2> INFO: 2663795 events read in total (121620ms).
[17:52:21.599] <TB2> INFO: 3120000 events read in total (142875ms).
[17:52:21.702] <TB2> INFO: Test took 143849ms.
[17:52:43.893] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 166 seconds
[17:52:43.893] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0
[17:52:43.893] <TB2> INFO: separation cut (per ROC): 101 101 103 101 104 101 100 107 100 101 104 106 104 113 102 105
[17:52:43.893] <TB2> INFO: Decoding statistics:
[17:52:43.893] <TB2> INFO: General information:
[17:52:43.893] <TB2> INFO: 16bit words read: 0
[17:52:43.893] <TB2> INFO: valid events total: 0
[17:52:43.893] <TB2> INFO: empty events: 0
[17:52:43.893] <TB2> INFO: valid events with pixels: 0
[17:52:43.893] <TB2> INFO: valid pixel hits: 0
[17:52:43.893] <TB2> INFO: Event errors: 0
[17:52:43.893] <TB2> INFO: start marker: 0
[17:52:43.893] <TB2> INFO: stop marker: 0
[17:52:43.893] <TB2> INFO: overflow: 0
[17:52:43.893] <TB2> INFO: invalid 5bit words: 0
[17:52:43.893] <TB2> INFO: invalid XOR eye diagram: 0
[17:52:43.893] <TB2> INFO: frame (failed synchr.): 0
[17:52:43.893] <TB2> INFO: idle data (no TBM trl): 0
[17:52:43.893] <TB2> INFO: no data (only TBM hdr): 0
[17:52:43.893] <TB2> INFO: TBM errors: 0
[17:52:43.894] <TB2> INFO: flawed TBM headers: 0
[17:52:43.894] <TB2> INFO: flawed TBM trailers: 0
[17:52:43.894] <TB2> INFO: event ID mismatches: 0
[17:52:43.894] <TB2> INFO: ROC errors: 0
[17:52:43.894] <TB2> INFO: missing ROC header(s): 0
[17:52:43.894] <TB2> INFO: misplaced readback start: 0
[17:52:43.894] <TB2> INFO: Pixel decoding errors: 0
[17:52:43.894] <TB2> INFO: pixel data incomplete: 0
[17:52:43.894] <TB2> INFO: pixel address: 0
[17:52:43.894] <TB2> INFO: pulse height fill bit: 0
[17:52:43.894] <TB2> INFO: buffer corruption: 0
[17:52:43.933] <TB2> INFO: ######################################################################
[17:52:43.933] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[17:52:43.933] <TB2> INFO: ######################################################################
[17:52:43.934] <TB2> INFO: ----------------------------------------------------------------------
[17:52:43.934] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[17:52:43.934] <TB2> INFO: ----------------------------------------------------------------------
[17:52:43.934] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[17:52:43.948] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[17:52:43.948] <TB2> INFO: run 1 of 1
[17:52:44.190] <TB2> INFO: Expecting 36608000 events.
[17:53:07.832] <TB2> INFO: 690800 events read in total (23050ms).
[17:53:30.982] <TB2> INFO: 1366400 events read in total (46200ms).
[17:53:54.119] <TB2> INFO: 2040200 events read in total (69337ms).
[17:54:17.596] <TB2> INFO: 2714950 events read in total (92814ms).
[17:54:40.247] <TB2> INFO: 3386150 events read in total (115465ms).
[17:55:03.319] <TB2> INFO: 4056550 events read in total (138537ms).
[17:55:26.984] <TB2> INFO: 4730050 events read in total (162202ms).
[17:55:50.086] <TB2> INFO: 5402100 events read in total (185304ms).
[17:56:13.391] <TB2> INFO: 6072650 events read in total (208609ms).
[17:56:36.379] <TB2> INFO: 6743000 events read in total (231597ms).
[17:56:59.478] <TB2> INFO: 7414000 events read in total (254696ms).
[17:57:22.681] <TB2> INFO: 8084250 events read in total (277899ms).
[17:57:46.057] <TB2> INFO: 8754000 events read in total (301275ms).
[17:58:09.375] <TB2> INFO: 9423650 events read in total (324593ms).
[17:58:32.479] <TB2> INFO: 10093200 events read in total (347697ms).
[17:58:56.268] <TB2> INFO: 10764300 events read in total (371486ms).
[17:59:19.847] <TB2> INFO: 11434250 events read in total (395065ms).
[17:59:43.378] <TB2> INFO: 12104000 events read in total (418596ms).
[18:00:07.257] <TB2> INFO: 12772400 events read in total (442475ms).
[18:00:31.371] <TB2> INFO: 13441150 events read in total (466589ms).
[18:00:55.116] <TB2> INFO: 14106900 events read in total (490334ms).
[18:01:19.576] <TB2> INFO: 14772800 events read in total (514794ms).
[18:01:43.352] <TB2> INFO: 15437800 events read in total (538570ms).
[18:02:07.681] <TB2> INFO: 16103650 events read in total (562899ms).
[18:02:31.772] <TB2> INFO: 16768800 events read in total (586990ms).
[18:02:55.841] <TB2> INFO: 17433800 events read in total (611059ms).
[18:03:20.252] <TB2> INFO: 18098250 events read in total (635470ms).
[18:03:44.485] <TB2> INFO: 18762250 events read in total (659703ms).
[18:04:09.076] <TB2> INFO: 19426000 events read in total (684294ms).
[18:04:33.736] <TB2> INFO: 20087800 events read in total (708954ms).
[18:04:57.947] <TB2> INFO: 20750350 events read in total (733165ms).
[18:05:23.380] <TB2> INFO: 21413850 events read in total (758598ms).
[18:05:48.256] <TB2> INFO: 22076400 events read in total (783474ms).
[18:06:12.903] <TB2> INFO: 22737100 events read in total (808121ms).
[18:06:36.771] <TB2> INFO: 23396650 events read in total (831989ms).
[18:07:01.150] <TB2> INFO: 24056200 events read in total (856368ms).
[18:07:25.717] <TB2> INFO: 24716950 events read in total (880935ms).
[18:07:50.027] <TB2> INFO: 25377100 events read in total (905245ms).
[18:08:13.940] <TB2> INFO: 26037400 events read in total (929158ms).
[18:08:38.977] <TB2> INFO: 26697700 events read in total (954195ms).
[18:09:02.961] <TB2> INFO: 27356900 events read in total (978179ms).
[18:09:27.504] <TB2> INFO: 28015700 events read in total (1002722ms).
[18:09:52.026] <TB2> INFO: 28675350 events read in total (1027244ms).
[18:10:16.970] <TB2> INFO: 29332000 events read in total (1052188ms).
[18:10:41.322] <TB2> INFO: 29990550 events read in total (1076540ms).
[18:11:05.329] <TB2> INFO: 30649050 events read in total (1100547ms).
[18:11:29.561] <TB2> INFO: 31306700 events read in total (1124779ms).
[18:11:53.376] <TB2> INFO: 31963450 events read in total (1148594ms).
[18:12:17.057] <TB2> INFO: 32620050 events read in total (1172275ms).
[18:12:41.425] <TB2> INFO: 33277950 events read in total (1196643ms).
[18:13:05.902] <TB2> INFO: 33936950 events read in total (1221120ms).
[18:13:29.823] <TB2> INFO: 34595900 events read in total (1245041ms).
[18:13:53.792] <TB2> INFO: 35255750 events read in total (1269010ms).
[18:14:19.284] <TB2> INFO: 35916250 events read in total (1294502ms).
[18:14:44.408] <TB2> INFO: 36588050 events read in total (1319626ms).
[18:14:45.573] <TB2> INFO: 36608000 events read in total (1320791ms).
[18:14:45.669] <TB2> INFO: Test took 1321720ms.
[18:14:46.246] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:14:48.432] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:14:50.303] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:14:52.312] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:14:54.385] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:14:56.593] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:14:59.034] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:15:01.073] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:15:02.943] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:15:04.959] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:15:07.317] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:15:09.461] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:15:11.763] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:15:14.133] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:15:16.498] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:15:18.895] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:15:21.293] <TB2> INFO: PixTestScurves::scurves() done
[18:15:21.293] <TB2> INFO: Vcal mean: 116.25 109.16 118.94 120.80 122.20 105.10 115.33 120.21 119.90 120.77 118.38 121.89 120.80 121.43 115.93 118.54
[18:15:21.293] <TB2> INFO: Vcal RMS: 5.86 5.04 5.81 7.11 5.68 5.40 5.14 6.23 6.06 6.39 6.52 6.78 6.21 6.22 5.11 6.12
[18:15:21.293] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1357 seconds
[18:15:21.293] <TB2> INFO: Decoding statistics:
[18:15:21.293] <TB2> INFO: General information:
[18:15:21.293] <TB2> INFO: 16bit words read: 0
[18:15:21.293] <TB2> INFO: valid events total: 0
[18:15:21.293] <TB2> INFO: empty events: 0
[18:15:21.293] <TB2> INFO: valid events with pixels: 0
[18:15:21.293] <TB2> INFO: valid pixel hits: 0
[18:15:21.293] <TB2> INFO: Event errors: 0
[18:15:21.293] <TB2> INFO: start marker: 0
[18:15:21.293] <TB2> INFO: stop marker: 0
[18:15:21.293] <TB2> INFO: overflow: 0
[18:15:21.293] <TB2> INFO: invalid 5bit words: 0
[18:15:21.293] <TB2> INFO: invalid XOR eye diagram: 0
[18:15:21.293] <TB2> INFO: frame (failed synchr.): 0
[18:15:21.293] <TB2> INFO: idle data (no TBM trl): 0
[18:15:21.293] <TB2> INFO: no data (only TBM hdr): 0
[18:15:21.293] <TB2> INFO: TBM errors: 0
[18:15:21.293] <TB2> INFO: flawed TBM headers: 0
[18:15:21.293] <TB2> INFO: flawed TBM trailers: 0
[18:15:21.293] <TB2> INFO: event ID mismatches: 0
[18:15:21.294] <TB2> INFO: ROC errors: 0
[18:15:21.294] <TB2> INFO: missing ROC header(s): 0
[18:15:21.294] <TB2> INFO: misplaced readback start: 0
[18:15:21.294] <TB2> INFO: Pixel decoding errors: 0
[18:15:21.294] <TB2> INFO: pixel data incomplete: 0
[18:15:21.294] <TB2> INFO: pixel address: 0
[18:15:21.294] <TB2> INFO: pulse height fill bit: 0
[18:15:21.294] <TB2> INFO: buffer corruption: 0
[18:15:21.361] <TB2> INFO: ######################################################################
[18:15:21.361] <TB2> INFO: PixTestTrim::doTest()
[18:15:21.361] <TB2> INFO: ######################################################################
[18:15:21.363] <TB2> INFO: ----------------------------------------------------------------------
[18:15:21.363] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[18:15:21.363] <TB2> INFO: ----------------------------------------------------------------------
[18:15:21.426] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[18:15:21.426] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[18:15:21.442] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:15:21.442] <TB2> INFO: run 1 of 1
[18:15:21.703] <TB2> INFO: Expecting 5025280 events.
[18:15:54.087] <TB2> INFO: 822960 events read in total (31782ms).
[18:16:25.872] <TB2> INFO: 1642792 events read in total (63567ms).
[18:16:57.270] <TB2> INFO: 2460560 events read in total (94966ms).
[18:17:28.663] <TB2> INFO: 3276016 events read in total (126358ms).
[18:18:00.804] <TB2> INFO: 4088208 events read in total (158499ms).
[18:18:31.841] <TB2> INFO: 4897656 events read in total (189536ms).
[18:18:37.242] <TB2> INFO: 5025280 events read in total (194937ms).
[18:18:37.352] <TB2> INFO: Test took 195910ms.
[18:18:56.641] <TB2> INFO: ROC 0 VthrComp = 115
[18:18:56.642] <TB2> INFO: ROC 1 VthrComp = 114
[18:18:56.642] <TB2> INFO: ROC 2 VthrComp = 128
[18:18:56.644] <TB2> INFO: ROC 3 VthrComp = 116
[18:18:56.644] <TB2> INFO: ROC 4 VthrComp = 127
[18:18:56.644] <TB2> INFO: ROC 5 VthrComp = 107
[18:18:56.644] <TB2> INFO: ROC 6 VthrComp = 113
[18:18:56.644] <TB2> INFO: ROC 7 VthrComp = 126
[18:18:56.644] <TB2> INFO: ROC 8 VthrComp = 117
[18:18:56.644] <TB2> INFO: ROC 9 VthrComp = 117
[18:18:56.645] <TB2> INFO: ROC 10 VthrComp = 114
[18:18:56.645] <TB2> INFO: ROC 11 VthrComp = 118
[18:18:56.646] <TB2> INFO: ROC 12 VthrComp = 118
[18:18:56.647] <TB2> INFO: ROC 13 VthrComp = 121
[18:18:56.648] <TB2> INFO: ROC 14 VthrComp = 118
[18:18:56.648] <TB2> INFO: ROC 15 VthrComp = 120
[18:18:56.985] <TB2> INFO: Expecting 41600 events.
[18:19:00.703] <TB2> INFO: 41600 events read in total (3123ms).
[18:19:00.703] <TB2> INFO: Test took 4051ms.
[18:19:00.714] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[18:19:00.714] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[18:19:00.729] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:19:00.729] <TB2> INFO: run 1 of 1
[18:19:01.007] <TB2> INFO: Expecting 5025280 events.
[18:19:28.662] <TB2> INFO: 592208 events read in total (27059ms).
[18:19:56.093] <TB2> INFO: 1182472 events read in total (54490ms).
[18:20:23.379] <TB2> INFO: 1772552 events read in total (81776ms).
[18:20:50.918] <TB2> INFO: 2361416 events read in total (109315ms).
[18:21:17.961] <TB2> INFO: 2948544 events read in total (136358ms).
[18:21:45.499] <TB2> INFO: 3534056 events read in total (163896ms).
[18:22:12.218] <TB2> INFO: 4118704 events read in total (190615ms).
[18:22:40.923] <TB2> INFO: 4702160 events read in total (219320ms).
[18:22:56.090] <TB2> INFO: 5025280 events read in total (234487ms).
[18:22:56.196] <TB2> INFO: Test took 235467ms.
[18:23:28.542] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 62.3596 for pixel 15/0 mean/min/max = 47.1369/31.8715/62.4022
[18:23:28.543] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 58.284 for pixel 21/4 mean/min/max = 45.3735/32.3301/58.417
[18:23:28.544] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 56.7156 for pixel 0/23 mean/min/max = 44.2723/31.5822/56.9624
[18:23:28.544] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 65.9859 for pixel 0/5 mean/min/max = 48.4189/30.6594/66.1783
[18:23:28.545] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 57.2975 for pixel 4/16 mean/min/max = 44.4489/31.5638/57.3341
[18:23:28.546] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 59.6863 for pixel 38/11 mean/min/max = 47.2983/34.613/59.9835
[18:23:28.546] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 58.551 for pixel 51/11 mean/min/max = 46.3262/33.8837/58.7687
[18:23:28.547] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 58.9342 for pixel 24/79 mean/min/max = 44.7296/30.3805/59.0786
[18:23:28.548] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 59.5538 for pixel 0/69 mean/min/max = 46.2206/32.6947/59.7465
[18:23:28.548] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 60.5958 for pixel 14/42 mean/min/max = 46.4393/32.2588/60.6198
[18:23:28.549] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 63.7552 for pixel 0/12 mean/min/max = 47.7934/31.6517/63.9352
[18:23:28.549] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 62.8569 for pixel 17/79 mean/min/max = 47.452/32.0232/62.8809
[18:23:28.550] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 60.8158 for pixel 24/28 mean/min/max = 46.3511/31.8545/60.8478
[18:23:28.550] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 59.2224 for pixel 8/73 mean/min/max = 46.1186/32.9648/59.2724
[18:23:28.551] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 57.3529 for pixel 17/10 mean/min/max = 45.2865/33.0164/57.5567
[18:23:28.551] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 60.6293 for pixel 18/7 mean/min/max = 46.7615/32.8551/60.6679
[18:23:28.552] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:23:28.641] <TB2> INFO: Expecting 411648 events.
[18:23:38.345] <TB2> INFO: 411648 events read in total (9113ms).
[18:23:38.355] <TB2> INFO: Expecting 411648 events.
[18:23:47.853] <TB2> INFO: 411648 events read in total (9094ms).
[18:23:47.868] <TB2> INFO: Expecting 411648 events.
[18:23:57.199] <TB2> INFO: 411648 events read in total (8928ms).
[18:23:57.212] <TB2> INFO: Expecting 411648 events.
[18:24:06.519] <TB2> INFO: 411648 events read in total (8903ms).
[18:24:06.538] <TB2> INFO: Expecting 411648 events.
[18:24:15.826] <TB2> INFO: 411648 events read in total (8885ms).
[18:24:15.858] <TB2> INFO: Expecting 411648 events.
[18:24:25.310] <TB2> INFO: 411648 events read in total (9049ms).
[18:24:25.332] <TB2> INFO: Expecting 411648 events.
[18:24:34.666] <TB2> INFO: 411648 events read in total (8931ms).
[18:24:34.699] <TB2> INFO: Expecting 411648 events.
[18:24:43.928] <TB2> INFO: 411648 events read in total (8826ms).
[18:24:43.964] <TB2> INFO: Expecting 411648 events.
[18:24:53.492] <TB2> INFO: 411648 events read in total (9125ms).
[18:24:53.542] <TB2> INFO: Expecting 411648 events.
[18:25:02.977] <TB2> INFO: 411648 events read in total (9032ms).
[18:25:03.023] <TB2> INFO: Expecting 411648 events.
[18:25:12.348] <TB2> INFO: 411648 events read in total (8919ms).
[18:25:12.383] <TB2> INFO: Expecting 411648 events.
[18:25:21.670] <TB2> INFO: 411648 events read in total (8884ms).
[18:25:21.736] <TB2> INFO: Expecting 411648 events.
[18:25:31.180] <TB2> INFO: 411648 events read in total (9041ms).
[18:25:31.269] <TB2> INFO: Expecting 411648 events.
[18:25:40.691] <TB2> INFO: 411648 events read in total (9019ms).
[18:25:40.751] <TB2> INFO: Expecting 411648 events.
[18:25:50.047] <TB2> INFO: 411648 events read in total (8893ms).
[18:25:50.132] <TB2> INFO: Expecting 411648 events.
[18:25:59.481] <TB2> INFO: 411648 events read in total (8946ms).
[18:25:59.574] <TB2> INFO: Test took 151022ms.
[18:26:00.385] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[18:26:00.399] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:26:00.399] <TB2> INFO: run 1 of 1
[18:26:00.654] <TB2> INFO: Expecting 5025280 events.
[18:26:27.901] <TB2> INFO: 587600 events read in total (26655ms).
[18:26:55.120] <TB2> INFO: 1174896 events read in total (53875ms).
[18:27:22.193] <TB2> INFO: 1759896 events read in total (80947ms).
[18:27:49.421] <TB2> INFO: 2344928 events read in total (108175ms).
[18:28:16.682] <TB2> INFO: 2930384 events read in total (135436ms).
[18:28:43.775] <TB2> INFO: 3514776 events read in total (162529ms).
[18:29:11.096] <TB2> INFO: 4098392 events read in total (189850ms).
[18:29:39.596] <TB2> INFO: 4680096 events read in total (218350ms).
[18:29:56.389] <TB2> INFO: 5025280 events read in total (235144ms).
[18:29:56.541] <TB2> INFO: Test took 236143ms.
[18:30:25.725] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 9.877472 .. 141.026032
[18:30:26.032] <TB2> INFO: Expecting 208000 events.
[18:30:35.783] <TB2> INFO: 208000 events read in total (9158ms).
[18:30:35.785] <TB2> INFO: Test took 10058ms.
[18:30:35.837] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 9 .. 151 (-1/-1) hits flags = 528 (plus default)
[18:30:35.852] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:30:35.852] <TB2> INFO: run 1 of 1
[18:30:36.131] <TB2> INFO: Expecting 4759040 events.
[18:31:03.352] <TB2> INFO: 574416 events read in total (26630ms).
[18:31:30.407] <TB2> INFO: 1149280 events read in total (53685ms).
[18:31:57.094] <TB2> INFO: 1724992 events read in total (80372ms).
[18:32:23.981] <TB2> INFO: 2300456 events read in total (107260ms).
[18:32:50.569] <TB2> INFO: 2875472 events read in total (133847ms).
[18:33:17.191] <TB2> INFO: 3449920 events read in total (160469ms).
[18:33:44.614] <TB2> INFO: 4023880 events read in total (187893ms).
[18:34:12.935] <TB2> INFO: 4597144 events read in total (216213ms).
[18:34:21.220] <TB2> INFO: 4759040 events read in total (224498ms).
[18:34:21.416] <TB2> INFO: Test took 225565ms.
[18:34:49.225] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.801854 .. 47.593387
[18:34:49.465] <TB2> INFO: Expecting 208000 events.
[18:35:00.375] <TB2> INFO: 208000 events read in total (10319ms).
[18:35:00.376] <TB2> INFO: Test took 11150ms.
[18:35:00.455] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 57 (-1/-1) hits flags = 528 (plus default)
[18:35:00.471] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:35:00.471] <TB2> INFO: run 1 of 1
[18:35:00.752] <TB2> INFO: Expecting 1364480 events.
[18:35:30.631] <TB2> INFO: 651560 events read in total (29287ms).
[18:36:00.993] <TB2> INFO: 1303400 events read in total (59649ms).
[18:36:03.003] <TB2> INFO: 1364480 events read in total (62659ms).
[18:36:04.038] <TB2> INFO: Test took 63567ms.
[18:36:19.293] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 26.343244 .. 48.025174
[18:36:19.551] <TB2> INFO: Expecting 208000 events.
[18:36:30.145] <TB2> INFO: 208000 events read in total (9999ms).
[18:36:30.145] <TB2> INFO: Test took 10851ms.
[18:36:30.197] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 58 (-1/-1) hits flags = 528 (plus default)
[18:36:30.216] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:36:30.216] <TB2> INFO: run 1 of 1
[18:36:30.524] <TB2> INFO: Expecting 1431040 events.
[18:37:00.690] <TB2> INFO: 652776 events read in total (29572ms).
[18:37:30.643] <TB2> INFO: 1304808 events read in total (59525ms).
[18:37:36.755] <TB2> INFO: 1431040 events read in total (65637ms).
[18:37:36.789] <TB2> INFO: Test took 66573ms.
[18:37:51.265] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 24.307328 .. 45.625673
[18:37:51.582] <TB2> INFO: Expecting 208000 events.
[18:38:02.172] <TB2> INFO: 208000 events read in total (9998ms).
[18:38:02.173] <TB2> INFO: Test took 10907ms.
[18:38:02.226] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 55 (-1/-1) hits flags = 528 (plus default)
[18:38:02.241] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:38:02.241] <TB2> INFO: run 1 of 1
[18:38:02.519] <TB2> INFO: Expecting 1397760 events.
[18:38:32.559] <TB2> INFO: 672304 events read in total (29448ms).
[18:39:03.056] <TB2> INFO: 1344528 events read in total (59945ms).
[18:39:05.965] <TB2> INFO: 1397760 events read in total (62855ms).
[18:39:05.999] <TB2> INFO: Test took 63758ms.
[18:39:18.780] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[18:39:18.780] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[18:39:18.797] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:39:18.797] <TB2> INFO: run 1 of 1
[18:39:19.129] <TB2> INFO: Expecting 1364480 events.
[18:39:49.438] <TB2> INFO: 668688 events read in total (29717ms).
[18:40:19.788] <TB2> INFO: 1337056 events read in total (60067ms).
[18:40:21.439] <TB2> INFO: 1364480 events read in total (61719ms).
[18:40:21.471] <TB2> INFO: Test took 62674ms.
[18:40:36.357] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C0.dat
[18:40:36.357] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C1.dat
[18:40:36.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C2.dat
[18:40:36.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C3.dat
[18:40:36.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C4.dat
[18:40:36.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C5.dat
[18:40:36.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C6.dat
[18:40:36.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C7.dat
[18:40:36.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C8.dat
[18:40:36.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C9.dat
[18:40:36.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C10.dat
[18:40:36.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C11.dat
[18:40:36.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C12.dat
[18:40:36.359] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C13.dat
[18:40:36.359] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C14.dat
[18:40:36.359] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C15.dat
[18:40:36.359] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C0.dat
[18:40:36.364] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C1.dat
[18:40:36.369] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C2.dat
[18:40:36.374] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C3.dat
[18:40:36.380] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C4.dat
[18:40:36.385] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C5.dat
[18:40:36.392] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C6.dat
[18:40:36.399] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C7.dat
[18:40:36.407] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C8.dat
[18:40:36.414] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C9.dat
[18:40:36.421] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C10.dat
[18:40:36.429] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C11.dat
[18:40:36.436] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C12.dat
[18:40:36.444] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C13.dat
[18:40:36.451] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C14.dat
[18:40:36.459] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters35_C15.dat
[18:40:36.466] <TB2> INFO: PixTestTrim::trimTest() done
[18:40:36.466] <TB2> INFO: vtrim: 128 121 112 143 128 120 100 136 118 118 117 124 125 122 125 129
[18:40:36.466] <TB2> INFO: vthrcomp: 115 114 128 116 127 107 113 126 117 117 114 118 118 121 118 120
[18:40:36.466] <TB2> INFO: vcal mean: 35.22 34.97 35.08 35.39 34.99 35.02 35.10 35.01 35.09 35.12 35.13 35.25 35.13 35.05 35.00 34.92
[18:40:36.466] <TB2> INFO: vcal RMS: 1.31 0.99 1.01 1.54 1.07 0.97 1.05 1.17 1.13 1.20 1.23 1.54 1.27 1.09 1.00 1.02
[18:40:36.466] <TB2> INFO: bits mean: 9.66 9.65 9.75 9.26 9.84 8.87 8.48 10.18 9.06 9.61 8.72 9.34 10.02 9.51 9.45 9.10
[18:40:36.466] <TB2> INFO: bits RMS: 2.64 2.60 2.69 2.87 2.71 2.51 2.89 2.67 2.84 2.63 3.00 2.75 2.50 2.57 2.62 2.71
[18:40:36.475] <TB2> INFO: ----------------------------------------------------------------------
[18:40:36.475] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[18:40:36.475] <TB2> INFO: ----------------------------------------------------------------------
[18:40:36.478] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[18:40:36.493] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:40:36.494] <TB2> INFO: run 1 of 1
[18:40:36.753] <TB2> INFO: Expecting 4160000 events.
[18:41:10.144] <TB2> INFO: 762020 events read in total (32800ms).
[18:41:42.999] <TB2> INFO: 1517575 events read in total (65655ms).
[18:42:16.016] <TB2> INFO: 2266535 events read in total (98672ms).
[18:42:49.272] <TB2> INFO: 3009570 events read in total (131928ms).
[18:43:22.570] <TB2> INFO: 3748900 events read in total (165226ms).
[18:43:41.382] <TB2> INFO: 4160000 events read in total (184038ms).
[18:43:41.465] <TB2> INFO: Test took 184972ms.
[18:44:10.858] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 200 (-1/-1) hits flags = 528 (plus default)
[18:44:10.873] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:44:10.873] <TB2> INFO: run 1 of 1
[18:44:11.112] <TB2> INFO: Expecting 4180800 events.
[18:44:44.805] <TB2> INFO: 734140 events read in total (33102ms).
[18:45:17.236] <TB2> INFO: 1462640 events read in total (65533ms).
[18:45:49.705] <TB2> INFO: 2185880 events read in total (98002ms).
[18:46:21.829] <TB2> INFO: 2903765 events read in total (130126ms).
[18:46:54.212] <TB2> INFO: 3618280 events read in total (162509ms).
[18:47:20.517] <TB2> INFO: 4180800 events read in total (188814ms).
[18:47:20.660] <TB2> INFO: Test took 189787ms.
[18:47:51.984] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 185 (-1/-1) hits flags = 528 (plus default)
[18:47:51.998] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:47:51.998] <TB2> INFO: run 1 of 1
[18:47:52.249] <TB2> INFO: Expecting 3868800 events.
[18:48:26.698] <TB2> INFO: 757945 events read in total (33857ms).
[18:48:59.562] <TB2> INFO: 1508625 events read in total (66721ms).
[18:49:32.280] <TB2> INFO: 2253020 events read in total (99439ms).
[18:50:05.227] <TB2> INFO: 2990480 events read in total (132386ms).
[18:50:38.129] <TB2> INFO: 3725695 events read in total (165288ms).
[18:50:44.773] <TB2> INFO: 3868800 events read in total (171932ms).
[18:50:44.876] <TB2> INFO: Test took 172878ms.
[18:51:14.803] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 185 (-1/-1) hits flags = 528 (plus default)
[18:51:14.815] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:51:14.815] <TB2> INFO: run 1 of 1
[18:51:15.055] <TB2> INFO: Expecting 3868800 events.
[18:51:48.928] <TB2> INFO: 757945 events read in total (33276ms).
[18:52:22.101] <TB2> INFO: 1508800 events read in total (66449ms).
[18:52:54.408] <TB2> INFO: 2253300 events read in total (98756ms).
[18:53:26.728] <TB2> INFO: 2990815 events read in total (131076ms).
[18:53:58.969] <TB2> INFO: 3726375 events read in total (163317ms).
[18:54:05.930] <TB2> INFO: 3868800 events read in total (170278ms).
[18:54:06.006] <TB2> INFO: Test took 171192ms.
[18:54:38.820] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 184 (-1/-1) hits flags = 528 (plus default)
[18:54:38.834] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:54:38.834] <TB2> INFO: run 1 of 1
[18:54:39.076] <TB2> INFO: Expecting 3848000 events.
[18:55:12.270] <TB2> INFO: 760170 events read in total (32602ms).
[18:55:45.619] <TB2> INFO: 1512665 events read in total (65951ms).
[18:56:17.951] <TB2> INFO: 2258965 events read in total (98283ms).
[18:56:50.424] <TB2> INFO: 2998745 events read in total (130756ms).
[18:57:22.720] <TB2> INFO: 3736355 events read in total (163052ms).
[18:57:28.128] <TB2> INFO: 3848000 events read in total (168460ms).
[18:57:28.215] <TB2> INFO: Test took 169381ms.
[18:58:00.590] <TB2> INFO: PixTestTrim::trimBitTest() done
[18:58:00.591] <TB2> INFO: PixTestTrim::doTest() done, duration: 2559 seconds
[18:58:00.592] <TB2> INFO: Decoding statistics:
[18:58:00.592] <TB2> INFO: General information:
[18:58:00.592] <TB2> INFO: 16bit words read: 0
[18:58:00.592] <TB2> INFO: valid events total: 0
[18:58:00.592] <TB2> INFO: empty events: 0
[18:58:00.592] <TB2> INFO: valid events with pixels: 0
[18:58:00.592] <TB2> INFO: valid pixel hits: 0
[18:58:00.592] <TB2> INFO: Event errors: 0
[18:58:00.592] <TB2> INFO: start marker: 0
[18:58:00.592] <TB2> INFO: stop marker: 0
[18:58:00.592] <TB2> INFO: overflow: 0
[18:58:00.592] <TB2> INFO: invalid 5bit words: 0
[18:58:00.592] <TB2> INFO: invalid XOR eye diagram: 0
[18:58:00.592] <TB2> INFO: frame (failed synchr.): 0
[18:58:00.592] <TB2> INFO: idle data (no TBM trl): 0
[18:58:00.592] <TB2> INFO: no data (only TBM hdr): 0
[18:58:00.592] <TB2> INFO: TBM errors: 0
[18:58:00.592] <TB2> INFO: flawed TBM headers: 0
[18:58:00.592] <TB2> INFO: flawed TBM trailers: 0
[18:58:00.592] <TB2> INFO: event ID mismatches: 0
[18:58:00.592] <TB2> INFO: ROC errors: 0
[18:58:00.593] <TB2> INFO: missing ROC header(s): 0
[18:58:00.593] <TB2> INFO: misplaced readback start: 0
[18:58:00.593] <TB2> INFO: Pixel decoding errors: 0
[18:58:00.593] <TB2> INFO: pixel data incomplete: 0
[18:58:00.593] <TB2> INFO: pixel address: 0
[18:58:00.593] <TB2> INFO: pulse height fill bit: 0
[18:58:00.593] <TB2> INFO: buffer corruption: 0
[18:58:01.310] <TB2> INFO: ######################################################################
[18:58:01.310] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[18:58:01.310] <TB2> INFO: ######################################################################
[18:58:01.582] <TB2> INFO: Expecting 41600 events.
[18:58:05.141] <TB2> INFO: 41600 events read in total (2967ms).
[18:58:05.142] <TB2> INFO: Test took 3827ms.
[18:58:05.602] <TB2> INFO: Expecting 41600 events.
[18:58:09.209] <TB2> INFO: 41600 events read in total (3015ms).
[18:58:09.210] <TB2> INFO: Test took 3857ms.
[18:58:09.512] <TB2> INFO: Expecting 41600 events.
[18:58:13.188] <TB2> INFO: 41600 events read in total (3084ms).
[18:58:13.189] <TB2> INFO: Test took 3953ms.
[18:58:13.492] <TB2> INFO: Expecting 41600 events.
[18:58:17.127] <TB2> INFO: 41600 events read in total (3043ms).
[18:58:17.129] <TB2> INFO: Test took 3915ms.
[18:58:17.486] <TB2> INFO: Expecting 41600 events.
[18:58:21.092] <TB2> INFO: 41600 events read in total (3013ms).
[18:58:21.092] <TB2> INFO: Test took 3932ms.
[18:58:21.382] <TB2> INFO: Expecting 41600 events.
[18:58:25.162] <TB2> INFO: 41600 events read in total (3189ms).
[18:58:25.163] <TB2> INFO: Test took 4046ms.
[18:58:25.473] <TB2> INFO: Expecting 41600 events.
[18:58:29.169] <TB2> INFO: 41600 events read in total (3103ms).
[18:58:29.170] <TB2> INFO: Test took 3981ms.
[18:58:29.461] <TB2> INFO: Expecting 41600 events.
[18:58:33.076] <TB2> INFO: 41600 events read in total (3024ms).
[18:58:33.078] <TB2> INFO: Test took 3883ms.
[18:58:33.374] <TB2> INFO: Expecting 41600 events.
[18:58:36.942] <TB2> INFO: 41600 events read in total (2976ms).
[18:58:36.943] <TB2> INFO: Test took 3834ms.
[18:58:37.274] <TB2> INFO: Expecting 41600 events.
[18:58:40.779] <TB2> INFO: 41600 events read in total (2913ms).
[18:58:40.780] <TB2> INFO: Test took 3812ms.
[18:58:41.077] <TB2> INFO: Expecting 41600 events.
[18:58:44.583] <TB2> INFO: 41600 events read in total (2915ms).
[18:58:44.583] <TB2> INFO: Test took 3776ms.
[18:58:44.872] <TB2> INFO: Expecting 41600 events.
[18:58:48.595] <TB2> INFO: 41600 events read in total (3129ms).
[18:58:48.596] <TB2> INFO: Test took 3989ms.
[18:58:48.886] <TB2> INFO: Expecting 41600 events.
[18:58:52.511] <TB2> INFO: 41600 events read in total (3034ms).
[18:58:52.511] <TB2> INFO: Test took 3890ms.
[18:58:52.810] <TB2> INFO: Expecting 41600 events.
[18:58:56.490] <TB2> INFO: 41600 events read in total (3088ms).
[18:58:56.490] <TB2> INFO: Test took 3951ms.
[18:58:56.803] <TB2> INFO: Expecting 41600 events.
[18:59:00.360] <TB2> INFO: 41600 events read in total (2965ms).
[18:59:00.361] <TB2> INFO: Test took 3846ms.
[18:59:00.709] <TB2> INFO: Expecting 41600 events.
[18:59:04.419] <TB2> INFO: 41600 events read in total (3108ms).
[18:59:04.419] <TB2> INFO: Test took 4034ms.
[18:59:04.709] <TB2> INFO: Expecting 41600 events.
[18:59:08.246] <TB2> INFO: 41600 events read in total (2946ms).
[18:59:08.247] <TB2> INFO: Test took 3803ms.
[18:59:08.545] <TB2> INFO: Expecting 41600 events.
[18:59:12.124] <TB2> INFO: 41600 events read in total (2987ms).
[18:59:12.125] <TB2> INFO: Test took 3852ms.
[18:59:12.418] <TB2> INFO: Expecting 41600 events.
[18:59:15.958] <TB2> INFO: 41600 events read in total (2948ms).
[18:59:15.960] <TB2> INFO: Test took 3807ms.
[18:59:16.308] <TB2> INFO: Expecting 41600 events.
[18:59:19.980] <TB2> INFO: 41600 events read in total (3080ms).
[18:59:19.981] <TB2> INFO: Test took 3996ms.
[18:59:20.271] <TB2> INFO: Expecting 41600 events.
[18:59:23.896] <TB2> INFO: 41600 events read in total (3033ms).
[18:59:23.897] <TB2> INFO: Test took 3891ms.
[18:59:24.212] <TB2> INFO: Expecting 41600 events.
[18:59:27.895] <TB2> INFO: 41600 events read in total (3091ms).
[18:59:27.896] <TB2> INFO: Test took 3974ms.
[18:59:28.185] <TB2> INFO: Expecting 41600 events.
[18:59:31.730] <TB2> INFO: 41600 events read in total (2953ms).
[18:59:31.731] <TB2> INFO: Test took 3811ms.
[18:59:32.020] <TB2> INFO: Expecting 41600 events.
[18:59:35.578] <TB2> INFO: 41600 events read in total (2966ms).
[18:59:35.578] <TB2> INFO: Test took 3823ms.
[18:59:35.868] <TB2> INFO: Expecting 41600 events.
[18:59:39.624] <TB2> INFO: 41600 events read in total (3165ms).
[18:59:39.625] <TB2> INFO: Test took 4022ms.
[18:59:39.914] <TB2> INFO: Expecting 41600 events.
[18:59:43.597] <TB2> INFO: 41600 events read in total (3089ms).
[18:59:43.598] <TB2> INFO: Test took 3949ms.
[18:59:43.909] <TB2> INFO: Expecting 41600 events.
[18:59:47.390] <TB2> INFO: 41600 events read in total (2889ms).
[18:59:47.391] <TB2> INFO: Test took 3766ms.
[18:59:47.684] <TB2> INFO: Expecting 2560 events.
[18:59:48.573] <TB2> INFO: 2560 events read in total (297ms).
[18:59:48.573] <TB2> INFO: Test took 1166ms.
[18:59:48.880] <TB2> INFO: Expecting 2560 events.
[18:59:49.769] <TB2> INFO: 2560 events read in total (297ms).
[18:59:49.769] <TB2> INFO: Test took 1196ms.
[18:59:50.077] <TB2> INFO: Expecting 2560 events.
[18:59:50.962] <TB2> INFO: 2560 events read in total (293ms).
[18:59:50.962] <TB2> INFO: Test took 1192ms.
[18:59:51.270] <TB2> INFO: Expecting 2560 events.
[18:59:52.153] <TB2> INFO: 2560 events read in total (291ms).
[18:59:52.153] <TB2> INFO: Test took 1190ms.
[18:59:52.461] <TB2> INFO: Expecting 2560 events.
[18:59:53.340] <TB2> INFO: 2560 events read in total (288ms).
[18:59:53.340] <TB2> INFO: Test took 1187ms.
[18:59:53.650] <TB2> INFO: Expecting 2560 events.
[18:59:54.538] <TB2> INFO: 2560 events read in total (296ms).
[18:59:54.538] <TB2> INFO: Test took 1193ms.
[18:59:54.846] <TB2> INFO: Expecting 2560 events.
[18:59:55.730] <TB2> INFO: 2560 events read in total (292ms).
[18:59:55.731] <TB2> INFO: Test took 1192ms.
[18:59:56.039] <TB2> INFO: Expecting 2560 events.
[18:59:56.920] <TB2> INFO: 2560 events read in total (290ms).
[18:59:56.920] <TB2> INFO: Test took 1188ms.
[18:59:57.228] <TB2> INFO: Expecting 2560 events.
[18:59:58.108] <TB2> INFO: 2560 events read in total (288ms).
[18:59:58.108] <TB2> INFO: Test took 1188ms.
[18:59:58.416] <TB2> INFO: Expecting 2560 events.
[18:59:59.298] <TB2> INFO: 2560 events read in total (288ms).
[18:59:59.298] <TB2> INFO: Test took 1189ms.
[18:59:59.606] <TB2> INFO: Expecting 2560 events.
[19:00:00.490] <TB2> INFO: 2560 events read in total (292ms).
[19:00:00.490] <TB2> INFO: Test took 1191ms.
[19:00:00.799] <TB2> INFO: Expecting 2560 events.
[19:00:01.679] <TB2> INFO: 2560 events read in total (288ms).
[19:00:01.679] <TB2> INFO: Test took 1188ms.
[19:00:01.987] <TB2> INFO: Expecting 2560 events.
[19:00:02.873] <TB2> INFO: 2560 events read in total (293ms).
[19:00:02.873] <TB2> INFO: Test took 1193ms.
[19:00:03.180] <TB2> INFO: Expecting 2560 events.
[19:00:04.064] <TB2> INFO: 2560 events read in total (292ms).
[19:00:04.064] <TB2> INFO: Test took 1191ms.
[19:00:04.373] <TB2> INFO: Expecting 2560 events.
[19:00:05.264] <TB2> INFO: 2560 events read in total (299ms).
[19:00:05.264] <TB2> INFO: Test took 1199ms.
[19:00:05.571] <TB2> INFO: Expecting 2560 events.
[19:00:06.455] <TB2> INFO: 2560 events read in total (292ms).
[19:00:06.455] <TB2> INFO: Test took 1191ms.
[19:00:06.458] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:00:06.764] <TB2> INFO: Expecting 655360 events.
[19:00:21.508] <TB2> INFO: 655360 events read in total (14151ms).
[19:00:21.527] <TB2> INFO: Expecting 655360 events.
[19:00:36.200] <TB2> INFO: 655360 events read in total (14270ms).
[19:00:36.224] <TB2> INFO: Expecting 655360 events.
[19:00:50.793] <TB2> INFO: 655360 events read in total (14166ms).
[19:00:50.820] <TB2> INFO: Expecting 655360 events.
[19:01:05.216] <TB2> INFO: 655360 events read in total (13993ms).
[19:01:05.247] <TB2> INFO: Expecting 655360 events.
[19:01:19.851] <TB2> INFO: 655360 events read in total (14201ms).
[19:01:19.898] <TB2> INFO: Expecting 655360 events.
[19:01:34.445] <TB2> INFO: 655360 events read in total (14144ms).
[19:01:34.502] <TB2> INFO: Expecting 655360 events.
[19:01:49.014] <TB2> INFO: 655360 events read in total (14109ms).
[19:01:49.066] <TB2> INFO: Expecting 655360 events.
[19:02:03.442] <TB2> INFO: 655360 events read in total (13973ms).
[19:02:03.486] <TB2> INFO: Expecting 655360 events.
[19:02:17.903] <TB2> INFO: 655360 events read in total (14014ms).
[19:02:17.975] <TB2> INFO: Expecting 655360 events.
[19:02:32.323] <TB2> INFO: 655360 events read in total (13945ms).
[19:02:32.378] <TB2> INFO: Expecting 655360 events.
[19:02:46.850] <TB2> INFO: 655360 events read in total (14069ms).
[19:02:46.946] <TB2> INFO: Expecting 655360 events.
[19:03:01.355] <TB2> INFO: 655360 events read in total (14006ms).
[19:03:01.500] <TB2> INFO: Expecting 655360 events.
[19:03:15.932] <TB2> INFO: 655360 events read in total (14028ms).
[19:03:16.046] <TB2> INFO: Expecting 655360 events.
[19:03:30.481] <TB2> INFO: 655360 events read in total (14030ms).
[19:03:30.587] <TB2> INFO: Expecting 655360 events.
[19:03:45.021] <TB2> INFO: 655360 events read in total (14031ms).
[19:03:45.135] <TB2> INFO: Expecting 655360 events.
[19:03:59.450] <TB2> INFO: 655360 events read in total (13912ms).
[19:03:59.558] <TB2> INFO: Test took 233100ms.
[19:03:59.679] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:03:59.931] <TB2> INFO: Expecting 655360 events.
[19:04:14.537] <TB2> INFO: 655360 events read in total (14014ms).
[19:04:14.558] <TB2> INFO: Expecting 655360 events.
[19:04:29.007] <TB2> INFO: 655360 events read in total (14043ms).
[19:04:29.029] <TB2> INFO: Expecting 655360 events.
[19:04:43.405] <TB2> INFO: 655360 events read in total (13973ms).
[19:04:43.427] <TB2> INFO: Expecting 655360 events.
[19:04:57.512] <TB2> INFO: 655360 events read in total (13682ms).
[19:04:57.541] <TB2> INFO: Expecting 655360 events.
[19:05:11.713] <TB2> INFO: 655360 events read in total (13769ms).
[19:05:11.745] <TB2> INFO: Expecting 655360 events.
[19:05:26.228] <TB2> INFO: 655360 events read in total (14080ms).
[19:05:26.267] <TB2> INFO: Expecting 655360 events.
[19:05:40.638] <TB2> INFO: 655360 events read in total (13968ms).
[19:05:40.759] <TB2> INFO: Expecting 655360 events.
[19:05:54.891] <TB2> INFO: 655360 events read in total (13725ms).
[19:05:54.936] <TB2> INFO: Expecting 655360 events.
[19:06:08.947] <TB2> INFO: 655360 events read in total (13607ms).
[19:06:08.998] <TB2> INFO: Expecting 655360 events.
[19:06:23.351] <TB2> INFO: 655360 events read in total (13950ms).
[19:06:23.444] <TB2> INFO: Expecting 655360 events.
[19:06:37.723] <TB2> INFO: 655360 events read in total (13876ms).
[19:06:37.801] <TB2> INFO: Expecting 655360 events.
[19:06:52.032] <TB2> INFO: 655360 events read in total (13828ms).
[19:06:52.114] <TB2> INFO: Expecting 655360 events.
[19:07:06.235] <TB2> INFO: 655360 events read in total (13717ms).
[19:07:06.325] <TB2> INFO: Expecting 655360 events.
[19:07:20.724] <TB2> INFO: 655360 events read in total (13996ms).
[19:07:20.831] <TB2> INFO: Expecting 655360 events.
[19:07:35.432] <TB2> INFO: 655360 events read in total (14197ms).
[19:07:35.539] <TB2> INFO: Expecting 655360 events.
[19:07:49.722] <TB2> INFO: 655360 events read in total (13780ms).
[19:07:49.829] <TB2> INFO: Test took 230150ms.
[19:07:50.032] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.040] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.048] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[19:07:50.056] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[19:07:50.064] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[19:07:50.072] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.080] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[19:07:50.089] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[19:07:50.094] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.100] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.107] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.113] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.119] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[19:07:50.125] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[19:07:50.131] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[19:07:50.137] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[19:07:50.143] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[19:07:50.150] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.156] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.162] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[19:07:50.169] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.174] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.181] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[19:07:50.187] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[19:07:50.193] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[19:07:50.200] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[19:07:50.206] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.213] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.223] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.234] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.245] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[19:07:50.252] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[19:07:50.259] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[19:07:50.265] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[19:07:50.271] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[19:07:50.277] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[19:07:50.283] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[19:07:50.290] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[19:07:50.296] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[19:07:50.330] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C0.dat
[19:07:50.330] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C1.dat
[19:07:50.330] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C2.dat
[19:07:50.331] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C3.dat
[19:07:50.331] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C4.dat
[19:07:50.331] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C5.dat
[19:07:50.331] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C6.dat
[19:07:50.331] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C7.dat
[19:07:50.331] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C8.dat
[19:07:50.331] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C9.dat
[19:07:50.331] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C10.dat
[19:07:50.331] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C11.dat
[19:07:50.331] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C12.dat
[19:07:50.331] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C13.dat
[19:07:50.331] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C14.dat
[19:07:50.331] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters35_C15.dat
[19:07:50.585] <TB2> INFO: Expecting 41600 events.
[19:07:53.766] <TB2> INFO: 41600 events read in total (2589ms).
[19:07:53.766] <TB2> INFO: Test took 3430ms.
[19:07:54.245] <TB2> INFO: Expecting 41600 events.
[19:07:57.265] <TB2> INFO: 41600 events read in total (2429ms).
[19:07:57.266] <TB2> INFO: Test took 3289ms.
[19:07:57.732] <TB2> INFO: Expecting 41600 events.
[19:08:00.891] <TB2> INFO: 41600 events read in total (2567ms).
[19:08:00.893] <TB2> INFO: Test took 3414ms.
[19:08:01.123] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:01.212] <TB2> INFO: Expecting 2560 events.
[19:08:02.104] <TB2> INFO: 2560 events read in total (300ms).
[19:08:02.105] <TB2> INFO: Test took 982ms.
[19:08:02.107] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:02.416] <TB2> INFO: Expecting 2560 events.
[19:08:03.300] <TB2> INFO: 2560 events read in total (293ms).
[19:08:03.301] <TB2> INFO: Test took 1194ms.
[19:08:03.303] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:03.609] <TB2> INFO: Expecting 2560 events.
[19:08:04.493] <TB2> INFO: 2560 events read in total (292ms).
[19:08:04.493] <TB2> INFO: Test took 1190ms.
[19:08:04.496] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:04.802] <TB2> INFO: Expecting 2560 events.
[19:08:05.686] <TB2> INFO: 2560 events read in total (293ms).
[19:08:05.686] <TB2> INFO: Test took 1190ms.
[19:08:05.688] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:05.994] <TB2> INFO: Expecting 2560 events.
[19:08:06.877] <TB2> INFO: 2560 events read in total (291ms).
[19:08:06.877] <TB2> INFO: Test took 1189ms.
[19:08:06.880] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:07.186] <TB2> INFO: Expecting 2560 events.
[19:08:08.078] <TB2> INFO: 2560 events read in total (300ms).
[19:08:08.078] <TB2> INFO: Test took 1198ms.
[19:08:08.080] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:08.390] <TB2> INFO: Expecting 2560 events.
[19:08:09.273] <TB2> INFO: 2560 events read in total (291ms).
[19:08:09.273] <TB2> INFO: Test took 1193ms.
[19:08:09.275] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:09.582] <TB2> INFO: Expecting 2560 events.
[19:08:10.474] <TB2> INFO: 2560 events read in total (301ms).
[19:08:10.474] <TB2> INFO: Test took 1199ms.
[19:08:10.476] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:10.783] <TB2> INFO: Expecting 2560 events.
[19:08:11.667] <TB2> INFO: 2560 events read in total (289ms).
[19:08:11.667] <TB2> INFO: Test took 1191ms.
[19:08:11.670] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:11.976] <TB2> INFO: Expecting 2560 events.
[19:08:12.858] <TB2> INFO: 2560 events read in total (290ms).
[19:08:12.858] <TB2> INFO: Test took 1188ms.
[19:08:12.861] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:13.167] <TB2> INFO: Expecting 2560 events.
[19:08:14.054] <TB2> INFO: 2560 events read in total (296ms).
[19:08:14.054] <TB2> INFO: Test took 1193ms.
[19:08:14.056] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:14.362] <TB2> INFO: Expecting 2560 events.
[19:08:15.243] <TB2> INFO: 2560 events read in total (289ms).
[19:08:15.244] <TB2> INFO: Test took 1188ms.
[19:08:15.246] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:15.551] <TB2> INFO: Expecting 2560 events.
[19:08:16.449] <TB2> INFO: 2560 events read in total (297ms).
[19:08:16.449] <TB2> INFO: Test took 1203ms.
[19:08:16.453] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:16.758] <TB2> INFO: Expecting 2560 events.
[19:08:17.640] <TB2> INFO: 2560 events read in total (291ms).
[19:08:17.640] <TB2> INFO: Test took 1187ms.
[19:08:17.643] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:17.949] <TB2> INFO: Expecting 2560 events.
[19:08:18.832] <TB2> INFO: 2560 events read in total (292ms).
[19:08:18.832] <TB2> INFO: Test took 1189ms.
[19:08:18.834] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:19.140] <TB2> INFO: Expecting 2560 events.
[19:08:20.020] <TB2> INFO: 2560 events read in total (288ms).
[19:08:20.020] <TB2> INFO: Test took 1186ms.
[19:08:20.022] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:20.328] <TB2> INFO: Expecting 2560 events.
[19:08:21.206] <TB2> INFO: 2560 events read in total (287ms).
[19:08:21.206] <TB2> INFO: Test took 1184ms.
[19:08:21.208] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:21.515] <TB2> INFO: Expecting 2560 events.
[19:08:22.392] <TB2> INFO: 2560 events read in total (286ms).
[19:08:22.393] <TB2> INFO: Test took 1185ms.
[19:08:22.395] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:22.705] <TB2> INFO: Expecting 2560 events.
[19:08:23.583] <TB2> INFO: 2560 events read in total (287ms).
[19:08:23.584] <TB2> INFO: Test took 1189ms.
[19:08:23.586] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:23.892] <TB2> INFO: Expecting 2560 events.
[19:08:24.770] <TB2> INFO: 2560 events read in total (286ms).
[19:08:24.771] <TB2> INFO: Test took 1185ms.
[19:08:24.773] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:25.080] <TB2> INFO: Expecting 2560 events.
[19:08:25.961] <TB2> INFO: 2560 events read in total (289ms).
[19:08:25.961] <TB2> INFO: Test took 1188ms.
[19:08:25.964] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:26.269] <TB2> INFO: Expecting 2560 events.
[19:08:27.149] <TB2> INFO: 2560 events read in total (288ms).
[19:08:27.149] <TB2> INFO: Test took 1185ms.
[19:08:27.151] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:27.458] <TB2> INFO: Expecting 2560 events.
[19:08:28.336] <TB2> INFO: 2560 events read in total (287ms).
[19:08:28.337] <TB2> INFO: Test took 1186ms.
[19:08:28.339] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:28.645] <TB2> INFO: Expecting 2560 events.
[19:08:29.524] <TB2> INFO: 2560 events read in total (287ms).
[19:08:29.524] <TB2> INFO: Test took 1185ms.
[19:08:29.526] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:29.832] <TB2> INFO: Expecting 2560 events.
[19:08:30.721] <TB2> INFO: 2560 events read in total (297ms).
[19:08:30.722] <TB2> INFO: Test took 1196ms.
[19:08:30.724] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:31.030] <TB2> INFO: Expecting 2560 events.
[19:08:31.912] <TB2> INFO: 2560 events read in total (291ms).
[19:08:31.913] <TB2> INFO: Test took 1189ms.
[19:08:31.916] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:32.222] <TB2> INFO: Expecting 2560 events.
[19:08:33.106] <TB2> INFO: 2560 events read in total (293ms).
[19:08:33.106] <TB2> INFO: Test took 1190ms.
[19:08:33.109] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:33.415] <TB2> INFO: Expecting 2560 events.
[19:08:34.303] <TB2> INFO: 2560 events read in total (296ms).
[19:08:34.303] <TB2> INFO: Test took 1194ms.
[19:08:34.305] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:34.612] <TB2> INFO: Expecting 2560 events.
[19:08:35.495] <TB2> INFO: 2560 events read in total (292ms).
[19:08:35.495] <TB2> INFO: Test took 1190ms.
[19:08:35.498] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:35.804] <TB2> INFO: Expecting 2560 events.
[19:08:36.695] <TB2> INFO: 2560 events read in total (299ms).
[19:08:36.695] <TB2> INFO: Test took 1198ms.
[19:08:36.697] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:37.004] <TB2> INFO: Expecting 2560 events.
[19:08:37.891] <TB2> INFO: 2560 events read in total (296ms).
[19:08:37.891] <TB2> INFO: Test took 1194ms.
[19:08:37.894] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:08:38.201] <TB2> INFO: Expecting 2560 events.
[19:08:39.086] <TB2> INFO: 2560 events read in total (293ms).
[19:08:39.086] <TB2> INFO: Test took 1193ms.
[19:08:39.567] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 638 seconds
[19:08:39.567] <TB2> INFO: PH scale (per ROC): 45 53 42 39 40 45 34 32 53 36 45 34 32 31 32 39
[19:08:39.567] <TB2> INFO: PH offset (per ROC): 115 125 101 103 97 108 114 98 122 99 106 94 111 96 94 90
[19:08:39.574] <TB2> INFO: Decoding statistics:
[19:08:39.574] <TB2> INFO: General information:
[19:08:39.574] <TB2> INFO: 16bit words read: 127882
[19:08:39.575] <TB2> INFO: valid events total: 20480
[19:08:39.575] <TB2> INFO: empty events: 17979
[19:08:39.575] <TB2> INFO: valid events with pixels: 2501
[19:08:39.575] <TB2> INFO: valid pixel hits: 2501
[19:08:39.575] <TB2> INFO: Event errors: 0
[19:08:39.575] <TB2> INFO: start marker: 0
[19:08:39.575] <TB2> INFO: stop marker: 0
[19:08:39.575] <TB2> INFO: overflow: 0
[19:08:39.575] <TB2> INFO: invalid 5bit words: 0
[19:08:39.575] <TB2> INFO: invalid XOR eye diagram: 0
[19:08:39.575] <TB2> INFO: frame (failed synchr.): 0
[19:08:39.575] <TB2> INFO: idle data (no TBM trl): 0
[19:08:39.575] <TB2> INFO: no data (only TBM hdr): 0
[19:08:39.575] <TB2> INFO: TBM errors: 0
[19:08:39.575] <TB2> INFO: flawed TBM headers: 0
[19:08:39.575] <TB2> INFO: flawed TBM trailers: 0
[19:08:39.575] <TB2> INFO: event ID mismatches: 0
[19:08:39.575] <TB2> INFO: ROC errors: 0
[19:08:39.575] <TB2> INFO: missing ROC header(s): 0
[19:08:39.575] <TB2> INFO: misplaced readback start: 0
[19:08:39.575] <TB2> INFO: Pixel decoding errors: 0
[19:08:39.575] <TB2> INFO: pixel data incomplete: 0
[19:08:39.575] <TB2> INFO: pixel address: 0
[19:08:39.575] <TB2> INFO: pulse height fill bit: 0
[19:08:39.575] <TB2> INFO: buffer corruption: 0
[19:08:39.741] <TB2> INFO: ######################################################################
[19:08:39.741] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[19:08:39.741] <TB2> INFO: ######################################################################
[19:08:39.757] <TB2> INFO: scanning low vcal = 10
[19:08:39.995] <TB2> INFO: Expecting 41600 events.
[19:08:43.554] <TB2> INFO: 41600 events read in total (2967ms).
[19:08:43.554] <TB2> INFO: Test took 3797ms.
[19:08:43.556] <TB2> INFO: scanning low vcal = 20
[19:08:43.854] <TB2> INFO: Expecting 41600 events.
[19:08:47.416] <TB2> INFO: 41600 events read in total (2970ms).
[19:08:47.416] <TB2> INFO: Test took 3860ms.
[19:08:47.418] <TB2> INFO: scanning low vcal = 30
[19:08:47.715] <TB2> INFO: Expecting 41600 events.
[19:08:51.391] <TB2> INFO: 41600 events read in total (3084ms).
[19:08:51.392] <TB2> INFO: Test took 3974ms.
[19:08:51.394] <TB2> INFO: scanning low vcal = 40
[19:08:51.672] <TB2> INFO: Expecting 41600 events.
[19:08:55.611] <TB2> INFO: 41600 events read in total (3347ms).
[19:08:55.612] <TB2> INFO: Test took 4217ms.
[19:08:55.615] <TB2> INFO: scanning low vcal = 50
[19:08:55.891] <TB2> INFO: Expecting 41600 events.
[19:08:59.872] <TB2> INFO: 41600 events read in total (3389ms).
[19:08:59.873] <TB2> INFO: Test took 4258ms.
[19:08:59.876] <TB2> INFO: scanning low vcal = 60
[19:09:00.154] <TB2> INFO: Expecting 41600 events.
[19:09:04.107] <TB2> INFO: 41600 events read in total (3361ms).
[19:09:04.108] <TB2> INFO: Test took 4232ms.
[19:09:04.111] <TB2> INFO: scanning low vcal = 70
[19:09:04.387] <TB2> INFO: Expecting 41600 events.
[19:09:08.431] <TB2> INFO: 41600 events read in total (3453ms).
[19:09:08.433] <TB2> INFO: Test took 4322ms.
[19:09:08.436] <TB2> INFO: scanning low vcal = 80
[19:09:08.807] <TB2> INFO: Expecting 41600 events.
[19:09:12.772] <TB2> INFO: 41600 events read in total (3373ms).
[19:09:12.772] <TB2> INFO: Test took 4335ms.
[19:09:12.776] <TB2> INFO: scanning low vcal = 90
[19:09:13.052] <TB2> INFO: Expecting 41600 events.
[19:09:16.989] <TB2> INFO: 41600 events read in total (3345ms).
[19:09:16.989] <TB2> INFO: Test took 4213ms.
[19:09:16.994] <TB2> INFO: scanning low vcal = 100
[19:09:17.276] <TB2> INFO: Expecting 41600 events.
[19:09:21.284] <TB2> INFO: 41600 events read in total (3417ms).
[19:09:21.285] <TB2> INFO: Test took 4291ms.
[19:09:21.288] <TB2> INFO: scanning low vcal = 110
[19:09:21.631] <TB2> INFO: Expecting 41600 events.
[19:09:25.603] <TB2> INFO: 41600 events read in total (3380ms).
[19:09:25.604] <TB2> INFO: Test took 4316ms.
[19:09:25.607] <TB2> INFO: scanning low vcal = 120
[19:09:25.883] <TB2> INFO: Expecting 41600 events.
[19:09:29.820] <TB2> INFO: 41600 events read in total (3345ms).
[19:09:29.820] <TB2> INFO: Test took 4213ms.
[19:09:29.826] <TB2> INFO: scanning low vcal = 130
[19:09:30.100] <TB2> INFO: Expecting 41600 events.
[19:09:34.083] <TB2> INFO: 41600 events read in total (3386ms).
[19:09:34.084] <TB2> INFO: Test took 4258ms.
[19:09:34.087] <TB2> INFO: scanning low vcal = 140
[19:09:34.363] <TB2> INFO: Expecting 41600 events.
[19:09:38.346] <TB2> INFO: 41600 events read in total (3391ms).
[19:09:38.347] <TB2> INFO: Test took 4260ms.
[19:09:38.350] <TB2> INFO: scanning low vcal = 150
[19:09:38.718] <TB2> INFO: Expecting 41600 events.
[19:09:42.662] <TB2> INFO: 41600 events read in total (3352ms).
[19:09:42.663] <TB2> INFO: Test took 4313ms.
[19:09:42.666] <TB2> INFO: scanning low vcal = 160
[19:09:42.943] <TB2> INFO: Expecting 41600 events.
[19:09:46.902] <TB2> INFO: 41600 events read in total (3367ms).
[19:09:46.903] <TB2> INFO: Test took 4237ms.
[19:09:46.907] <TB2> INFO: scanning low vcal = 170
[19:09:47.193] <TB2> INFO: Expecting 41600 events.
[19:09:51.161] <TB2> INFO: 41600 events read in total (3376ms).
[19:09:51.164] <TB2> INFO: Test took 4257ms.
[19:09:51.170] <TB2> INFO: scanning low vcal = 180
[19:09:51.444] <TB2> INFO: Expecting 41600 events.
[19:09:55.390] <TB2> INFO: 41600 events read in total (3355ms).
[19:09:55.391] <TB2> INFO: Test took 4221ms.
[19:09:55.394] <TB2> INFO: scanning low vcal = 190
[19:09:55.670] <TB2> INFO: Expecting 41600 events.
[19:09:59.626] <TB2> INFO: 41600 events read in total (3364ms).
[19:09:59.627] <TB2> INFO: Test took 4233ms.
[19:09:59.630] <TB2> INFO: scanning low vcal = 200
[19:09:59.906] <TB2> INFO: Expecting 41600 events.
[19:10:03.913] <TB2> INFO: 41600 events read in total (3415ms).
[19:10:03.914] <TB2> INFO: Test took 4284ms.
[19:10:03.917] <TB2> INFO: scanning low vcal = 210
[19:10:04.258] <TB2> INFO: Expecting 41600 events.
[19:10:08.216] <TB2> INFO: 41600 events read in total (3361ms).
[19:10:08.217] <TB2> INFO: Test took 4300ms.
[19:10:08.224] <TB2> INFO: scanning low vcal = 220
[19:10:08.595] <TB2> INFO: Expecting 41600 events.
[19:10:12.587] <TB2> INFO: 41600 events read in total (3401ms).
[19:10:12.588] <TB2> INFO: Test took 4364ms.
[19:10:12.591] <TB2> INFO: scanning low vcal = 230
[19:10:12.868] <TB2> INFO: Expecting 41600 events.
[19:10:16.831] <TB2> INFO: 41600 events read in total (3371ms).
[19:10:16.832] <TB2> INFO: Test took 4241ms.
[19:10:16.835] <TB2> INFO: scanning low vcal = 240
[19:10:17.111] <TB2> INFO: Expecting 41600 events.
[19:10:21.058] <TB2> INFO: 41600 events read in total (3355ms).
[19:10:21.059] <TB2> INFO: Test took 4224ms.
[19:10:21.064] <TB2> INFO: scanning low vcal = 250
[19:10:21.434] <TB2> INFO: Expecting 41600 events.
[19:10:25.409] <TB2> INFO: 41600 events read in total (3383ms).
[19:10:25.410] <TB2> INFO: Test took 4346ms.
[19:10:25.414] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[19:10:25.690] <TB2> INFO: Expecting 41600 events.
[19:10:29.638] <TB2> INFO: 41600 events read in total (3356ms).
[19:10:29.638] <TB2> INFO: Test took 4224ms.
[19:10:29.641] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[19:10:29.918] <TB2> INFO: Expecting 41600 events.
[19:10:33.903] <TB2> INFO: 41600 events read in total (3393ms).
[19:10:33.904] <TB2> INFO: Test took 4262ms.
[19:10:33.907] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[19:10:34.183] <TB2> INFO: Expecting 41600 events.
[19:10:38.247] <TB2> INFO: 41600 events read in total (3472ms).
[19:10:38.248] <TB2> INFO: Test took 4341ms.
[19:10:38.252] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[19:10:38.528] <TB2> INFO: Expecting 41600 events.
[19:10:42.488] <TB2> INFO: 41600 events read in total (3368ms).
[19:10:42.489] <TB2> INFO: Test took 4237ms.
[19:10:42.492] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[19:10:42.769] <TB2> INFO: Expecting 41600 events.
[19:10:46.714] <TB2> INFO: 41600 events read in total (3353ms).
[19:10:46.715] <TB2> INFO: Test took 4222ms.
[19:10:47.216] <TB2> INFO: PixTestGainPedestal::measure() done
[19:11:31.467] <TB2> INFO: PixTestGainPedestal::fit() done
[19:11:31.467] <TB2> INFO: non-linearity mean: 0.957 0.981 0.924 0.931 0.920 0.944 0.926 0.949 0.985 0.929 0.964 0.924 0.930 0.966 1.036 0.935
[19:11:31.467] <TB2> INFO: non-linearity RMS: 0.041 0.003 0.138 0.093 0.081 0.080 0.137 0.207 0.003 0.099 0.025 0.069 0.115 0.192 0.187 0.103
[19:11:31.467] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[19:11:31.481] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[19:11:31.494] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[19:11:31.509] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[19:11:31.524] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[19:11:31.540] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[19:11:31.554] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[19:11:31.570] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[19:11:31.585] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[19:11:31.599] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[19:11:31.612] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[19:11:31.626] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[19:11:31.639] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[19:11:31.652] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[19:11:31.666] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[19:11:31.679] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[19:11:31.692] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 171 seconds
[19:11:31.692] <TB2> INFO: Decoding statistics:
[19:11:31.692] <TB2> INFO: General information:
[19:11:31.692] <TB2> INFO: 16bit words read: 3313672
[19:11:31.692] <TB2> INFO: valid events total: 332800
[19:11:31.692] <TB2> INFO: empty events: 51
[19:11:31.692] <TB2> INFO: valid events with pixels: 332749
[19:11:31.692] <TB2> INFO: valid pixel hits: 658436
[19:11:31.692] <TB2> INFO: Event errors: 0
[19:11:31.692] <TB2> INFO: start marker: 0
[19:11:31.692] <TB2> INFO: stop marker: 0
[19:11:31.692] <TB2> INFO: overflow: 0
[19:11:31.692] <TB2> INFO: invalid 5bit words: 0
[19:11:31.692] <TB2> INFO: invalid XOR eye diagram: 0
[19:11:31.692] <TB2> INFO: frame (failed synchr.): 0
[19:11:31.692] <TB2> INFO: idle data (no TBM trl): 0
[19:11:31.692] <TB2> INFO: no data (only TBM hdr): 0
[19:11:31.692] <TB2> INFO: TBM errors: 0
[19:11:31.692] <TB2> INFO: flawed TBM headers: 0
[19:11:31.692] <TB2> INFO: flawed TBM trailers: 0
[19:11:31.692] <TB2> INFO: event ID mismatches: 0
[19:11:31.692] <TB2> INFO: ROC errors: 0
[19:11:31.692] <TB2> INFO: missing ROC header(s): 0
[19:11:31.693] <TB2> INFO: misplaced readback start: 0
[19:11:31.693] <TB2> INFO: Pixel decoding errors: 0
[19:11:31.693] <TB2> INFO: pixel data incomplete: 0
[19:11:31.693] <TB2> INFO: pixel address: 0
[19:11:31.693] <TB2> INFO: pulse height fill bit: 0
[19:11:31.693] <TB2> INFO: buffer corruption: 0
[19:11:31.711] <TB2> INFO: Decoding statistics:
[19:11:31.711] <TB2> INFO: General information:
[19:11:31.711] <TB2> INFO: 16bit words read: 3443090
[19:11:31.711] <TB2> INFO: valid events total: 353536
[19:11:31.711] <TB2> INFO: empty events: 18286
[19:11:31.711] <TB2> INFO: valid events with pixels: 335250
[19:11:31.711] <TB2> INFO: valid pixel hits: 660937
[19:11:31.711] <TB2> INFO: Event errors: 0
[19:11:31.711] <TB2> INFO: start marker: 0
[19:11:31.711] <TB2> INFO: stop marker: 0
[19:11:31.711] <TB2> INFO: overflow: 0
[19:11:31.711] <TB2> INFO: invalid 5bit words: 0
[19:11:31.711] <TB2> INFO: invalid XOR eye diagram: 0
[19:11:31.711] <TB2> INFO: frame (failed synchr.): 0
[19:11:31.711] <TB2> INFO: idle data (no TBM trl): 0
[19:11:31.711] <TB2> INFO: no data (only TBM hdr): 0
[19:11:31.711] <TB2> INFO: TBM errors: 0
[19:11:31.711] <TB2> INFO: flawed TBM headers: 0
[19:11:31.711] <TB2> INFO: flawed TBM trailers: 0
[19:11:31.711] <TB2> INFO: event ID mismatches: 0
[19:11:31.711] <TB2> INFO: ROC errors: 0
[19:11:31.711] <TB2> INFO: missing ROC header(s): 0
[19:11:31.711] <TB2> INFO: misplaced readback start: 0
[19:11:31.711] <TB2> INFO: Pixel decoding errors: 0
[19:11:31.711] <TB2> INFO: pixel data incomplete: 0
[19:11:31.711] <TB2> INFO: pixel address: 0
[19:11:31.711] <TB2> INFO: pulse height fill bit: 0
[19:11:31.711] <TB2> INFO: buffer corruption: 0
[19:11:31.711] <TB2> INFO: enter test to run
[19:11:31.711] <TB2> INFO: test: trim80 no parameter change
[19:11:31.711] <TB2> INFO: running: trim80
[19:11:31.718] <TB2> INFO: ######################################################################
[19:11:31.719] <TB2> INFO: PixTestTrim80::doTest()
[19:11:31.719] <TB2> INFO: ######################################################################
[19:11:31.720] <TB2> INFO: ----------------------------------------------------------------------
[19:11:31.720] <TB2> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[19:11:31.720] <TB2> INFO: ----------------------------------------------------------------------
[19:11:31.762] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[19:11:31.762] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[19:11:31.776] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:11:31.776] <TB2> INFO: run 1 of 1
[19:11:32.079] <TB2> INFO: Expecting 5025280 events.
[19:12:01.958] <TB2> INFO: 677576 events read in total (29287ms).
[19:12:29.687] <TB2> INFO: 1352536 events read in total (57016ms).
[19:12:57.500] <TB2> INFO: 2025576 events read in total (84829ms).
[19:13:25.521] <TB2> INFO: 2698200 events read in total (112850ms).
[19:13:53.590] <TB2> INFO: 3370232 events read in total (140919ms).
[19:14:21.585] <TB2> INFO: 4040712 events read in total (168914ms).
[19:14:48.918] <TB2> INFO: 4709584 events read in total (196247ms).
[19:15:02.458] <TB2> INFO: 5025280 events read in total (209787ms).
[19:15:02.561] <TB2> INFO: Test took 210784ms.
[19:15:28.481] <TB2> INFO: ROC 0 VthrComp = 71
[19:15:28.481] <TB2> INFO: ROC 1 VthrComp = 67
[19:15:28.481] <TB2> INFO: ROC 2 VthrComp = 74
[19:15:28.484] <TB2> INFO: ROC 3 VthrComp = 71
[19:15:28.484] <TB2> INFO: ROC 4 VthrComp = 75
[19:15:28.484] <TB2> INFO: ROC 5 VthrComp = 61
[19:15:28.484] <TB2> INFO: ROC 6 VthrComp = 71
[19:15:28.484] <TB2> INFO: ROC 7 VthrComp = 73
[19:15:28.484] <TB2> INFO: ROC 8 VthrComp = 73
[19:15:28.484] <TB2> INFO: ROC 9 VthrComp = 73
[19:15:28.484] <TB2> INFO: ROC 10 VthrComp = 71
[19:15:28.484] <TB2> INFO: ROC 11 VthrComp = 73
[19:15:28.485] <TB2> INFO: ROC 12 VthrComp = 74
[19:15:28.485] <TB2> INFO: ROC 13 VthrComp = 74
[19:15:28.485] <TB2> INFO: ROC 14 VthrComp = 72
[19:15:28.485] <TB2> INFO: ROC 15 VthrComp = 72
[19:15:28.752] <TB2> INFO: Expecting 41600 events.
[19:15:32.321] <TB2> INFO: 41600 events read in total (2977ms).
[19:15:32.322] <TB2> INFO: Test took 3836ms.
[19:15:32.332] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[19:15:32.332] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[19:15:32.346] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:15:32.346] <TB2> INFO: run 1 of 1
[19:15:32.629] <TB2> INFO: Expecting 5025280 events.
[19:16:01.975] <TB2> INFO: 688848 events read in total (28754ms).
[19:16:30.284] <TB2> INFO: 1372264 events read in total (57063ms).
[19:16:59.131] <TB2> INFO: 2053440 events read in total (85910ms).
[19:17:27.631] <TB2> INFO: 2730576 events read in total (114410ms).
[19:17:55.767] <TB2> INFO: 3402856 events read in total (142546ms).
[19:18:23.744] <TB2> INFO: 4072536 events read in total (170523ms).
[19:18:51.956] <TB2> INFO: 4740464 events read in total (198735ms).
[19:19:04.220] <TB2> INFO: 5025280 events read in total (210999ms).
[19:19:04.282] <TB2> INFO: Test took 211935ms.
[19:19:35.533] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 107.917 for pixel 0/45 mean/min/max = 91.0519/74.1514/107.952
[19:19:35.534] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 105.259 for pixel 7/9 mean/min/max = 89.3236/73.1695/105.478
[19:19:35.535] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 107.713 for pixel 0/31 mean/min/max = 92.8678/77.9231/107.813
[19:19:35.536] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 113.882 for pixel 12/79 mean/min/max = 93.5287/73.1674/113.89
[19:19:35.537] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 108.209 for pixel 17/79 mean/min/max = 92.7678/77.0773/108.458
[19:19:35.538] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 109.233 for pixel 0/71 mean/min/max = 92.98/76.4951/109.465
[19:19:35.539] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 103.747 for pixel 0/12 mean/min/max = 88.9599/73.8735/104.046
[19:19:35.539] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 111.541 for pixel 0/38 mean/min/max = 94.7295/77.8757/111.583
[19:19:35.540] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 107.707 for pixel 28/33 mean/min/max = 92.5728/77.1416/108.004
[19:19:35.541] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 109.233 for pixel 7/41 mean/min/max = 92.9548/76.5312/109.378
[19:19:35.541] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 110.359 for pixel 0/2 mean/min/max = 91.9861/73.4982/110.474
[19:19:35.542] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 113.409 for pixel 0/50 mean/min/max = 94.9393/76.4334/113.445
[19:19:35.542] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 109.207 for pixel 0/54 mean/min/max = 93.0824/76.9438/109.221
[19:19:35.543] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 108.755 for pixel 51/76 mean/min/max = 93.0041/77.2285/108.78
[19:19:35.543] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 105.861 for pixel 0/20 mean/min/max = 91.5591/77.1964/105.922
[19:19:35.544] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 109.763 for pixel 11/79 mean/min/max = 93.1461/76.5282/109.764
[19:19:35.544] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:19:35.633] <TB2> INFO: Expecting 411648 events.
[19:19:45.184] <TB2> INFO: 411648 events read in total (8959ms).
[19:19:45.195] <TB2> INFO: Expecting 411648 events.
[19:19:54.487] <TB2> INFO: 411648 events read in total (8888ms).
[19:19:54.500] <TB2> INFO: Expecting 411648 events.
[19:20:03.944] <TB2> INFO: 411648 events read in total (9037ms).
[19:20:03.959] <TB2> INFO: Expecting 411648 events.
[19:20:13.500] <TB2> INFO: 411648 events read in total (9138ms).
[19:20:13.518] <TB2> INFO: Expecting 411648 events.
[19:20:22.827] <TB2> INFO: 411648 events read in total (8906ms).
[19:20:22.848] <TB2> INFO: Expecting 411648 events.
[19:20:32.191] <TB2> INFO: 411648 events read in total (8940ms).
[19:20:32.222] <TB2> INFO: Expecting 411648 events.
[19:20:41.486] <TB2> INFO: 411648 events read in total (8861ms).
[19:20:41.521] <TB2> INFO: Expecting 411648 events.
[19:20:50.801] <TB2> INFO: 411648 events read in total (8877ms).
[19:20:50.841] <TB2> INFO: Expecting 411648 events.
[19:21:00.308] <TB2> INFO: 411648 events read in total (9064ms).
[19:21:00.359] <TB2> INFO: Expecting 411648 events.
[19:21:09.895] <TB2> INFO: 411648 events read in total (9133ms).
[19:21:09.935] <TB2> INFO: Expecting 411648 events.
[19:21:19.352] <TB2> INFO: 411648 events read in total (9013ms).
[19:21:19.398] <TB2> INFO: Expecting 411648 events.
[19:21:28.600] <TB2> INFO: 411648 events read in total (8799ms).
[19:21:28.657] <TB2> INFO: Expecting 411648 events.
[19:21:38.013] <TB2> INFO: 411648 events read in total (8953ms).
[19:21:38.077] <TB2> INFO: Expecting 411648 events.
[19:21:47.367] <TB2> INFO: 411648 events read in total (8887ms).
[19:21:47.416] <TB2> INFO: Expecting 411648 events.
[19:21:56.707] <TB2> INFO: 411648 events read in total (8888ms).
[19:21:56.800] <TB2> INFO: Expecting 411648 events.
[19:22:05.956] <TB2> INFO: 411648 events read in total (8753ms).
[19:22:06.012] <TB2> INFO: Test took 150468ms.
[19:22:07.861] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[19:22:07.877] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:22:07.877] <TB2> INFO: run 1 of 1
[19:22:08.125] <TB2> INFO: Expecting 5025280 events.
[19:22:36.051] <TB2> INFO: 671712 events read in total (27335ms).
[19:23:03.746] <TB2> INFO: 1339992 events read in total (55030ms).
[19:23:31.708] <TB2> INFO: 2007264 events read in total (82992ms).
[19:23:59.695] <TB2> INFO: 2672008 events read in total (110979ms).
[19:24:27.397] <TB2> INFO: 3332512 events read in total (138681ms).
[19:24:55.598] <TB2> INFO: 3989912 events read in total (166882ms).
[19:25:23.409] <TB2> INFO: 4645120 events read in total (194693ms).
[19:25:40.114] <TB2> INFO: 5025280 events read in total (211398ms).
[19:25:40.206] <TB2> INFO: Test took 212329ms.
[19:26:09.991] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 49.785348 .. 103.858623
[19:26:10.285] <TB2> INFO: Expecting 208000 events.
[19:26:20.081] <TB2> INFO: 208000 events read in total (9204ms).
[19:26:20.082] <TB2> INFO: Test took 10087ms.
[19:26:20.132] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 39 .. 113 (-1/-1) hits flags = 528 (plus default)
[19:26:20.146] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:26:20.146] <TB2> INFO: run 1 of 1
[19:26:20.434] <TB2> INFO: Expecting 2496000 events.
[19:26:50.228] <TB2> INFO: 690648 events read in total (29203ms).
[19:27:19.325] <TB2> INFO: 1379448 events read in total (58300ms).
[19:27:49.431] <TB2> INFO: 2059664 events read in total (88406ms).
[19:28:08.336] <TB2> INFO: 2496000 events read in total (107311ms).
[19:28:08.379] <TB2> INFO: Test took 108232ms.
[19:28:30.153] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 62.271119 .. 93.666579
[19:28:30.404] <TB2> INFO: Expecting 208000 events.
[19:28:40.275] <TB2> INFO: 208000 events read in total (9279ms).
[19:28:40.276] <TB2> INFO: Test took 10121ms.
[19:28:40.323] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 52 .. 103 (-1/-1) hits flags = 528 (plus default)
[19:28:40.337] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:28:40.337] <TB2> INFO: run 1 of 1
[19:28:40.615] <TB2> INFO: Expecting 1730560 events.
[19:29:09.675] <TB2> INFO: 685752 events read in total (28468ms).
[19:29:39.696] <TB2> INFO: 1371256 events read in total (58489ms).
[19:29:55.708] <TB2> INFO: 1730560 events read in total (74501ms).
[19:29:55.747] <TB2> INFO: Test took 75410ms.
[19:30:18.119] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 65.875937 .. 87.706071
[19:30:18.357] <TB2> INFO: Expecting 208000 events.
[19:30:28.589] <TB2> INFO: 208000 events read in total (9641ms).
[19:30:28.590] <TB2> INFO: Test took 10469ms.
[19:30:28.640] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 55 .. 97 (-1/-1) hits flags = 528 (plus default)
[19:30:28.652] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:30:28.652] <TB2> INFO: run 1 of 1
[19:30:28.932] <TB2> INFO: Expecting 1431040 events.
[19:30:58.884] <TB2> INFO: 702040 events read in total (29361ms).
[19:31:28.829] <TB2> INFO: 1403496 events read in total (59306ms).
[19:31:30.487] <TB2> INFO: 1431040 events read in total (60964ms).
[19:31:30.522] <TB2> INFO: Test took 61870ms.
[19:31:52.577] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 68.924438 .. 87.239863
[19:31:52.886] <TB2> INFO: Expecting 208000 events.
[19:32:03.840] <TB2> INFO: 208000 events read in total (10362ms).
[19:32:03.840] <TB2> INFO: Test took 11262ms.
[19:32:03.893] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 58 .. 97 (-1/-1) hits flags = 528 (plus default)
[19:32:03.907] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:32:03.907] <TB2> INFO: run 1 of 1
[19:32:04.197] <TB2> INFO: Expecting 1331200 events.
[19:32:33.699] <TB2> INFO: 692512 events read in total (28908ms).
[19:33:01.250] <TB2> INFO: 1331200 events read in total (56459ms).
[19:33:01.287] <TB2> INFO: Test took 57380ms.
[19:33:21.976] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[19:33:21.976] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[19:33:21.991] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:33:21.991] <TB2> INFO: run 1 of 1
[19:33:22.321] <TB2> INFO: Expecting 1364480 events.
[19:33:52.287] <TB2> INFO: 669280 events read in total (29374ms).
[19:34:21.410] <TB2> INFO: 1338128 events read in total (58498ms).
[19:34:22.940] <TB2> INFO: 1364480 events read in total (60027ms).
[19:34:22.966] <TB2> INFO: Test took 60974ms.
[19:34:42.335] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C0.dat
[19:34:42.335] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C1.dat
[19:34:42.335] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C2.dat
[19:34:42.335] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C3.dat
[19:34:42.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C4.dat
[19:34:42.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C5.dat
[19:34:42.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C6.dat
[19:34:42.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C7.dat
[19:34:42.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C8.dat
[19:34:42.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C9.dat
[19:34:42.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C10.dat
[19:34:42.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C11.dat
[19:34:42.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C12.dat
[19:34:42.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C13.dat
[19:34:42.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C14.dat
[19:34:42.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//dacParameters80_C15.dat
[19:34:42.337] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C0.dat
[19:34:42.343] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C1.dat
[19:34:42.348] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C2.dat
[19:34:42.353] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C3.dat
[19:34:42.360] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C4.dat
[19:34:42.369] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C5.dat
[19:34:42.378] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C6.dat
[19:34:42.387] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C7.dat
[19:34:42.395] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C8.dat
[19:34:42.403] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C9.dat
[19:34:42.410] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C10.dat
[19:34:42.417] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C11.dat
[19:34:42.424] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C12.dat
[19:34:42.431] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C13.dat
[19:34:42.439] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C14.dat
[19:34:42.446] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1110_FullQualification_2016-11-02_15h17m_1478096238//003_FulltestTrim80_p17//trimParameters80_C15.dat
[19:34:42.453] <TB2> INFO: PixTestTrim80::trimTest() done
[19:34:42.453] <TB2> INFO: vtrim: 89 83 92 117 103 88 77 113 108 97 99 109 89 98 90 109
[19:34:42.453] <TB2> INFO: vthrcomp: 71 67 74 71 75 61 71 73 73 73 71 73 74 74 72 72
[19:34:42.453] <TB2> INFO: vcal mean: 79.94 79.96 79.96 79.99 80.03 80.02 79.96 80.00 80.00 80.00 80.00 80.00 80.01 80.02 80.00 79.99
[19:34:42.453] <TB2> INFO: vcal RMS: 0.77 0.75 0.72 0.85 0.73 0.72 0.75 0.77 0.73 0.72 0.78 0.74 0.73 0.74 0.72 0.75
[19:34:42.453] <TB2> INFO: bits mean: 10.12 10.59 9.14 10.12 9.24 9.62 10.28 9.45 9.78 9.78 10.05 9.57 9.16 9.50 9.15 9.79
[19:34:42.453] <TB2> INFO: bits RMS: 2.52 2.44 2.37 2.48 2.36 2.33 2.57 2.24 2.25 2.32 2.56 2.31 2.54 2.30 2.49 2.27
[19:34:42.460] <TB2> INFO: ----------------------------------------------------------------------
[19:34:42.460] <TB2> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[19:34:42.460] <TB2> INFO: ----------------------------------------------------------------------
[19:34:42.462] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[19:34:42.478] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[19:34:42.478] <TB2> INFO: run 1 of 1
[19:34:42.765] <TB2> INFO: Expecting 4160000 events.
[19:35:17.028] <TB2> INFO: 761970 events read in total (33671ms).
[19:35:50.032] <TB2> INFO: 1517395 events read in total (66675ms).
[19:36:23.596] <TB2> INFO: 2266380 events read in total (100239ms).
[19:36:56.056] <TB2> INFO: 3009790 events read in total (132699ms).
[19:37:28.848] <TB2> INFO: 3749625 events read in total (165491ms).
[19:37:47.513] <TB2> INFO: 4160000 events read in total (184156ms).
[19:37:47.600] <TB2> INFO: Test took 185121ms.
[19:38:16.515] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 200 (-1/-1) hits flags = 528 (plus default)
[19:38:16.531] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[19:38:16.531] <TB2> INFO: run 1 of 1
[19:38:16.820] <TB2> INFO: Expecting 4180800 events.
[19:38:50.037] <TB2> INFO: 734930 events read in total (32625ms).
[19:39:22.518] <TB2> INFO: 1463505 events read in total (65106ms).
[19:39:55.180] <TB2> INFO: 2187190 events read in total (97768ms).
[19:40:27.893] <TB2> INFO: 2905260 events read in total (130481ms).
[19:41:00.395] <TB2> INFO: 3619975 events read in total (162983ms).
[19:41:26.645] <TB2> INFO: 4180800 events read in total (189233ms).
[19:41:26.743] <TB2> INFO: Test took 190211ms.
[19:41:55.668] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 186 (-1/-1) hits flags = 528 (plus default)
[19:41:55.683] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[19:41:55.683] <TB2> INFO: run 1 of 1
[19:41:55.941] <TB2> INFO: Expecting 3889600 events.
[19:42:29.970] <TB2> INFO: 756240 events read in total (33439ms).
[19:43:03.409] <TB2> INFO: 1505135 events read in total (66877ms).
[19:43:37.267] <TB2> INFO: 2248010 events read in total (100735ms).
[19:44:10.665] <TB2> INFO: 2983845 events read in total (134133ms).
[19:44:43.911] <TB2> INFO: 3716775 events read in total (167379ms).
[19:44:52.035] <TB2> INFO: 3889600 events read in total (175503ms).
[19:44:52.129] <TB2> INFO: Test took 176447ms.
[19:45:21.608] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 185 (-1/-1) hits flags = 528 (plus default)
[19:45:21.622] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[19:45:21.622] <TB2> INFO: run 1 of 1
[19:45:21.879] <TB2> INFO: Expecting 3868800 events.
[19:45:55.237] <TB2> INFO: 758000 events read in total (32766ms).
[19:46:27.785] <TB2> INFO: 1508440 events read in total (65314ms).
[19:47:00.361] <TB2> INFO: 2252870 events read in total (97890ms).
[19:47:33.882] <TB2> INFO: 2990615 events read in total (131411ms).
[19:48:06.251] <TB2> INFO: 3725615 events read in total (163780ms).
[19:48:13.024] <TB2> INFO: 3868800 events read in total (170553ms).
[19:48:13.095] <TB2> INFO: Test took 171474ms.
[19:48:42.453] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 185 (-1/-1) hits flags = 528 (plus default)
[19:48:42.468] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[19:48:42.468] <TB2> INFO: run 1 of 1
[19:48:42.745] <TB2> INFO: Expecting 3868800 events.
[19:49:15.974] <TB2> INFO: 758495 events read in total (32637ms).
[19:49:48.292] <TB2> INFO: 1508790 events read in total (64955ms).
[19:50:20.565] <TB2> INFO: 2252985 events read in total (97228ms).
[19:50:53.623] <TB2> INFO: 2990975 events read in total (130286ms).
[19:51:26.794] <TB2> INFO: 3726605 events read in total (163457ms).
[19:51:33.494] <TB2> INFO: 3868800 events read in total (170157ms).
[19:51:33.564] <TB2> INFO: Test took 171096ms.
[19:52:07.617] <TB2> INFO: PixTestTrim80::trimBitTest() done
[19:52:07.619] <TB2> INFO: PixTestTrim80::doTest() done, duration: 2435 seconds
[19:52:08.389] <TB2> INFO: enter test to run
[19:52:08.389] <TB2> INFO: test: exit no parameter change
[19:52:08.668] <TB2> QUIET: Connection to board 149 closed.
[19:52:08.703] <TB2> INFO: pXar: this is the end, my friend