[12:23:12.164] <TB3> INFO: *** Welcome to pxar ***
[12:23:12.164] <TB3> INFO: *** Today: 2016/11/02
[12:23:12.170] <TB3> INFO: *** Version: c8ba-dirty
[12:23:12.170] <TB3> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:23:12.171] <TB3> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:23:12.171] <TB3> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//defaultMaskFile.dat
[12:23:12.171] <TB3> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters_C15.dat
[12:23:12.252] <TB3> INFO: clk: 4
[12:23:12.252] <TB3> INFO: ctr: 4
[12:23:12.252] <TB3> INFO: sda: 19
[12:23:12.252] <TB3> INFO: tin: 9
[12:23:12.252] <TB3> INFO: level: 15
[12:23:12.252] <TB3> INFO: triggerdelay: 0
[12:23:12.252] <TB3> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[12:23:12.252] <TB3> INFO: Log level: INFO
[12:23:12.262] <TB3> INFO: Found DTB DTB_WZ4I6J
[12:23:12.270] <TB3> QUIET: Connection to board DTB_WZ4I6J opened.
[12:23:12.272] <TB3> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 170
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WZ4I6J
MAC address: 40D8551180AA
Hostname: pixelDTB170
Comment:
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[12:23:12.274] <TB3> INFO: RPC call hashes of host and DTB match: 486171790
[12:23:13.776] <TB3> INFO: DUT info:
[12:23:13.776] <TB3> INFO: The DUT currently contains the following objects:
[12:23:13.776] <TB3> INFO: 4 TBM Cores tbm10c (4 ON)
[12:23:13.776] <TB3> INFO: TBM Core alpha (0): 7 registers set
[12:23:13.776] <TB3> INFO: TBM Core beta (1): 7 registers set
[12:23:13.776] <TB3> INFO: TBM Core alpha (2): 7 registers set
[12:23:13.776] <TB3> INFO: TBM Core beta (3): 7 registers set
[12:23:13.776] <TB3> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[12:23:13.776] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:13.776] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:23:14.177] <TB3> INFO: enter 'restricted' command line mode
[12:23:14.177] <TB3> INFO: enter test to run
[12:23:14.177] <TB3> INFO: test: pretest no parameter change
[12:23:14.177] <TB3> INFO: running: pretest
[12:23:14.720] <TB3> INFO: ######################################################################
[12:23:14.720] <TB3> INFO: PixTestPretest::doTest()
[12:23:14.720] <TB3> INFO: ######################################################################
[12:23:14.721] <TB3> INFO: ----------------------------------------------------------------------
[12:23:14.721] <TB3> INFO: PixTestPretest::programROC()
[12:23:14.721] <TB3> INFO: ----------------------------------------------------------------------
[12:23:32.734] <TB3> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:23:32.734] <TB3> INFO: IA differences per ROC: 18.5 20.9 20.9 20.1 20.9 17.7 19.3 22.5 17.7 19.3 20.1 20.9 19.3 16.9 19.3 22.5
[12:23:32.774] <TB3> INFO: ----------------------------------------------------------------------
[12:23:32.774] <TB3> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:23:32.774] <TB3> INFO: ----------------------------------------------------------------------
[12:23:39.753] <TB3> INFO: PixTestPretest::setVana() done, Module Ia 391.5 mA = 24.4688 mA/ROC
[12:23:39.753] <TB3> INFO: i(loss) [mA/ROC]: 19.3 18.5 19.3 19.3 20.1 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 18.5 19.3
[12:23:39.782] <TB3> INFO: ----------------------------------------------------------------------
[12:23:39.782] <TB3> INFO: PixTestPretest::findTiming()
[12:23:39.782] <TB3> INFO: ----------------------------------------------------------------------
[12:23:39.782] <TB3> INFO: PixTestCmd::init()

[12:24:10.951] <TB3> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:24:10.951] <TB3> INFO: (success/tries = 100/100), width = 4
[12:24:12.449] <TB3> INFO: ----------------------------------------------------------------------
[12:24:12.449] <TB3> INFO: PixTestPretest::findWorkingPixel()
[12:24:12.449] <TB3> INFO: ----------------------------------------------------------------------
[12:24:12.541] <TB3> INFO: Expecting 231680 events.
[12:24:22.211] <TB3> INFO: 231680 events read in total (9079ms).
[12:24:22.219] <TB3> INFO: Test took 9768ms.
[12:24:22.467] <TB3> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:24:22.497] <TB3> INFO: ----------------------------------------------------------------------
[12:24:22.497] <TB3> INFO: PixTestPretest::setVthrCompCalDel()
[12:24:22.497] <TB3> INFO: ----------------------------------------------------------------------
[12:24:22.589] <TB3> INFO: Expecting 231680 events.
[12:24:32.261] <TB3> INFO: 231680 events read in total (9081ms).
[12:24:32.272] <TB3> INFO: Test took 9771ms.
[12:24:32.534] <TB3> INFO: PixTestPretest::setVthrCompCalDel() done
[12:24:32.534] <TB3> INFO: CalDel: 84 75 91 83 84 78 88 69 107 79 85 100 108 114 100 99
[12:24:32.534] <TB3> INFO: VthrComp: 51 51 51 51 51 51 51 53 51 51 51 51 51 51 51 51
[12:24:32.537] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C0.dat
[12:24:32.537] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C1.dat
[12:24:32.538] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C2.dat
[12:24:32.538] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C3.dat
[12:24:32.538] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C4.dat
[12:24:32.538] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C5.dat
[12:24:32.538] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C6.dat
[12:24:32.538] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C7.dat
[12:24:32.538] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C8.dat
[12:24:32.538] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C9.dat
[12:24:32.538] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C10.dat
[12:24:32.538] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C11.dat
[12:24:32.538] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C12.dat
[12:24:32.538] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C13.dat
[12:24:32.539] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C14.dat
[12:24:32.539] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:24:32.539] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[12:24:32.539] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[12:24:32.539] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[12:24:32.539] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:24:32.539] <TB3> INFO: PixTestPretest::doTest() done, duration: 78 seconds
[12:24:32.644] <TB3> INFO: enter test to run
[12:24:32.644] <TB3> INFO: test: fulltest no parameter change
[12:24:32.644] <TB3> INFO: running: fulltest
[12:24:32.644] <TB3> INFO: ######################################################################
[12:24:32.644] <TB3> INFO: PixTestFullTest::doTest()
[12:24:32.644] <TB3> INFO: ######################################################################
[12:24:32.646] <TB3> INFO: ######################################################################
[12:24:32.646] <TB3> INFO: PixTestAlive::doTest()
[12:24:32.646] <TB3> INFO: ######################################################################
[12:24:32.647] <TB3> INFO: ----------------------------------------------------------------------
[12:24:32.647] <TB3> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:24:32.647] <TB3> INFO: ----------------------------------------------------------------------
[12:24:32.883] <TB3> INFO: Expecting 41600 events.
[12:24:36.329] <TB3> INFO: 41600 events read in total (2854ms).
[12:24:36.330] <TB3> INFO: Test took 3682ms.
[12:24:36.555] <TB3> INFO: PixTestAlive::aliveTest() done
[12:24:36.555] <TB3> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:24:36.557] <TB3> INFO: ----------------------------------------------------------------------
[12:24:36.557] <TB3> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:24:36.557] <TB3> INFO: ----------------------------------------------------------------------
[12:24:36.790] <TB3> INFO: Expecting 41600 events.
[12:24:39.806] <TB3> INFO: 41600 events read in total (2425ms).
[12:24:39.806] <TB3> INFO: Test took 3248ms.
[12:24:39.807] <TB3> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:24:40.044] <TB3> INFO: PixTestAlive::maskTest() done
[12:24:40.044] <TB3> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:24:40.045] <TB3> INFO: ----------------------------------------------------------------------
[12:24:40.045] <TB3> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:24:40.045] <TB3> INFO: ----------------------------------------------------------------------
[12:24:40.278] <TB3> INFO: Expecting 41600 events.
[12:24:43.715] <TB3> INFO: 41600 events read in total (2845ms).
[12:24:43.716] <TB3> INFO: Test took 3669ms.
[12:24:43.947] <TB3> INFO: PixTestAlive::addressDecodingTest() done
[12:24:43.947] <TB3> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:24:43.948] <TB3> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:24:43.948] <TB3> INFO: Decoding statistics:
[12:24:43.948] <TB3> INFO: General information:
[12:24:43.948] <TB3> INFO: 16bit words read: 0
[12:24:43.948] <TB3> INFO: valid events total: 0
[12:24:43.948] <TB3> INFO: empty events: 0
[12:24:43.948] <TB3> INFO: valid events with pixels: 0
[12:24:43.948] <TB3> INFO: valid pixel hits: 0
[12:24:43.948] <TB3> INFO: Event errors: 0
[12:24:43.948] <TB3> INFO: start marker: 0
[12:24:43.948] <TB3> INFO: stop marker: 0
[12:24:43.948] <TB3> INFO: overflow: 0
[12:24:43.948] <TB3> INFO: invalid 5bit words: 0
[12:24:43.948] <TB3> INFO: invalid XOR eye diagram: 0
[12:24:43.948] <TB3> INFO: frame (failed synchr.): 0
[12:24:43.948] <TB3> INFO: idle data (no TBM trl): 0
[12:24:43.948] <TB3> INFO: no data (only TBM hdr): 0
[12:24:43.948] <TB3> INFO: TBM errors: 0
[12:24:43.948] <TB3> INFO: flawed TBM headers: 0
[12:24:43.948] <TB3> INFO: flawed TBM trailers: 0
[12:24:43.948] <TB3> INFO: event ID mismatches: 0
[12:24:43.948] <TB3> INFO: ROC errors: 0
[12:24:43.948] <TB3> INFO: missing ROC header(s): 0
[12:24:43.948] <TB3> INFO: misplaced readback start: 0
[12:24:43.948] <TB3> INFO: Pixel decoding errors: 0
[12:24:43.948] <TB3> INFO: pixel data incomplete: 0
[12:24:43.948] <TB3> INFO: pixel address: 0
[12:24:43.948] <TB3> INFO: pulse height fill bit: 0
[12:24:43.948] <TB3> INFO: buffer corruption: 0
[12:24:43.955] <TB3> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:24:43.955] <TB3> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[12:24:43.955] <TB3> INFO: ######################################################################
[12:24:43.955] <TB3> INFO: PixTestReadback::doTest()
[12:24:43.955] <TB3> INFO: ######################################################################
[12:24:43.955] <TB3> INFO: ----------------------------------------------------------------------
[12:24:43.955] <TB3> INFO: PixTestReadback::CalibrateVd()
[12:24:43.955] <TB3> INFO: ----------------------------------------------------------------------
[12:24:53.918] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:24:53.918] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:24:53.918] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:24:53.918] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:24:53.918] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:24:53.918] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:24:53.919] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:24:53.919] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:24:53.919] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:24:53.919] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:24:53.919] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:24:53.919] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:24:53.919] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:24:53.919] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:24:53.919] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:24:53.919] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:24:53.947] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[12:24:53.947] <TB3> INFO: ----------------------------------------------------------------------
[12:24:53.947] <TB3> INFO: PixTestReadback::CalibrateVa()
[12:24:53.947] <TB3> INFO: ----------------------------------------------------------------------
[12:25:03.836] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:25:03.836] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:25:03.836] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:25:03.836] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:25:03.836] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:25:03.836] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:25:03.836] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:25:03.836] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:25:03.836] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:25:03.837] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:25:03.837] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:25:03.837] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:25:03.837] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:25:03.837] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:25:03.837] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:25:03.837] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:25:03.866] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[12:25:03.866] <TB3> INFO: ----------------------------------------------------------------------
[12:25:03.866] <TB3> INFO: PixTestReadback::readbackVbg()
[12:25:03.866] <TB3> INFO: ----------------------------------------------------------------------
[12:25:11.506] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[12:25:11.506] <TB3> INFO: ----------------------------------------------------------------------
[12:25:11.506] <TB3> INFO: PixTestReadback::getCalibratedVbg()
[12:25:11.506] <TB3> INFO: ----------------------------------------------------------------------
[12:25:11.506] <TB3> INFO: Vbg will be calibrated using Vd calibration
[12:25:11.506] <TB3> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 152.6calibrated Vbg = 1.16969 :::*/*/*/*/
[12:25:11.506] <TB3> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 142.3calibrated Vbg = 1.17512 :::*/*/*/*/
[12:25:11.506] <TB3> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 158.5calibrated Vbg = 1.17034 :::*/*/*/*/
[12:25:11.506] <TB3> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 154.5calibrated Vbg = 1.17018 :::*/*/*/*/
[12:25:11.506] <TB3> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 148.4calibrated Vbg = 1.17404 :::*/*/*/*/
[12:25:11.506] <TB3> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 153calibrated Vbg = 1.17151 :::*/*/*/*/
[12:25:11.506] <TB3> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 150.6calibrated Vbg = 1.17393 :::*/*/*/*/
[12:25:11.506] <TB3> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 155.6calibrated Vbg = 1.17706 :::*/*/*/*/
[12:25:11.506] <TB3> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 154calibrated Vbg = 1.18079 :::*/*/*/*/
[12:25:11.506] <TB3> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 156.1calibrated Vbg = 1.17118 :::*/*/*/*/
[12:25:11.506] <TB3> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 159calibrated Vbg = 1.16333 :::*/*/*/*/
[12:25:11.507] <TB3> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 149.8calibrated Vbg = 1.16322 :::*/*/*/*/
[12:25:11.507] <TB3> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 159.7calibrated Vbg = 1.17097 :::*/*/*/*/
[12:25:11.507] <TB3> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 161.2calibrated Vbg = 1.16577 :::*/*/*/*/
[12:25:11.507] <TB3> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 157.2calibrated Vbg = 1.17398 :::*/*/*/*/
[12:25:11.507] <TB3> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 146.9calibrated Vbg = 1.17719 :::*/*/*/*/
[12:25:11.508] <TB3> INFO: ----------------------------------------------------------------------
[12:25:11.508] <TB3> INFO: PixTestReadback::CalibrateIa()
[12:25:11.508] <TB3> INFO: ----------------------------------------------------------------------
[12:27:51.796] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:27:51.796] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:27:51.796] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:27:51.796] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:27:51.796] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:27:51.797] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:27:51.797] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:27:51.797] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:27:51.797] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:27:51.797] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:27:51.797] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:27:51.797] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:27:51.797] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:27:51.797] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:27:51.797] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:27:51.797] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:27:51.825] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[12:27:51.826] <TB3> INFO: PixTestReadback::doTest() done
[12:27:51.826] <TB3> INFO: Decoding statistics:
[12:27:51.826] <TB3> INFO: General information:
[12:27:51.826] <TB3> INFO: 16bit words read: 1536
[12:27:51.826] <TB3> INFO: valid events total: 256
[12:27:51.826] <TB3> INFO: empty events: 256
[12:27:51.826] <TB3> INFO: valid events with pixels: 0
[12:27:51.826] <TB3> INFO: valid pixel hits: 0
[12:27:51.826] <TB3> INFO: Event errors: 0
[12:27:51.826] <TB3> INFO: start marker: 0
[12:27:51.826] <TB3> INFO: stop marker: 0
[12:27:51.826] <TB3> INFO: overflow: 0
[12:27:51.826] <TB3> INFO: invalid 5bit words: 0
[12:27:51.826] <TB3> INFO: invalid XOR eye diagram: 0
[12:27:51.826] <TB3> INFO: frame (failed synchr.): 0
[12:27:51.826] <TB3> INFO: idle data (no TBM trl): 0
[12:27:51.826] <TB3> INFO: no data (only TBM hdr): 0
[12:27:51.826] <TB3> INFO: TBM errors: 0
[12:27:51.826] <TB3> INFO: flawed TBM headers: 0
[12:27:51.826] <TB3> INFO: flawed TBM trailers: 0
[12:27:51.826] <TB3> INFO: event ID mismatches: 0
[12:27:51.826] <TB3> INFO: ROC errors: 0
[12:27:51.826] <TB3> INFO: missing ROC header(s): 0
[12:27:51.826] <TB3> INFO: misplaced readback start: 0
[12:27:51.826] <TB3> INFO: Pixel decoding errors: 0
[12:27:51.826] <TB3> INFO: pixel data incomplete: 0
[12:27:51.826] <TB3> INFO: pixel address: 0
[12:27:51.826] <TB3> INFO: pulse height fill bit: 0
[12:27:51.826] <TB3> INFO: buffer corruption: 0
[12:27:51.861] <TB3> INFO: ######################################################################
[12:27:51.861] <TB3> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:27:51.861] <TB3> INFO: ######################################################################
[12:27:51.863] <TB3> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:27:51.875] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[12:27:51.875] <TB3> INFO: run 1 of 1
[12:27:52.110] <TB3> INFO: Expecting 3120000 events.
[12:28:22.246] <TB3> INFO: 658710 events read in total (29544ms).











[12:28:52.176] <TB3> INFO: 1313105 events read in total (59474ms).











[12:29:21.824] <TB3> INFO: 1964780 events read in total (89122ms).











[12:29:51.225] <TB3> INFO: 2618340 events read in total (118523ms).











[12:30:14.292] <TB3> INFO: 3120000 events read in total (141590ms).
[12:30:14.350] <TB3> INFO: Test took 142476ms.
[12:30:38.964] <TB3> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 167 seconds
[12:30:38.964] <TB3> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 54 0 0 0 0 0 0 0
[12:30:38.965] <TB3> INFO: separation cut (per ROC): 106 107 107 102 108 103 98 116 87 108 105 100 91 89 102 104
[12:30:38.965] <TB3> INFO: Decoding statistics:
[12:30:38.965] <TB3> INFO: General information:
[12:30:38.965] <TB3> INFO: 16bit words read: 0
[12:30:38.965] <TB3> INFO: valid events total: 0
[12:30:38.965] <TB3> INFO: empty events: 0
[12:30:38.965] <TB3> INFO: valid events with pixels: 0
[12:30:38.965] <TB3> INFO: valid pixel hits: 0
[12:30:38.965] <TB3> INFO: Event errors: 0
[12:30:38.965] <TB3> INFO: start marker: 0
[12:30:38.965] <TB3> INFO: stop marker: 0
[12:30:38.965] <TB3> INFO: overflow: 0
[12:30:38.965] <TB3> INFO: invalid 5bit words: 0
[12:30:38.965] <TB3> INFO: invalid XOR eye diagram: 0
[12:30:38.965] <TB3> INFO: frame (failed synchr.): 0
[12:30:38.965] <TB3> INFO: idle data (no TBM trl): 0
[12:30:38.965] <TB3> INFO: no data (only TBM hdr): 0
[12:30:38.965] <TB3> INFO: TBM errors: 0
[12:30:38.965] <TB3> INFO: flawed TBM headers: 0
[12:30:38.965] <TB3> INFO: flawed TBM trailers: 0
[12:30:38.965] <TB3> INFO: event ID mismatches: 0
[12:30:38.965] <TB3> INFO: ROC errors: 0
[12:30:38.965] <TB3> INFO: missing ROC header(s): 0
[12:30:38.965] <TB3> INFO: misplaced readback start: 0
[12:30:38.965] <TB3> INFO: Pixel decoding errors: 0
[12:30:38.965] <TB3> INFO: pixel data incomplete: 0
[12:30:38.965] <TB3> INFO: pixel address: 0
[12:30:38.965] <TB3> INFO: pulse height fill bit: 0
[12:30:38.965] <TB3> INFO: buffer corruption: 0
[12:30:39.004] <TB3> INFO: ######################################################################
[12:30:39.004] <TB3> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:30:39.004] <TB3> INFO: ######################################################################
[12:30:39.004] <TB3> INFO: ----------------------------------------------------------------------
[12:30:39.004] <TB3> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:30:39.004] <TB3> INFO: ----------------------------------------------------------------------
[12:30:39.004] <TB3> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:30:39.014] <TB3> INFO: dacScan split into 1 runs with ntrig = 50
[12:30:39.014] <TB3> INFO: run 1 of 1
[12:30:39.268] <TB3> INFO: Expecting 36608000 events.
[12:31:03.339] <TB3> INFO: 699350 events read in total (23479ms).
[12:31:26.314] <TB3> INFO: 1379600 events read in total (46454ms).
[12:31:49.181] <TB3> INFO: 2059300 events read in total (69321ms).
[12:32:12.236] <TB3> INFO: 2738950 events read in total (92376ms).
[12:32:35.006] <TB3> INFO: 3416200 events read in total (115146ms).
[12:32:57.798] <TB3> INFO: 4092800 events read in total (137938ms).
[12:33:20.324] <TB3> INFO: 4771050 events read in total (160464ms).
[12:33:43.105] <TB3> INFO: 5448700 events read in total (183245ms).
[12:34:06.066] <TB3> INFO: 6126800 events read in total (206206ms).
[12:34:28.718] <TB3> INFO: 6803600 events read in total (228858ms).
[12:34:51.308] <TB3> INFO: 7480750 events read in total (251448ms).
[12:35:14.005] <TB3> INFO: 8156900 events read in total (274145ms).
[12:35:36.929] <TB3> INFO: 8834850 events read in total (297069ms).
[12:35:59.815] <TB3> INFO: 9512250 events read in total (319955ms).
[12:36:22.323] <TB3> INFO: 10188600 events read in total (342463ms).
[12:36:44.938] <TB3> INFO: 10864650 events read in total (365078ms).
[12:37:07.449] <TB3> INFO: 11537550 events read in total (387589ms).
[12:37:30.255] <TB3> INFO: 12211650 events read in total (410395ms).
[12:37:52.827] <TB3> INFO: 12883800 events read in total (432967ms).
[12:38:15.310] <TB3> INFO: 13558050 events read in total (455450ms).
[12:38:37.631] <TB3> INFO: 14229600 events read in total (477771ms).
[12:39:00.145] <TB3> INFO: 14902000 events read in total (500285ms).
[12:39:22.607] <TB3> INFO: 15572300 events read in total (522747ms).
[12:39:45.523] <TB3> INFO: 16242200 events read in total (545663ms).
[12:40:07.905] <TB3> INFO: 16911400 events read in total (568045ms).
[12:40:30.596] <TB3> INFO: 17582350 events read in total (590736ms).
[12:40:52.960] <TB3> INFO: 18251850 events read in total (613100ms).
[12:41:15.721] <TB3> INFO: 18921350 events read in total (635861ms).
[12:41:38.475] <TB3> INFO: 19591550 events read in total (658615ms).
[12:42:00.935] <TB3> INFO: 20259200 events read in total (681075ms).
[12:42:23.571] <TB3> INFO: 20927350 events read in total (703711ms).
[12:42:45.892] <TB3> INFO: 21593750 events read in total (726032ms).
[12:43:08.513] <TB3> INFO: 22260550 events read in total (748653ms).
[12:43:30.994] <TB3> INFO: 22927000 events read in total (771134ms).
[12:43:53.406] <TB3> INFO: 23592700 events read in total (793546ms).
[12:44:15.957] <TB3> INFO: 24258900 events read in total (816097ms).
[12:44:38.407] <TB3> INFO: 24923850 events read in total (838547ms).
[12:45:00.000] <TB3> INFO: 25588100 events read in total (861140ms).
[12:45:23.381] <TB3> INFO: 26251650 events read in total (883521ms).
[12:45:46.080] <TB3> INFO: 26915750 events read in total (906220ms).
[12:46:08.270] <TB3> INFO: 27578400 events read in total (928410ms).
[12:46:30.655] <TB3> INFO: 28241950 events read in total (950795ms).
[12:46:52.965] <TB3> INFO: 28905150 events read in total (973105ms).
[12:47:15.470] <TB3> INFO: 29567250 events read in total (995610ms).
[12:47:37.915] <TB3> INFO: 30229950 events read in total (1018055ms).
[12:48:00.460] <TB3> INFO: 30891950 events read in total (1040600ms).
[12:48:22.903] <TB3> INFO: 31554200 events read in total (1063043ms).
[12:48:45.551] <TB3> INFO: 32216350 events read in total (1085691ms).
[12:49:07.816] <TB3> INFO: 32878450 events read in total (1107956ms).
[12:49:30.394] <TB3> INFO: 33541800 events read in total (1130534ms).
[12:49:52.876] <TB3> INFO: 34205200 events read in total (1153016ms).
[12:50:15.163] <TB3> INFO: 34870750 events read in total (1175303ms).
[12:50:38.003] <TB3> INFO: 35533900 events read in total (1198143ms).
[12:51:00.488] <TB3> INFO: 36204200 events read in total (1220628ms).
[12:51:13.892] <TB3> INFO: 36608000 events read in total (1234032ms).
[12:51:13.964] <TB3> INFO: Test took 1234950ms.
[12:51:14.369] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:16.066] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:17.877] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:19.783] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:21.756] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:23.680] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:25.404] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:27.287] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:29.140] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:30.768] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:32.485] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:34.016] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:35.510] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:36.964] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:38.407] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:40.128] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:51:41.586] <TB3> INFO: PixTestScurves::scurves() done
[12:51:41.586] <TB3> INFO: Vcal mean: 125.64 117.35 125.51 113.96 116.28 120.53 114.08 133.55 112.14 123.73 114.38 116.55 113.01 119.62 124.00 122.28
[12:51:41.586] <TB3> INFO: Vcal RMS: 6.23 5.75 6.93 5.24 5.69 5.90 5.53 6.16 6.51 6.59 5.58 5.81 6.92 8.00 5.39 5.32
[12:51:41.586] <TB3> INFO: PixTestScurves::fullTest() done, duration: 1262 seconds
[12:51:41.586] <TB3> INFO: Decoding statistics:
[12:51:41.586] <TB3> INFO: General information:
[12:51:41.586] <TB3> INFO: 16bit words read: 0
[12:51:41.586] <TB3> INFO: valid events total: 0
[12:51:41.586] <TB3> INFO: empty events: 0
[12:51:41.586] <TB3> INFO: valid events with pixels: 0
[12:51:41.586] <TB3> INFO: valid pixel hits: 0
[12:51:41.586] <TB3> INFO: Event errors: 0
[12:51:41.586] <TB3> INFO: start marker: 0
[12:51:41.586] <TB3> INFO: stop marker: 0
[12:51:41.586] <TB3> INFO: overflow: 0
[12:51:41.586] <TB3> INFO: invalid 5bit words: 0
[12:51:41.586] <TB3> INFO: invalid XOR eye diagram: 0
[12:51:41.586] <TB3> INFO: frame (failed synchr.): 0
[12:51:41.586] <TB3> INFO: idle data (no TBM trl): 0
[12:51:41.586] <TB3> INFO: no data (only TBM hdr): 0
[12:51:41.586] <TB3> INFO: TBM errors: 0
[12:51:41.586] <TB3> INFO: flawed TBM headers: 0
[12:51:41.586] <TB3> INFO: flawed TBM trailers: 0
[12:51:41.586] <TB3> INFO: event ID mismatches: 0
[12:51:41.586] <TB3> INFO: ROC errors: 0
[12:51:41.586] <TB3> INFO: missing ROC header(s): 0
[12:51:41.586] <TB3> INFO: misplaced readback start: 0
[12:51:41.586] <TB3> INFO: Pixel decoding errors: 0
[12:51:41.586] <TB3> INFO: pixel data incomplete: 0
[12:51:41.586] <TB3> INFO: pixel address: 0
[12:51:41.587] <TB3> INFO: pulse height fill bit: 0
[12:51:41.587] <TB3> INFO: buffer corruption: 0
[12:51:41.672] <TB3> INFO: ######################################################################
[12:51:41.672] <TB3> INFO: PixTestTrim::doTest()
[12:51:41.672] <TB3> INFO: ######################################################################
[12:51:41.673] <TB3> INFO: ----------------------------------------------------------------------
[12:51:41.673] <TB3> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:51:41.673] <TB3> INFO: ----------------------------------------------------------------------
[12:51:41.716] <TB3> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:51:41.716] <TB3> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:51:41.726] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:51:41.726] <TB3> INFO: run 1 of 1
[12:51:41.998] <TB3> INFO: Expecting 5025280 events.
[12:52:12.414] <TB3> INFO: 829968 events read in total (29823ms).
[12:52:42.176] <TB3> INFO: 1656360 events read in total (59586ms).
[12:53:12.068] <TB3> INFO: 2478936 events read in total (89477ms).
[12:53:41.604] <TB3> INFO: 3297808 events read in total (119013ms).
[12:54:11.086] <TB3> INFO: 4110720 events read in total (148495ms).
[12:54:40.570] <TB3> INFO: 4921808 events read in total (177979ms).
[12:54:44.944] <TB3> INFO: 5025280 events read in total (182353ms).
[12:54:44.994] <TB3> INFO: Test took 183269ms.
[12:54:58.917] <TB3> INFO: ROC 0 VthrComp = 130
[12:54:58.917] <TB3> INFO: ROC 1 VthrComp = 124
[12:54:58.917] <TB3> INFO: ROC 2 VthrComp = 135
[12:54:58.918] <TB3> INFO: ROC 3 VthrComp = 123
[12:54:58.918] <TB3> INFO: ROC 4 VthrComp = 124
[12:54:58.918] <TB3> INFO: ROC 5 VthrComp = 123
[12:54:58.918] <TB3> INFO: ROC 6 VthrComp = 119
[12:54:58.918] <TB3> INFO: ROC 7 VthrComp = 138
[12:54:58.919] <TB3> INFO: ROC 8 VthrComp = 111
[12:54:58.919] <TB3> INFO: ROC 9 VthrComp = 126
[12:54:58.919] <TB3> INFO: ROC 10 VthrComp = 119
[12:54:58.919] <TB3> INFO: ROC 11 VthrComp = 118
[12:54:58.919] <TB3> INFO: ROC 12 VthrComp = 112
[12:54:58.919] <TB3> INFO: ROC 13 VthrComp = 107
[12:54:58.919] <TB3> INFO: ROC 14 VthrComp = 124
[12:54:58.920] <TB3> INFO: ROC 15 VthrComp = 128
[12:54:59.154] <TB3> INFO: Expecting 41600 events.
[12:55:02.633] <TB3> INFO: 41600 events read in total (2888ms).
[12:55:02.634] <TB3> INFO: Test took 3713ms.
[12:55:02.642] <TB3> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:55:02.642] <TB3> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:55:02.651] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[12:55:02.651] <TB3> INFO: run 1 of 1
[12:55:02.929] <TB3> INFO: Expecting 5025280 events.
[12:55:29.061] <TB3> INFO: 589528 events read in total (25540ms).
[12:55:54.335] <TB3> INFO: 1178224 events read in total (50814ms).
[12:56:19.785] <TB3> INFO: 1768504 events read in total (76264ms).
[12:56:44.752] <TB3> INFO: 2358736 events read in total (101231ms).
[12:57:10.018] <TB3> INFO: 2945936 events read in total (126497ms).
[12:57:35.073] <TB3> INFO: 3531816 events read in total (151552ms).
[12:58:00.458] <TB3> INFO: 4116384 events read in total (176937ms).
[12:58:25.868] <TB3> INFO: 4700312 events read in total (202347ms).
[12:58:39.991] <TB3> INFO: 5025280 events read in total (216470ms).
[12:58:40.052] <TB3> INFO: Test took 217401ms.
[12:59:06.371] <TB3> INFO: roc 0 with ID = 0 has maximal Vcal 59.5408 for pixel 1/8 mean/min/max = 46.1691/32.7802/59.5581
[12:59:06.371] <TB3> INFO: roc 1 with ID = 1 has maximal Vcal 58.5104 for pixel 14/79 mean/min/max = 45.8288/33.1006/58.5571
[12:59:06.372] <TB3> INFO: roc 2 with ID = 2 has maximal Vcal 60.1751 for pixel 1/11 mean/min/max = 46.8819/33.5549/60.2089
[12:59:06.372] <TB3> INFO: roc 3 with ID = 3 has maximal Vcal 57.6545 for pixel 3/1 mean/min/max = 44.8322/31.9582/57.7062
[12:59:06.372] <TB3> INFO: roc 4 with ID = 4 has maximal Vcal 58.8969 for pixel 3/14 mean/min/max = 45.931/32.7889/59.0731
[12:59:06.372] <TB3> INFO: roc 5 with ID = 5 has maximal Vcal 59.4192 for pixel 5/54 mean/min/max = 46.4811/33.5151/59.447
[12:59:06.373] <TB3> INFO: roc 6 with ID = 6 has maximal Vcal 58.3218 for pixel 23/73 mean/min/max = 45.6539/32.5782/58.7297
[12:59:06.373] <TB3> INFO: roc 7 with ID = 7 has maximal Vcal 64.7731 for pixel 19/8 mean/min/max = 50.5362/36.203/64.8695
[12:59:06.373] <TB3> INFO: roc 8 with ID = 8 has maximal Vcal 66.7924 for pixel 21/0 mean/min/max = 49.8062/32.1381/67.4743
[12:59:06.373] <TB3> INFO: roc 9 with ID = 9 has maximal Vcal 64.7088 for pixel 1/3 mean/min/max = 49.2304/33.6152/64.8456
[12:59:06.374] <TB3> INFO: roc 10 with ID = 10 has maximal Vcal 59.1442 for pixel 0/76 mean/min/max = 45.683/32.1076/59.2584
[12:59:06.374] <TB3> INFO: roc 11 with ID = 11 has maximal Vcal 59.8972 for pixel 9/42 mean/min/max = 46.4188/32.9378/59.8998
[12:59:06.374] <TB3> INFO: roc 12 with ID = 12 has maximal Vcal 65.5329 for pixel 2/0 mean/min/max = 48.327/31.048/65.6061
[12:59:06.374] <TB3> INFO: roc 13 with ID = 13 has maximal Vcal 73.3517 for pixel 18/0 mean/min/max = 53.0462/32.5689/73.5236
[12:59:06.375] <TB3> INFO: roc 14 with ID = 14 has maximal Vcal 60.5696 for pixel 51/11 mean/min/max = 46.542/32.5097/60.5744
[12:59:06.375] <TB3> INFO: roc 15 with ID = 15 has maximal Vcal 59.7931 for pixel 18/9 mean/min/max = 46.4788/33.1031/59.8545
[12:59:06.375] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:59:06.464] <TB3> INFO: Expecting 411648 events.
[12:59:15.785] <TB3> INFO: 411648 events read in total (8728ms).
[12:59:15.791] <TB3> INFO: Expecting 411648 events.
[12:59:24.848] <TB3> INFO: 411648 events read in total (8654ms).
[12:59:24.857] <TB3> INFO: Expecting 411648 events.
[12:59:33.959] <TB3> INFO: 411648 events read in total (8699ms).
[12:59:33.975] <TB3> INFO: Expecting 411648 events.
[12:59:43.059] <TB3> INFO: 411648 events read in total (8681ms).
[12:59:43.078] <TB3> INFO: Expecting 411648 events.
[12:59:52.265] <TB3> INFO: 411648 events read in total (8784ms).
[12:59:52.286] <TB3> INFO: Expecting 411648 events.
[13:00:01.425] <TB3> INFO: 411648 events read in total (8736ms).
[13:00:01.452] <TB3> INFO: Expecting 411648 events.
[13:00:10.539] <TB3> INFO: 411648 events read in total (8684ms).
[13:00:10.562] <TB3> INFO: Expecting 411648 events.
[13:00:19.719] <TB3> INFO: 411648 events read in total (8754ms).
[13:00:19.753] <TB3> INFO: Expecting 411648 events.
[13:00:28.905] <TB3> INFO: 411648 events read in total (8749ms).
[13:00:28.943] <TB3> INFO: Expecting 411648 events.
[13:00:38.121] <TB3> INFO: 411648 events read in total (8775ms).
[13:00:38.163] <TB3> INFO: Expecting 411648 events.
[13:00:47.285] <TB3> INFO: 411648 events read in total (8720ms).
[13:00:47.330] <TB3> INFO: Expecting 411648 events.
[13:00:56.350] <TB3> INFO: 411648 events read in total (8617ms).
[13:00:56.388] <TB3> INFO: Expecting 411648 events.
[13:01:05.436] <TB3> INFO: 411648 events read in total (8645ms).
[13:01:05.476] <TB3> INFO: Expecting 411648 events.
[13:01:14.573] <TB3> INFO: 411648 events read in total (8694ms).
[13:01:14.614] <TB3> INFO: Expecting 411648 events.
[13:01:23.764] <TB3> INFO: 411648 events read in total (8747ms).
[13:01:23.826] <TB3> INFO: Expecting 411648 events.
[13:01:32.973] <TB3> INFO: 411648 events read in total (8744ms).
[13:01:33.022] <TB3> INFO: Test took 146647ms.
[13:01:33.695] <TB3> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:01:33.706] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:01:33.706] <TB3> INFO: run 1 of 1
[13:01:33.977] <TB3> INFO: Expecting 5025280 events.
[13:02:00.027] <TB3> INFO: 586728 events read in total (25458ms).
[13:02:25.562] <TB3> INFO: 1171728 events read in total (50993ms).
[13:02:51.088] <TB3> INFO: 1756416 events read in total (76519ms).
[13:03:16.604] <TB3> INFO: 2340872 events read in total (102035ms).
[13:03:42.257] <TB3> INFO: 2926816 events read in total (127688ms).
[13:04:07.993] <TB3> INFO: 3514120 events read in total (153424ms).
[13:04:33.522] <TB3> INFO: 4101504 events read in total (178953ms).
[13:04:59.192] <TB3> INFO: 4687528 events read in total (204623ms).
[13:05:14.114] <TB3> INFO: 5025280 events read in total (219545ms).
[13:05:14.225] <TB3> INFO: Test took 220519ms.
[13:05:38.508] <TB3> INFO: ---> TrimStepCorr4 extremal thresholds: 5.061714 .. 147.687698
[13:05:38.741] <TB3> INFO: Expecting 208000 events.
[13:05:48.076] <TB3> INFO: 208000 events read in total (8744ms).
[13:05:48.078] <TB3> INFO: Test took 9569ms.
[13:05:48.124] <TB3> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 5 .. 157 (-1/-1) hits flags = 528 (plus default)
[13:05:48.133] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:05:48.133] <TB3> INFO: run 1 of 1
[13:05:48.411] <TB3> INFO: Expecting 5091840 events.
[13:06:14.380] <TB3> INFO: 579440 events read in total (25377ms).
[13:06:40.021] <TB3> INFO: 1159112 events read in total (51018ms).
[13:07:05.140] <TB3> INFO: 1738808 events read in total (76137ms).
[13:07:30.538] <TB3> INFO: 2318424 events read in total (101536ms).
[13:07:55.993] <TB3> INFO: 2897528 events read in total (126990ms).
[13:08:20.966] <TB3> INFO: 3475840 events read in total (151963ms).
[13:08:46.343] <TB3> INFO: 4053528 events read in total (177340ms).
[13:09:12.082] <TB3> INFO: 4629992 events read in total (203079ms).
[13:09:32.355] <TB3> INFO: 5091840 events read in total (223352ms).
[13:09:32.433] <TB3> INFO: Test took 224299ms.
[13:09:57.739] <TB3> INFO: ---> TrimStepCorr2 extremal thresholds: 26.500000 .. 46.358066
[13:09:57.972] <TB3> INFO: Expecting 208000 events.
[13:10:07.482] <TB3> INFO: 208000 events read in total (8919ms).
[13:10:07.483] <TB3> INFO: Test took 9743ms.
[13:10:07.532] <TB3> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 56 (-1/-1) hits flags = 528 (plus default)
[13:10:07.542] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:10:07.542] <TB3> INFO: run 1 of 1
[13:10:07.820] <TB3> INFO: Expecting 1364480 events.
[13:10:36.015] <TB3> INFO: 661608 events read in total (27603ms).
[13:11:03.863] <TB3> INFO: 1321816 events read in total (55451ms).
[13:11:06.125] <TB3> INFO: 1364480 events read in total (57713ms).
[13:11:06.156] <TB3> INFO: Test took 58613ms.
[13:11:18.308] <TB3> INFO: ---> TrimStepCorr1a extremal thresholds: 27.850743 .. 53.149649
[13:11:18.542] <TB3> INFO: Expecting 208000 events.
[13:11:28.226] <TB3> INFO: 208000 events read in total (9093ms).
[13:11:28.227] <TB3> INFO: Test took 9917ms.
[13:11:28.274] <TB3> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 63 (-1/-1) hits flags = 528 (plus default)
[13:11:28.282] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:11:28.283] <TB3> INFO: run 1 of 1
[13:11:28.560] <TB3> INFO: Expecting 1564160 events.
[13:11:55.733] <TB3> INFO: 634656 events read in total (26581ms).
[13:12:22.737] <TB3> INFO: 1268424 events read in total (53585ms).
[13:12:35.591] <TB3> INFO: 1564160 events read in total (66439ms).
[13:12:35.629] <TB3> INFO: Test took 67347ms.
[13:12:47.979] <TB3> INFO: ---> TrimStepCorr1b extremal thresholds: 26.581435 .. 54.128015
[13:12:48.212] <TB3> INFO: Expecting 208000 events.
[13:12:57.990] <TB3> INFO: 208000 events read in total (9186ms).
[13:12:57.990] <TB3> INFO: Test took 10009ms.
[13:12:58.061] <TB3> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 64 (-1/-1) hits flags = 528 (plus default)
[13:12:58.072] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:12:58.072] <TB3> INFO: run 1 of 1
[13:12:58.350] <TB3> INFO: Expecting 1630720 events.
[13:13:25.786] <TB3> INFO: 635488 events read in total (26844ms).
[13:13:52.226] <TB3> INFO: 1270720 events read in total (53285ms).
[13:14:07.476] <TB3> INFO: 1630720 events read in total (68534ms).
[13:14:07.504] <TB3> INFO: Test took 69432ms.
[13:14:22.135] <TB3> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[13:14:22.135] <TB3> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[13:14:22.146] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:14:22.146] <TB3> INFO: run 1 of 1
[13:14:22.418] <TB3> INFO: Expecting 1364480 events.
[13:14:50.282] <TB3> INFO: 668320 events read in total (27273ms).
[13:15:18.083] <TB3> INFO: 1336368 events read in total (55074ms).
[13:15:19.712] <TB3> INFO: 1364480 events read in total (56704ms).
[13:15:19.734] <TB3> INFO: Test took 57588ms.
[13:15:32.263] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C0.dat
[13:15:32.263] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C1.dat
[13:15:32.264] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C2.dat
[13:15:32.264] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C3.dat
[13:15:32.264] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C4.dat
[13:15:32.264] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C5.dat
[13:15:32.264] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C6.dat
[13:15:32.264] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C7.dat
[13:15:32.264] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C8.dat
[13:15:32.264] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C9.dat
[13:15:32.264] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C10.dat
[13:15:32.264] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C11.dat
[13:15:32.264] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C12.dat
[13:15:32.264] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C13.dat
[13:15:32.264] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C14.dat
[13:15:32.264] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C15.dat
[13:15:32.264] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C0.dat
[13:15:32.272] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C1.dat
[13:15:32.278] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C2.dat
[13:15:32.283] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C3.dat
[13:15:32.289] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C4.dat
[13:15:32.295] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C5.dat
[13:15:32.301] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C6.dat
[13:15:32.307] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C7.dat
[13:15:32.313] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C8.dat
[13:15:32.318] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C9.dat
[13:15:32.324] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C10.dat
[13:15:32.329] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C11.dat
[13:15:32.335] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C12.dat
[13:15:32.341] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C13.dat
[13:15:32.346] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C14.dat
[13:15:32.352] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C15.dat
[13:15:32.358] <TB3> INFO: PixTestTrim::trimTest() done
[13:15:32.358] <TB3> INFO: vtrim: 128 143 162 126 150 151 144 181 177 164 134 136 136 170 137 145
[13:15:32.358] <TB3> INFO: vthrcomp: 130 124 135 123 124 123 119 138 111 126 119 118 112 107 124 128
[13:15:32.358] <TB3> INFO: vcal mean: 34.90 34.99 35.05 34.94 35.02 35.04 35.09 35.05 35.07 35.14 34.95 35.09 34.98 36.09 35.08 34.94
[13:15:32.358] <TB3> INFO: vcal RMS: 0.99 1.01 1.06 0.97 0.98 1.08 1.21 1.12 1.22 1.26 0.95 1.13 1.13 2.50 1.24 0.99
[13:15:32.358] <TB3> INFO: bits mean: 9.57 9.86 9.61 10.02 9.95 9.84 10.65 8.66 9.63 9.55 9.67 9.93 9.62 9.79 10.04 9.64
[13:15:32.358] <TB3> INFO: bits RMS: 2.55 2.40 2.40 2.54 2.39 2.34 2.15 2.21 2.38 2.34 2.61 2.35 2.54 2.32 2.42 2.49
[13:15:32.365] <TB3> INFO: ----------------------------------------------------------------------
[13:15:32.365] <TB3> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:15:32.365] <TB3> INFO: ----------------------------------------------------------------------
[13:15:32.368] <TB3> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:15:32.378] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:15:32.378] <TB3> INFO: run 1 of 1
[13:15:32.617] <TB3> INFO: Expecting 4160000 events.
[13:16:05.488] <TB3> INFO: 767780 events read in total (32280ms).
[13:16:37.309] <TB3> INFO: 1528080 events read in total (64101ms).
[13:17:09.242] <TB3> INFO: 2281170 events read in total (96035ms).
[13:17:41.133] <TB3> INFO: 3029200 events read in total (127925ms).
[13:18:12.625] <TB3> INFO: 3772615 events read in total (159417ms).
[13:18:29.310] <TB3> INFO: 4160000 events read in total (176102ms).
[13:18:29.357] <TB3> INFO: Test took 176979ms.
[13:18:54.041] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[13:18:54.049] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:18:54.049] <TB3> INFO: run 1 of 1
[13:18:54.281] <TB3> INFO: Expecting 4305600 events.
[13:19:26.006] <TB3> INFO: 732925 events read in total (31133ms).
[13:19:57.698] <TB3> INFO: 1460225 events read in total (62825ms).
[13:20:28.773] <TB3> INFO: 2182325 events read in total (93901ms).
[13:20:59.392] <TB3> INFO: 2899735 events read in total (124519ms).
[13:21:29.905] <TB3> INFO: 3611980 events read in total (155032ms).
[13:21:59.456] <TB3> INFO: 4305600 events read in total (184583ms).
[13:21:59.526] <TB3> INFO: Test took 185477ms.
[13:22:25.640] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[13:22:25.650] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:22:25.650] <TB3> INFO: run 1 of 1
[13:22:25.912] <TB3> INFO: Expecting 4243200 events.
[13:22:57.414] <TB3> INFO: 737400 events read in total (30910ms).
[13:23:28.525] <TB3> INFO: 1469060 events read in total (62021ms).
[13:23:59.240] <TB3> INFO: 2195100 events read in total (92736ms).
[13:24:29.870] <TB3> INFO: 2916165 events read in total (123366ms).
[13:25:00.652] <TB3> INFO: 3632310 events read in total (154148ms).
[13:25:26.736] <TB3> INFO: 4243200 events read in total (180232ms).
[13:25:26.791] <TB3> INFO: Test took 181141ms.
[13:25:54.222] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[13:25:54.231] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:25:54.231] <TB3> INFO: run 1 of 1
[13:25:54.463] <TB3> INFO: Expecting 4243200 events.
[13:26:26.572] <TB3> INFO: 737320 events read in total (31517ms).
[13:26:57.602] <TB3> INFO: 1468920 events read in total (62547ms).
[13:27:28.690] <TB3> INFO: 2194970 events read in total (93635ms).
[13:27:59.644] <TB3> INFO: 2916340 events read in total (124589ms).
[13:28:30.157] <TB3> INFO: 3632605 events read in total (155102ms).
[13:28:56.582] <TB3> INFO: 4243200 events read in total (181527ms).
[13:28:56.652] <TB3> INFO: Test took 182421ms.
[13:29:24.247] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[13:29:24.258] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:29:24.259] <TB3> INFO: run 1 of 1
[13:29:24.508] <TB3> INFO: Expecting 4097600 events.
[13:29:56.460] <TB3> INFO: 747595 events read in total (31361ms).
[13:30:27.906] <TB3> INFO: 1489330 events read in total (62807ms).
[13:30:58.936] <TB3> INFO: 2224540 events read in total (93838ms).
[13:31:29.991] <TB3> INFO: 2954295 events read in total (124892ms).
[13:32:01.099] <TB3> INFO: 3679315 events read in total (156000ms).
[13:32:19.065] <TB3> INFO: 4097600 events read in total (173966ms).
[13:32:19.120] <TB3> INFO: Test took 174861ms.
[13:32:46.556] <TB3> INFO: PixTestTrim::trimBitTest() done
[13:32:46.557] <TB3> INFO: PixTestTrim::doTest() done, duration: 2464 seconds
[13:32:46.557] <TB3> INFO: Decoding statistics:
[13:32:46.557] <TB3> INFO: General information:
[13:32:46.557] <TB3> INFO: 16bit words read: 0
[13:32:46.557] <TB3> INFO: valid events total: 0
[13:32:46.557] <TB3> INFO: empty events: 0
[13:32:46.557] <TB3> INFO: valid events with pixels: 0
[13:32:46.557] <TB3> INFO: valid pixel hits: 0
[13:32:46.557] <TB3> INFO: Event errors: 0
[13:32:46.557] <TB3> INFO: start marker: 0
[13:32:46.557] <TB3> INFO: stop marker: 0
[13:32:46.557] <TB3> INFO: overflow: 0
[13:32:46.557] <TB3> INFO: invalid 5bit words: 0
[13:32:46.557] <TB3> INFO: invalid XOR eye diagram: 0
[13:32:46.557] <TB3> INFO: frame (failed synchr.): 0
[13:32:46.557] <TB3> INFO: idle data (no TBM trl): 0
[13:32:46.557] <TB3> INFO: no data (only TBM hdr): 0
[13:32:46.557] <TB3> INFO: TBM errors: 0
[13:32:46.557] <TB3> INFO: flawed TBM headers: 0
[13:32:46.557] <TB3> INFO: flawed TBM trailers: 0
[13:32:46.557] <TB3> INFO: event ID mismatches: 0
[13:32:46.557] <TB3> INFO: ROC errors: 0
[13:32:46.557] <TB3> INFO: missing ROC header(s): 0
[13:32:46.557] <TB3> INFO: misplaced readback start: 0
[13:32:46.558] <TB3> INFO: Pixel decoding errors: 0
[13:32:46.558] <TB3> INFO: pixel data incomplete: 0
[13:32:46.558] <TB3> INFO: pixel address: 0
[13:32:46.558] <TB3> INFO: pulse height fill bit: 0
[13:32:46.558] <TB3> INFO: buffer corruption: 0
[13:32:47.175] <TB3> INFO: ######################################################################
[13:32:47.175] <TB3> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:32:47.175] <TB3> INFO: ######################################################################
[13:32:47.420] <TB3> INFO: Expecting 41600 events.
[13:32:50.846] <TB3> INFO: 41600 events read in total (2835ms).
[13:32:50.847] <TB3> INFO: Test took 3670ms.
[13:32:51.286] <TB3> INFO: Expecting 41600 events.
[13:32:54.822] <TB3> INFO: 41600 events read in total (2944ms).
[13:32:54.823] <TB3> INFO: Test took 3772ms.
[13:32:55.111] <TB3> INFO: Expecting 41600 events.
[13:32:58.637] <TB3> INFO: 41600 events read in total (2935ms).
[13:32:58.638] <TB3> INFO: Test took 3792ms.
[13:32:58.927] <TB3> INFO: Expecting 41600 events.
[13:33:02.435] <TB3> INFO: 41600 events read in total (2917ms).
[13:33:02.436] <TB3> INFO: Test took 3774ms.
[13:33:02.724] <TB3> INFO: Expecting 41600 events.
[13:33:06.244] <TB3> INFO: 41600 events read in total (2929ms).
[13:33:06.245] <TB3> INFO: Test took 3786ms.
[13:33:06.533] <TB3> INFO: Expecting 41600 events.
[13:33:09.993] <TB3> INFO: 41600 events read in total (2868ms).
[13:33:09.994] <TB3> INFO: Test took 3726ms.
[13:33:10.282] <TB3> INFO: Expecting 41600 events.
[13:33:13.776] <TB3> INFO: 41600 events read in total (2902ms).
[13:33:13.777] <TB3> INFO: Test took 3759ms.
[13:33:14.066] <TB3> INFO: Expecting 41600 events.
[13:33:17.565] <TB3> INFO: 41600 events read in total (2907ms).
[13:33:17.565] <TB3> INFO: Test took 3766ms.
[13:33:17.854] <TB3> INFO: Expecting 41600 events.
[13:33:21.342] <TB3> INFO: 41600 events read in total (2897ms).
[13:33:21.343] <TB3> INFO: Test took 3754ms.
[13:33:21.631] <TB3> INFO: Expecting 41600 events.
[13:33:25.068] <TB3> INFO: 41600 events read in total (2846ms).
[13:33:25.069] <TB3> INFO: Test took 3703ms.
[13:33:25.371] <TB3> INFO: Expecting 41600 events.
[13:33:28.969] <TB3> INFO: 41600 events read in total (3006ms).
[13:33:28.969] <TB3> INFO: Test took 3874ms.
[13:33:29.258] <TB3> INFO: Expecting 41600 events.
[13:33:32.700] <TB3> INFO: 41600 events read in total (2851ms).
[13:33:32.701] <TB3> INFO: Test took 3708ms.
[13:33:33.030] <TB3> INFO: Expecting 41600 events.
[13:33:36.679] <TB3> INFO: 41600 events read in total (3058ms).
[13:33:36.680] <TB3> INFO: Test took 3956ms.
[13:33:36.975] <TB3> INFO: Expecting 41600 events.
[13:33:40.509] <TB3> INFO: 41600 events read in total (2943ms).
[13:33:40.510] <TB3> INFO: Test took 3802ms.
[13:33:40.800] <TB3> INFO: Expecting 41600 events.
[13:33:44.286] <TB3> INFO: 41600 events read in total (2894ms).
[13:33:44.287] <TB3> INFO: Test took 3752ms.
[13:33:44.577] <TB3> INFO: Expecting 41600 events.
[13:33:48.091] <TB3> INFO: 41600 events read in total (2922ms).
[13:33:48.092] <TB3> INFO: Test took 3779ms.
[13:33:48.380] <TB3> INFO: Expecting 41600 events.
[13:33:51.838] <TB3> INFO: 41600 events read in total (2866ms).
[13:33:51.838] <TB3> INFO: Test took 3723ms.
[13:33:52.128] <TB3> INFO: Expecting 41600 events.
[13:33:55.621] <TB3> INFO: 41600 events read in total (2902ms).
[13:33:55.621] <TB3> INFO: Test took 3759ms.
[13:33:55.909] <TB3> INFO: Expecting 41600 events.
[13:33:59.449] <TB3> INFO: 41600 events read in total (2948ms).
[13:33:59.450] <TB3> INFO: Test took 3805ms.
[13:33:59.738] <TB3> INFO: Expecting 41600 events.
[13:34:03.227] <TB3> INFO: 41600 events read in total (2897ms).
[13:34:03.228] <TB3> INFO: Test took 3755ms.
[13:34:03.527] <TB3> INFO: Expecting 41600 events.
[13:34:06.984] <TB3> INFO: 41600 events read in total (2866ms).
[13:34:06.984] <TB3> INFO: Test took 3730ms.
[13:34:07.272] <TB3> INFO: Expecting 41600 events.
[13:34:10.734] <TB3> INFO: 41600 events read in total (2870ms).
[13:34:10.735] <TB3> INFO: Test took 3727ms.
[13:34:11.023] <TB3> INFO: Expecting 41600 events.
[13:34:14.531] <TB3> INFO: 41600 events read in total (2916ms).
[13:34:14.533] <TB3> INFO: Test took 3774ms.
[13:34:14.824] <TB3> INFO: Expecting 41600 events.
[13:34:18.260] <TB3> INFO: 41600 events read in total (2845ms).
[13:34:18.261] <TB3> INFO: Test took 3702ms.
[13:34:18.551] <TB3> INFO: Expecting 41600 events.
[13:34:22.006] <TB3> INFO: 41600 events read in total (2863ms).
[13:34:22.006] <TB3> INFO: Test took 3719ms.
[13:34:22.294] <TB3> INFO: Expecting 41600 events.
[13:34:25.756] <TB3> INFO: 41600 events read in total (2870ms).
[13:34:25.757] <TB3> INFO: Test took 3728ms.
[13:34:26.045] <TB3> INFO: Expecting 41600 events.
[13:34:29.503] <TB3> INFO: 41600 events read in total (2866ms).
[13:34:29.504] <TB3> INFO: Test took 3724ms.
[13:34:29.792] <TB3> INFO: Expecting 41600 events.
[13:34:33.233] <TB3> INFO: 41600 events read in total (2850ms).
[13:34:33.233] <TB3> INFO: Test took 3706ms.
[13:34:33.522] <TB3> INFO: Expecting 41600 events.
[13:34:37.046] <TB3> INFO: 41600 events read in total (2933ms).
[13:34:37.047] <TB3> INFO: Test took 3790ms.
[13:34:37.339] <TB3> INFO: Expecting 41600 events.
[13:34:40.824] <TB3> INFO: 41600 events read in total (2893ms).
[13:34:40.825] <TB3> INFO: Test took 3750ms.
[13:34:41.113] <TB3> INFO: Expecting 2560 events.
[13:34:41.998] <TB3> INFO: 2560 events read in total (293ms).
[13:34:41.998] <TB3> INFO: Test took 1161ms.
[13:34:42.305] <TB3> INFO: Expecting 2560 events.
[13:34:43.192] <TB3> INFO: 2560 events read in total (295ms).
[13:34:43.193] <TB3> INFO: Test took 1195ms.
[13:34:43.500] <TB3> INFO: Expecting 2560 events.
[13:34:44.386] <TB3> INFO: 2560 events read in total (295ms).
[13:34:44.387] <TB3> INFO: Test took 1194ms.
[13:34:44.694] <TB3> INFO: Expecting 2560 events.
[13:34:45.578] <TB3> INFO: 2560 events read in total (292ms).
[13:34:45.578] <TB3> INFO: Test took 1191ms.
[13:34:45.885] <TB3> INFO: Expecting 2560 events.
[13:34:46.764] <TB3> INFO: 2560 events read in total (287ms).
[13:34:46.764] <TB3> INFO: Test took 1186ms.
[13:34:47.072] <TB3> INFO: Expecting 2560 events.
[13:34:47.953] <TB3> INFO: 2560 events read in total (289ms).
[13:34:47.953] <TB3> INFO: Test took 1188ms.
[13:34:48.261] <TB3> INFO: Expecting 2560 events.
[13:34:49.142] <TB3> INFO: 2560 events read in total (289ms).
[13:34:49.142] <TB3> INFO: Test took 1188ms.
[13:34:49.450] <TB3> INFO: Expecting 2560 events.
[13:34:50.333] <TB3> INFO: 2560 events read in total (291ms).
[13:34:50.333] <TB3> INFO: Test took 1191ms.
[13:34:50.641] <TB3> INFO: Expecting 2560 events.
[13:34:51.519] <TB3> INFO: 2560 events read in total (287ms).
[13:34:51.519] <TB3> INFO: Test took 1186ms.
[13:34:51.828] <TB3> INFO: Expecting 2560 events.
[13:34:52.708] <TB3> INFO: 2560 events read in total (289ms).
[13:34:52.708] <TB3> INFO: Test took 1188ms.
[13:34:53.016] <TB3> INFO: Expecting 2560 events.
[13:34:53.895] <TB3> INFO: 2560 events read in total (287ms).
[13:34:53.896] <TB3> INFO: Test took 1187ms.
[13:34:54.204] <TB3> INFO: Expecting 2560 events.
[13:34:55.086] <TB3> INFO: 2560 events read in total (291ms).
[13:34:55.086] <TB3> INFO: Test took 1190ms.
[13:34:55.394] <TB3> INFO: Expecting 2560 events.
[13:34:56.278] <TB3> INFO: 2560 events read in total (292ms).
[13:34:56.279] <TB3> INFO: Test took 1192ms.
[13:34:56.587] <TB3> INFO: Expecting 2560 events.
[13:34:57.470] <TB3> INFO: 2560 events read in total (292ms).
[13:34:57.470] <TB3> INFO: Test took 1191ms.
[13:34:57.777] <TB3> INFO: Expecting 2560 events.
[13:34:58.662] <TB3> INFO: 2560 events read in total (293ms).
[13:34:58.662] <TB3> INFO: Test took 1192ms.
[13:34:58.970] <TB3> INFO: Expecting 2560 events.
[13:34:59.852] <TB3> INFO: 2560 events read in total (290ms).
[13:34:59.852] <TB3> INFO: Test took 1190ms.
[13:34:59.855] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:35:00.161] <TB3> INFO: Expecting 655360 events.
[13:35:14.495] <TB3> INFO: 655360 events read in total (13743ms).
[13:35:14.506] <TB3> INFO: Expecting 655360 events.
[13:35:28.621] <TB3> INFO: 655360 events read in total (13713ms).
[13:35:28.637] <TB3> INFO: Expecting 655360 events.
[13:35:42.799] <TB3> INFO: 655360 events read in total (13759ms).
[13:35:42.818] <TB3> INFO: Expecting 655360 events.
[13:35:56.950] <TB3> INFO: 655360 events read in total (13729ms).
[13:35:56.979] <TB3> INFO: Expecting 655360 events.
[13:36:11.127] <TB3> INFO: 655360 events read in total (13745ms).
[13:36:11.154] <TB3> INFO: Expecting 655360 events.
[13:36:25.229] <TB3> INFO: 655360 events read in total (13672ms).
[13:36:25.260] <TB3> INFO: Expecting 655360 events.
[13:36:39.243] <TB3> INFO: 655360 events read in total (13580ms).
[13:36:39.291] <TB3> INFO: Expecting 655360 events.
[13:36:53.416] <TB3> INFO: 655360 events read in total (13723ms).
[13:36:53.455] <TB3> INFO: Expecting 655360 events.
[13:37:07.559] <TB3> INFO: 655360 events read in total (13701ms).
[13:37:07.601] <TB3> INFO: Expecting 655360 events.
[13:37:21.638] <TB3> INFO: 655360 events read in total (13634ms).
[13:37:21.704] <TB3> INFO: Expecting 655360 events.
[13:37:35.651] <TB3> INFO: 655360 events read in total (13544ms).
[13:37:35.720] <TB3> INFO: Expecting 655360 events.
[13:37:49.744] <TB3> INFO: 655360 events read in total (13621ms).
[13:37:49.800] <TB3> INFO: Expecting 655360 events.
[13:38:03.853] <TB3> INFO: 655360 events read in total (13650ms).
[13:38:03.917] <TB3> INFO: Expecting 655360 events.
[13:38:18.054] <TB3> INFO: 655360 events read in total (13734ms).
[13:38:18.121] <TB3> INFO: Expecting 655360 events.
[13:38:32.211] <TB3> INFO: 655360 events read in total (13687ms).
[13:38:32.281] <TB3> INFO: Expecting 655360 events.
[13:38:46.309] <TB3> INFO: 655360 events read in total (13625ms).
[13:38:46.410] <TB3> INFO: Test took 226555ms.
[13:38:46.489] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:38:46.753] <TB3> INFO: Expecting 655360 events.
[13:39:01.010] <TB3> INFO: 655360 events read in total (13665ms).
[13:39:01.025] <TB3> INFO: Expecting 655360 events.
[13:39:14.910] <TB3> INFO: 655360 events read in total (13482ms).
[13:39:14.925] <TB3> INFO: Expecting 655360 events.
[13:39:28.617] <TB3> INFO: 655360 events read in total (13289ms).
[13:39:28.634] <TB3> INFO: Expecting 655360 events.
[13:39:42.514] <TB3> INFO: 655360 events read in total (13477ms).
[13:39:42.536] <TB3> INFO: Expecting 655360 events.
[13:39:56.400] <TB3> INFO: 655360 events read in total (13461ms).
[13:39:56.426] <TB3> INFO: Expecting 655360 events.
[13:40:10.345] <TB3> INFO: 655360 events read in total (13516ms).
[13:40:10.375] <TB3> INFO: Expecting 655360 events.
[13:40:24.247] <TB3> INFO: 655360 events read in total (13469ms).
[13:40:24.280] <TB3> INFO: Expecting 655360 events.
[13:40:38.207] <TB3> INFO: 655360 events read in total (13524ms).
[13:40:38.259] <TB3> INFO: Expecting 655360 events.
[13:40:52.162] <TB3> INFO: 655360 events read in total (13501ms).
[13:40:52.204] <TB3> INFO: Expecting 655360 events.
[13:41:06.035] <TB3> INFO: 655360 events read in total (13428ms).
[13:41:06.097] <TB3> INFO: Expecting 655360 events.
[13:41:20.171] <TB3> INFO: 655360 events read in total (13671ms).
[13:41:20.222] <TB3> INFO: Expecting 655360 events.
[13:41:34.176] <TB3> INFO: 655360 events read in total (13551ms).
[13:41:34.232] <TB3> INFO: Expecting 655360 events.
[13:41:48.213] <TB3> INFO: 655360 events read in total (13578ms).
[13:41:48.273] <TB3> INFO: Expecting 655360 events.
[13:42:01.839] <TB3> INFO: 655360 events read in total (13163ms).
[13:42:01.901] <TB3> INFO: Expecting 655360 events.
[13:42:15.864] <TB3> INFO: 655360 events read in total (13560ms).
[13:42:15.932] <TB3> INFO: Expecting 655360 events.
[13:42:29.869] <TB3> INFO: 655360 events read in total (13534ms).
[13:42:29.941] <TB3> INFO: Test took 223453ms.
[13:42:30.161] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.167] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.173] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.180] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[13:42:30.186] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[13:42:30.192] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[13:42:30.198] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[13:42:30.204] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[13:42:30.210] <TB3> INFO: safety margin for low PH: adding 6, margin is now 26
[13:42:30.216] <TB3> INFO: safety margin for low PH: adding 7, margin is now 27
[13:42:30.222] <TB3> INFO: safety margin for low PH: adding 8, margin is now 28
[13:42:30.228] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.234] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.240] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.246] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.252] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.258] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[13:42:30.265] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[13:42:30.271] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[13:42:30.277] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[13:42:30.283] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.290] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[13:42:30.296] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[13:42:30.302] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[13:42:30.308] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[13:42:30.314] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[13:42:30.321] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.327] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.333] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[13:42:30.339] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[13:42:30.345] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[13:42:30.351] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[13:42:30.357] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.364] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[13:42:30.371] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.377] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.383] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.389] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[13:42:30.396] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[13:42:30.402] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[13:42:30.408] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:30.443] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C0.dat
[13:42:30.444] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C1.dat
[13:42:30.444] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C2.dat
[13:42:30.444] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C3.dat
[13:42:30.444] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C4.dat
[13:42:30.444] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C5.dat
[13:42:30.444] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C6.dat
[13:42:30.444] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C7.dat
[13:42:30.444] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C8.dat
[13:42:30.444] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C9.dat
[13:42:30.445] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C10.dat
[13:42:30.445] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C11.dat
[13:42:30.445] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C12.dat
[13:42:30.445] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C13.dat
[13:42:30.445] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C14.dat
[13:42:30.445] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C15.dat
[13:42:30.681] <TB3> INFO: Expecting 41600 events.
[13:42:33.814] <TB3> INFO: 41600 events read in total (2541ms).
[13:42:33.815] <TB3> INFO: Test took 3366ms.
[13:42:34.279] <TB3> INFO: Expecting 41600 events.
[13:42:37.278] <TB3> INFO: 41600 events read in total (2408ms).
[13:42:37.279] <TB3> INFO: Test took 3251ms.
[13:42:37.751] <TB3> INFO: Expecting 41600 events.
[13:42:40.825] <TB3> INFO: 41600 events read in total (2482ms).
[13:42:40.826] <TB3> INFO: Test took 3335ms.
[13:42:41.041] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:41.130] <TB3> INFO: Expecting 2560 events.
[13:42:42.012] <TB3> INFO: 2560 events read in total (291ms).
[13:42:42.012] <TB3> INFO: Test took 971ms.
[13:42:42.014] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:42.320] <TB3> INFO: Expecting 2560 events.
[13:42:43.204] <TB3> INFO: 2560 events read in total (292ms).
[13:42:43.205] <TB3> INFO: Test took 1191ms.
[13:42:43.206] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:43.513] <TB3> INFO: Expecting 2560 events.
[13:42:44.396] <TB3> INFO: 2560 events read in total (291ms).
[13:42:44.396] <TB3> INFO: Test took 1190ms.
[13:42:44.398] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:44.705] <TB3> INFO: Expecting 2560 events.
[13:42:45.587] <TB3> INFO: 2560 events read in total (291ms).
[13:42:45.588] <TB3> INFO: Test took 1190ms.
[13:42:45.590] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:45.896] <TB3> INFO: Expecting 2560 events.
[13:42:46.782] <TB3> INFO: 2560 events read in total (294ms).
[13:42:46.782] <TB3> INFO: Test took 1192ms.
[13:42:46.784] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:47.090] <TB3> INFO: Expecting 2560 events.
[13:42:47.973] <TB3> INFO: 2560 events read in total (291ms).
[13:42:47.973] <TB3> INFO: Test took 1189ms.
[13:42:47.975] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:48.282] <TB3> INFO: Expecting 2560 events.
[13:42:49.166] <TB3> INFO: 2560 events read in total (293ms).
[13:42:49.166] <TB3> INFO: Test took 1191ms.
[13:42:49.168] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:49.475] <TB3> INFO: Expecting 2560 events.
[13:42:50.358] <TB3> INFO: 2560 events read in total (292ms).
[13:42:50.358] <TB3> INFO: Test took 1190ms.
[13:42:50.360] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:50.666] <TB3> INFO: Expecting 2560 events.
[13:42:51.547] <TB3> INFO: 2560 events read in total (289ms).
[13:42:51.547] <TB3> INFO: Test took 1187ms.
[13:42:51.549] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:51.855] <TB3> INFO: Expecting 2560 events.
[13:42:52.734] <TB3> INFO: 2560 events read in total (287ms).
[13:42:52.734] <TB3> INFO: Test took 1185ms.
[13:42:52.736] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:53.042] <TB3> INFO: Expecting 2560 events.
[13:42:53.921] <TB3> INFO: 2560 events read in total (287ms).
[13:42:53.921] <TB3> INFO: Test took 1185ms.
[13:42:53.923] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:54.230] <TB3> INFO: Expecting 2560 events.
[13:42:55.109] <TB3> INFO: 2560 events read in total (287ms).
[13:42:55.110] <TB3> INFO: Test took 1187ms.
[13:42:55.112] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:55.417] <TB3> INFO: Expecting 2560 events.
[13:42:56.300] <TB3> INFO: 2560 events read in total (291ms).
[13:42:56.300] <TB3> INFO: Test took 1188ms.
[13:42:56.303] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:56.609] <TB3> INFO: Expecting 2560 events.
[13:42:57.488] <TB3> INFO: 2560 events read in total (288ms).
[13:42:57.488] <TB3> INFO: Test took 1186ms.
[13:42:57.490] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:57.797] <TB3> INFO: Expecting 2560 events.
[13:42:58.675] <TB3> INFO: 2560 events read in total (287ms).
[13:42:58.675] <TB3> INFO: Test took 1185ms.
[13:42:58.677] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:42:58.983] <TB3> INFO: Expecting 2560 events.
[13:42:59.862] <TB3> INFO: 2560 events read in total (287ms).
[13:42:59.863] <TB3> INFO: Test took 1186ms.
[13:42:59.864] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:00.171] <TB3> INFO: Expecting 2560 events.
[13:43:01.051] <TB3> INFO: 2560 events read in total (288ms).
[13:43:01.051] <TB3> INFO: Test took 1187ms.
[13:43:01.053] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:01.359] <TB3> INFO: Expecting 2560 events.
[13:43:02.241] <TB3> INFO: 2560 events read in total (290ms).
[13:43:02.241] <TB3> INFO: Test took 1188ms.
[13:43:02.243] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:02.549] <TB3> INFO: Expecting 2560 events.
[13:43:03.431] <TB3> INFO: 2560 events read in total (290ms).
[13:43:03.432] <TB3> INFO: Test took 1189ms.
[13:43:03.434] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:03.740] <TB3> INFO: Expecting 2560 events.
[13:43:04.622] <TB3> INFO: 2560 events read in total (290ms).
[13:43:04.622] <TB3> INFO: Test took 1188ms.
[13:43:04.624] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:04.930] <TB3> INFO: Expecting 2560 events.
[13:43:05.813] <TB3> INFO: 2560 events read in total (291ms).
[13:43:05.813] <TB3> INFO: Test took 1189ms.
[13:43:05.815] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:06.121] <TB3> INFO: Expecting 2560 events.
[13:43:06.000] <TB3> INFO: 2560 events read in total (287ms).
[13:43:06.001] <TB3> INFO: Test took 1186ms.
[13:43:06.003] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:07.309] <TB3> INFO: Expecting 2560 events.
[13:43:08.188] <TB3> INFO: 2560 events read in total (287ms).
[13:43:08.188] <TB3> INFO: Test took 1185ms.
[13:43:08.190] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:08.497] <TB3> INFO: Expecting 2560 events.
[13:43:09.374] <TB3> INFO: 2560 events read in total (286ms).
[13:43:09.374] <TB3> INFO: Test took 1184ms.
[13:43:09.376] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:09.683] <TB3> INFO: Expecting 2560 events.
[13:43:10.565] <TB3> INFO: 2560 events read in total (291ms).
[13:43:10.565] <TB3> INFO: Test took 1189ms.
[13:43:10.567] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:10.874] <TB3> INFO: Expecting 2560 events.
[13:43:11.762] <TB3> INFO: 2560 events read in total (296ms).
[13:43:11.762] <TB3> INFO: Test took 1195ms.
[13:43:11.764] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:12.070] <TB3> INFO: Expecting 2560 events.
[13:43:12.953] <TB3> INFO: 2560 events read in total (291ms).
[13:43:12.953] <TB3> INFO: Test took 1189ms.
[13:43:12.955] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:13.262] <TB3> INFO: Expecting 2560 events.
[13:43:14.149] <TB3> INFO: 2560 events read in total (296ms).
[13:43:14.149] <TB3> INFO: Test took 1194ms.
[13:43:14.151] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:14.457] <TB3> INFO: Expecting 2560 events.
[13:43:15.344] <TB3> INFO: 2560 events read in total (295ms).
[13:43:15.345] <TB3> INFO: Test took 1194ms.
[13:43:15.346] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:15.653] <TB3> INFO: Expecting 2560 events.
[13:43:16.537] <TB3> INFO: 2560 events read in total (292ms).
[13:43:16.538] <TB3> INFO: Test took 1192ms.
[13:43:16.540] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:16.846] <TB3> INFO: Expecting 2560 events.
[13:43:17.731] <TB3> INFO: 2560 events read in total (293ms).
[13:43:17.731] <TB3> INFO: Test took 1192ms.
[13:43:17.733] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:18.039] <TB3> INFO: Expecting 2560 events.
[13:43:18.922] <TB3> INFO: 2560 events read in total (291ms).
[13:43:18.923] <TB3> INFO: Test took 1190ms.
[13:43:19.385] <TB3> INFO: PixTestPhOptimization::doTest() done, duration: 632 seconds
[13:43:19.385] <TB3> INFO: PH scale (per ROC): 44 33 43 34 35 43 52 46 32 36 38 42 37 31 37 48
[13:43:19.385] <TB3> INFO: PH offset (per ROC): 108 86 108 96 88 82 132 100 110 101 110 117 93 100 86 102
[13:43:19.390] <TB3> INFO: Decoding statistics:
[13:43:19.390] <TB3> INFO: General information:
[13:43:19.390] <TB3> INFO: 16bit words read: 127888
[13:43:19.390] <TB3> INFO: valid events total: 20480
[13:43:19.390] <TB3> INFO: empty events: 17976
[13:43:19.390] <TB3> INFO: valid events with pixels: 2504
[13:43:19.390] <TB3> INFO: valid pixel hits: 2504
[13:43:19.390] <TB3> INFO: Event errors: 0
[13:43:19.390] <TB3> INFO: start marker: 0
[13:43:19.390] <TB3> INFO: stop marker: 0
[13:43:19.390] <TB3> INFO: overflow: 0
[13:43:19.390] <TB3> INFO: invalid 5bit words: 0
[13:43:19.390] <TB3> INFO: invalid XOR eye diagram: 0
[13:43:19.390] <TB3> INFO: frame (failed synchr.): 0
[13:43:19.390] <TB3> INFO: idle data (no TBM trl): 0
[13:43:19.390] <TB3> INFO: no data (only TBM hdr): 0
[13:43:19.390] <TB3> INFO: TBM errors: 0
[13:43:19.390] <TB3> INFO: flawed TBM headers: 0
[13:43:19.390] <TB3> INFO: flawed TBM trailers: 0
[13:43:19.390] <TB3> INFO: event ID mismatches: 0
[13:43:19.390] <TB3> INFO: ROC errors: 0
[13:43:19.390] <TB3> INFO: missing ROC header(s): 0
[13:43:19.390] <TB3> INFO: misplaced readback start: 0
[13:43:19.390] <TB3> INFO: Pixel decoding errors: 0
[13:43:19.390] <TB3> INFO: pixel data incomplete: 0
[13:43:19.390] <TB3> INFO: pixel address: 0
[13:43:19.390] <TB3> INFO: pulse height fill bit: 0
[13:43:19.390] <TB3> INFO: buffer corruption: 0
[13:43:19.655] <TB3> INFO: ######################################################################
[13:43:19.655] <TB3> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:43:19.655] <TB3> INFO: ######################################################################
[13:43:19.668] <TB3> INFO: scanning low vcal = 10
[13:43:19.908] <TB3> INFO: Expecting 41600 events.
[13:43:23.466] <TB3> INFO: 41600 events read in total (2967ms).
[13:43:23.466] <TB3> INFO: Test took 3798ms.
[13:43:23.468] <TB3> INFO: scanning low vcal = 20
[13:43:23.767] <TB3> INFO: Expecting 41600 events.
[13:43:27.344] <TB3> INFO: 41600 events read in total (2986ms).
[13:43:27.345] <TB3> INFO: Test took 3877ms.
[13:43:27.347] <TB3> INFO: scanning low vcal = 30
[13:43:27.645] <TB3> INFO: Expecting 41600 events.
[13:43:31.260] <TB3> INFO: 41600 events read in total (3023ms).
[13:43:31.261] <TB3> INFO: Test took 3914ms.
[13:43:31.263] <TB3> INFO: scanning low vcal = 40
[13:43:31.544] <TB3> INFO: Expecting 41600 events.
[13:43:35.439] <TB3> INFO: 41600 events read in total (3303ms).
[13:43:35.440] <TB3> INFO: Test took 4177ms.
[13:43:35.443] <TB3> INFO: scanning low vcal = 50
[13:43:35.719] <TB3> INFO: Expecting 41600 events.
[13:43:39.660] <TB3> INFO: 41600 events read in total (3349ms).
[13:43:39.661] <TB3> INFO: Test took 4218ms.
[13:43:39.664] <TB3> INFO: scanning low vcal = 60
[13:43:39.941] <TB3> INFO: Expecting 41600 events.
[13:43:43.873] <TB3> INFO: 41600 events read in total (3341ms).
[13:43:43.873] <TB3> INFO: Test took 4209ms.
[13:43:43.876] <TB3> INFO: scanning low vcal = 70
[13:43:44.153] <TB3> INFO: Expecting 41600 events.
[13:43:48.085] <TB3> INFO: 41600 events read in total (3341ms).
[13:43:48.085] <TB3> INFO: Test took 4209ms.
[13:43:48.088] <TB3> INFO: scanning low vcal = 80
[13:43:48.365] <TB3> INFO: Expecting 41600 events.
[13:43:52.302] <TB3> INFO: 41600 events read in total (3345ms).
[13:43:52.302] <TB3> INFO: Test took 4214ms.
[13:43:52.305] <TB3> INFO: scanning low vcal = 90
[13:43:52.581] <TB3> INFO: Expecting 41600 events.
[13:43:56.529] <TB3> INFO: 41600 events read in total (3356ms).
[13:43:56.530] <TB3> INFO: Test took 4225ms.
[13:43:56.532] <TB3> INFO: scanning low vcal = 100
[13:43:56.809] <TB3> INFO: Expecting 41600 events.
[13:44:00.735] <TB3> INFO: 41600 events read in total (3335ms).
[13:44:00.736] <TB3> INFO: Test took 4203ms.
[13:44:00.739] <TB3> INFO: scanning low vcal = 110
[13:44:01.023] <TB3> INFO: Expecting 41600 events.
[13:44:04.966] <TB3> INFO: 41600 events read in total (3351ms).
[13:44:04.967] <TB3> INFO: Test took 4228ms.
[13:44:04.971] <TB3> INFO: scanning low vcal = 120
[13:44:05.247] <TB3> INFO: Expecting 41600 events.
[13:44:09.179] <TB3> INFO: 41600 events read in total (3341ms).
[13:44:09.179] <TB3> INFO: Test took 4208ms.
[13:44:09.182] <TB3> INFO: scanning low vcal = 130
[13:44:09.459] <TB3> INFO: Expecting 41600 events.
[13:44:13.460] <TB3> INFO: 41600 events read in total (3410ms).
[13:44:13.461] <TB3> INFO: Test took 4279ms.
[13:44:13.464] <TB3> INFO: scanning low vcal = 140
[13:44:13.740] <TB3> INFO: Expecting 41600 events.
[13:44:17.718] <TB3> INFO: 41600 events read in total (3386ms).
[13:44:17.719] <TB3> INFO: Test took 4255ms.
[13:44:17.723] <TB3> INFO: scanning low vcal = 150
[13:44:17.999] <TB3> INFO: Expecting 41600 events.
[13:44:21.943] <TB3> INFO: 41600 events read in total (3353ms).
[13:44:21.943] <TB3> INFO: Test took 4220ms.
[13:44:21.947] <TB3> INFO: scanning low vcal = 160
[13:44:22.223] <TB3> INFO: Expecting 41600 events.
[13:44:26.174] <TB3> INFO: 41600 events read in total (3360ms).
[13:44:26.175] <TB3> INFO: Test took 4228ms.
[13:44:26.177] <TB3> INFO: scanning low vcal = 170
[13:44:26.454] <TB3> INFO: Expecting 41600 events.
[13:44:30.398] <TB3> INFO: 41600 events read in total (3352ms).
[13:44:30.399] <TB3> INFO: Test took 4222ms.
[13:44:30.402] <TB3> INFO: scanning low vcal = 180
[13:44:30.678] <TB3> INFO: Expecting 41600 events.
[13:44:34.611] <TB3> INFO: 41600 events read in total (3341ms).
[13:44:34.611] <TB3> INFO: Test took 4209ms.
[13:44:34.614] <TB3> INFO: scanning low vcal = 190
[13:44:34.891] <TB3> INFO: Expecting 41600 events.
[13:44:38.845] <TB3> INFO: 41600 events read in total (3363ms).
[13:44:38.845] <TB3> INFO: Test took 4231ms.
[13:44:38.848] <TB3> INFO: scanning low vcal = 200
[13:44:39.124] <TB3> INFO: Expecting 41600 events.
[13:44:43.068] <TB3> INFO: 41600 events read in total (3352ms).
[13:44:43.068] <TB3> INFO: Test took 4220ms.
[13:44:43.071] <TB3> INFO: scanning low vcal = 210
[13:44:43.348] <TB3> INFO: Expecting 41600 events.
[13:44:47.292] <TB3> INFO: 41600 events read in total (3353ms).
[13:44:47.293] <TB3> INFO: Test took 4222ms.
[13:44:47.295] <TB3> INFO: scanning low vcal = 220
[13:44:47.572] <TB3> INFO: Expecting 41600 events.
[13:44:51.519] <TB3> INFO: 41600 events read in total (3356ms).
[13:44:51.520] <TB3> INFO: Test took 4225ms.
[13:44:51.522] <TB3> INFO: scanning low vcal = 230
[13:44:51.799] <TB3> INFO: Expecting 41600 events.
[13:44:55.770] <TB3> INFO: 41600 events read in total (3379ms).
[13:44:55.770] <TB3> INFO: Test took 4248ms.
[13:44:55.773] <TB3> INFO: scanning low vcal = 240
[13:44:56.049] <TB3> INFO: Expecting 41600 events.
[13:45:00.026] <TB3> INFO: 41600 events read in total (3385ms).
[13:45:00.026] <TB3> INFO: Test took 4253ms.
[13:45:00.029] <TB3> INFO: scanning low vcal = 250
[13:45:00.306] <TB3> INFO: Expecting 41600 events.
[13:45:04.276] <TB3> INFO: 41600 events read in total (3379ms).
[13:45:04.277] <TB3> INFO: Test took 4248ms.
[13:45:04.281] <TB3> INFO: scanning high vcal = 30 (= 210 in low range)
[13:45:04.557] <TB3> INFO: Expecting 41600 events.
[13:45:08.514] <TB3> INFO: 41600 events read in total (3366ms).
[13:45:08.514] <TB3> INFO: Test took 4233ms.
[13:45:08.517] <TB3> INFO: scanning high vcal = 50 (= 350 in low range)
[13:45:08.793] <TB3> INFO: Expecting 41600 events.
[13:45:12.721] <TB3> INFO: 41600 events read in total (3336ms).
[13:45:12.722] <TB3> INFO: Test took 4205ms.
[13:45:12.725] <TB3> INFO: scanning high vcal = 70 (= 490 in low range)
[13:45:12.001] <TB3> INFO: Expecting 41600 events.
[13:45:16.928] <TB3> INFO: 41600 events read in total (3335ms).
[13:45:16.928] <TB3> INFO: Test took 4203ms.
[13:45:16.931] <TB3> INFO: scanning high vcal = 90 (= 630 in low range)
[13:45:17.209] <TB3> INFO: Expecting 41600 events.
[13:45:21.156] <TB3> INFO: 41600 events read in total (3355ms).
[13:45:21.157] <TB3> INFO: Test took 4226ms.
[13:45:21.159] <TB3> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:45:21.436] <TB3> INFO: Expecting 41600 events.
[13:45:25.428] <TB3> INFO: 41600 events read in total (3400ms).
[13:45:25.429] <TB3> INFO: Test took 4269ms.
[13:45:26.004] <TB3> INFO: PixTestGainPedestal::measure() done
[13:46:05.333] <TB3> INFO: PixTestGainPedestal::fit() done
[13:46:05.333] <TB3> INFO: non-linearity mean: 0.948 1.015 0.947 1.022 0.999 0.925 0.978 0.932 0.949 0.901 0.981 0.938 0.929 0.951 0.942 0.969
[13:46:05.333] <TB3> INFO: non-linearity RMS: 0.042 0.194 0.072 0.177 0.191 0.141 0.005 0.086 0.186 0.121 0.184 0.095 0.112 0.170 0.070 0.023
[13:46:05.333] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[13:46:05.356] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[13:46:05.378] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[13:46:05.401] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[13:46:05.424] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[13:46:05.447] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[13:46:05.470] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[13:46:05.493] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[13:46:05.515] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[13:46:05.538] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[13:46:05.561] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[13:46:05.584] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[13:46:05.606] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[13:46:05.629] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[13:46:05.652] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[13:46:05.675] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[13:46:05.697] <TB3> INFO: PixTestGainPedestal::fullTest() done, duration: 166 seconds
[13:46:05.697] <TB3> INFO: Decoding statistics:
[13:46:05.697] <TB3> INFO: General information:
[13:46:05.697] <TB3> INFO: 16bit words read: 3312308
[13:46:05.697] <TB3> INFO: valid events total: 332800
[13:46:05.697] <TB3> INFO: empty events: 663
[13:46:05.697] <TB3> INFO: valid events with pixels: 332137
[13:46:05.697] <TB3> INFO: valid pixel hits: 657754
[13:46:05.697] <TB3> INFO: Event errors: 0
[13:46:05.697] <TB3> INFO: start marker: 0
[13:46:05.697] <TB3> INFO: stop marker: 0
[13:46:05.697] <TB3> INFO: overflow: 0
[13:46:05.697] <TB3> INFO: invalid 5bit words: 0
[13:46:05.697] <TB3> INFO: invalid XOR eye diagram: 0
[13:46:05.697] <TB3> INFO: frame (failed synchr.): 0
[13:46:05.697] <TB3> INFO: idle data (no TBM trl): 0
[13:46:05.697] <TB3> INFO: no data (only TBM hdr): 0
[13:46:05.698] <TB3> INFO: TBM errors: 0
[13:46:05.698] <TB3> INFO: flawed TBM headers: 0
[13:46:05.698] <TB3> INFO: flawed TBM trailers: 0
[13:46:05.698] <TB3> INFO: event ID mismatches: 0
[13:46:05.698] <TB3> INFO: ROC errors: 0
[13:46:05.698] <TB3> INFO: missing ROC header(s): 0
[13:46:05.698] <TB3> INFO: misplaced readback start: 0
[13:46:05.698] <TB3> INFO: Pixel decoding errors: 0
[13:46:05.698] <TB3> INFO: pixel data incomplete: 0
[13:46:05.698] <TB3> INFO: pixel address: 0
[13:46:05.698] <TB3> INFO: pulse height fill bit: 0
[13:46:05.698] <TB3> INFO: buffer corruption: 0
[13:46:05.718] <TB3> INFO: Decoding statistics:
[13:46:05.718] <TB3> INFO: General information:
[13:46:05.718] <TB3> INFO: 16bit words read: 3441732
[13:46:05.718] <TB3> INFO: valid events total: 353536
[13:46:05.718] <TB3> INFO: empty events: 18895
[13:46:05.718] <TB3> INFO: valid events with pixels: 334641
[13:46:05.718] <TB3> INFO: valid pixel hits: 660258
[13:46:05.718] <TB3> INFO: Event errors: 0
[13:46:05.718] <TB3> INFO: start marker: 0
[13:46:05.718] <TB3> INFO: stop marker: 0
[13:46:05.718] <TB3> INFO: overflow: 0
[13:46:05.718] <TB3> INFO: invalid 5bit words: 0
[13:46:05.718] <TB3> INFO: invalid XOR eye diagram: 0
[13:46:05.718] <TB3> INFO: frame (failed synchr.): 0
[13:46:05.718] <TB3> INFO: idle data (no TBM trl): 0
[13:46:05.718] <TB3> INFO: no data (only TBM hdr): 0
[13:46:05.718] <TB3> INFO: TBM errors: 0
[13:46:05.718] <TB3> INFO: flawed TBM headers: 0
[13:46:05.718] <TB3> INFO: flawed TBM trailers: 0
[13:46:05.718] <TB3> INFO: event ID mismatches: 0
[13:46:05.718] <TB3> INFO: ROC errors: 0
[13:46:05.718] <TB3> INFO: missing ROC header(s): 0
[13:46:05.718] <TB3> INFO: misplaced readback start: 0
[13:46:05.718] <TB3> INFO: Pixel decoding errors: 0
[13:46:05.718] <TB3> INFO: pixel data incomplete: 0
[13:46:05.718] <TB3> INFO: pixel address: 0
[13:46:05.718] <TB3> INFO: pulse height fill bit: 0
[13:46:05.718] <TB3> INFO: buffer corruption: 0
[13:46:05.719] <TB3> INFO: enter test to run
[13:46:05.719] <TB3> INFO: test: Trim80 no parameter change
[13:46:05.719] <TB3> INFO: running: trim80
[13:46:05.741] <TB3> INFO: ######################################################################
[13:46:05.741] <TB3> INFO: PixTestTrim80::doTest()
[13:46:05.741] <TB3> INFO: ######################################################################
[13:46:05.742] <TB3> INFO: ----------------------------------------------------------------------
[13:46:05.742] <TB3> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[13:46:05.742] <TB3> INFO: ----------------------------------------------------------------------
[13:46:05.808] <TB3> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:46:05.808] <TB3> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:46:05.819] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:46:05.820] <TB3> INFO: run 1 of 1
[13:46:06.073] <TB3> INFO: Expecting 5025280 events.
[13:46:33.765] <TB3> INFO: 680936 events read in total (27101ms).
[13:47:00.857] <TB3> INFO: 1357024 events read in total (54193ms).
[13:47:27.945] <TB3> INFO: 2030416 events read in total (81281ms).
[13:47:54.432] <TB3> INFO: 2702864 events read in total (107768ms).
[13:48:21.220] <TB3> INFO: 3371736 events read in total (134556ms).
[13:48:47.901] <TB3> INFO: 4039912 events read in total (161237ms).
[13:49:14.642] <TB3> INFO: 4708264 events read in total (187978ms).
[13:49:27.453] <TB3> INFO: 5025280 events read in total (200789ms).
[13:49:27.513] <TB3> INFO: Test took 201693ms.
[13:49:50.914] <TB3> INFO: ROC 0 VthrComp = 78
[13:49:50.915] <TB3> INFO: ROC 1 VthrComp = 73
[13:49:50.915] <TB3> INFO: ROC 2 VthrComp = 79
[13:49:50.915] <TB3> INFO: ROC 3 VthrComp = 71
[13:49:50.916] <TB3> INFO: ROC 4 VthrComp = 72
[13:49:50.916] <TB3> INFO: ROC 5 VthrComp = 74
[13:49:50.916] <TB3> INFO: ROC 6 VthrComp = 70
[13:49:50.916] <TB3> INFO: ROC 7 VthrComp = 88
[13:49:50.916] <TB3> INFO: ROC 8 VthrComp = 66
[13:49:50.916] <TB3> INFO: ROC 9 VthrComp = 75
[13:49:50.916] <TB3> INFO: ROC 10 VthrComp = 70
[13:49:50.917] <TB3> INFO: ROC 11 VthrComp = 71
[13:49:50.917] <TB3> INFO: ROC 12 VthrComp = 66
[13:49:50.917] <TB3> INFO: ROC 13 VthrComp = 68
[13:49:50.917] <TB3> INFO: ROC 14 VthrComp = 77
[13:49:50.917] <TB3> INFO: ROC 15 VthrComp = 76
[13:49:51.153] <TB3> INFO: Expecting 41600 events.
[13:49:54.628] <TB3> INFO: 41600 events read in total (2883ms).
[13:49:54.629] <TB3> INFO: Test took 3710ms.
[13:49:54.640] <TB3> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:49:54.640] <TB3> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:49:54.651] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:49:54.651] <TB3> INFO: run 1 of 1
[13:49:54.929] <TB3> INFO: Expecting 5025280 events.
[13:50:22.640] <TB3> INFO: 686896 events read in total (27119ms).
[13:50:49.985] <TB3> INFO: 1370424 events read in total (54464ms).
[13:51:16.764] <TB3> INFO: 2052392 events read in total (81243ms).
[13:51:43.839] <TB3> INFO: 2731016 events read in total (108318ms).
[13:52:10.641] <TB3> INFO: 3405256 events read in total (135120ms).
[13:52:37.631] <TB3> INFO: 4075792 events read in total (162110ms).
[13:53:04.628] <TB3> INFO: 4746016 events read in total (189107ms).
[13:53:15.884] <TB3> INFO: 5025280 events read in total (200363ms).
[13:53:15.945] <TB3> INFO: Test took 201293ms.
[13:53:41.056] <TB3> INFO: roc 0 with ID = 0 has maximal Vcal 108.855 for pixel 17/50 mean/min/max = 93.3339/77.6639/109.004
[13:53:41.056] <TB3> INFO: roc 1 with ID = 1 has maximal Vcal 107.687 for pixel 3/75 mean/min/max = 92.2631/76.7663/107.76
[13:53:41.057] <TB3> INFO: roc 2 with ID = 2 has maximal Vcal 109.796 for pixel 0/4 mean/min/max = 93.6487/77.327/109.97
[13:53:41.058] <TB3> INFO: roc 3 with ID = 3 has maximal Vcal 105.613 for pixel 5/21 mean/min/max = 90.0485/74.4748/105.622
[13:53:41.058] <TB3> INFO: roc 4 with ID = 4 has maximal Vcal 108.605 for pixel 0/39 mean/min/max = 92.7204/76.7326/108.708
[13:53:41.059] <TB3> INFO: roc 5 with ID = 5 has maximal Vcal 109.753 for pixel 36/74 mean/min/max = 94.0718/78.1984/109.945
[13:53:41.059] <TB3> INFO: roc 6 with ID = 6 has maximal Vcal 106.82 for pixel 3/79 mean/min/max = 90.8761/74.7116/107.041
[13:53:41.060] <TB3> INFO: roc 7 with ID = 7 has maximal Vcal 107.653 for pixel 26/79 mean/min/max = 91.8062/75.9371/107.675
[13:53:41.060] <TB3> INFO: roc 8 with ID = 8 has maximal Vcal 111.886 for pixel 0/46 mean/min/max = 92.8545/73.7459/111.963
[13:53:41.060] <TB3> INFO: roc 9 with ID = 9 has maximal Vcal 112.331 for pixel 0/14 mean/min/max = 95.2068/77.867/112.546
[13:53:41.061] <TB3> INFO: roc 10 with ID = 10 has maximal Vcal 106.895 for pixel 0/40 mean/min/max = 91.0385/75.1733/106.904
[13:53:41.061] <TB3> INFO: roc 11 with ID = 11 has maximal Vcal 107.094 for pixel 9/42 mean/min/max = 90.7826/74.3463/107.219
[13:53:41.062] <TB3> INFO: roc 12 with ID = 12 has maximal Vcal 114.309 for pixel 1/0 mean/min/max = 94.2298/74.0282/114.431
[13:53:41.062] <TB3> INFO: roc 13 with ID = 13 has maximal Vcal 117.056 for pixel 48/2 mean/min/max = 95.6481/73.7209/117.575
[13:53:41.063] <TB3> INFO: roc 14 with ID = 14 has maximal Vcal 105.902 for pixel 49/23 mean/min/max = 92.1052/78.2464/105.964
[13:53:41.063] <TB3> INFO: roc 15 with ID = 15 has maximal Vcal 107.749 for pixel 0/1 mean/min/max = 93.6011/79.4067/107.795
[13:53:41.063] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:53:41.152] <TB3> INFO: Expecting 411648 events.
[13:53:50.541] <TB3> INFO: 411648 events read in total (8797ms).
[13:53:50.548] <TB3> INFO: Expecting 411648 events.
[13:53:59.750] <TB3> INFO: 411648 events read in total (8799ms).
[13:53:59.762] <TB3> INFO: Expecting 411648 events.
[13:54:08.814] <TB3> INFO: 411648 events read in total (8648ms).
[13:54:08.825] <TB3> INFO: Expecting 411648 events.
[13:54:17.970] <TB3> INFO: 411648 events read in total (8742ms).
[13:54:17.985] <TB3> INFO: Expecting 411648 events.
[13:54:27.048] <TB3> INFO: 411648 events read in total (8660ms).
[13:54:27.070] <TB3> INFO: Expecting 411648 events.
[13:54:36.159] <TB3> INFO: 411648 events read in total (8686ms).
[13:54:36.178] <TB3> INFO: Expecting 411648 events.
[13:54:45.328] <TB3> INFO: 411648 events read in total (8747ms).
[13:54:45.357] <TB3> INFO: Expecting 411648 events.
[13:54:54.544] <TB3> INFO: 411648 events read in total (8784ms).
[13:54:54.577] <TB3> INFO: Expecting 411648 events.
[13:55:03.696] <TB3> INFO: 411648 events read in total (8716ms).
[13:55:03.724] <TB3> INFO: Expecting 411648 events.
[13:55:12.868] <TB3> INFO: 411648 events read in total (8741ms).
[13:55:12.900] <TB3> INFO: Expecting 411648 events.
[13:55:21.939] <TB3> INFO: 411648 events read in total (8636ms).
[13:55:21.972] <TB3> INFO: Expecting 411648 events.
[13:55:31.102] <TB3> INFO: 411648 events read in total (8727ms).
[13:55:31.137] <TB3> INFO: Expecting 411648 events.
[13:55:40.228] <TB3> INFO: 411648 events read in total (8688ms).
[13:55:40.267] <TB3> INFO: Expecting 411648 events.
[13:55:49.425] <TB3> INFO: 411648 events read in total (8755ms).
[13:55:49.467] <TB3> INFO: Expecting 411648 events.
[13:55:58.635] <TB3> INFO: 411648 events read in total (8765ms).
[13:55:58.680] <TB3> INFO: Expecting 411648 events.
[13:56:07.889] <TB3> INFO: 411648 events read in total (8806ms).
[13:56:07.935] <TB3> INFO: Test took 146872ms.
[13:56:09.524] <TB3> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:56:09.534] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[13:56:09.534] <TB3> INFO: run 1 of 1
[13:56:09.809] <TB3> INFO: Expecting 5025280 events.
[13:56:36.753] <TB3> INFO: 667544 events read in total (26352ms).
[13:57:03.127] <TB3> INFO: 1332736 events read in total (52726ms).
[13:57:29.868] <TB3> INFO: 1996168 events read in total (79467ms).
[13:57:56.544] <TB3> INFO: 2655512 events read in total (106143ms).
[13:58:23.201] <TB3> INFO: 3310112 events read in total (132800ms).
[13:58:50.212] <TB3> INFO: 3963224 events read in total (159811ms).
[13:59:16.538] <TB3> INFO: 4614400 events read in total (186137ms).
[13:59:33.207] <TB3> INFO: 5025280 events read in total (202806ms).
[13:59:33.255] <TB3> INFO: Test took 203721ms.
[13:59:58.757] <TB3> INFO: ---> TrimStepCorr4 extremal thresholds: 44.943102 .. 102.401902
[13:59:59.028] <TB3> INFO: Expecting 208000 events.
[14:00:08.805] <TB3> INFO: 208000 events read in total (9185ms).
[14:00:08.806] <TB3> INFO: Test took 10046ms.
[14:00:08.856] <TB3> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 34 .. 112 (-1/-1) hits flags = 528 (plus default)
[14:00:08.865] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:00:08.865] <TB3> INFO: run 1 of 1
[14:00:09.143] <TB3> INFO: Expecting 2629120 events.
[14:00:37.403] <TB3> INFO: 704168 events read in total (27669ms).
[14:01:04.964] <TB3> INFO: 1405712 events read in total (55230ms).
[14:01:32.315] <TB3> INFO: 2099888 events read in total (82581ms).
[14:01:53.868] <TB3> INFO: 2629120 events read in total (104134ms).
[14:01:53.905] <TB3> INFO: Test took 105040ms.
[14:02:13.597] <TB3> INFO: ---> TrimStepCorr2 extremal thresholds: 56.064664 .. 92.550185
[14:02:13.848] <TB3> INFO: Expecting 208000 events.
[14:02:23.717] <TB3> INFO: 208000 events read in total (9277ms).
[14:02:23.718] <TB3> INFO: Test took 10119ms.
[14:02:23.764] <TB3> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 46 .. 102 (-1/-1) hits flags = 528 (plus default)
[14:02:23.772] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:02:23.772] <TB3> INFO: run 1 of 1
[14:02:24.050] <TB3> INFO: Expecting 1896960 events.
[14:02:52.696] <TB3> INFO: 704960 events read in total (28055ms).
[14:03:20.320] <TB3> INFO: 1410056 events read in total (55679ms).
[14:03:40.067] <TB3> INFO: 1896960 events read in total (75426ms).
[14:03:40.095] <TB3> INFO: Test took 76324ms.
[14:03:58.682] <TB3> INFO: ---> TrimStepCorr1a extremal thresholds: 62.870635 .. 87.959151
[14:03:58.915] <TB3> INFO: Expecting 208000 events.
[14:04:08.549] <TB3> INFO: 208000 events read in total (9042ms).
[14:04:08.549] <TB3> INFO: Test took 9867ms.
[14:04:08.597] <TB3> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 52 .. 97 (-1/-1) hits flags = 528 (plus default)
[14:04:08.606] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:04:08.606] <TB3> INFO: run 1 of 1
[14:04:08.884] <TB3> INFO: Expecting 1530880 events.
[14:04:37.205] <TB3> INFO: 711544 events read in total (27730ms).
[14:05:05.091] <TB3> INFO: 1422424 events read in total (55616ms).
[14:05:09.886] <TB3> INFO: 1530880 events read in total (60412ms).
[14:05:09.916] <TB3> INFO: Test took 61311ms.
[14:05:27.335] <TB3> INFO: ---> TrimStepCorr1b extremal thresholds: 65.016776 .. 87.340438
[14:05:27.586] <TB3> INFO: Expecting 208000 events.
[14:05:37.277] <TB3> INFO: 208000 events read in total (9099ms).
[14:05:37.277] <TB3> INFO: Test took 9941ms.
[14:05:37.324] <TB3> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 55 .. 97 (-1/-1) hits flags = 528 (plus default)
[14:05:37.334] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:05:37.334] <TB3> INFO: run 1 of 1
[14:05:37.612] <TB3> INFO: Expecting 1431040 events.
[14:06:06.175] <TB3> INFO: 702072 events read in total (27972ms).
[14:06:34.026] <TB3> INFO: 1404288 events read in total (55823ms).
[14:06:35.578] <TB3> INFO: 1431040 events read in total (57375ms).
[14:06:35.606] <TB3> INFO: Test took 58273ms.
[14:06:52.092] <TB3> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[14:06:52.092] <TB3> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[14:06:52.102] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:06:52.102] <TB3> INFO: run 1 of 1
[14:06:52.343] <TB3> INFO: Expecting 1364480 events.
[14:07:20.219] <TB3> INFO: 668992 events read in total (27285ms).
[14:07:47.838] <TB3> INFO: 1337552 events read in total (54904ms).
[14:07:49.377] <TB3> INFO: 1364480 events read in total (56443ms).
[14:07:49.396] <TB3> INFO: Test took 57294ms.
[14:08:06.702] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C0.dat
[14:08:06.702] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C1.dat
[14:08:06.703] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C2.dat
[14:08:06.703] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C3.dat
[14:08:06.703] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C4.dat
[14:08:06.703] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C5.dat
[14:08:06.703] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C6.dat
[14:08:06.703] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C7.dat
[14:08:06.703] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C8.dat
[14:08:06.703] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C9.dat
[14:08:06.703] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C10.dat
[14:08:06.703] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C11.dat
[14:08:06.703] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C12.dat
[14:08:06.704] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C13.dat
[14:08:06.704] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C14.dat
[14:08:06.704] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C15.dat
[14:08:06.704] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C0.dat
[14:08:06.711] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C1.dat
[14:08:06.718] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C2.dat
[14:08:06.726] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C3.dat
[14:08:06.733] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C4.dat
[14:08:06.740] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C5.dat
[14:08:06.747] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C6.dat
[14:08:06.755] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C7.dat
[14:08:06.762] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C8.dat
[14:08:06.769] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C9.dat
[14:08:06.776] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C10.dat
[14:08:06.784] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C11.dat
[14:08:06.791] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C12.dat
[14:08:06.798] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C13.dat
[14:08:06.805] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C14.dat
[14:08:06.814] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1107_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C15.dat
[14:08:06.822] <TB3> INFO: PixTestTrim80::trimTest() done
[14:08:06.822] <TB3> INFO: vtrim: 113 110 122 89 116 115 92 131 116 119 100 92 104 123 101 108
[14:08:06.822] <TB3> INFO: vthrcomp: 78 73 79 71 72 74 70 88 66 75 70 71 66 68 77 76
[14:08:06.822] <TB3> INFO: vcal mean: 80.03 80.01 79.99 80.01 80.01 80.01 79.98 80.04 80.00 80.01 79.98 80.01 80.00 80.02 79.99 79.99
[14:08:06.822] <TB3> INFO: vcal RMS: 0.79 0.73 0.74 0.72 0.77 0.75 0.73 0.79 0.83 0.82 0.74 0.75 0.81 0.94 0.80 0.72
[14:08:06.822] <TB3> INFO: bits mean: 10.23 9.92 9.62 10.25 10.06 9.42 10.18 10.48 10.31 9.77 10.17 10.21 9.96 10.30 10.04 9.31
[14:08:06.822] <TB3> INFO: bits RMS: 2.02 2.24 2.24 2.43 2.18 2.22 2.41 2.11 2.42 2.09 2.39 2.40 2.44 2.24 2.03 2.12
[14:08:06.829] <TB3> INFO: ----------------------------------------------------------------------
[14:08:06.829] <TB3> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:08:06.829] <TB3> INFO: ----------------------------------------------------------------------
[14:08:06.831] <TB3> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:08:06.840] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[14:08:06.840] <TB3> INFO: run 1 of 1
[14:08:07.113] <TB3> INFO: Expecting 4160000 events.
[14:08:39.668] <TB3> INFO: 767680 events read in total (31963ms).
[14:09:11.629] <TB3> INFO: 1527970 events read in total (63924ms).
[14:09:43.189] <TB3> INFO: 2281065 events read in total (95484ms).
[14:10:14.645] <TB3> INFO: 3028965 events read in total (126940ms).
[14:10:46.007] <TB3> INFO: 3772185 events read in total (158302ms).
[14:11:02.548] <TB3> INFO: 4160000 events read in total (174843ms).
[14:11:02.608] <TB3> INFO: Test took 175768ms.
[14:11:32.773] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 210 (-1/-1) hits flags = 528 (plus default)
[14:11:32.781] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[14:11:32.781] <TB3> INFO: run 1 of 1
[14:11:33.018] <TB3> INFO: Expecting 4388800 events.
[14:12:04.441] <TB3> INFO: 727810 events read in total (30831ms).
[14:12:35.268] <TB3> INFO: 1450385 events read in total (61658ms).
[14:13:05.987] <TB3> INFO: 2167385 events read in total (92377ms).
[14:13:36.758] <TB3> INFO: 2880345 events read in total (123148ms).
[14:14:07.048] <TB3> INFO: 3588530 events read in total (153438ms).
[14:14:37.529] <TB3> INFO: 4295995 events read in total (183919ms).
[14:14:42.015] <TB3> INFO: 4388800 events read in total (188405ms).
[14:14:42.088] <TB3> INFO: Test took 189307ms.
[14:15:14.710] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[14:15:14.721] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[14:15:14.721] <TB3> INFO: run 1 of 1
[14:15:14.997] <TB3> INFO: Expecting 4284800 events.
[14:15:46.924] <TB3> INFO: 734515 events read in total (31336ms).
[14:16:17.659] <TB3> INFO: 1463460 events read in total (62071ms).
[14:16:48.552] <TB3> INFO: 2186930 events read in total (92964ms).
[14:17:19.046] <TB3> INFO: 2905830 events read in total (123458ms).
[14:17:49.430] <TB3> INFO: 3619625 events read in total (153842ms).
[14:18:18.079] <TB3> INFO: 4284800 events read in total (182491ms).
[14:18:18.148] <TB3> INFO: Test took 183427ms.
[14:18:46.094] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[14:18:46.104] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[14:18:46.104] <TB3> INFO: run 1 of 1
[14:18:46.337] <TB3> INFO: Expecting 4284800 events.
[14:19:18.271] <TB3> INFO: 734675 events read in total (31342ms).
[14:19:49.181] <TB3> INFO: 1463615 events read in total (62252ms).
[14:20:20.378] <TB3> INFO: 2187380 events read in total (93450ms).
[14:20:51.258] <TB3> INFO: 2906430 events read in total (124329ms).
[14:21:21.984] <TB3> INFO: 3620410 events read in total (155055ms).
[14:21:51.081] <TB3> INFO: 4284800 events read in total (184152ms).
[14:21:51.143] <TB3> INFO: Test took 185039ms.
[14:22:20.722] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[14:22:20.733] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[14:22:20.733] <TB3> INFO: run 1 of 1
[14:22:21.012] <TB3> INFO: Expecting 4097600 events.
[14:22:53.469] <TB3> INFO: 747460 events read in total (31866ms).
[14:23:24.615] <TB3> INFO: 1489085 events read in total (63012ms).
[14:23:55.880] <TB3> INFO: 2224185 events read in total (94278ms).
[14:24:27.338] <TB3> INFO: 2953895 events read in total (125735ms).
[14:24:58.490] <TB3> INFO: 3678815 events read in total (156887ms).
[14:25:16.361] <TB3> INFO: 4097600 events read in total (174758ms).
[14:25:16.425] <TB3> INFO: Test took 175691ms.
[14:25:43.721] <TB3> INFO: PixTestTrim80::trimBitTest() done
[14:25:43.723] <TB3> INFO: PixTestTrim80::doTest() done, duration: 2378 seconds
[14:25:44.657] <TB3> INFO: enter test to run
[14:25:44.657] <TB3> INFO: test: exit no parameter change
[14:25:44.784] <TB3> QUIET: Connection to board 170 closed.
[14:25:44.785] <TB3> INFO: pXar: this is the end, my friend