[20:08:03.103] <TB1> INFO: *** Welcome to pxar ***
[20:08:03.103] <TB1> INFO: *** Today: 2016/11/04
[20:08:03.111] <TB1> INFO: *** Version: c8ba-dirty
[20:08:03.111] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C15.dat
[20:08:03.112] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[20:08:03.112] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//defaultMaskFile.dat
[20:08:03.112] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters_C15.dat
[20:08:03.174] <TB1> INFO: clk: 4
[20:08:03.174] <TB1> INFO: ctr: 4
[20:08:03.174] <TB1> INFO: sda: 19
[20:08:03.174] <TB1> INFO: tin: 9
[20:08:03.174] <TB1> INFO: level: 15
[20:08:03.174] <TB1> INFO: triggerdelay: 0
[20:08:03.174] <TB1> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[20:08:03.174] <TB1> INFO: Log level: INFO
[20:08:03.184] <TB1> INFO: Found DTB DTB_WXC03A
[20:08:03.195] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[20:08:03.197] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
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[20:08:03.199] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[20:08:04.688] <TB1> INFO: DUT info:
[20:08:04.688] <TB1> INFO: The DUT currently contains the following objects:
[20:08:04.688] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[20:08:04.688] <TB1> INFO: TBM Core alpha (0): 7 registers set
[20:08:04.688] <TB1> INFO: TBM Core beta (1): 7 registers set
[20:08:04.688] <TB1> INFO: TBM Core alpha (2): 7 registers set
[20:08:04.688] <TB1> INFO: TBM Core beta (3): 7 registers set
[20:08:04.688] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[20:08:04.688] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.688] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.688] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.688] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.688] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.688] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.688] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.688] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.688] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.688] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.688] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.688] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.688] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.688] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.688] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:04.689] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[20:08:05.089] <TB1> INFO: enter 'restricted' command line mode
[20:08:05.089] <TB1> INFO: enter test to run
[20:08:05.090] <TB1> INFO: test: pretest no parameter change
[20:08:05.090] <TB1> INFO: running: pretest
[20:08:05.094] <TB1> INFO: ######################################################################
[20:08:05.094] <TB1> INFO: PixTestPretest::doTest()
[20:08:05.094] <TB1> INFO: ######################################################################
[20:08:05.095] <TB1> INFO: ----------------------------------------------------------------------
[20:08:05.095] <TB1> INFO: PixTestPretest::programROC()
[20:08:05.095] <TB1> INFO: ----------------------------------------------------------------------
[20:08:23.109] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[20:08:23.109] <TB1> INFO: IA differences per ROC: 19.3 20.1 17.7 19.3 21.7 18.5 20.1 20.9 20.1 20.9 18.5 18.5 20.9 17.7 18.5 18.5
[20:08:23.169] <TB1> INFO: ----------------------------------------------------------------------
[20:08:23.170] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[20:08:23.170] <TB1> INFO: ----------------------------------------------------------------------
[20:08:30.271] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 381 mA = 23.8125 mA/ROC
[20:08:30.271] <TB1> INFO: i(loss) [mA/ROC]: 19.2 19.2 18.4 18.4 19.2 18.4 19.2 18.4 18.4 18.4 18.4 19.2 19.2 19.2 19.2 18.4
[20:08:30.303] <TB1> INFO: ----------------------------------------------------------------------
[20:08:30.303] <TB1> INFO: PixTestPretest::findTiming()
[20:08:30.303] <TB1> INFO: ----------------------------------------------------------------------
[20:08:30.303] <TB1> INFO: PixTestCmd::init()

[20:09:02.617] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[20:09:02.617] <TB1> INFO: (success/tries = 100/100), width = 4
[20:09:04.118] <TB1> INFO: ----------------------------------------------------------------------
[20:09:04.118] <TB1> INFO: PixTestPretest::findWorkingPixel()
[20:09:04.118] <TB1> INFO: ----------------------------------------------------------------------
[20:09:04.214] <TB1> INFO: Expecting 231680 events.
[20:09:14.220] <TB1> INFO: 231680 events read in total (9414ms).
[20:09:14.230] <TB1> INFO: Test took 10106ms.
[20:09:14.478] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[20:09:14.514] <TB1> INFO: ----------------------------------------------------------------------
[20:09:14.514] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[20:09:14.515] <TB1> INFO: ----------------------------------------------------------------------
[20:09:14.608] <TB1> INFO: Expecting 231680 events.
[20:09:24.541] <TB1> INFO: 231680 events read in total (9341ms).
[20:09:24.554] <TB1> INFO: Test took 10035ms.
[20:09:24.822] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[20:09:24.822] <TB1> INFO: CalDel: 113 71 78 94 78 98 95 92 81 87 88 73 68 87 96 90
[20:09:24.822] <TB1> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 53 51
[20:09:24.826] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C0.dat
[20:09:24.826] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C1.dat
[20:09:24.826] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C2.dat
[20:09:24.827] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C3.dat
[20:09:24.827] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C4.dat
[20:09:24.827] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C5.dat
[20:09:24.827] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C6.dat
[20:09:24.827] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C7.dat
[20:09:24.827] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C8.dat
[20:09:24.828] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C9.dat
[20:09:24.828] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C10.dat
[20:09:24.828] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C11.dat
[20:09:24.828] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C12.dat
[20:09:24.828] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C13.dat
[20:09:24.828] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C14.dat
[20:09:24.828] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters_C15.dat
[20:09:24.829] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[20:09:24.829] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[20:09:24.829] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[20:09:24.829] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[20:09:24.829] <TB1> INFO: PixTestPretest::doTest() done, duration: 79 seconds
[20:09:24.883] <TB1> INFO: enter test to run
[20:09:24.883] <TB1> INFO: test: fulltest no parameter change
[20:09:24.883] <TB1> INFO: running: fulltest
[20:09:24.883] <TB1> INFO: ######################################################################
[20:09:24.883] <TB1> INFO: PixTestFullTest::doTest()
[20:09:24.883] <TB1> INFO: ######################################################################
[20:09:24.885] <TB1> INFO: ######################################################################
[20:09:24.885] <TB1> INFO: PixTestAlive::doTest()
[20:09:24.885] <TB1> INFO: ######################################################################
[20:09:24.886] <TB1> INFO: ----------------------------------------------------------------------
[20:09:24.886] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[20:09:24.886] <TB1> INFO: ----------------------------------------------------------------------
[20:09:25.123] <TB1> INFO: Expecting 41600 events.
[20:09:28.695] <TB1> INFO: 41600 events read in total (2980ms).
[20:09:28.696] <TB1> INFO: Test took 3809ms.
[20:09:28.930] <TB1> INFO: PixTestAlive::aliveTest() done
[20:09:28.930] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
[20:09:28.932] <TB1> INFO: ----------------------------------------------------------------------
[20:09:28.932] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[20:09:28.932] <TB1> INFO: ----------------------------------------------------------------------
[20:09:29.220] <TB1> INFO: Expecting 41600 events.
[20:09:32.171] <TB1> INFO: 41600 events read in total (2360ms).
[20:09:32.171] <TB1> INFO: Test took 3238ms.
[20:09:32.172] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[20:09:32.411] <TB1> INFO: PixTestAlive::maskTest() done
[20:09:32.411] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[20:09:32.412] <TB1> INFO: ----------------------------------------------------------------------
[20:09:32.412] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[20:09:32.412] <TB1> INFO: ----------------------------------------------------------------------
[20:09:32.654] <TB1> INFO: Expecting 41600 events.
[20:09:36.170] <TB1> INFO: 41600 events read in total (2924ms).
[20:09:36.171] <TB1> INFO: Test took 3756ms.
[20:09:36.405] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[20:09:36.405] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[20:09:36.405] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[20:09:36.405] <TB1> INFO: Decoding statistics:
[20:09:36.405] <TB1> INFO: General information:
[20:09:36.405] <TB1> INFO: 16bit words read: 0
[20:09:36.405] <TB1> INFO: valid events total: 0
[20:09:36.405] <TB1> INFO: empty events: 0
[20:09:36.405] <TB1> INFO: valid events with pixels: 0
[20:09:36.406] <TB1> INFO: valid pixel hits: 0
[20:09:36.406] <TB1> INFO: Event errors: 0
[20:09:36.406] <TB1> INFO: start marker: 0
[20:09:36.406] <TB1> INFO: stop marker: 0
[20:09:36.406] <TB1> INFO: overflow: 0
[20:09:36.406] <TB1> INFO: invalid 5bit words: 0
[20:09:36.406] <TB1> INFO: invalid XOR eye diagram: 0
[20:09:36.406] <TB1> INFO: frame (failed synchr.): 0
[20:09:36.406] <TB1> INFO: idle data (no TBM trl): 0
[20:09:36.406] <TB1> INFO: no data (only TBM hdr): 0
[20:09:36.406] <TB1> INFO: TBM errors: 0
[20:09:36.406] <TB1> INFO: flawed TBM headers: 0
[20:09:36.406] <TB1> INFO: flawed TBM trailers: 0
[20:09:36.406] <TB1> INFO: event ID mismatches: 0
[20:09:36.406] <TB1> INFO: ROC errors: 0
[20:09:36.406] <TB1> INFO: missing ROC header(s): 0
[20:09:36.406] <TB1> INFO: misplaced readback start: 0
[20:09:36.406] <TB1> INFO: Pixel decoding errors: 0
[20:09:36.406] <TB1> INFO: pixel data incomplete: 0
[20:09:36.406] <TB1> INFO: pixel address: 0
[20:09:36.406] <TB1> INFO: pulse height fill bit: 0
[20:09:36.406] <TB1> INFO: buffer corruption: 0
[20:09:36.416] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C15.dat
[20:09:36.416] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[20:09:36.416] <TB1> INFO: ######################################################################
[20:09:36.416] <TB1> INFO: PixTestReadback::doTest()
[20:09:36.416] <TB1> INFO: ######################################################################
[20:09:36.416] <TB1> INFO: ----------------------------------------------------------------------
[20:09:36.416] <TB1> INFO: PixTestReadback::CalibrateVd()
[20:09:36.416] <TB1> INFO: ----------------------------------------------------------------------
[20:09:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C0.dat
[20:09:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C1.dat
[20:09:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C2.dat
[20:09:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C3.dat
[20:09:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C4.dat
[20:09:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C5.dat
[20:09:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C6.dat
[20:09:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C7.dat
[20:09:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C8.dat
[20:09:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C9.dat
[20:09:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C10.dat
[20:09:46.384] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C11.dat
[20:09:46.384] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C12.dat
[20:09:46.384] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C13.dat
[20:09:46.384] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C14.dat
[20:09:46.384] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C15.dat
[20:09:46.413] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[20:09:46.413] <TB1> INFO: ----------------------------------------------------------------------
[20:09:46.413] <TB1> INFO: PixTestReadback::CalibrateVa()
[20:09:46.413] <TB1> INFO: ----------------------------------------------------------------------
[20:09:56.332] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C0.dat
[20:09:56.332] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C1.dat
[20:09:56.332] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C2.dat
[20:09:56.332] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C3.dat
[20:09:56.332] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C4.dat
[20:09:56.332] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C5.dat
[20:09:56.332] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C6.dat
[20:09:56.332] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C7.dat
[20:09:56.332] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C8.dat
[20:09:56.332] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C9.dat
[20:09:56.332] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C10.dat
[20:09:56.332] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C11.dat
[20:09:56.333] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C12.dat
[20:09:56.333] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C13.dat
[20:09:56.333] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C14.dat
[20:09:56.333] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C15.dat
[20:09:56.364] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[20:09:56.364] <TB1> INFO: ----------------------------------------------------------------------
[20:09:56.364] <TB1> INFO: PixTestReadback::readbackVbg()
[20:09:56.364] <TB1> INFO: ----------------------------------------------------------------------
[20:10:04.029] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[20:10:04.029] <TB1> INFO: ----------------------------------------------------------------------
[20:10:04.029] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[20:10:04.029] <TB1> INFO: ----------------------------------------------------------------------
[20:10:04.029] <TB1> INFO: Vbg will be calibrated using Vd calibration
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 149.9calibrated Vbg = 1.21 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 157calibrated Vbg = 1.19808 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 151.5calibrated Vbg = 1.19753 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 153.1calibrated Vbg = 1.18654 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 158.7calibrated Vbg = 1.1974 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 156.5calibrated Vbg = 1.20382 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 165.4calibrated Vbg = 1.20581 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 160.4calibrated Vbg = 1.20202 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 155.5calibrated Vbg = 1.19076 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154.9calibrated Vbg = 1.1936 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 165.8calibrated Vbg = 1.19386 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 155.6calibrated Vbg = 1.17954 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 161.7calibrated Vbg = 1.19602 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 160.7calibrated Vbg = 1.19552 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 156calibrated Vbg = 1.19591 :::*/*/*/*/
[20:10:04.029] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 154.7calibrated Vbg = 1.19837 :::*/*/*/*/
[20:10:04.033] <TB1> INFO: ----------------------------------------------------------------------
[20:10:04.033] <TB1> INFO: PixTestReadback::CalibrateIa()
[20:10:04.033] <TB1> INFO: ----------------------------------------------------------------------
[20:12:44.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C0.dat
[20:12:44.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C1.dat
[20:12:44.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C2.dat
[20:12:44.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C3.dat
[20:12:44.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C4.dat
[20:12:44.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C5.dat
[20:12:44.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C6.dat
[20:12:44.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C7.dat
[20:12:44.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C8.dat
[20:12:44.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C9.dat
[20:12:44.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C10.dat
[20:12:44.876] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C11.dat
[20:12:44.877] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C12.dat
[20:12:44.877] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C13.dat
[20:12:44.877] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C14.dat
[20:12:44.877] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//readbackCal_C15.dat
[20:12:44.906] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[20:12:44.908] <TB1> INFO: PixTestReadback::doTest() done
[20:12:44.908] <TB1> INFO: Decoding statistics:
[20:12:44.908] <TB1> INFO: General information:
[20:12:44.908] <TB1> INFO: 16bit words read: 1536
[20:12:44.908] <TB1> INFO: valid events total: 256
[20:12:44.908] <TB1> INFO: empty events: 256
[20:12:44.908] <TB1> INFO: valid events with pixels: 0
[20:12:44.908] <TB1> INFO: valid pixel hits: 0
[20:12:44.908] <TB1> INFO: Event errors: 0
[20:12:44.908] <TB1> INFO: start marker: 0
[20:12:44.908] <TB1> INFO: stop marker: 0
[20:12:44.908] <TB1> INFO: overflow: 0
[20:12:44.908] <TB1> INFO: invalid 5bit words: 0
[20:12:44.908] <TB1> INFO: invalid XOR eye diagram: 0
[20:12:44.908] <TB1> INFO: frame (failed synchr.): 0
[20:12:44.908] <TB1> INFO: idle data (no TBM trl): 0
[20:12:44.908] <TB1> INFO: no data (only TBM hdr): 0
[20:12:44.908] <TB1> INFO: TBM errors: 0
[20:12:44.908] <TB1> INFO: flawed TBM headers: 0
[20:12:44.909] <TB1> INFO: flawed TBM trailers: 0
[20:12:44.909] <TB1> INFO: event ID mismatches: 0
[20:12:44.909] <TB1> INFO: ROC errors: 0
[20:12:44.909] <TB1> INFO: missing ROC header(s): 0
[20:12:44.909] <TB1> INFO: misplaced readback start: 0
[20:12:44.909] <TB1> INFO: Pixel decoding errors: 0
[20:12:44.909] <TB1> INFO: pixel data incomplete: 0
[20:12:44.909] <TB1> INFO: pixel address: 0
[20:12:44.909] <TB1> INFO: pulse height fill bit: 0
[20:12:44.909] <TB1> INFO: buffer corruption: 0
[20:12:44.960] <TB1> INFO: ######################################################################
[20:12:44.960] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[20:12:44.960] <TB1> INFO: ######################################################################
[20:12:44.962] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[20:12:44.978] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[20:12:44.978] <TB1> INFO: run 1 of 1
[20:12:45.262] <TB1> INFO: Expecting 3120000 events.
[20:13:17.774] <TB1> INFO: 661310 events read in total (31920ms).
[20:13:48.646] <TB1> INFO: 1317855 events read in total (62792ms).












[20:14:19.363] <TB1> INFO: 1970785 events read in total (93509ms).
[20:14:49.796] <TB1> INFO: 2622985 events read in total (123942ms).











[20:15:12.994] <TB1> INFO: 3120000 events read in total (147140ms).
[20:15:13.070] <TB1> INFO: Test took 148093ms.
[20:15:39.541] <TB1> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 174 seconds
[20:15:39.541] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 3
[20:15:39.541] <TB1> INFO: separation cut (per ROC): 98 108 103 104 106 97 105 96 108 107 104 113 112 103 107 103
[20:15:39.541] <TB1> INFO: Decoding statistics:
[20:15:39.541] <TB1> INFO: General information:
[20:15:39.541] <TB1> INFO: 16bit words read: 0
[20:15:39.541] <TB1> INFO: valid events total: 0
[20:15:39.541] <TB1> INFO: empty events: 0
[20:15:39.541] <TB1> INFO: valid events with pixels: 0
[20:15:39.541] <TB1> INFO: valid pixel hits: 0
[20:15:39.541] <TB1> INFO: Event errors: 0
[20:15:39.541] <TB1> INFO: start marker: 0
[20:15:39.541] <TB1> INFO: stop marker: 0
[20:15:39.541] <TB1> INFO: overflow: 0
[20:15:39.541] <TB1> INFO: invalid 5bit words: 0
[20:15:39.541] <TB1> INFO: invalid XOR eye diagram: 0
[20:15:39.541] <TB1> INFO: frame (failed synchr.): 0
[20:15:39.541] <TB1> INFO: idle data (no TBM trl): 0
[20:15:39.541] <TB1> INFO: no data (only TBM hdr): 0
[20:15:39.541] <TB1> INFO: TBM errors: 0
[20:15:39.541] <TB1> INFO: flawed TBM headers: 0
[20:15:39.541] <TB1> INFO: flawed TBM trailers: 0
[20:15:39.541] <TB1> INFO: event ID mismatches: 0
[20:15:39.541] <TB1> INFO: ROC errors: 0
[20:15:39.541] <TB1> INFO: missing ROC header(s): 0
[20:15:39.542] <TB1> INFO: misplaced readback start: 0
[20:15:39.542] <TB1> INFO: Pixel decoding errors: 0
[20:15:39.542] <TB1> INFO: pixel data incomplete: 0
[20:15:39.542] <TB1> INFO: pixel address: 0
[20:15:39.542] <TB1> INFO: pulse height fill bit: 0
[20:15:39.542] <TB1> INFO: buffer corruption: 0
[20:15:39.581] <TB1> INFO: ######################################################################
[20:15:39.581] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[20:15:39.581] <TB1> INFO: ######################################################################
[20:15:39.581] <TB1> INFO: ----------------------------------------------------------------------
[20:15:39.581] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[20:15:39.581] <TB1> INFO: ----------------------------------------------------------------------
[20:15:39.582] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[20:15:39.596] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[20:15:39.596] <TB1> INFO: run 1 of 1
[20:15:39.832] <TB1> INFO: Expecting 36608000 events.
[20:16:03.593] <TB1> INFO: 701350 events read in total (23169ms).
[20:16:26.784] <TB1> INFO: 1384200 events read in total (46360ms).
[20:16:49.886] <TB1> INFO: 2066650 events read in total (69462ms).
[20:17:12.652] <TB1> INFO: 2748750 events read in total (92228ms).
[20:17:35.719] <TB1> INFO: 3428350 events read in total (115295ms).
[20:17:58.627] <TB1> INFO: 4106350 events read in total (138203ms).
[20:18:21.787] <TB1> INFO: 4788300 events read in total (161363ms).
[20:18:44.997] <TB1> INFO: 5470350 events read in total (184573ms).
[20:19:08.359] <TB1> INFO: 6150150 events read in total (207935ms).
[20:19:31.402] <TB1> INFO: 6829750 events read in total (230978ms).
[20:19:54.252] <TB1> INFO: 7507050 events read in total (253828ms).
[20:20:17.510] <TB1> INFO: 8183750 events read in total (277086ms).
[20:20:40.648] <TB1> INFO: 8864650 events read in total (300224ms).
[20:21:03.769] <TB1> INFO: 9544950 events read in total (323345ms).
[20:21:26.786] <TB1> INFO: 10222650 events read in total (346362ms).
[20:21:49.806] <TB1> INFO: 10901600 events read in total (369382ms).
[20:22:13.053] <TB1> INFO: 11579350 events read in total (392629ms).
[20:22:36.169] <TB1> INFO: 12256150 events read in total (415745ms).
[20:22:59.432] <TB1> INFO: 12933200 events read in total (439008ms).
[20:23:22.591] <TB1> INFO: 13610650 events read in total (462167ms).
[20:23:45.801] <TB1> INFO: 14287200 events read in total (485377ms).
[20:24:08.890] <TB1> INFO: 14962550 events read in total (508466ms).
[20:24:31.999] <TB1> INFO: 15636550 events read in total (531575ms).
[20:24:55.145] <TB1> INFO: 16312350 events read in total (554721ms).
[20:25:18.378] <TB1> INFO: 16987350 events read in total (577954ms).
[20:25:41.551] <TB1> INFO: 17660800 events read in total (601127ms).
[20:26:04.774] <TB1> INFO: 18333550 events read in total (624350ms).
[20:26:27.941] <TB1> INFO: 19005850 events read in total (647517ms).
[20:26:50.868] <TB1> INFO: 19676400 events read in total (670444ms).
[20:27:14.042] <TB1> INFO: 20347700 events read in total (693618ms).
[20:27:36.987] <TB1> INFO: 21017750 events read in total (716563ms).
[20:27:59.992] <TB1> INFO: 21687950 events read in total (739568ms).
[20:28:23.048] <TB1> INFO: 22356700 events read in total (762624ms).
[20:28:46.131] <TB1> INFO: 23027250 events read in total (785707ms).
[20:29:09.184] <TB1> INFO: 23697000 events read in total (808760ms).
[20:29:32.221] <TB1> INFO: 24366050 events read in total (831797ms).
[20:29:55.674] <TB1> INFO: 25034350 events read in total (855250ms).
[20:30:18.816] <TB1> INFO: 25703300 events read in total (878392ms).
[20:30:42.094] <TB1> INFO: 26372400 events read in total (901670ms).
[20:31:05.351] <TB1> INFO: 27040800 events read in total (924927ms).
[20:31:28.643] <TB1> INFO: 27709050 events read in total (948219ms).
[20:31:51.747] <TB1> INFO: 28376600 events read in total (971323ms).
[20:32:14.890] <TB1> INFO: 29043750 events read in total (994466ms).
[20:32:38.316] <TB1> INFO: 29711150 events read in total (1017892ms).
[20:33:01.608] <TB1> INFO: 30377100 events read in total (1041184ms).
[20:33:24.784] <TB1> INFO: 31043450 events read in total (1064360ms).
[20:33:47.773] <TB1> INFO: 31709050 events read in total (1087349ms).
[20:34:11.129] <TB1> INFO: 32374150 events read in total (1110705ms).
[20:34:34.274] <TB1> INFO: 33040250 events read in total (1133850ms).
[20:34:57.830] <TB1> INFO: 33706450 events read in total (1157406ms).
[20:35:21.112] <TB1> INFO: 34372300 events read in total (1180688ms).
[20:35:44.165] <TB1> INFO: 35037700 events read in total (1203741ms).
[20:36:07.396] <TB1> INFO: 35702400 events read in total (1226973ms).
[20:36:30.831] <TB1> INFO: 36377000 events read in total (1250407ms).
[20:36:39.040] <TB1> INFO: 36608000 events read in total (1258616ms).
[20:36:39.119] <TB1> INFO: Test took 1259523ms.
[20:36:39.660] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:36:41.705] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:36:43.552] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:36:45.203] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:36:46.618] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:36:48.578] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:36:50.540] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:36:52.455] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:36:54.431] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:36:56.374] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:36:58.421] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:37:00.439] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:37:02.217] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:37:04.483] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:37:06.662] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:37:08.957] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[20:37:11.303] <TB1> INFO: PixTestScurves::scurves() done
[20:37:11.303] <TB1> INFO: Vcal mean: 112.76 121.95 117.14 121.01 132.50 108.91 126.14 114.74 115.01 120.12 120.16 128.59 130.27 126.73 128.12 111.75
[20:37:11.303] <TB1> INFO: Vcal RMS: 4.94 6.37 5.67 5.97 6.84 5.22 5.74 7.18 5.19 6.11 9.34 5.92 5.40 6.24 6.58 5.00
[20:37:11.303] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1291 seconds
[20:37:11.303] <TB1> INFO: Decoding statistics:
[20:37:11.303] <TB1> INFO: General information:
[20:37:11.303] <TB1> INFO: 16bit words read: 0
[20:37:11.303] <TB1> INFO: valid events total: 0
[20:37:11.303] <TB1> INFO: empty events: 0
[20:37:11.303] <TB1> INFO: valid events with pixels: 0
[20:37:11.303] <TB1> INFO: valid pixel hits: 0
[20:37:11.303] <TB1> INFO: Event errors: 0
[20:37:11.304] <TB1> INFO: start marker: 0
[20:37:11.304] <TB1> INFO: stop marker: 0
[20:37:11.304] <TB1> INFO: overflow: 0
[20:37:11.304] <TB1> INFO: invalid 5bit words: 0
[20:37:11.304] <TB1> INFO: invalid XOR eye diagram: 0
[20:37:11.304] <TB1> INFO: frame (failed synchr.): 0
[20:37:11.304] <TB1> INFO: idle data (no TBM trl): 0
[20:37:11.304] <TB1> INFO: no data (only TBM hdr): 0
[20:37:11.304] <TB1> INFO: TBM errors: 0
[20:37:11.304] <TB1> INFO: flawed TBM headers: 0
[20:37:11.304] <TB1> INFO: flawed TBM trailers: 0
[20:37:11.304] <TB1> INFO: event ID mismatches: 0
[20:37:11.304] <TB1> INFO: ROC errors: 0
[20:37:11.304] <TB1> INFO: missing ROC header(s): 0
[20:37:11.304] <TB1> INFO: misplaced readback start: 0
[20:37:11.304] <TB1> INFO: Pixel decoding errors: 0
[20:37:11.304] <TB1> INFO: pixel data incomplete: 0
[20:37:11.304] <TB1> INFO: pixel address: 0
[20:37:11.304] <TB1> INFO: pulse height fill bit: 0
[20:37:11.304] <TB1> INFO: buffer corruption: 0
[20:37:11.397] <TB1> INFO: ######################################################################
[20:37:11.397] <TB1> INFO: PixTestTrim::doTest()
[20:37:11.397] <TB1> INFO: ######################################################################
[20:37:11.398] <TB1> INFO: ----------------------------------------------------------------------
[20:37:11.398] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[20:37:11.398] <TB1> INFO: ----------------------------------------------------------------------
[20:37:11.444] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[20:37:11.444] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[20:37:11.457] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:37:11.457] <TB1> INFO: run 1 of 1
[20:37:11.700] <TB1> INFO: Expecting 5025280 events.
[20:37:42.561] <TB1> INFO: 833992 events read in total (30258ms).
[20:38:13.003] <TB1> INFO: 1664720 events read in total (60700ms).
[20:38:43.370] <TB1> INFO: 2493248 events read in total (91068ms).
[20:39:13.662] <TB1> INFO: 3317696 events read in total (121359ms).
[20:39:44.331] <TB1> INFO: 4137568 events read in total (152029ms).
[20:40:14.301] <TB1> INFO: 4954784 events read in total (181998ms).
[20:40:17.329] <TB1> INFO: 5025280 events read in total (185026ms).
[20:40:17.381] <TB1> INFO: Test took 185924ms.
[20:40:33.829] <TB1> INFO: ROC 0 VthrComp = 119
[20:40:33.830] <TB1> INFO: ROC 1 VthrComp = 130
[20:40:33.830] <TB1> INFO: ROC 2 VthrComp = 122
[20:40:33.830] <TB1> INFO: ROC 3 VthrComp = 123
[20:40:33.830] <TB1> INFO: ROC 4 VthrComp = 134
[20:40:33.830] <TB1> INFO: ROC 5 VthrComp = 111
[20:40:33.830] <TB1> INFO: ROC 6 VthrComp = 129
[20:40:33.830] <TB1> INFO: ROC 7 VthrComp = 114
[20:40:33.831] <TB1> INFO: ROC 8 VthrComp = 124
[20:40:33.831] <TB1> INFO: ROC 9 VthrComp = 128
[20:40:33.831] <TB1> INFO: ROC 10 VthrComp = 118
[20:40:33.831] <TB1> INFO: ROC 11 VthrComp = 130
[20:40:33.831] <TB1> INFO: ROC 12 VthrComp = 135
[20:40:33.832] <TB1> INFO: ROC 13 VthrComp = 125
[20:40:33.832] <TB1> INFO: ROC 14 VthrComp = 128
[20:40:33.832] <TB1> INFO: ROC 15 VthrComp = 117
[20:40:34.075] <TB1> INFO: Expecting 41600 events.
[20:40:37.597] <TB1> INFO: 41600 events read in total (2931ms).
[20:40:37.598] <TB1> INFO: Test took 3765ms.
[20:40:37.607] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[20:40:37.607] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[20:40:37.618] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:40:37.618] <TB1> INFO: run 1 of 1
[20:40:37.896] <TB1> INFO: Expecting 5025280 events.
[20:41:04.310] <TB1> INFO: 591272 events read in total (25823ms).
[20:41:30.107] <TB1> INFO: 1181552 events read in total (51620ms).
[20:41:56.191] <TB1> INFO: 1772336 events read in total (77704ms).
[20:42:21.972] <TB1> INFO: 2362096 events read in total (103485ms).
[20:42:47.786] <TB1> INFO: 2949592 events read in total (129299ms).
[20:43:13.480] <TB1> INFO: 3535520 events read in total (154993ms).
[20:43:38.959] <TB1> INFO: 4120936 events read in total (180472ms).
[20:44:04.271] <TB1> INFO: 4704736 events read in total (205784ms).
[20:44:18.372] <TB1> INFO: 5025280 events read in total (219885ms).
[20:44:18.449] <TB1> INFO: Test took 220832ms.
[20:44:46.182] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 56.0238 for pixel 0/45 mean/min/max = 44.5028/32.7835/56.2221
[20:44:46.182] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 61.2814 for pixel 2/79 mean/min/max = 47.2089/33.0679/61.3499
[20:44:46.183] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 58.9489 for pixel 8/62 mean/min/max = 46.0446/32.9184/59.1708
[20:44:46.184] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 59.8394 for pixel 14/11 mean/min/max = 46.4868/32.9481/60.0254
[20:44:46.184] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 63.7173 for pixel 2/18 mean/min/max = 48.9897/34.2246/63.7547
[20:44:46.185] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 62.4118 for pixel 3/47 mean/min/max = 48.0778/33.7409/62.4147
[20:44:46.185] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 60.488 for pixel 22/2 mean/min/max = 46.6689/32.7463/60.5915
[20:44:46.186] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 66.3838 for pixel 0/12 mean/min/max = 47.9945/29.5926/66.3963
[20:44:46.186] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 57.3255 for pixel 4/69 mean/min/max = 45.3466/33.315/57.3782
[20:44:46.187] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 58.7164 for pixel 15/64 mean/min/max = 45.8198/32.843/58.7967
[20:44:46.187] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 68.7661 for pixel 0/2 mean/min/max = 48.9085/28.8989/68.9181
[20:44:46.188] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 63.5205 for pixel 11/6 mean/min/max = 49.7092/35.8837/63.5346
[20:44:46.188] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 62.354 for pixel 7/10 mean/min/max = 49.4167/36.4176/62.4159
[20:44:46.189] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 62.441 for pixel 9/72 mean/min/max = 47.8391/32.9164/62.7618
[20:44:46.189] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 64.2164 for pixel 2/10 mean/min/max = 49.1324/34.0203/64.2446
[20:44:46.190] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 57.4297 for pixel 6/60 mean/min/max = 45.2605/32.9783/57.5428
[20:44:46.191] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:44:46.279] <TB1> INFO: Expecting 411648 events.
[20:44:55.740] <TB1> INFO: 411648 events read in total (8869ms).
[20:44:55.748] <TB1> INFO: Expecting 411648 events.
[20:45:05.224] <TB1> INFO: 411648 events read in total (9073ms).
[20:45:05.234] <TB1> INFO: Expecting 411648 events.
[20:45:14.631] <TB1> INFO: 411648 events read in total (8993ms).
[20:45:14.645] <TB1> INFO: Expecting 411648 events.
[20:45:24.051] <TB1> INFO: 411648 events read in total (9003ms).
[20:45:24.073] <TB1> INFO: Expecting 411648 events.
[20:45:33.494] <TB1> INFO: 411648 events read in total (9018ms).
[20:45:33.518] <TB1> INFO: Expecting 411648 events.
[20:45:42.887] <TB1> INFO: 411648 events read in total (8966ms).
[20:45:42.909] <TB1> INFO: Expecting 411648 events.
[20:45:52.262] <TB1> INFO: 411648 events read in total (8949ms).
[20:45:52.294] <TB1> INFO: Expecting 411648 events.
[20:46:01.660] <TB1> INFO: 411648 events read in total (8963ms).
[20:46:01.688] <TB1> INFO: Expecting 411648 events.
[20:46:11.154] <TB1> INFO: 411648 events read in total (9063ms).
[20:46:11.183] <TB1> INFO: Expecting 411648 events.
[20:46:20.603] <TB1> INFO: 411648 events read in total (9016ms).
[20:46:20.645] <TB1> INFO: Expecting 411648 events.
[20:46:30.058] <TB1> INFO: 411648 events read in total (9010ms).
[20:46:30.103] <TB1> INFO: Expecting 411648 events.
[20:46:39.563] <TB1> INFO: 411648 events read in total (9057ms).
[20:46:39.602] <TB1> INFO: Expecting 411648 events.
[20:46:49.012] <TB1> INFO: 411648 events read in total (9008ms).
[20:46:49.174] <TB1> INFO: Expecting 411648 events.
[20:46:58.576] <TB1> INFO: 411648 events read in total (8999ms).
[20:46:58.623] <TB1> INFO: Expecting 411648 events.
[20:47:07.911] <TB1> INFO: 411648 events read in total (8885ms).
[20:47:07.968] <TB1> INFO: Expecting 411648 events.
[20:47:17.407] <TB1> INFO: 411648 events read in total (9036ms).
[20:47:17.460] <TB1> INFO: Test took 151269ms.
[20:47:18.258] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[20:47:18.271] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:47:18.271] <TB1> INFO: run 1 of 1
[20:47:18.507] <TB1> INFO: Expecting 5025280 events.
[20:47:45.094] <TB1> INFO: 588192 events read in total (25995ms).
[20:48:11.615] <TB1> INFO: 1175240 events read in total (52517ms).
[20:48:37.580] <TB1> INFO: 1761928 events read in total (78482ms).
[20:49:03.458] <TB1> INFO: 2347392 events read in total (104359ms).
[20:49:29.237] <TB1> INFO: 2931888 events read in total (130138ms).
[20:49:55.529] <TB1> INFO: 3516872 events read in total (156430ms).
[20:50:21.832] <TB1> INFO: 4100464 events read in total (182733ms).
[20:50:47.836] <TB1> INFO: 4684320 events read in total (208737ms).
[20:51:03.335] <TB1> INFO: 5025280 events read in total (224236ms).
[20:51:03.467] <TB1> INFO: Test took 225196ms.
[20:51:26.784] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 10.501522 .. 144.666627
[20:51:27.025] <TB1> INFO: Expecting 208000 events.
[20:51:36.453] <TB1> INFO: 208000 events read in total (8836ms).
[20:51:36.454] <TB1> INFO: Test took 9669ms.
[20:51:36.523] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 154 (-1/-1) hits flags = 528 (plus default)
[20:51:36.537] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:51:36.537] <TB1> INFO: run 1 of 1
[20:51:36.815] <TB1> INFO: Expecting 5158400 events.
[20:52:03.164] <TB1> INFO: 585248 events read in total (25757ms).
[20:52:29.390] <TB1> INFO: 1171000 events read in total (51984ms).
[20:52:55.262] <TB1> INFO: 1756952 events read in total (77855ms).
[20:53:20.827] <TB1> INFO: 2343328 events read in total (103420ms).
[20:53:47.054] <TB1> INFO: 2929768 events read in total (129647ms).
[20:54:13.096] <TB1> INFO: 3515896 events read in total (155689ms).
[20:54:38.730] <TB1> INFO: 4101096 events read in total (181323ms).
[20:55:05.149] <TB1> INFO: 4684592 events read in total (207742ms).
[20:55:25.657] <TB1> INFO: 5158400 events read in total (228250ms).
[20:55:25.814] <TB1> INFO: Test took 229278ms.
[20:55:53.417] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.642801 .. 49.042558
[20:55:53.679] <TB1> INFO: Expecting 208000 events.
[20:56:03.001] <TB1> INFO: 208000 events read in total (9730ms).
[20:56:03.002] <TB1> INFO: Test took 10584ms.
[20:56:04.050] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 59 (-1/-1) hits flags = 528 (plus default)
[20:56:04.064] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:56:04.064] <TB1> INFO: run 1 of 1
[20:56:04.342] <TB1> INFO: Expecting 1431040 events.
[20:56:32.921] <TB1> INFO: 644968 events read in total (27987ms).
[20:57:00.365] <TB1> INFO: 1289320 events read in total (55432ms).
[20:57:06.738] <TB1> INFO: 1431040 events read in total (61804ms).
[20:57:06.774] <TB1> INFO: Test took 62711ms.
[20:57:19.546] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 26.402747 .. 48.987368
[20:57:19.824] <TB1> INFO: Expecting 208000 events.
[20:57:29.646] <TB1> INFO: 208000 events read in total (9230ms).
[20:57:29.647] <TB1> INFO: Test took 10100ms.
[20:57:29.702] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 58 (-1/-1) hits flags = 528 (plus default)
[20:57:29.716] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:57:29.716] <TB1> INFO: run 1 of 1
[20:57:29.994] <TB1> INFO: Expecting 1431040 events.
[20:57:58.217] <TB1> INFO: 653384 events read in total (27631ms).
[20:58:25.605] <TB1> INFO: 1305752 events read in total (55019ms).
[20:58:31.454] <TB1> INFO: 1431040 events read in total (60868ms).
[20:58:31.495] <TB1> INFO: Test took 61779ms.
[20:58:46.291] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 24.495333 .. 47.731218
[20:58:46.529] <TB1> INFO: Expecting 208000 events.
[20:58:56.243] <TB1> INFO: 208000 events read in total (9123ms).
[20:58:56.244] <TB1> INFO: Test took 9951ms.
[20:58:56.294] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 57 (-1/-1) hits flags = 528 (plus default)
[20:58:56.307] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:58:56.307] <TB1> INFO: run 1 of 1
[20:58:56.585] <TB1> INFO: Expecting 1464320 events.
[20:59:24.751] <TB1> INFO: 664080 events read in total (27574ms).
[20:59:52.090] <TB1> INFO: 1328112 events read in total (54913ms).
[20:59:58.198] <TB1> INFO: 1464320 events read in total (61021ms).
[20:59:58.236] <TB1> INFO: Test took 61930ms.
[21:00:12.112] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[21:00:12.112] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[21:00:12.126] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[21:00:12.127] <TB1> INFO: run 1 of 1
[21:00:12.376] <TB1> INFO: Expecting 1364480 events.
[21:00:40.901] <TB1> INFO: 668736 events read in total (27934ms).
[21:01:08.193] <TB1> INFO: 1336760 events read in total (55226ms).
[21:01:09.766] <TB1> INFO: 1364480 events read in total (56799ms).
[21:01:09.796] <TB1> INFO: Test took 57670ms.
[21:01:25.046] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C0.dat
[21:01:25.046] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C1.dat
[21:01:25.046] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C2.dat
[21:01:25.046] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C3.dat
[21:01:25.046] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C4.dat
[21:01:25.046] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C5.dat
[21:01:25.046] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C6.dat
[21:01:25.046] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C7.dat
[21:01:25.046] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C8.dat
[21:01:25.046] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C9.dat
[21:01:25.046] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C10.dat
[21:01:25.047] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C11.dat
[21:01:25.047] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C12.dat
[21:01:25.047] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C13.dat
[21:01:25.047] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C14.dat
[21:01:25.047] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C15.dat
[21:01:25.047] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C0.dat
[21:01:25.053] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C1.dat
[21:01:25.059] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C2.dat
[21:01:25.065] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C3.dat
[21:01:25.071] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C4.dat
[21:01:25.077] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C5.dat
[21:01:25.083] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C6.dat
[21:01:25.089] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C7.dat
[21:01:25.095] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C8.dat
[21:01:25.100] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C9.dat
[21:01:25.105] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C10.dat
[21:01:25.110] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C11.dat
[21:01:25.115] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C12.dat
[21:01:25.120] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C13.dat
[21:01:25.125] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C14.dat
[21:01:25.130] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters35_C15.dat
[21:01:25.135] <TB1> INFO: PixTestTrim::trimTest() done
[21:01:25.135] <TB1> INFO: vtrim: 106 138 138 123 153 137 130 139 119 131 132 150 155 122 151 108
[21:01:25.135] <TB1> INFO: vthrcomp: 119 130 122 123 134 111 129 114 124 128 118 130 135 125 128 117
[21:01:25.135] <TB1> INFO: vcal mean: 35.03 35.05 35.05 35.14 35.08 34.98 34.99 34.96 35.05 35.01 35.15 35.56 35.06 35.87 35.18 35.02
[21:01:25.135] <TB1> INFO: vcal RMS: 0.95 1.01 1.03 1.12 1.15 0.99 1.05 1.12 0.93 1.22 1.23 1.65 1.03 2.01 1.25 1.02
[21:01:25.135] <TB1> INFO: bits mean: 9.09 8.72 9.48 9.53 8.70 8.91 9.34 9.29 9.11 9.76 8.62 8.49 8.20 9.41 8.77 9.15
[21:01:25.135] <TB1> INFO: bits RMS: 2.83 2.81 2.60 2.54 2.57 2.60 2.66 2.94 2.73 2.51 3.20 2.52 2.37 2.80 2.60 2.80
[21:01:25.142] <TB1> INFO: ----------------------------------------------------------------------
[21:01:25.143] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[21:01:25.143] <TB1> INFO: ----------------------------------------------------------------------
[21:01:25.145] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[21:01:25.158] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[21:01:25.158] <TB1> INFO: run 1 of 1
[21:01:25.430] <TB1> INFO: Expecting 4160000 events.
[21:01:58.675] <TB1> INFO: 768855 events read in total (32654ms).
[21:02:31.059] <TB1> INFO: 1530435 events read in total (65038ms).
[21:03:03.403] <TB1> INFO: 2286030 events read in total (97382ms).
[21:03:35.563] <TB1> INFO: 3035930 events read in total (129542ms).
[21:04:07.509] <TB1> INFO: 3781065 events read in total (161488ms).
[21:04:23.821] <TB1> INFO: 4160000 events read in total (177800ms).
[21:04:24.003] <TB1> INFO: Test took 178845ms.
[21:04:53.632] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 209 (-1/-1) hits flags = 528 (plus default)
[21:04:53.646] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[21:04:53.646] <TB1> INFO: run 1 of 1
[21:04:53.882] <TB1> INFO: Expecting 4368000 events.
[21:05:26.033] <TB1> INFO: 730035 events read in total (31559ms).
[21:05:57.559] <TB1> INFO: 1454405 events read in total (63085ms).
[21:06:29.072] <TB1> INFO: 2175580 events read in total (94598ms).
[21:07:00.593] <TB1> INFO: 2891705 events read in total (126119ms).
[21:07:32.023] <TB1> INFO: 3604690 events read in total (157549ms).
[21:08:03.143] <TB1> INFO: 4315495 events read in total (188669ms).
[21:08:05.768] <TB1> INFO: 4368000 events read in total (191294ms).
[21:08:05.948] <TB1> INFO: Test took 192302ms.
[21:08:36.787] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 201 (-1/-1) hits flags = 528 (plus default)
[21:08:36.801] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[21:08:36.801] <TB1> INFO: run 1 of 1
[21:08:37.043] <TB1> INFO: Expecting 4201600 events.
[21:09:08.814] <TB1> INFO: 741035 events read in total (31179ms).
[21:09:40.443] <TB1> INFO: 1476245 events read in total (62808ms).
[21:10:12.103] <TB1> INFO: 2207170 events read in total (94468ms).
[21:10:43.913] <TB1> INFO: 2932745 events read in total (126278ms).
[21:11:15.692] <TB1> INFO: 3655090 events read in total (158057ms).
[21:11:39.719] <TB1> INFO: 4201600 events read in total (182084ms).
[21:11:39.892] <TB1> INFO: Test took 183091ms.
[21:12:04.837] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 200 (-1/-1) hits flags = 528 (plus default)
[21:12:04.851] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[21:12:04.851] <TB1> INFO: run 1 of 1
[21:12:05.122] <TB1> INFO: Expecting 4180800 events.
[21:12:37.720] <TB1> INFO: 742560 events read in total (32006ms).
[21:13:09.663] <TB1> INFO: 1479180 events read in total (63949ms).
[21:13:41.365] <TB1> INFO: 2211165 events read in total (95651ms).
[21:14:12.873] <TB1> INFO: 2938220 events read in total (127159ms).
[21:14:44.599] <TB1> INFO: 3661865 events read in total (158885ms).
[21:15:07.181] <TB1> INFO: 4180800 events read in total (181467ms).
[21:15:07.288] <TB1> INFO: Test took 182437ms.
[21:15:37.646] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 197 (-1/-1) hits flags = 528 (plus default)
[21:15:37.660] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[21:15:37.660] <TB1> INFO: run 1 of 1
[21:15:37.925] <TB1> INFO: Expecting 4118400 events.
[21:16:10.710] <TB1> INFO: 746955 events read in total (32193ms).
[21:16:42.032] <TB1> INFO: 1487555 events read in total (63515ms).
[21:17:13.710] <TB1> INFO: 2223745 events read in total (95193ms).
[21:17:45.325] <TB1> INFO: 2954795 events read in total (126808ms).
[21:18:17.265] <TB1> INFO: 3682285 events read in total (158748ms).
[21:18:36.201] <TB1> INFO: 4118400 events read in total (177684ms).
[21:18:36.384] <TB1> INFO: Test took 178725ms.
[21:19:01.416] <TB1> INFO: PixTestTrim::trimBitTest() done
[21:19:01.418] <TB1> INFO: PixTestTrim::doTest() done, duration: 2510 seconds
[21:19:01.418] <TB1> INFO: Decoding statistics:
[21:19:01.418] <TB1> INFO: General information:
[21:19:01.418] <TB1> INFO: 16bit words read: 0
[21:19:01.418] <TB1> INFO: valid events total: 0
[21:19:01.418] <TB1> INFO: empty events: 0
[21:19:01.418] <TB1> INFO: valid events with pixels: 0
[21:19:01.418] <TB1> INFO: valid pixel hits: 0
[21:19:01.418] <TB1> INFO: Event errors: 0
[21:19:01.418] <TB1> INFO: start marker: 0
[21:19:01.418] <TB1> INFO: stop marker: 0
[21:19:01.418] <TB1> INFO: overflow: 0
[21:19:01.418] <TB1> INFO: invalid 5bit words: 0
[21:19:01.418] <TB1> INFO: invalid XOR eye diagram: 0
[21:19:01.418] <TB1> INFO: frame (failed synchr.): 0
[21:19:01.418] <TB1> INFO: idle data (no TBM trl): 0
[21:19:01.418] <TB1> INFO: no data (only TBM hdr): 0
[21:19:01.418] <TB1> INFO: TBM errors: 0
[21:19:01.418] <TB1> INFO: flawed TBM headers: 0
[21:19:01.418] <TB1> INFO: flawed TBM trailers: 0
[21:19:01.418] <TB1> INFO: event ID mismatches: 0
[21:19:01.418] <TB1> INFO: ROC errors: 0
[21:19:01.418] <TB1> INFO: missing ROC header(s): 0
[21:19:01.418] <TB1> INFO: misplaced readback start: 0
[21:19:01.418] <TB1> INFO: Pixel decoding errors: 0
[21:19:01.419] <TB1> INFO: pixel data incomplete: 0
[21:19:01.419] <TB1> INFO: pixel address: 0
[21:19:01.419] <TB1> INFO: pulse height fill bit: 0
[21:19:01.419] <TB1> INFO: buffer corruption: 0
[21:19:02.063] <TB1> INFO: ######################################################################
[21:19:02.063] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[21:19:02.063] <TB1> INFO: ######################################################################
[21:19:02.329] <TB1> INFO: Expecting 41600 events.
[21:19:05.831] <TB1> INFO: 41600 events read in total (2910ms).
[21:19:05.832] <TB1> INFO: Test took 3768ms.
[21:19:06.364] <TB1> INFO: Expecting 41600 events.
[21:19:09.896] <TB1> INFO: 41600 events read in total (2941ms).
[21:19:09.897] <TB1> INFO: Test took 3860ms.
[21:19:10.207] <TB1> INFO: Expecting 41600 events.
[21:19:13.766] <TB1> INFO: 41600 events read in total (2968ms).
[21:19:13.767] <TB1> INFO: Test took 3843ms.
[21:19:14.065] <TB1> INFO: Expecting 41600 events.
[21:19:17.636] <TB1> INFO: 41600 events read in total (2980ms).
[21:19:17.637] <TB1> INFO: Test took 3843ms.
[21:19:17.938] <TB1> INFO: Expecting 41600 events.
[21:19:21.524] <TB1> INFO: 41600 events read in total (2994ms).
[21:19:21.525] <TB1> INFO: Test took 3863ms.
[21:19:21.815] <TB1> INFO: Expecting 41600 events.
[21:19:25.392] <TB1> INFO: 41600 events read in total (2986ms).
[21:19:25.393] <TB1> INFO: Test took 3843ms.
[21:19:25.687] <TB1> INFO: Expecting 41600 events.
[21:19:29.264] <TB1> INFO: 41600 events read in total (2986ms).
[21:19:29.265] <TB1> INFO: Test took 3843ms.
[21:19:29.555] <TB1> INFO: Expecting 41600 events.
[21:19:33.121] <TB1> INFO: 41600 events read in total (2975ms).
[21:19:33.122] <TB1> INFO: Test took 3832ms.
[21:19:33.411] <TB1> INFO: Expecting 41600 events.
[21:19:36.892] <TB1> INFO: 41600 events read in total (2889ms).
[21:19:36.893] <TB1> INFO: Test took 3747ms.
[21:19:37.182] <TB1> INFO: Expecting 41600 events.
[21:19:40.786] <TB1> INFO: 41600 events read in total (3013ms).
[21:19:40.787] <TB1> INFO: Test took 3870ms.
[21:19:41.075] <TB1> INFO: Expecting 41600 events.
[21:19:44.696] <TB1> INFO: 41600 events read in total (3029ms).
[21:19:44.697] <TB1> INFO: Test took 3886ms.
[21:19:44.989] <TB1> INFO: Expecting 41600 events.
[21:19:48.623] <TB1> INFO: 41600 events read in total (3043ms).
[21:19:48.624] <TB1> INFO: Test took 3900ms.
[21:19:48.916] <TB1> INFO: Expecting 41600 events.
[21:19:52.482] <TB1> INFO: 41600 events read in total (2975ms).
[21:19:52.483] <TB1> INFO: Test took 3832ms.
[21:19:52.772] <TB1> INFO: Expecting 41600 events.
[21:19:56.378] <TB1> INFO: 41600 events read in total (3014ms).
[21:19:56.379] <TB1> INFO: Test took 3872ms.
[21:19:56.668] <TB1> INFO: Expecting 41600 events.
[21:20:00.248] <TB1> INFO: 41600 events read in total (2988ms).
[21:20:00.249] <TB1> INFO: Test took 3847ms.
[21:20:00.539] <TB1> INFO: Expecting 41600 events.
[21:20:04.103] <TB1> INFO: 41600 events read in total (2972ms).
[21:20:04.104] <TB1> INFO: Test took 3830ms.
[21:20:04.393] <TB1> INFO: Expecting 41600 events.
[21:20:07.901] <TB1> INFO: 41600 events read in total (2917ms).
[21:20:07.902] <TB1> INFO: Test took 3774ms.
[21:20:08.193] <TB1> INFO: Expecting 41600 events.
[21:20:11.735] <TB1> INFO: 41600 events read in total (2950ms).
[21:20:11.736] <TB1> INFO: Test took 3808ms.
[21:20:12.028] <TB1> INFO: Expecting 41600 events.
[21:20:15.630] <TB1> INFO: 41600 events read in total (3010ms).
[21:20:15.631] <TB1> INFO: Test took 3868ms.
[21:20:15.921] <TB1> INFO: Expecting 41600 events.
[21:20:19.429] <TB1> INFO: 41600 events read in total (2917ms).
[21:20:19.429] <TB1> INFO: Test took 3773ms.
[21:20:19.735] <TB1> INFO: Expecting 41600 events.
[21:20:23.281] <TB1> INFO: 41600 events read in total (2955ms).
[21:20:23.282] <TB1> INFO: Test took 3828ms.
[21:20:23.584] <TB1> INFO: Expecting 41600 events.
[21:20:27.195] <TB1> INFO: 41600 events read in total (3020ms).
[21:20:27.196] <TB1> INFO: Test took 3890ms.
[21:20:27.503] <TB1> INFO: Expecting 41600 events.
[21:20:30.981] <TB1> INFO: 41600 events read in total (2886ms).
[21:20:30.982] <TB1> INFO: Test took 3759ms.
[21:20:31.272] <TB1> INFO: Expecting 41600 events.
[21:20:34.815] <TB1> INFO: 41600 events read in total (2952ms).
[21:20:34.816] <TB1> INFO: Test took 3809ms.
[21:20:35.105] <TB1> INFO: Expecting 41600 events.
[21:20:38.573] <TB1> INFO: 41600 events read in total (2876ms).
[21:20:38.574] <TB1> INFO: Test took 3734ms.
[21:20:38.864] <TB1> INFO: Expecting 41600 events.
[21:20:42.367] <TB1> INFO: 41600 events read in total (2911ms).
[21:20:42.368] <TB1> INFO: Test took 3769ms.
[21:20:42.657] <TB1> INFO: Expecting 41600 events.
[21:20:46.285] <TB1> INFO: 41600 events read in total (3036ms).
[21:20:46.286] <TB1> INFO: Test took 3894ms.
[21:20:46.600] <TB1> INFO: Expecting 41600 events.
[21:20:50.068] <TB1> INFO: 41600 events read in total (2876ms).
[21:20:50.069] <TB1> INFO: Test took 3758ms.
[21:20:50.358] <TB1> INFO: Expecting 41600 events.
[21:20:53.824] <TB1> INFO: 41600 events read in total (2875ms).
[21:20:53.825] <TB1> INFO: Test took 3732ms.
[21:20:54.117] <TB1> INFO: Expecting 41600 events.
[21:20:57.648] <TB1> INFO: 41600 events read in total (2939ms).
[21:20:57.649] <TB1> INFO: Test took 3796ms.
[21:20:57.941] <TB1> INFO: Expecting 41600 events.
[21:21:01.480] <TB1> INFO: 41600 events read in total (2948ms).
[21:21:01.481] <TB1> INFO: Test took 3806ms.
[21:21:01.771] <TB1> INFO: Expecting 2560 events.
[21:21:02.659] <TB1> INFO: 2560 events read in total (296ms).
[21:21:02.659] <TB1> INFO: Test took 1165ms.
[21:21:02.966] <TB1> INFO: Expecting 2560 events.
[21:21:03.861] <TB1> INFO: 2560 events read in total (304ms).
[21:21:03.861] <TB1> INFO: Test took 1201ms.
[21:21:04.170] <TB1> INFO: Expecting 2560 events.
[21:21:05.063] <TB1> INFO: 2560 events read in total (301ms).
[21:21:05.063] <TB1> INFO: Test took 1201ms.
[21:21:05.371] <TB1> INFO: Expecting 2560 events.
[21:21:06.265] <TB1> INFO: 2560 events read in total (302ms).
[21:21:06.265] <TB1> INFO: Test took 1202ms.
[21:21:06.574] <TB1> INFO: Expecting 2560 events.
[21:21:07.455] <TB1> INFO: 2560 events read in total (289ms).
[21:21:07.455] <TB1> INFO: Test took 1189ms.
[21:21:07.761] <TB1> INFO: Expecting 2560 events.
[21:21:08.654] <TB1> INFO: 2560 events read in total (301ms).
[21:21:08.655] <TB1> INFO: Test took 1200ms.
[21:21:08.962] <TB1> INFO: Expecting 2560 events.
[21:21:09.846] <TB1> INFO: 2560 events read in total (293ms).
[21:21:09.846] <TB1> INFO: Test took 1190ms.
[21:21:10.153] <TB1> INFO: Expecting 2560 events.
[21:21:11.042] <TB1> INFO: 2560 events read in total (297ms).
[21:21:11.042] <TB1> INFO: Test took 1195ms.
[21:21:11.351] <TB1> INFO: Expecting 2560 events.
[21:21:12.243] <TB1> INFO: 2560 events read in total (301ms).
[21:21:12.243] <TB1> INFO: Test took 1200ms.
[21:21:12.551] <TB1> INFO: Expecting 2560 events.
[21:21:13.430] <TB1> INFO: 2560 events read in total (287ms).
[21:21:13.430] <TB1> INFO: Test took 1185ms.
[21:21:13.738] <TB1> INFO: Expecting 2560 events.
[21:21:14.631] <TB1> INFO: 2560 events read in total (301ms).
[21:21:14.631] <TB1> INFO: Test took 1201ms.
[21:21:14.939] <TB1> INFO: Expecting 2560 events.
[21:21:15.822] <TB1> INFO: 2560 events read in total (291ms).
[21:21:15.822] <TB1> INFO: Test took 1191ms.
[21:21:16.130] <TB1> INFO: Expecting 2560 events.
[21:21:17.022] <TB1> INFO: 2560 events read in total (300ms).
[21:21:17.022] <TB1> INFO: Test took 1199ms.
[21:21:17.328] <TB1> INFO: Expecting 2560 events.
[21:21:18.214] <TB1> INFO: 2560 events read in total (294ms).
[21:21:18.214] <TB1> INFO: Test took 1191ms.
[21:21:18.521] <TB1> INFO: Expecting 2560 events.
[21:21:19.412] <TB1> INFO: 2560 events read in total (300ms).
[21:21:19.412] <TB1> INFO: Test took 1197ms.
[21:21:19.720] <TB1> INFO: Expecting 2560 events.
[21:21:20.605] <TB1> INFO: 2560 events read in total (293ms).
[21:21:20.605] <TB1> INFO: Test took 1193ms.
[21:21:20.610] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:21:20.913] <TB1> INFO: Expecting 655360 events.
[21:21:36.055] <TB1> INFO: 655360 events read in total (14551ms).
[21:21:36.071] <TB1> INFO: Expecting 655360 events.
[21:21:50.716] <TB1> INFO: 655360 events read in total (14242ms).
[21:21:50.736] <TB1> INFO: Expecting 655360 events.
[21:22:05.285] <TB1> INFO: 655360 events read in total (14145ms).
[21:22:05.315] <TB1> INFO: Expecting 655360 events.
[21:22:19.785] <TB1> INFO: 655360 events read in total (14067ms).
[21:22:19.814] <TB1> INFO: Expecting 655360 events.
[21:22:34.473] <TB1> INFO: 655360 events read in total (14256ms).
[21:22:34.507] <TB1> INFO: Expecting 655360 events.
[21:22:49.180] <TB1> INFO: 655360 events read in total (14270ms).
[21:22:49.217] <TB1> INFO: Expecting 655360 events.
[21:23:03.984] <TB1> INFO: 655360 events read in total (14364ms).
[21:23:04.113] <TB1> INFO: Expecting 655360 events.
[21:23:18.877] <TB1> INFO: 655360 events read in total (14360ms).
[21:23:18.925] <TB1> INFO: Expecting 655360 events.
[21:23:33.488] <TB1> INFO: 655360 events read in total (14160ms).
[21:23:33.557] <TB1> INFO: Expecting 655360 events.
[21:23:48.026] <TB1> INFO: 655360 events read in total (14066ms).
[21:23:48.165] <TB1> INFO: Expecting 655360 events.
[21:24:02.572] <TB1> INFO: 655360 events read in total (14003ms).
[21:24:02.648] <TB1> INFO: Expecting 655360 events.
[21:24:17.178] <TB1> INFO: 655360 events read in total (14127ms).
[21:24:17.258] <TB1> INFO: Expecting 655360 events.
[21:24:31.800] <TB1> INFO: 655360 events read in total (14139ms).
[21:24:31.889] <TB1> INFO: Expecting 655360 events.
[21:24:46.590] <TB1> INFO: 655360 events read in total (14297ms).
[21:24:46.681] <TB1> INFO: Expecting 655360 events.
[21:25:01.197] <TB1> INFO: 655360 events read in total (14112ms).
[21:25:01.294] <TB1> INFO: Expecting 655360 events.
[21:25:15.850] <TB1> INFO: 655360 events read in total (14152ms).
[21:25:16.010] <TB1> INFO: Test took 235400ms.
[21:25:16.109] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:25:16.363] <TB1> INFO: Expecting 655360 events.
[21:25:31.105] <TB1> INFO: 655360 events read in total (14150ms).
[21:25:31.121] <TB1> INFO: Expecting 655360 events.
[21:25:45.573] <TB1> INFO: 655360 events read in total (14049ms).
[21:25:45.592] <TB1> INFO: Expecting 655360 events.
[21:25:59.911] <TB1> INFO: 655360 events read in total (13915ms).
[21:25:59.935] <TB1> INFO: Expecting 655360 events.
[21:26:14.085] <TB1> INFO: 655360 events read in total (13747ms).
[21:26:14.120] <TB1> INFO: Expecting 655360 events.
[21:26:28.816] <TB1> INFO: 655360 events read in total (14293ms).
[21:26:28.857] <TB1> INFO: Expecting 655360 events.
[21:26:43.214] <TB1> INFO: 655360 events read in total (13954ms).
[21:26:43.250] <TB1> INFO: Expecting 655360 events.
[21:26:57.681] <TB1> INFO: 655360 events read in total (14028ms).
[21:26:57.723] <TB1> INFO: Expecting 655360 events.
[21:27:12.145] <TB1> INFO: 655360 events read in total (14019ms).
[21:27:12.189] <TB1> INFO: Expecting 655360 events.
[21:27:26.649] <TB1> INFO: 655360 events read in total (14056ms).
[21:27:26.708] <TB1> INFO: Expecting 655360 events.
[21:27:41.214] <TB1> INFO: 655360 events read in total (14103ms).
[21:27:41.292] <TB1> INFO: Expecting 655360 events.
[21:27:55.687] <TB1> INFO: 655360 events read in total (13992ms).
[21:27:55.760] <TB1> INFO: Expecting 655360 events.
[21:28:09.934] <TB1> INFO: 655360 events read in total (13771ms).
[21:28:10.076] <TB1> INFO: Expecting 655360 events.
[21:28:24.606] <TB1> INFO: 655360 events read in total (14127ms).
[21:28:24.689] <TB1> INFO: Expecting 655360 events.
[21:28:39.147] <TB1> INFO: 655360 events read in total (14055ms).
[21:28:39.313] <TB1> INFO: Expecting 655360 events.
[21:28:53.451] <TB1> INFO: 655360 events read in total (13735ms).
[21:28:53.548] <TB1> INFO: Expecting 655360 events.
[21:29:08.101] <TB1> INFO: 655360 events read in total (14150ms).
[21:29:08.266] <TB1> INFO: Test took 232157ms.
[21:29:08.440] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.446] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[21:29:08.452] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.457] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[21:29:08.463] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[21:29:08.470] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[21:29:08.476] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[21:29:08.481] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[21:29:08.487] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[21:29:08.494] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.500] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[21:29:08.506] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.512] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.518] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.524] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[21:29:08.530] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[21:29:08.536] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[21:29:08.542] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[21:29:08.548] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[21:29:08.554] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.560] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.566] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.572] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.578] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.584] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.590] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[21:29:08.596] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[21:29:08.603] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[21:29:08.611] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[21:29:08.619] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[21:29:08.627] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[21:29:08.635] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[21:29:08.643] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.651] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.659] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.667] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[21:29:08.675] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[21:29:08.682] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[21:29:08.691] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[21:29:08.698] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[21:29:08.707] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[21:29:08.714] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[21:29:08.723] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[21:29:08.731] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[21:29:08.766] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C0.dat
[21:29:08.767] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C1.dat
[21:29:08.767] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C2.dat
[21:29:08.767] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C3.dat
[21:29:08.767] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C4.dat
[21:29:08.767] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C5.dat
[21:29:08.768] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C6.dat
[21:29:08.768] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C7.dat
[21:29:08.768] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C8.dat
[21:29:08.768] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C9.dat
[21:29:08.768] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C10.dat
[21:29:08.769] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C11.dat
[21:29:08.769] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C12.dat
[21:29:08.769] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C13.dat
[21:29:08.769] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C14.dat
[21:29:08.769] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters35_C15.dat
[21:29:09.013] <TB1> INFO: Expecting 41600 events.
[21:29:12.144] <TB1> INFO: 41600 events read in total (2539ms).
[21:29:12.145] <TB1> INFO: Test took 3372ms.
[21:29:12.593] <TB1> INFO: Expecting 41600 events.
[21:29:15.623] <TB1> INFO: 41600 events read in total (2438ms).
[21:29:15.624] <TB1> INFO: Test took 3267ms.
[21:29:16.091] <TB1> INFO: Expecting 41600 events.
[21:29:19.202] <TB1> INFO: 41600 events read in total (2520ms).
[21:29:19.203] <TB1> INFO: Test took 3365ms.
[21:29:19.428] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:19.521] <TB1> INFO: Expecting 2560 events.
[21:29:20.413] <TB1> INFO: 2560 events read in total (301ms).
[21:29:20.413] <TB1> INFO: Test took 985ms.
[21:29:20.418] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:20.723] <TB1> INFO: Expecting 2560 events.
[21:29:21.617] <TB1> INFO: 2560 events read in total (303ms).
[21:29:21.618] <TB1> INFO: Test took 1201ms.
[21:29:21.621] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:21.925] <TB1> INFO: Expecting 2560 events.
[21:29:22.819] <TB1> INFO: 2560 events read in total (302ms).
[21:29:22.820] <TB1> INFO: Test took 1199ms.
[21:29:22.823] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:23.128] <TB1> INFO: Expecting 2560 events.
[21:29:24.017] <TB1> INFO: 2560 events read in total (297ms).
[21:29:24.018] <TB1> INFO: Test took 1195ms.
[21:29:24.020] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:24.326] <TB1> INFO: Expecting 2560 events.
[21:29:25.212] <TB1> INFO: 2560 events read in total (294ms).
[21:29:25.213] <TB1> INFO: Test took 1193ms.
[21:29:25.216] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:25.519] <TB1> INFO: Expecting 2560 events.
[21:29:26.410] <TB1> INFO: 2560 events read in total (299ms).
[21:29:26.410] <TB1> INFO: Test took 1194ms.
[21:29:26.412] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:26.719] <TB1> INFO: Expecting 2560 events.
[21:29:27.609] <TB1> INFO: 2560 events read in total (299ms).
[21:29:27.610] <TB1> INFO: Test took 1198ms.
[21:29:27.613] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:27.919] <TB1> INFO: Expecting 2560 events.
[21:29:28.805] <TB1> INFO: 2560 events read in total (295ms).
[21:29:28.806] <TB1> INFO: Test took 1193ms.
[21:29:28.809] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:29.113] <TB1> INFO: Expecting 2560 events.
[21:29:29.999] <TB1> INFO: 2560 events read in total (294ms).
[21:29:29.000] <TB1> INFO: Test took 1192ms.
[21:29:30.003] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:30.307] <TB1> INFO: Expecting 2560 events.
[21:29:31.190] <TB1> INFO: 2560 events read in total (291ms).
[21:29:31.190] <TB1> INFO: Test took 1187ms.
[21:29:31.192] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:31.499] <TB1> INFO: Expecting 2560 events.
[21:29:32.383] <TB1> INFO: 2560 events read in total (293ms).
[21:29:32.384] <TB1> INFO: Test took 1192ms.
[21:29:32.386] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:32.689] <TB1> INFO: Expecting 2560 events.
[21:29:33.572] <TB1> INFO: 2560 events read in total (291ms).
[21:29:33.572] <TB1> INFO: Test took 1186ms.
[21:29:33.575] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:33.881] <TB1> INFO: Expecting 2560 events.
[21:29:34.762] <TB1> INFO: 2560 events read in total (289ms).
[21:29:34.762] <TB1> INFO: Test took 1187ms.
[21:29:34.765] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:35.070] <TB1> INFO: Expecting 2560 events.
[21:29:35.958] <TB1> INFO: 2560 events read in total (296ms).
[21:29:35.958] <TB1> INFO: Test took 1193ms.
[21:29:35.961] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:36.266] <TB1> INFO: Expecting 2560 events.
[21:29:37.153] <TB1> INFO: 2560 events read in total (295ms).
[21:29:37.154] <TB1> INFO: Test took 1193ms.
[21:29:37.156] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:37.462] <TB1> INFO: Expecting 2560 events.
[21:29:38.352] <TB1> INFO: 2560 events read in total (298ms).
[21:29:38.352] <TB1> INFO: Test took 1196ms.
[21:29:38.357] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:38.660] <TB1> INFO: Expecting 2560 events.
[21:29:39.546] <TB1> INFO: 2560 events read in total (294ms).
[21:29:39.547] <TB1> INFO: Test took 1190ms.
[21:29:39.549] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:39.856] <TB1> INFO: Expecting 2560 events.
[21:29:40.736] <TB1> INFO: 2560 events read in total (288ms).
[21:29:40.737] <TB1> INFO: Test took 1188ms.
[21:29:40.741] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:41.044] <TB1> INFO: Expecting 2560 events.
[21:29:41.925] <TB1> INFO: 2560 events read in total (289ms).
[21:29:41.925] <TB1> INFO: Test took 1184ms.
[21:29:41.928] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:42.233] <TB1> INFO: Expecting 2560 events.
[21:29:43.119] <TB1> INFO: 2560 events read in total (294ms).
[21:29:43.120] <TB1> INFO: Test took 1192ms.
[21:29:43.124] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:43.427] <TB1> INFO: Expecting 2560 events.
[21:29:44.306] <TB1> INFO: 2560 events read in total (288ms).
[21:29:44.307] <TB1> INFO: Test took 1183ms.
[21:29:44.310] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:44.615] <TB1> INFO: Expecting 2560 events.
[21:29:45.495] <TB1> INFO: 2560 events read in total (288ms).
[21:29:45.496] <TB1> INFO: Test took 1186ms.
[21:29:45.499] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:45.804] <TB1> INFO: Expecting 2560 events.
[21:29:46.684] <TB1> INFO: 2560 events read in total (288ms).
[21:29:46.684] <TB1> INFO: Test took 1185ms.
[21:29:46.687] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:46.993] <TB1> INFO: Expecting 2560 events.
[21:29:47.881] <TB1> INFO: 2560 events read in total (296ms).
[21:29:47.882] <TB1> INFO: Test took 1195ms.
[21:29:47.885] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:48.189] <TB1> INFO: Expecting 2560 events.
[21:29:49.075] <TB1> INFO: 2560 events read in total (294ms).
[21:29:49.075] <TB1> INFO: Test took 1190ms.
[21:29:49.078] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:49.382] <TB1> INFO: Expecting 2560 events.
[21:29:50.273] <TB1> INFO: 2560 events read in total (299ms).
[21:29:50.274] <TB1> INFO: Test took 1196ms.
[21:29:50.276] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:50.582] <TB1> INFO: Expecting 2560 events.
[21:29:51.474] <TB1> INFO: 2560 events read in total (300ms).
[21:29:51.475] <TB1> INFO: Test took 1199ms.
[21:29:51.478] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:51.783] <TB1> INFO: Expecting 2560 events.
[21:29:52.677] <TB1> INFO: 2560 events read in total (302ms).
[21:29:52.677] <TB1> INFO: Test took 1200ms.
[21:29:52.680] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:52.985] <TB1> INFO: Expecting 2560 events.
[21:29:53.883] <TB1> INFO: 2560 events read in total (306ms).
[21:29:53.883] <TB1> INFO: Test took 1203ms.
[21:29:53.886] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:54.191] <TB1> INFO: Expecting 2560 events.
[21:29:55.083] <TB1> INFO: 2560 events read in total (300ms).
[21:29:55.083] <TB1> INFO: Test took 1197ms.
[21:29:55.086] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:55.392] <TB1> INFO: Expecting 2560 events.
[21:29:56.282] <TB1> INFO: 2560 events read in total (299ms).
[21:29:56.282] <TB1> INFO: Test took 1196ms.
[21:29:56.284] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:29:56.591] <TB1> INFO: Expecting 2560 events.
[21:29:57.480] <TB1> INFO: 2560 events read in total (297ms).
[21:29:57.480] <TB1> INFO: Test took 1196ms.
[21:29:57.948] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 655 seconds
[21:29:57.948] <TB1> INFO: PH scale (per ROC): 49 48 38 48 45 36 46 48 51 45 31 35 43 39 37 50
[21:29:57.948] <TB1> INFO: PH offset (per ROC): 122 111 97 125 95 95 99 109 131 102 94 109 98 85 80 127
[21:29:57.958] <TB1> INFO: Decoding statistics:
[21:29:57.958] <TB1> INFO: General information:
[21:29:57.958] <TB1> INFO: 16bit words read: 127886
[21:29:57.958] <TB1> INFO: valid events total: 20480
[21:29:57.958] <TB1> INFO: empty events: 17977
[21:29:57.958] <TB1> INFO: valid events with pixels: 2503
[21:29:57.958] <TB1> INFO: valid pixel hits: 2503
[21:29:57.958] <TB1> INFO: Event errors: 0
[21:29:57.958] <TB1> INFO: start marker: 0
[21:29:57.958] <TB1> INFO: stop marker: 0
[21:29:57.959] <TB1> INFO: overflow: 0
[21:29:57.959] <TB1> INFO: invalid 5bit words: 0
[21:29:57.959] <TB1> INFO: invalid XOR eye diagram: 0
[21:29:57.959] <TB1> INFO: frame (failed synchr.): 0
[21:29:57.959] <TB1> INFO: idle data (no TBM trl): 0
[21:29:57.959] <TB1> INFO: no data (only TBM hdr): 0
[21:29:57.959] <TB1> INFO: TBM errors: 0
[21:29:57.959] <TB1> INFO: flawed TBM headers: 0
[21:29:57.959] <TB1> INFO: flawed TBM trailers: 0
[21:29:57.959] <TB1> INFO: event ID mismatches: 0
[21:29:57.959] <TB1> INFO: ROC errors: 0
[21:29:57.959] <TB1> INFO: missing ROC header(s): 0
[21:29:57.959] <TB1> INFO: misplaced readback start: 0
[21:29:57.959] <TB1> INFO: Pixel decoding errors: 0
[21:29:57.959] <TB1> INFO: pixel data incomplete: 0
[21:29:57.959] <TB1> INFO: pixel address: 0
[21:29:57.959] <TB1> INFO: pulse height fill bit: 0
[21:29:57.959] <TB1> INFO: buffer corruption: 0
[21:29:58.175] <TB1> INFO: ######################################################################
[21:29:58.175] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[21:29:58.175] <TB1> INFO: ######################################################################
[21:29:58.190] <TB1> INFO: scanning low vcal = 10
[21:29:58.429] <TB1> INFO: Expecting 41600 events.
[21:30:02.004] <TB1> INFO: 41600 events read in total (2983ms).
[21:30:02.005] <TB1> INFO: Test took 3815ms.
[21:30:02.006] <TB1> INFO: scanning low vcal = 20
[21:30:02.300] <TB1> INFO: Expecting 41600 events.
[21:30:05.905] <TB1> INFO: 41600 events read in total (3013ms).
[21:30:05.905] <TB1> INFO: Test took 3898ms.
[21:30:05.907] <TB1> INFO: scanning low vcal = 30
[21:30:06.202] <TB1> INFO: Expecting 41600 events.
[21:30:09.863] <TB1> INFO: 41600 events read in total (3069ms).
[21:30:09.865] <TB1> INFO: Test took 3958ms.
[21:30:09.868] <TB1> INFO: scanning low vcal = 40
[21:30:10.145] <TB1> INFO: Expecting 41600 events.
[21:30:14.113] <TB1> INFO: 41600 events read in total (3376ms).
[21:30:14.114] <TB1> INFO: Test took 4246ms.
[21:30:14.118] <TB1> INFO: scanning low vcal = 50
[21:30:14.417] <TB1> INFO: Expecting 41600 events.
[21:30:18.398] <TB1> INFO: 41600 events read in total (3390ms).
[21:30:18.400] <TB1> INFO: Test took 4282ms.
[21:30:18.403] <TB1> INFO: scanning low vcal = 60
[21:30:18.680] <TB1> INFO: Expecting 41600 events.
[21:30:22.695] <TB1> INFO: 41600 events read in total (3423ms).
[21:30:22.695] <TB1> INFO: Test took 4291ms.
[21:30:22.698] <TB1> INFO: scanning low vcal = 70
[21:30:22.976] <TB1> INFO: Expecting 41600 events.
[21:30:26.979] <TB1> INFO: 41600 events read in total (3411ms).
[21:30:26.980] <TB1> INFO: Test took 4282ms.
[21:30:26.983] <TB1> INFO: scanning low vcal = 80
[21:30:27.260] <TB1> INFO: Expecting 41600 events.
[21:30:31.259] <TB1> INFO: 41600 events read in total (3407ms).
[21:30:31.260] <TB1> INFO: Test took 4277ms.
[21:30:31.264] <TB1> INFO: scanning low vcal = 90
[21:30:31.541] <TB1> INFO: Expecting 41600 events.
[21:30:35.543] <TB1> INFO: 41600 events read in total (3410ms).
[21:30:35.544] <TB1> INFO: Test took 4280ms.
[21:30:35.548] <TB1> INFO: scanning low vcal = 100
[21:30:35.825] <TB1> INFO: Expecting 41600 events.
[21:30:39.830] <TB1> INFO: 41600 events read in total (3414ms).
[21:30:39.831] <TB1> INFO: Test took 4283ms.
[21:30:39.834] <TB1> INFO: scanning low vcal = 110
[21:30:40.111] <TB1> INFO: Expecting 41600 events.
[21:30:44.093] <TB1> INFO: 41600 events read in total (3390ms).
[21:30:44.094] <TB1> INFO: Test took 4260ms.
[21:30:44.099] <TB1> INFO: scanning low vcal = 120
[21:30:44.374] <TB1> INFO: Expecting 41600 events.
[21:30:48.379] <TB1> INFO: 41600 events read in total (3413ms).
[21:30:48.380] <TB1> INFO: Test took 4281ms.
[21:30:48.383] <TB1> INFO: scanning low vcal = 130
[21:30:48.667] <TB1> INFO: Expecting 41600 events.
[21:30:52.671] <TB1> INFO: 41600 events read in total (3412ms).
[21:30:52.672] <TB1> INFO: Test took 4289ms.
[21:30:52.675] <TB1> INFO: scanning low vcal = 140
[21:30:52.952] <TB1> INFO: Expecting 41600 events.
[21:30:56.971] <TB1> INFO: 41600 events read in total (3427ms).
[21:30:56.972] <TB1> INFO: Test took 4297ms.
[21:30:56.975] <TB1> INFO: scanning low vcal = 150
[21:30:57.252] <TB1> INFO: Expecting 41600 events.
[21:31:01.253] <TB1> INFO: 41600 events read in total (3409ms).
[21:31:01.254] <TB1> INFO: Test took 4279ms.
[21:31:01.257] <TB1> INFO: scanning low vcal = 160
[21:31:01.534] <TB1> INFO: Expecting 41600 events.
[21:31:05.537] <TB1> INFO: 41600 events read in total (3411ms).
[21:31:05.538] <TB1> INFO: Test took 4281ms.
[21:31:05.541] <TB1> INFO: scanning low vcal = 170
[21:31:05.819] <TB1> INFO: Expecting 41600 events.
[21:31:09.786] <TB1> INFO: 41600 events read in total (3376ms).
[21:31:09.787] <TB1> INFO: Test took 4245ms.
[21:31:09.792] <TB1> INFO: scanning low vcal = 180
[21:31:10.067] <TB1> INFO: Expecting 41600 events.
[21:31:14.113] <TB1> INFO: 41600 events read in total (3454ms).
[21:31:14.114] <TB1> INFO: Test took 4322ms.
[21:31:14.117] <TB1> INFO: scanning low vcal = 190
[21:31:14.394] <TB1> INFO: Expecting 41600 events.
[21:31:18.385] <TB1> INFO: 41600 events read in total (3399ms).
[21:31:18.386] <TB1> INFO: Test took 4269ms.
[21:31:18.389] <TB1> INFO: scanning low vcal = 200
[21:31:18.666] <TB1> INFO: Expecting 41600 events.
[21:31:22.701] <TB1> INFO: 41600 events read in total (3443ms).
[21:31:22.702] <TB1> INFO: Test took 4313ms.
[21:31:22.705] <TB1> INFO: scanning low vcal = 210
[21:31:22.983] <TB1> INFO: Expecting 41600 events.
[21:31:26.956] <TB1> INFO: 41600 events read in total (3382ms).
[21:31:26.956] <TB1> INFO: Test took 4251ms.
[21:31:26.960] <TB1> INFO: scanning low vcal = 220
[21:31:27.236] <TB1> INFO: Expecting 41600 events.
[21:31:31.196] <TB1> INFO: 41600 events read in total (3368ms).
[21:31:31.197] <TB1> INFO: Test took 4237ms.
[21:31:31.200] <TB1> INFO: scanning low vcal = 230
[21:31:31.477] <TB1> INFO: Expecting 41600 events.
[21:31:35.477] <TB1> INFO: 41600 events read in total (3408ms).
[21:31:35.478] <TB1> INFO: Test took 4278ms.
[21:31:35.481] <TB1> INFO: scanning low vcal = 240
[21:31:35.758] <TB1> INFO: Expecting 41600 events.
[21:31:39.736] <TB1> INFO: 41600 events read in total (3386ms).
[21:31:39.737] <TB1> INFO: Test took 4256ms.
[21:31:39.740] <TB1> INFO: scanning low vcal = 250
[21:31:40.017] <TB1> INFO: Expecting 41600 events.
[21:31:44.004] <TB1> INFO: 41600 events read in total (3395ms).
[21:31:44.004] <TB1> INFO: Test took 4264ms.
[21:31:44.009] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[21:31:44.285] <TB1> INFO: Expecting 41600 events.
[21:31:48.306] <TB1> INFO: 41600 events read in total (3429ms).
[21:31:48.306] <TB1> INFO: Test took 4297ms.
[21:31:48.309] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[21:31:48.587] <TB1> INFO: Expecting 41600 events.
[21:31:52.600] <TB1> INFO: 41600 events read in total (3422ms).
[21:31:52.601] <TB1> INFO: Test took 4292ms.
[21:31:52.604] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[21:31:52.882] <TB1> INFO: Expecting 41600 events.
[21:31:56.871] <TB1> INFO: 41600 events read in total (3398ms).
[21:31:56.872] <TB1> INFO: Test took 4268ms.
[21:31:56.875] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[21:31:57.152] <TB1> INFO: Expecting 41600 events.
[21:32:01.102] <TB1> INFO: 41600 events read in total (3358ms).
[21:32:01.103] <TB1> INFO: Test took 4228ms.
[21:32:01.106] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[21:32:01.384] <TB1> INFO: Expecting 41600 events.
[21:32:05.398] <TB1> INFO: 41600 events read in total (3423ms).
[21:32:05.399] <TB1> INFO: Test took 4291ms.
[21:32:05.845] <TB1> INFO: PixTestGainPedestal::measure() done
[21:32:42.690] <TB1> INFO: PixTestGainPedestal::fit() done
[21:32:42.690] <TB1> INFO: non-linearity mean: 0.977 0.940 0.912 0.979 0.931 0.919 0.946 0.946 0.980 0.959 0.904 0.931 0.941 0.936 0.956 0.978
[21:32:42.690] <TB1> INFO: non-linearity RMS: 0.005 0.059 0.100 0.005 0.088 0.144 0.069 0.049 0.004 0.019 0.145 0.171 0.054 0.104 0.176 0.005
[21:32:42.690] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[21:32:42.703] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[21:32:42.716] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[21:32:42.729] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[21:32:42.742] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[21:32:42.755] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[21:32:42.769] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[21:32:42.781] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[21:32:42.794] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[21:32:42.807] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[21:32:42.820] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[21:32:42.833] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[21:32:42.847] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[21:32:42.860] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[21:32:42.874] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[21:32:42.887] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[21:32:42.901] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 164 seconds
[21:32:42.901] <TB1> INFO: Decoding statistics:
[21:32:42.901] <TB1> INFO: General information:
[21:32:42.901] <TB1> INFO: 16bit words read: 3286062
[21:32:42.901] <TB1> INFO: valid events total: 332800
[21:32:42.901] <TB1> INFO: empty events: 1983
[21:32:42.901] <TB1> INFO: valid events with pixels: 330817
[21:32:42.901] <TB1> INFO: valid pixel hits: 644631
[21:32:42.901] <TB1> INFO: Event errors: 0
[21:32:42.901] <TB1> INFO: start marker: 0
[21:32:42.901] <TB1> INFO: stop marker: 0
[21:32:42.901] <TB1> INFO: overflow: 0
[21:32:42.901] <TB1> INFO: invalid 5bit words: 0
[21:32:42.901] <TB1> INFO: invalid XOR eye diagram: 0
[21:32:42.901] <TB1> INFO: frame (failed synchr.): 0
[21:32:42.901] <TB1> INFO: idle data (no TBM trl): 0
[21:32:42.901] <TB1> INFO: no data (only TBM hdr): 0
[21:32:42.901] <TB1> INFO: TBM errors: 0
[21:32:42.901] <TB1> INFO: flawed TBM headers: 0
[21:32:42.901] <TB1> INFO: flawed TBM trailers: 0
[21:32:42.901] <TB1> INFO: event ID mismatches: 0
[21:32:42.901] <TB1> INFO: ROC errors: 0
[21:32:42.901] <TB1> INFO: missing ROC header(s): 0
[21:32:42.901] <TB1> INFO: misplaced readback start: 0
[21:32:42.901] <TB1> INFO: Pixel decoding errors: 0
[21:32:42.901] <TB1> INFO: pixel data incomplete: 0
[21:32:42.901] <TB1> INFO: pixel address: 0
[21:32:42.901] <TB1> INFO: pulse height fill bit: 0
[21:32:42.901] <TB1> INFO: buffer corruption: 0
[21:32:42.918] <TB1> INFO: Decoding statistics:
[21:32:42.918] <TB1> INFO: General information:
[21:32:42.918] <TB1> INFO: 16bit words read: 3415484
[21:32:42.918] <TB1> INFO: valid events total: 353536
[21:32:42.918] <TB1> INFO: empty events: 20216
[21:32:42.918] <TB1> INFO: valid events with pixels: 333320
[21:32:42.918] <TB1> INFO: valid pixel hits: 647134
[21:32:42.918] <TB1> INFO: Event errors: 0
[21:32:42.918] <TB1> INFO: start marker: 0
[21:32:42.918] <TB1> INFO: stop marker: 0
[21:32:42.918] <TB1> INFO: overflow: 0
[21:32:42.918] <TB1> INFO: invalid 5bit words: 0
[21:32:42.918] <TB1> INFO: invalid XOR eye diagram: 0
[21:32:42.918] <TB1> INFO: frame (failed synchr.): 0
[21:32:42.918] <TB1> INFO: idle data (no TBM trl): 0
[21:32:42.918] <TB1> INFO: no data (only TBM hdr): 0
[21:32:42.918] <TB1> INFO: TBM errors: 0
[21:32:42.918] <TB1> INFO: flawed TBM headers: 0
[21:32:42.918] <TB1> INFO: flawed TBM trailers: 0
[21:32:42.918] <TB1> INFO: event ID mismatches: 0
[21:32:42.918] <TB1> INFO: ROC errors: 0
[21:32:42.918] <TB1> INFO: missing ROC header(s): 0
[21:32:42.918] <TB1> INFO: misplaced readback start: 0
[21:32:42.918] <TB1> INFO: Pixel decoding errors: 0
[21:32:42.918] <TB1> INFO: pixel data incomplete: 0
[21:32:42.918] <TB1> INFO: pixel address: 0
[21:32:42.918] <TB1> INFO: pulse height fill bit: 0
[21:32:42.918] <TB1> INFO: buffer corruption: 0
[21:32:42.918] <TB1> INFO: enter test to run
[21:32:42.918] <TB1> INFO: test: trim80 no parameter change
[21:32:42.918] <TB1> INFO: running: trim80
[21:32:42.920] <TB1> INFO: ######################################################################
[21:32:42.920] <TB1> INFO: PixTestTrim80::doTest()
[21:32:42.920] <TB1> INFO: ######################################################################
[21:32:42.921] <TB1> INFO: ----------------------------------------------------------------------
[21:32:42.921] <TB1> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[21:32:42.921] <TB1> INFO: ----------------------------------------------------------------------
[21:32:42.963] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[21:32:42.963] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[21:32:42.976] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[21:32:42.976] <TB1> INFO: run 1 of 1
[21:32:43.213] <TB1> INFO: Expecting 5025280 events.
[21:33:11.555] <TB1> INFO: 677640 events read in total (27750ms).
[21:33:38.655] <TB1> INFO: 1351392 events read in total (54850ms).
[21:34:05.989] <TB1> INFO: 2022960 events read in total (82184ms).
[21:34:33.403] <TB1> INFO: 2692328 events read in total (109598ms).
[21:35:00.514] <TB1> INFO: 3360480 events read in total (136709ms).
[21:35:27.658] <TB1> INFO: 4027080 events read in total (163853ms).
[21:35:54.293] <TB1> INFO: 4691320 events read in total (190488ms).
[21:36:07.915] <TB1> INFO: 5025280 events read in total (204110ms).
[21:36:08.027] <TB1> INFO: Test took 205051ms.
[21:36:30.083] <TB1> INFO: ROC 0 VthrComp = 70
[21:36:30.084] <TB1> INFO: ROC 1 VthrComp = 75
[21:36:30.084] <TB1> INFO: ROC 2 VthrComp = 73
[21:36:30.084] <TB1> INFO: ROC 3 VthrComp = 74
[21:36:30.084] <TB1> INFO: ROC 4 VthrComp = 82
[21:36:30.084] <TB1> INFO: ROC 5 VthrComp = 66
[21:36:30.084] <TB1> INFO: ROC 6 VthrComp = 78
[21:36:30.084] <TB1> INFO: ROC 7 VthrComp = 68
[21:36:30.084] <TB1> INFO: ROC 8 VthrComp = 72
[21:36:30.085] <TB1> INFO: ROC 9 VthrComp = 74
[21:36:30.085] <TB1> INFO: ROC 10 VthrComp = 69
[21:36:30.085] <TB1> INFO: ROC 11 VthrComp = 81
[21:36:30.085] <TB1> INFO: ROC 12 VthrComp = 84
[21:36:30.085] <TB1> INFO: ROC 13 VthrComp = 78
[21:36:30.085] <TB1> INFO: ROC 14 VthrComp = 80
[21:36:30.085] <TB1> INFO: ROC 15 VthrComp = 69
[21:36:30.324] <TB1> INFO: Expecting 41600 events.
[21:36:33.807] <TB1> INFO: 41600 events read in total (2891ms).
[21:36:33.808] <TB1> INFO: Test took 3721ms.
[21:36:33.817] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[21:36:33.817] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[21:36:33.830] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[21:36:33.830] <TB1> INFO: run 1 of 1
[21:36:34.108] <TB1> INFO: Expecting 5025280 events.
[21:37:02.126] <TB1> INFO: 688320 events read in total (27426ms).
[21:37:29.476] <TB1> INFO: 1370944 events read in total (54776ms).
[21:37:56.718] <TB1> INFO: 2051840 events read in total (82018ms).
[21:38:24.157] <TB1> INFO: 2729856 events read in total (109457ms).
[21:38:52.057] <TB1> INFO: 3404024 events read in total (137357ms).
[21:39:19.522] <TB1> INFO: 4076408 events read in total (164822ms).
[21:39:47.159] <TB1> INFO: 4747328 events read in total (192459ms).
[21:39:58.577] <TB1> INFO: 5025280 events read in total (203877ms).
[21:39:58.657] <TB1> INFO: Test took 204826ms.
[21:40:22.021] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 104.211 for pixel 6/7 mean/min/max = 89.3526/74.4496/104.256
[21:40:22.022] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 111.527 for pixel 6/45 mean/min/max = 94.7026/77.7047/111.701
[21:40:22.022] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 108.45 for pixel 14/65 mean/min/max = 92.6242/76.7215/108.527
[21:40:22.023] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 108.739 for pixel 14/44 mean/min/max = 92.9374/76.8916/108.983
[21:40:22.023] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 109.568 for pixel 5/61 mean/min/max = 92.3352/75.0976/109.573
[21:40:22.024] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 107.204 for pixel 0/57 mean/min/max = 90.9398/74.6291/107.25
[21:40:22.024] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 109.421 for pixel 5/31 mean/min/max = 93.8941/78.217/109.571
[21:40:22.025] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 114.149 for pixel 12/79 mean/min/max = 93.4777/72.7888/114.167
[21:40:22.025] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 107.195 for pixel 1/79 mean/min/max = 91.7894/76.3209/107.258
[21:40:22.026] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 109.849 for pixel 8/78 mean/min/max = 94.0115/78.1576/109.865
[21:40:22.026] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 121.72 for pixel 2/14 mean/min/max = 97.3961/72.5176/122.275
[21:40:22.027] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 107.436 for pixel 24/76 mean/min/max = 91.262/74.968/107.556
[21:40:22.027] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 105.493 for pixel 50/79 mean/min/max = 90.5202/75.3089/105.732
[21:40:22.028] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 110.247 for pixel 0/65 mean/min/max = 93.7012/77.1154/110.287
[21:40:22.028] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 108.828 for pixel 6/67 mean/min/max = 92.0815/74.9894/109.174
[21:40:22.029] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 105.03 for pixel 6/60 mean/min/max = 89.3/73.3044/105.296
[21:40:22.029] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:40:22.118] <TB1> INFO: Expecting 411648 events.
[21:40:31.578] <TB1> INFO: 411648 events read in total (8869ms).
[21:40:31.585] <TB1> INFO: Expecting 411648 events.
[21:40:40.762] <TB1> INFO: 411648 events read in total (8774ms).
[21:40:40.777] <TB1> INFO: Expecting 411648 events.
[21:40:50.046] <TB1> INFO: 411648 events read in total (8867ms).
[21:40:50.064] <TB1> INFO: Expecting 411648 events.
[21:40:59.154] <TB1> INFO: 411648 events read in total (8687ms).
[21:40:59.170] <TB1> INFO: Expecting 411648 events.
[21:41:08.343] <TB1> INFO: 411648 events read in total (8770ms).
[21:41:08.361] <TB1> INFO: Expecting 411648 events.
[21:41:17.590] <TB1> INFO: 411648 events read in total (8826ms).
[21:41:17.612] <TB1> INFO: Expecting 411648 events.
[21:41:27.125] <TB1> INFO: 411648 events read in total (9110ms).
[21:41:27.150] <TB1> INFO: Expecting 411648 events.
[21:41:36.371] <TB1> INFO: 411648 events read in total (8817ms).
[21:41:36.398] <TB1> INFO: Expecting 411648 events.
[21:41:45.646] <TB1> INFO: 411648 events read in total (8845ms).
[21:41:45.688] <TB1> INFO: Expecting 411648 events.
[21:41:55.207] <TB1> INFO: 411648 events read in total (9116ms).
[21:41:55.241] <TB1> INFO: Expecting 411648 events.
[21:42:04.502] <TB1> INFO: 411648 events read in total (8858ms).
[21:42:04.545] <TB1> INFO: Expecting 411648 events.
[21:42:13.879] <TB1> INFO: 411648 events read in total (8931ms).
[21:42:13.928] <TB1> INFO: Expecting 411648 events.
[21:42:23.377] <TB1> INFO: 411648 events read in total (9046ms).
[21:42:23.428] <TB1> INFO: Expecting 411648 events.
[21:42:32.759] <TB1> INFO: 411648 events read in total (8928ms).
[21:42:32.813] <TB1> INFO: Expecting 411648 events.
[21:42:42.199] <TB1> INFO: 411648 events read in total (8983ms).
[21:42:42.257] <TB1> INFO: Expecting 411648 events.
[21:42:51.665] <TB1> INFO: 411648 events read in total (9005ms).
[21:42:51.727] <TB1> INFO: Test took 149698ms.
[21:42:53.255] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[21:42:53.270] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[21:42:53.270] <TB1> INFO: run 1 of 1
[21:42:53.507] <TB1> INFO: Expecting 5025280 events.
[21:43:21.578] <TB1> INFO: 671400 events read in total (27479ms).
[21:43:48.747] <TB1> INFO: 1339536 events read in total (54648ms).
[21:44:15.767] <TB1> INFO: 2007120 events read in total (81668ms).
[21:44:43.087] <TB1> INFO: 2670616 events read in total (108988ms).
[21:45:10.152] <TB1> INFO: 3329088 events read in total (136054ms).
[21:45:37.141] <TB1> INFO: 3986072 events read in total (163042ms).
[21:46:04.098] <TB1> INFO: 4640128 events read in total (189999ms).
[21:46:19.766] <TB1> INFO: 5025280 events read in total (205667ms).
[21:46:19.868] <TB1> INFO: Test took 206598ms.
[21:46:43.805] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 51.763637 .. 104.955789
[21:46:44.050] <TB1> INFO: Expecting 208000 events.
[21:46:54.182] <TB1> INFO: 208000 events read in total (9540ms).
[21:46:54.183] <TB1> INFO: Test took 10377ms.
[21:46:54.251] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 41 .. 114 (-1/-1) hits flags = 528 (plus default)
[21:46:54.265] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[21:46:54.265] <TB1> INFO: run 1 of 1
[21:46:54.549] <TB1> INFO: Expecting 2462720 events.
[21:47:22.337] <TB1> INFO: 683112 events read in total (27196ms).
[21:47:49.784] <TB1> INFO: 1365344 events read in total (54643ms).
[21:48:17.113] <TB1> INFO: 2039656 events read in total (81972ms).
[21:48:34.482] <TB1> INFO: 2462720 events read in total (99341ms).
[21:48:34.523] <TB1> INFO: Test took 100259ms.
[21:48:52.241] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 61.984601 .. 95.346259
[21:48:52.483] <TB1> INFO: Expecting 208000 events.
[21:49:02.150] <TB1> INFO: 208000 events read in total (9076ms).
[21:49:02.151] <TB1> INFO: Test took 9908ms.
[21:49:02.200] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 51 .. 105 (-1/-1) hits flags = 528 (plus default)
[21:49:02.213] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[21:49:02.213] <TB1> INFO: run 1 of 1
[21:49:02.491] <TB1> INFO: Expecting 1830400 events.
[21:49:31.576] <TB1> INFO: 680632 events read in total (28493ms).
[21:49:58.884] <TB1> INFO: 1360856 events read in total (55801ms).
[21:50:18.139] <TB1> INFO: 1830400 events read in total (75056ms).
[21:50:18.186] <TB1> INFO: Test took 75973ms.
[21:50:35.470] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 68.239372 .. 90.167852
[21:50:35.711] <TB1> INFO: Expecting 208000 events.
[21:50:45.459] <TB1> INFO: 208000 events read in total (9157ms).
[21:50:45.460] <TB1> INFO: Test took 9988ms.
[21:50:45.511] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 58 .. 100 (-1/-1) hits flags = 528 (plus default)
[21:50:45.525] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[21:50:45.525] <TB1> INFO: run 1 of 1
[21:50:45.813] <TB1> INFO: Expecting 1431040 events.
[21:51:14.325] <TB1> INFO: 676672 events read in total (27920ms).
[21:51:41.913] <TB1> INFO: 1352912 events read in total (55508ms).
[21:51:45.456] <TB1> INFO: 1431040 events read in total (59051ms).
[21:51:45.484] <TB1> INFO: Test took 59960ms.
[21:52:06.062] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 69.457206 .. 90.167852
[21:52:06.311] <TB1> INFO: Expecting 208000 events.
[21:52:16.028] <TB1> INFO: 208000 events read in total (9126ms).
[21:52:16.029] <TB1> INFO: Test took 9966ms.
[21:52:16.078] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 59 .. 100 (-1/-1) hits flags = 528 (plus default)
[21:52:16.091] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[21:52:16.091] <TB1> INFO: run 1 of 1
[21:52:16.370] <TB1> INFO: Expecting 1397760 events.
[21:52:44.928] <TB1> INFO: 673984 events read in total (27967ms).
[21:53:12.943] <TB1> INFO: 1347632 events read in total (55983ms).
[21:53:15.486] <TB1> INFO: 1397760 events read in total (58525ms).
[21:53:15.514] <TB1> INFO: Test took 59424ms.
[21:53:32.582] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[21:53:32.582] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[21:53:32.596] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[21:53:32.596] <TB1> INFO: run 1 of 1
[21:53:32.855] <TB1> INFO: Expecting 1364480 events.
[21:54:01.531] <TB1> INFO: 668616 events read in total (28084ms).
[21:54:29.784] <TB1> INFO: 1337376 events read in total (56337ms).
[21:54:31.298] <TB1> INFO: 1364480 events read in total (57851ms).
[21:54:31.324] <TB1> INFO: Test took 58728ms.
[21:54:48.386] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C0.dat
[21:54:48.387] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C1.dat
[21:54:48.387] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C2.dat
[21:54:48.387] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C3.dat
[21:54:48.387] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C4.dat
[21:54:48.387] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C5.dat
[21:54:48.387] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C6.dat
[21:54:48.387] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C7.dat
[21:54:48.387] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C8.dat
[21:54:48.387] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C9.dat
[21:54:48.387] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C10.dat
[21:54:48.388] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C11.dat
[21:54:48.388] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C12.dat
[21:54:48.388] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C13.dat
[21:54:48.388] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C14.dat
[21:54:48.388] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//dacParameters80_C15.dat
[21:54:48.388] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C0.dat
[21:54:48.393] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C1.dat
[21:54:48.398] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C2.dat
[21:54:48.403] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C3.dat
[21:54:48.407] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C4.dat
[21:54:48.412] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C5.dat
[21:54:48.417] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C6.dat
[21:54:48.422] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C7.dat
[21:54:48.428] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C8.dat
[21:54:48.432] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C9.dat
[21:54:48.437] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C10.dat
[21:54:48.442] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C11.dat
[21:54:48.447] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C12.dat
[21:54:48.452] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C13.dat
[21:54:48.456] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C14.dat
[21:54:48.461] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1106_FullQualification_2016-11-04_17h17m_1478276226//003_FulltestTrim80_p17//trimParameters80_C15.dat
[21:54:48.466] <TB1> INFO: PixTestTrim80::trimTest() done
[21:54:48.466] <TB1> INFO: vtrim: 92 127 107 93 112 93 103 111 97 100 129 101 108 93 109 82
[21:54:48.466] <TB1> INFO: vthrcomp: 70 75 73 74 82 66 78 68 72 74 69 81 84 78 80 69
[21:54:48.466] <TB1> INFO: vcal mean: 80.02 80.04 80.00 80.04 80.00 80.05 80.02 80.01 80.04 79.97 80.00 80.00 79.99 79.97 79.98 80.02
[21:54:48.466] <TB1> INFO: vcal RMS: 0.73 0.78 0.71 0.79 0.74 0.77 0.76 0.85 0.71 1.43 0.88 0.73 0.75 0.73 0.75 0.73
[21:54:48.466] <TB1> INFO: bits mean: 10.65 9.75 9.65 9.44 10.03 10.23 9.36 10.09 9.69 9.24 9.66 9.85 10.17 9.15 9.85 10.50
[21:54:48.466] <TB1> INFO: bits RMS: 2.29 2.14 2.33 2.37 2.40 2.45 2.23 2.59 2.38 2.29 2.55 2.50 2.35 2.49 2.48 2.52
[21:54:48.473] <TB1> INFO: ----------------------------------------------------------------------
[21:54:48.473] <TB1> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[21:54:48.473] <TB1> INFO: ----------------------------------------------------------------------
[21:54:48.475] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[21:54:48.488] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[21:54:48.488] <TB1> INFO: run 1 of 1
[21:54:48.725] <TB1> INFO: Expecting 4160000 events.
[21:55:21.847] <TB1> INFO: 769020 events read in total (32530ms).
[21:55:54.405] <TB1> INFO: 1530445 events read in total (65088ms).
[21:56:27.061] <TB1> INFO: 2285965 events read in total (97744ms).
[21:56:59.427] <TB1> INFO: 3035455 events read in total (130110ms).
[21:57:30.657] <TB1> INFO: 3780025 events read in total (161341ms).
[21:57:47.108] <TB1> INFO: 4160000 events read in total (177791ms).
[21:57:47.200] <TB1> INFO: Test took 178711ms.
[21:58:10.617] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[21:58:10.630] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[21:58:10.630] <TB1> INFO: run 1 of 1
[21:58:10.887] <TB1> INFO: Expecting 4264000 events.
[21:58:42.905] <TB1> INFO: 736770 events read in total (31427ms).
[21:59:14.489] <TB1> INFO: 1467190 events read in total (63011ms).
[21:59:45.941] <TB1> INFO: 2193990 events read in total (94463ms).
[22:00:17.166] <TB1> INFO: 2915470 events read in total (125688ms).
[22:00:48.524] <TB1> INFO: 3633535 events read in total (157046ms).
[22:01:16.051] <TB1> INFO: 4264000 events read in total (184573ms).
[22:01:16.135] <TB1> INFO: Test took 185504ms.
[22:01:45.958] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[22:01:45.972] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[22:01:45.972] <TB1> INFO: run 1 of 1
[22:01:46.298] <TB1> INFO: Expecting 4139200 events.
[22:02:19.417] <TB1> INFO: 745180 events read in total (32527ms).
[22:02:51.912] <TB1> INFO: 1484560 events read in total (65022ms).
[22:03:23.372] <TB1> INFO: 2219415 events read in total (96482ms).
[22:03:55.012] <TB1> INFO: 2948690 events read in total (128122ms).
[22:04:26.281] <TB1> INFO: 3674340 events read in total (159391ms).
[22:04:46.592] <TB1> INFO: 4139200 events read in total (179702ms).
[22:04:46.677] <TB1> INFO: Test took 180705ms.
[22:05:12.666] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 201 (-1/-1) hits flags = 528 (plus default)
[22:05:12.680] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[22:05:12.680] <TB1> INFO: run 1 of 1
[22:05:12.935] <TB1> INFO: Expecting 4201600 events.
[22:05:45.549] <TB1> INFO: 741355 events read in total (32022ms).
[22:06:17.703] <TB1> INFO: 1476640 events read in total (64176ms).
[22:06:48.652] <TB1> INFO: 2207560 events read in total (95125ms).
[22:07:20.661] <TB1> INFO: 2933150 events read in total (127134ms).
[22:07:52.353] <TB1> INFO: 3655435 events read in total (158826ms).
[22:08:16.584] <TB1> INFO: 4201600 events read in total (183057ms).
[22:08:16.687] <TB1> INFO: Test took 184007ms.
[22:08:44.690] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[22:08:44.704] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[22:08:44.704] <TB1> INFO: run 1 of 1
[22:08:44.939] <TB1> INFO: Expecting 4160000 events.
[22:09:17.566] <TB1> INFO: 744020 events read in total (32035ms).
[22:09:49.450] <TB1> INFO: 1482190 events read in total (63919ms).
[22:10:21.149] <TB1> INFO: 2215845 events read in total (95619ms).
[22:10:52.509] <TB1> INFO: 2943955 events read in total (126978ms).
[22:11:23.646] <TB1> INFO: 3668380 events read in total (158115ms).
[22:11:44.899] <TB1> INFO: 4160000 events read in total (179368ms).
[22:11:44.989] <TB1> INFO: Test took 180285ms.
[22:12:11.789] <TB1> INFO: PixTestTrim80::trimBitTest() done
[22:12:11.790] <TB1> INFO: PixTestTrim80::doTest() done, duration: 2368 seconds
[22:12:12.434] <TB1> INFO: enter test to run
[22:12:12.434] <TB1> INFO: test: exit no parameter change
[22:12:12.644] <TB1> QUIET: Connection to board 154 closed.
[22:12:12.647] <TB1> INFO: pXar: this is the end, my friend