[10:40:22.531] <TB1> INFO: *** Welcome to pxar ***
[10:40:22.531] <TB1> INFO: *** Today: 2016/11/02
[10:40:22.539] <TB1> INFO: *** Version: c8ba-dirty
[10:40:22.539] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C15.dat
[10:40:22.539] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//tbmParameters_C1b.dat
[10:40:22.539] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//defaultMaskFile.dat
[10:40:22.539] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters_C15.dat
[10:40:22.594] <TB1> INFO: clk: 4
[10:40:22.594] <TB1> INFO: ctr: 4
[10:40:22.594] <TB1> INFO: sda: 19
[10:40:22.594] <TB1> INFO: tin: 9
[10:40:22.594] <TB1> INFO: level: 15
[10:40:22.594] <TB1> INFO: triggerdelay: 0
[10:40:22.594] <TB1> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[10:40:22.594] <TB1> INFO: Log level: INFO
[10:40:22.603] <TB1> INFO: Found DTB DTB_WXBYFL
[10:40:22.613] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[10:40:22.615] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
------------------------------------------------------
[10:40:22.617] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[10:40:24.168] <TB1> INFO: DUT info:
[10:40:24.168] <TB1> INFO: The DUT currently contains the following objects:
[10:40:24.168] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[10:40:24.168] <TB1> INFO: TBM Core alpha (0): 7 registers set
[10:40:24.168] <TB1> INFO: TBM Core beta (1): 7 registers set
[10:40:24.168] <TB1> INFO: TBM Core alpha (2): 7 registers set
[10:40:24.168] <TB1> INFO: TBM Core beta (3): 7 registers set
[10:40:24.168] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[10:40:24.168] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.168] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[10:40:24.568] <TB1> INFO: enter 'restricted' command line mode
[10:40:24.569] <TB1> INFO: enter test to run
[10:40:24.569] <TB1> INFO: test: pretest no parameter change
[10:40:24.569] <TB1> INFO: running: pretest
[10:40:25.094] <TB1> INFO: ######################################################################
[10:40:25.094] <TB1> INFO: PixTestPretest::doTest()
[10:40:25.094] <TB1> INFO: ######################################################################
[10:40:25.095] <TB1> INFO: ----------------------------------------------------------------------
[10:40:25.095] <TB1> INFO: PixTestPretest::programROC()
[10:40:25.095] <TB1> INFO: ----------------------------------------------------------------------
[10:40:43.108] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[10:40:43.108] <TB1> INFO: IA differences per ROC: 17.7 20.1 18.5 20.1 19.3 19.3 17.7 18.5 18.5 18.5 18.5 17.7 19.3 18.5 18.5 19.3
[10:40:43.142] <TB1> INFO: ----------------------------------------------------------------------
[10:40:43.142] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[10:40:43.142] <TB1> INFO: ----------------------------------------------------------------------
[10:40:50.521] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 386.7 mA = 24.1687 mA/ROC
[10:40:50.521] <TB1> INFO: i(loss) [mA/ROC]: 20.1 20.1 20.1 20.1 19.3 19.3 20.1 20.1 20.9 20.1 19.3 20.1 19.3 20.1 19.3 20.1
[10:40:50.549] <TB1> INFO: ----------------------------------------------------------------------
[10:40:50.549] <TB1> INFO: PixTestPretest::findTiming()
[10:40:50.549] <TB1> INFO: ----------------------------------------------------------------------
[10:40:50.549] <TB1> INFO: PixTestCmd::init()

[10:41:21.847] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[10:41:21.847] <TB1> INFO: (success/tries = 100/100), width = 4
[10:41:23.347] <TB1> INFO: ----------------------------------------------------------------------
[10:41:23.347] <TB1> INFO: PixTestPretest::findWorkingPixel()
[10:41:23.347] <TB1> INFO: ----------------------------------------------------------------------
[10:41:23.438] <TB1> INFO: Expecting 231680 events.
[10:41:33.122] <TB1> INFO: 231680 events read in total (9092ms).
[10:41:33.130] <TB1> INFO: Test took 9781ms.
[10:41:33.377] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[10:41:33.409] <TB1> INFO: ----------------------------------------------------------------------
[10:41:33.409] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[10:41:33.409] <TB1> INFO: ----------------------------------------------------------------------
[10:41:33.501] <TB1> INFO: Expecting 231680 events.
[10:41:43.105] <TB1> INFO: 231680 events read in total (9012ms).
[10:41:43.112] <TB1> INFO: Test took 9699ms.
[10:41:43.374] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[10:41:43.374] <TB1> INFO: CalDel: 99 107 96 81 109 96 81 91 111 99 82 85 109 86 82 95
[10:41:43.374] <TB1> INFO: VthrComp: 51 51 51 51 51 51 51 52 51 54 51 55 51 51 51 51
[10:41:43.377] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C0.dat
[10:41:43.377] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C1.dat
[10:41:43.377] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C2.dat
[10:41:43.377] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C3.dat
[10:41:43.377] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C4.dat
[10:41:43.377] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C5.dat
[10:41:43.377] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C6.dat
[10:41:43.378] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C7.dat
[10:41:43.378] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C8.dat
[10:41:43.378] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C9.dat
[10:41:43.378] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C10.dat
[10:41:43.378] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C11.dat
[10:41:43.378] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C12.dat
[10:41:43.378] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C13.dat
[10:41:43.378] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C14.dat
[10:41:43.378] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters_C15.dat
[10:41:43.379] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//tbmParameters_C0a.dat
[10:41:43.379] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//tbmParameters_C0b.dat
[10:41:43.379] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//tbmParameters_C1a.dat
[10:41:43.379] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//tbmParameters_C1b.dat
[10:41:43.379] <TB1> INFO: PixTestPretest::doTest() done, duration: 78 seconds
[10:41:43.476] <TB1> INFO: enter test to run
[10:41:43.476] <TB1> INFO: test: FullTest no parameter change
[10:41:43.476] <TB1> INFO: running: fulltest
[10:41:43.476] <TB1> INFO: ######################################################################
[10:41:43.476] <TB1> INFO: PixTestFullTest::doTest()
[10:41:43.476] <TB1> INFO: ######################################################################
[10:41:43.477] <TB1> INFO: ######################################################################
[10:41:43.477] <TB1> INFO: PixTestAlive::doTest()
[10:41:43.477] <TB1> INFO: ######################################################################
[10:41:43.478] <TB1> INFO: ----------------------------------------------------------------------
[10:41:43.478] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:41:43.478] <TB1> INFO: ----------------------------------------------------------------------
[10:41:43.720] <TB1> INFO: Expecting 41600 events.
[10:41:47.223] <TB1> INFO: 41600 events read in total (2911ms).
[10:41:47.224] <TB1> INFO: Test took 3744ms.
[10:41:47.450] <TB1> INFO: PixTestAlive::aliveTest() done
[10:41:47.450] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:41:47.451] <TB1> INFO: ----------------------------------------------------------------------
[10:41:47.451] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:41:47.451] <TB1> INFO: ----------------------------------------------------------------------
[10:41:47.685] <TB1> INFO: Expecting 41600 events.
[10:41:50.717] <TB1> INFO: 41600 events read in total (2441ms).
[10:41:50.717] <TB1> INFO: Test took 3265ms.
[10:41:50.718] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[10:41:50.957] <TB1> INFO: PixTestAlive::maskTest() done
[10:41:50.957] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:41:50.958] <TB1> INFO: ----------------------------------------------------------------------
[10:41:50.958] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:41:50.958] <TB1> INFO: ----------------------------------------------------------------------
[10:41:51.210] <TB1> INFO: Expecting 41600 events.
[10:41:54.698] <TB1> INFO: 41600 events read in total (2896ms).
[10:41:54.699] <TB1> INFO: Test took 3740ms.
[10:41:54.926] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[10:41:54.926] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:41:54.926] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[10:41:54.926] <TB1> INFO: Decoding statistics:
[10:41:54.926] <TB1> INFO: General information:
[10:41:54.926] <TB1> INFO: 16bit words read: 0
[10:41:54.926] <TB1> INFO: valid events total: 0
[10:41:54.926] <TB1> INFO: empty events: 0
[10:41:54.926] <TB1> INFO: valid events with pixels: 0
[10:41:54.926] <TB1> INFO: valid pixel hits: 0
[10:41:54.926] <TB1> INFO: Event errors: 0
[10:41:54.926] <TB1> INFO: start marker: 0
[10:41:54.926] <TB1> INFO: stop marker: 0
[10:41:54.926] <TB1> INFO: overflow: 0
[10:41:54.926] <TB1> INFO: invalid 5bit words: 0
[10:41:54.926] <TB1> INFO: invalid XOR eye diagram: 0
[10:41:54.926] <TB1> INFO: frame (failed synchr.): 0
[10:41:54.926] <TB1> INFO: idle data (no TBM trl): 0
[10:41:54.926] <TB1> INFO: no data (only TBM hdr): 0
[10:41:54.926] <TB1> INFO: TBM errors: 0
[10:41:54.926] <TB1> INFO: flawed TBM headers: 0
[10:41:54.926] <TB1> INFO: flawed TBM trailers: 0
[10:41:54.926] <TB1> INFO: event ID mismatches: 0
[10:41:54.926] <TB1> INFO: ROC errors: 0
[10:41:54.926] <TB1> INFO: missing ROC header(s): 0
[10:41:54.926] <TB1> INFO: misplaced readback start: 0
[10:41:54.926] <TB1> INFO: Pixel decoding errors: 0
[10:41:54.926] <TB1> INFO: pixel data incomplete: 0
[10:41:54.926] <TB1> INFO: pixel address: 0
[10:41:54.926] <TB1> INFO: pulse height fill bit: 0
[10:41:54.926] <TB1> INFO: buffer corruption: 0
[10:41:54.933] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C15.dat
[10:41:54.934] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[10:41:54.934] <TB1> INFO: ######################################################################
[10:41:54.934] <TB1> INFO: PixTestReadback::doTest()
[10:41:54.934] <TB1> INFO: ######################################################################
[10:41:54.934] <TB1> INFO: ----------------------------------------------------------------------
[10:41:54.934] <TB1> INFO: PixTestReadback::CalibrateVd()
[10:41:54.934] <TB1> INFO: ----------------------------------------------------------------------
[10:42:04.928] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C0.dat
[10:42:04.928] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C1.dat
[10:42:04.929] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C2.dat
[10:42:04.929] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C3.dat
[10:42:04.929] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C4.dat
[10:42:04.929] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C5.dat
[10:42:04.929] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C6.dat
[10:42:04.929] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C7.dat
[10:42:04.929] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C8.dat
[10:42:04.929] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C9.dat
[10:42:04.929] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C10.dat
[10:42:04.929] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C11.dat
[10:42:04.929] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C12.dat
[10:42:04.929] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C13.dat
[10:42:04.929] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C14.dat
[10:42:04.929] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C15.dat
[10:42:04.961] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:42:04.961] <TB1> INFO: ----------------------------------------------------------------------
[10:42:04.961] <TB1> INFO: PixTestReadback::CalibrateVa()
[10:42:04.961] <TB1> INFO: ----------------------------------------------------------------------
[10:42:14.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C0.dat
[10:42:14.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C1.dat
[10:42:14.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C2.dat
[10:42:14.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C3.dat
[10:42:14.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C4.dat
[10:42:14.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C5.dat
[10:42:14.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C6.dat
[10:42:14.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C7.dat
[10:42:14.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C8.dat
[10:42:14.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C9.dat
[10:42:14.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C10.dat
[10:42:14.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C11.dat
[10:42:14.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C12.dat
[10:42:14.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C13.dat
[10:42:14.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C14.dat
[10:42:14.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C15.dat
[10:42:14.880] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:42:14.880] <TB1> INFO: ----------------------------------------------------------------------
[10:42:14.880] <TB1> INFO: PixTestReadback::readbackVbg()
[10:42:14.880] <TB1> INFO: ----------------------------------------------------------------------
[10:42:22.520] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:42:22.521] <TB1> INFO: ----------------------------------------------------------------------
[10:42:22.521] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[10:42:22.521] <TB1> INFO: ----------------------------------------------------------------------
[10:42:22.521] <TB1> INFO: Vbg will be calibrated using Vd calibration
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 149.2calibrated Vbg = 1.1457 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 151.4calibrated Vbg = 1.14954 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 146.9calibrated Vbg = 1.14331 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 150.3calibrated Vbg = 1.13377 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 159.5calibrated Vbg = 1.13758 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 149.1calibrated Vbg = 1.13928 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 160.9calibrated Vbg = 1.14263 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 154.9calibrated Vbg = 1.14878 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 151.9calibrated Vbg = 1.14258 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 147.9calibrated Vbg = 1.13369 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 156.5calibrated Vbg = 1.12908 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 153.8calibrated Vbg = 1.13384 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 148calibrated Vbg = 1.1402 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152calibrated Vbg = 1.14628 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 150.8calibrated Vbg = 1.14412 :::*/*/*/*/
[10:42:22.521] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 154.2calibrated Vbg = 1.14525 :::*/*/*/*/
[10:42:22.523] <TB1> INFO: ----------------------------------------------------------------------
[10:42:22.523] <TB1> INFO: PixTestReadback::CalibrateIa()
[10:42:22.523] <TB1> INFO: ----------------------------------------------------------------------
[10:45:02.828] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C0.dat
[10:45:02.828] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C1.dat
[10:45:02.828] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C2.dat
[10:45:02.828] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C3.dat
[10:45:02.828] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C4.dat
[10:45:02.828] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C5.dat
[10:45:02.828] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C6.dat
[10:45:02.828] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C7.dat
[10:45:02.828] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C8.dat
[10:45:02.828] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C9.dat
[10:45:02.828] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C10.dat
[10:45:02.829] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C11.dat
[10:45:02.829] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C12.dat
[10:45:02.829] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C13.dat
[10:45:02.829] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C14.dat
[10:45:02.829] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//readbackCal_C15.dat
[10:45:02.855] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:45:02.856] <TB1> INFO: PixTestReadback::doTest() done
[10:45:02.856] <TB1> INFO: Decoding statistics:
[10:45:02.856] <TB1> INFO: General information:
[10:45:02.856] <TB1> INFO: 16bit words read: 1536
[10:45:02.856] <TB1> INFO: valid events total: 256
[10:45:02.856] <TB1> INFO: empty events: 256
[10:45:02.856] <TB1> INFO: valid events with pixels: 0
[10:45:02.856] <TB1> INFO: valid pixel hits: 0
[10:45:02.856] <TB1> INFO: Event errors: 0
[10:45:02.856] <TB1> INFO: start marker: 0
[10:45:02.856] <TB1> INFO: stop marker: 0
[10:45:02.856] <TB1> INFO: overflow: 0
[10:45:02.856] <TB1> INFO: invalid 5bit words: 0
[10:45:02.856] <TB1> INFO: invalid XOR eye diagram: 0
[10:45:02.856] <TB1> INFO: frame (failed synchr.): 0
[10:45:02.856] <TB1> INFO: idle data (no TBM trl): 0
[10:45:02.856] <TB1> INFO: no data (only TBM hdr): 0
[10:45:02.856] <TB1> INFO: TBM errors: 0
[10:45:02.856] <TB1> INFO: flawed TBM headers: 0
[10:45:02.856] <TB1> INFO: flawed TBM trailers: 0
[10:45:02.856] <TB1> INFO: event ID mismatches: 0
[10:45:02.856] <TB1> INFO: ROC errors: 0
[10:45:02.856] <TB1> INFO: missing ROC header(s): 0
[10:45:02.856] <TB1> INFO: misplaced readback start: 0
[10:45:02.856] <TB1> INFO: Pixel decoding errors: 0
[10:45:02.856] <TB1> INFO: pixel data incomplete: 0
[10:45:02.856] <TB1> INFO: pixel address: 0
[10:45:02.856] <TB1> INFO: pulse height fill bit: 0
[10:45:02.856] <TB1> INFO: buffer corruption: 0
[10:45:02.892] <TB1> INFO: ######################################################################
[10:45:02.892] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[10:45:02.892] <TB1> INFO: ######################################################################
[10:45:02.894] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[10:45:02.906] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[10:45:02.906] <TB1> INFO: run 1 of 1
[10:45:03.138] <TB1> INFO: Expecting 3120000 events.
[10:45:32.957] <TB1> INFO: 649905 events read in total (29227ms).











[10:46:01.699] <TB1> INFO: 1295075 events read in total (57970ms).











[10:46:30.584] <TB1> INFO: 1937155 events read in total (86854ms).











[10:46:59.682] <TB1> INFO: 2580375 events read in total (115952ms).











[10:47:24.449] <TB1> INFO: 3120000 events read in total (140719ms).
[10:47:24.513] <TB1> INFO: Test took 141608ms.
[10:47:51.562] <TB1> INFO: PixTestBBMap::doTest() done with 4 decoding errors: , duration: 168 seconds
[10:47:51.562] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 7
[10:47:51.562] <TB1> INFO: separation cut (per ROC): 97 103 99 98 97 97 107 109 106 114 106 110 106 106 96 100
[10:47:51.562] <TB1> INFO: Decoding statistics:
[10:47:51.562] <TB1> INFO: General information:
[10:47:51.562] <TB1> INFO: 16bit words read: 0
[10:47:51.562] <TB1> INFO: valid events total: 0
[10:47:51.562] <TB1> INFO: empty events: 0
[10:47:51.562] <TB1> INFO: valid events with pixels: 0
[10:47:51.562] <TB1> INFO: valid pixel hits: 0
[10:47:51.562] <TB1> INFO: Event errors: 0
[10:47:51.562] <TB1> INFO: start marker: 0
[10:47:51.562] <TB1> INFO: stop marker: 0
[10:47:51.562] <TB1> INFO: overflow: 0
[10:47:51.562] <TB1> INFO: invalid 5bit words: 0
[10:47:51.562] <TB1> INFO: invalid XOR eye diagram: 0
[10:47:51.562] <TB1> INFO: frame (failed synchr.): 0
[10:47:51.562] <TB1> INFO: idle data (no TBM trl): 0
[10:47:51.562] <TB1> INFO: no data (only TBM hdr): 0
[10:47:51.562] <TB1> INFO: TBM errors: 0
[10:47:51.563] <TB1> INFO: flawed TBM headers: 0
[10:47:51.563] <TB1> INFO: flawed TBM trailers: 0
[10:47:51.563] <TB1> INFO: event ID mismatches: 0
[10:47:51.563] <TB1> INFO: ROC errors: 0
[10:47:51.563] <TB1> INFO: missing ROC header(s): 0
[10:47:51.563] <TB1> INFO: misplaced readback start: 0
[10:47:51.563] <TB1> INFO: Pixel decoding errors: 0
[10:47:51.563] <TB1> INFO: pixel data incomplete: 0
[10:47:51.563] <TB1> INFO: pixel address: 0
[10:47:51.563] <TB1> INFO: pulse height fill bit: 0
[10:47:51.563] <TB1> INFO: buffer corruption: 0
[10:47:51.599] <TB1> INFO: ######################################################################
[10:47:51.599] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:47:51.599] <TB1> INFO: ######################################################################
[10:47:51.599] <TB1> INFO: ----------------------------------------------------------------------
[10:47:51.599] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:47:51.599] <TB1> INFO: ----------------------------------------------------------------------
[10:47:51.599] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[10:47:51.609] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[10:47:51.609] <TB1> INFO: run 1 of 1
[10:47:51.861] <TB1> INFO: Expecting 36608000 events.
[10:48:14.646] <TB1> INFO: 663300 events read in total (22194ms).
[10:48:37.153] <TB1> INFO: 1315500 events read in total (44701ms).
[10:48:59.268] <TB1> INFO: 1966400 events read in total (66816ms).
[10:49:21.419] <TB1> INFO: 2618750 events read in total (88968ms).
[10:49:43.528] <TB1> INFO: 3269400 events read in total (111077ms).
[10:50:06.021] <TB1> INFO: 3921650 events read in total (133569ms).
[10:50:28.007] <TB1> INFO: 4572950 events read in total (155555ms).
[10:50:50.425] <TB1> INFO: 5223500 events read in total (177973ms).
[10:51:12.507] <TB1> INFO: 5874600 events read in total (200055ms).
[10:51:34.700] <TB1> INFO: 6525400 events read in total (222248ms).
[10:51:57.092] <TB1> INFO: 7176250 events read in total (244640ms).
[10:52:19.181] <TB1> INFO: 7823650 events read in total (266729ms).
[10:52:41.174] <TB1> INFO: 8472850 events read in total (288722ms).
[10:53:03.316] <TB1> INFO: 9122900 events read in total (310864ms).
[10:53:25.652] <TB1> INFO: 9773700 events read in total (333200ms).
[10:53:47.798] <TB1> INFO: 10424100 events read in total (355346ms).
[10:54:09.804] <TB1> INFO: 11075600 events read in total (377352ms).
[10:54:31.749] <TB1> INFO: 11725600 events read in total (399297ms).
[10:54:53.866] <TB1> INFO: 12373900 events read in total (421414ms).
[10:55:15.849] <TB1> INFO: 13022950 events read in total (443397ms).
[10:55:37.902] <TB1> INFO: 13672700 events read in total (465450ms).
[10:56:00.060] <TB1> INFO: 14322550 events read in total (487608ms).
[10:56:22.265] <TB1> INFO: 14973050 events read in total (509813ms).
[10:56:44.423] <TB1> INFO: 15621350 events read in total (531971ms).
[10:57:06.667] <TB1> INFO: 16269850 events read in total (554215ms).
[10:57:28.745] <TB1> INFO: 16918750 events read in total (576293ms).
[10:57:50.933] <TB1> INFO: 17566900 events read in total (598481ms).
[10:58:13.053] <TB1> INFO: 18214800 events read in total (620601ms).
[10:58:34.832] <TB1> INFO: 18858750 events read in total (642381ms).
[10:58:56.794] <TB1> INFO: 19506250 events read in total (664342ms).
[10:59:18.836] <TB1> INFO: 20150100 events read in total (686385ms).
[10:59:40.714] <TB1> INFO: 20795400 events read in total (708262ms).
[11:00:02.816] <TB1> INFO: 21441700 events read in total (730364ms).
[11:00:24.567] <TB1> INFO: 22086050 events read in total (752115ms).
[11:00:46.757] <TB1> INFO: 22731200 events read in total (774305ms).
[11:01:08.847] <TB1> INFO: 23378250 events read in total (796395ms).
[11:01:30.721] <TB1> INFO: 24023500 events read in total (818269ms).
[11:01:52.790] <TB1> INFO: 24669700 events read in total (840338ms).
[11:02:15.058] <TB1> INFO: 25314700 events read in total (862606ms).
[11:02:37.207] <TB1> INFO: 25959250 events read in total (884755ms).
[11:02:59.311] <TB1> INFO: 26606050 events read in total (906859ms).
[11:03:21.427] <TB1> INFO: 27250400 events read in total (928975ms).
[11:03:43.628] <TB1> INFO: 27895350 events read in total (951176ms).
[11:04:05.932] <TB1> INFO: 28539450 events read in total (973480ms).
[11:04:27.858] <TB1> INFO: 29184700 events read in total (995406ms).
[11:04:49.900] <TB1> INFO: 29828250 events read in total (1017448ms).
[11:05:11.936] <TB1> INFO: 30471650 events read in total (1039484ms).
[11:05:33.785] <TB1> INFO: 31114700 events read in total (1061333ms).
[11:05:55.923] <TB1> INFO: 31757550 events read in total (1083471ms).
[11:06:17.964] <TB1> INFO: 32401900 events read in total (1105512ms).
[11:06:39.921] <TB1> INFO: 33044450 events read in total (1127469ms).
[11:07:01.794] <TB1> INFO: 33688650 events read in total (1149342ms).
[11:07:23.590] <TB1> INFO: 34333000 events read in total (1171138ms).
[11:07:45.551] <TB1> INFO: 34977400 events read in total (1193099ms).
[11:08:07.676] <TB1> INFO: 35622300 events read in total (1215224ms).
[11:08:30.090] <TB1> INFO: 36274300 events read in total (1237638ms).
[11:08:41.504] <TB1> INFO: 36608000 events read in total (1249052ms).
[11:08:41.564] <TB1> INFO: Test took 1249954ms.
[11:08:41.976] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:08:43.877] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:08:45.915] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:08:47.976] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:08:50.053] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:08:51.543] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:08:53.366] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:08:55.505] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:08:57.077] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:08:58.668] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:09:00.382] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:09:02.342] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:09:04.289] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:09:06.336] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:09:08.339] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:09:10.445] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:09:12.412] <TB1> INFO: PixTestScurves::scurves() done
[11:09:12.412] <TB1> INFO: Vcal mean: 103.65 112.81 102.06 104.43 109.40 99.03 111.91 126.99 110.08 118.71 113.84 119.29 108.71 114.34 100.63 107.52
[11:09:12.412] <TB1> INFO: Vcal RMS: 5.24 4.62 4.84 4.85 4.80 4.95 4.74 6.21 4.80 7.82 4.96 6.32 4.70 5.37 5.02 4.58
[11:09:12.414] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1280 seconds
[11:09:12.414] <TB1> INFO: Decoding statistics:
[11:09:12.414] <TB1> INFO: General information:
[11:09:12.414] <TB1> INFO: 16bit words read: 0
[11:09:12.414] <TB1> INFO: valid events total: 0
[11:09:12.414] <TB1> INFO: empty events: 0
[11:09:12.414] <TB1> INFO: valid events with pixels: 0
[11:09:12.414] <TB1> INFO: valid pixel hits: 0
[11:09:12.414] <TB1> INFO: Event errors: 0
[11:09:12.414] <TB1> INFO: start marker: 0
[11:09:12.414] <TB1> INFO: stop marker: 0
[11:09:12.414] <TB1> INFO: overflow: 0
[11:09:12.414] <TB1> INFO: invalid 5bit words: 0
[11:09:12.414] <TB1> INFO: invalid XOR eye diagram: 0
[11:09:12.414] <TB1> INFO: frame (failed synchr.): 0
[11:09:12.414] <TB1> INFO: idle data (no TBM trl): 0
[11:09:12.414] <TB1> INFO: no data (only TBM hdr): 0
[11:09:12.414] <TB1> INFO: TBM errors: 0
[11:09:12.414] <TB1> INFO: flawed TBM headers: 0
[11:09:12.414] <TB1> INFO: flawed TBM trailers: 0
[11:09:12.414] <TB1> INFO: event ID mismatches: 0
[11:09:12.414] <TB1> INFO: ROC errors: 0
[11:09:12.414] <TB1> INFO: missing ROC header(s): 0
[11:09:12.414] <TB1> INFO: misplaced readback start: 0
[11:09:12.414] <TB1> INFO: Pixel decoding errors: 0
[11:09:12.414] <TB1> INFO: pixel data incomplete: 0
[11:09:12.414] <TB1> INFO: pixel address: 0
[11:09:12.414] <TB1> INFO: pulse height fill bit: 0
[11:09:12.414] <TB1> INFO: buffer corruption: 0
[11:09:12.489] <TB1> INFO: ######################################################################
[11:09:12.490] <TB1> INFO: PixTestTrim::doTest()
[11:09:12.490] <TB1> INFO: ######################################################################
[11:09:12.491] <TB1> INFO: ----------------------------------------------------------------------
[11:09:12.491] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[11:09:12.491] <TB1> INFO: ----------------------------------------------------------------------
[11:09:12.533] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[11:09:12.533] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:09:12.542] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:09:12.542] <TB1> INFO: run 1 of 1
[11:09:12.779] <TB1> INFO: Expecting 5025280 events.
[11:09:42.092] <TB1> INFO: 810416 events read in total (28719ms).
[11:10:11.143] <TB1> INFO: 1618104 events read in total (57770ms).
[11:10:40.226] <TB1> INFO: 2424568 events read in total (86853ms).
[11:11:09.233] <TB1> INFO: 3225768 events read in total (115860ms).
[11:11:38.607] <TB1> INFO: 4024808 events read in total (145234ms).
[11:12:08.107] <TB1> INFO: 4820584 events read in total (174734ms).
[11:12:16.337] <TB1> INFO: 5025280 events read in total (182964ms).
[11:12:16.388] <TB1> INFO: Test took 183846ms.
[11:12:36.342] <TB1> INFO: ROC 0 VthrComp = 112
[11:12:36.342] <TB1> INFO: ROC 1 VthrComp = 125
[11:12:36.342] <TB1> INFO: ROC 2 VthrComp = 116
[11:12:36.342] <TB1> INFO: ROC 3 VthrComp = 118
[11:12:36.342] <TB1> INFO: ROC 4 VthrComp = 116
[11:12:36.342] <TB1> INFO: ROC 5 VthrComp = 108
[11:12:36.342] <TB1> INFO: ROC 6 VthrComp = 124
[11:12:36.342] <TB1> INFO: ROC 7 VthrComp = 131
[11:12:36.342] <TB1> INFO: ROC 8 VthrComp = 124
[11:12:36.342] <TB1> INFO: ROC 9 VthrComp = 129
[11:12:36.343] <TB1> INFO: ROC 10 VthrComp = 124
[11:12:36.343] <TB1> INFO: ROC 11 VthrComp = 129
[11:12:36.343] <TB1> INFO: ROC 12 VthrComp = 121
[11:12:36.344] <TB1> INFO: ROC 13 VthrComp = 126
[11:12:36.344] <TB1> INFO: ROC 14 VthrComp = 110
[11:12:36.344] <TB1> INFO: ROC 15 VthrComp = 120
[11:12:36.578] <TB1> INFO: Expecting 41600 events.
[11:12:40.147] <TB1> INFO: 41600 events read in total (2978ms).
[11:12:40.147] <TB1> INFO: Test took 3802ms.
[11:12:40.156] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[11:12:40.156] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:12:40.165] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:12:40.165] <TB1> INFO: run 1 of 1
[11:12:40.443] <TB1> INFO: Expecting 5025280 events.
[11:13:06.163] <TB1> INFO: 587416 events read in total (25128ms).
[11:13:31.494] <TB1> INFO: 1173408 events read in total (50459ms).
[11:13:56.788] <TB1> INFO: 1759832 events read in total (75753ms).
[11:14:22.110] <TB1> INFO: 2346144 events read in total (101075ms).
[11:14:47.515] <TB1> INFO: 2930832 events read in total (126480ms).
[11:15:13.092] <TB1> INFO: 3514456 events read in total (152057ms).
[11:15:37.981] <TB1> INFO: 4097728 events read in total (176946ms).
[11:16:03.205] <TB1> INFO: 4680456 events read in total (202170ms).
[11:16:18.357] <TB1> INFO: 5025280 events read in total (217322ms).
[11:16:18.436] <TB1> INFO: Test took 218271ms.
[11:16:45.176] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 57.5589 for pixel 3/0 mean/min/max = 45.3151/32.742/57.8882
[11:16:45.177] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 57.0644 for pixel 5/44 mean/min/max = 44.8576/32.5979/57.1174
[11:16:45.177] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 55.8237 for pixel 31/7 mean/min/max = 43.9988/32.1437/55.8539
[11:16:45.177] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 56.0932 for pixel 35/1 mean/min/max = 43.855/31.5788/56.1311
[11:16:45.178] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 59.2117 for pixel 9/57 mean/min/max = 45.8565/32.4456/59.2673
[11:16:45.178] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 57.1142 for pixel 42/44 mean/min/max = 45.956/34.7406/57.1714
[11:16:45.179] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 57.4045 for pixel 18/0 mean/min/max = 44.2687/30.903/57.6344
[11:16:45.179] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 62.5366 for pixel 34/5 mean/min/max = 47.6475/32.7011/62.5939
[11:16:45.179] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 56.5126 for pixel 0/77 mean/min/max = 44.284/32.016/56.5519
[11:16:45.180] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 66.746 for pixel 6/72 mean/min/max = 48.9664/31.1837/66.7492
[11:16:45.180] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 57.9316 for pixel 2/78 mean/min/max = 45.0439/31.7322/58.3557
[11:16:45.181] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 62.8294 for pixel 2/6 mean/min/max = 47.1129/31.3694/62.8565
[11:16:45.181] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 57.2579 for pixel 0/2 mean/min/max = 44.6719/31.9798/57.3639
[11:16:45.181] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 57.6055 for pixel 18/73 mean/min/max = 44.0479/30.445/57.6508
[11:16:45.182] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 58.0982 for pixel 24/79 mean/min/max = 46.4331/34.646/58.2202
[11:16:45.182] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 55.7831 for pixel 27/5 mean/min/max = 44.1529/32.1849/56.1208
[11:16:45.182] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:16:45.271] <TB1> INFO: Expecting 411648 events.
[11:16:54.682] <TB1> INFO: 411648 events read in total (8819ms).
[11:16:54.689] <TB1> INFO: Expecting 411648 events.
[11:17:03.806] <TB1> INFO: 411648 events read in total (8714ms).
[11:17:03.815] <TB1> INFO: Expecting 411648 events.
[11:17:12.896] <TB1> INFO: 411648 events read in total (8678ms).
[11:17:12.912] <TB1> INFO: Expecting 411648 events.
[11:17:22.035] <TB1> INFO: 411648 events read in total (8720ms).
[11:17:22.054] <TB1> INFO: Expecting 411648 events.
[11:17:31.090] <TB1> INFO: 411648 events read in total (8633ms).
[11:17:31.107] <TB1> INFO: Expecting 411648 events.
[11:17:40.191] <TB1> INFO: 411648 events read in total (8680ms).
[11:17:40.211] <TB1> INFO: Expecting 411648 events.
[11:17:49.253] <TB1> INFO: 411648 events read in total (8639ms).
[11:17:49.276] <TB1> INFO: Expecting 411648 events.
[11:17:58.314] <TB1> INFO: 411648 events read in total (8635ms).
[11:17:58.350] <TB1> INFO: Expecting 411648 events.
[11:18:07.430] <TB1> INFO: 411648 events read in total (8677ms).
[11:18:07.469] <TB1> INFO: Expecting 411648 events.
[11:18:16.483] <TB1> INFO: 411648 events read in total (8611ms).
[11:18:16.525] <TB1> INFO: Expecting 411648 events.
[11:18:25.478] <TB1> INFO: 411648 events read in total (8550ms).
[11:18:25.511] <TB1> INFO: Expecting 411648 events.
[11:18:34.570] <TB1> INFO: 411648 events read in total (8656ms).
[11:18:34.605] <TB1> INFO: Expecting 411648 events.
[11:18:43.622] <TB1> INFO: 411648 events read in total (8613ms).
[11:18:43.663] <TB1> INFO: Expecting 411648 events.
[11:18:52.633] <TB1> INFO: 411648 events read in total (8567ms).
[11:18:52.676] <TB1> INFO: Expecting 411648 events.
[11:19:01.755] <TB1> INFO: 411648 events read in total (8677ms).
[11:19:01.812] <TB1> INFO: Expecting 411648 events.
[11:19:10.887] <TB1> INFO: 411648 events read in total (8673ms).
[11:19:10.936] <TB1> INFO: Test took 145754ms.
[11:19:11.801] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[11:19:11.812] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:19:11.812] <TB1> INFO: run 1 of 1
[11:19:12.064] <TB1> INFO: Expecting 5025280 events.
[11:19:37.834] <TB1> INFO: 583544 events read in total (25179ms).
[11:20:03.067] <TB1> INFO: 1166776 events read in total (50412ms).
[11:20:28.334] <TB1> INFO: 1749352 events read in total (75679ms).
[11:20:53.696] <TB1> INFO: 2330592 events read in total (101041ms).
[11:21:18.961] <TB1> INFO: 2911384 events read in total (126306ms).
[11:21:44.288] <TB1> INFO: 3491880 events read in total (151633ms).
[11:22:09.665] <TB1> INFO: 4071560 events read in total (177010ms).
[11:22:35.016] <TB1> INFO: 4650376 events read in total (202361ms).
[11:22:51.620] <TB1> INFO: 5025280 events read in total (218965ms).
[11:22:51.717] <TB1> INFO: Test took 219906ms.
[11:23:16.859] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 3.500000 .. 140.827498
[11:23:17.126] <TB1> INFO: Expecting 208000 events.
[11:23:26.711] <TB1> INFO: 208000 events read in total (8993ms).
[11:23:26.712] <TB1> INFO: Test took 9852ms.
[11:23:26.769] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 3 .. 150 (-1/-1) hits flags = 528 (plus default)
[11:23:26.779] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:23:26.779] <TB1> INFO: run 1 of 1
[11:23:27.060] <TB1> INFO: Expecting 4925440 events.
[11:23:53.236] <TB1> INFO: 583824 events read in total (25585ms).
[11:24:18.519] <TB1> INFO: 1167248 events read in total (50868ms).
[11:24:43.767] <TB1> INFO: 1750792 events read in total (76116ms).
[11:25:09.170] <TB1> INFO: 2334392 events read in total (101519ms).
[11:25:34.127] <TB1> INFO: 2917080 events read in total (126476ms).
[11:25:59.311] <TB1> INFO: 3498480 events read in total (151660ms).
[11:26:24.537] <TB1> INFO: 4080136 events read in total (176886ms).
[11:26:49.446] <TB1> INFO: 4661224 events read in total (201795ms).
[11:27:01.287] <TB1> INFO: 4925440 events read in total (213636ms).
[11:27:01.347] <TB1> INFO: Test took 214569ms.
[11:27:27.327] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.852240 .. 43.922930
[11:27:27.562] <TB1> INFO: Expecting 208000 events.
[11:27:37.411] <TB1> INFO: 208000 events read in total (9258ms).
[11:27:37.411] <TB1> INFO: Test took 10082ms.
[11:27:37.459] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 53 (-1/-1) hits flags = 528 (plus default)
[11:27:37.469] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:27:37.469] <TB1> INFO: run 1 of 1
[11:27:37.747] <TB1> INFO: Expecting 1231360 events.
[11:28:05.688] <TB1> INFO: 666392 events read in total (27350ms).
[11:28:28.910] <TB1> INFO: 1231360 events read in total (50573ms).
[11:28:28.935] <TB1> INFO: Test took 51467ms.
[11:28:42.057] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 25.835401 .. 47.347807
[11:28:42.295] <TB1> INFO: Expecting 208000 events.
[11:28:51.889] <TB1> INFO: 208000 events read in total (9002ms).
[11:28:51.890] <TB1> INFO: Test took 9832ms.
[11:28:51.942] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 57 (-1/-1) hits flags = 528 (plus default)
[11:28:51.953] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:28:51.953] <TB1> INFO: run 1 of 1
[11:28:52.231] <TB1> INFO: Expecting 1431040 events.
[11:29:20.127] <TB1> INFO: 659072 events read in total (27305ms).
[11:29:47.367] <TB1> INFO: 1317512 events read in total (54545ms).
[11:29:52.429] <TB1> INFO: 1431040 events read in total (59607ms).
[11:29:52.453] <TB1> INFO: Test took 60500ms.
[11:30:06.995] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 24.487322 .. 45.730297
[11:30:07.229] <TB1> INFO: Expecting 208000 events.
[11:30:16.808] <TB1> INFO: 208000 events read in total (8988ms).
[11:30:16.809] <TB1> INFO: Test took 9813ms.
[11:30:16.855] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 55 (-1/-1) hits flags = 528 (plus default)
[11:30:16.863] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:30:16.863] <TB1> INFO: run 1 of 1
[11:30:17.141] <TB1> INFO: Expecting 1397760 events.
[11:30:45.004] <TB1> INFO: 671296 events read in total (27271ms).
[11:31:12.037] <TB1> INFO: 1341464 events read in total (54304ms).
[11:31:14.839] <TB1> INFO: 1397760 events read in total (57107ms).
[11:31:14.870] <TB1> INFO: Test took 58007ms.
[11:31:28.697] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[11:31:28.697] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[11:31:28.707] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:31:28.707] <TB1> INFO: run 1 of 1
[11:31:28.940] <TB1> INFO: Expecting 1364480 events.
[11:31:57.769] <TB1> INFO: 667344 events read in total (28238ms).
[11:32:25.180] <TB1> INFO: 1333784 events read in total (55649ms).
[11:32:26.976] <TB1> INFO: 1364480 events read in total (57445ms).
[11:32:27.004] <TB1> INFO: Test took 58297ms.
[11:32:40.559] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C0.dat
[11:32:40.559] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C1.dat
[11:32:40.559] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C2.dat
[11:32:40.559] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C3.dat
[11:32:40.559] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C4.dat
[11:32:40.559] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C5.dat
[11:32:40.559] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C6.dat
[11:32:40.559] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C7.dat
[11:32:40.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C8.dat
[11:32:40.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C9.dat
[11:32:40.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C10.dat
[11:32:40.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C11.dat
[11:32:40.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C12.dat
[11:32:40.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C13.dat
[11:32:40.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C14.dat
[11:32:40.560] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C15.dat
[11:32:40.560] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C0.dat
[11:32:40.566] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C1.dat
[11:32:40.572] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C2.dat
[11:32:40.577] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C3.dat
[11:32:40.583] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C4.dat
[11:32:40.588] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C5.dat
[11:32:40.594] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C6.dat
[11:32:40.599] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C7.dat
[11:32:40.605] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C8.dat
[11:32:40.610] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C9.dat
[11:32:40.616] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C10.dat
[11:32:40.622] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C11.dat
[11:32:40.628] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C12.dat
[11:32:40.635] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C13.dat
[11:32:40.641] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C14.dat
[11:32:40.648] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//trimParameters35_C15.dat
[11:32:40.655] <TB1> INFO: PixTestTrim::trimTest() done
[11:32:40.655] <TB1> INFO: vtrim: 132 137 143 134 146 139 157 187 123 182 115 152 137 132 143 121
[11:32:40.655] <TB1> INFO: vthrcomp: 112 125 116 118 116 108 124 131 124 129 124 129 121 126 110 120
[11:32:40.655] <TB1> INFO: vcal mean: 34.98 34.94 34.95 34.92 35.00 34.99 34.94 35.06 34.91 35.00 34.94 35.16 34.98 34.91 35.02 34.92
[11:32:40.655] <TB1> INFO: vcal RMS: 0.95 1.01 0.98 1.01 1.03 0.91 1.07 1.20 0.99 1.15 0.97 1.26 0.99 1.09 0.95 0.95
[11:32:40.655] <TB1> INFO: bits mean: 9.73 9.93 10.73 10.31 9.77 9.37 10.90 9.90 9.65 9.81 9.25 9.85 10.09 10.57 9.26 10.16
[11:32:40.655] <TB1> INFO: bits RMS: 2.53 2.45 2.17 2.47 2.56 2.35 2.24 2.33 2.73 2.38 2.88 2.58 2.44 2.48 2.40 2.45
[11:32:40.662] <TB1> INFO: ----------------------------------------------------------------------
[11:32:40.662] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[11:32:40.662] <TB1> INFO: ----------------------------------------------------------------------
[11:32:40.665] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[11:32:40.674] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:32:40.674] <TB1> INFO: run 1 of 1
[11:32:40.910] <TB1> INFO: Expecting 4160000 events.
[11:33:12.471] <TB1> INFO: 728610 events read in total (30969ms).
[11:33:43.095] <TB1> INFO: 1452990 events read in total (61593ms).
[11:34:13.699] <TB1> INFO: 2174970 events read in total (92197ms).
[11:34:44.434] <TB1> INFO: 2892360 events read in total (122932ms).
[11:35:14.867] <TB1> INFO: 3607730 events read in total (153365ms).
[11:35:38.674] <TB1> INFO: 4160000 events read in total (177172ms).
[11:35:38.728] <TB1> INFO: Test took 178054ms.
[11:36:06.463] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 201 (-1/-1) hits flags = 528 (plus default)
[11:36:06.473] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:36:06.473] <TB1> INFO: run 1 of 1
[11:36:06.721] <TB1> INFO: Expecting 4201600 events.
[11:36:37.717] <TB1> INFO: 703700 events read in total (30404ms).
[11:37:07.787] <TB1> INFO: 1403840 events read in total (60474ms).
[11:37:37.936] <TB1> INFO: 2102565 events read in total (90623ms).
[11:38:07.871] <TB1> INFO: 2796490 events read in total (120558ms).
[11:38:37.734] <TB1> INFO: 3490270 events read in total (150421ms).
[11:39:07.724] <TB1> INFO: 4184090 events read in total (180411ms).
[11:39:08.930] <TB1> INFO: 4201600 events read in total (181617ms).
[11:39:08.993] <TB1> INFO: Test took 182520ms.
[11:39:38.227] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 201 (-1/-1) hits flags = 528 (plus default)
[11:39:38.237] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:39:38.238] <TB1> INFO: run 1 of 1
[11:39:38.473] <TB1> INFO: Expecting 4201600 events.
[11:40:08.942] <TB1> INFO: 703935 events read in total (29878ms).
[11:40:38.854] <TB1> INFO: 1404510 events read in total (59790ms).
[11:41:08.934] <TB1> INFO: 2103425 events read in total (89870ms).
[11:41:38.844] <TB1> INFO: 2797475 events read in total (119780ms).
[11:42:08.706] <TB1> INFO: 3491385 events read in total (149642ms).
[11:42:38.793] <TB1> INFO: 4185380 events read in total (179730ms).
[11:42:39.861] <TB1> INFO: 4201600 events read in total (180797ms).
[11:42:39.930] <TB1> INFO: Test took 181692ms.
[11:43:09.200] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[11:43:09.210] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:43:09.210] <TB1> INFO: run 1 of 1
[11:43:09.443] <TB1> INFO: Expecting 4243200 events.
[11:43:40.389] <TB1> INFO: 701700 events read in total (30354ms).
[11:44:10.588] <TB1> INFO: 1400200 events read in total (60553ms).
[11:44:40.723] <TB1> INFO: 2096905 events read in total (90688ms).
[11:45:10.445] <TB1> INFO: 2789495 events read in total (120410ms).
[11:45:40.648] <TB1> INFO: 3481310 events read in total (150613ms).
[11:46:10.852] <TB1> INFO: 4172615 events read in total (180817ms).
[11:46:14.233] <TB1> INFO: 4243200 events read in total (184198ms).
[11:46:14.289] <TB1> INFO: Test took 185078ms.
[11:46:42.715] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 201 (-1/-1) hits flags = 528 (plus default)
[11:46:42.727] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:46:42.727] <TB1> INFO: run 1 of 1
[11:46:42.967] <TB1> INFO: Expecting 4201600 events.
[11:47:14.258] <TB1> INFO: 704200 events read in total (30700ms).
[11:47:44.384] <TB1> INFO: 1404945 events read in total (60826ms).
[11:48:14.557] <TB1> INFO: 2104135 events read in total (90999ms).
[11:48:44.689] <TB1> INFO: 2798585 events read in total (121131ms).
[11:49:14.660] <TB1> INFO: 3492935 events read in total (151102ms).
[11:49:45.135] <TB1> INFO: 4187375 events read in total (181577ms).
[11:49:46.198] <TB1> INFO: 4201600 events read in total (182640ms).
[11:49:46.253] <TB1> INFO: Test took 183525ms.
[11:50:13.536] <TB1> INFO: PixTestTrim::trimBitTest() done
[11:50:13.537] <TB1> INFO: PixTestTrim::doTest() done, duration: 2461 seconds
[11:50:13.537] <TB1> INFO: Decoding statistics:
[11:50:13.537] <TB1> INFO: General information:
[11:50:13.537] <TB1> INFO: 16bit words read: 0
[11:50:13.537] <TB1> INFO: valid events total: 0
[11:50:13.537] <TB1> INFO: empty events: 0
[11:50:13.537] <TB1> INFO: valid events with pixels: 0
[11:50:13.537] <TB1> INFO: valid pixel hits: 0
[11:50:13.537] <TB1> INFO: Event errors: 0
[11:50:13.537] <TB1> INFO: start marker: 0
[11:50:13.537] <TB1> INFO: stop marker: 0
[11:50:13.537] <TB1> INFO: overflow: 0
[11:50:13.537] <TB1> INFO: invalid 5bit words: 0
[11:50:13.537] <TB1> INFO: invalid XOR eye diagram: 0
[11:50:13.537] <TB1> INFO: frame (failed synchr.): 0
[11:50:13.537] <TB1> INFO: idle data (no TBM trl): 0
[11:50:13.537] <TB1> INFO: no data (only TBM hdr): 0
[11:50:13.537] <TB1> INFO: TBM errors: 0
[11:50:13.537] <TB1> INFO: flawed TBM headers: 0
[11:50:13.537] <TB1> INFO: flawed TBM trailers: 0
[11:50:13.538] <TB1> INFO: event ID mismatches: 0
[11:50:13.538] <TB1> INFO: ROC errors: 0
[11:50:13.538] <TB1> INFO: missing ROC header(s): 0
[11:50:13.538] <TB1> INFO: misplaced readback start: 0
[11:50:13.538] <TB1> INFO: Pixel decoding errors: 0
[11:50:13.538] <TB1> INFO: pixel data incomplete: 0
[11:50:13.538] <TB1> INFO: pixel address: 0
[11:50:13.538] <TB1> INFO: pulse height fill bit: 0
[11:50:13.538] <TB1> INFO: buffer corruption: 0
[11:50:14.182] <TB1> INFO: ######################################################################
[11:50:14.182] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[11:50:14.182] <TB1> INFO: ######################################################################
[11:50:14.416] <TB1> INFO: Expecting 41600 events.
[11:50:17.828] <TB1> INFO: 41600 events read in total (2820ms).
[11:50:17.829] <TB1> INFO: Test took 3645ms.
[11:50:18.265] <TB1> INFO: Expecting 41600 events.
[11:50:21.803] <TB1> INFO: 41600 events read in total (2946ms).
[11:50:21.804] <TB1> INFO: Test took 3772ms.
[11:50:22.092] <TB1> INFO: Expecting 41600 events.
[11:50:25.571] <TB1> INFO: 41600 events read in total (2887ms).
[11:50:25.571] <TB1> INFO: Test took 3744ms.
[11:50:25.860] <TB1> INFO: Expecting 41600 events.
[11:50:29.350] <TB1> INFO: 41600 events read in total (2899ms).
[11:50:29.350] <TB1> INFO: Test took 3755ms.
[11:50:29.648] <TB1> INFO: Expecting 41600 events.
[11:50:33.110] <TB1> INFO: 41600 events read in total (2870ms).
[11:50:33.111] <TB1> INFO: Test took 3738ms.
[11:50:33.409] <TB1> INFO: Expecting 41600 events.
[11:50:36.928] <TB1> INFO: 41600 events read in total (2928ms).
[11:50:36.929] <TB1> INFO: Test took 3795ms.
[11:50:37.219] <TB1> INFO: Expecting 41600 events.
[11:50:40.809] <TB1> INFO: 41600 events read in total (2999ms).
[11:50:40.810] <TB1> INFO: Test took 3856ms.
[11:50:41.097] <TB1> INFO: Expecting 41600 events.
[11:50:44.602] <TB1> INFO: 41600 events read in total (2913ms).
[11:50:44.603] <TB1> INFO: Test took 3760ms.
[11:50:44.891] <TB1> INFO: Expecting 41600 events.
[11:50:48.333] <TB1> INFO: 41600 events read in total (2851ms).
[11:50:48.334] <TB1> INFO: Test took 3708ms.
[11:50:48.622] <TB1> INFO: Expecting 41600 events.
[11:50:52.265] <TB1> INFO: 41600 events read in total (3051ms).
[11:50:52.266] <TB1> INFO: Test took 3909ms.
[11:50:52.554] <TB1> INFO: Expecting 41600 events.
[11:50:56.079] <TB1> INFO: 41600 events read in total (2934ms).
[11:50:56.079] <TB1> INFO: Test took 3790ms.
[11:50:56.367] <TB1> INFO: Expecting 41600 events.
[11:50:59.868] <TB1> INFO: 41600 events read in total (2909ms).
[11:50:59.869] <TB1> INFO: Test took 3766ms.
[11:51:00.157] <TB1> INFO: Expecting 41600 events.
[11:51:03.669] <TB1> INFO: 41600 events read in total (2920ms).
[11:51:03.670] <TB1> INFO: Test took 3778ms.
[11:51:03.961] <TB1> INFO: Expecting 41600 events.
[11:51:07.426] <TB1> INFO: 41600 events read in total (2873ms).
[11:51:07.426] <TB1> INFO: Test took 3730ms.
[11:51:07.714] <TB1> INFO: Expecting 41600 events.
[11:51:11.200] <TB1> INFO: 41600 events read in total (2894ms).
[11:51:11.200] <TB1> INFO: Test took 3751ms.
[11:51:11.488] <TB1> INFO: Expecting 41600 events.
[11:51:14.912] <TB1> INFO: 41600 events read in total (2832ms).
[11:51:14.912] <TB1> INFO: Test took 3689ms.
[11:51:15.200] <TB1> INFO: Expecting 41600 events.
[11:51:18.764] <TB1> INFO: 41600 events read in total (2972ms).
[11:51:18.765] <TB1> INFO: Test took 3829ms.
[11:51:19.053] <TB1> INFO: Expecting 41600 events.
[11:51:22.608] <TB1> INFO: 41600 events read in total (2964ms).
[11:51:22.609] <TB1> INFO: Test took 3821ms.
[11:51:22.897] <TB1> INFO: Expecting 41600 events.
[11:51:26.355] <TB1> INFO: 41600 events read in total (2866ms).
[11:51:26.355] <TB1> INFO: Test took 3723ms.
[11:51:26.643] <TB1> INFO: Expecting 41600 events.
[11:51:30.142] <TB1> INFO: 41600 events read in total (2907ms).
[11:51:30.143] <TB1> INFO: Test took 3764ms.
[11:51:30.431] <TB1> INFO: Expecting 41600 events.
[11:51:33.986] <TB1> INFO: 41600 events read in total (2963ms).
[11:51:33.987] <TB1> INFO: Test took 3820ms.
[11:51:34.275] <TB1> INFO: Expecting 41600 events.
[11:51:37.794] <TB1> INFO: 41600 events read in total (2928ms).
[11:51:37.795] <TB1> INFO: Test took 3785ms.
[11:51:38.085] <TB1> INFO: Expecting 41600 events.
[11:51:41.568] <TB1> INFO: 41600 events read in total (2891ms).
[11:51:41.569] <TB1> INFO: Test took 3751ms.
[11:51:41.857] <TB1> INFO: Expecting 41600 events.
[11:51:45.370] <TB1> INFO: 41600 events read in total (2922ms).
[11:51:45.371] <TB1> INFO: Test took 3779ms.
[11:51:45.659] <TB1> INFO: Expecting 41600 events.
[11:51:49.132] <TB1> INFO: 41600 events read in total (2881ms).
[11:51:49.132] <TB1> INFO: Test took 3737ms.
[11:51:49.420] <TB1> INFO: Expecting 41600 events.
[11:51:52.001] <TB1> INFO: 41600 events read in total (2989ms).
[11:51:52.002] <TB1> INFO: Test took 3846ms.
[11:51:53.290] <TB1> INFO: Expecting 41600 events.
[11:51:56.730] <TB1> INFO: 41600 events read in total (2848ms).
[11:51:56.731] <TB1> INFO: Test took 3706ms.
[11:51:57.019] <TB1> INFO: Expecting 41600 events.
[11:52:00.463] <TB1> INFO: 41600 events read in total (2852ms).
[11:52:00.464] <TB1> INFO: Test took 3709ms.
[11:52:00.754] <TB1> INFO: Expecting 41600 events.
[11:52:04.351] <TB1> INFO: 41600 events read in total (3006ms).
[11:52:04.352] <TB1> INFO: Test took 3863ms.
[11:52:04.643] <TB1> INFO: Expecting 2560 events.
[11:52:05.529] <TB1> INFO: 2560 events read in total (294ms).
[11:52:05.529] <TB1> INFO: Test took 1162ms.
[11:52:05.837] <TB1> INFO: Expecting 2560 events.
[11:52:06.722] <TB1> INFO: 2560 events read in total (293ms).
[11:52:06.722] <TB1> INFO: Test took 1193ms.
[11:52:07.030] <TB1> INFO: Expecting 2560 events.
[11:52:07.911] <TB1> INFO: 2560 events read in total (289ms).
[11:52:07.912] <TB1> INFO: Test took 1189ms.
[11:52:08.219] <TB1> INFO: Expecting 2560 events.
[11:52:09.100] <TB1> INFO: 2560 events read in total (289ms).
[11:52:09.101] <TB1> INFO: Test took 1189ms.
[11:52:09.409] <TB1> INFO: Expecting 2560 events.
[11:52:10.287] <TB1> INFO: 2560 events read in total (287ms).
[11:52:10.287] <TB1> INFO: Test took 1186ms.
[11:52:10.595] <TB1> INFO: Expecting 2560 events.
[11:52:11.476] <TB1> INFO: 2560 events read in total (289ms).
[11:52:11.476] <TB1> INFO: Test took 1188ms.
[11:52:11.784] <TB1> INFO: Expecting 2560 events.
[11:52:12.665] <TB1> INFO: 2560 events read in total (290ms).
[11:52:12.665] <TB1> INFO: Test took 1189ms.
[11:52:12.973] <TB1> INFO: Expecting 2560 events.
[11:52:13.853] <TB1> INFO: 2560 events read in total (288ms).
[11:52:13.853] <TB1> INFO: Test took 1187ms.
[11:52:14.161] <TB1> INFO: Expecting 2560 events.
[11:52:15.040] <TB1> INFO: 2560 events read in total (287ms).
[11:52:15.040] <TB1> INFO: Test took 1187ms.
[11:52:15.348] <TB1> INFO: Expecting 2560 events.
[11:52:16.227] <TB1> INFO: 2560 events read in total (287ms).
[11:52:16.227] <TB1> INFO: Test took 1186ms.
[11:52:16.535] <TB1> INFO: Expecting 2560 events.
[11:52:17.414] <TB1> INFO: 2560 events read in total (287ms).
[11:52:17.415] <TB1> INFO: Test took 1187ms.
[11:52:17.722] <TB1> INFO: Expecting 2560 events.
[11:52:18.601] <TB1> INFO: 2560 events read in total (287ms).
[11:52:18.601] <TB1> INFO: Test took 1186ms.
[11:52:18.909] <TB1> INFO: Expecting 2560 events.
[11:52:19.792] <TB1> INFO: 2560 events read in total (292ms).
[11:52:19.793] <TB1> INFO: Test took 1191ms.
[11:52:20.100] <TB1> INFO: Expecting 2560 events.
[11:52:20.985] <TB1> INFO: 2560 events read in total (293ms).
[11:52:20.985] <TB1> INFO: Test took 1192ms.
[11:52:21.293] <TB1> INFO: Expecting 2560 events.
[11:52:22.176] <TB1> INFO: 2560 events read in total (291ms).
[11:52:22.176] <TB1> INFO: Test took 1190ms.
[11:52:22.485] <TB1> INFO: Expecting 2560 events.
[11:52:23.367] <TB1> INFO: 2560 events read in total (291ms).
[11:52:23.367] <TB1> INFO: Test took 1190ms.
[11:52:23.370] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:52:23.675] <TB1> INFO: Expecting 655360 events.
[11:52:38.090] <TB1> INFO: 655360 events read in total (13823ms).
[11:52:38.100] <TB1> INFO: Expecting 655360 events.
[11:52:52.318] <TB1> INFO: 655360 events read in total (13816ms).
[11:52:52.333] <TB1> INFO: Expecting 655360 events.
[11:53:06.432] <TB1> INFO: 655360 events read in total (13696ms).
[11:53:06.451] <TB1> INFO: Expecting 655360 events.
[11:53:20.563] <TB1> INFO: 655360 events read in total (13709ms).
[11:53:20.585] <TB1> INFO: Expecting 655360 events.
[11:53:34.587] <TB1> INFO: 655360 events read in total (13599ms).
[11:53:34.613] <TB1> INFO: Expecting 655360 events.
[11:53:48.698] <TB1> INFO: 655360 events read in total (13682ms).
[11:53:48.739] <TB1> INFO: Expecting 655360 events.
[11:54:02.838] <TB1> INFO: 655360 events read in total (13696ms).
[11:54:02.876] <TB1> INFO: Expecting 655360 events.
[11:54:16.916] <TB1> INFO: 655360 events read in total (13638ms).
[11:54:16.968] <TB1> INFO: Expecting 655360 events.
[11:54:31.038] <TB1> INFO: 655360 events read in total (13668ms).
[11:54:31.106] <TB1> INFO: Expecting 655360 events.
[11:54:45.284] <TB1> INFO: 655360 events read in total (13775ms).
[11:54:45.353] <TB1> INFO: Expecting 655360 events.
[11:54:59.313] <TB1> INFO: 655360 events read in total (13557ms).
[11:54:59.366] <TB1> INFO: Expecting 655360 events.
[11:55:13.423] <TB1> INFO: 655360 events read in total (13654ms).
[11:55:13.494] <TB1> INFO: Expecting 655360 events.
[11:55:27.529] <TB1> INFO: 655360 events read in total (13632ms).
[11:55:27.612] <TB1> INFO: Expecting 655360 events.
[11:55:41.602] <TB1> INFO: 655360 events read in total (13587ms).
[11:55:41.667] <TB1> INFO: Expecting 655360 events.
[11:55:55.741] <TB1> INFO: 655360 events read in total (13671ms).
[11:55:55.810] <TB1> INFO: Expecting 655360 events.
[11:56:09.839] <TB1> INFO: 655360 events read in total (13626ms).
[11:56:09.938] <TB1> INFO: Test took 226569ms.
[11:56:10.034] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:56:10.299] <TB1> INFO: Expecting 655360 events.
[11:56:24.355] <TB1> INFO: 655360 events read in total (13465ms).
[11:56:24.365] <TB1> INFO: Expecting 655360 events.
[11:56:38.338] <TB1> INFO: 655360 events read in total (13570ms).
[11:56:38.352] <TB1> INFO: Expecting 655360 events.
[11:56:52.388] <TB1> INFO: 655360 events read in total (13633ms).
[11:56:52.407] <TB1> INFO: Expecting 655360 events.
[11:57:06.422] <TB1> INFO: 655360 events read in total (13612ms).
[11:57:06.444] <TB1> INFO: Expecting 655360 events.
[11:57:20.372] <TB1> INFO: 655360 events read in total (13525ms).
[11:57:20.398] <TB1> INFO: Expecting 655360 events.
[11:57:34.362] <TB1> INFO: 655360 events read in total (13561ms).
[11:57:34.393] <TB1> INFO: Expecting 655360 events.
[11:57:48.206] <TB1> INFO: 655360 events read in total (13410ms).
[11:57:48.241] <TB1> INFO: Expecting 655360 events.
[11:58:02.118] <TB1> INFO: 655360 events read in total (13474ms).
[11:58:02.156] <TB1> INFO: Expecting 655360 events.
[11:58:16.152] <TB1> INFO: 655360 events read in total (13593ms).
[11:58:16.196] <TB1> INFO: Expecting 655360 events.
[11:58:30.254] <TB1> INFO: 655360 events read in total (13655ms).
[11:58:30.304] <TB1> INFO: Expecting 655360 events.
[11:58:44.279] <TB1> INFO: 655360 events read in total (13572ms).
[11:58:44.333] <TB1> INFO: Expecting 655360 events.
[11:58:58.322] <TB1> INFO: 655360 events read in total (13586ms).
[11:58:58.399] <TB1> INFO: Expecting 655360 events.
[11:59:12.439] <TB1> INFO: 655360 events read in total (13637ms).
[11:59:12.501] <TB1> INFO: Expecting 655360 events.
[11:59:26.619] <TB1> INFO: 655360 events read in total (13715ms).
[11:59:26.712] <TB1> INFO: Expecting 655360 events.
[11:59:40.726] <TB1> INFO: 655360 events read in total (13612ms).
[11:59:40.797] <TB1> INFO: Expecting 655360 events.
[11:59:54.842] <TB1> INFO: 655360 events read in total (13642ms).
[11:59:54.923] <TB1> INFO: Test took 224889ms.
[11:59:55.101] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.106] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:59:55.111] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:59:55.115] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.119] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:59:55.124] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:59:55.128] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.133] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.138] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.143] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.148] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:59:55.153] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.157] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.162] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.167] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.172] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.176] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.181] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.186] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.191] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.197] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:59:55.233] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C0.dat
[11:59:55.233] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C1.dat
[11:59:55.233] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C2.dat
[11:59:55.233] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C3.dat
[11:59:55.233] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C4.dat
[11:59:55.233] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C5.dat
[11:59:55.233] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C6.dat
[11:59:55.233] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C7.dat
[11:59:55.233] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C8.dat
[11:59:55.233] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C9.dat
[11:59:55.233] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C10.dat
[11:59:55.234] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C11.dat
[11:59:55.234] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C12.dat
[11:59:55.234] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C13.dat
[11:59:55.234] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C14.dat
[11:59:55.234] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//dacParameters35_C15.dat
[11:59:55.472] <TB1> INFO: Expecting 41600 events.
[11:59:58.571] <TB1> INFO: 41600 events read in total (2508ms).
[11:59:58.572] <TB1> INFO: Test took 3336ms.
[11:59:59.055] <TB1> INFO: Expecting 41600 events.
[12:00:02.076] <TB1> INFO: 41600 events read in total (2429ms).
[12:00:02.076] <TB1> INFO: Test took 3292ms.
[12:00:02.522] <TB1> INFO: Expecting 41600 events.
[12:00:05.594] <TB1> INFO: 41600 events read in total (2480ms).
[12:00:05.595] <TB1> INFO: Test took 3306ms.
[12:00:05.808] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:05.897] <TB1> INFO: Expecting 2560 events.
[12:00:06.777] <TB1> INFO: 2560 events read in total (289ms).
[12:00:06.778] <TB1> INFO: Test took 970ms.
[12:00:06.779] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:07.086] <TB1> INFO: Expecting 2560 events.
[12:00:07.969] <TB1> INFO: 2560 events read in total (291ms).
[12:00:07.969] <TB1> INFO: Test took 1190ms.
[12:00:07.971] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:08.278] <TB1> INFO: Expecting 2560 events.
[12:00:09.163] <TB1> INFO: 2560 events read in total (294ms).
[12:00:09.163] <TB1> INFO: Test took 1192ms.
[12:00:09.165] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:09.472] <TB1> INFO: Expecting 2560 events.
[12:00:10.353] <TB1> INFO: 2560 events read in total (290ms).
[12:00:10.353] <TB1> INFO: Test took 1188ms.
[12:00:10.355] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:10.661] <TB1> INFO: Expecting 2560 events.
[12:00:11.544] <TB1> INFO: 2560 events read in total (291ms).
[12:00:11.544] <TB1> INFO: Test took 1189ms.
[12:00:11.546] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:11.852] <TB1> INFO: Expecting 2560 events.
[12:00:12.735] <TB1> INFO: 2560 events read in total (291ms).
[12:00:12.736] <TB1> INFO: Test took 1190ms.
[12:00:12.737] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:13.044] <TB1> INFO: Expecting 2560 events.
[12:00:13.929] <TB1> INFO: 2560 events read in total (293ms).
[12:00:13.929] <TB1> INFO: Test took 1192ms.
[12:00:13.931] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:14.238] <TB1> INFO: Expecting 2560 events.
[12:00:15.124] <TB1> INFO: 2560 events read in total (295ms).
[12:00:15.124] <TB1> INFO: Test took 1193ms.
[12:00:15.126] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:15.433] <TB1> INFO: Expecting 2560 events.
[12:00:16.311] <TB1> INFO: 2560 events read in total (287ms).
[12:00:16.311] <TB1> INFO: Test took 1185ms.
[12:00:16.313] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:16.619] <TB1> INFO: Expecting 2560 events.
[12:00:17.497] <TB1> INFO: 2560 events read in total (286ms).
[12:00:17.498] <TB1> INFO: Test took 1185ms.
[12:00:17.500] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:17.806] <TB1> INFO: Expecting 2560 events.
[12:00:18.684] <TB1> INFO: 2560 events read in total (286ms).
[12:00:18.684] <TB1> INFO: Test took 1185ms.
[12:00:18.686] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:18.992] <TB1> INFO: Expecting 2560 events.
[12:00:19.871] <TB1> INFO: 2560 events read in total (287ms).
[12:00:19.871] <TB1> INFO: Test took 1185ms.
[12:00:19.873] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:20.179] <TB1> INFO: Expecting 2560 events.
[12:00:21.057] <TB1> INFO: 2560 events read in total (286ms).
[12:00:21.058] <TB1> INFO: Test took 1185ms.
[12:00:21.059] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:21.366] <TB1> INFO: Expecting 2560 events.
[12:00:22.246] <TB1> INFO: 2560 events read in total (289ms).
[12:00:22.246] <TB1> INFO: Test took 1187ms.
[12:00:22.248] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:22.554] <TB1> INFO: Expecting 2560 events.
[12:00:23.432] <TB1> INFO: 2560 events read in total (286ms).
[12:00:23.432] <TB1> INFO: Test took 1184ms.
[12:00:23.434] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:23.740] <TB1> INFO: Expecting 2560 events.
[12:00:24.618] <TB1> INFO: 2560 events read in total (286ms).
[12:00:24.618] <TB1> INFO: Test took 1184ms.
[12:00:24.620] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:24.926] <TB1> INFO: Expecting 2560 events.
[12:00:25.804] <TB1> INFO: 2560 events read in total (286ms).
[12:00:25.805] <TB1> INFO: Test took 1185ms.
[12:00:25.807] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:26.113] <TB1> INFO: Expecting 2560 events.
[12:00:26.993] <TB1> INFO: 2560 events read in total (288ms).
[12:00:26.993] <TB1> INFO: Test took 1186ms.
[12:00:26.995] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:27.302] <TB1> INFO: Expecting 2560 events.
[12:00:28.181] <TB1> INFO: 2560 events read in total (288ms).
[12:00:28.181] <TB1> INFO: Test took 1186ms.
[12:00:28.183] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:28.489] <TB1> INFO: Expecting 2560 events.
[12:00:29.368] <TB1> INFO: 2560 events read in total (287ms).
[12:00:29.368] <TB1> INFO: Test took 1185ms.
[12:00:29.370] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:29.676] <TB1> INFO: Expecting 2560 events.
[12:00:30.555] <TB1> INFO: 2560 events read in total (287ms).
[12:00:30.555] <TB1> INFO: Test took 1185ms.
[12:00:30.557] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:30.863] <TB1> INFO: Expecting 2560 events.
[12:00:31.742] <TB1> INFO: 2560 events read in total (287ms).
[12:00:31.742] <TB1> INFO: Test took 1185ms.
[12:00:31.744] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:32.050] <TB1> INFO: Expecting 2560 events.
[12:00:32.928] <TB1> INFO: 2560 events read in total (286ms).
[12:00:32.928] <TB1> INFO: Test took 1184ms.
[12:00:32.931] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:33.236] <TB1> INFO: Expecting 2560 events.
[12:00:34.115] <TB1> INFO: 2560 events read in total (287ms).
[12:00:34.115] <TB1> INFO: Test took 1184ms.
[12:00:34.118] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:34.424] <TB1> INFO: Expecting 2560 events.
[12:00:35.307] <TB1> INFO: 2560 events read in total (292ms).
[12:00:35.307] <TB1> INFO: Test took 1189ms.
[12:00:35.309] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:35.615] <TB1> INFO: Expecting 2560 events.
[12:00:36.499] <TB1> INFO: 2560 events read in total (292ms).
[12:00:36.500] <TB1> INFO: Test took 1192ms.
[12:00:36.502] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:36.808] <TB1> INFO: Expecting 2560 events.
[12:00:37.697] <TB1> INFO: 2560 events read in total (297ms).
[12:00:37.697] <TB1> INFO: Test took 1195ms.
[12:00:37.699] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:38.006] <TB1> INFO: Expecting 2560 events.
[12:00:38.890] <TB1> INFO: 2560 events read in total (293ms).
[12:00:38.890] <TB1> INFO: Test took 1191ms.
[12:00:38.892] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:39.199] <TB1> INFO: Expecting 2560 events.
[12:00:40.081] <TB1> INFO: 2560 events read in total (291ms).
[12:00:40.081] <TB1> INFO: Test took 1189ms.
[12:00:40.083] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:40.389] <TB1> INFO: Expecting 2560 events.
[12:00:41.271] <TB1> INFO: 2560 events read in total (290ms).
[12:00:41.272] <TB1> INFO: Test took 1189ms.
[12:00:41.273] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:41.580] <TB1> INFO: Expecting 2560 events.
[12:00:42.467] <TB1> INFO: 2560 events read in total (295ms).
[12:00:42.467] <TB1> INFO: Test took 1194ms.
[12:00:42.469] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:00:42.775] <TB1> INFO: Expecting 2560 events.
[12:00:43.657] <TB1> INFO: 2560 events read in total (290ms).
[12:00:43.657] <TB1> INFO: Test took 1188ms.
[12:00:44.119] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 629 seconds
[12:00:44.119] <TB1> INFO: PH scale (per ROC): 68 49 66 43 57 58 50 48 54 49 63 61 53 49 51 62
[12:00:44.119] <TB1> INFO: PH offset (per ROC): 123 107 125 101 113 121 108 111 98 103 126 128 109 97 103 129
[12:00:44.124] <TB1> INFO: Decoding statistics:
[12:00:44.124] <TB1> INFO: General information:
[12:00:44.124] <TB1> INFO: 16bit words read: 127880
[12:00:44.124] <TB1> INFO: valid events total: 20480
[12:00:44.124] <TB1> INFO: empty events: 17980
[12:00:44.124] <TB1> INFO: valid events with pixels: 2500
[12:00:44.124] <TB1> INFO: valid pixel hits: 2500
[12:00:44.124] <TB1> INFO: Event errors: 0
[12:00:44.124] <TB1> INFO: start marker: 0
[12:00:44.124] <TB1> INFO: stop marker: 0
[12:00:44.124] <TB1> INFO: overflow: 0
[12:00:44.124] <TB1> INFO: invalid 5bit words: 0
[12:00:44.124] <TB1> INFO: invalid XOR eye diagram: 0
[12:00:44.124] <TB1> INFO: frame (failed synchr.): 0
[12:00:44.124] <TB1> INFO: idle data (no TBM trl): 0
[12:00:44.124] <TB1> INFO: no data (only TBM hdr): 0
[12:00:44.124] <TB1> INFO: TBM errors: 0
[12:00:44.124] <TB1> INFO: flawed TBM headers: 0
[12:00:44.124] <TB1> INFO: flawed TBM trailers: 0
[12:00:44.124] <TB1> INFO: event ID mismatches: 0
[12:00:44.124] <TB1> INFO: ROC errors: 0
[12:00:44.124] <TB1> INFO: missing ROC header(s): 0
[12:00:44.124] <TB1> INFO: misplaced readback start: 0
[12:00:44.124] <TB1> INFO: Pixel decoding errors: 0
[12:00:44.124] <TB1> INFO: pixel data incomplete: 0
[12:00:44.124] <TB1> INFO: pixel address: 0
[12:00:44.124] <TB1> INFO: pulse height fill bit: 0
[12:00:44.124] <TB1> INFO: buffer corruption: 0
[12:00:44.386] <TB1> INFO: ######################################################################
[12:00:44.386] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[12:00:44.386] <TB1> INFO: ######################################################################
[12:00:44.399] <TB1> INFO: scanning low vcal = 10
[12:00:44.659] <TB1> INFO: Expecting 41600 events.
[12:00:48.202] <TB1> INFO: 41600 events read in total (2951ms).
[12:00:48.202] <TB1> INFO: Test took 3803ms.
[12:00:48.204] <TB1> INFO: scanning low vcal = 20
[12:00:48.503] <TB1> INFO: Expecting 41600 events.
[12:00:52.064] <TB1> INFO: 41600 events read in total (2970ms).
[12:00:52.064] <TB1> INFO: Test took 3860ms.
[12:00:52.066] <TB1> INFO: scanning low vcal = 30
[12:00:52.365] <TB1> INFO: Expecting 41600 events.
[12:00:55.978] <TB1> INFO: 41600 events read in total (3022ms).
[12:00:55.978] <TB1> INFO: Test took 3912ms.
[12:00:55.981] <TB1> INFO: scanning low vcal = 40
[12:00:56.259] <TB1> INFO: Expecting 41600 events.
[12:01:00.205] <TB1> INFO: 41600 events read in total (3355ms).
[12:01:00.206] <TB1> INFO: Test took 4226ms.
[12:01:00.209] <TB1> INFO: scanning low vcal = 50
[12:01:00.486] <TB1> INFO: Expecting 41600 events.
[12:01:04.431] <TB1> INFO: 41600 events read in total (3353ms).
[12:01:04.431] <TB1> INFO: Test took 4222ms.
[12:01:04.434] <TB1> INFO: scanning low vcal = 60
[12:01:04.711] <TB1> INFO: Expecting 41600 events.
[12:01:08.674] <TB1> INFO: 41600 events read in total (3372ms).
[12:01:08.675] <TB1> INFO: Test took 4241ms.
[12:01:08.677] <TB1> INFO: scanning low vcal = 70
[12:01:08.954] <TB1> INFO: Expecting 41600 events.
[12:01:12.915] <TB1> INFO: 41600 events read in total (3369ms).
[12:01:12.916] <TB1> INFO: Test took 4239ms.
[12:01:12.918] <TB1> INFO: scanning low vcal = 80
[12:01:13.195] <TB1> INFO: Expecting 41600 events.
[12:01:17.181] <TB1> INFO: 41600 events read in total (3394ms).
[12:01:17.182] <TB1> INFO: Test took 4263ms.
[12:01:17.184] <TB1> INFO: scanning low vcal = 90
[12:01:17.461] <TB1> INFO: Expecting 41600 events.
[12:01:21.433] <TB1> INFO: 41600 events read in total (3380ms).
[12:01:21.433] <TB1> INFO: Test took 4248ms.
[12:01:21.436] <TB1> INFO: scanning low vcal = 100
[12:01:21.713] <TB1> INFO: Expecting 41600 events.
[12:01:25.664] <TB1> INFO: 41600 events read in total (3360ms).
[12:01:25.665] <TB1> INFO: Test took 4229ms.
[12:01:25.667] <TB1> INFO: scanning low vcal = 110
[12:01:25.944] <TB1> INFO: Expecting 41600 events.
[12:01:29.903] <TB1> INFO: 41600 events read in total (3368ms).
[12:01:29.904] <TB1> INFO: Test took 4237ms.
[12:01:29.907] <TB1> INFO: scanning low vcal = 120
[12:01:30.183] <TB1> INFO: Expecting 41600 events.
[12:01:34.128] <TB1> INFO: 41600 events read in total (3353ms).
[12:01:34.129] <TB1> INFO: Test took 4222ms.
[12:01:34.131] <TB1> INFO: scanning low vcal = 130
[12:01:34.408] <TB1> INFO: Expecting 41600 events.
[12:01:38.342] <TB1> INFO: 41600 events read in total (3343ms).
[12:01:38.343] <TB1> INFO: Test took 4211ms.
[12:01:38.346] <TB1> INFO: scanning low vcal = 140
[12:01:38.623] <TB1> INFO: Expecting 41600 events.
[12:01:42.570] <TB1> INFO: 41600 events read in total (3356ms).
[12:01:42.571] <TB1> INFO: Test took 4225ms.
[12:01:42.574] <TB1> INFO: scanning low vcal = 150
[12:01:42.850] <TB1> INFO: Expecting 41600 events.
[12:01:46.801] <TB1> INFO: 41600 events read in total (3359ms).
[12:01:46.802] <TB1> INFO: Test took 4228ms.
[12:01:46.805] <TB1> INFO: scanning low vcal = 160
[12:01:47.082] <TB1> INFO: Expecting 41600 events.
[12:01:51.026] <TB1> INFO: 41600 events read in total (3352ms).
[12:01:51.027] <TB1> INFO: Test took 4222ms.
[12:01:51.029] <TB1> INFO: scanning low vcal = 170
[12:01:51.306] <TB1> INFO: Expecting 41600 events.
[12:01:55.241] <TB1> INFO: 41600 events read in total (3344ms).
[12:01:55.241] <TB1> INFO: Test took 4212ms.
[12:01:55.244] <TB1> INFO: scanning low vcal = 180
[12:01:55.520] <TB1> INFO: Expecting 41600 events.
[12:01:59.516] <TB1> INFO: 41600 events read in total (3404ms).
[12:01:59.517] <TB1> INFO: Test took 4273ms.
[12:01:59.520] <TB1> INFO: scanning low vcal = 190
[12:01:59.841] <TB1> INFO: Expecting 41600 events.
[12:02:03.786] <TB1> INFO: 41600 events read in total (3354ms).
[12:02:03.787] <TB1> INFO: Test took 4267ms.
[12:02:03.789] <TB1> INFO: scanning low vcal = 200
[12:02:04.066] <TB1> INFO: Expecting 41600 events.
[12:02:08.055] <TB1> INFO: 41600 events read in total (3398ms).
[12:02:08.056] <TB1> INFO: Test took 4267ms.
[12:02:08.059] <TB1> INFO: scanning low vcal = 210
[12:02:08.351] <TB1> INFO: Expecting 41600 events.
[12:02:12.302] <TB1> INFO: 41600 events read in total (3359ms).
[12:02:12.303] <TB1> INFO: Test took 4244ms.
[12:02:12.305] <TB1> INFO: scanning low vcal = 220
[12:02:12.582] <TB1> INFO: Expecting 41600 events.
[12:02:16.593] <TB1> INFO: 41600 events read in total (3420ms).
[12:02:16.594] <TB1> INFO: Test took 4289ms.
[12:02:16.597] <TB1> INFO: scanning low vcal = 230
[12:02:16.873] <TB1> INFO: Expecting 41600 events.
[12:02:20.815] <TB1> INFO: 41600 events read in total (3350ms).
[12:02:20.815] <TB1> INFO: Test took 4218ms.
[12:02:20.818] <TB1> INFO: scanning low vcal = 240
[12:02:21.095] <TB1> INFO: Expecting 41600 events.
[12:02:25.105] <TB1> INFO: 41600 events read in total (3419ms).
[12:02:25.106] <TB1> INFO: Test took 4288ms.
[12:02:25.109] <TB1> INFO: scanning low vcal = 250
[12:02:25.400] <TB1> INFO: Expecting 41600 events.
[12:02:29.366] <TB1> INFO: 41600 events read in total (3374ms).
[12:02:29.366] <TB1> INFO: Test took 4257ms.
[12:02:29.370] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[12:02:29.646] <TB1> INFO: Expecting 41600 events.
[12:02:33.641] <TB1> INFO: 41600 events read in total (3404ms).
[12:02:33.642] <TB1> INFO: Test took 4272ms.
[12:02:33.645] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[12:02:33.921] <TB1> INFO: Expecting 41600 events.
[12:02:37.933] <TB1> INFO: 41600 events read in total (3420ms).
[12:02:37.934] <TB1> INFO: Test took 4289ms.
[12:02:37.936] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[12:02:38.213] <TB1> INFO: Expecting 41600 events.
[12:02:42.207] <TB1> INFO: 41600 events read in total (3403ms).
[12:02:42.208] <TB1> INFO: Test took 4272ms.
[12:02:42.211] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[12:02:42.503] <TB1> INFO: Expecting 41600 events.
[12:02:46.458] <TB1> INFO: 41600 events read in total (3364ms).
[12:02:46.458] <TB1> INFO: Test took 4248ms.
[12:02:46.461] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:02:46.738] <TB1> INFO: Expecting 41600 events.
[12:02:50.746] <TB1> INFO: 41600 events read in total (3417ms).
[12:02:50.747] <TB1> INFO: Test took 4286ms.
[12:02:51.194] <TB1> INFO: PixTestGainPedestal::measure() done
[12:03:23.021] <TB1> INFO: PixTestGainPedestal::fit() done
[12:03:23.021] <TB1> INFO: non-linearity mean: 0.981 0.944 0.981 0.893 0.980 0.973 0.927 0.926 0.945 0.928 0.980 0.985 0.931 0.910 0.952 0.980
[12:03:23.021] <TB1> INFO: non-linearity RMS: 0.004 0.058 0.005 0.103 0.003 0.003 0.085 0.090 0.057 0.113 0.004 0.002 0.113 0.097 0.023 0.004
[12:03:23.021] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[12:03:23.043] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[12:03:23.066] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[12:03:23.088] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[12:03:23.110] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[12:03:23.132] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[12:03:23.154] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[12:03:23.176] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[12:03:23.198] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[12:03:23.221] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[12:03:23.243] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[12:03:23.266] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[12:03:23.288] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[12:03:23.310] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[12:03:23.333] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[12:03:23.354] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[12:03:23.376] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 158 seconds
[12:03:23.376] <TB1> INFO: Decoding statistics:
[12:03:23.376] <TB1> INFO: General information:
[12:03:23.376] <TB1> INFO: 16bit words read: 3327930
[12:03:23.376] <TB1> INFO: valid events total: 332800
[12:03:23.376] <TB1> INFO: empty events: 0
[12:03:23.376] <TB1> INFO: valid events with pixels: 332800
[12:03:23.376] <TB1> INFO: valid pixel hits: 665565
[12:03:23.376] <TB1> INFO: Event errors: 0
[12:03:23.376] <TB1> INFO: start marker: 0
[12:03:23.376] <TB1> INFO: stop marker: 0
[12:03:23.376] <TB1> INFO: overflow: 0
[12:03:23.376] <TB1> INFO: invalid 5bit words: 0
[12:03:23.376] <TB1> INFO: invalid XOR eye diagram: 0
[12:03:23.376] <TB1> INFO: frame (failed synchr.): 0
[12:03:23.376] <TB1> INFO: idle data (no TBM trl): 0
[12:03:23.376] <TB1> INFO: no data (only TBM hdr): 0
[12:03:23.376] <TB1> INFO: TBM errors: 0
[12:03:23.376] <TB1> INFO: flawed TBM headers: 0
[12:03:23.376] <TB1> INFO: flawed TBM trailers: 0
[12:03:23.376] <TB1> INFO: event ID mismatches: 0
[12:03:23.376] <TB1> INFO: ROC errors: 0
[12:03:23.376] <TB1> INFO: missing ROC header(s): 0
[12:03:23.376] <TB1> INFO: misplaced readback start: 0
[12:03:23.376] <TB1> INFO: Pixel decoding errors: 0
[12:03:23.376] <TB1> INFO: pixel data incomplete: 0
[12:03:23.376] <TB1> INFO: pixel address: 0
[12:03:23.376] <TB1> INFO: pulse height fill bit: 0
[12:03:23.376] <TB1> INFO: buffer corruption: 0
[12:03:23.398] <TB1> INFO: Decoding statistics:
[12:03:23.398] <TB1> INFO: General information:
[12:03:23.398] <TB1> INFO: 16bit words read: 3457346
[12:03:23.398] <TB1> INFO: valid events total: 353536
[12:03:23.398] <TB1> INFO: empty events: 18236
[12:03:23.398] <TB1> INFO: valid events with pixels: 335300
[12:03:23.398] <TB1> INFO: valid pixel hits: 668065
[12:03:23.398] <TB1> INFO: Event errors: 0
[12:03:23.398] <TB1> INFO: start marker: 0
[12:03:23.398] <TB1> INFO: stop marker: 0
[12:03:23.398] <TB1> INFO: overflow: 0
[12:03:23.398] <TB1> INFO: invalid 5bit words: 0
[12:03:23.398] <TB1> INFO: invalid XOR eye diagram: 0
[12:03:23.398] <TB1> INFO: frame (failed synchr.): 0
[12:03:23.398] <TB1> INFO: idle data (no TBM trl): 0
[12:03:23.398] <TB1> INFO: no data (only TBM hdr): 0
[12:03:23.398] <TB1> INFO: TBM errors: 0
[12:03:23.398] <TB1> INFO: flawed TBM headers: 0
[12:03:23.398] <TB1> INFO: flawed TBM trailers: 0
[12:03:23.398] <TB1> INFO: event ID mismatches: 0
[12:03:23.398] <TB1> INFO: ROC errors: 0
[12:03:23.398] <TB1> INFO: missing ROC header(s): 0
[12:03:23.398] <TB1> INFO: misplaced readback start: 0
[12:03:23.398] <TB1> INFO: Pixel decoding errors: 0
[12:03:23.398] <TB1> INFO: pixel data incomplete: 0
[12:03:23.398] <TB1> INFO: pixel address: 0
[12:03:23.398] <TB1> INFO: pulse height fill bit: 0
[12:03:23.398] <TB1> INFO: buffer corruption: 0
[12:03:23.398] <TB1> INFO: enter test to run
[12:03:23.398] <TB1> INFO: test: exit no parameter change
[12:03:23.436] <TB1> QUIET: Connection to board 153 closed.
[12:03:23.437] <TB1> INFO: pXar: this is the end, my friend