[12:22:52.100] <TB1> INFO: *** Welcome to pxar ***
[12:22:52.100] <TB1> INFO: *** Today: 2016/11/02
[12:22:52.106] <TB1> INFO: *** Version: c8ba-dirty
[12:22:52.106] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:22:52.107] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:22:52.107] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//defaultMaskFile.dat
[12:22:52.107] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters_C15.dat
[12:22:52.162] <TB1> INFO: clk: 4
[12:22:52.162] <TB1> INFO: ctr: 4
[12:22:52.162] <TB1> INFO: sda: 19
[12:22:52.162] <TB1> INFO: tin: 9
[12:22:52.162] <TB1> INFO: level: 15
[12:22:52.162] <TB1> INFO: triggerdelay: 0
[12:22:52.162] <TB1> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[12:22:52.162] <TB1> INFO: Log level: INFO
[12:22:52.170] <TB1> INFO: Found DTB DTB_WXBYFL
[12:22:52.180] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[12:22:52.182] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
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[12:22:52.184] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[12:22:53.667] <TB1> INFO: DUT info:
[12:22:53.667] <TB1> INFO: The DUT currently contains the following objects:
[12:22:53.667] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[12:22:53.667] <TB1> INFO: TBM Core alpha (0): 7 registers set
[12:22:53.667] <TB1> INFO: TBM Core beta (1): 7 registers set
[12:22:53.667] <TB1> INFO: TBM Core alpha (2): 7 registers set
[12:22:53.667] <TB1> INFO: TBM Core beta (3): 7 registers set
[12:22:53.667] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[12:22:53.667] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:53.667] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:54.068] <TB1> INFO: enter 'restricted' command line mode
[12:22:54.068] <TB1> INFO: enter test to run
[12:22:54.068] <TB1> INFO: test: pretest no parameter change
[12:22:54.068] <TB1> INFO: running: pretest
[12:22:54.598] <TB1> INFO: ######################################################################
[12:22:54.598] <TB1> INFO: PixTestPretest::doTest()
[12:22:54.598] <TB1> INFO: ######################################################################
[12:22:54.599] <TB1> INFO: ----------------------------------------------------------------------
[12:22:54.599] <TB1> INFO: PixTestPretest::programROC()
[12:22:54.599] <TB1> INFO: ----------------------------------------------------------------------
[12:23:12.613] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:23:12.613] <TB1> INFO: IA differences per ROC: 16.9 19.3 18.5 19.3 17.7 18.5 16.9 17.7 18.5 17.7 17.7 16.9 18.5 18.5 18.5 19.3
[12:23:12.647] <TB1> INFO: ----------------------------------------------------------------------
[12:23:12.647] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:23:12.647] <TB1> INFO: ----------------------------------------------------------------------
[12:23:33.892] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 382.7 mA = 23.9187 mA/ROC
[12:23:33.892] <TB1> INFO: i(loss) [mA/ROC]: 18.5 20.1 18.5 19.3 18.5 21.0 19.3 17.7 19.3 18.5 18.5 19.3 19.3 17.7 18.5 18.5
[12:23:33.923] <TB1> INFO: ----------------------------------------------------------------------
[12:23:33.923] <TB1> INFO: PixTestPretest::findTiming()
[12:23:33.923] <TB1> INFO: ----------------------------------------------------------------------
[12:23:33.923] <TB1> INFO: PixTestCmd::init()

[12:24:05.291] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 6, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:24:05.291] <TB1> INFO: (success/tries = 100/100), width = 4
[12:24:06.791] <TB1> INFO: ----------------------------------------------------------------------
[12:24:06.791] <TB1> INFO: PixTestPretest::findWorkingPixel()
[12:24:06.791] <TB1> INFO: ----------------------------------------------------------------------
[12:24:06.882] <TB1> INFO: Expecting 231680 events.
[12:24:16.543] <TB1> INFO: 231680 events read in total (9069ms).
[12:24:16.549] <TB1> INFO: Test took 9756ms.
[12:24:16.793] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:24:16.822] <TB1> INFO: ----------------------------------------------------------------------
[12:24:16.822] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[12:24:16.822] <TB1> INFO: ----------------------------------------------------------------------
[12:24:16.914] <TB1> INFO: Expecting 231680 events.
[12:24:26.586] <TB1> INFO: 231680 events read in total (9081ms).
[12:24:26.593] <TB1> INFO: Test took 9768ms.
[12:24:26.849] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[12:24:26.849] <TB1> INFO: CalDel: 89 96 87 73 95 86 74 81 101 89 75 77 96 78 76 83
[12:24:26.849] <TB1> INFO: VthrComp: 51 51 51 51 51 51 51 52 51 54 51 56 51 51 51 51
[12:24:26.852] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C0.dat
[12:24:26.852] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C1.dat
[12:24:26.852] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C2.dat
[12:24:26.852] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C3.dat
[12:24:26.852] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C4.dat
[12:24:26.852] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C5.dat
[12:24:26.852] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C6.dat
[12:24:26.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C7.dat
[12:24:26.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C8.dat
[12:24:26.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C9.dat
[12:24:26.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C10.dat
[12:24:26.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C11.dat
[12:24:26.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C12.dat
[12:24:26.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C13.dat
[12:24:26.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C14.dat
[12:24:26.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:24:26.854] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[12:24:26.854] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[12:24:26.854] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[12:24:26.854] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:24:26.854] <TB1> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[12:24:26.949] <TB1> INFO: enter test to run
[12:24:26.949] <TB1> INFO: test: fulltest no parameter change
[12:24:26.949] <TB1> INFO: running: fulltest
[12:24:26.949] <TB1> INFO: ######################################################################
[12:24:26.950] <TB1> INFO: PixTestFullTest::doTest()
[12:24:26.950] <TB1> INFO: ######################################################################
[12:24:26.951] <TB1> INFO: ######################################################################
[12:24:26.951] <TB1> INFO: PixTestAlive::doTest()
[12:24:26.951] <TB1> INFO: ######################################################################
[12:24:26.952] <TB1> INFO: ----------------------------------------------------------------------
[12:24:26.952] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:24:26.952] <TB1> INFO: ----------------------------------------------------------------------
[12:24:27.185] <TB1> INFO: Expecting 41600 events.
[12:24:30.614] <TB1> INFO: 41600 events read in total (2838ms).
[12:24:30.615] <TB1> INFO: Test took 3662ms.
[12:24:30.842] <TB1> INFO: PixTestAlive::aliveTest() done
[12:24:30.842] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:24:30.843] <TB1> INFO: ----------------------------------------------------------------------
[12:24:30.843] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:24:30.843] <TB1> INFO: ----------------------------------------------------------------------
[12:24:31.080] <TB1> INFO: Expecting 41600 events.
[12:24:34.026] <TB1> INFO: 41600 events read in total (2354ms).
[12:24:34.026] <TB1> INFO: Test took 3181ms.
[12:24:34.027] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:24:34.267] <TB1> INFO: PixTestAlive::maskTest() done
[12:24:34.267] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:24:34.268] <TB1> INFO: ----------------------------------------------------------------------
[12:24:34.268] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:24:34.268] <TB1> INFO: ----------------------------------------------------------------------
[12:24:34.501] <TB1> INFO: Expecting 41600 events.
[12:24:38.097] <TB1> INFO: 41600 events read in total (3005ms).
[12:24:38.098] <TB1> INFO: Test took 3828ms.
[12:24:38.324] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[12:24:38.324] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:24:38.325] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:24:38.325] <TB1> INFO: Decoding statistics:
[12:24:38.325] <TB1> INFO: General information:
[12:24:38.325] <TB1> INFO: 16bit words read: 0
[12:24:38.325] <TB1> INFO: valid events total: 0
[12:24:38.325] <TB1> INFO: empty events: 0
[12:24:38.325] <TB1> INFO: valid events with pixels: 0
[12:24:38.325] <TB1> INFO: valid pixel hits: 0
[12:24:38.325] <TB1> INFO: Event errors: 0
[12:24:38.325] <TB1> INFO: start marker: 0
[12:24:38.325] <TB1> INFO: stop marker: 0
[12:24:38.325] <TB1> INFO: overflow: 0
[12:24:38.325] <TB1> INFO: invalid 5bit words: 0
[12:24:38.325] <TB1> INFO: invalid XOR eye diagram: 0
[12:24:38.325] <TB1> INFO: frame (failed synchr.): 0
[12:24:38.325] <TB1> INFO: idle data (no TBM trl): 0
[12:24:38.325] <TB1> INFO: no data (only TBM hdr): 0
[12:24:38.325] <TB1> INFO: TBM errors: 0
[12:24:38.325] <TB1> INFO: flawed TBM headers: 0
[12:24:38.325] <TB1> INFO: flawed TBM trailers: 0
[12:24:38.325] <TB1> INFO: event ID mismatches: 0
[12:24:38.325] <TB1> INFO: ROC errors: 0
[12:24:38.325] <TB1> INFO: missing ROC header(s): 0
[12:24:38.325] <TB1> INFO: misplaced readback start: 0
[12:24:38.325] <TB1> INFO: Pixel decoding errors: 0
[12:24:38.325] <TB1> INFO: pixel data incomplete: 0
[12:24:38.325] <TB1> INFO: pixel address: 0
[12:24:38.325] <TB1> INFO: pulse height fill bit: 0
[12:24:38.325] <TB1> INFO: buffer corruption: 0
[12:24:38.332] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:24:38.332] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[12:24:38.332] <TB1> INFO: ######################################################################
[12:24:38.332] <TB1> INFO: PixTestReadback::doTest()
[12:24:38.332] <TB1> INFO: ######################################################################
[12:24:38.332] <TB1> INFO: ----------------------------------------------------------------------
[12:24:38.332] <TB1> INFO: PixTestReadback::CalibrateVd()
[12:24:38.332] <TB1> INFO: ----------------------------------------------------------------------
[12:24:48.289] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:24:48.290] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:24:48.290] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:24:48.290] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:24:48.290] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:24:48.290] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:24:48.290] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:24:48.290] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:24:48.290] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:24:48.290] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:24:48.290] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:24:48.290] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:24:48.290] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:24:48.290] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:24:48.290] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:24:48.291] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:24:48.318] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:24:48.318] <TB1> INFO: ----------------------------------------------------------------------
[12:24:48.318] <TB1> INFO: PixTestReadback::CalibrateVa()
[12:24:48.318] <TB1> INFO: ----------------------------------------------------------------------
[12:24:58.207] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:24:58.207] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:24:58.208] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:24:58.208] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:24:58.208] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:24:58.208] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:24:58.208] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:24:58.208] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:24:58.208] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:24:58.208] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:24:58.208] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:24:58.208] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:24:58.208] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:24:58.208] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:24:58.208] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:24:58.208] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:24:58.236] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:24:58.236] <TB1> INFO: ----------------------------------------------------------------------
[12:24:58.236] <TB1> INFO: PixTestReadback::readbackVbg()
[12:24:58.236] <TB1> INFO: ----------------------------------------------------------------------
[12:25:05.874] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:25:05.874] <TB1> INFO: ----------------------------------------------------------------------
[12:25:05.874] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[12:25:05.874] <TB1> INFO: ----------------------------------------------------------------------
[12:25:05.874] <TB1> INFO: Vbg will be calibrated using Vd calibration
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 149.5calibrated Vbg = 1.15725 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 151.9calibrated Vbg = 1.16382 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 148calibrated Vbg = 1.15413 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 150.9calibrated Vbg = 1.14999 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 159.3calibrated Vbg = 1.1542 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 150.3calibrated Vbg = 1.15986 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 160.9calibrated Vbg = 1.1574 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 155.2calibrated Vbg = 1.16131 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 153calibrated Vbg = 1.15916 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 149.1calibrated Vbg = 1.15324 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 157calibrated Vbg = 1.14459 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 153.9calibrated Vbg = 1.14301 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 149.3calibrated Vbg = 1.15775 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152.8calibrated Vbg = 1.15933 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 151.7calibrated Vbg = 1.15985 :::*/*/*/*/
[12:25:05.874] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 154.7calibrated Vbg = 1.16262 :::*/*/*/*/
[12:25:05.876] <TB1> INFO: ----------------------------------------------------------------------
[12:25:05.876] <TB1> INFO: PixTestReadback::CalibrateIa()
[12:25:05.876] <TB1> INFO: ----------------------------------------------------------------------
[12:27:46.165] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:27:46.165] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:27:46.165] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:27:46.165] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:27:46.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:27:46.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:27:46.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:27:46.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:27:46.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:27:46.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:27:46.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:27:46.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:27:46.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:27:46.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:27:46.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:27:46.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:27:46.193] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:27:46.194] <TB1> INFO: PixTestReadback::doTest() done
[12:27:46.194] <TB1> INFO: Decoding statistics:
[12:27:46.194] <TB1> INFO: General information:
[12:27:46.194] <TB1> INFO: 16bit words read: 1536
[12:27:46.194] <TB1> INFO: valid events total: 256
[12:27:46.194] <TB1> INFO: empty events: 256
[12:27:46.194] <TB1> INFO: valid events with pixels: 0
[12:27:46.194] <TB1> INFO: valid pixel hits: 0
[12:27:46.194] <TB1> INFO: Event errors: 0
[12:27:46.195] <TB1> INFO: start marker: 0
[12:27:46.195] <TB1> INFO: stop marker: 0
[12:27:46.195] <TB1> INFO: overflow: 0
[12:27:46.195] <TB1> INFO: invalid 5bit words: 0
[12:27:46.195] <TB1> INFO: invalid XOR eye diagram: 0
[12:27:46.195] <TB1> INFO: frame (failed synchr.): 0
[12:27:46.195] <TB1> INFO: idle data (no TBM trl): 0
[12:27:46.195] <TB1> INFO: no data (only TBM hdr): 0
[12:27:46.195] <TB1> INFO: TBM errors: 0
[12:27:46.195] <TB1> INFO: flawed TBM headers: 0
[12:27:46.195] <TB1> INFO: flawed TBM trailers: 0
[12:27:46.195] <TB1> INFO: event ID mismatches: 0
[12:27:46.195] <TB1> INFO: ROC errors: 0
[12:27:46.195] <TB1> INFO: missing ROC header(s): 0
[12:27:46.195] <TB1> INFO: misplaced readback start: 0
[12:27:46.195] <TB1> INFO: Pixel decoding errors: 0
[12:27:46.195] <TB1> INFO: pixel data incomplete: 0
[12:27:46.195] <TB1> INFO: pixel address: 0
[12:27:46.195] <TB1> INFO: pulse height fill bit: 0
[12:27:46.195] <TB1> INFO: buffer corruption: 0
[12:27:46.230] <TB1> INFO: ######################################################################
[12:27:46.230] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:27:46.230] <TB1> INFO: ######################################################################
[12:27:46.232] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:27:46.243] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:27:46.243] <TB1> INFO: run 1 of 1
[12:27:46.474] <TB1> INFO: Expecting 3120000 events.
[12:28:17.161] <TB1> INFO: 663985 events read in total (30095ms).











[12:28:46.646] <TB1> INFO: 1321160 events read in total (59580ms).











[12:29:16.194] <TB1> INFO: 1973065 events read in total (89128ms).
[12:29:45.370] <TB1> INFO: 2625810 events read in total (118304ms).











[12:30:07.480] <TB1> INFO: 3120000 events read in total (140414ms).
[12:30:07.529] <TB1> INFO: Test took 141287ms.
[12:30:33.302] <TB1> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 167 seconds
[12:30:33.302] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 7
[12:30:33.302] <TB1> INFO: separation cut (per ROC): 99 106 105 103 100 105 108 106 108 115 106 111 109 102 102 103
[12:30:33.302] <TB1> INFO: Decoding statistics:
[12:30:33.302] <TB1> INFO: General information:
[12:30:33.302] <TB1> INFO: 16bit words read: 0
[12:30:33.302] <TB1> INFO: valid events total: 0
[12:30:33.302] <TB1> INFO: empty events: 0
[12:30:33.302] <TB1> INFO: valid events with pixels: 0
[12:30:33.302] <TB1> INFO: valid pixel hits: 0
[12:30:33.302] <TB1> INFO: Event errors: 0
[12:30:33.302] <TB1> INFO: start marker: 0
[12:30:33.302] <TB1> INFO: stop marker: 0
[12:30:33.302] <TB1> INFO: overflow: 0
[12:30:33.302] <TB1> INFO: invalid 5bit words: 0
[12:30:33.302] <TB1> INFO: invalid XOR eye diagram: 0
[12:30:33.302] <TB1> INFO: frame (failed synchr.): 0
[12:30:33.302] <TB1> INFO: idle data (no TBM trl): 0
[12:30:33.302] <TB1> INFO: no data (only TBM hdr): 0
[12:30:33.302] <TB1> INFO: TBM errors: 0
[12:30:33.303] <TB1> INFO: flawed TBM headers: 0
[12:30:33.303] <TB1> INFO: flawed TBM trailers: 0
[12:30:33.303] <TB1> INFO: event ID mismatches: 0
[12:30:33.303] <TB1> INFO: ROC errors: 0
[12:30:33.303] <TB1> INFO: missing ROC header(s): 0
[12:30:33.303] <TB1> INFO: misplaced readback start: 0
[12:30:33.303] <TB1> INFO: Pixel decoding errors: 0
[12:30:33.303] <TB1> INFO: pixel data incomplete: 0
[12:30:33.303] <TB1> INFO: pixel address: 0
[12:30:33.303] <TB1> INFO: pulse height fill bit: 0
[12:30:33.303] <TB1> INFO: buffer corruption: 0
[12:30:33.339] <TB1> INFO: ######################################################################
[12:30:33.339] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:30:33.339] <TB1> INFO: ######################################################################
[12:30:33.339] <TB1> INFO: ----------------------------------------------------------------------
[12:30:33.339] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:30:33.339] <TB1> INFO: ----------------------------------------------------------------------
[12:30:33.339] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:30:33.349] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[12:30:33.349] <TB1> INFO: run 1 of 1
[12:30:33.582] <TB1> INFO: Expecting 36608000 events.
[12:30:56.514] <TB1> INFO: 685550 events read in total (22341ms).
[12:31:18.880] <TB1> INFO: 1360600 events read in total (44707ms).
[12:31:41.292] <TB1> INFO: 2030950 events read in total (67119ms).
[12:32:03.755] <TB1> INFO: 2701700 events read in total (89582ms).
[12:32:26.103] <TB1> INFO: 3372100 events read in total (111930ms).
[12:32:48.586] <TB1> INFO: 4042550 events read in total (134413ms).
[12:33:11.108] <TB1> INFO: 4713500 events read in total (156935ms).
[12:33:33.681] <TB1> INFO: 5383650 events read in total (179508ms).
[12:33:56.064] <TB1> INFO: 6054750 events read in total (201891ms).
[12:34:18.405] <TB1> INFO: 6726100 events read in total (224232ms).
[12:34:40.822] <TB1> INFO: 7397300 events read in total (246649ms).
[12:35:03.533] <TB1> INFO: 8066800 events read in total (269360ms).
[12:35:26.281] <TB1> INFO: 8737000 events read in total (292108ms).
[12:35:48.576] <TB1> INFO: 9406500 events read in total (314403ms).
[12:36:10.949] <TB1> INFO: 10075150 events read in total (336776ms).
[12:36:33.541] <TB1> INFO: 10743800 events read in total (359368ms).
[12:36:56.123] <TB1> INFO: 11413200 events read in total (381950ms).
[12:37:18.831] <TB1> INFO: 12081550 events read in total (404658ms).
[12:37:41.290] <TB1> INFO: 12751000 events read in total (427117ms).
[12:38:03.629] <TB1> INFO: 13418800 events read in total (449456ms).
[12:38:26.271] <TB1> INFO: 14087950 events read in total (472098ms).
[12:38:48.548] <TB1> INFO: 14755000 events read in total (494375ms).
[12:39:11.122] <TB1> INFO: 15421200 events read in total (516949ms).
[12:39:33.643] <TB1> INFO: 16088300 events read in total (539470ms).
[12:39:55.948] <TB1> INFO: 16757350 events read in total (561775ms).
[12:40:18.326] <TB1> INFO: 17423200 events read in total (584153ms).
[12:40:40.523] <TB1> INFO: 18090200 events read in total (606350ms).
[12:41:02.857] <TB1> INFO: 18754700 events read in total (628684ms).
[12:41:25.184] <TB1> INFO: 19419800 events read in total (651011ms).
[12:41:47.353] <TB1> INFO: 20083050 events read in total (673180ms).
[12:42:09.730] <TB1> INFO: 20747000 events read in total (695557ms).
[12:42:32.068] <TB1> INFO: 21409200 events read in total (717895ms).
[12:42:54.248] <TB1> INFO: 22072850 events read in total (740075ms).
[12:43:16.531] <TB1> INFO: 22736150 events read in total (762358ms).
[12:43:38.752] <TB1> INFO: 23399850 events read in total (784579ms).
[12:44:01.037] <TB1> INFO: 24063650 events read in total (806864ms).
[12:44:23.237] <TB1> INFO: 24726350 events read in total (829064ms).
[12:44:45.303] <TB1> INFO: 25389850 events read in total (851130ms).
[12:45:07.414] <TB1> INFO: 26053700 events read in total (873241ms).
[12:45:29.795] <TB1> INFO: 26715650 events read in total (895622ms).
[12:45:52.175] <TB1> INFO: 27377200 events read in total (918002ms).
[12:46:14.484] <TB1> INFO: 28039600 events read in total (940311ms).
[12:46:36.815] <TB1> INFO: 28701950 events read in total (962642ms).
[12:46:59.021] <TB1> INFO: 29363050 events read in total (984848ms).
[12:47:21.224] <TB1> INFO: 30024050 events read in total (1007051ms).
[12:47:43.428] <TB1> INFO: 30685700 events read in total (1029255ms).
[12:48:06.017] <TB1> INFO: 31347150 events read in total (1051844ms).
[12:48:28.217] <TB1> INFO: 32007850 events read in total (1074044ms).
[12:48:50.552] <TB1> INFO: 32668900 events read in total (1096379ms).
[12:49:12.918] <TB1> INFO: 33330800 events read in total (1118745ms).
[12:49:35.239] <TB1> INFO: 33992900 events read in total (1141066ms).
[12:49:57.511] <TB1> INFO: 34654250 events read in total (1163338ms).
[12:50:19.964] <TB1> INFO: 35317750 events read in total (1185791ms).
[12:50:42.254] <TB1> INFO: 35980450 events read in total (1208081ms).
[12:51:03.052] <TB1> INFO: 36608000 events read in total (1228879ms).
[12:51:03.102] <TB1> INFO: Test took 1229753ms.
[12:51:03.454] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:05.081] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:06.684] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:08.402] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:10.204] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:12.068] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:13.935] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:15.589] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:17.541] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:19.344] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:21.547] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:23.467] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:25.551] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:27.357] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:29.308] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:31.089] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:51:33.059] <TB1> INFO: PixTestScurves::scurves() done
[12:51:33.059] <TB1> INFO: Vcal mean: 110.90 123.71 115.22 114.11 117.51 115.00 120.29 132.18 120.34 126.36 124.31 131.82 120.28 117.25 111.78 114.68
[12:51:33.059] <TB1> INFO: Vcal RMS: 4.91 5.44 4.91 4.85 5.57 4.82 5.45 6.21 5.78 8.31 5.79 6.61 5.50 5.84 4.65 4.89
[12:51:33.059] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1259 seconds
[12:51:33.059] <TB1> INFO: Decoding statistics:
[12:51:33.059] <TB1> INFO: General information:
[12:51:33.059] <TB1> INFO: 16bit words read: 0
[12:51:33.059] <TB1> INFO: valid events total: 0
[12:51:33.059] <TB1> INFO: empty events: 0
[12:51:33.059] <TB1> INFO: valid events with pixels: 0
[12:51:33.059] <TB1> INFO: valid pixel hits: 0
[12:51:33.059] <TB1> INFO: Event errors: 0
[12:51:33.059] <TB1> INFO: start marker: 0
[12:51:33.059] <TB1> INFO: stop marker: 0
[12:51:33.059] <TB1> INFO: overflow: 0
[12:51:33.059] <TB1> INFO: invalid 5bit words: 0
[12:51:33.059] <TB1> INFO: invalid XOR eye diagram: 0
[12:51:33.059] <TB1> INFO: frame (failed synchr.): 0
[12:51:33.059] <TB1> INFO: idle data (no TBM trl): 0
[12:51:33.059] <TB1> INFO: no data (only TBM hdr): 0
[12:51:33.059] <TB1> INFO: TBM errors: 0
[12:51:33.059] <TB1> INFO: flawed TBM headers: 0
[12:51:33.059] <TB1> INFO: flawed TBM trailers: 0
[12:51:33.059] <TB1> INFO: event ID mismatches: 0
[12:51:33.059] <TB1> INFO: ROC errors: 0
[12:51:33.059] <TB1> INFO: missing ROC header(s): 0
[12:51:33.059] <TB1> INFO: misplaced readback start: 0
[12:51:33.059] <TB1> INFO: Pixel decoding errors: 0
[12:51:33.059] <TB1> INFO: pixel data incomplete: 0
[12:51:33.059] <TB1> INFO: pixel address: 0
[12:51:33.059] <TB1> INFO: pulse height fill bit: 0
[12:51:33.059] <TB1> INFO: buffer corruption: 0
[12:51:33.123] <TB1> INFO: ######################################################################
[12:51:33.123] <TB1> INFO: PixTestTrim::doTest()
[12:51:33.123] <TB1> INFO: ######################################################################
[12:51:33.124] <TB1> INFO: ----------------------------------------------------------------------
[12:51:33.124] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:51:33.124] <TB1> INFO: ----------------------------------------------------------------------
[12:51:33.163] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:51:33.163] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:51:33.172] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:51:33.172] <TB1> INFO: run 1 of 1
[12:51:33.405] <TB1> INFO: Expecting 5025280 events.
[12:52:03.650] <TB1> INFO: 822872 events read in total (29651ms).
[12:52:33.376] <TB1> INFO: 1642960 events read in total (59377ms).
[12:53:02.754] <TB1> INFO: 2461792 events read in total (88755ms).
[12:53:32.472] <TB1> INFO: 3276232 events read in total (118473ms).
[12:54:02.134] <TB1> INFO: 4087336 events read in total (148135ms).
[12:54:31.311] <TB1> INFO: 4896024 events read in total (177312ms).
[12:54:36.481] <TB1> INFO: 5025280 events read in total (182482ms).
[12:54:36.520] <TB1> INFO: Test took 183348ms.
[12:54:55.354] <TB1> INFO: ROC 0 VthrComp = 115
[12:54:55.354] <TB1> INFO: ROC 1 VthrComp = 131
[12:54:55.354] <TB1> INFO: ROC 2 VthrComp = 126
[12:54:55.354] <TB1> INFO: ROC 3 VthrComp = 126
[12:54:55.354] <TB1> INFO: ROC 4 VthrComp = 120
[12:54:55.354] <TB1> INFO: ROC 5 VthrComp = 125
[12:54:55.355] <TB1> INFO: ROC 6 VthrComp = 129
[12:54:55.355] <TB1> INFO: ROC 7 VthrComp = 127
[12:54:55.355] <TB1> INFO: ROC 8 VthrComp = 130
[12:54:55.355] <TB1> INFO: ROC 9 VthrComp = 132
[12:54:55.355] <TB1> INFO: ROC 10 VthrComp = 130
[12:54:55.355] <TB1> INFO: ROC 11 VthrComp = 132
[12:54:55.355] <TB1> INFO: ROC 12 VthrComp = 128
[12:54:55.355] <TB1> INFO: ROC 13 VthrComp = 119
[12:54:55.355] <TB1> INFO: ROC 14 VthrComp = 118
[12:54:55.356] <TB1> INFO: ROC 15 VthrComp = 124
[12:54:55.589] <TB1> INFO: Expecting 41600 events.
[12:54:59.020] <TB1> INFO: 41600 events read in total (2840ms).
[12:54:59.021] <TB1> INFO: Test took 3664ms.
[12:54:59.029] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:54:59.029] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:54:59.038] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:54:59.038] <TB1> INFO: run 1 of 1
[12:54:59.316] <TB1> INFO: Expecting 5025280 events.
[12:55:25.201] <TB1> INFO: 588432 events read in total (25294ms).
[12:55:50.366] <TB1> INFO: 1175608 events read in total (50459ms).
[12:56:15.796] <TB1> INFO: 1763248 events read in total (75889ms).
[12:56:41.462] <TB1> INFO: 2350688 events read in total (101555ms).
[12:57:06.742] <TB1> INFO: 2936160 events read in total (126835ms).
[12:57:32.009] <TB1> INFO: 3520880 events read in total (152102ms).
[12:57:57.465] <TB1> INFO: 4104576 events read in total (177558ms).
[12:58:22.544] <TB1> INFO: 4688024 events read in total (202637ms).
[12:58:37.521] <TB1> INFO: 5025280 events read in total (217614ms).
[12:58:37.584] <TB1> INFO: Test took 218546ms.
[12:59:05.538] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 57.823 for pixel 37/17 mean/min/max = 45.2418/32.5212/57.9625
[12:59:05.538] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 56.7469 for pixel 13/11 mean/min/max = 44.3387/31.9224/56.755
[12:59:05.538] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 56.4875 for pixel 25/14 mean/min/max = 44.7721/33.035/56.5091
[12:59:05.539] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 55.962 for pixel 10/76 mean/min/max = 44.195/31.9222/56.4678
[12:59:05.539] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 60.4304 for pixel 14/79 mean/min/max = 46.9726/33.383/60.5622
[12:59:05.539] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 55.651 for pixel 5/31 mean/min/max = 44.1669/32.33/56.0039
[12:59:05.540] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 58.673 for pixel 16/0 mean/min/max = 45.4802/32.1699/58.7906
[12:59:05.540] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 63.1868 for pixel 15/8 mean/min/max = 47.3993/31.4952/63.3033
[12:59:05.540] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 56.5301 for pixel 46/71 mean/min/max = 44.1364/31.7403/56.5326
[12:59:05.541] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 66.6816 for pixel 6/72 mean/min/max = 49.5214/31.8069/67.236
[12:59:05.541] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 58.5326 for pixel 5/28 mean/min/max = 45.7122/32.7515/58.673
[12:59:05.541] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 65.7728 for pixel 12/2 mean/min/max = 49.6876/33.5728/65.8023
[12:59:05.542] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 58.171 for pixel 2/77 mean/min/max = 45.7252/33.2575/58.193
[12:59:05.542] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 58.7635 for pixel 20/16 mean/min/max = 45.0731/31.2484/58.8978
[12:59:05.542] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 57.5387 for pixel 1/13 mean/min/max = 44.9449/32.3063/57.5835
[12:59:05.542] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 56.2041 for pixel 21/3 mean/min/max = 44.3002/32.3812/56.2193
[12:59:05.543] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:59:05.631] <TB1> INFO: Expecting 411648 events.
[12:59:14.914] <TB1> INFO: 411648 events read in total (8691ms).
[12:59:14.924] <TB1> INFO: Expecting 411648 events.
[12:59:23.939] <TB1> INFO: 411648 events read in total (8612ms).
[12:59:23.948] <TB1> INFO: Expecting 411648 events.
[12:59:32.974] <TB1> INFO: 411648 events read in total (8623ms).
[12:59:32.986] <TB1> INFO: Expecting 411648 events.
[12:59:42.035] <TB1> INFO: 411648 events read in total (8646ms).
[12:59:42.051] <TB1> INFO: Expecting 411648 events.
[12:59:51.098] <TB1> INFO: 411648 events read in total (8644ms).
[12:59:51.121] <TB1> INFO: Expecting 411648 events.
[13:00:00.211] <TB1> INFO: 411648 events read in total (8687ms).
[13:00:00.232] <TB1> INFO: Expecting 411648 events.
[13:00:09.307] <TB1> INFO: 411648 events read in total (8673ms).
[13:00:09.329] <TB1> INFO: Expecting 411648 events.
[13:00:18.346] <TB1> INFO: 411648 events read in total (8614ms).
[13:00:18.370] <TB1> INFO: Expecting 411648 events.
[13:00:27.372] <TB1> INFO: 411648 events read in total (8599ms).
[13:00:27.400] <TB1> INFO: Expecting 411648 events.
[13:00:36.429] <TB1> INFO: 411648 events read in total (8626ms).
[13:00:36.464] <TB1> INFO: Expecting 411648 events.
[13:00:45.510] <TB1> INFO: 411648 events read in total (8644ms).
[13:00:45.545] <TB1> INFO: Expecting 411648 events.
[13:00:54.600] <TB1> INFO: 411648 events read in total (8652ms).
[13:00:54.648] <TB1> INFO: Expecting 411648 events.
[13:01:03.642] <TB1> INFO: 411648 events read in total (8591ms).
[13:01:03.682] <TB1> INFO: Expecting 411648 events.
[13:01:12.678] <TB1> INFO: 411648 events read in total (8593ms).
[13:01:12.719] <TB1> INFO: Expecting 411648 events.
[13:01:21.776] <TB1> INFO: 411648 events read in total (8654ms).
[13:01:21.821] <TB1> INFO: Expecting 411648 events.
[13:01:30.928] <TB1> INFO: 411648 events read in total (8704ms).
[13:01:30.989] <TB1> INFO: Test took 145446ms.
[13:01:31.753] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:01:31.761] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:01:31.761] <TB1> INFO: run 1 of 1
[13:01:31.994] <TB1> INFO: Expecting 5025280 events.
[13:01:58.046] <TB1> INFO: 586712 events read in total (25460ms).
[13:02:23.623] <TB1> INFO: 1172704 events read in total (51037ms).
[13:02:49.072] <TB1> INFO: 1757792 events read in total (76486ms).
[13:03:14.568] <TB1> INFO: 2341464 events read in total (101982ms).
[13:03:40.040] <TB1> INFO: 2925592 events read in total (127455ms).
[13:04:05.574] <TB1> INFO: 3512552 events read in total (152988ms).
[13:04:30.944] <TB1> INFO: 4096688 events read in total (178358ms).
[13:04:56.240] <TB1> INFO: 4680368 events read in total (203654ms).
[13:05:11.858] <TB1> INFO: 5025280 events read in total (219273ms).
[13:05:11.958] <TB1> INFO: Test took 220197ms.
[13:05:36.399] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 8.806066 .. 145.059298
[13:05:36.633] <TB1> INFO: Expecting 208000 events.
[13:05:45.914] <TB1> INFO: 208000 events read in total (8689ms).
[13:05:45.915] <TB1> INFO: Test took 9514ms.
[13:05:45.962] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 8 .. 155 (-1/-1) hits flags = 528 (plus default)
[13:05:45.971] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:05:45.971] <TB1> INFO: run 1 of 1
[13:05:46.248] <TB1> INFO: Expecting 4925440 events.
[13:06:11.692] <TB1> INFO: 575752 events read in total (24852ms).
[13:06:36.861] <TB1> INFO: 1151408 events read in total (50021ms).
[13:07:01.883] <TB1> INFO: 1726920 events read in total (75043ms).
[13:07:27.115] <TB1> INFO: 2302688 events read in total (100275ms).
[13:07:52.675] <TB1> INFO: 2877008 events read in total (125835ms).
[13:08:17.871] <TB1> INFO: 3450720 events read in total (151031ms).
[13:08:42.755] <TB1> INFO: 4023960 events read in total (175915ms).
[13:09:08.196] <TB1> INFO: 4597264 events read in total (201356ms).
[13:09:22.494] <TB1> INFO: 4925440 events read in total (215654ms).
[13:09:22.582] <TB1> INFO: Test took 216611ms.
[13:09:51.946] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.195771 .. 43.358461
[13:09:52.187] <TB1> INFO: Expecting 208000 events.
[13:10:01.902] <TB1> INFO: 208000 events read in total (9123ms).
[13:10:01.903] <TB1> INFO: Test took 9955ms.
[13:10:01.948] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 53 (-1/-1) hits flags = 528 (plus default)
[13:10:01.957] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:10:01.957] <TB1> INFO: run 1 of 1
[13:10:02.235] <TB1> INFO: Expecting 1231360 events.
[13:10:30.743] <TB1> INFO: 668936 events read in total (27916ms).
[13:10:53.924] <TB1> INFO: 1231360 events read in total (51097ms).
[13:10:53.953] <TB1> INFO: Test took 51996ms.
[13:11:08.189] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 26.727585 .. 48.373611
[13:11:08.423] <TB1> INFO: Expecting 208000 events.
[13:11:18.174] <TB1> INFO: 208000 events read in total (9159ms).
[13:11:18.175] <TB1> INFO: Test took 9985ms.
[13:11:18.242] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 58 (-1/-1) hits flags = 528 (plus default)
[13:11:18.253] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:11:18.253] <TB1> INFO: run 1 of 1
[13:11:18.531] <TB1> INFO: Expecting 1431040 events.
[13:11:46.560] <TB1> INFO: 653288 events read in total (27437ms).
[13:12:13.706] <TB1> INFO: 1305000 events read in total (54583ms).
[13:12:19.432] <TB1> INFO: 1431040 events read in total (60309ms).
[13:12:19.462] <TB1> INFO: Test took 61209ms.
[13:12:32.257] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 26.224736 .. 50.654874
[13:12:32.489] <TB1> INFO: Expecting 208000 events.
[13:12:42.170] <TB1> INFO: 208000 events read in total (9089ms).
[13:12:42.171] <TB1> INFO: Test took 9913ms.
[13:12:42.217] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 60 (-1/-1) hits flags = 528 (plus default)
[13:12:42.226] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:12:42.226] <TB1> INFO: run 1 of 1
[13:12:42.504] <TB1> INFO: Expecting 1497600 events.
[13:13:09.543] <TB1> INFO: 646224 events read in total (26447ms).
[13:13:36.379] <TB1> INFO: 1292160 events read in total (53283ms).
[13:13:45.342] <TB1> INFO: 1497600 events read in total (62246ms).
[13:13:45.375] <TB1> INFO: Test took 63149ms.
[13:13:58.723] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[13:13:58.723] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[13:13:58.733] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:13:58.733] <TB1> INFO: run 1 of 1
[13:13:58.964] <TB1> INFO: Expecting 1364480 events.
[13:14:26.543] <TB1> INFO: 668368 events read in total (26987ms).
[13:14:53.685] <TB1> INFO: 1335424 events read in total (54129ms).
[13:14:55.261] <TB1> INFO: 1364480 events read in total (55706ms).
[13:14:55.284] <TB1> INFO: Test took 56550ms.
[13:15:08.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C0.dat
[13:15:08.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C1.dat
[13:15:08.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C2.dat
[13:15:08.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C3.dat
[13:15:08.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C4.dat
[13:15:08.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C5.dat
[13:15:08.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C6.dat
[13:15:08.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C7.dat
[13:15:08.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C8.dat
[13:15:08.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C9.dat
[13:15:08.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C10.dat
[13:15:08.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C11.dat
[13:15:08.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C12.dat
[13:15:08.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C13.dat
[13:15:08.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C14.dat
[13:15:08.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C15.dat
[13:15:08.903] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C0.dat
[13:15:08.911] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C1.dat
[13:15:08.919] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C2.dat
[13:15:08.927] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C3.dat
[13:15:08.936] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C4.dat
[13:15:08.944] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C5.dat
[13:15:08.952] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C6.dat
[13:15:08.960] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C7.dat
[13:15:08.968] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C8.dat
[13:15:08.976] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C9.dat
[13:15:08.984] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C10.dat
[13:15:08.993] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C11.dat
[13:15:08.001] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C12.dat
[13:15:09.009] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C13.dat
[13:15:09.017] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C14.dat
[13:15:09.025] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C15.dat
[13:15:09.033] <TB1> INFO: PixTestTrim::trimTest() done
[13:15:09.033] <TB1> INFO: vtrim: 132 137 134 137 146 141 136 158 140 176 136 166 134 128 150 131
[13:15:09.033] <TB1> INFO: vthrcomp: 115 131 126 126 120 125 129 127 130 132 130 132 128 119 118 124
[13:15:09.033] <TB1> INFO: vcal mean: 34.98 34.94 34.95 34.93 35.13 34.96 34.98 35.63 34.95 35.12 35.01 36.21 34.98 35.12 34.94 34.95
[13:15:09.033] <TB1> INFO: vcal RMS: 1.04 1.05 0.97 1.02 1.23 0.93 1.00 1.90 1.09 1.28 1.02 2.43 0.96 1.24 1.04 1.01
[13:15:09.033] <TB1> INFO: bits mean: 10.11 10.36 10.12 10.33 9.60 10.27 9.73 10.13 10.60 9.64 9.85 9.82 9.53 10.54 10.51 10.66
[13:15:09.033] <TB1> INFO: bits RMS: 2.42 2.40 2.33 2.42 2.52 2.40 2.63 2.57 2.33 2.42 2.47 2.45 2.51 2.40 2.27 2.20
[13:15:09.040] <TB1> INFO: ----------------------------------------------------------------------
[13:15:09.040] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:15:09.040] <TB1> INFO: ----------------------------------------------------------------------
[13:15:09.043] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:15:09.054] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:15:09.054] <TB1> INFO: run 1 of 1
[13:15:09.287] <TB1> INFO: Expecting 4160000 events.
[13:15:41.274] <TB1> INFO: 757090 events read in total (31396ms).
[13:16:12.933] <TB1> INFO: 1509560 events read in total (63055ms).
[13:16:44.354] <TB1> INFO: 2258000 events read in total (94476ms).
[13:17:15.896] <TB1> INFO: 3002185 events read in total (126018ms).
[13:17:47.125] <TB1> INFO: 3743525 events read in total (157247ms).
[13:18:04.658] <TB1> INFO: 4160000 events read in total (174780ms).
[13:18:04.705] <TB1> INFO: Test took 175651ms.
[13:18:33.028] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[13:18:33.040] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:18:33.040] <TB1> INFO: run 1 of 1
[13:18:33.313] <TB1> INFO: Expecting 4305600 events.
[13:19:04.885] <TB1> INFO: 725285 events read in total (30980ms).
[13:19:35.658] <TB1> INFO: 1446725 events read in total (61753ms).
[13:20:06.323] <TB1> INFO: 2165300 events read in total (92419ms).
[13:20:37.224] <TB1> INFO: 2878595 events read in total (123319ms).
[13:21:07.594] <TB1> INFO: 3590650 events read in total (153689ms).
[13:21:37.991] <TB1> INFO: 4302750 events read in total (184086ms).
[13:21:38.522] <TB1> INFO: 4305600 events read in total (184617ms).
[13:21:38.572] <TB1> INFO: Test took 185533ms.
[13:22:08.979] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[13:22:08.989] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:22:08.989] <TB1> INFO: run 1 of 1
[13:22:09.259] <TB1> INFO: Expecting 4430400 events.
[13:22:40.582] <TB1> INFO: 718305 events read in total (30731ms).
[13:23:11.120] <TB1> INFO: 1433035 events read in total (61269ms).
[13:23:41.597] <TB1> INFO: 2145260 events read in total (91746ms).
[13:24:11.768] <TB1> INFO: 2852465 events read in total (121917ms).
[13:24:41.951] <TB1> INFO: 3558100 events read in total (152100ms).
[13:25:12.216] <TB1> INFO: 4262195 events read in total (182365ms).
[13:25:19.776] <TB1> INFO: 4430400 events read in total (189925ms).
[13:25:19.849] <TB1> INFO: Test took 190859ms.
[13:25:51.952] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 213 (-1/-1) hits flags = 528 (plus default)
[13:25:51.962] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:25:51.962] <TB1> INFO: run 1 of 1
[13:25:52.195] <TB1> INFO: Expecting 4451200 events.
[13:26:23.594] <TB1> INFO: 717265 events read in total (30807ms).
[13:26:54.391] <TB1> INFO: 1430975 events read in total (61604ms).
[13:27:25.046] <TB1> INFO: 2142155 events read in total (92259ms).
[13:27:55.008] <TB1> INFO: 2848560 events read in total (122221ms).
[13:28:24.880] <TB1> INFO: 3553450 events read in total (152093ms).
[13:28:55.111] <TB1> INFO: 4256665 events read in total (182324ms).
[13:29:03.960] <TB1> INFO: 4451200 events read in total (191173ms).
[13:29:04.022] <TB1> INFO: Test took 192060ms.
[13:29:33.209] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[13:29:33.219] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:29:33.219] <TB1> INFO: run 1 of 1
[13:29:33.452] <TB1> INFO: Expecting 4472000 events.
[13:30:04.690] <TB1> INFO: 716180 events read in total (30646ms).
[13:30:34.908] <TB1> INFO: 1429010 events read in total (60864ms).
[13:31:04.001] <TB1> INFO: 2139235 events read in total (90957ms).
[13:31:35.232] <TB1> INFO: 2844890 events read in total (121188ms).
[13:32:05.568] <TB1> INFO: 3548695 events read in total (151524ms).
[13:32:36.075] <TB1> INFO: 4250525 events read in total (182031ms).
[13:32:45.820] <TB1> INFO: 4472000 events read in total (191776ms).
[13:32:45.881] <TB1> INFO: Test took 192662ms.
[13:33:14.015] <TB1> INFO: PixTestTrim::trimBitTest() done
[13:33:14.016] <TB1> INFO: PixTestTrim::doTest() done, duration: 2500 seconds
[13:33:14.016] <TB1> INFO: Decoding statistics:
[13:33:14.016] <TB1> INFO: General information:
[13:33:14.016] <TB1> INFO: 16bit words read: 0
[13:33:14.016] <TB1> INFO: valid events total: 0
[13:33:14.016] <TB1> INFO: empty events: 0
[13:33:14.016] <TB1> INFO: valid events with pixels: 0
[13:33:14.016] <TB1> INFO: valid pixel hits: 0
[13:33:14.016] <TB1> INFO: Event errors: 0
[13:33:14.016] <TB1> INFO: start marker: 0
[13:33:14.016] <TB1> INFO: stop marker: 0
[13:33:14.016] <TB1> INFO: overflow: 0
[13:33:14.016] <TB1> INFO: invalid 5bit words: 0
[13:33:14.016] <TB1> INFO: invalid XOR eye diagram: 0
[13:33:14.016] <TB1> INFO: frame (failed synchr.): 0
[13:33:14.016] <TB1> INFO: idle data (no TBM trl): 0
[13:33:14.016] <TB1> INFO: no data (only TBM hdr): 0
[13:33:14.016] <TB1> INFO: TBM errors: 0
[13:33:14.016] <TB1> INFO: flawed TBM headers: 0
[13:33:14.016] <TB1> INFO: flawed TBM trailers: 0
[13:33:14.016] <TB1> INFO: event ID mismatches: 0
[13:33:14.016] <TB1> INFO: ROC errors: 0
[13:33:14.016] <TB1> INFO: missing ROC header(s): 0
[13:33:14.016] <TB1> INFO: misplaced readback start: 0
[13:33:14.016] <TB1> INFO: Pixel decoding errors: 0
[13:33:14.016] <TB1> INFO: pixel data incomplete: 0
[13:33:14.016] <TB1> INFO: pixel address: 0
[13:33:14.017] <TB1> INFO: pulse height fill bit: 0
[13:33:14.017] <TB1> INFO: buffer corruption: 0
[13:33:14.699] <TB1> INFO: ######################################################################
[13:33:14.699] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:33:14.699] <TB1> INFO: ######################################################################
[13:33:14.933] <TB1> INFO: Expecting 41600 events.
[13:33:18.411] <TB1> INFO: 41600 events read in total (2886ms).
[13:33:18.412] <TB1> INFO: Test took 3712ms.
[13:33:18.851] <TB1> INFO: Expecting 41600 events.
[13:33:22.319] <TB1> INFO: 41600 events read in total (2876ms).
[13:33:22.320] <TB1> INFO: Test took 3706ms.
[13:33:22.614] <TB1> INFO: Expecting 41600 events.
[13:33:26.080] <TB1> INFO: 41600 events read in total (2875ms).
[13:33:26.081] <TB1> INFO: Test took 3737ms.
[13:33:26.369] <TB1> INFO: Expecting 41600 events.
[13:33:29.882] <TB1> INFO: 41600 events read in total (2921ms).
[13:33:29.883] <TB1> INFO: Test took 3779ms.
[13:33:30.172] <TB1> INFO: Expecting 41600 events.
[13:33:33.701] <TB1> INFO: 41600 events read in total (2938ms).
[13:33:33.702] <TB1> INFO: Test took 3795ms.
[13:33:33.989] <TB1> INFO: Expecting 41600 events.
[13:33:37.554] <TB1> INFO: 41600 events read in total (2973ms).
[13:33:37.555] <TB1> INFO: Test took 3830ms.
[13:33:37.845] <TB1> INFO: Expecting 41600 events.
[13:33:41.412] <TB1> INFO: 41600 events read in total (2975ms).
[13:33:41.413] <TB1> INFO: Test took 3832ms.
[13:33:41.701] <TB1> INFO: Expecting 41600 events.
[13:33:45.268] <TB1> INFO: 41600 events read in total (2975ms).
[13:33:45.269] <TB1> INFO: Test took 3832ms.
[13:33:45.557] <TB1> INFO: Expecting 41600 events.
[13:33:49.126] <TB1> INFO: 41600 events read in total (2977ms).
[13:33:49.127] <TB1> INFO: Test took 3835ms.
[13:33:49.416] <TB1> INFO: Expecting 41600 events.
[13:33:52.885] <TB1> INFO: 41600 events read in total (2878ms).
[13:33:52.886] <TB1> INFO: Test took 3735ms.
[13:33:53.178] <TB1> INFO: Expecting 41600 events.
[13:33:56.635] <TB1> INFO: 41600 events read in total (2866ms).
[13:33:56.636] <TB1> INFO: Test took 3726ms.
[13:33:56.933] <TB1> INFO: Expecting 41600 events.
[13:34:00.495] <TB1> INFO: 41600 events read in total (2971ms).
[13:34:00.496] <TB1> INFO: Test took 3837ms.
[13:34:00.786] <TB1> INFO: Expecting 41600 events.
[13:34:04.238] <TB1> INFO: 41600 events read in total (2860ms).
[13:34:04.239] <TB1> INFO: Test took 3717ms.
[13:34:04.527] <TB1> INFO: Expecting 41600 events.
[13:34:08.139] <TB1> INFO: 41600 events read in total (3020ms).
[13:34:08.139] <TB1> INFO: Test took 3877ms.
[13:34:08.429] <TB1> INFO: Expecting 41600 events.
[13:34:11.932] <TB1> INFO: 41600 events read in total (2912ms).
[13:34:11.933] <TB1> INFO: Test took 3770ms.
[13:34:12.221] <TB1> INFO: Expecting 41600 events.
[13:34:15.772] <TB1> INFO: 41600 events read in total (2959ms).
[13:34:15.772] <TB1> INFO: Test took 3815ms.
[13:34:16.060] <TB1> INFO: Expecting 41600 events.
[13:34:19.585] <TB1> INFO: 41600 events read in total (2933ms).
[13:34:19.586] <TB1> INFO: Test took 3790ms.
[13:34:19.877] <TB1> INFO: Expecting 41600 events.
[13:34:23.474] <TB1> INFO: 41600 events read in total (3006ms).
[13:34:23.475] <TB1> INFO: Test took 3863ms.
[13:34:23.763] <TB1> INFO: Expecting 41600 events.
[13:34:27.217] <TB1> INFO: 41600 events read in total (2863ms).
[13:34:27.218] <TB1> INFO: Test took 3720ms.
[13:34:27.506] <TB1> INFO: Expecting 41600 events.
[13:34:30.993] <TB1> INFO: 41600 events read in total (2895ms).
[13:34:30.993] <TB1> INFO: Test took 3751ms.
[13:34:31.284] <TB1> INFO: Expecting 41600 events.
[13:34:34.842] <TB1> INFO: 41600 events read in total (2967ms).
[13:34:34.843] <TB1> INFO: Test took 3824ms.
[13:34:35.139] <TB1> INFO: Expecting 41600 events.
[13:34:38.581] <TB1> INFO: 41600 events read in total (2850ms).
[13:34:38.582] <TB1> INFO: Test took 3716ms.
[13:34:38.881] <TB1> INFO: Expecting 41600 events.
[13:34:42.494] <TB1> INFO: 41600 events read in total (3022ms).
[13:34:42.495] <TB1> INFO: Test took 3890ms.
[13:34:42.796] <TB1> INFO: Expecting 41600 events.
[13:34:46.329] <TB1> INFO: 41600 events read in total (2941ms).
[13:34:46.330] <TB1> INFO: Test took 3809ms.
[13:34:46.617] <TB1> INFO: Expecting 41600 events.
[13:34:50.094] <TB1> INFO: 41600 events read in total (2885ms).
[13:34:50.095] <TB1> INFO: Test took 3742ms.
[13:34:50.383] <TB1> INFO: Expecting 41600 events.
[13:34:53.845] <TB1> INFO: 41600 events read in total (2870ms).
[13:34:53.845] <TB1> INFO: Test took 3726ms.
[13:34:54.133] <TB1> INFO: Expecting 41600 events.
[13:34:57.610] <TB1> INFO: 41600 events read in total (2885ms).
[13:34:57.611] <TB1> INFO: Test took 3742ms.
[13:34:57.900] <TB1> INFO: Expecting 41600 events.
[13:35:01.492] <TB1> INFO: 41600 events read in total (3000ms).
[13:35:01.493] <TB1> INFO: Test took 3857ms.
[13:35:01.782] <TB1> INFO: Expecting 2560 events.
[13:35:02.666] <TB1> INFO: 2560 events read in total (292ms).
[13:35:02.666] <TB1> INFO: Test took 1161ms.
[13:35:02.974] <TB1> INFO: Expecting 2560 events.
[13:35:03.859] <TB1> INFO: 2560 events read in total (293ms).
[13:35:03.859] <TB1> INFO: Test took 1192ms.
[13:35:04.167] <TB1> INFO: Expecting 2560 events.
[13:35:05.050] <TB1> INFO: 2560 events read in total (291ms).
[13:35:05.050] <TB1> INFO: Test took 1190ms.
[13:35:05.358] <TB1> INFO: Expecting 2560 events.
[13:35:06.243] <TB1> INFO: 2560 events read in total (294ms).
[13:35:06.243] <TB1> INFO: Test took 1193ms.
[13:35:06.551] <TB1> INFO: Expecting 2560 events.
[13:35:07.429] <TB1> INFO: 2560 events read in total (286ms).
[13:35:07.429] <TB1> INFO: Test took 1185ms.
[13:35:07.737] <TB1> INFO: Expecting 2560 events.
[13:35:08.617] <TB1> INFO: 2560 events read in total (288ms).
[13:35:08.617] <TB1> INFO: Test took 1189ms.
[13:35:08.925] <TB1> INFO: Expecting 2560 events.
[13:35:09.806] <TB1> INFO: 2560 events read in total (289ms).
[13:35:09.806] <TB1> INFO: Test took 1188ms.
[13:35:10.114] <TB1> INFO: Expecting 2560 events.
[13:35:10.992] <TB1> INFO: 2560 events read in total (287ms).
[13:35:10.992] <TB1> INFO: Test took 1186ms.
[13:35:11.300] <TB1> INFO: Expecting 2560 events.
[13:35:12.180] <TB1> INFO: 2560 events read in total (288ms).
[13:35:12.181] <TB1> INFO: Test took 1188ms.
[13:35:12.488] <TB1> INFO: Expecting 2560 events.
[13:35:13.367] <TB1> INFO: 2560 events read in total (287ms).
[13:35:13.368] <TB1> INFO: Test took 1187ms.
[13:35:13.674] <TB1> INFO: Expecting 2560 events.
[13:35:14.553] <TB1> INFO: 2560 events read in total (287ms).
[13:35:14.554] <TB1> INFO: Test took 1186ms.
[13:35:14.862] <TB1> INFO: Expecting 2560 events.
[13:35:15.741] <TB1> INFO: 2560 events read in total (288ms).
[13:35:15.741] <TB1> INFO: Test took 1187ms.
[13:35:16.049] <TB1> INFO: Expecting 2560 events.
[13:35:16.932] <TB1> INFO: 2560 events read in total (291ms).
[13:35:16.932] <TB1> INFO: Test took 1190ms.
[13:35:17.240] <TB1> INFO: Expecting 2560 events.
[13:35:18.123] <TB1> INFO: 2560 events read in total (291ms).
[13:35:18.123] <TB1> INFO: Test took 1190ms.
[13:35:18.431] <TB1> INFO: Expecting 2560 events.
[13:35:19.314] <TB1> INFO: 2560 events read in total (291ms).
[13:35:19.314] <TB1> INFO: Test took 1190ms.
[13:35:19.622] <TB1> INFO: Expecting 2560 events.
[13:35:20.503] <TB1> INFO: 2560 events read in total (290ms).
[13:35:20.504] <TB1> INFO: Test took 1189ms.
[13:35:20.507] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:35:20.813] <TB1> INFO: Expecting 655360 events.
[13:35:35.159] <TB1> INFO: 655360 events read in total (13755ms).
[13:35:35.173] <TB1> INFO: Expecting 655360 events.
[13:35:49.360] <TB1> INFO: 655360 events read in total (13784ms).
[13:35:49.375] <TB1> INFO: Expecting 655360 events.
[13:36:03.493] <TB1> INFO: 655360 events read in total (13715ms).
[13:36:03.511] <TB1> INFO: Expecting 655360 events.
[13:36:17.606] <TB1> INFO: 655360 events read in total (13692ms).
[13:36:17.629] <TB1> INFO: Expecting 655360 events.
[13:36:31.788] <TB1> INFO: 655360 events read in total (13749ms).
[13:36:31.817] <TB1> INFO: Expecting 655360 events.
[13:36:45.899] <TB1> INFO: 655360 events read in total (13679ms).
[13:36:45.932] <TB1> INFO: Expecting 655360 events.
[13:37:00.010] <TB1> INFO: 655360 events read in total (13675ms).
[13:37:00.057] <TB1> INFO: Expecting 655360 events.
[13:37:14.098] <TB1> INFO: 655360 events read in total (13638ms).
[13:37:14.137] <TB1> INFO: Expecting 655360 events.
[13:37:28.278] <TB1> INFO: 655360 events read in total (13738ms).
[13:37:28.327] <TB1> INFO: Expecting 655360 events.
[13:37:42.373] <TB1> INFO: 655360 events read in total (13643ms).
[13:37:42.422] <TB1> INFO: Expecting 655360 events.
[13:37:56.506] <TB1> INFO: 655360 events read in total (13681ms).
[13:37:56.577] <TB1> INFO: Expecting 655360 events.
[13:38:10.706] <TB1> INFO: 655360 events read in total (13726ms).
[13:38:10.781] <TB1> INFO: Expecting 655360 events.
[13:38:24.997] <TB1> INFO: 655360 events read in total (13813ms).
[13:38:25.079] <TB1> INFO: Expecting 655360 events.
[13:38:39.178] <TB1> INFO: 655360 events read in total (13696ms).
[13:38:39.244] <TB1> INFO: Expecting 655360 events.
[13:38:53.272] <TB1> INFO: 655360 events read in total (13625ms).
[13:38:53.342] <TB1> INFO: Expecting 655360 events.
[13:39:07.504] <TB1> INFO: 655360 events read in total (13759ms).
[13:39:07.603] <TB1> INFO: Test took 227097ms.
[13:39:07.698] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:07.965] <TB1> INFO: Expecting 655360 events.
[13:39:22.233] <TB1> INFO: 655360 events read in total (13676ms).
[13:39:22.243] <TB1> INFO: Expecting 655360 events.
[13:39:36.029] <TB1> INFO: 655360 events read in total (13383ms).
[13:39:36.044] <TB1> INFO: Expecting 655360 events.
[13:39:50.107] <TB1> INFO: 655360 events read in total (13660ms).
[13:39:50.131] <TB1> INFO: Expecting 655360 events.
[13:40:04.171] <TB1> INFO: 655360 events read in total (13636ms).
[13:40:04.203] <TB1> INFO: Expecting 655360 events.
[13:40:17.846] <TB1> INFO: 655360 events read in total (13240ms).
[13:40:17.870] <TB1> INFO: Expecting 655360 events.
[13:40:31.788] <TB1> INFO: 655360 events read in total (13515ms).
[13:40:31.828] <TB1> INFO: Expecting 655360 events.
[13:40:45.871] <TB1> INFO: 655360 events read in total (13640ms).
[13:40:45.915] <TB1> INFO: Expecting 655360 events.
[13:40:59.812] <TB1> INFO: 655360 events read in total (13494ms).
[13:40:59.850] <TB1> INFO: Expecting 655360 events.
[13:41:13.705] <TB1> INFO: 655360 events read in total (13451ms).
[13:41:13.751] <TB1> INFO: Expecting 655360 events.
[13:41:27.748] <TB1> INFO: 655360 events read in total (13594ms).
[13:41:27.795] <TB1> INFO: Expecting 655360 events.
[13:41:41.688] <TB1> INFO: 655360 events read in total (13490ms).
[13:41:41.757] <TB1> INFO: Expecting 655360 events.
[13:41:55.464] <TB1> INFO: 655360 events read in total (13304ms).
[13:41:55.519] <TB1> INFO: Expecting 655360 events.
[13:42:09.258] <TB1> INFO: 655360 events read in total (13336ms).
[13:42:09.339] <TB1> INFO: Expecting 655360 events.
[13:42:23.224] <TB1> INFO: 655360 events read in total (13482ms).
[13:42:23.311] <TB1> INFO: Expecting 655360 events.
[13:42:37.338] <TB1> INFO: 655360 events read in total (13624ms).
[13:42:37.431] <TB1> INFO: Expecting 655360 events.
[13:42:51.466] <TB1> INFO: 655360 events read in total (13632ms).
[13:42:51.540] <TB1> INFO: Test took 223842ms.
[13:42:51.697] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.701] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:42:51.706] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:42:51.711] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:42:51.715] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:42:51.719] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:42:51.724] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[13:42:51.729] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[13:42:51.734] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[13:42:51.740] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[13:42:51.745] <TB1> INFO: safety margin for low PH: adding 10, margin is now 30
[13:42:51.751] <TB1> INFO: safety margin for low PH: adding 11, margin is now 31
[13:42:51.756] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.760] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:42:51.765] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.771] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.775] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:42:51.780] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:42:51.785] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.790] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:42:51.795] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:42:51.800] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:42:51.804] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:42:51.809] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:42:51.814] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[13:42:51.819] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[13:42:51.825] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[13:42:51.831] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[13:42:51.837] <TB1> INFO: safety margin for low PH: adding 10, margin is now 30
[13:42:51.842] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.848] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.854] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.859] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.864] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:42:51.870] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:42:51.874] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:42:51.879] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:42:51.884] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:42:51.890] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[13:42:51.896] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[13:42:51.901] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[13:42:51.906] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[13:42:51.911] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.916] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.921] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:42:51.926] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:42:51.931] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:42:51.936] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:42:51.941] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:42:51.946] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.951] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.956] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.961] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:42:51.966] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.970] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:42:51.975] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:42:51.980] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:42:51.985] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:42:51.990] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:42:51.996] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:42:51.001] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[13:42:52.006] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[13:42:52.011] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[13:42:52.044] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C0.dat
[13:42:52.044] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C1.dat
[13:42:52.045] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C2.dat
[13:42:52.045] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C3.dat
[13:42:52.045] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C4.dat
[13:42:52.045] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C5.dat
[13:42:52.045] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C6.dat
[13:42:52.045] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C7.dat
[13:42:52.045] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C8.dat
[13:42:52.045] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C9.dat
[13:42:52.045] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C10.dat
[13:42:52.045] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C11.dat
[13:42:52.045] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C12.dat
[13:42:52.045] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C13.dat
[13:42:52.046] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C14.dat
[13:42:52.046] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C15.dat
[13:42:52.282] <TB1> INFO: Expecting 41600 events.
[13:42:55.429] <TB1> INFO: 41600 events read in total (2555ms).
[13:42:55.430] <TB1> INFO: Test took 3382ms.
[13:42:55.872] <TB1> INFO: Expecting 41600 events.
[13:42:58.898] <TB1> INFO: 41600 events read in total (2434ms).
[13:42:58.899] <TB1> INFO: Test took 3258ms.
[13:42:59.340] <TB1> INFO: Expecting 41600 events.
[13:43:02.437] <TB1> INFO: 41600 events read in total (2505ms).
[13:43:02.438] <TB1> INFO: Test took 3329ms.
[13:43:02.652] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:02.740] <TB1> INFO: Expecting 2560 events.
[13:43:03.623] <TB1> INFO: 2560 events read in total (291ms).
[13:43:03.624] <TB1> INFO: Test took 972ms.
[13:43:03.626] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:03.932] <TB1> INFO: Expecting 2560 events.
[13:43:04.814] <TB1> INFO: 2560 events read in total (290ms).
[13:43:04.814] <TB1> INFO: Test took 1188ms.
[13:43:04.816] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:05.122] <TB1> INFO: Expecting 2560 events.
[13:43:06.008] <TB1> INFO: 2560 events read in total (294ms).
[13:43:06.008] <TB1> INFO: Test took 1192ms.
[13:43:06.010] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:06.316] <TB1> INFO: Expecting 2560 events.
[13:43:07.199] <TB1> INFO: 2560 events read in total (291ms).
[13:43:07.199] <TB1> INFO: Test took 1189ms.
[13:43:07.201] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:07.507] <TB1> INFO: Expecting 2560 events.
[13:43:08.390] <TB1> INFO: 2560 events read in total (291ms).
[13:43:08.391] <TB1> INFO: Test took 1190ms.
[13:43:08.393] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:08.699] <TB1> INFO: Expecting 2560 events.
[13:43:09.586] <TB1> INFO: 2560 events read in total (295ms).
[13:43:09.586] <TB1> INFO: Test took 1194ms.
[13:43:09.588] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:09.894] <TB1> INFO: Expecting 2560 events.
[13:43:10.777] <TB1> INFO: 2560 events read in total (291ms).
[13:43:10.777] <TB1> INFO: Test took 1190ms.
[13:43:10.779] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:11.085] <TB1> INFO: Expecting 2560 events.
[13:43:11.969] <TB1> INFO: 2560 events read in total (292ms).
[13:43:11.969] <TB1> INFO: Test took 1190ms.
[13:43:11.971] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:12.277] <TB1> INFO: Expecting 2560 events.
[13:43:13.156] <TB1> INFO: 2560 events read in total (287ms).
[13:43:13.157] <TB1> INFO: Test took 1186ms.
[13:43:13.158] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:13.465] <TB1> INFO: Expecting 2560 events.
[13:43:14.347] <TB1> INFO: 2560 events read in total (290ms).
[13:43:14.347] <TB1> INFO: Test took 1189ms.
[13:43:14.349] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:14.656] <TB1> INFO: Expecting 2560 events.
[13:43:15.534] <TB1> INFO: 2560 events read in total (286ms).
[13:43:15.535] <TB1> INFO: Test took 1186ms.
[13:43:15.537] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:15.843] <TB1> INFO: Expecting 2560 events.
[13:43:16.722] <TB1> INFO: 2560 events read in total (287ms).
[13:43:16.722] <TB1> INFO: Test took 1185ms.
[13:43:16.724] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:17.031] <TB1> INFO: Expecting 2560 events.
[13:43:17.911] <TB1> INFO: 2560 events read in total (289ms).
[13:43:17.911] <TB1> INFO: Test took 1187ms.
[13:43:17.913] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:18.219] <TB1> INFO: Expecting 2560 events.
[13:43:19.097] <TB1> INFO: 2560 events read in total (286ms).
[13:43:19.097] <TB1> INFO: Test took 1184ms.
[13:43:19.099] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:19.406] <TB1> INFO: Expecting 2560 events.
[13:43:20.284] <TB1> INFO: 2560 events read in total (287ms).
[13:43:20.284] <TB1> INFO: Test took 1185ms.
[13:43:20.287] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:20.593] <TB1> INFO: Expecting 2560 events.
[13:43:21.470] <TB1> INFO: 2560 events read in total (286ms).
[13:43:21.470] <TB1> INFO: Test took 1183ms.
[13:43:21.472] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:21.779] <TB1> INFO: Expecting 2560 events.
[13:43:22.657] <TB1> INFO: 2560 events read in total (287ms).
[13:43:22.657] <TB1> INFO: Test took 1185ms.
[13:43:22.659] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:22.965] <TB1> INFO: Expecting 2560 events.
[13:43:23.844] <TB1> INFO: 2560 events read in total (287ms).
[13:43:23.844] <TB1> INFO: Test took 1185ms.
[13:43:23.846] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:24.152] <TB1> INFO: Expecting 2560 events.
[13:43:25.032] <TB1> INFO: 2560 events read in total (288ms).
[13:43:25.032] <TB1> INFO: Test took 1186ms.
[13:43:25.034] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:25.340] <TB1> INFO: Expecting 2560 events.
[13:43:26.221] <TB1> INFO: 2560 events read in total (289ms).
[13:43:26.221] <TB1> INFO: Test took 1187ms.
[13:43:26.223] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:26.530] <TB1> INFO: Expecting 2560 events.
[13:43:27.408] <TB1> INFO: 2560 events read in total (287ms).
[13:43:27.409] <TB1> INFO: Test took 1186ms.
[13:43:27.410] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:27.717] <TB1> INFO: Expecting 2560 events.
[13:43:28.596] <TB1> INFO: 2560 events read in total (287ms).
[13:43:28.596] <TB1> INFO: Test took 1186ms.
[13:43:28.598] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:28.905] <TB1> INFO: Expecting 2560 events.
[13:43:29.784] <TB1> INFO: 2560 events read in total (288ms).
[13:43:29.784] <TB1> INFO: Test took 1186ms.
[13:43:29.786] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:30.093] <TB1> INFO: Expecting 2560 events.
[13:43:30.971] <TB1> INFO: 2560 events read in total (287ms).
[13:43:30.971] <TB1> INFO: Test took 1185ms.
[13:43:30.974] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:31.279] <TB1> INFO: Expecting 2560 events.
[13:43:32.162] <TB1> INFO: 2560 events read in total (291ms).
[13:43:32.162] <TB1> INFO: Test took 1189ms.
[13:43:32.164] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:32.470] <TB1> INFO: Expecting 2560 events.
[13:43:33.353] <TB1> INFO: 2560 events read in total (291ms).
[13:43:33.353] <TB1> INFO: Test took 1189ms.
[13:43:33.355] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:33.661] <TB1> INFO: Expecting 2560 events.
[13:43:34.544] <TB1> INFO: 2560 events read in total (291ms).
[13:43:34.545] <TB1> INFO: Test took 1190ms.
[13:43:34.546] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:34.853] <TB1> INFO: Expecting 2560 events.
[13:43:35.736] <TB1> INFO: 2560 events read in total (291ms).
[13:43:35.736] <TB1> INFO: Test took 1190ms.
[13:43:35.738] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:36.044] <TB1> INFO: Expecting 2560 events.
[13:43:36.927] <TB1> INFO: 2560 events read in total (291ms).
[13:43:36.927] <TB1> INFO: Test took 1189ms.
[13:43:36.929] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:37.236] <TB1> INFO: Expecting 2560 events.
[13:43:38.122] <TB1> INFO: 2560 events read in total (295ms).
[13:43:38.122] <TB1> INFO: Test took 1193ms.
[13:43:38.124] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:38.430] <TB1> INFO: Expecting 2560 events.
[13:43:39.314] <TB1> INFO: 2560 events read in total (291ms).
[13:43:39.314] <TB1> INFO: Test took 1190ms.
[13:43:39.316] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:39.623] <TB1> INFO: Expecting 2560 events.
[13:43:40.508] <TB1> INFO: 2560 events read in total (294ms).
[13:43:40.508] <TB1> INFO: Test took 1192ms.
[13:43:40.969] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 626 seconds
[13:43:40.969] <TB1> INFO: PH scale (per ROC): 49 44 60 35 45 46 34 37 48 42 48 38 45 41 46 39
[13:43:40.969] <TB1> INFO: PH offset (per ROC): 112 101 117 96 96 99 100 108 96 99 113 111 102 94 99 112
[13:43:40.974] <TB1> INFO: Decoding statistics:
[13:43:40.974] <TB1> INFO: General information:
[13:43:40.974] <TB1> INFO: 16bit words read: 127884
[13:43:40.974] <TB1> INFO: valid events total: 20480
[13:43:40.974] <TB1> INFO: empty events: 17978
[13:43:40.974] <TB1> INFO: valid events with pixels: 2502
[13:43:40.974] <TB1> INFO: valid pixel hits: 2502
[13:43:40.975] <TB1> INFO: Event errors: 0
[13:43:40.975] <TB1> INFO: start marker: 0
[13:43:40.975] <TB1> INFO: stop marker: 0
[13:43:40.975] <TB1> INFO: overflow: 0
[13:43:40.975] <TB1> INFO: invalid 5bit words: 0
[13:43:40.975] <TB1> INFO: invalid XOR eye diagram: 0
[13:43:40.975] <TB1> INFO: frame (failed synchr.): 0
[13:43:40.975] <TB1> INFO: idle data (no TBM trl): 0
[13:43:40.975] <TB1> INFO: no data (only TBM hdr): 0
[13:43:40.975] <TB1> INFO: TBM errors: 0
[13:43:40.975] <TB1> INFO: flawed TBM headers: 0
[13:43:40.975] <TB1> INFO: flawed TBM trailers: 0
[13:43:40.975] <TB1> INFO: event ID mismatches: 0
[13:43:40.975] <TB1> INFO: ROC errors: 0
[13:43:40.975] <TB1> INFO: missing ROC header(s): 0
[13:43:40.975] <TB1> INFO: misplaced readback start: 0
[13:43:40.975] <TB1> INFO: Pixel decoding errors: 0
[13:43:40.975] <TB1> INFO: pixel data incomplete: 0
[13:43:40.975] <TB1> INFO: pixel address: 0
[13:43:40.975] <TB1> INFO: pulse height fill bit: 0
[13:43:40.975] <TB1> INFO: buffer corruption: 0
[13:43:41.243] <TB1> INFO: ######################################################################
[13:43:41.243] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:43:41.243] <TB1> INFO: ######################################################################
[13:43:41.253] <TB1> INFO: scanning low vcal = 10
[13:43:41.486] <TB1> INFO: Expecting 41600 events.
[13:43:45.034] <TB1> INFO: 41600 events read in total (2957ms).
[13:43:45.034] <TB1> INFO: Test took 3781ms.
[13:43:45.036] <TB1> INFO: scanning low vcal = 20
[13:43:45.335] <TB1> INFO: Expecting 41600 events.
[13:43:48.903] <TB1> INFO: 41600 events read in total (2976ms).
[13:43:48.904] <TB1> INFO: Test took 3868ms.
[13:43:48.906] <TB1> INFO: scanning low vcal = 30
[13:43:49.201] <TB1> INFO: Expecting 41600 events.
[13:43:52.820] <TB1> INFO: 41600 events read in total (3027ms).
[13:43:52.821] <TB1> INFO: Test took 3915ms.
[13:43:52.823] <TB1> INFO: scanning low vcal = 40
[13:43:53.100] <TB1> INFO: Expecting 41600 events.
[13:43:57.013] <TB1> INFO: 41600 events read in total (3322ms).
[13:43:57.014] <TB1> INFO: Test took 4191ms.
[13:43:57.017] <TB1> INFO: scanning low vcal = 50
[13:43:57.293] <TB1> INFO: Expecting 41600 events.
[13:44:01.254] <TB1> INFO: 41600 events read in total (3367ms).
[13:44:01.255] <TB1> INFO: Test took 4238ms.
[13:44:01.258] <TB1> INFO: scanning low vcal = 60
[13:44:01.534] <TB1> INFO: Expecting 41600 events.
[13:44:05.510] <TB1> INFO: 41600 events read in total (3384ms).
[13:44:05.511] <TB1> INFO: Test took 4253ms.
[13:44:05.514] <TB1> INFO: scanning low vcal = 70
[13:44:05.790] <TB1> INFO: Expecting 41600 events.
[13:44:09.720] <TB1> INFO: 41600 events read in total (3338ms).
[13:44:09.721] <TB1> INFO: Test took 4207ms.
[13:44:09.723] <TB1> INFO: scanning low vcal = 80
[13:44:09.001] <TB1> INFO: Expecting 41600 events.
[13:44:13.959] <TB1> INFO: 41600 events read in total (3366ms).
[13:44:13.960] <TB1> INFO: Test took 4236ms.
[13:44:13.962] <TB1> INFO: scanning low vcal = 90
[13:44:14.239] <TB1> INFO: Expecting 41600 events.
[13:44:18.194] <TB1> INFO: 41600 events read in total (3364ms).
[13:44:18.195] <TB1> INFO: Test took 4233ms.
[13:44:18.197] <TB1> INFO: scanning low vcal = 100
[13:44:18.474] <TB1> INFO: Expecting 41600 events.
[13:44:22.438] <TB1> INFO: 41600 events read in total (3373ms).
[13:44:22.439] <TB1> INFO: Test took 4242ms.
[13:44:22.442] <TB1> INFO: scanning low vcal = 110
[13:44:22.718] <TB1> INFO: Expecting 41600 events.
[13:44:26.651] <TB1> INFO: 41600 events read in total (3341ms).
[13:44:26.652] <TB1> INFO: Test took 4210ms.
[13:44:26.654] <TB1> INFO: scanning low vcal = 120
[13:44:26.931] <TB1> INFO: Expecting 41600 events.
[13:44:30.907] <TB1> INFO: 41600 events read in total (3385ms).
[13:44:30.907] <TB1> INFO: Test took 4253ms.
[13:44:30.910] <TB1> INFO: scanning low vcal = 130
[13:44:31.187] <TB1> INFO: Expecting 41600 events.
[13:44:35.124] <TB1> INFO: 41600 events read in total (3346ms).
[13:44:35.125] <TB1> INFO: Test took 4215ms.
[13:44:35.128] <TB1> INFO: scanning low vcal = 140
[13:44:35.404] <TB1> INFO: Expecting 41600 events.
[13:44:39.394] <TB1> INFO: 41600 events read in total (3398ms).
[13:44:39.395] <TB1> INFO: Test took 4267ms.
[13:44:39.397] <TB1> INFO: scanning low vcal = 150
[13:44:39.674] <TB1> INFO: Expecting 41600 events.
[13:44:43.616] <TB1> INFO: 41600 events read in total (3351ms).
[13:44:43.616] <TB1> INFO: Test took 4219ms.
[13:44:43.619] <TB1> INFO: scanning low vcal = 160
[13:44:43.895] <TB1> INFO: Expecting 41600 events.
[13:44:47.826] <TB1> INFO: 41600 events read in total (3339ms).
[13:44:47.826] <TB1> INFO: Test took 4207ms.
[13:44:47.829] <TB1> INFO: scanning low vcal = 170
[13:44:48.106] <TB1> INFO: Expecting 41600 events.
[13:44:52.098] <TB1> INFO: 41600 events read in total (3401ms).
[13:44:52.099] <TB1> INFO: Test took 4270ms.
[13:44:52.102] <TB1> INFO: scanning low vcal = 180
[13:44:52.379] <TB1> INFO: Expecting 41600 events.
[13:44:56.326] <TB1> INFO: 41600 events read in total (3356ms).
[13:44:56.326] <TB1> INFO: Test took 4224ms.
[13:44:56.329] <TB1> INFO: scanning low vcal = 190
[13:44:56.606] <TB1> INFO: Expecting 41600 events.
[13:45:00.560] <TB1> INFO: 41600 events read in total (3363ms).
[13:45:00.561] <TB1> INFO: Test took 4232ms.
[13:45:00.563] <TB1> INFO: scanning low vcal = 200
[13:45:00.840] <TB1> INFO: Expecting 41600 events.
[13:45:04.794] <TB1> INFO: 41600 events read in total (3363ms).
[13:45:04.795] <TB1> INFO: Test took 4232ms.
[13:45:04.798] <TB1> INFO: scanning low vcal = 210
[13:45:05.074] <TB1> INFO: Expecting 41600 events.
[13:45:09.022] <TB1> INFO: 41600 events read in total (3356ms).
[13:45:09.023] <TB1> INFO: Test took 4225ms.
[13:45:09.025] <TB1> INFO: scanning low vcal = 220
[13:45:09.302] <TB1> INFO: Expecting 41600 events.
[13:45:13.249] <TB1> INFO: 41600 events read in total (3355ms).
[13:45:13.250] <TB1> INFO: Test took 4224ms.
[13:45:13.252] <TB1> INFO: scanning low vcal = 230
[13:45:13.529] <TB1> INFO: Expecting 41600 events.
[13:45:17.461] <TB1> INFO: 41600 events read in total (3341ms).
[13:45:17.462] <TB1> INFO: Test took 4210ms.
[13:45:17.465] <TB1> INFO: scanning low vcal = 240
[13:45:17.741] <TB1> INFO: Expecting 41600 events.
[13:45:21.751] <TB1> INFO: 41600 events read in total (3418ms).
[13:45:21.752] <TB1> INFO: Test took 4287ms.
[13:45:21.755] <TB1> INFO: scanning low vcal = 250
[13:45:22.031] <TB1> INFO: Expecting 41600 events.
[13:45:26.027] <TB1> INFO: 41600 events read in total (3404ms).
[13:45:26.027] <TB1> INFO: Test took 4272ms.
[13:45:26.031] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[13:45:26.307] <TB1> INFO: Expecting 41600 events.
[13:45:30.277] <TB1> INFO: 41600 events read in total (3379ms).
[13:45:30.278] <TB1> INFO: Test took 4247ms.
[13:45:30.281] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[13:45:30.557] <TB1> INFO: Expecting 41600 events.
[13:45:34.536] <TB1> INFO: 41600 events read in total (3387ms).
[13:45:34.537] <TB1> INFO: Test took 4256ms.
[13:45:34.540] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[13:45:34.817] <TB1> INFO: Expecting 41600 events.
[13:45:38.801] <TB1> INFO: 41600 events read in total (3393ms).
[13:45:38.802] <TB1> INFO: Test took 4262ms.
[13:45:38.804] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[13:45:39.081] <TB1> INFO: Expecting 41600 events.
[13:45:43.036] <TB1> INFO: 41600 events read in total (3363ms).
[13:45:43.037] <TB1> INFO: Test took 4233ms.
[13:45:43.039] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:45:43.316] <TB1> INFO: Expecting 41600 events.
[13:45:47.308] <TB1> INFO: 41600 events read in total (3400ms).
[13:45:47.309] <TB1> INFO: Test took 4269ms.
[13:45:47.972] <TB1> INFO: PixTestGainPedestal::measure() done
[13:46:23.743] <TB1> INFO: PixTestGainPedestal::fit() done
[13:46:23.743] <TB1> INFO: non-linearity mean: 0.964 0.941 0.979 0.893 0.956 0.910 0.932 0.928 0.959 0.928 0.959 0.936 0.926 0.920 0.953 0.938
[13:46:23.743] <TB1> INFO: non-linearity RMS: 0.028 0.064 0.005 0.123 0.052 0.103 0.177 0.102 0.034 0.125 0.029 0.068 0.132 0.112 0.022 0.083
[13:46:23.743] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[13:46:23.765] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[13:46:23.787] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[13:46:23.805] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[13:46:23.825] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[13:46:23.843] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[13:46:23.862] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[13:46:23.876] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[13:46:23.897] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[13:46:23.918] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[13:46:23.941] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[13:46:23.957] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[13:46:23.972] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[13:46:23.986] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[13:46:23.000] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[13:46:24.014] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[13:46:24.033] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 162 seconds
[13:46:24.033] <TB1> INFO: Decoding statistics:
[13:46:24.033] <TB1> INFO: General information:
[13:46:24.033] <TB1> INFO: 16bit words read: 3302662
[13:46:24.033] <TB1> INFO: valid events total: 332800
[13:46:24.033] <TB1> INFO: empty events: 107
[13:46:24.033] <TB1> INFO: valid events with pixels: 332693
[13:46:24.033] <TB1> INFO: valid pixel hits: 652931
[13:46:24.033] <TB1> INFO: Event errors: 0
[13:46:24.033] <TB1> INFO: start marker: 0
[13:46:24.033] <TB1> INFO: stop marker: 0
[13:46:24.033] <TB1> INFO: overflow: 0
[13:46:24.033] <TB1> INFO: invalid 5bit words: 0
[13:46:24.033] <TB1> INFO: invalid XOR eye diagram: 0
[13:46:24.033] <TB1> INFO: frame (failed synchr.): 0
[13:46:24.033] <TB1> INFO: idle data (no TBM trl): 0
[13:46:24.033] <TB1> INFO: no data (only TBM hdr): 0
[13:46:24.033] <TB1> INFO: TBM errors: 0
[13:46:24.033] <TB1> INFO: flawed TBM headers: 0
[13:46:24.033] <TB1> INFO: flawed TBM trailers: 0
[13:46:24.033] <TB1> INFO: event ID mismatches: 0
[13:46:24.033] <TB1> INFO: ROC errors: 0
[13:46:24.033] <TB1> INFO: missing ROC header(s): 0
[13:46:24.033] <TB1> INFO: misplaced readback start: 0
[13:46:24.033] <TB1> INFO: Pixel decoding errors: 0
[13:46:24.033] <TB1> INFO: pixel data incomplete: 0
[13:46:24.033] <TB1> INFO: pixel address: 0
[13:46:24.033] <TB1> INFO: pulse height fill bit: 0
[13:46:24.033] <TB1> INFO: buffer corruption: 0
[13:46:24.055] <TB1> INFO: Decoding statistics:
[13:46:24.055] <TB1> INFO: General information:
[13:46:24.055] <TB1> INFO: 16bit words read: 3432082
[13:46:24.055] <TB1> INFO: valid events total: 353536
[13:46:24.055] <TB1> INFO: empty events: 18341
[13:46:24.055] <TB1> INFO: valid events with pixels: 335195
[13:46:24.055] <TB1> INFO: valid pixel hits: 655433
[13:46:24.055] <TB1> INFO: Event errors: 0
[13:46:24.055] <TB1> INFO: start marker: 0
[13:46:24.055] <TB1> INFO: stop marker: 0
[13:46:24.055] <TB1> INFO: overflow: 0
[13:46:24.055] <TB1> INFO: invalid 5bit words: 0
[13:46:24.055] <TB1> INFO: invalid XOR eye diagram: 0
[13:46:24.055] <TB1> INFO: frame (failed synchr.): 0
[13:46:24.055] <TB1> INFO: idle data (no TBM trl): 0
[13:46:24.055] <TB1> INFO: no data (only TBM hdr): 0
[13:46:24.055] <TB1> INFO: TBM errors: 0
[13:46:24.055] <TB1> INFO: flawed TBM headers: 0
[13:46:24.055] <TB1> INFO: flawed TBM trailers: 0
[13:46:24.055] <TB1> INFO: event ID mismatches: 0
[13:46:24.055] <TB1> INFO: ROC errors: 0
[13:46:24.055] <TB1> INFO: missing ROC header(s): 0
[13:46:24.055] <TB1> INFO: misplaced readback start: 0
[13:46:24.055] <TB1> INFO: Pixel decoding errors: 0
[13:46:24.055] <TB1> INFO: pixel data incomplete: 0
[13:46:24.055] <TB1> INFO: pixel address: 0
[13:46:24.055] <TB1> INFO: pulse height fill bit: 0
[13:46:24.055] <TB1> INFO: buffer corruption: 0
[13:46:24.055] <TB1> INFO: enter test to run
[13:46:24.055] <TB1> INFO: test: Trim80 no parameter change
[13:46:24.055] <TB1> INFO: running: trim80
[13:46:24.081] <TB1> INFO: ######################################################################
[13:46:24.081] <TB1> INFO: PixTestTrim80::doTest()
[13:46:24.081] <TB1> INFO: ######################################################################
[13:46:24.082] <TB1> INFO: ----------------------------------------------------------------------
[13:46:24.082] <TB1> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[13:46:24.082] <TB1> INFO: ----------------------------------------------------------------------
[13:46:24.146] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:46:24.146] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:46:24.158] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:46:24.158] <TB1> INFO: run 1 of 1
[13:46:24.424] <TB1> INFO: Expecting 5025280 events.
[13:46:51.455] <TB1> INFO: 671616 events read in total (26440ms).
[13:47:18.034] <TB1> INFO: 1340080 events read in total (53019ms).
[13:47:44.689] <TB1> INFO: 2007080 events read in total (79674ms).
[13:48:11.056] <TB1> INFO: 2671992 events read in total (106041ms).
[13:48:37.632] <TB1> INFO: 3335416 events read in total (132617ms).
[13:49:04.242] <TB1> INFO: 3997920 events read in total (159227ms).
[13:49:31.272] <TB1> INFO: 4658856 events read in total (186257ms).
[13:49:46.385] <TB1> INFO: 5025280 events read in total (201370ms).
[13:49:46.445] <TB1> INFO: Test took 202287ms.
[13:50:08.997] <TB1> INFO: ROC 0 VthrComp = 68
[13:50:08.997] <TB1> INFO: ROC 1 VthrComp = 77
[13:50:08.997] <TB1> INFO: ROC 2 VthrComp = 73
[13:50:08.997] <TB1> INFO: ROC 3 VthrComp = 72
[13:50:08.997] <TB1> INFO: ROC 4 VthrComp = 72
[13:50:08.997] <TB1> INFO: ROC 5 VthrComp = 73
[13:50:08.998] <TB1> INFO: ROC 6 VthrComp = 75
[13:50:08.998] <TB1> INFO: ROC 7 VthrComp = 80
[13:50:08.998] <TB1> INFO: ROC 8 VthrComp = 75
[13:50:08.998] <TB1> INFO: ROC 9 VthrComp = 79
[13:50:08.998] <TB1> INFO: ROC 10 VthrComp = 76
[13:50:08.998] <TB1> INFO: ROC 11 VthrComp = 84
[13:50:08.998] <TB1> INFO: ROC 12 VthrComp = 76
[13:50:08.999] <TB1> INFO: ROC 13 VthrComp = 72
[13:50:08.999] <TB1> INFO: ROC 14 VthrComp = 70
[13:50:08.999] <TB1> INFO: ROC 15 VthrComp = 73
[13:50:09.259] <TB1> INFO: Expecting 41600 events.
[13:50:12.691] <TB1> INFO: 41600 events read in total (2840ms).
[13:50:12.691] <TB1> INFO: Test took 3691ms.
[13:50:12.700] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:50:12.700] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:50:12.708] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:50:12.708] <TB1> INFO: run 1 of 1
[13:50:12.986] <TB1> INFO: Expecting 5025280 events.
[13:50:40.482] <TB1> INFO: 683880 events read in total (26904ms).
[13:51:07.178] <TB1> INFO: 1365136 events read in total (53600ms).
[13:51:34.258] <TB1> INFO: 2044552 events read in total (80680ms).
[13:52:01.395] <TB1> INFO: 2721288 events read in total (107817ms).
[13:52:28.269] <TB1> INFO: 3394424 events read in total (134691ms).
[13:52:54.925] <TB1> INFO: 4066568 events read in total (161347ms).
[13:53:21.509] <TB1> INFO: 4737544 events read in total (187931ms).
[13:53:33.220] <TB1> INFO: 5025280 events read in total (199642ms).
[13:53:33.281] <TB1> INFO: Test took 200572ms.
[13:53:56.420] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 106.289 for pixel 0/58 mean/min/max = 90.5617/74.7857/106.338
[13:53:56.420] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 108.139 for pixel 0/63 mean/min/max = 93.1247/78.0776/108.172
[13:53:56.420] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 105.742 for pixel 51/32 mean/min/max = 91.8414/77.9101/105.773
[13:53:56.421] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 106.486 for pixel 0/36 mean/min/max = 92.0725/77.6463/106.499
[13:53:56.421] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 109.789 for pixel 0/74 mean/min/max = 93.5648/77.3317/109.798
[13:53:56.421] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 105.353 for pixel 0/79 mean/min/max = 90.941/76.5151/105.367
[13:53:56.422] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 108.139 for pixel 0/69 mean/min/max = 92.9657/77.6019/108.33
[13:53:56.422] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 108.989 for pixel 0/79 mean/min/max = 92.0143/74.9026/109.126
[13:53:56.422] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 107.812 for pixel 51/71 mean/min/max = 92.6834/77.419/107.948
[13:53:56.423] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 118.789 for pixel 0/71 mean/min/max = 97.1198/75.4259/118.814
[13:53:56.423] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 108.842 for pixel 0/21 mean/min/max = 94.0536/79.2511/108.856
[13:53:56.423] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 110.593 for pixel 25/73 mean/min/max = 92.8977/75.1808/110.615
[13:53:56.424] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 107.089 for pixel 0/8 mean/min/max = 92.7476/78.3382/107.157
[13:53:56.424] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 109.737 for pixel 2/78 mean/min/max = 92.9066/75.9871/109.826
[13:53:56.424] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 104.693 for pixel 0/54 mean/min/max = 89.5274/74.306/104.749
[13:53:56.424] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 104.724 for pixel 15/77 mean/min/max = 90.7055/76.4844/104.927
[13:53:56.425] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:53:56.513] <TB1> INFO: Expecting 411648 events.
[13:54:05.767] <TB1> INFO: 411648 events read in total (8662ms).
[13:54:05.774] <TB1> INFO: Expecting 411648 events.
[13:54:14.858] <TB1> INFO: 411648 events read in total (8681ms).
[13:54:14.868] <TB1> INFO: Expecting 411648 events.
[13:54:23.960] <TB1> INFO: 411648 events read in total (8689ms).
[13:54:23.973] <TB1> INFO: Expecting 411648 events.
[13:54:33.098] <TB1> INFO: 411648 events read in total (8722ms).
[13:54:33.118] <TB1> INFO: Expecting 411648 events.
[13:54:42.231] <TB1> INFO: 411648 events read in total (8711ms).
[13:54:42.248] <TB1> INFO: Expecting 411648 events.
[13:54:51.273] <TB1> INFO: 411648 events read in total (8622ms).
[13:54:51.293] <TB1> INFO: Expecting 411648 events.
[13:55:00.376] <TB1> INFO: 411648 events read in total (8680ms).
[13:55:00.398] <TB1> INFO: Expecting 411648 events.
[13:55:09.466] <TB1> INFO: 411648 events read in total (8665ms).
[13:55:09.491] <TB1> INFO: Expecting 411648 events.
[13:55:18.529] <TB1> INFO: 411648 events read in total (8635ms).
[13:55:18.565] <TB1> INFO: Expecting 411648 events.
[13:55:27.604] <TB1> INFO: 411648 events read in total (8636ms).
[13:55:27.646] <TB1> INFO: Expecting 411648 events.
[13:55:36.667] <TB1> INFO: 411648 events read in total (8618ms).
[13:55:36.712] <TB1> INFO: Expecting 411648 events.
[13:55:45.686] <TB1> INFO: 411648 events read in total (8571ms).
[13:55:45.735] <TB1> INFO: Expecting 411648 events.
[13:55:54.771] <TB1> INFO: 411648 events read in total (8633ms).
[13:55:54.811] <TB1> INFO: Expecting 411648 events.
[13:56:03.855] <TB1> INFO: 411648 events read in total (8641ms).
[13:56:03.911] <TB1> INFO: Expecting 411648 events.
[13:56:12.983] <TB1> INFO: 411648 events read in total (8669ms).
[13:56:13.028] <TB1> INFO: Expecting 411648 events.
[13:56:22.089] <TB1> INFO: 411648 events read in total (8659ms).
[13:56:22.151] <TB1> INFO: Test took 145726ms.
[13:56:23.798] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:56:23.810] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:56:23.810] <TB1> INFO: run 1 of 1
[13:56:24.043] <TB1> INFO: Expecting 5025280 events.
[13:56:51.099] <TB1> INFO: 667880 events read in total (26465ms).
[13:57:17.698] <TB1> INFO: 1333968 events read in total (53064ms).
[13:57:44.409] <TB1> INFO: 1998544 events read in total (79775ms).
[13:58:11.075] <TB1> INFO: 2661352 events read in total (106442ms).
[13:58:37.617] <TB1> INFO: 3320552 events read in total (132983ms).
[13:59:04.253] <TB1> INFO: 3977176 events read in total (159619ms).
[13:59:30.628] <TB1> INFO: 4631456 events read in total (185994ms).
[13:59:46.574] <TB1> INFO: 5025280 events read in total (201940ms).
[13:59:46.623] <TB1> INFO: Test took 202813ms.
[14:00:10.946] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 50.027510 .. 110.075027
[14:00:11.221] <TB1> INFO: Expecting 208000 events.
[14:00:20.693] <TB1> INFO: 208000 events read in total (8881ms).
[14:00:20.694] <TB1> INFO: Test took 9746ms.
[14:00:20.758] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 40 .. 120 (-1/-1) hits flags = 528 (plus default)
[14:00:20.769] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:00:20.769] <TB1> INFO: run 1 of 1
[14:00:21.046] <TB1> INFO: Expecting 2695680 events.
[14:00:48.673] <TB1> INFO: 671760 events read in total (27035ms).
[14:01:15.563] <TB1> INFO: 1341944 events read in total (53925ms).
[14:01:42.117] <TB1> INFO: 2006248 events read in total (80479ms).
[14:02:09.504] <TB1> INFO: 2668712 events read in total (107866ms).
[14:02:11.023] <TB1> INFO: 2695680 events read in total (109385ms).
[14:02:11.058] <TB1> INFO: Test took 110290ms.
[14:02:29.907] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 62.139418 .. 95.928373
[14:02:30.140] <TB1> INFO: Expecting 208000 events.
[14:02:40.095] <TB1> INFO: 208000 events read in total (9363ms).
[14:02:40.096] <TB1> INFO: Test took 10187ms.
[14:02:40.142] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 52 .. 105 (-1/-1) hits flags = 528 (plus default)
[14:02:40.150] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:02:40.150] <TB1> INFO: run 1 of 1
[14:02:40.429] <TB1> INFO: Expecting 1797120 events.
[14:03:08.099] <TB1> INFO: 677752 events read in total (27079ms).
[14:03:35.614] <TB1> INFO: 1355272 events read in total (54595ms).
[14:03:54.006] <TB1> INFO: 1797120 events read in total (72986ms).
[14:03:54.034] <TB1> INFO: Test took 73884ms.
[14:04:10.999] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 67.138140 .. 90.791992
[14:04:11.233] <TB1> INFO: Expecting 208000 events.
[14:04:20.908] <TB1> INFO: 208000 events read in total (9084ms).
[14:04:20.909] <TB1> INFO: Test took 9909ms.
[14:04:20.955] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 57 .. 100 (-1/-1) hits flags = 528 (plus default)
[14:04:20.963] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:04:20.964] <TB1> INFO: run 1 of 1
[14:04:21.251] <TB1> INFO: Expecting 1464320 events.
[14:04:49.424] <TB1> INFO: 680792 events read in total (27582ms).
[14:05:17.446] <TB1> INFO: 1361160 events read in total (55605ms).
[14:05:22.077] <TB1> INFO: 1464320 events read in total (60235ms).
[14:05:22.099] <TB1> INFO: Test took 61136ms.
[14:05:39.708] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 70.130983 .. 90.698324
[14:05:39.943] <TB1> INFO: Expecting 208000 events.
[14:05:49.914] <TB1> INFO: 208000 events read in total (9379ms).
[14:05:49.915] <TB1> INFO: Test took 10205ms.
[14:05:49.975] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[14:05:49.987] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:05:49.987] <TB1> INFO: run 1 of 1
[14:05:50.265] <TB1> INFO: Expecting 1364480 events.
[14:06:17.985] <TB1> INFO: 670208 events read in total (27129ms).
[14:06:46.229] <TB1> INFO: 1339920 events read in total (55373ms).
[14:06:47.636] <TB1> INFO: 1364480 events read in total (56780ms).
[14:06:47.655] <TB1> INFO: Test took 57669ms.
[14:07:03.212] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[14:07:03.212] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[14:07:03.222] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:07:03.222] <TB1> INFO: run 1 of 1
[14:07:03.469] <TB1> INFO: Expecting 1364480 events.
[14:07:31.718] <TB1> INFO: 668728 events read in total (27658ms).
[14:07:59.689] <TB1> INFO: 1337144 events read in total (55629ms).
[14:08:01.231] <TB1> INFO: 1364480 events read in total (57171ms).
[14:08:01.253] <TB1> INFO: Test took 58031ms.
[14:08:16.739] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C0.dat
[14:08:16.739] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C1.dat
[14:08:16.740] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C2.dat
[14:08:16.740] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C3.dat
[14:08:16.740] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C4.dat
[14:08:16.740] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C5.dat
[14:08:16.740] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C6.dat
[14:08:16.740] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C7.dat
[14:08:16.740] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C8.dat
[14:08:16.740] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C9.dat
[14:08:16.740] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C10.dat
[14:08:16.740] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C11.dat
[14:08:16.740] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C12.dat
[14:08:16.740] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C13.dat
[14:08:16.741] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C14.dat
[14:08:16.741] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C15.dat
[14:08:16.741] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C0.dat
[14:08:16.746] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C1.dat
[14:08:16.752] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C2.dat
[14:08:16.757] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C3.dat
[14:08:16.763] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C4.dat
[14:08:16.769] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C5.dat
[14:08:16.774] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C6.dat
[14:08:16.780] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C7.dat
[14:08:16.785] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C8.dat
[14:08:16.790] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C9.dat
[14:08:16.796] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C10.dat
[14:08:16.801] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C11.dat
[14:08:16.807] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C12.dat
[14:08:16.812] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C13.dat
[14:08:16.818] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C14.dat
[14:08:16.823] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1105_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C15.dat
[14:08:16.829] <TB1> INFO: PixTestTrim80::trimTest() done
[14:08:16.829] <TB1> INFO: vtrim: 94 113 101 102 110 92 105 111 111 132 112 126 107 97 106 95
[14:08:16.829] <TB1> INFO: vthrcomp: 68 77 73 72 72 73 75 80 75 79 76 84 76 72 70 73
[14:08:16.829] <TB1> INFO: vcal mean: 79.98 80.03 79.99 80.02 80.04 80.05 79.99 80.00 80.01 79.98 79.99 80.01 80.02 80.01 80.00 79.98
[14:08:16.829] <TB1> INFO: vcal RMS: 0.72 0.74 0.71 0.68 0.74 0.68 0.73 0.77 0.74 0.84 0.75 0.80 0.74 0.73 0.74 0.73
[14:08:16.829] <TB1> INFO: bits mean: 10.32 9.97 9.95 9.66 9.41 9.45 9.43 9.97 9.89 9.53 9.67 10.47 9.53 9.94 10.86 10.35
[14:08:16.829] <TB1> INFO: bits RMS: 2.32 1.98 2.07 2.20 2.32 2.47 2.28 2.39 2.13 2.41 1.97 2.12 2.16 2.24 2.19 2.10
[14:08:16.835] <TB1> INFO: ----------------------------------------------------------------------
[14:08:16.836] <TB1> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:08:16.836] <TB1> INFO: ----------------------------------------------------------------------
[14:08:16.838] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:08:16.847] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:08:16.847] <TB1> INFO: run 1 of 1
[14:08:17.079] <TB1> INFO: Expecting 4160000 events.
[14:08:49.273] <TB1> INFO: 757105 events read in total (31603ms).
[14:09:20.668] <TB1> INFO: 1509645 events read in total (62998ms).
[14:09:52.183] <TB1> INFO: 2258080 events read in total (94513ms).
[14:10:23.687] <TB1> INFO: 3002435 events read in total (126017ms).
[14:10:55.175] <TB1> INFO: 3743795 events read in total (157505ms).
[14:11:13.097] <TB1> INFO: 4160000 events read in total (175427ms).
[14:11:13.154] <TB1> INFO: Test took 176307ms.
[14:11:41.147] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 248 (-1/-1) hits flags = 528 (plus default)
[14:11:41.157] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:11:41.158] <TB1> INFO: run 1 of 1
[14:11:41.390] <TB1> INFO: Expecting 5179200 events.
[14:12:11.521] <TB1> INFO: 683465 events read in total (29540ms).
[14:12:41.103] <TB1> INFO: 1364705 events read in total (59122ms).
[14:13:10.967] <TB1> INFO: 2044015 events read in total (88986ms).
[14:13:40.614] <TB1> INFO: 2721420 events read in total (118633ms).
[14:14:10.013] <TB1> INFO: 3395835 events read in total (148032ms).
[14:14:39.763] <TB1> INFO: 4069405 events read in total (177782ms).
[14:15:10.720] <TB1> INFO: 4741120 events read in total (208739ms).
[14:15:29.781] <TB1> INFO: 5179200 events read in total (227800ms).
[14:15:29.859] <TB1> INFO: Test took 228701ms.
[14:16:01.305] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[14:16:01.313] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:16:01.313] <TB1> INFO: run 1 of 1
[14:16:01.568] <TB1> INFO: Expecting 4472000 events.
[14:16:32.642] <TB1> INFO: 715930 events read in total (30483ms).
[14:17:03.142] <TB1> INFO: 1428380 events read in total (60983ms).
[14:17:33.503] <TB1> INFO: 2138310 events read in total (91345ms).
[14:18:03.567] <TB1> INFO: 2843600 events read in total (121408ms).
[14:18:34.987] <TB1> INFO: 3547330 events read in total (152828ms).
[14:19:05.260] <TB1> INFO: 4249145 events read in total (183101ms).
[14:19:15.236] <TB1> INFO: 4472000 events read in total (193077ms).
[14:19:15.304] <TB1> INFO: Test took 193991ms.
[14:19:42.355] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 213 (-1/-1) hits flags = 528 (plus default)
[14:19:42.366] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:19:42.366] <TB1> INFO: run 1 of 1
[14:19:42.601] <TB1> INFO: Expecting 4451200 events.
[14:20:13.955] <TB1> INFO: 717265 events read in total (30763ms).
[14:20:44.568] <TB1> INFO: 1431025 events read in total (61376ms).
[14:21:15.018] <TB1> INFO: 2142260 events read in total (91827ms).
[14:21:45.405] <TB1> INFO: 2848615 events read in total (122213ms).
[14:22:16.353] <TB1> INFO: 3553315 events read in total (153161ms).
[14:22:46.881] <TB1> INFO: 4256455 events read in total (183689ms).
[14:22:55.329] <TB1> INFO: 4451200 events read in total (192137ms).
[14:22:55.384] <TB1> INFO: Test took 193018ms.
[14:23:24.617] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 213 (-1/-1) hits flags = 528 (plus default)
[14:23:24.628] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:23:24.628] <TB1> INFO: run 1 of 1
[14:23:24.875] <TB1> INFO: Expecting 4451200 events.
[14:23:56.281] <TB1> INFO: 717585 events read in total (30815ms).
[14:24:27.202] <TB1> INFO: 1431355 events read in total (61736ms).
[14:24:57.722] <TB1> INFO: 2142550 events read in total (92257ms).
[14:25:29.413] <TB1> INFO: 2849090 events read in total (123947ms).
[14:25:58.968] <TB1> INFO: 3553880 events read in total (153502ms).
[14:26:28.378] <TB1> INFO: 4257115 events read in total (182912ms).
[14:26:36.694] <TB1> INFO: 4451200 events read in total (191228ms).
[14:26:36.750] <TB1> INFO: Test took 192121ms.
[14:27:00.915] <TB1> INFO: PixTestTrim80::trimBitTest() done
[14:27:00.916] <TB1> INFO: PixTestTrim80::doTest() done, duration: 2436 seconds
[14:27:01.556] <TB1> INFO: enter test to run
[14:27:01.556] <TB1> INFO: test: exit no parameter change
[14:27:01.655] <TB1> QUIET: Connection to board 153 closed.
[14:27:01.656] <TB1> INFO: pXar: this is the end, my friend