[12:22:42.178] <TB0> INFO: *** Welcome to pxar ***
[12:22:42.178] <TB0> INFO: *** Today: 2016/11/02
[12:22:42.184] <TB0> INFO: *** Version: c8ba-dirty
[12:22:42.184] <TB0> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:22:42.184] <TB0> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:22:42.185] <TB0> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//defaultMaskFile.dat
[12:22:42.185] <TB0> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters_C15.dat
[12:22:42.237] <TB0> INFO: clk: 4
[12:22:42.238] <TB0> INFO: ctr: 4
[12:22:42.238] <TB0> INFO: sda: 19
[12:22:42.238] <TB0> INFO: tin: 9
[12:22:42.238] <TB0> INFO: level: 15
[12:22:42.238] <TB0> INFO: triggerdelay: 0
[12:22:42.238] <TB0> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[12:22:42.238] <TB0> INFO: Log level: INFO
[12:22:42.246] <TB0> INFO: Found DTB DTB_WS6AYH
[12:22:42.254] <TB0> QUIET: Connection to board DTB_WS6AYH opened.
[12:22:42.256] <TB0> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 73
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WS6AYH
MAC address: 40D855118049
Hostname: pixelDTB073
Comment:
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[12:22:42.257] <TB0> INFO: RPC call hashes of host and DTB match: 486171790
[12:22:43.741] <TB0> INFO: DUT info:
[12:22:43.741] <TB0> INFO: The DUT currently contains the following objects:
[12:22:43.741] <TB0> INFO: 4 TBM Cores tbm10c (4 ON)
[12:22:43.741] <TB0> INFO: TBM Core alpha (0): 7 registers set
[12:22:43.741] <TB0> INFO: TBM Core beta (1): 7 registers set
[12:22:43.741] <TB0> INFO: TBM Core alpha (2): 7 registers set
[12:22:43.741] <TB0> INFO: TBM Core beta (3): 7 registers set
[12:22:43.741] <TB0> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[12:22:43.741] <TB0> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:43.741] <TB0> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:22:44.142] <TB0> INFO: enter 'restricted' command line mode
[12:22:44.142] <TB0> INFO: enter test to run
[12:22:44.142] <TB0> INFO: test: pretest no parameter change
[12:22:44.142] <TB0> INFO: running: pretest
[12:22:44.681] <TB0> INFO: ######################################################################
[12:22:44.681] <TB0> INFO: PixTestPretest::doTest()
[12:22:44.681] <TB0> INFO: ######################################################################
[12:22:44.682] <TB0> INFO: ----------------------------------------------------------------------
[12:22:44.682] <TB0> INFO: PixTestPretest::programROC()
[12:22:44.682] <TB0> INFO: ----------------------------------------------------------------------
[12:23:02.696] <TB0> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:23:02.696] <TB0> INFO: IA differences per ROC: 19.3 19.3 20.1 19.3 20.1 19.3 18.5 18.5 21.7 19.3 19.3 21.7 20.1 20.1 19.3 20.1
[12:23:02.729] <TB0> INFO: ----------------------------------------------------------------------
[12:23:02.729] <TB0> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:23:02.729] <TB0> INFO: ----------------------------------------------------------------------
[12:23:07.596] <TB0> INFO: PixTestPretest::setVana() done, Module Ia 385.1 mA = 24.0688 mA/ROC
[12:23:07.596] <TB0> INFO: i(loss) [mA/ROC]: 18.5 18.5 19.3 19.3 19.3 18.5 18.5 19.3 18.5 18.5 18.5 18.5 18.5 18.5 19.3 18.5
[12:23:07.623] <TB0> INFO: ----------------------------------------------------------------------
[12:23:07.623] <TB0> INFO: PixTestPretest::findTiming()
[12:23:07.623] <TB0> INFO: ----------------------------------------------------------------------
[12:23:07.623] <TB0> INFO: PixTestCmd::init()

[12:23:38.990] <TB0> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:23:38.990] <TB0> INFO: (success/tries = 100/100), width = 4
[12:23:40.495] <TB0> INFO: ----------------------------------------------------------------------
[12:23:40.495] <TB0> INFO: PixTestPretest::findWorkingPixel()
[12:23:40.495] <TB0> INFO: ----------------------------------------------------------------------
[12:23:40.587] <TB0> INFO: Expecting 231680 events.
[12:23:50.237] <TB0> INFO: 231680 events read in total (9059ms).
[12:23:50.243] <TB0> INFO: Test took 9745ms.
[12:23:50.489] <TB0> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:23:50.521] <TB0> INFO: ----------------------------------------------------------------------
[12:23:50.521] <TB0> INFO: PixTestPretest::setVthrCompCalDel()
[12:23:50.521] <TB0> INFO: ----------------------------------------------------------------------
[12:23:50.613] <TB0> INFO: Expecting 231680 events.
[12:24:00.331] <TB0> INFO: 231680 events read in total (9127ms).
[12:24:00.339] <TB0> INFO: Test took 9815ms.
[12:24:00.599] <TB0> INFO: PixTestPretest::setVthrCompCalDel() done
[12:24:00.599] <TB0> INFO: CalDel: 91 93 82 80 99 104 88 96 89 93 85 95 91 84 85 82
[12:24:00.599] <TB0> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[12:24:00.602] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C0.dat
[12:24:00.602] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C1.dat
[12:24:00.602] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C2.dat
[12:24:00.602] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C3.dat
[12:24:00.602] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C4.dat
[12:24:00.602] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C5.dat
[12:24:00.602] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C6.dat
[12:24:00.602] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C7.dat
[12:24:00.602] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C8.dat
[12:24:00.603] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C9.dat
[12:24:00.603] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C10.dat
[12:24:00.603] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C11.dat
[12:24:00.603] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C12.dat
[12:24:00.603] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C13.dat
[12:24:00.603] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C14.dat
[12:24:00.603] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:24:00.603] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[12:24:00.603] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[12:24:00.603] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[12:24:00.603] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:24:00.603] <TB0> INFO: PixTestPretest::doTest() done, duration: 76 seconds
[12:24:00.698] <TB0> INFO: enter test to run
[12:24:00.698] <TB0> INFO: test: fulltest no parameter change
[12:24:00.698] <TB0> INFO: running: fulltest
[12:24:00.698] <TB0> INFO: ######################################################################
[12:24:00.698] <TB0> INFO: PixTestFullTest::doTest()
[12:24:00.698] <TB0> INFO: ######################################################################
[12:24:00.700] <TB0> INFO: ######################################################################
[12:24:00.700] <TB0> INFO: PixTestAlive::doTest()
[12:24:00.700] <TB0> INFO: ######################################################################
[12:24:00.701] <TB0> INFO: ----------------------------------------------------------------------
[12:24:00.701] <TB0> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:24:00.701] <TB0> INFO: ----------------------------------------------------------------------
[12:24:00.936] <TB0> INFO: Expecting 41600 events.
[12:24:04.576] <TB0> INFO: 41600 events read in total (3048ms).
[12:24:04.577] <TB0> INFO: Test took 3875ms.
[12:24:04.802] <TB0> INFO: PixTestAlive::aliveTest() done
[12:24:04.802] <TB0> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:24:04.803] <TB0> INFO: ----------------------------------------------------------------------
[12:24:04.803] <TB0> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:24:04.803] <TB0> INFO: ----------------------------------------------------------------------
[12:24:05.036] <TB0> INFO: Expecting 41600 events.
[12:24:08.066] <TB0> INFO: 41600 events read in total (2439ms).
[12:24:08.066] <TB0> INFO: Test took 3262ms.
[12:24:08.067] <TB0> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:24:08.303] <TB0> INFO: PixTestAlive::maskTest() done
[12:24:08.303] <TB0> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:24:08.304] <TB0> INFO: ----------------------------------------------------------------------
[12:24:08.304] <TB0> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:24:08.304] <TB0> INFO: ----------------------------------------------------------------------
[12:24:08.562] <TB0> INFO: Expecting 41600 events.
[12:24:11.980] <TB0> INFO: 41600 events read in total (2826ms).
[12:24:11.980] <TB0> INFO: Test took 3674ms.
[12:24:12.208] <TB0> INFO: PixTestAlive::addressDecodingTest() done
[12:24:12.208] <TB0> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:24:12.208] <TB0> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:24:12.208] <TB0> INFO: Decoding statistics:
[12:24:12.208] <TB0> INFO: General information:
[12:24:12.208] <TB0> INFO: 16bit words read: 0
[12:24:12.208] <TB0> INFO: valid events total: 0
[12:24:12.208] <TB0> INFO: empty events: 0
[12:24:12.208] <TB0> INFO: valid events with pixels: 0
[12:24:12.208] <TB0> INFO: valid pixel hits: 0
[12:24:12.208] <TB0> INFO: Event errors: 0
[12:24:12.208] <TB0> INFO: start marker: 0
[12:24:12.208] <TB0> INFO: stop marker: 0
[12:24:12.208] <TB0> INFO: overflow: 0
[12:24:12.208] <TB0> INFO: invalid 5bit words: 0
[12:24:12.208] <TB0> INFO: invalid XOR eye diagram: 0
[12:24:12.208] <TB0> INFO: frame (failed synchr.): 0
[12:24:12.208] <TB0> INFO: idle data (no TBM trl): 0
[12:24:12.208] <TB0> INFO: no data (only TBM hdr): 0
[12:24:12.208] <TB0> INFO: TBM errors: 0
[12:24:12.208] <TB0> INFO: flawed TBM headers: 0
[12:24:12.208] <TB0> INFO: flawed TBM trailers: 0
[12:24:12.208] <TB0> INFO: event ID mismatches: 0
[12:24:12.208] <TB0> INFO: ROC errors: 0
[12:24:12.208] <TB0> INFO: missing ROC header(s): 0
[12:24:12.208] <TB0> INFO: misplaced readback start: 0
[12:24:12.208] <TB0> INFO: Pixel decoding errors: 0
[12:24:12.208] <TB0> INFO: pixel data incomplete: 0
[12:24:12.208] <TB0> INFO: pixel address: 0
[12:24:12.208] <TB0> INFO: pulse height fill bit: 0
[12:24:12.208] <TB0> INFO: buffer corruption: 0
[12:24:12.215] <TB0> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:24:12.215] <TB0> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[12:24:12.215] <TB0> INFO: ######################################################################
[12:24:12.215] <TB0> INFO: PixTestReadback::doTest()
[12:24:12.215] <TB0> INFO: ######################################################################
[12:24:12.215] <TB0> INFO: ----------------------------------------------------------------------
[12:24:12.215] <TB0> INFO: PixTestReadback::CalibrateVd()
[12:24:12.215] <TB0> INFO: ----------------------------------------------------------------------
[12:24:22.176] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:24:22.177] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:24:22.177] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:24:22.177] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:24:22.177] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:24:22.177] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:24:22.177] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:24:22.177] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:24:22.177] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:24:22.177] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:24:22.177] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:24:22.177] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:24:22.177] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:24:22.178] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:24:22.178] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:24:22.178] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:24:22.206] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:24:22.206] <TB0> INFO: ----------------------------------------------------------------------
[12:24:22.206] <TB0> INFO: PixTestReadback::CalibrateVa()
[12:24:22.206] <TB0> INFO: ----------------------------------------------------------------------
[12:24:32.093] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:24:32.094] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:24:32.094] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:24:32.094] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:24:32.094] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:24:32.094] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:24:32.094] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:24:32.094] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:24:32.094] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:24:32.094] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:24:32.094] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:24:32.094] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:24:32.094] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:24:32.094] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:24:32.094] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:24:32.095] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:24:32.122] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:24:32.122] <TB0> INFO: ----------------------------------------------------------------------
[12:24:32.122] <TB0> INFO: PixTestReadback::readbackVbg()
[12:24:32.122] <TB0> INFO: ----------------------------------------------------------------------
[12:24:39.759] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:24:39.759] <TB0> INFO: ----------------------------------------------------------------------
[12:24:39.759] <TB0> INFO: PixTestReadback::getCalibratedVbg()
[12:24:39.759] <TB0> INFO: ----------------------------------------------------------------------
[12:24:39.760] <TB0> INFO: Vbg will be calibrated using Vd calibration
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 161.9calibrated Vbg = 1.19779 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 160.1calibrated Vbg = 1.19217 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 152.4calibrated Vbg = 1.1853 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 167.5calibrated Vbg = 1.18962 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 154.1calibrated Vbg = 1.19104 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 155.1calibrated Vbg = 1.19699 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 159calibrated Vbg = 1.19531 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 152.9calibrated Vbg = 1.20015 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 145.7calibrated Vbg = 1.18872 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 148.7calibrated Vbg = 1.18728 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 155.5calibrated Vbg = 1.17935 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 161calibrated Vbg = 1.17938 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 154.9calibrated Vbg = 1.19097 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 163.6calibrated Vbg = 1.19092 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 154.2calibrated Vbg = 1.19589 :::*/*/*/*/
[12:24:39.760] <TB0> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 154.3calibrated Vbg = 1.19439 :::*/*/*/*/
[12:24:39.762] <TB0> INFO: ----------------------------------------------------------------------
[12:24:39.762] <TB0> INFO: PixTestReadback::CalibrateIa()
[12:24:39.762] <TB0> INFO: ----------------------------------------------------------------------
[12:27:20.061] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:27:20.061] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:27:20.061] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:27:20.061] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:27:20.061] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:27:20.062] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:27:20.062] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:27:20.062] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:27:20.062] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:27:20.062] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:27:20.062] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:27:20.062] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:27:20.062] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:27:20.062] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:27:20.062] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:27:20.062] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:27:20.091] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:27:20.092] <TB0> INFO: PixTestReadback::doTest() done
[12:27:20.092] <TB0> INFO: Decoding statistics:
[12:27:20.092] <TB0> INFO: General information:
[12:27:20.092] <TB0> INFO: 16bit words read: 1536
[12:27:20.092] <TB0> INFO: valid events total: 256
[12:27:20.092] <TB0> INFO: empty events: 256
[12:27:20.092] <TB0> INFO: valid events with pixels: 0
[12:27:20.092] <TB0> INFO: valid pixel hits: 0
[12:27:20.092] <TB0> INFO: Event errors: 0
[12:27:20.092] <TB0> INFO: start marker: 0
[12:27:20.092] <TB0> INFO: stop marker: 0
[12:27:20.092] <TB0> INFO: overflow: 0
[12:27:20.092] <TB0> INFO: invalid 5bit words: 0
[12:27:20.092] <TB0> INFO: invalid XOR eye diagram: 0
[12:27:20.092] <TB0> INFO: frame (failed synchr.): 0
[12:27:20.092] <TB0> INFO: idle data (no TBM trl): 0
[12:27:20.092] <TB0> INFO: no data (only TBM hdr): 0
[12:27:20.092] <TB0> INFO: TBM errors: 0
[12:27:20.092] <TB0> INFO: flawed TBM headers: 0
[12:27:20.092] <TB0> INFO: flawed TBM trailers: 0
[12:27:20.092] <TB0> INFO: event ID mismatches: 0
[12:27:20.092] <TB0> INFO: ROC errors: 0
[12:27:20.092] <TB0> INFO: missing ROC header(s): 0
[12:27:20.092] <TB0> INFO: misplaced readback start: 0
[12:27:20.092] <TB0> INFO: Pixel decoding errors: 0
[12:27:20.092] <TB0> INFO: pixel data incomplete: 0
[12:27:20.092] <TB0> INFO: pixel address: 0
[12:27:20.092] <TB0> INFO: pulse height fill bit: 0
[12:27:20.092] <TB0> INFO: buffer corruption: 0
[12:27:20.127] <TB0> INFO: ######################################################################
[12:27:20.127] <TB0> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:27:20.127] <TB0> INFO: ######################################################################
[12:27:20.129] <TB0> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:27:20.144] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:27:20.144] <TB0> INFO: run 1 of 1
[12:27:20.419] <TB0> INFO: Expecting 3120000 events.
[12:27:50.903] <TB0> INFO: 679855 events read in total (29892ms).











[12:28:21.064] <TB0> INFO: 1356645 events read in total (60053ms).











[12:28:51.260] <TB0> INFO: 2031670 events read in total (90249ms).











[12:29:21.870] <TB0> INFO: 2705810 events read in total (120859ms).
[12:29:40.617] <TB0> INFO: 3120000 events read in total (139606ms).
[12:29:40.674] <TB0> INFO: Test took 140531ms.
[12:30:06.403] <TB0> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 166 seconds
[12:30:06.403] <TB0> INFO: number of dead bumps (per ROC): 0 0 2 0 0 1 0 0 0 0 0 0 0 0 1 0
[12:30:06.403] <TB0> INFO: separation cut (per ROC): 101 114 105 105 107 118 101 105 102 102 120 108 108 107 109 111
[12:30:06.403] <TB0> INFO: Decoding statistics:
[12:30:06.403] <TB0> INFO: General information:
[12:30:06.403] <TB0> INFO: 16bit words read: 0
[12:30:06.403] <TB0> INFO: valid events total: 0
[12:30:06.403] <TB0> INFO: empty events: 0
[12:30:06.403] <TB0> INFO: valid events with pixels: 0
[12:30:06.404] <TB0> INFO: valid pixel hits: 0
[12:30:06.404] <TB0> INFO: Event errors: 0
[12:30:06.404] <TB0> INFO: start marker: 0
[12:30:06.404] <TB0> INFO: stop marker: 0
[12:30:06.404] <TB0> INFO: overflow: 0
[12:30:06.404] <TB0> INFO: invalid 5bit words: 0
[12:30:06.404] <TB0> INFO: invalid XOR eye diagram: 0
[12:30:06.404] <TB0> INFO: frame (failed synchr.): 0
[12:30:06.404] <TB0> INFO: idle data (no TBM trl): 0
[12:30:06.404] <TB0> INFO: no data (only TBM hdr): 0
[12:30:06.404] <TB0> INFO: TBM errors: 0
[12:30:06.404] <TB0> INFO: flawed TBM headers: 0
[12:30:06.404] <TB0> INFO: flawed TBM trailers: 0
[12:30:06.404] <TB0> INFO: event ID mismatches: 0
[12:30:06.404] <TB0> INFO: ROC errors: 0
[12:30:06.404] <TB0> INFO: missing ROC header(s): 0
[12:30:06.404] <TB0> INFO: misplaced readback start: 0
[12:30:06.404] <TB0> INFO: Pixel decoding errors: 0
[12:30:06.404] <TB0> INFO: pixel data incomplete: 0
[12:30:06.404] <TB0> INFO: pixel address: 0
[12:30:06.404] <TB0> INFO: pulse height fill bit: 0
[12:30:06.404] <TB0> INFO: buffer corruption: 0
[12:30:06.439] <TB0> INFO: ######################################################################
[12:30:06.439] <TB0> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:30:06.439] <TB0> INFO: ######################################################################
[12:30:06.440] <TB0> INFO: ----------------------------------------------------------------------
[12:30:06.440] <TB0> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:30:06.440] <TB0> INFO: ----------------------------------------------------------------------
[12:30:06.440] <TB0> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:30:06.451] <TB0> INFO: dacScan split into 1 runs with ntrig = 50
[12:30:06.451] <TB0> INFO: run 1 of 1
[12:30:06.698] <TB0> INFO: Expecting 36608000 events.
[12:30:31.070] <TB0> INFO: 691450 events read in total (23781ms).
[12:30:53.645] <TB0> INFO: 1365950 events read in total (46356ms).
[12:31:16.297] <TB0> INFO: 2039450 events read in total (69008ms).
[12:31:38.530] <TB0> INFO: 2712000 events read in total (91241ms).
[12:32:01.070] <TB0> INFO: 3386750 events read in total (113781ms).
[12:32:23.407] <TB0> INFO: 4060350 events read in total (136118ms).
[12:32:45.848] <TB0> INFO: 4733850 events read in total (158559ms).
[12:33:08.065] <TB0> INFO: 5409000 events read in total (180776ms).
[12:33:30.471] <TB0> INFO: 6082900 events read in total (203182ms).
[12:33:52.645] <TB0> INFO: 6755950 events read in total (225356ms).
[12:34:15.194] <TB0> INFO: 7429850 events read in total (247905ms).
[12:34:37.759] <TB0> INFO: 8103800 events read in total (270470ms).
[12:35:00.246] <TB0> INFO: 8777250 events read in total (292957ms).
[12:35:22.738] <TB0> INFO: 9447500 events read in total (315449ms).
[12:35:44.845] <TB0> INFO: 10118950 events read in total (337556ms).
[12:36:07.065] <TB0> INFO: 10792350 events read in total (359776ms).
[12:36:29.240] <TB0> INFO: 11464150 events read in total (381951ms).
[12:36:51.402] <TB0> INFO: 12133250 events read in total (404113ms).
[12:37:13.608] <TB0> INFO: 12803000 events read in total (426319ms).
[12:37:35.663] <TB0> INFO: 13471700 events read in total (448374ms).
[12:37:57.890] <TB0> INFO: 14140300 events read in total (470601ms).
[12:38:20.192] <TB0> INFO: 14809850 events read in total (492903ms).
[12:38:42.637] <TB0> INFO: 15480800 events read in total (515348ms).
[12:39:04.984] <TB0> INFO: 16149850 events read in total (537695ms).
[12:39:27.046] <TB0> INFO: 16820450 events read in total (559757ms).
[12:39:49.411] <TB0> INFO: 17489650 events read in total (582122ms).
[12:40:11.681] <TB0> INFO: 18157900 events read in total (604392ms).
[12:40:33.985] <TB0> INFO: 18826550 events read in total (626696ms).
[12:40:56.313] <TB0> INFO: 19495450 events read in total (649024ms).
[12:41:18.502] <TB0> INFO: 20161100 events read in total (671213ms).
[12:41:40.923] <TB0> INFO: 20827150 events read in total (693634ms).
[12:42:03.205] <TB0> INFO: 21493450 events read in total (715916ms).
[12:42:25.382] <TB0> INFO: 22159800 events read in total (738093ms).
[12:42:47.829] <TB0> INFO: 22825650 events read in total (760540ms).
[12:43:10.093] <TB0> INFO: 23492450 events read in total (782804ms).
[12:43:32.460] <TB0> INFO: 24156850 events read in total (805171ms).
[12:43:54.887] <TB0> INFO: 24821550 events read in total (827598ms).
[12:44:17.222] <TB0> INFO: 25485550 events read in total (849933ms).
[12:44:39.464] <TB0> INFO: 26151650 events read in total (872175ms).
[12:45:01.706] <TB0> INFO: 26817600 events read in total (894417ms).
[12:45:24.351] <TB0> INFO: 27481100 events read in total (917062ms).
[12:45:46.771] <TB0> INFO: 28146650 events read in total (939482ms).
[12:46:09.111] <TB0> INFO: 28808900 events read in total (961822ms).
[12:46:31.285] <TB0> INFO: 29473100 events read in total (983996ms).
[12:46:53.616] <TB0> INFO: 30135900 events read in total (1006327ms).
[12:47:15.743] <TB0> INFO: 30798100 events read in total (1028454ms).
[12:47:38.029] <TB0> INFO: 31461600 events read in total (1050740ms).
[12:48:00.144] <TB0> INFO: 32126200 events read in total (1072855ms).
[12:48:22.472] <TB0> INFO: 32789950 events read in total (1095183ms).
[12:48:44.996] <TB0> INFO: 33454400 events read in total (1117707ms).
[12:49:07.164] <TB0> INFO: 34120750 events read in total (1139875ms).
[12:49:29.587] <TB0> INFO: 34785050 events read in total (1162298ms).
[12:49:51.757] <TB0> INFO: 35451450 events read in total (1184468ms).
[12:50:13.876] <TB0> INFO: 36122000 events read in total (1206587ms).
[12:50:29.881] <TB0> INFO: 36608000 events read in total (1222592ms).
[12:50:29.930] <TB0> INFO: Test took 1223479ms.
[12:50:30.303] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:32.150] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:34.076] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:36.009] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:37.928] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:39.903] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:41.868] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:43.883] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:45.710] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:47.671] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:49.587] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:51.387] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:53.378] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:55.307] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:57.296] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:50:59.228] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:51:01.049] <TB0> INFO: PixTestScurves::scurves() done
[12:51:01.050] <TB0> INFO: Vcal mean: 126.13 128.86 126.07 127.74 135.32 134.39 117.42 121.54 113.10 116.12 130.64 126.05 126.48 124.51 124.33 125.69
[12:51:01.050] <TB0> INFO: Vcal RMS: 6.39 5.87 6.09 5.84 6.62 5.87 5.89 6.42 4.59 5.41 6.55 6.56 6.12 5.47 6.21 5.89
[12:51:01.050] <TB0> INFO: PixTestScurves::fullTest() done, duration: 1254 seconds
[12:51:01.050] <TB0> INFO: Decoding statistics:
[12:51:01.050] <TB0> INFO: General information:
[12:51:01.050] <TB0> INFO: 16bit words read: 0
[12:51:01.050] <TB0> INFO: valid events total: 0
[12:51:01.050] <TB0> INFO: empty events: 0
[12:51:01.050] <TB0> INFO: valid events with pixels: 0
[12:51:01.050] <TB0> INFO: valid pixel hits: 0
[12:51:01.050] <TB0> INFO: Event errors: 0
[12:51:01.050] <TB0> INFO: start marker: 0
[12:51:01.050] <TB0> INFO: stop marker: 0
[12:51:01.050] <TB0> INFO: overflow: 0
[12:51:01.050] <TB0> INFO: invalid 5bit words: 0
[12:51:01.050] <TB0> INFO: invalid XOR eye diagram: 0
[12:51:01.050] <TB0> INFO: frame (failed synchr.): 0
[12:51:01.050] <TB0> INFO: idle data (no TBM trl): 0
[12:51:01.050] <TB0> INFO: no data (only TBM hdr): 0
[12:51:01.050] <TB0> INFO: TBM errors: 0
[12:51:01.050] <TB0> INFO: flawed TBM headers: 0
[12:51:01.050] <TB0> INFO: flawed TBM trailers: 0
[12:51:01.050] <TB0> INFO: event ID mismatches: 0
[12:51:01.050] <TB0> INFO: ROC errors: 0
[12:51:01.050] <TB0> INFO: missing ROC header(s): 0
[12:51:01.050] <TB0> INFO: misplaced readback start: 0
[12:51:01.050] <TB0> INFO: Pixel decoding errors: 0
[12:51:01.050] <TB0> INFO: pixel data incomplete: 0
[12:51:01.050] <TB0> INFO: pixel address: 0
[12:51:01.050] <TB0> INFO: pulse height fill bit: 0
[12:51:01.050] <TB0> INFO: buffer corruption: 0
[12:51:01.115] <TB0> INFO: ######################################################################
[12:51:01.115] <TB0> INFO: PixTestTrim::doTest()
[12:51:01.115] <TB0> INFO: ######################################################################
[12:51:01.116] <TB0> INFO: ----------------------------------------------------------------------
[12:51:01.116] <TB0> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:51:01.116] <TB0> INFO: ----------------------------------------------------------------------
[12:51:01.158] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:51:01.158] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:51:01.168] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:51:01.168] <TB0> INFO: run 1 of 1
[12:51:01.407] <TB0> INFO: Expecting 5025280 events.
[12:51:32.648] <TB0> INFO: 829376 events read in total (30649ms).
[12:52:02.367] <TB0> INFO: 1655880 events read in total (60368ms).
[12:52:32.422] <TB0> INFO: 2479952 events read in total (90423ms).
[12:53:02.473] <TB0> INFO: 3302768 events read in total (120474ms).
[12:53:32.413] <TB0> INFO: 4121120 events read in total (150415ms).
[12:54:02.142] <TB0> INFO: 4938408 events read in total (180143ms).
[12:54:05.711] <TB0> INFO: 5025280 events read in total (183712ms).
[12:54:05.747] <TB0> INFO: Test took 184579ms.
[12:54:20.318] <TB0> INFO: ROC 0 VthrComp = 124
[12:54:20.319] <TB0> INFO: ROC 1 VthrComp = 129
[12:54:20.319] <TB0> INFO: ROC 2 VthrComp = 123
[12:54:20.319] <TB0> INFO: ROC 3 VthrComp = 129
[12:54:20.319] <TB0> INFO: ROC 4 VthrComp = 130
[12:54:20.319] <TB0> INFO: ROC 5 VthrComp = 132
[12:54:20.319] <TB0> INFO: ROC 6 VthrComp = 117
[12:54:20.319] <TB0> INFO: ROC 7 VthrComp = 115
[12:54:20.319] <TB0> INFO: ROC 8 VthrComp = 117
[12:54:20.320] <TB0> INFO: ROC 9 VthrComp = 116
[12:54:20.320] <TB0> INFO: ROC 10 VthrComp = 129
[12:54:20.320] <TB0> INFO: ROC 11 VthrComp = 122
[12:54:20.320] <TB0> INFO: ROC 12 VthrComp = 130
[12:54:20.320] <TB0> INFO: ROC 13 VthrComp = 129
[12:54:20.320] <TB0> INFO: ROC 14 VthrComp = 127
[12:54:20.320] <TB0> INFO: ROC 15 VthrComp = 125
[12:54:20.567] <TB0> INFO: Expecting 41600 events.
[12:54:24.178] <TB0> INFO: 41600 events read in total (3019ms).
[12:54:24.178] <TB0> INFO: Test took 3856ms.
[12:54:24.187] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:54:24.187] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:54:24.196] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:54:24.196] <TB0> INFO: run 1 of 1
[12:54:24.474] <TB0> INFO: Expecting 5025280 events.
[12:54:51.105] <TB0> INFO: 590000 events read in total (26040ms).
[12:55:16.511] <TB0> INFO: 1179344 events read in total (51446ms).
[12:55:41.677] <TB0> INFO: 1769208 events read in total (76612ms).
[12:56:06.916] <TB0> INFO: 2357912 events read in total (101851ms).
[12:56:31.000] <TB0> INFO: 2945592 events read in total (126935ms).
[12:56:57.124] <TB0> INFO: 3531472 events read in total (152059ms).
[12:57:22.317] <TB0> INFO: 4116192 events read in total (177252ms).
[12:57:47.629] <TB0> INFO: 4700480 events read in total (202564ms).
[12:58:01.798] <TB0> INFO: 5025280 events read in total (216733ms).
[12:58:01.853] <TB0> INFO: Test took 217657ms.
[12:58:27.983] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 62.6517 for pixel 10/5 mean/min/max = 47.4552/32.2483/62.6621
[12:58:27.984] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 60.2871 for pixel 0/42 mean/min/max = 47.7066/35.025/60.3882
[12:58:27.984] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 64.905 for pixel 0/41 mean/min/max = 49.2057/33.2728/65.1387
[12:58:27.985] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 58.4652 for pixel 3/68 mean/min/max = 45.6576/32.7894/58.5257
[12:58:27.985] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 65.013 for pixel 51/0 mean/min/max = 49.2645/33.4439/65.0852
[12:58:27.985] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 59.8482 for pixel 35/78 mean/min/max = 46.8923/33.8504/59.9342
[12:58:27.986] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 60.8974 for pixel 14/4 mean/min/max = 46.5887/32.0849/61.0925
[12:58:27.986] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 64.7292 for pixel 7/2 mean/min/max = 48.8029/32.1312/65.4746
[12:58:27.986] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 58.1592 for pixel 25/9 mean/min/max = 45.4742/32.7575/58.191
[12:58:27.987] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 58.7153 for pixel 9/32 mean/min/max = 45.9518/32.934/58.9695
[12:58:27.987] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 60.6286 for pixel 8/37 mean/min/max = 46.5646/32.412/60.7173
[12:58:27.987] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 62.6263 for pixel 1/14 mean/min/max = 48.073/33.4975/62.6484
[12:58:27.988] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 57.8055 for pixel 44/79 mean/min/max = 45.5379/33.1631/57.9127
[12:58:27.988] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 57.8124 for pixel 48/13 mean/min/max = 46.0206/34.1874/57.8538
[12:58:27.988] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 58.6249 for pixel 2/41 mean/min/max = 44.9296/31.1162/58.7431
[12:58:27.989] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 61.0866 for pixel 5/0 mean/min/max = 46.4791/31.835/61.1232
[12:58:27.989] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:58:28.078] <TB0> INFO: Expecting 411648 events.
[12:58:37.463] <TB0> INFO: 411648 events read in total (8794ms).
[12:58:37.471] <TB0> INFO: Expecting 411648 events.
[12:58:46.801] <TB0> INFO: 411648 events read in total (8927ms).
[12:58:46.813] <TB0> INFO: Expecting 411648 events.
[12:58:56.179] <TB0> INFO: 411648 events read in total (8963ms).
[12:58:56.195] <TB0> INFO: Expecting 411648 events.
[12:59:05.417] <TB0> INFO: 411648 events read in total (8819ms).
[12:59:05.431] <TB0> INFO: Expecting 411648 events.
[12:59:14.412] <TB0> INFO: 411648 events read in total (8578ms).
[12:59:14.428] <TB0> INFO: Expecting 411648 events.
[12:59:23.446] <TB0> INFO: 411648 events read in total (8615ms).
[12:59:23.470] <TB0> INFO: Expecting 411648 events.
[12:59:32.471] <TB0> INFO: 411648 events read in total (8598ms).
[12:59:32.493] <TB0> INFO: Expecting 411648 events.
[12:59:41.506] <TB0> INFO: 411648 events read in total (8610ms).
[12:59:41.532] <TB0> INFO: Expecting 411648 events.
[12:59:50.538] <TB0> INFO: 411648 events read in total (8603ms).
[12:59:50.565] <TB0> INFO: Expecting 411648 events.
[12:59:59.535] <TB0> INFO: 411648 events read in total (8567ms).
[12:59:59.573] <TB0> INFO: Expecting 411648 events.
[13:00:08.582] <TB0> INFO: 411648 events read in total (8606ms).
[13:00:08.612] <TB0> INFO: Expecting 411648 events.
[13:00:17.603] <TB0> INFO: 411648 events read in total (8588ms).
[13:00:17.639] <TB0> INFO: Expecting 411648 events.
[13:00:26.780] <TB0> INFO: 411648 events read in total (8738ms).
[13:00:26.828] <TB0> INFO: Expecting 411648 events.
[13:00:35.858] <TB0> INFO: 411648 events read in total (8627ms).
[13:00:35.910] <TB0> INFO: Expecting 411648 events.
[13:00:44.903] <TB0> INFO: 411648 events read in total (8590ms).
[13:00:44.946] <TB0> INFO: Expecting 411648 events.
[13:00:53.898] <TB0> INFO: 411648 events read in total (8549ms).
[13:00:53.941] <TB0> INFO: Test took 145952ms.
[13:00:54.563] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:00:54.576] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:00:54.576] <TB0> INFO: run 1 of 1
[13:00:54.848] <TB0> INFO: Expecting 5025280 events.
[13:01:20.667] <TB0> INFO: 589256 events read in total (25228ms).
[13:01:46.274] <TB0> INFO: 1180704 events read in total (50835ms).
[13:02:11.629] <TB0> INFO: 1771088 events read in total (76190ms).
[13:02:37.230] <TB0> INFO: 2360856 events read in total (101791ms).
[13:03:03.018] <TB0> INFO: 2951328 events read in total (127580ms).
[13:03:28.716] <TB0> INFO: 3541536 events read in total (153277ms).
[13:03:54.281] <TB0> INFO: 4130256 events read in total (178842ms).
[13:04:20.017] <TB0> INFO: 4720296 events read in total (204578ms).
[13:04:33.591] <TB0> INFO: 5025280 events read in total (218153ms).
[13:04:33.702] <TB0> INFO: Test took 219127ms.
[13:04:58.473] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 5.799116 .. 147.823211
[13:04:58.706] <TB0> INFO: Expecting 208000 events.
[13:05:08.101] <TB0> INFO: 208000 events read in total (8803ms).
[13:05:08.102] <TB0> INFO: Test took 9628ms.
[13:05:08.156] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 5 .. 157 (-1/-1) hits flags = 528 (plus default)
[13:05:08.168] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:05:08.168] <TB0> INFO: run 1 of 1
[13:05:08.493] <TB0> INFO: Expecting 5091840 events.
[13:05:35.488] <TB0> INFO: 580120 events read in total (26403ms).
[13:06:00.975] <TB0> INFO: 1159856 events read in total (51891ms).
[13:06:26.377] <TB0> INFO: 1739240 events read in total (77292ms).
[13:06:51.513] <TB0> INFO: 2318976 events read in total (102428ms).
[13:07:16.629] <TB0> INFO: 2898288 events read in total (127544ms).
[13:07:42.095] <TB0> INFO: 3476672 events read in total (153010ms).
[13:08:07.462] <TB0> INFO: 4055040 events read in total (178377ms).
[13:08:32.540] <TB0> INFO: 4632608 events read in total (203455ms).
[13:08:52.502] <TB0> INFO: 5091840 events read in total (223417ms).
[13:08:52.601] <TB0> INFO: Test took 224433ms.
[13:09:18.418] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 26.500000 .. 44.492770
[13:09:18.654] <TB0> INFO: Expecting 208000 events.
[13:09:28.189] <TB0> INFO: 208000 events read in total (8943ms).
[13:09:28.190] <TB0> INFO: Test took 9771ms.
[13:09:28.236] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 54 (-1/-1) hits flags = 528 (plus default)
[13:09:28.247] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:09:28.247] <TB0> INFO: run 1 of 1
[13:09:28.525] <TB0> INFO: Expecting 1297920 events.
[13:09:57.216] <TB0> INFO: 672048 events read in total (28100ms).
[13:10:22.612] <TB0> INFO: 1297920 events read in total (53496ms).
[13:10:22.643] <TB0> INFO: Test took 54397ms.
[13:10:35.743] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 27.038281 .. 48.895624
[13:10:35.980] <TB0> INFO: Expecting 208000 events.
[13:10:45.578] <TB0> INFO: 208000 events read in total (9007ms).
[13:10:45.579] <TB0> INFO: Test took 9834ms.
[13:10:45.625] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 58 (-1/-1) hits flags = 528 (plus default)
[13:10:45.634] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:10:45.634] <TB0> INFO: run 1 of 1
[13:10:45.912] <TB0> INFO: Expecting 1397760 events.
[13:11:14.044] <TB0> INFO: 650456 events read in total (27540ms).
[13:11:41.110] <TB0> INFO: 1299576 events read in total (54606ms).
[13:11:45.606] <TB0> INFO: 1397760 events read in total (59102ms).
[13:11:45.645] <TB0> INFO: Test took 60012ms.
[13:11:57.789] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 25.791129 .. 50.831062
[13:11:58.024] <TB0> INFO: Expecting 208000 events.
[13:12:07.737] <TB0> INFO: 208000 events read in total (9121ms).
[13:12:07.737] <TB0> INFO: Test took 9946ms.
[13:12:07.783] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 60 (-1/-1) hits flags = 528 (plus default)
[13:12:07.791] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:12:07.791] <TB0> INFO: run 1 of 1
[13:12:08.069] <TB0> INFO: Expecting 1530880 events.

[13:14:49.795] <TB0> INFO: Expecting 1530880 events.
[13:15:17.554] <TB0> INFO: 649784 events read in total (27167ms).
[13:15:45.116] <TB0> INFO: 1299368 events read in total (54729ms).
[13:15:54.891] <TB0> INFO: 1530880 events read in total (64504ms).
[13:15:54.920] <TB0> INFO: Test took 65395ms.
[13:16:10.258] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[13:16:10.258] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[13:16:10.267] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:16:10.267] <TB0> INFO: run 1 of 1
[13:16:10.498] <TB0> INFO: Expecting 1364480 events.
[13:16:39.113] <TB0> INFO: 668920 events read in total (28023ms).
[13:17:07.145] <TB0> INFO: 1337408 events read in total (56056ms).
[13:17:08.715] <TB0> INFO: 1364480 events read in total (57625ms).
[13:17:08.742] <TB0> INFO: Test took 58475ms.
[13:17:22.026] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C0.dat
[13:17:22.026] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C1.dat
[13:17:22.026] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C2.dat
[13:17:22.026] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C3.dat
[13:17:22.026] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C4.dat
[13:17:22.026] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C5.dat
[13:17:22.026] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C6.dat
[13:17:22.026] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C7.dat
[13:17:22.026] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C8.dat
[13:17:22.027] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C9.dat
[13:17:22.027] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C10.dat
[13:17:22.027] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C11.dat
[13:17:22.027] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C12.dat
[13:17:22.027] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C13.dat
[13:17:22.027] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C14.dat
[13:17:22.027] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C15.dat
[13:17:22.027] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C0.dat
[13:17:22.033] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C1.dat
[13:17:22.038] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C2.dat
[13:17:22.044] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C3.dat
[13:17:22.049] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C4.dat
[13:17:22.054] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C5.dat
[13:17:22.060] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C6.dat
[13:17:22.065] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C7.dat
[13:17:22.071] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C8.dat
[13:17:22.076] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C9.dat
[13:17:22.082] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C10.dat
[13:17:22.087] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C11.dat
[13:17:22.093] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C12.dat
[13:17:22.098] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C13.dat
[13:17:22.104] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C14.dat
[13:17:22.109] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters35_C15.dat
[13:17:22.115] <TB0> INFO: PixTestTrim::trimTest() done
[13:17:22.115] <TB0> INFO: vtrim: 147 133 155 148 138 126 128 144 138 120 136 142 136 149 148 154
[13:17:22.115] <TB0> INFO: vthrcomp: 124 129 123 129 130 132 117 115 117 116 129 122 130 129 127 125
[13:17:22.115] <TB0> INFO: vcal mean: 35.28 35.09 35.27 35.06 35.59 35.45 35.43 35.84 35.00 35.08 35.17 35.48 35.04 35.11 35.21 35.19
[13:17:22.115] <TB0> INFO: vcal RMS: 1.43 1.10 1.48 1.20 1.86 1.58 1.65 2.17 1.13 1.19 1.36 1.66 1.16 1.09 1.38 1.38
[13:17:22.115] <TB0> INFO: bits mean: 9.70 8.81 9.22 10.40 9.02 9.66 9.76 10.08 10.18 10.03 9.68 9.59 9.93 10.15 10.85 10.27
[13:17:22.115] <TB0> INFO: bits RMS: 2.57 2.51 2.53 2.22 2.72 2.49 2.63 2.50 2.35 2.39 2.57 2.47 2.40 2.12 2.24 2.39
[13:17:22.121] <TB0> INFO: ----------------------------------------------------------------------
[13:17:22.121] <TB0> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:17:22.121] <TB0> INFO: ----------------------------------------------------------------------
[13:17:22.124] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:17:22.135] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:17:22.136] <TB0> INFO: run 1 of 1
[13:17:22.411] <TB0> INFO: Expecting 4160000 events.
[13:17:54.554] <TB0> INFO: 761575 events read in total (31552ms).
[13:18:26.315] <TB0> INFO: 1517795 events read in total (63313ms).
[13:18:57.678] <TB0> INFO: 2270555 events read in total (94676ms).
[13:19:29.232] <TB0> INFO: 3018865 events read in total (126230ms).
[13:20:00.707] <TB0> INFO: 3764240 events read in total (157705ms).
[13:20:17.303] <TB0> INFO: 4160000 events read in total (174301ms).
[13:20:17.362] <TB0> INFO: Test took 175226ms.
[13:20:42.916] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[13:20:42.927] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:20:42.927] <TB0> INFO: run 1 of 1
[13:20:43.158] <TB0> INFO: Expecting 4326400 events.
[13:21:14.619] <TB0> INFO: 726000 events read in total (30869ms).
[13:21:45.401] <TB0> INFO: 1448065 events read in total (61651ms).
[13:22:16.476] <TB0> INFO: 2167255 events read in total (92726ms).
[13:22:47.095] <TB0> INFO: 2882855 events read in total (123345ms).
[13:23:17.577] <TB0> INFO: 3596120 events read in total (153827ms).
[13:23:48.009] <TB0> INFO: 4311120 events read in total (184259ms).
[13:23:49.109] <TB0> INFO: 4326400 events read in total (185359ms).
[13:23:49.168] <TB0> INFO: Test took 186241ms.
[13:24:17.121] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 194 (-1/-1) hits flags = 528 (plus default)
[13:24:17.131] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:24:17.131] <TB0> INFO: run 1 of 1
[13:24:17.395] <TB0> INFO: Expecting 4056000 events.
[13:24:49.049] <TB0> INFO: 744240 events read in total (31063ms).
[13:25:20.097] <TB0> INFO: 1483810 events read in total (62111ms).
[13:25:51.893] <TB0> INFO: 2220065 events read in total (93907ms).
[13:26:22.874] <TB0> INFO: 2952095 events read in total (124888ms).
[13:26:53.482] <TB0> INFO: 3681230 events read in total (155496ms).
[13:27:09.347] <TB0> INFO: 4056000 events read in total (171361ms).
[13:27:09.393] <TB0> INFO: Test took 172262ms.
[13:27:35.425] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[13:27:35.436] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:27:35.436] <TB0> INFO: run 1 of 1
[13:27:35.712] <TB0> INFO: Expecting 4097600 events.
[13:28:06.847] <TB0> INFO: 741465 events read in total (30543ms).
[13:28:37.607] <TB0> INFO: 1478305 events read in total (61303ms).
[13:29:09.399] <TB0> INFO: 2212565 events read in total (93095ms).
[13:29:39.930] <TB0> INFO: 2942005 events read in total (123626ms).
[13:30:10.589] <TB0> INFO: 3668900 events read in total (154285ms).
[13:30:28.790] <TB0> INFO: 4097600 events read in total (172486ms).
[13:30:28.849] <TB0> INFO: Test took 173413ms.
[13:30:56.268] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 195 (-1/-1) hits flags = 528 (plus default)
[13:30:56.278] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:30:56.278] <TB0> INFO: run 1 of 1
[13:30:56.512] <TB0> INFO: Expecting 4076800 events.
[13:31:28.064] <TB0> INFO: 742860 events read in total (30960ms).
[13:31:59.116] <TB0> INFO: 1481110 events read in total (62012ms).
[13:32:30.351] <TB0> INFO: 2216500 events read in total (93247ms).
[13:33:01.251] <TB0> INFO: 2947135 events read in total (124147ms).
[13:33:31.839] <TB0> INFO: 3675145 events read in total (154735ms).
[13:33:48.859] <TB0> INFO: 4076800 events read in total (171755ms).
[13:33:48.906] <TB0> INFO: Test took 172628ms.
[13:34:13.794] <TB0> INFO: PixTestTrim::trimBitTest() done
[13:34:13.795] <TB0> INFO: PixTestTrim::doTest() done, duration: 2592 seconds
[13:34:13.795] <TB0> INFO: Decoding statistics:
[13:34:13.795] <TB0> INFO: General information:
[13:34:13.795] <TB0> INFO: 16bit words read: 0
[13:34:13.795] <TB0> INFO: valid events total: 0
[13:34:13.795] <TB0> INFO: empty events: 0
[13:34:13.795] <TB0> INFO: valid events with pixels: 0
[13:34:13.795] <TB0> INFO: valid pixel hits: 0
[13:34:13.796] <TB0> INFO: Event errors: 0
[13:34:13.796] <TB0> INFO: start marker: 0
[13:34:13.796] <TB0> INFO: stop marker: 0
[13:34:13.796] <TB0> INFO: overflow: 0
[13:34:13.796] <TB0> INFO: invalid 5bit words: 0
[13:34:13.796] <TB0> INFO: invalid XOR eye diagram: 0
[13:34:13.796] <TB0> INFO: frame (failed synchr.): 0
[13:34:13.796] <TB0> INFO: idle data (no TBM trl): 0
[13:34:13.796] <TB0> INFO: no data (only TBM hdr): 0
[13:34:13.796] <TB0> INFO: TBM errors: 0
[13:34:13.796] <TB0> INFO: flawed TBM headers: 0
[13:34:13.796] <TB0> INFO: flawed TBM trailers: 0
[13:34:13.796] <TB0> INFO: event ID mismatches: 0
[13:34:13.796] <TB0> INFO: ROC errors: 0
[13:34:13.796] <TB0> INFO: missing ROC header(s): 0
[13:34:13.796] <TB0> INFO: misplaced readback start: 0
[13:34:13.796] <TB0> INFO: Pixel decoding errors: 0
[13:34:13.796] <TB0> INFO: pixel data incomplete: 0
[13:34:13.796] <TB0> INFO: pixel address: 0
[13:34:13.796] <TB0> INFO: pulse height fill bit: 0
[13:34:13.796] <TB0> INFO: buffer corruption: 0
[13:34:14.549] <TB0> INFO: ######################################################################
[13:34:14.549] <TB0> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:34:14.549] <TB0> INFO: ######################################################################
[13:34:14.783] <TB0> INFO: Expecting 41600 events.
[13:34:18.270] <TB0> INFO: 41600 events read in total (2896ms).
[13:34:18.271] <TB0> INFO: Test took 3720ms.
[13:34:18.724] <TB0> INFO: Expecting 41600 events.
[13:34:22.227] <TB0> INFO: 41600 events read in total (2911ms).
[13:34:22.227] <TB0> INFO: Test took 3754ms.
[13:34:22.516] <TB0> INFO: Expecting 41600 events.
[13:34:26.127] <TB0> INFO: 41600 events read in total (3020ms).
[13:34:26.128] <TB0> INFO: Test took 3877ms.
[13:34:26.415] <TB0> INFO: Expecting 41600 events.
[13:34:29.900] <TB0> INFO: 41600 events read in total (2893ms).
[13:34:29.901] <TB0> INFO: Test took 3750ms.
[13:34:30.196] <TB0> INFO: Expecting 41600 events.
[13:34:33.739] <TB0> INFO: 41600 events read in total (2951ms).
[13:34:33.740] <TB0> INFO: Test took 3816ms.
[13:34:34.028] <TB0> INFO: Expecting 41600 events.
[13:34:37.661] <TB0> INFO: 41600 events read in total (3041ms).
[13:34:37.662] <TB0> INFO: Test took 3899ms.
[13:34:37.960] <TB0> INFO: Expecting 41600 events.
[13:34:41.522] <TB0> INFO: 41600 events read in total (2970ms).
[13:34:41.523] <TB0> INFO: Test took 3835ms.
[13:34:41.812] <TB0> INFO: Expecting 41600 events.
[13:34:45.363] <TB0> INFO: 41600 events read in total (2960ms).
[13:34:45.364] <TB0> INFO: Test took 3817ms.
[13:34:45.661] <TB0> INFO: Expecting 41600 events.
[13:34:49.275] <TB0> INFO: 41600 events read in total (3023ms).
[13:34:49.275] <TB0> INFO: Test took 3888ms.
[13:34:49.563] <TB0> INFO: Expecting 41600 events.
[13:34:53.050] <TB0> INFO: 41600 events read in total (2895ms).
[13:34:53.051] <TB0> INFO: Test took 3752ms.
[13:34:53.339] <TB0> INFO: Expecting 41600 events.
[13:34:56.822] <TB0> INFO: 41600 events read in total (2891ms).
[13:34:56.823] <TB0> INFO: Test took 3748ms.
[13:34:57.111] <TB0> INFO: Expecting 41600 events.
[13:35:00.619] <TB0> INFO: 41600 events read in total (2916ms).
[13:35:00.620] <TB0> INFO: Test took 3774ms.
[13:35:00.912] <TB0> INFO: Expecting 41600 events.
[13:35:04.482] <TB0> INFO: 41600 events read in total (2978ms).
[13:35:04.483] <TB0> INFO: Test took 3835ms.
[13:35:04.774] <TB0> INFO: Expecting 41600 events.
[13:35:08.273] <TB0> INFO: 41600 events read in total (2908ms).
[13:35:08.273] <TB0> INFO: Test took 3764ms.
[13:35:08.562] <TB0> INFO: Expecting 41600 events.
[13:35:12.038] <TB0> INFO: 41600 events read in total (2885ms).
[13:35:12.039] <TB0> INFO: Test took 3742ms.
[13:35:12.327] <TB0> INFO: Expecting 41600 events.
[13:35:15.788] <TB0> INFO: 41600 events read in total (2869ms).
[13:35:15.789] <TB0> INFO: Test took 3726ms.
[13:35:16.088] <TB0> INFO: Expecting 41600 events.
[13:35:19.662] <TB0> INFO: 41600 events read in total (2983ms).
[13:35:19.663] <TB0> INFO: Test took 3850ms.
[13:35:19.951] <TB0> INFO: Expecting 41600 events.
[13:35:23.436] <TB0> INFO: 41600 events read in total (2893ms).
[13:35:23.437] <TB0> INFO: Test took 3750ms.
[13:35:23.725] <TB0> INFO: Expecting 41600 events.
[13:35:27.265] <TB0> INFO: 41600 events read in total (2948ms).
[13:35:27.266] <TB0> INFO: Test took 3806ms.
[13:35:27.561] <TB0> INFO: Expecting 41600 events.
[13:35:31.028] <TB0> INFO: 41600 events read in total (2875ms).
[13:35:31.028] <TB0> INFO: Test took 3739ms.
[13:35:31.316] <TB0> INFO: Expecting 41600 events.
[13:35:34.795] <TB0> INFO: 41600 events read in total (2887ms).
[13:35:34.796] <TB0> INFO: Test took 3744ms.
[13:35:35.084] <TB0> INFO: Expecting 41600 events.
[13:35:38.667] <TB0> INFO: 41600 events read in total (2991ms).
[13:35:38.668] <TB0> INFO: Test took 3848ms.
[13:35:38.956] <TB0> INFO: Expecting 41600 events.
[13:35:42.508] <TB0> INFO: 41600 events read in total (2960ms).
[13:35:42.508] <TB0> INFO: Test took 3817ms.
[13:35:42.797] <TB0> INFO: Expecting 41600 events.
[13:35:46.258] <TB0> INFO: 41600 events read in total (2870ms).
[13:35:46.259] <TB0> INFO: Test took 3727ms.
[13:35:46.547] <TB0> INFO: Expecting 41600 events.
[13:35:50.114] <TB0> INFO: 41600 events read in total (2975ms).
[13:35:50.115] <TB0> INFO: Test took 3832ms.
[13:35:50.406] <TB0> INFO: Expecting 41600 events.
[13:35:53.949] <TB0> INFO: 41600 events read in total (2951ms).
[13:35:53.950] <TB0> INFO: Test took 3809ms.
[13:35:54.239] <TB0> INFO: Expecting 41600 events.
[13:35:57.789] <TB0> INFO: 41600 events read in total (2959ms).
[13:35:57.790] <TB0> INFO: Test took 3816ms.
[13:35:58.078] <TB0> INFO: Expecting 41600 events.
[13:36:01.531] <TB0> INFO: 41600 events read in total (2861ms).
[13:36:01.532] <TB0> INFO: Test took 3718ms.
[13:36:01.822] <TB0> INFO: Expecting 41600 events.
[13:36:05.288] <TB0> INFO: 41600 events read in total (2874ms).
[13:36:05.289] <TB0> INFO: Test took 3731ms.
[13:36:05.578] <TB0> INFO: Expecting 2560 events.
[13:36:06.460] <TB0> INFO: 2560 events read in total (290ms).
[13:36:06.461] <TB0> INFO: Test took 1159ms.
[13:36:06.768] <TB0> INFO: Expecting 2560 events.
[13:36:07.651] <TB0> INFO: 2560 events read in total (291ms).
[13:36:07.651] <TB0> INFO: Test took 1190ms.
[13:36:07.958] <TB0> INFO: Expecting 2560 events.
[13:36:08.841] <TB0> INFO: 2560 events read in total (291ms).
[13:36:08.841] <TB0> INFO: Test took 1190ms.
[13:36:09.150] <TB0> INFO: Expecting 2560 events.
[13:36:10.036] <TB0> INFO: 2560 events read in total (294ms).
[13:36:10.036] <TB0> INFO: Test took 1194ms.
[13:36:10.344] <TB0> INFO: Expecting 2560 events.
[13:36:11.222] <TB0> INFO: 2560 events read in total (287ms).
[13:36:11.222] <TB0> INFO: Test took 1185ms.
[13:36:11.530] <TB0> INFO: Expecting 2560 events.
[13:36:12.408] <TB0> INFO: 2560 events read in total (286ms).
[13:36:12.408] <TB0> INFO: Test took 1185ms.
[13:36:12.717] <TB0> INFO: Expecting 2560 events.
[13:36:13.595] <TB0> INFO: 2560 events read in total (287ms).
[13:36:13.596] <TB0> INFO: Test took 1187ms.
[13:36:13.903] <TB0> INFO: Expecting 2560 events.
[13:36:14.781] <TB0> INFO: 2560 events read in total (286ms).
[13:36:14.781] <TB0> INFO: Test took 1185ms.
[13:36:15.089] <TB0> INFO: Expecting 2560 events.
[13:36:15.969] <TB0> INFO: 2560 events read in total (288ms).
[13:36:15.970] <TB0> INFO: Test took 1188ms.
[13:36:16.278] <TB0> INFO: Expecting 2560 events.
[13:36:17.158] <TB0> INFO: 2560 events read in total (289ms).
[13:36:17.158] <TB0> INFO: Test took 1188ms.
[13:36:17.466] <TB0> INFO: Expecting 2560 events.
[13:36:18.345] <TB0> INFO: 2560 events read in total (287ms).
[13:36:18.345] <TB0> INFO: Test took 1186ms.
[13:36:18.653] <TB0> INFO: Expecting 2560 events.
[13:36:19.531] <TB0> INFO: 2560 events read in total (287ms).
[13:36:19.531] <TB0> INFO: Test took 1186ms.
[13:36:19.839] <TB0> INFO: Expecting 2560 events.
[13:36:20.721] <TB0> INFO: 2560 events read in total (291ms).
[13:36:20.721] <TB0> INFO: Test took 1190ms.
[13:36:21.029] <TB0> INFO: Expecting 2560 events.
[13:36:21.915] <TB0> INFO: 2560 events read in total (294ms).
[13:36:21.915] <TB0> INFO: Test took 1193ms.
[13:36:22.223] <TB0> INFO: Expecting 2560 events.
[13:36:23.105] <TB0> INFO: 2560 events read in total (290ms).
[13:36:23.105] <TB0> INFO: Test took 1189ms.
[13:36:23.413] <TB0> INFO: Expecting 2560 events.
[13:36:24.295] <TB0> INFO: 2560 events read in total (290ms).
[13:36:24.295] <TB0> INFO: Test took 1189ms.
[13:36:24.298] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:36:24.604] <TB0> INFO: Expecting 655360 events.
[13:36:38.856] <TB0> INFO: 655360 events read in total (13660ms).
[13:36:38.866] <TB0> INFO: Expecting 655360 events.
[13:36:52.825] <TB0> INFO: 655360 events read in total (13556ms).
[13:36:52.839] <TB0> INFO: Expecting 655360 events.
[13:37:06.780] <TB0> INFO: 655360 events read in total (13538ms).
[13:37:06.798] <TB0> INFO: Expecting 655360 events.
[13:37:20.778] <TB0> INFO: 655360 events read in total (13577ms).
[13:37:20.801] <TB0> INFO: Expecting 655360 events.
[13:37:34.855] <TB0> INFO: 655360 events read in total (13652ms).
[13:37:34.882] <TB0> INFO: Expecting 655360 events.
[13:37:48.817] <TB0> INFO: 655360 events read in total (13532ms).
[13:37:48.847] <TB0> INFO: Expecting 655360 events.
[13:38:02.792] <TB0> INFO: 655360 events read in total (13542ms).
[13:38:02.838] <TB0> INFO: Expecting 655360 events.
[13:38:16.805] <TB0> INFO: 655360 events read in total (13565ms).
[13:38:16.846] <TB0> INFO: Expecting 655360 events.
[13:38:30.798] <TB0> INFO: 655360 events read in total (13549ms).
[13:38:30.859] <TB0> INFO: Expecting 655360 events.
[13:38:44.923] <TB0> INFO: 655360 events read in total (13661ms).
[13:38:44.970] <TB0> INFO: Expecting 655360 events.
[13:38:59.098] <TB0> INFO: 655360 events read in total (13726ms).
[13:38:59.154] <TB0> INFO: Expecting 655360 events.
[13:39:13.218] <TB0> INFO: 655360 events read in total (13661ms).
[13:39:13.292] <TB0> INFO: Expecting 655360 events.
[13:39:27.368] <TB0> INFO: 655360 events read in total (13673ms).
[13:39:27.451] <TB0> INFO: Expecting 655360 events.
[13:39:41.395] <TB0> INFO: 655360 events read in total (13541ms).
[13:39:41.465] <TB0> INFO: Expecting 655360 events.
[13:39:55.472] <TB0> INFO: 655360 events read in total (13604ms).
[13:39:55.568] <TB0> INFO: Expecting 655360 events.
[13:40:09.575] <TB0> INFO: 655360 events read in total (13604ms).
[13:40:09.667] <TB0> INFO: Test took 225369ms.
[13:40:09.746] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:40:10.011] <TB0> INFO: Expecting 655360 events.
[13:40:23.868] <TB0> INFO: 655360 events read in total (13265ms).
[13:40:23.878] <TB0> INFO: Expecting 655360 events.
[13:40:37.797] <TB0> INFO: 655360 events read in total (13516ms).
[13:40:37.815] <TB0> INFO: Expecting 655360 events.
[13:40:51.754] <TB0> INFO: 655360 events read in total (13536ms).
[13:40:51.773] <TB0> INFO: Expecting 655360 events.
[13:41:05.575] <TB0> INFO: 655360 events read in total (13400ms).
[13:41:05.597] <TB0> INFO: Expecting 655360 events.
[13:41:19.325] <TB0> INFO: 655360 events read in total (13325ms).
[13:41:19.360] <TB0> INFO: Expecting 655360 events.
[13:41:33.324] <TB0> INFO: 655360 events read in total (13561ms).
[13:41:33.353] <TB0> INFO: Expecting 655360 events.
[13:41:47.268] <TB0> INFO: 655360 events read in total (13512ms).
[13:41:47.303] <TB0> INFO: Expecting 655360 events.
[13:42:01.094] <TB0> INFO: 655360 events read in total (13388ms).
[13:42:01.135] <TB0> INFO: Expecting 655360 events.
[13:42:15.128] <TB0> INFO: 655360 events read in total (13590ms).
[13:42:15.173] <TB0> INFO: Expecting 655360 events.
[13:42:29.063] <TB0> INFO: 655360 events read in total (13487ms).
[13:42:29.109] <TB0> INFO: Expecting 655360 events.
[13:42:43.089] <TB0> INFO: 655360 events read in total (13577ms).
[13:42:43.141] <TB0> INFO: Expecting 655360 events.
[13:42:56.961] <TB0> INFO: 655360 events read in total (13416ms).
[13:42:57.017] <TB0> INFO: Expecting 655360 events.
[13:43:11.129] <TB0> INFO: 655360 events read in total (13709ms).
[13:43:11.191] <TB0> INFO: Expecting 655360 events.
[13:43:25.385] <TB0> INFO: 655360 events read in total (13791ms).
[13:43:25.446] <TB0> INFO: Expecting 655360 events.
[13:43:39.613] <TB0> INFO: 655360 events read in total (13764ms).
[13:43:39.684] <TB0> INFO: Expecting 655360 events.
[13:43:53.542] <TB0> INFO: 655360 events read in total (13455ms).
[13:43:53.614] <TB0> INFO: Test took 223868ms.
[13:43:53.773] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.778] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[13:43:53.782] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[13:43:53.787] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[13:43:53.791] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[13:43:53.796] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[13:43:53.800] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.805] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[13:43:53.810] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.814] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.818] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.823] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.827] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[13:43:53.832] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[13:43:53.836] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[13:43:53.841] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[13:43:53.846] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[13:43:53.850] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[13:43:53.855] <TB0> INFO: safety margin for low PH: adding 7, margin is now 27
[13:43:53.859] <TB0> INFO: safety margin for low PH: adding 8, margin is now 28
[13:43:53.864] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.868] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.873] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[13:43:53.878] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[13:43:53.883] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[13:43:53.888] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[13:43:53.893] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[13:43:53.897] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[13:43:53.902] <TB0> INFO: safety margin for low PH: adding 7, margin is now 27
[13:43:53.906] <TB0> INFO: safety margin for low PH: adding 8, margin is now 28
[13:43:53.911] <TB0> INFO: safety margin for low PH: adding 9, margin is now 29
[13:43:53.916] <TB0> INFO: safety margin for low PH: adding 10, margin is now 30
[13:43:53.921] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.925] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.930] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.936] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.942] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.949] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.955] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.962] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:43:53.997] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C0.dat
[13:43:53.997] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C1.dat
[13:43:53.997] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C2.dat
[13:43:53.997] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C3.dat
[13:43:53.997] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C4.dat
[13:43:53.997] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C5.dat
[13:43:53.997] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C6.dat
[13:43:53.997] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C7.dat
[13:43:53.997] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C8.dat
[13:43:53.998] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C9.dat
[13:43:53.998] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C10.dat
[13:43:53.998] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C11.dat
[13:43:53.998] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C12.dat
[13:43:53.998] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C13.dat
[13:43:53.998] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C14.dat
[13:43:53.998] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters35_C15.dat
[13:43:54.233] <TB0> INFO: Expecting 41600 events.
[13:43:57.332] <TB0> INFO: 41600 events read in total (2507ms).
[13:43:57.333] <TB0> INFO: Test took 3332ms.
[13:43:57.776] <TB0> INFO: Expecting 41600 events.
[13:44:00.724] <TB0> INFO: 41600 events read in total (2356ms).
[13:44:00.724] <TB0> INFO: Test took 3180ms.
[13:44:01.170] <TB0> INFO: Expecting 41600 events.
[13:44:04.267] <TB0> INFO: 41600 events read in total (2506ms).
[13:44:04.268] <TB0> INFO: Test took 3332ms.
[13:44:04.481] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:04.570] <TB0> INFO: Expecting 2560 events.
[13:44:05.453] <TB0> INFO: 2560 events read in total (291ms).
[13:44:05.454] <TB0> INFO: Test took 973ms.
[13:44:05.455] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:05.762] <TB0> INFO: Expecting 2560 events.
[13:44:06.644] <TB0> INFO: 2560 events read in total (290ms).
[13:44:06.645] <TB0> INFO: Test took 1190ms.
[13:44:06.647] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:06.953] <TB0> INFO: Expecting 2560 events.
[13:44:07.836] <TB0> INFO: 2560 events read in total (291ms).
[13:44:07.837] <TB0> INFO: Test took 1190ms.
[13:44:07.839] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:08.145] <TB0> INFO: Expecting 2560 events.
[13:44:09.027] <TB0> INFO: 2560 events read in total (290ms).
[13:44:09.027] <TB0> INFO: Test took 1189ms.
[13:44:09.029] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:09.336] <TB0> INFO: Expecting 2560 events.
[13:44:10.220] <TB0> INFO: 2560 events read in total (292ms).
[13:44:10.220] <TB0> INFO: Test took 1191ms.
[13:44:10.222] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:10.528] <TB0> INFO: Expecting 2560 events.
[13:44:11.412] <TB0> INFO: 2560 events read in total (292ms).
[13:44:11.412] <TB0> INFO: Test took 1190ms.
[13:44:11.414] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:11.720] <TB0> INFO: Expecting 2560 events.
[13:44:12.603] <TB0> INFO: 2560 events read in total (292ms).
[13:44:12.603] <TB0> INFO: Test took 1189ms.
[13:44:12.605] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:12.911] <TB0> INFO: Expecting 2560 events.
[13:44:13.795] <TB0> INFO: 2560 events read in total (292ms).
[13:44:13.795] <TB0> INFO: Test took 1190ms.
[13:44:13.797] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:14.104] <TB0> INFO: Expecting 2560 events.
[13:44:14.982] <TB0> INFO: 2560 events read in total (287ms).
[13:44:14.982] <TB0> INFO: Test took 1185ms.
[13:44:14.984] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:15.291] <TB0> INFO: Expecting 2560 events.
[13:44:16.171] <TB0> INFO: 2560 events read in total (289ms).
[13:44:16.171] <TB0> INFO: Test took 1187ms.
[13:44:16.173] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:16.479] <TB0> INFO: Expecting 2560 events.
[13:44:17.360] <TB0> INFO: 2560 events read in total (289ms).
[13:44:17.360] <TB0> INFO: Test took 1187ms.
[13:44:17.362] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:17.668] <TB0> INFO: Expecting 2560 events.
[13:44:18.546] <TB0> INFO: 2560 events read in total (286ms).
[13:44:18.546] <TB0> INFO: Test took 1185ms.
[13:44:18.548] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:18.855] <TB0> INFO: Expecting 2560 events.
[13:44:19.735] <TB0> INFO: 2560 events read in total (288ms).
[13:44:19.736] <TB0> INFO: Test took 1188ms.
[13:44:19.737] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:20.044] <TB0> INFO: Expecting 2560 events.
[13:44:20.925] <TB0> INFO: 2560 events read in total (289ms).
[13:44:20.925] <TB0> INFO: Test took 1188ms.
[13:44:20.927] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:21.234] <TB0> INFO: Expecting 2560 events.
[13:44:22.113] <TB0> INFO: 2560 events read in total (288ms).
[13:44:22.114] <TB0> INFO: Test took 1187ms.
[13:44:22.115] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:22.422] <TB0> INFO: Expecting 2560 events.
[13:44:23.300] <TB0> INFO: 2560 events read in total (287ms).
[13:44:23.301] <TB0> INFO: Test took 1186ms.
[13:44:23.303] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:23.609] <TB0> INFO: Expecting 2560 events.
[13:44:24.491] <TB0> INFO: 2560 events read in total (290ms).
[13:44:24.492] <TB0> INFO: Test took 1189ms.
[13:44:24.493] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:24.800] <TB0> INFO: Expecting 2560 events.
[13:44:25.678] <TB0> INFO: 2560 events read in total (287ms).
[13:44:25.678] <TB0> INFO: Test took 1185ms.
[13:44:25.681] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:25.986] <TB0> INFO: Expecting 2560 events.
[13:44:26.867] <TB0> INFO: 2560 events read in total (289ms).
[13:44:26.868] <TB0> INFO: Test took 1187ms.
[13:44:26.869] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:27.176] <TB0> INFO: Expecting 2560 events.
[13:44:28.055] <TB0> INFO: 2560 events read in total (287ms).
[13:44:28.055] <TB0> INFO: Test took 1186ms.
[13:44:28.057] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:28.364] <TB0> INFO: Expecting 2560 events.
[13:44:29.243] <TB0> INFO: 2560 events read in total (288ms).
[13:44:29.243] <TB0> INFO: Test took 1186ms.
[13:44:29.245] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:29.551] <TB0> INFO: Expecting 2560 events.
[13:44:30.430] <TB0> INFO: 2560 events read in total (287ms).
[13:44:30.431] <TB0> INFO: Test took 1186ms.
[13:44:30.432] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:30.739] <TB0> INFO: Expecting 2560 events.
[13:44:31.617] <TB0> INFO: 2560 events read in total (287ms).
[13:44:31.618] <TB0> INFO: Test took 1186ms.
[13:44:31.619] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:31.926] <TB0> INFO: Expecting 2560 events.
[13:44:32.808] <TB0> INFO: 2560 events read in total (290ms).
[13:44:32.808] <TB0> INFO: Test took 1189ms.
[13:44:32.810] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:33.116] <TB0> INFO: Expecting 2560 events.
[13:44:33.998] <TB0> INFO: 2560 events read in total (290ms).
[13:44:33.999] <TB0> INFO: Test took 1189ms.
[13:44:33.001] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:34.307] <TB0> INFO: Expecting 2560 events.
[13:44:35.193] <TB0> INFO: 2560 events read in total (294ms).
[13:44:35.194] <TB0> INFO: Test took 1193ms.
[13:44:35.196] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:35.502] <TB0> INFO: Expecting 2560 events.
[13:44:36.384] <TB0> INFO: 2560 events read in total (290ms).
[13:44:36.384] <TB0> INFO: Test took 1188ms.
[13:44:36.386] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:36.693] <TB0> INFO: Expecting 2560 events.
[13:44:37.577] <TB0> INFO: 2560 events read in total (293ms).
[13:44:37.577] <TB0> INFO: Test took 1191ms.
[13:44:37.579] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:37.885] <TB0> INFO: Expecting 2560 events.
[13:44:38.768] <TB0> INFO: 2560 events read in total (291ms).
[13:44:38.768] <TB0> INFO: Test took 1189ms.
[13:44:38.770] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:39.076] <TB0> INFO: Expecting 2560 events.
[13:44:39.960] <TB0> INFO: 2560 events read in total (292ms).
[13:44:39.960] <TB0> INFO: Test took 1190ms.
[13:44:39.962] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:40.269] <TB0> INFO: Expecting 2560 events.
[13:44:41.152] <TB0> INFO: 2560 events read in total (292ms).
[13:44:41.152] <TB0> INFO: Test took 1190ms.
[13:44:41.154] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:41.460] <TB0> INFO: Expecting 2560 events.
[13:44:42.343] <TB0> INFO: 2560 events read in total (291ms).
[13:44:42.343] <TB0> INFO: Test took 1189ms.
[13:44:42.811] <TB0> INFO: PixTestPhOptimization::doTest() done, duration: 628 seconds
[13:44:42.812] <TB0> INFO: PH scale (per ROC): 33 45 34 38 42 27 49 41 39 49 52 59 51 37 57 42
[13:44:42.812] <TB0> INFO: PH offset (per ROC): 95 93 100 99 106 107 120 112 106 134 90 104 110 104 128 99
[13:44:42.816] <TB0> INFO: Decoding statistics:
[13:44:42.816] <TB0> INFO: General information:
[13:44:42.816] <TB0> INFO: 16bit words read: 127846
[13:44:42.817] <TB0> INFO: valid events total: 20480
[13:44:42.817] <TB0> INFO: empty events: 17997
[13:44:42.817] <TB0> INFO: valid events with pixels: 2483
[13:44:42.817] <TB0> INFO: valid pixel hits: 2483
[13:44:42.817] <TB0> INFO: Event errors: 0
[13:44:42.817] <TB0> INFO: start marker: 0
[13:44:42.817] <TB0> INFO: stop marker: 0
[13:44:42.817] <TB0> INFO: overflow: 0
[13:44:42.817] <TB0> INFO: invalid 5bit words: 0
[13:44:42.817] <TB0> INFO: invalid XOR eye diagram: 0
[13:44:42.817] <TB0> INFO: frame (failed synchr.): 0
[13:44:42.817] <TB0> INFO: idle data (no TBM trl): 0
[13:44:42.817] <TB0> INFO: no data (only TBM hdr): 0
[13:44:42.817] <TB0> INFO: TBM errors: 0
[13:44:42.817] <TB0> INFO: flawed TBM headers: 0
[13:44:42.817] <TB0> INFO: flawed TBM trailers: 0
[13:44:42.817] <TB0> INFO: event ID mismatches: 0
[13:44:42.817] <TB0> INFO: ROC errors: 0
[13:44:42.817] <TB0> INFO: missing ROC header(s): 0
[13:44:42.817] <TB0> INFO: misplaced readback start: 0
[13:44:42.817] <TB0> INFO: Pixel decoding errors: 0
[13:44:42.817] <TB0> INFO: pixel data incomplete: 0
[13:44:42.817] <TB0> INFO: pixel address: 0
[13:44:42.817] <TB0> INFO: pulse height fill bit: 0
[13:44:42.817] <TB0> INFO: buffer corruption: 0
[13:44:43.089] <TB0> INFO: ######################################################################
[13:44:43.089] <TB0> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:44:43.089] <TB0> INFO: ######################################################################
[13:44:43.101] <TB0> INFO: scanning low vcal = 10
[13:44:43.335] <TB0> INFO: Expecting 41600 events.
[13:44:46.883] <TB0> INFO: 41600 events read in total (2957ms).
[13:44:46.883] <TB0> INFO: Test took 3781ms.
[13:44:46.885] <TB0> INFO: scanning low vcal = 20
[13:44:47.182] <TB0> INFO: Expecting 41600 events.
[13:44:50.748] <TB0> INFO: 41600 events read in total (2975ms).
[13:44:50.748] <TB0> INFO: Test took 3863ms.
[13:44:50.750] <TB0> INFO: scanning low vcal = 30
[13:44:51.049] <TB0> INFO: Expecting 41600 events.
[13:44:54.687] <TB0> INFO: 41600 events read in total (3047ms).
[13:44:54.688] <TB0> INFO: Test took 3938ms.
[13:44:54.690] <TB0> INFO: scanning low vcal = 40
[13:44:54.967] <TB0> INFO: Expecting 41600 events.
[13:44:58.920] <TB0> INFO: 41600 events read in total (3361ms).
[13:44:58.921] <TB0> INFO: Test took 4232ms.
[13:44:58.924] <TB0> INFO: scanning low vcal = 50
[13:44:59.201] <TB0> INFO: Expecting 41600 events.
[13:45:03.161] <TB0> INFO: 41600 events read in total (3368ms).
[13:45:03.162] <TB0> INFO: Test took 4237ms.
[13:45:03.164] <TB0> INFO: scanning low vcal = 60
[13:45:03.441] <TB0> INFO: Expecting 41600 events.
[13:45:07.394] <TB0> INFO: 41600 events read in total (3361ms).
[13:45:07.395] <TB0> INFO: Test took 4231ms.
[13:45:07.397] <TB0> INFO: scanning low vcal = 70
[13:45:07.674] <TB0> INFO: Expecting 41600 events.
[13:45:11.662] <TB0> INFO: 41600 events read in total (3396ms).
[13:45:11.662] <TB0> INFO: Test took 4264ms.
[13:45:11.665] <TB0> INFO: scanning low vcal = 80
[13:45:11.942] <TB0> INFO: Expecting 41600 events.
[13:45:15.946] <TB0> INFO: 41600 events read in total (3412ms).
[13:45:15.947] <TB0> INFO: Test took 4282ms.
[13:45:15.950] <TB0> INFO: scanning low vcal = 90
[13:45:16.226] <TB0> INFO: Expecting 41600 events.
[13:45:20.180] <TB0> INFO: 41600 events read in total (3362ms).
[13:45:20.181] <TB0> INFO: Test took 4231ms.
[13:45:20.184] <TB0> INFO: scanning low vcal = 100
[13:45:20.461] <TB0> INFO: Expecting 41600 events.
[13:45:24.417] <TB0> INFO: 41600 events read in total (3365ms).
[13:45:24.418] <TB0> INFO: Test took 4234ms.
[13:45:24.421] <TB0> INFO: scanning low vcal = 110
[13:45:24.697] <TB0> INFO: Expecting 41600 events.
[13:45:28.688] <TB0> INFO: 41600 events read in total (3399ms).
[13:45:28.689] <TB0> INFO: Test took 4268ms.
[13:45:28.692] <TB0> INFO: scanning low vcal = 120
[13:45:28.969] <TB0> INFO: Expecting 41600 events.
[13:45:32.908] <TB0> INFO: 41600 events read in total (3347ms).
[13:45:32.909] <TB0> INFO: Test took 4216ms.
[13:45:32.912] <TB0> INFO: scanning low vcal = 130
[13:45:33.189] <TB0> INFO: Expecting 41600 events.
[13:45:37.140] <TB0> INFO: 41600 events read in total (3351ms).
[13:45:37.141] <TB0> INFO: Test took 4229ms.
[13:45:37.144] <TB0> INFO: scanning low vcal = 140
[13:45:37.421] <TB0> INFO: Expecting 41600 events.
[13:45:41.413] <TB0> INFO: 41600 events read in total (3401ms).
[13:45:41.414] <TB0> INFO: Test took 4270ms.
[13:45:41.416] <TB0> INFO: scanning low vcal = 150
[13:45:41.693] <TB0> INFO: Expecting 41600 events.
[13:45:45.641] <TB0> INFO: 41600 events read in total (3355ms).
[13:45:45.642] <TB0> INFO: Test took 4226ms.
[13:45:45.644] <TB0> INFO: scanning low vcal = 160
[13:45:45.921] <TB0> INFO: Expecting 41600 events.
[13:45:49.969] <TB0> INFO: 41600 events read in total (3456ms).
[13:45:49.971] <TB0> INFO: Test took 4326ms.
[13:45:49.974] <TB0> INFO: scanning low vcal = 170
[13:45:50.250] <TB0> INFO: Expecting 41600 events.
[13:45:54.266] <TB0> INFO: 41600 events read in total (3423ms).
[13:45:54.269] <TB0> INFO: Test took 4295ms.
[13:45:54.272] <TB0> INFO: scanning low vcal = 180
[13:45:54.548] <TB0> INFO: Expecting 41600 events.
[13:45:58.563] <TB0> INFO: 41600 events read in total (3423ms).
[13:45:58.564] <TB0> INFO: Test took 4292ms.
[13:45:58.567] <TB0> INFO: scanning low vcal = 190
[13:45:58.844] <TB0> INFO: Expecting 41600 events.
[13:46:02.855] <TB0> INFO: 41600 events read in total (3419ms).
[13:46:02.856] <TB0> INFO: Test took 4289ms.
[13:46:02.859] <TB0> INFO: scanning low vcal = 200
[13:46:03.135] <TB0> INFO: Expecting 41600 events.
[13:46:07.097] <TB0> INFO: 41600 events read in total (3370ms).
[13:46:07.098] <TB0> INFO: Test took 4239ms.
[13:46:07.100] <TB0> INFO: scanning low vcal = 210
[13:46:07.377] <TB0> INFO: Expecting 41600 events.
[13:46:11.341] <TB0> INFO: 41600 events read in total (3372ms).
[13:46:11.342] <TB0> INFO: Test took 4241ms.
[13:46:11.345] <TB0> INFO: scanning low vcal = 220
[13:46:11.621] <TB0> INFO: Expecting 41600 events.
[13:46:15.583] <TB0> INFO: 41600 events read in total (3370ms).
[13:46:15.584] <TB0> INFO: Test took 4239ms.
[13:46:15.587] <TB0> INFO: scanning low vcal = 230
[13:46:15.863] <TB0> INFO: Expecting 41600 events.
[13:46:19.863] <TB0> INFO: 41600 events read in total (3408ms).
[13:46:19.863] <TB0> INFO: Test took 4276ms.
[13:46:19.866] <TB0> INFO: scanning low vcal = 240
[13:46:20.143] <TB0> INFO: Expecting 41600 events.
[13:46:24.111] <TB0> INFO: 41600 events read in total (3376ms).
[13:46:24.112] <TB0> INFO: Test took 4245ms.
[13:46:24.115] <TB0> INFO: scanning low vcal = 250
[13:46:24.392] <TB0> INFO: Expecting 41600 events.
[13:46:28.315] <TB0> INFO: 41600 events read in total (3332ms).
[13:46:28.316] <TB0> INFO: Test took 4201ms.
[13:46:28.320] <TB0> INFO: scanning high vcal = 30 (= 210 in low range)
[13:46:28.596] <TB0> INFO: Expecting 41600 events.
[13:46:32.563] <TB0> INFO: 41600 events read in total (3375ms).
[13:46:32.564] <TB0> INFO: Test took 4244ms.
[13:46:32.567] <TB0> INFO: scanning high vcal = 50 (= 350 in low range)
[13:46:32.843] <TB0> INFO: Expecting 41600 events.
[13:46:36.763] <TB0> INFO: 41600 events read in total (3328ms).
[13:46:36.764] <TB0> INFO: Test took 4197ms.
[13:46:36.767] <TB0> INFO: scanning high vcal = 70 (= 490 in low range)
[13:46:37.043] <TB0> INFO: Expecting 41600 events.
[13:46:40.002] <TB0> INFO: 41600 events read in total (3367ms).
[13:46:41.003] <TB0> INFO: Test took 4236ms.
[13:46:41.006] <TB0> INFO: scanning high vcal = 90 (= 630 in low range)
[13:46:41.284] <TB0> INFO: Expecting 41600 events.
[13:46:45.220] <TB0> INFO: 41600 events read in total (3345ms).
[13:46:45.221] <TB0> INFO: Test took 4215ms.
[13:46:45.224] <TB0> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:46:45.501] <TB0> INFO: Expecting 41600 events.
[13:46:49.436] <TB0> INFO: 41600 events read in total (3344ms).
[13:46:49.436] <TB0> INFO: Test took 4213ms.
[13:46:50.012] <TB0> INFO: PixTestGainPedestal::measure() done
[13:47:28.610] <TB0> INFO: PixTestGainPedestal::fit() done
[13:47:28.610] <TB0> INFO: non-linearity mean: 0.912 0.942 0.917 0.930 0.955 0.996 0.981 0.964 0.940 0.979 0.971 0.986 0.969 0.915 0.986 0.964
[13:47:28.610] <TB0> INFO: non-linearity RMS: 0.156 0.059 0.140 0.141 0.045 0.194 0.005 0.036 0.068 0.004 0.016 0.006 0.028 0.136 0.003 0.025
[13:47:28.611] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[13:47:28.630] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[13:47:28.650] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[13:47:28.669] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[13:47:28.688] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[13:47:28.707] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[13:47:28.728] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[13:47:28.746] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[13:47:28.765] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[13:47:28.785] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[13:47:28.804] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[13:47:28.824] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[13:47:28.843] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[13:47:28.862] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[13:47:28.882] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[13:47:28.902] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[13:47:28.918] <TB0> INFO: PixTestGainPedestal::fullTest() done, duration: 165 seconds
[13:47:28.918] <TB0> INFO: Decoding statistics:
[13:47:28.918] <TB0> INFO: General information:
[13:47:28.918] <TB0> INFO: 16bit words read: 3271464
[13:47:28.918] <TB0> INFO: valid events total: 332800
[13:47:28.918] <TB0> INFO: empty events: 2945
[13:47:28.918] <TB0> INFO: valid events with pixels: 329855
[13:47:28.918] <TB0> INFO: valid pixel hits: 637332
[13:47:28.918] <TB0> INFO: Event errors: 0
[13:47:28.918] <TB0> INFO: start marker: 0
[13:47:28.918] <TB0> INFO: stop marker: 0
[13:47:28.918] <TB0> INFO: overflow: 0
[13:47:28.918] <TB0> INFO: invalid 5bit words: 0
[13:47:28.918] <TB0> INFO: invalid XOR eye diagram: 0
[13:47:28.918] <TB0> INFO: frame (failed synchr.): 0
[13:47:28.918] <TB0> INFO: idle data (no TBM trl): 0
[13:47:28.918] <TB0> INFO: no data (only TBM hdr): 0
[13:47:28.918] <TB0> INFO: TBM errors: 0
[13:47:28.918] <TB0> INFO: flawed TBM headers: 0
[13:47:28.918] <TB0> INFO: flawed TBM trailers: 0
[13:47:28.918] <TB0> INFO: event ID mismatches: 0
[13:47:28.918] <TB0> INFO: ROC errors: 0
[13:47:28.918] <TB0> INFO: missing ROC header(s): 0
[13:47:28.918] <TB0> INFO: misplaced readback start: 0
[13:47:28.918] <TB0> INFO: Pixel decoding errors: 0
[13:47:28.918] <TB0> INFO: pixel data incomplete: 0
[13:47:28.918] <TB0> INFO: pixel address: 0
[13:47:28.918] <TB0> INFO: pulse height fill bit: 0
[13:47:28.918] <TB0> INFO: buffer corruption: 0
[13:47:28.933] <TB0> INFO: Decoding statistics:
[13:47:28.933] <TB0> INFO: General information:
[13:47:28.933] <TB0> INFO: 16bit words read: 3400846
[13:47:28.933] <TB0> INFO: valid events total: 353536
[13:47:28.933] <TB0> INFO: empty events: 21198
[13:47:28.933] <TB0> INFO: valid events with pixels: 332338
[13:47:28.933] <TB0> INFO: valid pixel hits: 639815
[13:47:28.933] <TB0> INFO: Event errors: 0
[13:47:28.933] <TB0> INFO: start marker: 0
[13:47:28.933] <TB0> INFO: stop marker: 0
[13:47:28.933] <TB0> INFO: overflow: 0
[13:47:28.933] <TB0> INFO: invalid 5bit words: 0
[13:47:28.933] <TB0> INFO: invalid XOR eye diagram: 0
[13:47:28.933] <TB0> INFO: frame (failed synchr.): 0
[13:47:28.933] <TB0> INFO: idle data (no TBM trl): 0
[13:47:28.933] <TB0> INFO: no data (only TBM hdr): 0
[13:47:28.933] <TB0> INFO: TBM errors: 0
[13:47:28.933] <TB0> INFO: flawed TBM headers: 0
[13:47:28.933] <TB0> INFO: flawed TBM trailers: 0
[13:47:28.933] <TB0> INFO: event ID mismatches: 0
[13:47:28.933] <TB0> INFO: ROC errors: 0
[13:47:28.933] <TB0> INFO: missing ROC header(s): 0
[13:47:28.933] <TB0> INFO: misplaced readback start: 0
[13:47:28.933] <TB0> INFO: Pixel decoding errors: 0
[13:47:28.933] <TB0> INFO: pixel data incomplete: 0
[13:47:28.933] <TB0> INFO: pixel address: 0
[13:47:28.933] <TB0> INFO: pulse height fill bit: 0
[13:47:28.933] <TB0> INFO: buffer corruption: 0
[13:47:28.933] <TB0> INFO: enter test to run
[13:47:28.933] <TB0> INFO: test: Trim80 no parameter change
[13:47:28.933] <TB0> INFO: running: trim80
[13:47:28.948] <TB0> INFO: ######################################################################
[13:47:28.948] <TB0> INFO: PixTestTrim80::doTest()
[13:47:28.948] <TB0> INFO: ######################################################################
[13:47:28.949] <TB0> INFO: ----------------------------------------------------------------------
[13:47:28.949] <TB0> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[13:47:28.949] <TB0> INFO: ----------------------------------------------------------------------
[13:47:29.007] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:47:29.007] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:47:29.019] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:47:29.019] <TB0> INFO: run 1 of 1
[13:47:29.252] <TB0> INFO: Expecting 5025280 events.
[13:47:56.874] <TB0> INFO: 682824 events read in total (27030ms).
[13:48:23.831] <TB0> INFO: 1363480 events read in total (53987ms).
[13:48:50.849] <TB0> INFO: 2042952 events read in total (81005ms).
[13:49:17.995] <TB0> INFO: 2720616 events read in total (108151ms).
[13:49:45.465] <TB0> INFO: 3396264 events read in total (135621ms).
[13:50:11.983] <TB0> INFO: 4070144 events read in total (162139ms).
[13:50:38.638] <TB0> INFO: 4744232 events read in total (188794ms).
[13:50:49.970] <TB0> INFO: 5025280 events read in total (200126ms).
[13:50:50.045] <TB0> INFO: Test took 201026ms.
[13:51:12.517] <TB0> INFO: ROC 0 VthrComp = 76
[13:51:12.517] <TB0> INFO: ROC 1 VthrComp = 80
[13:51:12.517] <TB0> INFO: ROC 2 VthrComp = 76
[13:51:12.518] <TB0> INFO: ROC 3 VthrComp = 79
[13:51:12.518] <TB0> INFO: ROC 4 VthrComp = 83
[13:51:12.518] <TB0> INFO: ROC 5 VthrComp = 83
[13:51:12.518] <TB0> INFO: ROC 6 VthrComp = 72
[13:51:12.518] <TB0> INFO: ROC 7 VthrComp = 72
[13:51:12.518] <TB0> INFO: ROC 8 VthrComp = 71
[13:51:12.518] <TB0> INFO: ROC 9 VthrComp = 71
[13:51:12.518] <TB0> INFO: ROC 10 VthrComp = 80
[13:51:12.518] <TB0> INFO: ROC 11 VthrComp = 76
[13:51:12.518] <TB0> INFO: ROC 12 VthrComp = 78
[13:51:12.519] <TB0> INFO: ROC 13 VthrComp = 77
[13:51:12.519] <TB0> INFO: ROC 14 VthrComp = 76
[13:51:12.519] <TB0> INFO: ROC 15 VthrComp = 76
[13:51:12.752] <TB0> INFO: Expecting 41600 events.
[13:51:16.278] <TB0> INFO: 41600 events read in total (2934ms).
[13:51:16.279] <TB0> INFO: Test took 3759ms.
[13:51:16.288] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:51:16.288] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:51:16.297] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:51:16.297] <TB0> INFO: run 1 of 1
[13:51:16.575] <TB0> INFO: Expecting 5025280 events.
[13:51:44.480] <TB0> INFO: 683632 events read in total (27314ms).
[13:52:11.702] <TB0> INFO: 1363856 events read in total (54536ms).
[13:52:38.633] <TB0> INFO: 2041528 events read in total (81467ms).
[13:53:05.896] <TB0> INFO: 2717976 events read in total (108730ms).
[13:53:32.856] <TB0> INFO: 3390184 events read in total (135690ms).
[13:53:59.392] <TB0> INFO: 4061184 events read in total (162226ms).
[13:54:25.809] <TB0> INFO: 4731168 events read in total (188643ms).
[13:54:37.506] <TB0> INFO: 5025280 events read in total (200340ms).
[13:54:37.550] <TB0> INFO: Test took 201253ms.
[13:54:59.690] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 112.925 for pixel 0/44 mean/min/max = 95.2182/77.4908/112.946
[13:54:59.691] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 106.054 for pixel 0/50 mean/min/max = 91.1292/76.1295/106.129
[13:54:59.691] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 113.057 for pixel 0/79 mean/min/max = 95.9875/78.6828/113.292
[13:54:59.691] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 107.948 for pixel 13/73 mean/min/max = 92.9208/77.8886/107.953
[13:54:59.692] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 110.233 for pixel 0/46 mean/min/max = 92.0558/73.8121/110.299
[13:54:59.692] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 106.241 for pixel 15/76 mean/min/max = 91.0684/75.6807/106.456
[13:54:59.693] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 110.616 for pixel 0/12 mean/min/max = 93.1787/75.6499/110.707
[13:54:59.693] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 112.794 for pixel 0/5 mean/min/max = 94.7115/76.5338/112.889
[13:54:59.693] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 103.729 for pixel 10/79 mean/min/max = 89.0858/74.4324/103.739
[13:54:59.694] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 106.262 for pixel 0/77 mean/min/max = 90.3421/74.4088/106.275
[13:54:59.694] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 109.137 for pixel 0/8 mean/min/max = 92.3702/75.4326/109.308
[13:54:59.694] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 112.638 for pixel 15/73 mean/min/max = 95.0286/77.295/112.762
[13:54:59.695] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 107.502 for pixel 51/8 mean/min/max = 92.6711/77.749/107.593
[13:54:59.695] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 108.164 for pixel 0/7 mean/min/max = 93.296/78.3925/108.2
[13:54:59.695] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 110.884 for pixel 0/75 mean/min/max = 94.2283/77.4562/111
[13:54:59.696] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 109.929 for pixel 0/69 mean/min/max = 94.5028/78.7992/110.206
[13:54:59.696] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:54:59.785] <TB0> INFO: Expecting 411648 events.
[13:55:08.964] <TB0> INFO: 411648 events read in total (8588ms).
[13:55:08.972] <TB0> INFO: Expecting 411648 events.
[13:55:18.099] <TB0> INFO: 411648 events read in total (8724ms).
[13:55:18.111] <TB0> INFO: Expecting 411648 events.
[13:55:27.202] <TB0> INFO: 411648 events read in total (8688ms).
[13:55:27.214] <TB0> INFO: Expecting 411648 events.
[13:55:36.247] <TB0> INFO: 411648 events read in total (8630ms).
[13:55:36.266] <TB0> INFO: Expecting 411648 events.
[13:55:45.307] <TB0> INFO: 411648 events read in total (8638ms).
[13:55:45.324] <TB0> INFO: Expecting 411648 events.
[13:55:54.391] <TB0> INFO: 411648 events read in total (8664ms).
[13:55:54.409] <TB0> INFO: Expecting 411648 events.
[13:56:03.474] <TB0> INFO: 411648 events read in total (8662ms).
[13:56:03.507] <TB0> INFO: Expecting 411648 events.
[13:56:12.503] <TB0> INFO: 411648 events read in total (8593ms).
[13:56:12.528] <TB0> INFO: Expecting 411648 events.
[13:56:21.618] <TB0> INFO: 411648 events read in total (8687ms).
[13:56:21.646] <TB0> INFO: Expecting 411648 events.
[13:56:30.726] <TB0> INFO: 411648 events read in total (8677ms).
[13:56:30.766] <TB0> INFO: Expecting 411648 events.
[13:56:39.822] <TB0> INFO: 411648 events read in total (8653ms).
[13:56:39.867] <TB0> INFO: Expecting 411648 events.
[13:56:48.990] <TB0> INFO: 411648 events read in total (8720ms).
[13:56:49.030] <TB0> INFO: Expecting 411648 events.
[13:56:58.189] <TB0> INFO: 411648 events read in total (8756ms).
[13:56:58.240] <TB0> INFO: Expecting 411648 events.
[13:57:07.327] <TB0> INFO: 411648 events read in total (8684ms).
[13:57:07.370] <TB0> INFO: Expecting 411648 events.
[13:57:16.632] <TB0> INFO: 411648 events read in total (8859ms).
[13:57:16.689] <TB0> INFO: Expecting 411648 events.
[13:57:25.708] <TB0> INFO: 411648 events read in total (8616ms).
[13:57:25.773] <TB0> INFO: Test took 146077ms.
[13:57:27.439] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:57:27.450] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:57:27.450] <TB0> INFO: run 1 of 1
[13:57:27.687] <TB0> INFO: Expecting 5025280 events.
[13:57:55.242] <TB0> INFO: 667032 events read in total (26964ms).
[13:58:21.971] <TB0> INFO: 1331568 events read in total (53693ms).
[13:58:48.961] <TB0> INFO: 1995288 events read in total (80683ms).
[13:59:15.454] <TB0> INFO: 2656848 events read in total (107176ms).
[13:59:42.481] <TB0> INFO: 3314048 events read in total (134203ms).
[14:00:09.207] <TB0> INFO: 3969288 events read in total (160929ms).
[14:00:35.692] <TB0> INFO: 4622344 events read in total (187414ms).
[14:00:51.951] <TB0> INFO: 5025280 events read in total (203673ms).
[14:00:51.003] <TB0> INFO: Test took 204552ms.
[14:01:13.881] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 49.613040 .. 97.055737
[14:01:14.142] <TB0> INFO: Expecting 208000 events.
[14:01:23.830] <TB0> INFO: 208000 events read in total (9096ms).
[14:01:23.830] <TB0> INFO: Test took 9948ms.
[14:01:23.896] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 39 .. 107 (-1/-1) hits flags = 528 (plus default)
[14:01:23.907] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:01:23.907] <TB0> INFO: run 1 of 1
[14:01:24.185] <TB0> INFO: Expecting 2296320 events.
[14:01:52.881] <TB0> INFO: 708560 events read in total (28104ms).
[14:02:21.119] <TB0> INFO: 1412280 events read in total (56342ms).
[14:02:48.932] <TB0> INFO: 2108352 events read in total (84155ms).
[14:02:56.494] <TB0> INFO: 2296320 events read in total (91717ms).
[14:02:56.522] <TB0> INFO: Test took 92614ms.
[14:03:15.781] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 60.891978 .. 87.178410
[14:03:16.031] <TB0> INFO: Expecting 208000 events.
[14:03:25.653] <TB0> INFO: 208000 events read in total (9030ms).
[14:03:25.654] <TB0> INFO: Test took 9872ms.
[14:03:25.703] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 50 .. 97 (-1/-1) hits flags = 528 (plus default)
[14:03:25.714] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:03:25.714] <TB0> INFO: run 1 of 1
[14:03:25.992] <TB0> INFO: Expecting 1597440 events.
[14:03:55.417] <TB0> INFO: 717776 events read in total (28833ms).
[14:04:23.502] <TB0> INFO: 1434768 events read in total (56919ms).
[14:04:30.184] <TB0> INFO: 1597440 events read in total (63601ms).
[14:04:30.209] <TB0> INFO: Test took 64495ms.
[14:04:45.765] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 65.752382 .. 82.992354
[14:04:45.998] <TB0> INFO: Expecting 208000 events.
[14:04:55.875] <TB0> INFO: 208000 events read in total (9285ms).
[14:04:55.876] <TB0> INFO: Test took 10110ms.
[14:04:55.955] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 55 .. 92 (-1/-1) hits flags = 528 (plus default)
[14:04:55.968] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:04:55.968] <TB0> INFO: run 1 of 1
[14:04:56.246] <TB0> INFO: Expecting 1264640 events.
[14:05:26.273] <TB0> INFO: 733128 events read in total (29436ms).
[14:05:47.323] <TB0> INFO: 1264640 events read in total (50486ms).
[14:05:47.346] <TB0> INFO: Test took 51378ms.
[14:06:03.542] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 67.848125 .. 82.201804
[14:06:03.780] <TB0> INFO: Expecting 208000 events.
[14:06:13.423] <TB0> INFO: 208000 events read in total (9051ms).
[14:06:13.424] <TB0> INFO: Test took 9880ms.
[14:06:13.472] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 57 .. 92 (-1/-1) hits flags = 528 (plus default)
[14:06:13.481] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:06:13.481] <TB0> INFO: run 1 of 1
[14:06:13.759] <TB0> INFO: Expecting 1198080 events.
[14:06:43.614] <TB0> INFO: 727216 events read in total (29263ms).
[14:07:02.140] <TB0> INFO: 1198080 events read in total (47790ms).
[14:07:02.163] <TB0> INFO: Test took 48682ms.
[14:07:17.648] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[14:07:17.648] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[14:07:17.661] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:07:17.661] <TB0> INFO: run 1 of 1
[14:07:17.939] <TB0> INFO: Expecting 1364480 events.
[14:07:46.171] <TB0> INFO: 669056 events read in total (27641ms).
[14:08:14.397] <TB0> INFO: 1337752 events read in total (55867ms).
[14:08:15.878] <TB0> INFO: 1364480 events read in total (57348ms).
[14:08:15.897] <TB0> INFO: Test took 58236ms.
[14:08:33.423] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C0.dat
[14:08:33.424] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C1.dat
[14:08:33.424] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C2.dat
[14:08:33.424] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C3.dat
[14:08:33.424] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C4.dat
[14:08:33.424] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C5.dat
[14:08:33.424] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C6.dat
[14:08:33.424] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C7.dat
[14:08:33.424] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C8.dat
[14:08:33.424] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C9.dat
[14:08:33.424] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C10.dat
[14:08:33.424] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C11.dat
[14:08:33.425] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C12.dat
[14:08:33.425] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C13.dat
[14:08:33.425] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C14.dat
[14:08:33.425] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//dacParameters80_C15.dat
[14:08:33.425] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C0.dat
[14:08:33.433] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C1.dat
[14:08:33.439] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C2.dat
[14:08:33.447] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C3.dat
[14:08:33.456] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C4.dat
[14:08:33.462] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C5.dat
[14:08:33.471] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C6.dat
[14:08:33.479] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C7.dat
[14:08:33.488] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C8.dat
[14:08:33.497] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C9.dat
[14:08:33.505] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C10.dat
[14:08:33.513] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C11.dat
[14:08:33.521] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C12.dat
[14:08:33.529] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C13.dat
[14:08:33.537] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C14.dat
[14:08:33.545] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1104_FullQualification_2016-11-02_09h46m_1478076416//003_FulltestTrim80_p17//trimParameters80_C15.dat
[14:08:33.552] <TB0> INFO: PixTestTrim80::trimTest() done
[14:08:33.552] <TB0> INFO: vtrim: 131 99 119 111 113 96 110 114 96 83 120 123 111 100 112 113
[14:08:33.552] <TB0> INFO: vthrcomp: 76 80 76 79 83 83 72 72 71 71 80 76 78 77 76 76
[14:08:33.552] <TB0> INFO: vcal mean: 80.04 80.01 80.02 80.02 80.00 80.03 80.03 80.04 79.97 80.03 79.99 80.08 80.01 80.02 80.05 79.99
[14:08:33.552] <TB0> INFO: vcal RMS: 0.92 0.75 0.93 0.82 0.94 0.77 0.85 0.93 0.77 0.76 0.84 1.02 0.78 0.76 0.81 0.82
[14:08:33.552] <TB0> INFO: bits mean: 9.99 10.11 9.21 9.87 10.56 10.26 10.18 10.19 10.94 10.48 10.41 9.97 9.77 9.28 9.52 9.22
[14:08:33.552] <TB0> INFO: bits RMS: 2.05 2.24 2.21 2.11 2.24 2.24 2.16 2.07 2.18 2.32 2.13 2.05 2.12 2.19 2.22 2.24
[14:08:33.558] <TB0> INFO: ----------------------------------------------------------------------
[14:08:33.558] <TB0> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:08:33.558] <TB0> INFO: ----------------------------------------------------------------------
[14:08:33.561] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:08:33.572] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:08:33.573] <TB0> INFO: run 1 of 1
[14:08:33.847] <TB0> INFO: Expecting 4160000 events.
[14:09:05.973] <TB0> INFO: 761890 events read in total (31535ms).
[14:09:37.217] <TB0> INFO: 1518330 events read in total (62779ms).
[14:10:08.875] <TB0> INFO: 2271105 events read in total (94437ms).
[14:10:40.013] <TB0> INFO: 3019355 events read in total (125575ms).
[14:11:11.697] <TB0> INFO: 3764860 events read in total (157259ms).
[14:11:29.156] <TB0> INFO: 4160000 events read in total (174718ms).
[14:11:29.204] <TB0> INFO: Test took 175631ms.
[14:11:52.184] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[14:11:52.195] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:11:52.195] <TB0> INFO: run 1 of 1
[14:11:52.431] <TB0> INFO: Expecting 4430400 events.
[14:12:23.524] <TB0> INFO: 719965 events read in total (30501ms).
[14:12:53.917] <TB0> INFO: 1436385 events read in total (60894ms).
[14:13:24.402] <TB0> INFO: 2149590 events read in total (91379ms).
[14:13:54.934] <TB0> INFO: 2860255 events read in total (121911ms).
[14:14:25.555] <TB0> INFO: 3568000 events read in total (152532ms).
[14:14:55.803] <TB0> INFO: 4275320 events read in total (182780ms).
[14:15:02.762] <TB0> INFO: 4430400 events read in total (189739ms).
[14:15:02.819] <TB0> INFO: Test took 190624ms.
[14:15:31.977] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 195 (-1/-1) hits flags = 528 (plus default)
[14:15:31.987] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:15:31.988] <TB0> INFO: run 1 of 1
[14:15:32.255] <TB0> INFO: Expecting 4076800 events.
[14:16:03.691] <TB0> INFO: 742785 events read in total (30845ms).
[14:16:34.338] <TB0> INFO: 1480930 events read in total (61492ms).
[14:17:05.245] <TB0> INFO: 2216100 events read in total (92399ms).
[14:17:36.113] <TB0> INFO: 2946740 events read in total (123267ms).
[14:18:06.852] <TB0> INFO: 3674575 events read in total (154006ms).
[14:18:24.369] <TB0> INFO: 4076800 events read in total (171523ms).
[14:18:24.429] <TB0> INFO: Test took 172441ms.
[14:18:51.526] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 195 (-1/-1) hits flags = 528 (plus default)
[14:18:51.536] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:18:51.536] <TB0> INFO: run 1 of 1
[14:18:51.768] <TB0> INFO: Expecting 4076800 events.
[14:19:23.419] <TB0> INFO: 743085 events read in total (31060ms).
[14:19:54.596] <TB0> INFO: 1481625 events read in total (62237ms).
[14:20:25.816] <TB0> INFO: 2217155 events read in total (93457ms).
[14:20:57.036] <TB0> INFO: 2948170 events read in total (124677ms).
[14:21:27.910] <TB0> INFO: 3676340 events read in total (155551ms).
[14:21:45.648] <TB0> INFO: 4076800 events read in total (173289ms).
[14:21:45.696] <TB0> INFO: Test took 174161ms.
[14:22:15.129] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 195 (-1/-1) hits flags = 528 (plus default)
[14:22:15.139] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:22:15.139] <TB0> INFO: run 1 of 1
[14:22:15.372] <TB0> INFO: Expecting 4076800 events.
[14:22:47.016] <TB0> INFO: 742935 events read in total (31053ms).
[14:23:17.809] <TB0> INFO: 1481335 events read in total (61846ms).
[14:23:48.730] <TB0> INFO: 2216745 events read in total (92767ms).
[14:24:19.601] <TB0> INFO: 2947545 events read in total (123638ms).
[14:24:50.455] <TB0> INFO: 3675610 events read in total (154492ms).
[14:25:07.250] <TB0> INFO: 4076800 events read in total (171287ms).
[14:25:07.298] <TB0> INFO: Test took 172159ms.
[14:25:37.498] <TB0> INFO: PixTestTrim80::trimBitTest() done
[14:25:37.500] <TB0> INFO: PixTestTrim80::doTest() done, duration: 2288 seconds
[14:25:38.312] <TB0> INFO: enter test to run
[14:25:38.312] <TB0> INFO: test: exit no parameter change
[14:25:38.426] <TB0> QUIET: Connection to board 73 closed.
[14:25:38.427] <TB0> INFO: pXar: this is the end, my friend