[10:29:27.818] <TB2> INFO: *** Welcome to pxar ***
[10:29:27.818] <TB2> INFO: *** Today: 2016/11/02
[10:29:27.824] <TB2> INFO: *** Version: c8ba-dirty
[10:29:27.824] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C15.dat
[10:29:27.825] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//tbmParameters_C1b.dat
[10:29:27.825] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//defaultMaskFile.dat
[10:29:27.825] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters_C15.dat
[10:29:27.889] <TB2> INFO: clk: 4
[10:29:27.889] <TB2> INFO: ctr: 4
[10:29:27.889] <TB2> INFO: sda: 19
[10:29:27.889] <TB2> INFO: tin: 9
[10:29:27.889] <TB2> INFO: level: 15
[10:29:27.889] <TB2> INFO: triggerdelay: 0
[10:29:27.889] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[10:29:27.889] <TB2> INFO: Log level: INFO
[10:29:27.897] <TB2> INFO: Found DTB DTB_WWXUD2
[10:29:27.904] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[10:29:27.906] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[10:29:27.908] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[10:29:29.401] <TB2> INFO: DUT info:
[10:29:29.401] <TB2> INFO: The DUT currently contains the following objects:
[10:29:29.401] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[10:29:29.401] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:29:29.401] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:29:29.401] <TB2> INFO: TBM Core alpha (2): 7 registers set
[10:29:29.401] <TB2> INFO: TBM Core beta (3): 7 registers set
[10:29:29.401] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[10:29:29.401] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.401] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:29.802] <TB2> INFO: enter 'restricted' command line mode
[10:29:29.802] <TB2> INFO: enter test to run
[10:29:29.802] <TB2> INFO: test: pretest no parameter change
[10:29:29.802] <TB2> INFO: running: pretest
[10:29:29.810] <TB2> INFO: ######################################################################
[10:29:29.810] <TB2> INFO: PixTestPretest::doTest()
[10:29:29.810] <TB2> INFO: ######################################################################
[10:29:29.811] <TB2> INFO: ----------------------------------------------------------------------
[10:29:29.811] <TB2> INFO: PixTestPretest::programROC()
[10:29:29.811] <TB2> INFO: ----------------------------------------------------------------------
[10:29:47.825] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[10:29:47.826] <TB2> INFO: IA differences per ROC: 20.1 17.7 19.3 19.3 18.5 20.9 20.1 19.3 20.1 21.7 18.5 18.5 20.1 18.5 20.1 19.3
[10:29:47.891] <TB2> INFO: ----------------------------------------------------------------------
[10:29:47.891] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[10:29:47.891] <TB2> INFO: ----------------------------------------------------------------------
[10:29:53.992] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 383.5 mA = 23.9688 mA/ROC
[10:29:53.992] <TB2> INFO: i(loss) [mA/ROC]: 19.3 18.5 18.5 18.5 19.3 18.5 19.3 18.5 18.5 18.5 18.5 18.5 18.5 19.3 19.3 18.5
[10:29:54.026] <TB2> INFO: ----------------------------------------------------------------------
[10:29:54.026] <TB2> INFO: PixTestPretest::findTiming()
[10:29:54.026] <TB2> INFO: ----------------------------------------------------------------------
[10:29:54.026] <TB2> INFO: PixTestCmd::init()

[10:30:26.457] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[10:30:26.457] <TB2> INFO: (success/tries = 100/100), width = 4
[10:30:27.960] <TB2> INFO: ----------------------------------------------------------------------
[10:30:27.960] <TB2> INFO: PixTestPretest::findWorkingPixel()
[10:30:27.960] <TB2> INFO: ----------------------------------------------------------------------
[10:30:28.055] <TB2> INFO: Expecting 231680 events.
[10:30:38.020] <TB2> INFO: 231680 events read in total (9363ms).
[10:30:38.033] <TB2> INFO: Test took 10068ms.
[10:30:38.288] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[10:30:38.323] <TB2> INFO: ----------------------------------------------------------------------
[10:30:38.323] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[10:30:38.323] <TB2> INFO: ----------------------------------------------------------------------
[10:30:38.418] <TB2> INFO: Expecting 231680 events.
[10:30:48.564] <TB2> INFO: 231680 events read in total (9554ms).
[10:30:48.576] <TB2> INFO: Test took 10248ms.
[10:30:48.844] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[10:30:48.844] <TB2> INFO: CalDel: 99 96 105 90 91 96 112 98 93 90 76 92 103 96 93 80
[10:30:48.844] <TB2> INFO: VthrComp: 51 51 51 51 51 55 51 51 51 51 51 51 51 51 51 51
[10:30:48.848] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C0.dat
[10:30:48.848] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C1.dat
[10:30:48.848] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C2.dat
[10:30:48.848] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C3.dat
[10:30:48.849] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C4.dat
[10:30:48.849] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C5.dat
[10:30:48.849] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C6.dat
[10:30:48.849] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C7.dat
[10:30:48.849] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C8.dat
[10:30:48.850] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C9.dat
[10:30:48.850] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C10.dat
[10:30:48.850] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C11.dat
[10:30:48.850] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C12.dat
[10:30:48.850] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C13.dat
[10:30:48.851] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C14.dat
[10:30:48.851] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C15.dat
[10:30:48.851] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//tbmParameters_C0a.dat
[10:30:48.851] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//tbmParameters_C0b.dat
[10:30:48.851] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//tbmParameters_C1a.dat
[10:30:48.851] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//tbmParameters_C1b.dat
[10:30:48.852] <TB2> INFO: PixTestPretest::doTest() done, duration: 79 seconds
[10:30:48.905] <TB2> INFO: enter test to run
[10:30:48.905] <TB2> INFO: test: FullTest no parameter change
[10:30:48.905] <TB2> INFO: running: fulltest
[10:30:48.905] <TB2> INFO: ######################################################################
[10:30:48.905] <TB2> INFO: PixTestFullTest::doTest()
[10:30:48.905] <TB2> INFO: ######################################################################
[10:30:48.906] <TB2> INFO: ######################################################################
[10:30:48.906] <TB2> INFO: PixTestAlive::doTest()
[10:30:48.906] <TB2> INFO: ######################################################################
[10:30:48.908] <TB2> INFO: ----------------------------------------------------------------------
[10:30:48.908] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:30:48.908] <TB2> INFO: ----------------------------------------------------------------------
[10:30:49.195] <TB2> INFO: Expecting 41600 events.
[10:30:52.693] <TB2> INFO: 41600 events read in total (2907ms).
[10:30:52.694] <TB2> INFO: Test took 3785ms.
[10:30:52.928] <TB2> INFO: PixTestAlive::aliveTest() done
[10:30:52.928] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:30:52.930] <TB2> INFO: ----------------------------------------------------------------------
[10:30:52.930] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:30:52.930] <TB2> INFO: ----------------------------------------------------------------------
[10:30:53.173] <TB2> INFO: Expecting 41600 events.
[10:30:56.246] <TB2> INFO: 41600 events read in total (2481ms).
[10:30:56.246] <TB2> INFO: Test took 3314ms.
[10:30:56.246] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[10:30:56.491] <TB2> INFO: PixTestAlive::maskTest() done
[10:30:56.491] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:30:56.492] <TB2> INFO: ----------------------------------------------------------------------
[10:30:56.493] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:30:56.493] <TB2> INFO: ----------------------------------------------------------------------
[10:30:56.735] <TB2> INFO: Expecting 41600 events.
[10:31:00.253] <TB2> INFO: 41600 events read in total (2926ms).
[10:31:00.254] <TB2> INFO: Test took 3760ms.
[10:31:00.486] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[10:31:00.486] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:31:00.486] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[10:31:00.486] <TB2> INFO: Decoding statistics:
[10:31:00.486] <TB2> INFO: General information:
[10:31:00.486] <TB2> INFO: 16bit words read: 0
[10:31:00.486] <TB2> INFO: valid events total: 0
[10:31:00.486] <TB2> INFO: empty events: 0
[10:31:00.486] <TB2> INFO: valid events with pixels: 0
[10:31:00.486] <TB2> INFO: valid pixel hits: 0
[10:31:00.486] <TB2> INFO: Event errors: 0
[10:31:00.486] <TB2> INFO: start marker: 0
[10:31:00.486] <TB2> INFO: stop marker: 0
[10:31:00.486] <TB2> INFO: overflow: 0
[10:31:00.487] <TB2> INFO: invalid 5bit words: 0
[10:31:00.487] <TB2> INFO: invalid XOR eye diagram: 0
[10:31:00.487] <TB2> INFO: frame (failed synchr.): 0
[10:31:00.487] <TB2> INFO: idle data (no TBM trl): 0
[10:31:00.487] <TB2> INFO: no data (only TBM hdr): 0
[10:31:00.487] <TB2> INFO: TBM errors: 0
[10:31:00.487] <TB2> INFO: flawed TBM headers: 0
[10:31:00.487] <TB2> INFO: flawed TBM trailers: 0
[10:31:00.487] <TB2> INFO: event ID mismatches: 0
[10:31:00.487] <TB2> INFO: ROC errors: 0
[10:31:00.487] <TB2> INFO: missing ROC header(s): 0
[10:31:00.487] <TB2> INFO: misplaced readback start: 0
[10:31:00.487] <TB2> INFO: Pixel decoding errors: 0
[10:31:00.487] <TB2> INFO: pixel data incomplete: 0
[10:31:00.487] <TB2> INFO: pixel address: 0
[10:31:00.487] <TB2> INFO: pulse height fill bit: 0
[10:31:00.487] <TB2> INFO: buffer corruption: 0
[10:31:00.495] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C15.dat
[10:31:00.496] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[10:31:00.496] <TB2> INFO: ######################################################################
[10:31:00.496] <TB2> INFO: PixTestReadback::doTest()
[10:31:00.496] <TB2> INFO: ######################################################################
[10:31:00.496] <TB2> INFO: ----------------------------------------------------------------------
[10:31:00.496] <TB2> INFO: PixTestReadback::CalibrateVd()
[10:31:00.496] <TB2> INFO: ----------------------------------------------------------------------
[10:31:10.464] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C0.dat
[10:31:10.464] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C1.dat
[10:31:10.464] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C2.dat
[10:31:10.464] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C3.dat
[10:31:10.464] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C4.dat
[10:31:10.464] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C5.dat
[10:31:10.465] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C6.dat
[10:31:10.465] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C7.dat
[10:31:10.465] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C8.dat
[10:31:10.465] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C9.dat
[10:31:10.465] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C10.dat
[10:31:10.465] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C11.dat
[10:31:10.465] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C12.dat
[10:31:10.465] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C13.dat
[10:31:10.465] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C14.dat
[10:31:10.466] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C15.dat
[10:31:10.500] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:31:10.501] <TB2> INFO: ----------------------------------------------------------------------
[10:31:10.501] <TB2> INFO: PixTestReadback::CalibrateVa()
[10:31:10.501] <TB2> INFO: ----------------------------------------------------------------------
[10:31:20.430] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C0.dat
[10:31:20.430] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C1.dat
[10:31:20.430] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C2.dat
[10:31:20.430] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C3.dat
[10:31:20.430] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C4.dat
[10:31:20.430] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C5.dat
[10:31:20.430] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C6.dat
[10:31:20.430] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C7.dat
[10:31:20.430] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C8.dat
[10:31:20.430] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C9.dat
[10:31:20.430] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C10.dat
[10:31:20.431] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C11.dat
[10:31:20.431] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C12.dat
[10:31:20.431] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C13.dat
[10:31:20.431] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C14.dat
[10:31:20.431] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C15.dat
[10:31:20.459] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:31:20.459] <TB2> INFO: ----------------------------------------------------------------------
[10:31:20.459] <TB2> INFO: PixTestReadback::readbackVbg()
[10:31:20.459] <TB2> INFO: ----------------------------------------------------------------------
[10:31:28.130] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:31:28.130] <TB2> INFO: ----------------------------------------------------------------------
[10:31:28.130] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[10:31:28.130] <TB2> INFO: ----------------------------------------------------------------------
[10:31:28.130] <TB2> INFO: Vbg will be calibrated using Vd calibration
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 160.3calibrated Vbg = 1.18349 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 149.9calibrated Vbg = 1.18048 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 156calibrated Vbg = 1.17935 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 154.9calibrated Vbg = 1.17774 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 147.6calibrated Vbg = 1.17377 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 148.2calibrated Vbg = 1.17552 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 154.2calibrated Vbg = 1.18443 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 157.9calibrated Vbg = 1.18164 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 155.8calibrated Vbg = 1.17741 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 148.9calibrated Vbg = 1.17333 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 151.8calibrated Vbg = 1.16864 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 150.1calibrated Vbg = 1.16923 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 153.3calibrated Vbg = 1.17819 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 145.3calibrated Vbg = 1.18004 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 145.8calibrated Vbg = 1.17714 :::*/*/*/*/
[10:31:28.130] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 146.8calibrated Vbg = 1.17902 :::*/*/*/*/
[10:31:28.135] <TB2> INFO: ----------------------------------------------------------------------
[10:31:28.135] <TB2> INFO: PixTestReadback::CalibrateIa()
[10:31:28.135] <TB2> INFO: ----------------------------------------------------------------------
[10:34:08.942] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C0.dat
[10:34:08.942] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C1.dat
[10:34:08.942] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C2.dat
[10:34:08.942] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C3.dat
[10:34:08.942] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C4.dat
[10:34:08.942] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C5.dat
[10:34:08.942] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C6.dat
[10:34:08.942] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C7.dat
[10:34:08.942] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C8.dat
[10:34:08.942] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C9.dat
[10:34:08.943] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C10.dat
[10:34:08.943] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C11.dat
[10:34:08.943] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C12.dat
[10:34:08.943] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C13.dat
[10:34:08.943] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C14.dat
[10:34:08.943] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C15.dat
[10:34:08.973] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:34:08.975] <TB2> INFO: PixTestReadback::doTest() done
[10:34:08.975] <TB2> INFO: Decoding statistics:
[10:34:08.975] <TB2> INFO: General information:
[10:34:08.975] <TB2> INFO: 16bit words read: 1536
[10:34:08.975] <TB2> INFO: valid events total: 256
[10:34:08.975] <TB2> INFO: empty events: 256
[10:34:08.975] <TB2> INFO: valid events with pixels: 0
[10:34:08.975] <TB2> INFO: valid pixel hits: 0
[10:34:08.975] <TB2> INFO: Event errors: 0
[10:34:08.975] <TB2> INFO: start marker: 0
[10:34:08.975] <TB2> INFO: stop marker: 0
[10:34:08.975] <TB2> INFO: overflow: 0
[10:34:08.975] <TB2> INFO: invalid 5bit words: 0
[10:34:08.975] <TB2> INFO: invalid XOR eye diagram: 0
[10:34:08.975] <TB2> INFO: frame (failed synchr.): 0
[10:34:08.975] <TB2> INFO: idle data (no TBM trl): 0
[10:34:08.975] <TB2> INFO: no data (only TBM hdr): 0
[10:34:08.975] <TB2> INFO: TBM errors: 0
[10:34:08.975] <TB2> INFO: flawed TBM headers: 0
[10:34:08.975] <TB2> INFO: flawed TBM trailers: 0
[10:34:08.975] <TB2> INFO: event ID mismatches: 0
[10:34:08.975] <TB2> INFO: ROC errors: 0
[10:34:08.975] <TB2> INFO: missing ROC header(s): 0
[10:34:08.976] <TB2> INFO: misplaced readback start: 0
[10:34:08.976] <TB2> INFO: Pixel decoding errors: 0
[10:34:08.976] <TB2> INFO: pixel data incomplete: 0
[10:34:08.976] <TB2> INFO: pixel address: 0
[10:34:08.976] <TB2> INFO: pulse height fill bit: 0
[10:34:08.976] <TB2> INFO: buffer corruption: 0
[10:34:09.030] <TB2> INFO: ######################################################################
[10:34:09.030] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[10:34:09.030] <TB2> INFO: ######################################################################
[10:34:09.033] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[10:34:09.074] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[10:34:09.074] <TB2> INFO: run 1 of 1
[10:34:09.314] <TB2> INFO: Expecting 3120000 events.
[10:34:40.319] <TB2> INFO: 656395 events read in total (30413ms).











[10:35:09.921] <TB2> INFO: 1304535 events read in total (60015ms).











[10:35:39.653] <TB2> INFO: 1946655 events read in total (89747ms).











[10:36:09.144] <TB2> INFO: 2587205 events read in total (119238ms).











[10:36:33.729] <TB2> INFO: 3120000 events read in total (143823ms).
[10:36:33.820] <TB2> INFO: Test took 144746ms.
[10:37:02.452] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 173 seconds
[10:37:02.452] <TB2> INFO: number of dead bumps (per ROC): 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[10:37:02.452] <TB2> INFO: separation cut (per ROC): 107 104 106 112 108 112 99 103 112 106 104 114 100 110 98 109
[10:37:02.452] <TB2> INFO: Decoding statistics:
[10:37:02.452] <TB2> INFO: General information:
[10:37:02.452] <TB2> INFO: 16bit words read: 0
[10:37:02.452] <TB2> INFO: valid events total: 0
[10:37:02.452] <TB2> INFO: empty events: 0
[10:37:02.452] <TB2> INFO: valid events with pixels: 0
[10:37:02.452] <TB2> INFO: valid pixel hits: 0
[10:37:02.452] <TB2> INFO: Event errors: 0
[10:37:02.452] <TB2> INFO: start marker: 0
[10:37:02.452] <TB2> INFO: stop marker: 0
[10:37:02.452] <TB2> INFO: overflow: 0
[10:37:02.452] <TB2> INFO: invalid 5bit words: 0
[10:37:02.452] <TB2> INFO: invalid XOR eye diagram: 0
[10:37:02.452] <TB2> INFO: frame (failed synchr.): 0
[10:37:02.452] <TB2> INFO: idle data (no TBM trl): 0
[10:37:02.452] <TB2> INFO: no data (only TBM hdr): 0
[10:37:02.452] <TB2> INFO: TBM errors: 0
[10:37:02.452] <TB2> INFO: flawed TBM headers: 0
[10:37:02.452] <TB2> INFO: flawed TBM trailers: 0
[10:37:02.452] <TB2> INFO: event ID mismatches: 0
[10:37:02.452] <TB2> INFO: ROC errors: 0
[10:37:02.452] <TB2> INFO: missing ROC header(s): 0
[10:37:02.452] <TB2> INFO: misplaced readback start: 0
[10:37:02.452] <TB2> INFO: Pixel decoding errors: 0
[10:37:02.452] <TB2> INFO: pixel data incomplete: 0
[10:37:02.452] <TB2> INFO: pixel address: 0
[10:37:02.452] <TB2> INFO: pulse height fill bit: 0
[10:37:02.452] <TB2> INFO: buffer corruption: 0
[10:37:02.493] <TB2> INFO: ######################################################################
[10:37:02.493] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:37:02.493] <TB2> INFO: ######################################################################
[10:37:02.493] <TB2> INFO: ----------------------------------------------------------------------
[10:37:02.493] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:37:02.493] <TB2> INFO: ----------------------------------------------------------------------
[10:37:02.493] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[10:37:02.508] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[10:37:02.508] <TB2> INFO: run 1 of 1
[10:37:02.822] <TB2> INFO: Expecting 36608000 events.
[10:37:26.229] <TB2> INFO: 668400 events read in total (22815ms).
[10:37:48.719] <TB2> INFO: 1325650 events read in total (45305ms).
[10:38:11.213] <TB2> INFO: 1979550 events read in total (67799ms).
[10:38:34.169] <TB2> INFO: 2634850 events read in total (90755ms).
[10:38:57.009] <TB2> INFO: 3289200 events read in total (113595ms).
[10:39:19.368] <TB2> INFO: 3943450 events read in total (135954ms).
[10:39:41.970] <TB2> INFO: 4597600 events read in total (158556ms).
[10:40:04.346] <TB2> INFO: 5250350 events read in total (180932ms).
[10:40:26.826] <TB2> INFO: 5904100 events read in total (203412ms).
[10:40:49.450] <TB2> INFO: 6557850 events read in total (226036ms).
[10:41:12.294] <TB2> INFO: 7211900 events read in total (248880ms).
[10:41:34.746] <TB2> INFO: 7864750 events read in total (271332ms).
[10:41:57.436] <TB2> INFO: 8517800 events read in total (294022ms).
[10:42:19.808] <TB2> INFO: 9170000 events read in total (316394ms).
[10:42:42.436] <TB2> INFO: 9822600 events read in total (339022ms).
[10:43:04.866] <TB2> INFO: 10472700 events read in total (361452ms).
[10:43:27.346] <TB2> INFO: 11124650 events read in total (383932ms).
[10:43:49.805] <TB2> INFO: 11774800 events read in total (406391ms).
[10:44:12.315] <TB2> INFO: 12425550 events read in total (428901ms).
[10:44:34.627] <TB2> INFO: 13078000 events read in total (451213ms).
[10:44:57.174] <TB2> INFO: 13731200 events read in total (473760ms).
[10:45:19.460] <TB2> INFO: 14384550 events read in total (496046ms).
[10:45:41.793] <TB2> INFO: 15034400 events read in total (518379ms).
[10:46:04.423] <TB2> INFO: 15684200 events read in total (541009ms).
[10:46:27.037] <TB2> INFO: 16332850 events read in total (563623ms).
[10:46:49.840] <TB2> INFO: 16983700 events read in total (586426ms).
[10:47:12.266] <TB2> INFO: 17632800 events read in total (608852ms).
[10:47:34.761] <TB2> INFO: 18282250 events read in total (631347ms).
[10:47:57.505] <TB2> INFO: 18928750 events read in total (654091ms).
[10:48:20.426] <TB2> INFO: 19577900 events read in total (677012ms).
[10:48:42.872] <TB2> INFO: 20224000 events read in total (699458ms).
[10:49:04.993] <TB2> INFO: 20871550 events read in total (721579ms).
[10:49:27.686] <TB2> INFO: 21519950 events read in total (744272ms).
[10:49:50.170] <TB2> INFO: 22168250 events read in total (766756ms).
[10:50:12.435] <TB2> INFO: 22815800 events read in total (789021ms).
[10:50:34.726] <TB2> INFO: 23460300 events read in total (811312ms).
[10:50:57.336] <TB2> INFO: 24107200 events read in total (833922ms).
[10:51:19.522] <TB2> INFO: 24752600 events read in total (856108ms).
[10:51:41.913] <TB2> INFO: 25398750 events read in total (878499ms).
[10:52:04.481] <TB2> INFO: 26044550 events read in total (901067ms).
[10:52:26.740] <TB2> INFO: 26690600 events read in total (923326ms).
[10:52:49.332] <TB2> INFO: 27337600 events read in total (945918ms).
[10:53:11.777] <TB2> INFO: 27983200 events read in total (968363ms).
[10:53:33.904] <TB2> INFO: 28629500 events read in total (990490ms).
[10:53:56.465] <TB2> INFO: 29274600 events read in total (1013051ms).
[10:54:19.026] <TB2> INFO: 29920750 events read in total (1035612ms).
[10:54:41.167] <TB2> INFO: 30567350 events read in total (1057753ms).
[10:55:03.444] <TB2> INFO: 31211900 events read in total (1080030ms).
[10:55:25.841] <TB2> INFO: 31857950 events read in total (1102427ms).
[10:55:48.223] <TB2> INFO: 32504300 events read in total (1124809ms).
[10:56:10.796] <TB2> INFO: 33149750 events read in total (1147382ms).
[10:56:33.490] <TB2> INFO: 33799100 events read in total (1170076ms).
[10:56:56.225] <TB2> INFO: 34444600 events read in total (1192811ms).
[10:57:18.733] <TB2> INFO: 35090650 events read in total (1215319ms).
[10:57:41.081] <TB2> INFO: 35735400 events read in total (1237667ms).
[10:58:03.570] <TB2> INFO: 36391550 events read in total (1260156ms).
[10:58:11.046] <TB2> INFO: 36608000 events read in total (1267632ms).
[10:58:11.151] <TB2> INFO: Test took 1268643ms.
[10:58:11.701] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:13.552] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:15.413] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:17.256] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:19.315] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:21.368] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:22.942] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:24.438] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:25.990] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:27.880] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:30.128] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:32.083] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:34.188] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:35.739] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:37.776] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:39.622] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:58:41.482] <TB2> INFO: PixTestScurves::scurves() done
[10:58:41.482] <TB2> INFO: Vcal mean: 119.35 114.55 119.27 118.91 114.22 128.92 107.26 103.49 118.78 109.32 112.02 116.65 106.10 111.80 98.97 109.80
[10:58:41.482] <TB2> INFO: Vcal RMS: 7.34 5.44 8.22 6.09 4.95 6.77 5.05 5.04 6.35 4.82 5.09 5.26 4.77 4.37 5.74 4.73
[10:58:41.482] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1298 seconds
[10:58:41.482] <TB2> INFO: Decoding statistics:
[10:58:41.482] <TB2> INFO: General information:
[10:58:41.482] <TB2> INFO: 16bit words read: 0
[10:58:41.482] <TB2> INFO: valid events total: 0
[10:58:41.482] <TB2> INFO: empty events: 0
[10:58:41.482] <TB2> INFO: valid events with pixels: 0
[10:58:41.482] <TB2> INFO: valid pixel hits: 0
[10:58:41.482] <TB2> INFO: Event errors: 0
[10:58:41.482] <TB2> INFO: start marker: 0
[10:58:41.482] <TB2> INFO: stop marker: 0
[10:58:41.482] <TB2> INFO: overflow: 0
[10:58:41.482] <TB2> INFO: invalid 5bit words: 0
[10:58:41.482] <TB2> INFO: invalid XOR eye diagram: 0
[10:58:41.482] <TB2> INFO: frame (failed synchr.): 0
[10:58:41.482] <TB2> INFO: idle data (no TBM trl): 0
[10:58:41.482] <TB2> INFO: no data (only TBM hdr): 0
[10:58:41.482] <TB2> INFO: TBM errors: 0
[10:58:41.482] <TB2> INFO: flawed TBM headers: 0
[10:58:41.482] <TB2> INFO: flawed TBM trailers: 0
[10:58:41.482] <TB2> INFO: event ID mismatches: 0
[10:58:41.482] <TB2> INFO: ROC errors: 0
[10:58:41.482] <TB2> INFO: missing ROC header(s): 0
[10:58:41.482] <TB2> INFO: misplaced readback start: 0
[10:58:41.482] <TB2> INFO: Pixel decoding errors: 0
[10:58:41.482] <TB2> INFO: pixel data incomplete: 0
[10:58:41.482] <TB2> INFO: pixel address: 0
[10:58:41.482] <TB2> INFO: pulse height fill bit: 0
[10:58:41.482] <TB2> INFO: buffer corruption: 0
[10:58:41.578] <TB2> INFO: ######################################################################
[10:58:41.578] <TB2> INFO: PixTestTrim::doTest()
[10:58:41.578] <TB2> INFO: ######################################################################
[10:58:41.580] <TB2> INFO: ----------------------------------------------------------------------
[10:58:41.580] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[10:58:41.580] <TB2> INFO: ----------------------------------------------------------------------
[10:58:41.641] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[10:58:41.641] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:58:41.658] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:58:41.658] <TB2> INFO: run 1 of 1
[10:58:41.931] <TB2> INFO: Expecting 5025280 events.
[10:59:12.364] <TB2> INFO: 811240 events read in total (29828ms).
[10:59:42.047] <TB2> INFO: 1618768 events read in total (59511ms).
[11:00:11.410] <TB2> INFO: 2423432 events read in total (88874ms).
[11:00:41.157] <TB2> INFO: 3225064 events read in total (118621ms).
[11:01:11.272] <TB2> INFO: 4023504 events read in total (148736ms).
[11:01:41.233] <TB2> INFO: 4820744 events read in total (178697ms).
[11:01:49.239] <TB2> INFO: 5025280 events read in total (186703ms).
[11:01:49.299] <TB2> INFO: Test took 187642ms.
[11:02:08.539] <TB2> INFO: ROC 0 VthrComp = 127
[11:02:08.540] <TB2> INFO: ROC 1 VthrComp = 121
[11:02:08.540] <TB2> INFO: ROC 2 VthrComp = 124
[11:02:08.540] <TB2> INFO: ROC 3 VthrComp = 127
[11:02:08.540] <TB2> INFO: ROC 4 VthrComp = 121
[11:02:08.540] <TB2> INFO: ROC 5 VthrComp = 133
[11:02:08.540] <TB2> INFO: ROC 6 VthrComp = 113
[11:02:08.540] <TB2> INFO: ROC 7 VthrComp = 111
[11:02:08.540] <TB2> INFO: ROC 8 VthrComp = 127
[11:02:08.540] <TB2> INFO: ROC 9 VthrComp = 117
[11:02:08.540] <TB2> INFO: ROC 10 VthrComp = 119
[11:02:08.540] <TB2> INFO: ROC 11 VthrComp = 126
[11:02:08.540] <TB2> INFO: ROC 12 VthrComp = 113
[11:02:08.541] <TB2> INFO: ROC 13 VthrComp = 117
[11:02:08.541] <TB2> INFO: ROC 14 VthrComp = 107
[11:02:08.541] <TB2> INFO: ROC 15 VthrComp = 118
[11:02:08.779] <TB2> INFO: Expecting 41600 events.
[11:02:12.296] <TB2> INFO: 41600 events read in total (2925ms).
[11:02:12.296] <TB2> INFO: Test took 3754ms.
[11:02:12.306] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[11:02:12.306] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:02:12.318] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:02:12.318] <TB2> INFO: run 1 of 1
[11:02:12.596] <TB2> INFO: Expecting 5025280 events.
[11:02:38.942] <TB2> INFO: 588224 events read in total (25755ms).
[11:03:04.732] <TB2> INFO: 1176480 events read in total (51545ms).
[11:03:30.620] <TB2> INFO: 1764864 events read in total (77433ms).
[11:03:56.716] <TB2> INFO: 2353288 events read in total (103529ms).
[11:04:23.047] <TB2> INFO: 2939624 events read in total (129860ms).
[11:04:48.862] <TB2> INFO: 3524680 events read in total (155675ms).
[11:05:14.871] <TB2> INFO: 4109216 events read in total (181684ms).
[11:05:40.546] <TB2> INFO: 4692520 events read in total (207359ms).
[11:05:55.430] <TB2> INFO: 5025280 events read in total (222243ms).
[11:05:55.518] <TB2> INFO: Test took 223200ms.
[11:06:21.985] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 62.3704 for pixel 2/73 mean/min/max = 46.0572/29.5869/62.5275
[11:06:21.986] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 59.5907 for pixel 51/76 mean/min/max = 46.0084/32.2936/59.7232
[11:06:21.986] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 64.3862 for pixel 6/58 mean/min/max = 46.829/29.0933/64.5646
[11:06:21.987] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 59.0249 for pixel 0/54 mean/min/max = 45.4505/31.855/59.046
[11:06:21.987] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 58.3858 for pixel 5/7 mean/min/max = 45.8014/33.1119/58.491
[11:06:21.988] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 67.1522 for pixel 50/62 mean/min/max = 51.439/35.6698/67.2083
[11:06:21.989] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 58.1109 for pixel 40/45 mean/min/max = 45.3877/32.4864/58.2891
[11:06:21.989] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 57.7712 for pixel 51/68 mean/min/max = 45.7943/33.7799/57.8088
[11:06:21.990] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 61.504 for pixel 10/78 mean/min/max = 46.4983/31.3425/61.654
[11:06:21.990] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 57.6378 for pixel 0/61 mean/min/max = 45.1197/32.357/57.8824
[11:06:21.991] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 59.4272 for pixel 20/10 mean/min/max = 45.5197/31.3979/59.6416
[11:06:21.991] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 58.544 for pixel 10/22 mean/min/max = 45.19/31.7452/58.6348
[11:06:21.992] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 57.2011 for pixel 10/3 mean/min/max = 45.2461/33.1166/57.3757
[11:06:21.992] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 57.4174 for pixel 22/2 mean/min/max = 45.2298/32.6992/57.7604
[11:06:21.993] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 59.9916 for pixel 16/77 mean/min/max = 47.0242/33.966/60.0825
[11:06:21.993] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 57.8101 for pixel 3/7 mean/min/max = 45.1481/32.2751/58.0211
[11:06:21.994] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:06:22.082] <TB2> INFO: Expecting 411648 events.
[11:06:31.516] <TB2> INFO: 411648 events read in total (8842ms).
[11:06:31.524] <TB2> INFO: Expecting 411648 events.
[11:06:40.579] <TB2> INFO: 411648 events read in total (8652ms).
[11:06:40.589] <TB2> INFO: Expecting 411648 events.
[11:06:49.750] <TB2> INFO: 411648 events read in total (8758ms).
[11:06:49.766] <TB2> INFO: Expecting 411648 events.
[11:06:58.851] <TB2> INFO: 411648 events read in total (8682ms).
[11:06:58.868] <TB2> INFO: Expecting 411648 events.
[11:07:08.144] <TB2> INFO: 411648 events read in total (8873ms).
[11:07:08.163] <TB2> INFO: Expecting 411648 events.
[11:07:17.548] <TB2> INFO: 411648 events read in total (8981ms).
[11:07:17.569] <TB2> INFO: Expecting 411648 events.
[11:07:26.875] <TB2> INFO: 411648 events read in total (8902ms).
[11:07:26.900] <TB2> INFO: Expecting 411648 events.
[11:07:36.178] <TB2> INFO: 411648 events read in total (8874ms).
[11:07:36.206] <TB2> INFO: Expecting 411648 events.
[11:07:45.580] <TB2> INFO: 411648 events read in total (8971ms).
[11:07:45.619] <TB2> INFO: Expecting 411648 events.
[11:07:54.967] <TB2> INFO: 411648 events read in total (8945ms).
[11:07:55.014] <TB2> INFO: Expecting 411648 events.
[11:08:04.436] <TB2> INFO: 411648 events read in total (9019ms).
[11:08:04.479] <TB2> INFO: Expecting 411648 events.
[11:08:13.901] <TB2> INFO: 411648 events read in total (9018ms).
[11:08:13.943] <TB2> INFO: Expecting 411648 events.
[11:08:23.266] <TB2> INFO: 411648 events read in total (8920ms).
[11:08:23.384] <TB2> INFO: Expecting 411648 events.
[11:08:32.717] <TB2> INFO: 411648 events read in total (8930ms).
[11:08:32.764] <TB2> INFO: Expecting 411648 events.
[11:08:42.199] <TB2> INFO: 411648 events read in total (9031ms).
[11:08:42.309] <TB2> INFO: Expecting 411648 events.
[11:08:51.763] <TB2> INFO: 411648 events read in total (9051ms).
[11:08:51.819] <TB2> INFO: Test took 149825ms.
[11:08:52.720] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[11:08:52.735] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:08:52.735] <TB2> INFO: run 1 of 1
[11:08:52.996] <TB2> INFO: Expecting 5025280 events.
[11:09:19.320] <TB2> INFO: 585040 events read in total (25733ms).
[11:09:45.480] <TB2> INFO: 1168608 events read in total (51894ms).
[11:10:11.751] <TB2> INFO: 1751872 events read in total (78164ms).
[11:10:37.930] <TB2> INFO: 2335024 events read in total (104343ms).
[11:11:04.409] <TB2> INFO: 2917840 events read in total (130822ms).
[11:11:30.666] <TB2> INFO: 3501168 events read in total (157079ms).
[11:11:56.663] <TB2> INFO: 4082248 events read in total (183076ms).
[11:12:22.937] <TB2> INFO: 4664504 events read in total (209350ms).
[11:12:39.356] <TB2> INFO: 5025280 events read in total (225769ms).
[11:12:39.541] <TB2> INFO: Test took 226808ms.
[11:13:05.271] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 1.424214 .. 133.935464
[11:13:05.509] <TB2> INFO: Expecting 208000 events.
[11:13:15.377] <TB2> INFO: 208000 events read in total (9278ms).
[11:13:15.380] <TB2> INFO: Test took 10108ms.
[11:13:15.447] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 143 (-1/-1) hits flags = 528 (plus default)
[11:13:15.462] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:13:15.462] <TB2> INFO: run 1 of 1
[11:13:15.740] <TB2> INFO: Expecting 4759040 events.
[11:13:41.958] <TB2> INFO: 589016 events read in total (25627ms).
[11:14:08.408] <TB2> INFO: 1178616 events read in total (52077ms).
[11:14:34.139] <TB2> INFO: 1768288 events read in total (77808ms).
[11:14:59.931] <TB2> INFO: 2357264 events read in total (103601ms).
[11:15:25.517] <TB2> INFO: 2945664 events read in total (129186ms).
[11:15:50.994] <TB2> INFO: 3533480 events read in total (154663ms).
[11:16:16.379] <TB2> INFO: 4120224 events read in total (180048ms).
[11:16:42.196] <TB2> INFO: 4706920 events read in total (205865ms).
[11:16:44.952] <TB2> INFO: 4759040 events read in total (208621ms).
[11:16:45.039] <TB2> INFO: Test took 209577ms.
[11:17:08.715] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.546885 .. 52.151854
[11:17:08.958] <TB2> INFO: Expecting 208000 events.
[11:17:18.867] <TB2> INFO: 208000 events read in total (9317ms).
[11:17:18.868] <TB2> INFO: Test took 10151ms.
[11:17:18.926] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 62 (-1/-1) hits flags = 528 (plus default)
[11:17:18.940] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:17:18.940] <TB2> INFO: run 1 of 1
[11:17:19.218] <TB2> INFO: Expecting 1530880 events.
[11:17:47.133] <TB2> INFO: 634728 events read in total (27323ms).
[11:18:13.993] <TB2> INFO: 1269000 events read in total (54183ms).
[11:18:25.553] <TB2> INFO: 1530880 events read in total (65744ms).
[11:18:25.597] <TB2> INFO: Test took 66657ms.
[11:18:40.255] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 25.484508 .. 49.500532
[11:18:40.498] <TB2> INFO: Expecting 208000 events.
[11:18:50.885] <TB2> INFO: 208000 events read in total (9796ms).
[11:18:50.887] <TB2> INFO: Test took 10631ms.
[11:18:50.948] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 59 (-1/-1) hits flags = 528 (plus default)
[11:18:50.962] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:18:50.962] <TB2> INFO: run 1 of 1
[11:18:51.240] <TB2> INFO: Expecting 1497600 events.
[11:19:19.743] <TB2> INFO: 652248 events read in total (27911ms).
[11:19:47.679] <TB2> INFO: 1303992 events read in total (55848ms).
[11:19:56.239] <TB2> INFO: 1497600 events read in total (64407ms).
[11:19:56.270] <TB2> INFO: Test took 65308ms.
[11:20:11.351] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 24.833707 .. 48.571122
[11:20:11.631] <TB2> INFO: Expecting 208000 events.
[11:20:21.685] <TB2> INFO: 208000 events read in total (9462ms).
[11:20:21.686] <TB2> INFO: Test took 10335ms.
[11:20:21.734] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 58 (-1/-1) hits flags = 528 (plus default)
[11:20:21.748] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:20:21.748] <TB2> INFO: run 1 of 1
[11:20:22.026] <TB2> INFO: Expecting 1497600 events.
[11:20:50.420] <TB2> INFO: 660056 events read in total (27803ms).
[11:21:18.594] <TB2> INFO: 1319616 events read in total (55978ms).
[11:21:26.448] <TB2> INFO: 1497600 events read in total (63831ms).
[11:21:26.487] <TB2> INFO: Test took 64739ms.
[11:21:41.756] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[11:21:41.756] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[11:21:41.770] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:21:41.770] <TB2> INFO: run 1 of 1
[11:21:42.027] <TB2> INFO: Expecting 1364480 events.
[11:22:10.536] <TB2> INFO: 667416 events read in total (27918ms).
[11:22:37.912] <TB2> INFO: 1334016 events read in total (55294ms).
[11:22:39.755] <TB2> INFO: 1364480 events read in total (57138ms).
[11:22:39.784] <TB2> INFO: Test took 58015ms.
[11:22:55.253] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C0.dat
[11:22:55.253] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C1.dat
[11:22:55.253] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C2.dat
[11:22:55.254] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C3.dat
[11:22:55.254] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C4.dat
[11:22:55.254] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C5.dat
[11:22:55.254] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C6.dat
[11:22:55.254] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C7.dat
[11:22:55.254] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C8.dat
[11:22:55.254] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C9.dat
[11:22:55.254] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C10.dat
[11:22:55.254] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C11.dat
[11:22:55.254] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C12.dat
[11:22:55.254] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C13.dat
[11:22:55.255] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C14.dat
[11:22:55.255] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C15.dat
[11:22:55.255] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C0.dat
[11:22:55.261] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C1.dat
[11:22:55.266] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C2.dat
[11:22:55.271] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C3.dat
[11:22:55.276] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C4.dat
[11:22:55.281] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C5.dat
[11:22:55.286] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C6.dat
[11:22:55.291] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C7.dat
[11:22:55.296] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C8.dat
[11:22:55.301] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C9.dat
[11:22:55.305] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C10.dat
[11:22:55.311] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C11.dat
[11:22:55.315] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C12.dat
[11:22:55.320] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C13.dat
[11:22:55.325] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C14.dat
[11:22:55.330] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C15.dat
[11:22:55.334] <TB2> INFO: PixTestTrim::trimTest() done
[11:22:55.334] <TB2> INFO: vtrim: 153 118 146 114 125 158 122 112 154 99 131 142 112 117 138 140
[11:22:55.334] <TB2> INFO: vthrcomp: 127 121 124 127 121 133 113 111 127 117 119 126 113 117 107 118
[11:22:55.334] <TB2> INFO: vcal mean: 34.94 34.98 34.98 34.98 34.96 35.18 34.96 34.97 34.97 34.95 34.95 34.96 34.93 34.96 35.03 34.97
[11:22:55.334] <TB2> INFO: vcal RMS: 1.10 1.03 1.22 1.08 0.96 1.37 0.99 0.93 1.10 1.04 1.10 1.09 1.03 1.02 0.95 1.00
[11:22:55.334] <TB2> INFO: bits mean: 10.10 9.29 10.08 9.39 9.24 8.80 9.83 9.27 9.99 8.37 9.84 9.88 9.38 9.68 8.76 9.79
[11:22:55.334] <TB2> INFO: bits RMS: 2.67 2.76 2.73 2.81 2.67 2.30 2.51 2.52 2.49 3.16 2.63 2.58 2.65 2.60 2.67 2.57
[11:22:55.342] <TB2> INFO: ----------------------------------------------------------------------
[11:22:55.342] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[11:22:55.342] <TB2> INFO: ----------------------------------------------------------------------
[11:22:55.346] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[11:22:55.361] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:22:55.361] <TB2> INFO: run 1 of 1
[11:22:55.641] <TB2> INFO: Expecting 4160000 events.
[11:23:27.828] <TB2> INFO: 735335 events read in total (31596ms).
[11:23:58.740] <TB2> INFO: 1464960 events read in total (62508ms).
[11:24:30.035] <TB2> INFO: 2191260 events read in total (93803ms).
[11:25:01.124] <TB2> INFO: 2913590 events read in total (124892ms).
[11:25:32.409] <TB2> INFO: 3634755 events read in total (156177ms).
[11:25:55.467] <TB2> INFO: 4160000 events read in total (179235ms).
[11:25:55.552] <TB2> INFO: Test took 180191ms.
[11:26:22.973] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[11:26:22.988] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:26:22.988] <TB2> INFO: run 1 of 1
[11:26:23.267] <TB2> INFO: Expecting 4284800 events.
[11:26:54.962] <TB2> INFO: 704325 events read in total (31103ms).
[11:27:25.089] <TB2> INFO: 1404900 events read in total (61230ms).
[11:27:55.722] <TB2> INFO: 2103030 events read in total (91863ms).
[11:28:26.144] <TB2> INFO: 2797330 events read in total (122285ms).
[11:28:56.928] <TB2> INFO: 3490650 events read in total (153069ms).
[11:29:27.586] <TB2> INFO: 4183345 events read in total (183727ms).
[11:29:32.426] <TB2> INFO: 4284800 events read in total (188567ms).
[11:29:32.509] <TB2> INFO: Test took 189521ms.
[11:30:01.744] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[11:30:01.758] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:30:01.758] <TB2> INFO: run 1 of 1
[11:30:01.999] <TB2> INFO: Expecting 4097600 events.
[11:30:33.272] <TB2> INFO: 715085 events read in total (30681ms).
[11:31:04.269] <TB2> INFO: 1425930 events read in total (61678ms).
[11:31:35.420] <TB2> INFO: 2134025 events read in total (92829ms).
[11:32:06.233] <TB2> INFO: 2837490 events read in total (123642ms).
[11:32:37.030] <TB2> INFO: 3539980 events read in total (154439ms).
[11:33:02.145] <TB2> INFO: 4097600 events read in total (179554ms).
[11:33:02.220] <TB2> INFO: Test took 180461ms.
[11:33:25.871] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 197 (-1/-1) hits flags = 528 (plus default)
[11:33:25.885] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:33:25.885] <TB2> INFO: run 1 of 1
[11:33:26.132] <TB2> INFO: Expecting 4118400 events.
[11:33:57.132] <TB2> INFO: 713710 events read in total (30409ms).
[11:34:28.257] <TB2> INFO: 1423225 events read in total (61534ms).
[11:34:59.462] <TB2> INFO: 2129960 events read in total (92739ms).
[11:35:30.620] <TB2> INFO: 2832315 events read in total (123897ms).
[11:36:01.408] <TB2> INFO: 3533915 events read in total (154685ms).
[11:36:26.931] <TB2> INFO: 4118400 events read in total (180208ms).
[11:36:26.002] <TB2> INFO: Test took 181118ms.
[11:36:54.355] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 197 (-1/-1) hits flags = 528 (plus default)
[11:36:54.367] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:36:54.367] <TB2> INFO: run 1 of 1
[11:36:54.604] <TB2> INFO: Expecting 4118400 events.
[11:37:26.277] <TB2> INFO: 713975 events read in total (31081ms).
[11:37:57.231] <TB2> INFO: 1423695 events read in total (62035ms).
[11:38:28.287] <TB2> INFO: 2130665 events read in total (93091ms).
[11:38:59.566] <TB2> INFO: 2833255 events read in total (124370ms).
[11:39:30.429] <TB2> INFO: 3534775 events read in total (155233ms).
[11:39:56.561] <TB2> INFO: 4118400 events read in total (181365ms).
[11:39:56.642] <TB2> INFO: Test took 182274ms.
[11:40:23.197] <TB2> INFO: PixTestTrim::trimBitTest() done
[11:40:23.199] <TB2> INFO: PixTestTrim::doTest() done, duration: 2501 seconds
[11:40:23.199] <TB2> INFO: Decoding statistics:
[11:40:23.199] <TB2> INFO: General information:
[11:40:23.199] <TB2> INFO: 16bit words read: 0
[11:40:23.199] <TB2> INFO: valid events total: 0
[11:40:23.199] <TB2> INFO: empty events: 0
[11:40:23.199] <TB2> INFO: valid events with pixels: 0
[11:40:23.199] <TB2> INFO: valid pixel hits: 0
[11:40:23.199] <TB2> INFO: Event errors: 0
[11:40:23.199] <TB2> INFO: start marker: 0
[11:40:23.199] <TB2> INFO: stop marker: 0
[11:40:23.199] <TB2> INFO: overflow: 0
[11:40:23.199] <TB2> INFO: invalid 5bit words: 0
[11:40:23.199] <TB2> INFO: invalid XOR eye diagram: 0
[11:40:23.199] <TB2> INFO: frame (failed synchr.): 0
[11:40:23.199] <TB2> INFO: idle data (no TBM trl): 0
[11:40:23.199] <TB2> INFO: no data (only TBM hdr): 0
[11:40:23.199] <TB2> INFO: TBM errors: 0
[11:40:23.199] <TB2> INFO: flawed TBM headers: 0
[11:40:23.199] <TB2> INFO: flawed TBM trailers: 0
[11:40:23.199] <TB2> INFO: event ID mismatches: 0
[11:40:23.199] <TB2> INFO: ROC errors: 0
[11:40:23.199] <TB2> INFO: missing ROC header(s): 0
[11:40:23.199] <TB2> INFO: misplaced readback start: 0
[11:40:23.199] <TB2> INFO: Pixel decoding errors: 0
[11:40:23.199] <TB2> INFO: pixel data incomplete: 0
[11:40:23.199] <TB2> INFO: pixel address: 0
[11:40:23.199] <TB2> INFO: pulse height fill bit: 0
[11:40:23.199] <TB2> INFO: buffer corruption: 0
[11:40:23.975] <TB2> INFO: ######################################################################
[11:40:23.975] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[11:40:23.975] <TB2> INFO: ######################################################################
[11:40:24.214] <TB2> INFO: Expecting 41600 events.
[11:40:27.720] <TB2> INFO: 41600 events read in total (2914ms).
[11:40:27.721] <TB2> INFO: Test took 3744ms.
[11:40:28.160] <TB2> INFO: Expecting 41600 events.
[11:40:31.693] <TB2> INFO: 41600 events read in total (2941ms).
[11:40:31.694] <TB2> INFO: Test took 3770ms.
[11:40:31.983] <TB2> INFO: Expecting 41600 events.
[11:40:35.562] <TB2> INFO: 41600 events read in total (2987ms).
[11:40:35.563] <TB2> INFO: Test took 3844ms.
[11:40:35.854] <TB2> INFO: Expecting 41600 events.
[11:40:39.349] <TB2> INFO: 41600 events read in total (2904ms).
[11:40:39.350] <TB2> INFO: Test took 3761ms.
[11:40:39.641] <TB2> INFO: Expecting 41600 events.
[11:40:43.245] <TB2> INFO: 41600 events read in total (3012ms).
[11:40:43.246] <TB2> INFO: Test took 3870ms.
[11:40:43.536] <TB2> INFO: Expecting 41600 events.
[11:40:47.145] <TB2> INFO: 41600 events read in total (3017ms).
[11:40:47.145] <TB2> INFO: Test took 3875ms.
[11:40:47.434] <TB2> INFO: Expecting 41600 events.
[11:40:51.030] <TB2> INFO: 41600 events read in total (3004ms).
[11:40:51.031] <TB2> INFO: Test took 3862ms.
[11:40:51.319] <TB2> INFO: Expecting 41600 events.
[11:40:54.963] <TB2> INFO: 41600 events read in total (3052ms).
[11:40:54.963] <TB2> INFO: Test took 3909ms.
[11:40:55.254] <TB2> INFO: Expecting 41600 events.
[11:40:58.738] <TB2> INFO: 41600 events read in total (2893ms).
[11:40:58.739] <TB2> INFO: Test took 3751ms.
[11:40:59.028] <TB2> INFO: Expecting 41600 events.
[11:41:02.524] <TB2> INFO: 41600 events read in total (2904ms).
[11:41:02.524] <TB2> INFO: Test took 3761ms.
[11:41:02.813] <TB2> INFO: Expecting 41600 events.
[11:41:06.313] <TB2> INFO: 41600 events read in total (2908ms).
[11:41:06.314] <TB2> INFO: Test took 3766ms.
[11:41:06.607] <TB2> INFO: Expecting 41600 events.
[11:41:10.139] <TB2> INFO: 41600 events read in total (2940ms).
[11:41:10.140] <TB2> INFO: Test took 3799ms.
[11:41:10.431] <TB2> INFO: Expecting 41600 events.
[11:41:14.121] <TB2> INFO: 41600 events read in total (3099ms).
[11:41:14.122] <TB2> INFO: Test took 3957ms.
[11:41:14.412] <TB2> INFO: Expecting 41600 events.
[11:41:17.938] <TB2> INFO: 41600 events read in total (2934ms).
[11:41:17.940] <TB2> INFO: Test took 3793ms.
[11:41:18.230] <TB2> INFO: Expecting 41600 events.
[11:41:21.727] <TB2> INFO: 41600 events read in total (2905ms).
[11:41:21.728] <TB2> INFO: Test took 3764ms.
[11:41:22.019] <TB2> INFO: Expecting 41600 events.
[11:41:25.603] <TB2> INFO: 41600 events read in total (2992ms).
[11:41:25.604] <TB2> INFO: Test took 3850ms.
[11:41:25.894] <TB2> INFO: Expecting 41600 events.
[11:41:29.383] <TB2> INFO: 41600 events read in total (2897ms).
[11:41:29.383] <TB2> INFO: Test took 3754ms.
[11:41:29.674] <TB2> INFO: Expecting 41600 events.
[11:41:33.209] <TB2> INFO: 41600 events read in total (2943ms).
[11:41:33.210] <TB2> INFO: Test took 3802ms.
[11:41:33.500] <TB2> INFO: Expecting 41600 events.
[11:41:37.042] <TB2> INFO: 41600 events read in total (2951ms).
[11:41:37.043] <TB2> INFO: Test took 3808ms.
[11:41:37.333] <TB2> INFO: Expecting 41600 events.
[11:41:40.990] <TB2> INFO: 41600 events read in total (3065ms).
[11:41:40.991] <TB2> INFO: Test took 3924ms.
[11:41:41.284] <TB2> INFO: Expecting 41600 events.
[11:41:44.839] <TB2> INFO: 41600 events read in total (2964ms).
[11:41:44.840] <TB2> INFO: Test took 3822ms.
[11:41:45.130] <TB2> INFO: Expecting 41600 events.
[11:41:48.748] <TB2> INFO: 41600 events read in total (3026ms).
[11:41:48.749] <TB2> INFO: Test took 3884ms.
[11:41:49.039] <TB2> INFO: Expecting 41600 events.
[11:41:52.548] <TB2> INFO: 41600 events read in total (2917ms).
[11:41:52.549] <TB2> INFO: Test took 3776ms.
[11:41:52.859] <TB2> INFO: Expecting 41600 events.
[11:41:56.516] <TB2> INFO: 41600 events read in total (3066ms).
[11:41:56.517] <TB2> INFO: Test took 3941ms.
[11:41:56.809] <TB2> INFO: Expecting 41600 events.
[11:42:00.391] <TB2> INFO: 41600 events read in total (2991ms).
[11:42:00.392] <TB2> INFO: Test took 3851ms.
[11:42:00.681] <TB2> INFO: Expecting 41600 events.
[11:42:04.209] <TB2> INFO: 41600 events read in total (2936ms).
[11:42:04.210] <TB2> INFO: Test took 3795ms.
[11:42:04.501] <TB2> INFO: Expecting 41600 events.
[11:42:07.997] <TB2> INFO: 41600 events read in total (2904ms).
[11:42:07.998] <TB2> INFO: Test took 3762ms.
[11:42:08.309] <TB2> INFO: Expecting 41600 events.
[11:42:11.920] <TB2> INFO: 41600 events read in total (3020ms).
[11:42:11.921] <TB2> INFO: Test took 3891ms.
[11:42:12.211] <TB2> INFO: Expecting 2560 events.
[11:42:13.095] <TB2> INFO: 2560 events read in total (292ms).
[11:42:13.095] <TB2> INFO: Test took 1161ms.
[11:42:13.403] <TB2> INFO: Expecting 2560 events.
[11:42:14.297] <TB2> INFO: 2560 events read in total (302ms).
[11:42:14.297] <TB2> INFO: Test took 1201ms.
[11:42:14.605] <TB2> INFO: Expecting 2560 events.
[11:42:15.489] <TB2> INFO: 2560 events read in total (292ms).
[11:42:15.489] <TB2> INFO: Test took 1191ms.
[11:42:15.796] <TB2> INFO: Expecting 2560 events.
[11:42:16.685] <TB2> INFO: 2560 events read in total (298ms).
[11:42:16.685] <TB2> INFO: Test took 1195ms.
[11:42:16.993] <TB2> INFO: Expecting 2560 events.
[11:42:17.874] <TB2> INFO: 2560 events read in total (289ms).
[11:42:17.875] <TB2> INFO: Test took 1190ms.
[11:42:18.182] <TB2> INFO: Expecting 2560 events.
[11:42:19.069] <TB2> INFO: 2560 events read in total (295ms).
[11:42:19.069] <TB2> INFO: Test took 1194ms.
[11:42:19.377] <TB2> INFO: Expecting 2560 events.
[11:42:20.258] <TB2> INFO: 2560 events read in total (289ms).
[11:42:20.258] <TB2> INFO: Test took 1189ms.
[11:42:20.567] <TB2> INFO: Expecting 2560 events.
[11:42:21.450] <TB2> INFO: 2560 events read in total (291ms).
[11:42:21.450] <TB2> INFO: Test took 1192ms.
[11:42:21.757] <TB2> INFO: Expecting 2560 events.
[11:42:22.643] <TB2> INFO: 2560 events read in total (294ms).
[11:42:22.643] <TB2> INFO: Test took 1192ms.
[11:42:22.951] <TB2> INFO: Expecting 2560 events.
[11:42:23.835] <TB2> INFO: 2560 events read in total (292ms).
[11:42:23.835] <TB2> INFO: Test took 1191ms.
[11:42:24.144] <TB2> INFO: Expecting 2560 events.
[11:42:25.035] <TB2> INFO: 2560 events read in total (300ms).
[11:42:25.035] <TB2> INFO: Test took 1199ms.
[11:42:25.344] <TB2> INFO: Expecting 2560 events.
[11:42:26.228] <TB2> INFO: 2560 events read in total (293ms).
[11:42:26.228] <TB2> INFO: Test took 1193ms.
[11:42:26.536] <TB2> INFO: Expecting 2560 events.
[11:42:27.420] <TB2> INFO: 2560 events read in total (292ms).
[11:42:27.420] <TB2> INFO: Test took 1191ms.
[11:42:27.728] <TB2> INFO: Expecting 2560 events.
[11:42:28.611] <TB2> INFO: 2560 events read in total (291ms).
[11:42:28.612] <TB2> INFO: Test took 1191ms.
[11:42:28.920] <TB2> INFO: Expecting 2560 events.
[11:42:29.805] <TB2> INFO: 2560 events read in total (293ms).
[11:42:29.805] <TB2> INFO: Test took 1193ms.
[11:42:30.113] <TB2> INFO: Expecting 2560 events.
[11:42:30.000] <TB2> INFO: 2560 events read in total (295ms).
[11:42:30.001] <TB2> INFO: Test took 1195ms.
[11:42:31.003] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:42:31.311] <TB2> INFO: Expecting 655360 events.
[11:42:46.005] <TB2> INFO: 655360 events read in total (14103ms).
[11:42:46.018] <TB2> INFO: Expecting 655360 events.
[11:43:00.612] <TB2> INFO: 655360 events read in total (14191ms).
[11:43:00.628] <TB2> INFO: Expecting 655360 events.
[11:43:15.113] <TB2> INFO: 655360 events read in total (14082ms).
[11:43:15.139] <TB2> INFO: Expecting 655360 events.
[11:43:29.499] <TB2> INFO: 655360 events read in total (13957ms).
[11:43:29.524] <TB2> INFO: Expecting 655360 events.
[11:43:44.020] <TB2> INFO: 655360 events read in total (14093ms).
[11:43:44.057] <TB2> INFO: Expecting 655360 events.
[11:43:58.617] <TB2> INFO: 655360 events read in total (14157ms).
[11:43:58.650] <TB2> INFO: Expecting 655360 events.
[11:44:13.173] <TB2> INFO: 655360 events read in total (14120ms).
[11:44:13.221] <TB2> INFO: Expecting 655360 events.
[11:44:27.779] <TB2> INFO: 655360 events read in total (14155ms).
[11:44:27.824] <TB2> INFO: Expecting 655360 events.
[11:44:42.308] <TB2> INFO: 655360 events read in total (14081ms).
[11:44:42.377] <TB2> INFO: Expecting 655360 events.
[11:44:56.815] <TB2> INFO: 655360 events read in total (14035ms).
[11:44:56.884] <TB2> INFO: Expecting 655360 events.
[11:45:11.291] <TB2> INFO: 655360 events read in total (14004ms).
[11:45:11.370] <TB2> INFO: Expecting 655360 events.
[11:45:25.730] <TB2> INFO: 655360 events read in total (13957ms).
[11:45:25.794] <TB2> INFO: Expecting 655360 events.
[11:45:40.332] <TB2> INFO: 655360 events read in total (14135ms).
[11:45:40.419] <TB2> INFO: Expecting 655360 events.
[11:45:54.899] <TB2> INFO: 655360 events read in total (14077ms).
[11:45:54.973] <TB2> INFO: Expecting 655360 events.
[11:46:09.435] <TB2> INFO: 655360 events read in total (14059ms).
[11:46:09.529] <TB2> INFO: Expecting 655360 events.
[11:46:24.020] <TB2> INFO: 655360 events read in total (14088ms).
[11:46:24.102] <TB2> INFO: Test took 233099ms.
[11:46:24.194] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:46:24.456] <TB2> INFO: Expecting 655360 events.
[11:46:39.029] <TB2> INFO: 655360 events read in total (13981ms).
[11:46:39.041] <TB2> INFO: Expecting 655360 events.
[11:46:53.498] <TB2> INFO: 655360 events read in total (14054ms).
[11:46:53.517] <TB2> INFO: Expecting 655360 events.
[11:47:07.916] <TB2> INFO: 655360 events read in total (13996ms).
[11:47:07.942] <TB2> INFO: Expecting 655360 events.
[11:47:22.414] <TB2> INFO: 655360 events read in total (14069ms).
[11:47:22.439] <TB2> INFO: Expecting 655360 events.
[11:47:36.908] <TB2> INFO: 655360 events read in total (14066ms).
[11:47:36.937] <TB2> INFO: Expecting 655360 events.
[11:47:51.587] <TB2> INFO: 655360 events read in total (14247ms).
[11:47:51.631] <TB2> INFO: Expecting 655360 events.
[11:48:06.219] <TB2> INFO: 655360 events read in total (14181ms).
[11:48:06.261] <TB2> INFO: Expecting 655360 events.
[11:48:20.863] <TB2> INFO: 655360 events read in total (14199ms).
[11:48:20.906] <TB2> INFO: Expecting 655360 events.
[11:48:34.903] <TB2> INFO: 655360 events read in total (13594ms).
[11:48:34.993] <TB2> INFO: Expecting 655360 events.
[11:48:49.258] <TB2> INFO: 655360 events read in total (13862ms).
[11:48:49.312] <TB2> INFO: Expecting 655360 events.
[11:49:03.337] <TB2> INFO: 655360 events read in total (13622ms).
[11:49:03.445] <TB2> INFO: Expecting 655360 events.
[11:49:17.618] <TB2> INFO: 655360 events read in total (13769ms).
[11:49:17.681] <TB2> INFO: Expecting 655360 events.
[11:49:31.948] <TB2> INFO: 655360 events read in total (13864ms).
[11:49:32.061] <TB2> INFO: Expecting 655360 events.
[11:49:46.988] <TB2> INFO: 655360 events read in total (14524ms).
[11:49:47.060] <TB2> INFO: Expecting 655360 events.
[11:50:02.140] <TB2> INFO: 655360 events read in total (14676ms).
[11:50:02.269] <TB2> INFO: Expecting 655360 events.
[11:50:17.233] <TB2> INFO: 655360 events read in total (14561ms).
[11:50:17.318] <TB2> INFO: Test took 233124ms.
[11:50:17.508] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.513] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.519] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.525] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.531] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.536] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.542] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.548] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.554] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.560] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.566] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:50:17.572] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:50:17.578] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[11:50:17.584] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[11:50:17.590] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[11:50:17.596] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[11:50:17.602] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[11:50:17.608] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[11:50:17.613] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[11:50:17.619] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.624] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.630] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.635] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:50:17.641] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.646] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.652] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:50:17.658] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:50:17.663] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:50:17.704] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C0.dat
[11:50:17.705] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C1.dat
[11:50:17.705] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C2.dat
[11:50:17.705] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C3.dat
[11:50:17.705] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C4.dat
[11:50:17.706] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C5.dat
[11:50:17.706] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C6.dat
[11:50:17.706] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C7.dat
[11:50:17.706] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C8.dat
[11:50:17.706] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C9.dat
[11:50:17.707] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C10.dat
[11:50:17.707] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C11.dat
[11:50:17.707] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C12.dat
[11:50:17.707] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C13.dat
[11:50:17.707] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C14.dat
[11:50:17.707] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C15.dat
[11:50:17.951] <TB2> INFO: Expecting 41600 events.
[11:50:21.150] <TB2> INFO: 41600 events read in total (2607ms).
[11:50:21.151] <TB2> INFO: Test took 3441ms.
[11:50:21.614] <TB2> INFO: Expecting 41600 events.
[11:50:24.683] <TB2> INFO: 41600 events read in total (2477ms).
[11:50:24.684] <TB2> INFO: Test took 3319ms.
[11:50:25.141] <TB2> INFO: Expecting 41600 events.
[11:50:28.337] <TB2> INFO: 41600 events read in total (2601ms).
[11:50:28.338] <TB2> INFO: Test took 3439ms.
[11:50:28.561] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:28.651] <TB2> INFO: Expecting 2560 events.
[11:50:29.546] <TB2> INFO: 2560 events read in total (303ms).
[11:50:29.546] <TB2> INFO: Test took 985ms.
[11:50:29.549] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:29.855] <TB2> INFO: Expecting 2560 events.
[11:50:30.751] <TB2> INFO: 2560 events read in total (304ms).
[11:50:30.751] <TB2> INFO: Test took 1203ms.
[11:50:30.754] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:31.061] <TB2> INFO: Expecting 2560 events.
[11:50:31.946] <TB2> INFO: 2560 events read in total (294ms).
[11:50:31.946] <TB2> INFO: Test took 1192ms.
[11:50:31.948] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:32.254] <TB2> INFO: Expecting 2560 events.
[11:50:33.147] <TB2> INFO: 2560 events read in total (301ms).
[11:50:33.148] <TB2> INFO: Test took 1200ms.
[11:50:33.151] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:33.456] <TB2> INFO: Expecting 2560 events.
[11:50:34.345] <TB2> INFO: 2560 events read in total (297ms).
[11:50:34.346] <TB2> INFO: Test took 1195ms.
[11:50:34.349] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:34.654] <TB2> INFO: Expecting 2560 events.
[11:50:35.540] <TB2> INFO: 2560 events read in total (294ms).
[11:50:35.540] <TB2> INFO: Test took 1192ms.
[11:50:35.544] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:35.851] <TB2> INFO: Expecting 2560 events.
[11:50:36.748] <TB2> INFO: 2560 events read in total (304ms).
[11:50:36.748] <TB2> INFO: Test took 1204ms.
[11:50:36.751] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:37.056] <TB2> INFO: Expecting 2560 events.
[11:50:37.949] <TB2> INFO: 2560 events read in total (301ms).
[11:50:37.950] <TB2> INFO: Test took 1199ms.
[11:50:37.952] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:38.258] <TB2> INFO: Expecting 2560 events.
[11:50:39.142] <TB2> INFO: 2560 events read in total (292ms).
[11:50:39.143] <TB2> INFO: Test took 1191ms.
[11:50:39.146] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:39.452] <TB2> INFO: Expecting 2560 events.
[11:50:40.331] <TB2> INFO: 2560 events read in total (288ms).
[11:50:40.332] <TB2> INFO: Test took 1186ms.
[11:50:40.336] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:40.640] <TB2> INFO: Expecting 2560 events.
[11:50:41.521] <TB2> INFO: 2560 events read in total (289ms).
[11:50:41.521] <TB2> INFO: Test took 1185ms.
[11:50:41.524] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:41.829] <TB2> INFO: Expecting 2560 events.
[11:50:42.710] <TB2> INFO: 2560 events read in total (287ms).
[11:50:42.711] <TB2> INFO: Test took 1187ms.
[11:50:42.712] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:43.019] <TB2> INFO: Expecting 2560 events.
[11:50:43.907] <TB2> INFO: 2560 events read in total (297ms).
[11:50:43.907] <TB2> INFO: Test took 1195ms.
[11:50:43.909] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:44.216] <TB2> INFO: Expecting 2560 events.
[11:50:45.097] <TB2> INFO: 2560 events read in total (289ms).
[11:50:45.097] <TB2> INFO: Test took 1188ms.
[11:50:45.101] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:45.405] <TB2> INFO: Expecting 2560 events.
[11:50:46.289] <TB2> INFO: 2560 events read in total (290ms).
[11:50:46.290] <TB2> INFO: Test took 1189ms.
[11:50:46.292] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:46.598] <TB2> INFO: Expecting 2560 events.
[11:50:47.478] <TB2> INFO: 2560 events read in total (289ms).
[11:50:47.479] <TB2> INFO: Test took 1187ms.
[11:50:47.480] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:47.788] <TB2> INFO: Expecting 2560 events.
[11:50:48.671] <TB2> INFO: 2560 events read in total (292ms).
[11:50:48.672] <TB2> INFO: Test took 1192ms.
[11:50:48.674] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:48.980] <TB2> INFO: Expecting 2560 events.
[11:50:49.867] <TB2> INFO: 2560 events read in total (295ms).
[11:50:49.868] <TB2> INFO: Test took 1195ms.
[11:50:49.870] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:50.177] <TB2> INFO: Expecting 2560 events.
[11:50:51.057] <TB2> INFO: 2560 events read in total (288ms).
[11:50:51.058] <TB2> INFO: Test took 1188ms.
[11:50:51.060] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:51.366] <TB2> INFO: Expecting 2560 events.
[11:50:52.247] <TB2> INFO: 2560 events read in total (289ms).
[11:50:52.247] <TB2> INFO: Test took 1187ms.
[11:50:52.252] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:52.556] <TB2> INFO: Expecting 2560 events.
[11:50:53.438] <TB2> INFO: 2560 events read in total (290ms).
[11:50:53.438] <TB2> INFO: Test took 1186ms.
[11:50:53.441] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:53.747] <TB2> INFO: Expecting 2560 events.
[11:50:54.637] <TB2> INFO: 2560 events read in total (298ms).
[11:50:54.638] <TB2> INFO: Test took 1197ms.
[11:50:54.641] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:54.946] <TB2> INFO: Expecting 2560 events.
[11:50:55.837] <TB2> INFO: 2560 events read in total (299ms).
[11:50:55.838] <TB2> INFO: Test took 1197ms.
[11:50:55.841] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:56.146] <TB2> INFO: Expecting 2560 events.
[11:50:57.031] <TB2> INFO: 2560 events read in total (293ms).
[11:50:57.031] <TB2> INFO: Test took 1190ms.
[11:50:57.034] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:57.340] <TB2> INFO: Expecting 2560 events.
[11:50:58.234] <TB2> INFO: 2560 events read in total (302ms).
[11:50:58.234] <TB2> INFO: Test took 1200ms.
[11:50:58.238] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:58.542] <TB2> INFO: Expecting 2560 events.
[11:50:59.429] <TB2> INFO: 2560 events read in total (295ms).
[11:50:59.429] <TB2> INFO: Test took 1191ms.
[11:50:59.432] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:59.738] <TB2> INFO: Expecting 2560 events.
[11:51:00.628] <TB2> INFO: 2560 events read in total (298ms).
[11:51:00.628] <TB2> INFO: Test took 1196ms.
[11:51:00.632] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:51:00.937] <TB2> INFO: Expecting 2560 events.
[11:51:01.823] <TB2> INFO: 2560 events read in total (294ms).
[11:51:01.823] <TB2> INFO: Test took 1192ms.
[11:51:01.825] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:51:02.131] <TB2> INFO: Expecting 2560 events.
[11:51:03.024] <TB2> INFO: 2560 events read in total (301ms).
[11:51:03.024] <TB2> INFO: Test took 1199ms.
[11:51:03.027] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:51:03.332] <TB2> INFO: Expecting 2560 events.
[11:51:04.214] <TB2> INFO: 2560 events read in total (290ms).
[11:51:04.215] <TB2> INFO: Test took 1188ms.
[11:51:04.218] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:51:04.523] <TB2> INFO: Expecting 2560 events.
[11:51:05.418] <TB2> INFO: 2560 events read in total (303ms).
[11:51:05.418] <TB2> INFO: Test took 1201ms.
[11:51:05.420] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:51:05.727] <TB2> INFO: Expecting 2560 events.
[11:51:06.620] <TB2> INFO: 2560 events read in total (301ms).
[11:51:06.621] <TB2> INFO: Test took 1201ms.
[11:51:07.110] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 643 seconds
[11:51:07.110] <TB2> INFO: PH scale (per ROC): 53 54 59 57 58 50 59 50 65 48 48 68 62 58 46 65
[11:51:07.110] <TB2> INFO: PH offset (per ROC): 120 121 123 104 129 118 126 103 131 112 109 123 122 130 107 112
[11:51:07.120] <TB2> INFO: Decoding statistics:
[11:51:07.120] <TB2> INFO: General information:
[11:51:07.120] <TB2> INFO: 16bit words read: 127890
[11:51:07.120] <TB2> INFO: valid events total: 20480
[11:51:07.120] <TB2> INFO: empty events: 17975
[11:51:07.120] <TB2> INFO: valid events with pixels: 2505
[11:51:07.120] <TB2> INFO: valid pixel hits: 2505
[11:51:07.120] <TB2> INFO: Event errors: 0
[11:51:07.120] <TB2> INFO: start marker: 0
[11:51:07.120] <TB2> INFO: stop marker: 0
[11:51:07.120] <TB2> INFO: overflow: 0
[11:51:07.120] <TB2> INFO: invalid 5bit words: 0
[11:51:07.120] <TB2> INFO: invalid XOR eye diagram: 0
[11:51:07.120] <TB2> INFO: frame (failed synchr.): 0
[11:51:07.120] <TB2> INFO: idle data (no TBM trl): 0
[11:51:07.120] <TB2> INFO: no data (only TBM hdr): 0
[11:51:07.120] <TB2> INFO: TBM errors: 0
[11:51:07.120] <TB2> INFO: flawed TBM headers: 0
[11:51:07.120] <TB2> INFO: flawed TBM trailers: 0
[11:51:07.121] <TB2> INFO: event ID mismatches: 0
[11:51:07.121] <TB2> INFO: ROC errors: 0
[11:51:07.121] <TB2> INFO: missing ROC header(s): 0
[11:51:07.121] <TB2> INFO: misplaced readback start: 0
[11:51:07.121] <TB2> INFO: Pixel decoding errors: 0
[11:51:07.121] <TB2> INFO: pixel data incomplete: 0
[11:51:07.121] <TB2> INFO: pixel address: 0
[11:51:07.121] <TB2> INFO: pulse height fill bit: 0
[11:51:07.121] <TB2> INFO: buffer corruption: 0
[11:51:07.285] <TB2> INFO: ######################################################################
[11:51:07.285] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[11:51:07.285] <TB2> INFO: ######################################################################
[11:51:07.299] <TB2> INFO: scanning low vcal = 10
[11:51:07.550] <TB2> INFO: Expecting 41600 events.
[11:51:11.114] <TB2> INFO: 41600 events read in total (2972ms).
[11:51:11.114] <TB2> INFO: Test took 3815ms.
[11:51:11.117] <TB2> INFO: scanning low vcal = 20
[11:51:11.413] <TB2> INFO: Expecting 41600 events.
[11:51:14.987] <TB2> INFO: 41600 events read in total (2982ms).
[11:51:14.988] <TB2> INFO: Test took 3871ms.
[11:51:14.990] <TB2> INFO: scanning low vcal = 30
[11:51:15.282] <TB2> INFO: Expecting 41600 events.
[11:51:18.952] <TB2> INFO: 41600 events read in total (3078ms).
[11:51:18.953] <TB2> INFO: Test took 3963ms.
[11:51:18.956] <TB2> INFO: scanning low vcal = 40
[11:51:19.233] <TB2> INFO: Expecting 41600 events.
[11:51:23.176] <TB2> INFO: 41600 events read in total (3351ms).
[11:51:23.177] <TB2> INFO: Test took 4220ms.
[11:51:23.181] <TB2> INFO: scanning low vcal = 50
[11:51:23.458] <TB2> INFO: Expecting 41600 events.
[11:51:27.495] <TB2> INFO: 41600 events read in total (3446ms).
[11:51:27.496] <TB2> INFO: Test took 4314ms.
[11:51:27.500] <TB2> INFO: scanning low vcal = 60
[11:51:27.776] <TB2> INFO: Expecting 41600 events.
[11:51:31.792] <TB2> INFO: 41600 events read in total (3424ms).
[11:51:31.793] <TB2> INFO: Test took 4293ms.
[11:51:31.797] <TB2> INFO: scanning low vcal = 70
[11:51:32.073] <TB2> INFO: Expecting 41600 events.
[11:51:36.054] <TB2> INFO: 41600 events read in total (3389ms).
[11:51:36.055] <TB2> INFO: Test took 4258ms.
[11:51:36.058] <TB2> INFO: scanning low vcal = 80
[11:51:36.334] <TB2> INFO: Expecting 41600 events.
[11:51:40.291] <TB2> INFO: 41600 events read in total (3365ms).
[11:51:40.292] <TB2> INFO: Test took 4234ms.
[11:51:40.295] <TB2> INFO: scanning low vcal = 90
[11:51:40.571] <TB2> INFO: Expecting 41600 events.
[11:51:44.539] <TB2> INFO: 41600 events read in total (3376ms).
[11:51:44.540] <TB2> INFO: Test took 4245ms.
[11:51:44.545] <TB2> INFO: scanning low vcal = 100
[11:51:44.821] <TB2> INFO: Expecting 41600 events.
[11:51:48.784] <TB2> INFO: 41600 events read in total (3372ms).
[11:51:48.785] <TB2> INFO: Test took 4240ms.
[11:51:48.788] <TB2> INFO: scanning low vcal = 110
[11:51:49.064] <TB2> INFO: Expecting 41600 events.
[11:51:53.011] <TB2> INFO: 41600 events read in total (3355ms).
[11:51:53.012] <TB2> INFO: Test took 4224ms.
[11:51:53.016] <TB2> INFO: scanning low vcal = 120
[11:51:53.341] <TB2> INFO: Expecting 41600 events.
[11:51:57.302] <TB2> INFO: 41600 events read in total (3369ms).
[11:51:57.303] <TB2> INFO: Test took 4287ms.
[11:51:57.307] <TB2> INFO: scanning low vcal = 130
[11:51:57.583] <TB2> INFO: Expecting 41600 events.
[11:52:01.540] <TB2> INFO: 41600 events read in total (3366ms).
[11:52:01.540] <TB2> INFO: Test took 4233ms.
[11:52:01.544] <TB2> INFO: scanning low vcal = 140
[11:52:01.820] <TB2> INFO: Expecting 41600 events.
[11:52:05.760] <TB2> INFO: 41600 events read in total (3348ms).
[11:52:05.762] <TB2> INFO: Test took 4218ms.
[11:52:05.765] <TB2> INFO: scanning low vcal = 150
[11:52:06.041] <TB2> INFO: Expecting 41600 events.
[11:52:10.017] <TB2> INFO: 41600 events read in total (3384ms).
[11:52:10.018] <TB2> INFO: Test took 4253ms.
[11:52:10.023] <TB2> INFO: scanning low vcal = 160
[11:52:10.298] <TB2> INFO: Expecting 41600 events.
[11:52:14.252] <TB2> INFO: 41600 events read in total (3363ms).
[11:52:14.253] <TB2> INFO: Test took 4230ms.
[11:52:14.256] <TB2> INFO: scanning low vcal = 170
[11:52:14.580] <TB2> INFO: Expecting 41600 events.
[11:52:18.580] <TB2> INFO: 41600 events read in total (3408ms).
[11:52:18.580] <TB2> INFO: Test took 4325ms.
[11:52:18.586] <TB2> INFO: scanning low vcal = 180
[11:52:18.861] <TB2> INFO: Expecting 41600 events.
[11:52:22.896] <TB2> INFO: 41600 events read in total (3444ms).
[11:52:22.896] <TB2> INFO: Test took 4310ms.
[11:52:22.899] <TB2> INFO: scanning low vcal = 190
[11:52:23.202] <TB2> INFO: Expecting 41600 events.
[11:52:27.235] <TB2> INFO: 41600 events read in total (3441ms).
[11:52:27.236] <TB2> INFO: Test took 4337ms.
[11:52:27.240] <TB2> INFO: scanning low vcal = 200
[11:52:27.516] <TB2> INFO: Expecting 41600 events.
[11:52:31.534] <TB2> INFO: 41600 events read in total (3426ms).
[11:52:31.535] <TB2> INFO: Test took 4295ms.
[11:52:31.538] <TB2> INFO: scanning low vcal = 210
[11:52:31.814] <TB2> INFO: Expecting 41600 events.
[11:52:35.834] <TB2> INFO: 41600 events read in total (3428ms).
[11:52:35.835] <TB2> INFO: Test took 4297ms.
[11:52:35.840] <TB2> INFO: scanning low vcal = 220
[11:52:36.126] <TB2> INFO: Expecting 41600 events.
[11:52:40.132] <TB2> INFO: 41600 events read in total (3415ms).
[11:52:40.133] <TB2> INFO: Test took 4293ms.
[11:52:40.138] <TB2> INFO: scanning low vcal = 230
[11:52:40.429] <TB2> INFO: Expecting 41600 events.
[11:52:44.498] <TB2> INFO: 41600 events read in total (3477ms).
[11:52:44.500] <TB2> INFO: Test took 4362ms.
[11:52:44.503] <TB2> INFO: scanning low vcal = 240
[11:52:44.796] <TB2> INFO: Expecting 41600 events.
[11:52:48.876] <TB2> INFO: 41600 events read in total (3489ms).
[11:52:48.877] <TB2> INFO: Test took 4374ms.
[11:52:48.881] <TB2> INFO: scanning low vcal = 250
[11:52:49.157] <TB2> INFO: Expecting 41600 events.
[11:52:53.200] <TB2> INFO: 41600 events read in total (3452ms).
[11:52:53.201] <TB2> INFO: Test took 4319ms.
[11:52:53.206] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[11:52:53.481] <TB2> INFO: Expecting 41600 events.
[11:52:57.560] <TB2> INFO: 41600 events read in total (3487ms).
[11:52:57.561] <TB2> INFO: Test took 4355ms.
[11:52:57.564] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[11:52:57.840] <TB2> INFO: Expecting 41600 events.
[11:53:01.900] <TB2> INFO: 41600 events read in total (3468ms).
[11:53:01.901] <TB2> INFO: Test took 4337ms.
[11:53:01.904] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[11:53:02.181] <TB2> INFO: Expecting 41600 events.
[11:53:06.178] <TB2> INFO: 41600 events read in total (3406ms).
[11:53:06.179] <TB2> INFO: Test took 4275ms.
[11:53:06.183] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[11:53:06.459] <TB2> INFO: Expecting 41600 events.
[11:53:10.421] <TB2> INFO: 41600 events read in total (3370ms).
[11:53:10.422] <TB2> INFO: Test took 4239ms.
[11:53:10.425] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[11:53:10.702] <TB2> INFO: Expecting 41600 events.
[11:53:14.666] <TB2> INFO: 41600 events read in total (3372ms).
[11:53:14.667] <TB2> INFO: Test took 4242ms.
[11:53:15.053] <TB2> INFO: PixTestGainPedestal::measure() done
[11:53:47.508] <TB2> INFO: PixTestGainPedestal::fit() done
[11:53:47.508] <TB2> INFO: non-linearity mean: 0.972 0.978 0.975 0.946 0.979 0.978 0.978 0.928 0.983 0.931 0.962 0.985 0.979 0.982 0.929 0.982
[11:53:47.508] <TB2> INFO: non-linearity RMS: 0.005 0.005 0.005 0.039 0.008 0.006 0.006 0.070 0.004 0.087 0.023 0.004 0.004 0.003 0.064 0.003
[11:53:47.508] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[11:53:47.521] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[11:53:47.535] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[11:53:47.548] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[11:53:47.561] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[11:53:47.575] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[11:53:47.588] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[11:53:47.602] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[11:53:47.615] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[11:53:47.629] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[11:53:47.642] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[11:53:47.655] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[11:53:47.669] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[11:53:47.682] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[11:53:47.695] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[11:53:47.709] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[11:53:47.722] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 160 seconds
[11:53:47.722] <TB2> INFO: Decoding statistics:
[11:53:47.722] <TB2> INFO: General information:
[11:53:47.722] <TB2> INFO: 16bit words read: 3327872
[11:53:47.722] <TB2> INFO: valid events total: 332800
[11:53:47.722] <TB2> INFO: empty events: 0
[11:53:47.722] <TB2> INFO: valid events with pixels: 332800
[11:53:47.722] <TB2> INFO: valid pixel hits: 665536
[11:53:47.722] <TB2> INFO: Event errors: 0
[11:53:47.722] <TB2> INFO: start marker: 0
[11:53:47.722] <TB2> INFO: stop marker: 0
[11:53:47.722] <TB2> INFO: overflow: 0
[11:53:47.722] <TB2> INFO: invalid 5bit words: 0
[11:53:47.722] <TB2> INFO: invalid XOR eye diagram: 0
[11:53:47.722] <TB2> INFO: frame (failed synchr.): 0
[11:53:47.722] <TB2> INFO: idle data (no TBM trl): 0
[11:53:47.722] <TB2> INFO: no data (only TBM hdr): 0
[11:53:47.722] <TB2> INFO: TBM errors: 0
[11:53:47.722] <TB2> INFO: flawed TBM headers: 0
[11:53:47.722] <TB2> INFO: flawed TBM trailers: 0
[11:53:47.722] <TB2> INFO: event ID mismatches: 0
[11:53:47.722] <TB2> INFO: ROC errors: 0
[11:53:47.722] <TB2> INFO: missing ROC header(s): 0
[11:53:47.722] <TB2> INFO: misplaced readback start: 0
[11:53:47.722] <TB2> INFO: Pixel decoding errors: 0
[11:53:47.722] <TB2> INFO: pixel data incomplete: 0
[11:53:47.722] <TB2> INFO: pixel address: 0
[11:53:47.722] <TB2> INFO: pulse height fill bit: 0
[11:53:47.722] <TB2> INFO: buffer corruption: 0
[11:53:47.740] <TB2> INFO: Decoding statistics:
[11:53:47.740] <TB2> INFO: General information:
[11:53:47.740] <TB2> INFO: 16bit words read: 3457298
[11:53:47.740] <TB2> INFO: valid events total: 353536
[11:53:47.740] <TB2> INFO: empty events: 18231
[11:53:47.740] <TB2> INFO: valid events with pixels: 335305
[11:53:47.740] <TB2> INFO: valid pixel hits: 668041
[11:53:47.740] <TB2> INFO: Event errors: 0
[11:53:47.740] <TB2> INFO: start marker: 0
[11:53:47.740] <TB2> INFO: stop marker: 0
[11:53:47.740] <TB2> INFO: overflow: 0
[11:53:47.740] <TB2> INFO: invalid 5bit words: 0
[11:53:47.740] <TB2> INFO: invalid XOR eye diagram: 0
[11:53:47.740] <TB2> INFO: frame (failed synchr.): 0
[11:53:47.740] <TB2> INFO: idle data (no TBM trl): 0
[11:53:47.740] <TB2> INFO: no data (only TBM hdr): 0
[11:53:47.740] <TB2> INFO: TBM errors: 0
[11:53:47.740] <TB2> INFO: flawed TBM headers: 0
[11:53:47.740] <TB2> INFO: flawed TBM trailers: 0
[11:53:47.741] <TB2> INFO: event ID mismatches: 0
[11:53:47.741] <TB2> INFO: ROC errors: 0
[11:53:47.741] <TB2> INFO: missing ROC header(s): 0
[11:53:47.741] <TB2> INFO: misplaced readback start: 0
[11:53:47.741] <TB2> INFO: Pixel decoding errors: 0
[11:53:47.741] <TB2> INFO: pixel data incomplete: 0
[11:53:47.741] <TB2> INFO: pixel address: 0
[11:53:47.741] <TB2> INFO: pulse height fill bit: 0
[11:53:47.741] <TB2> INFO: buffer corruption: 0
[11:53:47.741] <TB2> INFO: enter test to run
[11:53:47.741] <TB2> INFO: test: exit no parameter change
[11:53:47.868] <TB2> QUIET: Connection to board 149 closed.
[11:53:47.869] <TB2> INFO: pXar: this is the end, my friend