[12:02:58.584] <TB2> INFO: *** Welcome to pxar ***
[12:02:58.584] <TB2> INFO: *** Today: 2016/11/02
[12:02:58.592] <TB2> INFO: *** Version: c8ba-dirty
[12:02:58.592] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:02:58.593] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:02:58.593] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//defaultMaskFile.dat
[12:02:58.593] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters_C15.dat
[12:02:58.655] <TB2> INFO: clk: 4
[12:02:58.655] <TB2> INFO: ctr: 4
[12:02:58.655] <TB2> INFO: sda: 19
[12:02:58.655] <TB2> INFO: tin: 9
[12:02:58.655] <TB2> INFO: level: 15
[12:02:58.655] <TB2> INFO: triggerdelay: 0
[12:02:58.655] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[12:02:58.655] <TB2> INFO: Log level: INFO
[12:02:58.664] <TB2> INFO: Found DTB DTB_WWXUD2
[12:02:58.671] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[12:02:58.673] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[12:02:58.675] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[12:03:00.171] <TB2> INFO: DUT info:
[12:03:00.171] <TB2> INFO: The DUT currently contains the following objects:
[12:03:00.171] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[12:03:00.171] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:03:00.171] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:03:00.171] <TB2> INFO: TBM Core alpha (2): 7 registers set
[12:03:00.171] <TB2> INFO: TBM Core beta (3): 7 registers set
[12:03:00.171] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[12:03:00.171] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.171] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.171] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.171] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.171] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.171] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.171] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.171] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.171] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.171] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.171] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.171] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.172] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.172] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.172] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.172] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:03:00.573] <TB2> INFO: enter 'restricted' command line mode
[12:03:00.573] <TB2> INFO: enter test to run
[12:03:00.573] <TB2> INFO: test: pretest no parameter change
[12:03:00.573] <TB2> INFO: running: pretest
[12:03:00.580] <TB2> INFO: ######################################################################
[12:03:00.580] <TB2> INFO: PixTestPretest::doTest()
[12:03:00.580] <TB2> INFO: ######################################################################
[12:03:00.581] <TB2> INFO: ----------------------------------------------------------------------
[12:03:00.581] <TB2> INFO: PixTestPretest::programROC()
[12:03:00.581] <TB2> INFO: ----------------------------------------------------------------------
[12:03:18.596] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:03:18.596] <TB2> INFO: IA differences per ROC: 19.3 17.7 18.5 18.5 18.5 20.1 19.3 18.5 20.1 20.9 17.7 18.5 19.3 18.5 19.3 18.5
[12:03:18.663] <TB2> INFO: ----------------------------------------------------------------------
[12:03:18.663] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:03:18.663] <TB2> INFO: ----------------------------------------------------------------------
[12:03:26.868] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 390.7 mA = 24.4187 mA/ROC
[12:03:26.869] <TB2> INFO: i(loss) [mA/ROC]: 19.3 19.3 19.3 20.1 19.3 19.3 19.3 20.9 19.3 18.5 19.3 20.1 19.3 19.3 19.3 19.3
[12:03:26.901] <TB2> INFO: ----------------------------------------------------------------------
[12:03:26.901] <TB2> INFO: PixTestPretest::findTiming()
[12:03:26.901] <TB2> INFO: ----------------------------------------------------------------------
[12:03:26.901] <TB2> INFO: PixTestCmd::init()

[12:03:59.488] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:03:59.488] <TB2> INFO: (success/tries = 100/100), width = 4
[12:04:00.992] <TB2> INFO: ----------------------------------------------------------------------
[12:04:00.992] <TB2> INFO: PixTestPretest::findWorkingPixel()
[12:04:00.992] <TB2> INFO: ----------------------------------------------------------------------
[12:04:01.085] <TB2> INFO: Expecting 231680 events.
[12:04:10.954] <TB2> INFO: 231680 events read in total (9277ms).
[12:04:10.964] <TB2> INFO: Test took 9969ms.
[12:04:11.204] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:04:11.237] <TB2> INFO: ----------------------------------------------------------------------
[12:04:11.237] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[12:04:11.237] <TB2> INFO: ----------------------------------------------------------------------
[12:04:11.329] <TB2> INFO: Expecting 231680 events.
[12:04:21.564] <TB2> INFO: 231680 events read in total (9643ms).
[12:04:21.584] <TB2> INFO: Test took 10343ms.
[12:04:21.847] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[12:04:21.847] <TB2> INFO: CalDel: 87 84 93 79 80 83 100 88 82 81 67 82 91 85 82 71
[12:04:21.847] <TB2> INFO: VthrComp: 51 51 51 53 51 56 51 51 52 51 52 54 51 51 51 52
[12:04:21.850] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C0.dat
[12:04:21.850] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C1.dat
[12:04:21.851] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C2.dat
[12:04:21.851] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C3.dat
[12:04:21.851] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C4.dat
[12:04:21.851] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C5.dat
[12:04:21.851] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C6.dat
[12:04:21.851] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C7.dat
[12:04:21.851] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C8.dat
[12:04:21.851] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C9.dat
[12:04:21.851] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C10.dat
[12:04:21.852] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C11.dat
[12:04:21.852] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C12.dat
[12:04:21.852] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C13.dat
[12:04:21.852] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C14.dat
[12:04:21.852] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:04:21.852] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[12:04:21.852] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[12:04:21.852] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[12:04:21.852] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:04:21.852] <TB2> INFO: PixTestPretest::doTest() done, duration: 81 seconds
[12:04:21.904] <TB2> INFO: enter test to run
[12:04:21.904] <TB2> INFO: test: fulltest no parameter change
[12:04:21.904] <TB2> INFO: running: fulltest
[12:04:21.904] <TB2> INFO: ######################################################################
[12:04:21.904] <TB2> INFO: PixTestFullTest::doTest()
[12:04:21.904] <TB2> INFO: ######################################################################
[12:04:21.906] <TB2> INFO: ######################################################################
[12:04:21.906] <TB2> INFO: PixTestAlive::doTest()
[12:04:21.906] <TB2> INFO: ######################################################################
[12:04:21.907] <TB2> INFO: ----------------------------------------------------------------------
[12:04:21.907] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:04:21.907] <TB2> INFO: ----------------------------------------------------------------------
[12:04:22.148] <TB2> INFO: Expecting 41600 events.
[12:04:25.663] <TB2> INFO: 41600 events read in total (2923ms).
[12:04:25.664] <TB2> INFO: Test took 3755ms.
[12:04:25.899] <TB2> INFO: PixTestAlive::aliveTest() done
[12:04:25.899] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:04:25.900] <TB2> INFO: ----------------------------------------------------------------------
[12:04:25.900] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:04:25.900] <TB2> INFO: ----------------------------------------------------------------------
[12:04:26.146] <TB2> INFO: Expecting 41600 events.
[12:04:29.122] <TB2> INFO: 41600 events read in total (2384ms).
[12:04:29.122] <TB2> INFO: Test took 3219ms.
[12:04:29.123] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:04:29.360] <TB2> INFO: PixTestAlive::maskTest() done
[12:04:29.360] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:04:29.361] <TB2> INFO: ----------------------------------------------------------------------
[12:04:29.361] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:04:29.361] <TB2> INFO: ----------------------------------------------------------------------
[12:04:29.607] <TB2> INFO: Expecting 41600 events.
[12:04:33.179] <TB2> INFO: 41600 events read in total (2981ms).
[12:04:33.180] <TB2> INFO: Test took 3816ms.
[12:04:33.410] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[12:04:33.410] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:04:33.410] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:04:33.410] <TB2> INFO: Decoding statistics:
[12:04:33.410] <TB2> INFO: General information:
[12:04:33.410] <TB2> INFO: 16bit words read: 0
[12:04:33.410] <TB2> INFO: valid events total: 0
[12:04:33.410] <TB2> INFO: empty events: 0
[12:04:33.410] <TB2> INFO: valid events with pixels: 0
[12:04:33.410] <TB2> INFO: valid pixel hits: 0
[12:04:33.410] <TB2> INFO: Event errors: 0
[12:04:33.410] <TB2> INFO: start marker: 0
[12:04:33.410] <TB2> INFO: stop marker: 0
[12:04:33.410] <TB2> INFO: overflow: 0
[12:04:33.410] <TB2> INFO: invalid 5bit words: 0
[12:04:33.410] <TB2> INFO: invalid XOR eye diagram: 0
[12:04:33.410] <TB2> INFO: frame (failed synchr.): 0
[12:04:33.410] <TB2> INFO: idle data (no TBM trl): 0
[12:04:33.410] <TB2> INFO: no data (only TBM hdr): 0
[12:04:33.410] <TB2> INFO: TBM errors: 0
[12:04:33.411] <TB2> INFO: flawed TBM headers: 0
[12:04:33.411] <TB2> INFO: flawed TBM trailers: 0
[12:04:33.411] <TB2> INFO: event ID mismatches: 0
[12:04:33.411] <TB2> INFO: ROC errors: 0
[12:04:33.411] <TB2> INFO: missing ROC header(s): 0
[12:04:33.411] <TB2> INFO: misplaced readback start: 0
[12:04:33.411] <TB2> INFO: Pixel decoding errors: 0
[12:04:33.411] <TB2> INFO: pixel data incomplete: 0
[12:04:33.411] <TB2> INFO: pixel address: 0
[12:04:33.411] <TB2> INFO: pulse height fill bit: 0
[12:04:33.411] <TB2> INFO: buffer corruption: 0
[12:04:33.416] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:04:33.416] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[12:04:33.416] <TB2> INFO: ######################################################################
[12:04:33.416] <TB2> INFO: PixTestReadback::doTest()
[12:04:33.416] <TB2> INFO: ######################################################################
[12:04:33.416] <TB2> INFO: ----------------------------------------------------------------------
[12:04:33.416] <TB2> INFO: PixTestReadback::CalibrateVd()
[12:04:33.416] <TB2> INFO: ----------------------------------------------------------------------
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:04:43.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:04:43.411] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:04:43.411] <TB2> INFO: ----------------------------------------------------------------------
[12:04:43.411] <TB2> INFO: PixTestReadback::CalibrateVa()
[12:04:43.411] <TB2> INFO: ----------------------------------------------------------------------
[12:04:53.343] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:04:53.343] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:04:53.344] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:04:53.344] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:04:53.344] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:04:53.344] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:04:53.344] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:04:53.344] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:04:53.344] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:04:53.344] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:04:53.344] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:04:53.344] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:04:53.344] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:04:53.345] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:04:53.345] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:04:53.345] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:04:53.373] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:04:53.373] <TB2> INFO: ----------------------------------------------------------------------
[12:04:53.373] <TB2> INFO: PixTestReadback::readbackVbg()
[12:04:53.373] <TB2> INFO: ----------------------------------------------------------------------
[12:05:01.043] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:05:01.043] <TB2> INFO: ----------------------------------------------------------------------
[12:05:01.043] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[12:05:01.043] <TB2> INFO: ----------------------------------------------------------------------
[12:05:01.044] <TB2> INFO: Vbg will be calibrated using Vd calibration
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 160.2calibrated Vbg = 1.19816 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 151.2calibrated Vbg = 1.19675 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 156.9calibrated Vbg = 1.197 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 155.6calibrated Vbg = 1.1935 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 148.5calibrated Vbg = 1.18893 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 150calibrated Vbg = 1.19686 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 155.2calibrated Vbg = 1.20433 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 158calibrated Vbg = 1.19729 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 157calibrated Vbg = 1.19712 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 149.7calibrated Vbg = 1.19755 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 152.6calibrated Vbg = 1.18564 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 151.8calibrated Vbg = 1.18508 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 154calibrated Vbg = 1.19365 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 147.2calibrated Vbg = 1.19727 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 147.8calibrated Vbg = 1.19988 :::*/*/*/*/
[12:05:01.044] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 148.2calibrated Vbg = 1.19878 :::*/*/*/*/
[12:05:01.047] <TB2> INFO: ----------------------------------------------------------------------
[12:05:01.047] <TB2> INFO: PixTestReadback::CalibrateIa()
[12:05:01.047] <TB2> INFO: ----------------------------------------------------------------------
[12:07:41.866] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:07:41.866] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:07:41.866] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:07:41.866] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:07:41.866] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:07:41.866] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:07:41.866] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:07:41.866] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:07:41.866] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:07:41.866] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:07:41.866] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:07:41.866] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:07:41.866] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:07:41.866] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:07:41.867] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:07:41.867] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:07:41.896] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:07:41.898] <TB2> INFO: PixTestReadback::doTest() done
[12:07:41.898] <TB2> INFO: Decoding statistics:
[12:07:41.898] <TB2> INFO: General information:
[12:07:41.898] <TB2> INFO: 16bit words read: 1536
[12:07:41.898] <TB2> INFO: valid events total: 256
[12:07:41.898] <TB2> INFO: empty events: 256
[12:07:41.898] <TB2> INFO: valid events with pixels: 0
[12:07:41.898] <TB2> INFO: valid pixel hits: 0
[12:07:41.898] <TB2> INFO: Event errors: 0
[12:07:41.898] <TB2> INFO: start marker: 0
[12:07:41.898] <TB2> INFO: stop marker: 0
[12:07:41.898] <TB2> INFO: overflow: 0
[12:07:41.898] <TB2> INFO: invalid 5bit words: 0
[12:07:41.898] <TB2> INFO: invalid XOR eye diagram: 0
[12:07:41.898] <TB2> INFO: frame (failed synchr.): 0
[12:07:41.898] <TB2> INFO: idle data (no TBM trl): 0
[12:07:41.898] <TB2> INFO: no data (only TBM hdr): 0
[12:07:41.898] <TB2> INFO: TBM errors: 0
[12:07:41.898] <TB2> INFO: flawed TBM headers: 0
[12:07:41.898] <TB2> INFO: flawed TBM trailers: 0
[12:07:41.898] <TB2> INFO: event ID mismatches: 0
[12:07:41.898] <TB2> INFO: ROC errors: 0
[12:07:41.898] <TB2> INFO: missing ROC header(s): 0
[12:07:41.898] <TB2> INFO: misplaced readback start: 0
[12:07:41.898] <TB2> INFO: Pixel decoding errors: 0
[12:07:41.898] <TB2> INFO: pixel data incomplete: 0
[12:07:41.898] <TB2> INFO: pixel address: 0
[12:07:41.898] <TB2> INFO: pulse height fill bit: 0
[12:07:41.898] <TB2> INFO: buffer corruption: 0
[12:07:41.954] <TB2> INFO: ######################################################################
[12:07:41.954] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:07:41.954] <TB2> INFO: ######################################################################
[12:07:41.956] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:07:41.979] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:07:41.979] <TB2> INFO: run 1 of 1
[12:07:42.216] <TB2> INFO: Expecting 3120000 events.
[12:08:13.399] <TB2> INFO: 671760 events read in total (30591ms).











[12:08:43.528] <TB2> INFO: 1334595 events read in total (60720ms).











[12:09:13.463] <TB2> INFO: 1990240 events read in total (90655ms).











[12:09:43.292] <TB2> INFO: 2644375 events read in total (120484ms).











[12:10:04.982] <TB2> INFO: 3120000 events read in total (142174ms).
[12:10:05.071] <TB2> INFO: Test took 143091ms.
[12:10:31.595] <TB2> INFO: PixTestBBMap::doTest() done with 4 decoding errors: , duration: 169 seconds
[12:10:31.595] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
[12:10:31.595] <TB2> INFO: separation cut (per ROC): 106 107 109 115 107 112 105 108 114 111 110 130 104 112 107 115
[12:10:31.595] <TB2> INFO: Decoding statistics:
[12:10:31.595] <TB2> INFO: General information:
[12:10:31.595] <TB2> INFO: 16bit words read: 0
[12:10:31.595] <TB2> INFO: valid events total: 0
[12:10:31.595] <TB2> INFO: empty events: 0
[12:10:31.595] <TB2> INFO: valid events with pixels: 0
[12:10:31.595] <TB2> INFO: valid pixel hits: 0
[12:10:31.595] <TB2> INFO: Event errors: 0
[12:10:31.595] <TB2> INFO: start marker: 0
[12:10:31.595] <TB2> INFO: stop marker: 0
[12:10:31.595] <TB2> INFO: overflow: 0
[12:10:31.595] <TB2> INFO: invalid 5bit words: 0
[12:10:31.595] <TB2> INFO: invalid XOR eye diagram: 0
[12:10:31.595] <TB2> INFO: frame (failed synchr.): 0
[12:10:31.595] <TB2> INFO: idle data (no TBM trl): 0
[12:10:31.595] <TB2> INFO: no data (only TBM hdr): 0
[12:10:31.595] <TB2> INFO: TBM errors: 0
[12:10:31.595] <TB2> INFO: flawed TBM headers: 0
[12:10:31.595] <TB2> INFO: flawed TBM trailers: 0
[12:10:31.595] <TB2> INFO: event ID mismatches: 0
[12:10:31.595] <TB2> INFO: ROC errors: 0
[12:10:31.595] <TB2> INFO: missing ROC header(s): 0
[12:10:31.595] <TB2> INFO: misplaced readback start: 0
[12:10:31.595] <TB2> INFO: Pixel decoding errors: 0
[12:10:31.595] <TB2> INFO: pixel data incomplete: 0
[12:10:31.595] <TB2> INFO: pixel address: 0
[12:10:31.595] <TB2> INFO: pulse height fill bit: 0
[12:10:31.595] <TB2> INFO: buffer corruption: 0
[12:10:31.633] <TB2> INFO: ######################################################################
[12:10:31.633] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:10:31.633] <TB2> INFO: ######################################################################
[12:10:31.633] <TB2> INFO: ----------------------------------------------------------------------
[12:10:31.633] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:10:31.633] <TB2> INFO: ----------------------------------------------------------------------
[12:10:31.633] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:10:31.647] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[12:10:31.647] <TB2> INFO: run 1 of 1
[12:10:31.885] <TB2> INFO: Expecting 36608000 events.
[12:10:55.720] <TB2> INFO: 696550 events read in total (23243ms).
[12:11:18.696] <TB2> INFO: 1378950 events read in total (46219ms).
[12:11:41.711] <TB2> INFO: 2057800 events read in total (69234ms).
[12:12:04.769] <TB2> INFO: 2736800 events read in total (92292ms).
[12:12:27.971] <TB2> INFO: 3417600 events read in total (115494ms).
[12:12:51.196] <TB2> INFO: 4096800 events read in total (138719ms).
[12:13:14.185] <TB2> INFO: 4773400 events read in total (161708ms).
[12:13:37.125] <TB2> INFO: 5451100 events read in total (184648ms).
[12:14:00.220] <TB2> INFO: 6127950 events read in total (207743ms).
[12:14:24.227] <TB2> INFO: 6805750 events read in total (231750ms).
[12:14:47.653] <TB2> INFO: 7482200 events read in total (255176ms).
[12:15:11.072] <TB2> INFO: 8159150 events read in total (278595ms).
[12:15:34.196] <TB2> INFO: 8836800 events read in total (301719ms).
[12:15:57.495] <TB2> INFO: 9513200 events read in total (325018ms).
[12:16:20.679] <TB2> INFO: 10188600 events read in total (348202ms).
[12:16:43.566] <TB2> INFO: 10864100 events read in total (371089ms).
[12:17:06.520] <TB2> INFO: 11540250 events read in total (394043ms).
[12:17:29.148] <TB2> INFO: 12212600 events read in total (416671ms).
[12:17:51.800] <TB2> INFO: 12888950 events read in total (439323ms).
[12:18:14.676] <TB2> INFO: 13565300 events read in total (462199ms).
[12:18:37.493] <TB2> INFO: 14242700 events read in total (485016ms).
[12:19:00.265] <TB2> INFO: 14914200 events read in total (507788ms).
[12:19:23.899] <TB2> INFO: 15587150 events read in total (531422ms).
[12:19:47.340] <TB2> INFO: 16259150 events read in total (554863ms).
[12:20:10.961] <TB2> INFO: 16932700 events read in total (578484ms).
[12:20:33.943] <TB2> INFO: 17604250 events read in total (601466ms).
[12:20:57.009] <TB2> INFO: 18275250 events read in total (624532ms).
[12:21:19.609] <TB2> INFO: 18944650 events read in total (647132ms).
[12:21:42.489] <TB2> INFO: 19615150 events read in total (670012ms).
[12:22:05.089] <TB2> INFO: 20282900 events read in total (692612ms).
[12:22:27.976] <TB2> INFO: 20952950 events read in total (715499ms).
[12:22:51.122] <TB2> INFO: 21623750 events read in total (738645ms).
[12:23:14.165] <TB2> INFO: 22295300 events read in total (761689ms).
[12:23:36.835] <TB2> INFO: 22962950 events read in total (784358ms).
[12:23:59.505] <TB2> INFO: 23627850 events read in total (807028ms).
[12:24:22.332] <TB2> INFO: 24295500 events read in total (829855ms).
[12:24:44.987] <TB2> INFO: 24963050 events read in total (852510ms).
[12:25:07.655] <TB2> INFO: 25630200 events read in total (875178ms).
[12:25:30.214] <TB2> INFO: 26297450 events read in total (897737ms).
[12:25:53.188] <TB2> INFO: 26966600 events read in total (920711ms).
[12:26:15.945] <TB2> INFO: 27633500 events read in total (943468ms).
[12:26:38.651] <TB2> INFO: 28300400 events read in total (966174ms).
[12:27:01.622] <TB2> INFO: 28967200 events read in total (989145ms).
[12:27:24.412] <TB2> INFO: 29634900 events read in total (1011935ms).
[12:27:47.089] <TB2> INFO: 30299950 events read in total (1034612ms).
[12:28:09.723] <TB2> INFO: 30966250 events read in total (1057246ms).
[12:28:32.294] <TB2> INFO: 31630500 events read in total (1079817ms).
[12:28:55.035] <TB2> INFO: 32298350 events read in total (1102558ms).
[12:29:18.143] <TB2> INFO: 32963550 events read in total (1125666ms).
[12:29:41.189] <TB2> INFO: 33632700 events read in total (1148712ms).
[12:30:03.944] <TB2> INFO: 34301100 events read in total (1171467ms).
[12:30:26.688] <TB2> INFO: 34968450 events read in total (1194211ms).
[12:30:49.598] <TB2> INFO: 35635150 events read in total (1217121ms).
[12:31:12.555] <TB2> INFO: 36310750 events read in total (1240078ms).
[12:31:22.807] <TB2> INFO: 36608000 events read in total (1250330ms).
[12:31:22.904] <TB2> INFO: Test took 1251257ms.
[12:31:23.215] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:24.825] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:26.764] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:28.750] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:30.862] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:32.889] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:34.992] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:37.250] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:39.580] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:41.431] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:42.003] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:44.562] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:46.126] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:47.679] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:49.191] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:50.786] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:31:52.832] <TB2> INFO: PixTestScurves::scurves() done
[12:31:52.832] <TB2> INFO: Vcal mean: 132.19 130.55 130.47 131.42 126.71 141.12 117.22 120.85 130.07 121.25 126.56 132.25 116.52 123.54 110.23 122.63
[12:31:52.832] <TB2> INFO: Vcal RMS: 7.63 6.51 8.67 6.38 5.81 6.34 5.70 5.62 6.65 5.76 6.34 5.69 5.02 5.13 5.54 6.12
[12:31:52.833] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1281 seconds
[12:31:52.833] <TB2> INFO: Decoding statistics:
[12:31:52.833] <TB2> INFO: General information:
[12:31:52.833] <TB2> INFO: 16bit words read: 0
[12:31:52.833] <TB2> INFO: valid events total: 0
[12:31:52.833] <TB2> INFO: empty events: 0
[12:31:52.833] <TB2> INFO: valid events with pixels: 0
[12:31:52.833] <TB2> INFO: valid pixel hits: 0
[12:31:52.833] <TB2> INFO: Event errors: 0
[12:31:52.833] <TB2> INFO: start marker: 0
[12:31:52.833] <TB2> INFO: stop marker: 0
[12:31:52.833] <TB2> INFO: overflow: 0
[12:31:52.833] <TB2> INFO: invalid 5bit words: 0
[12:31:52.833] <TB2> INFO: invalid XOR eye diagram: 0
[12:31:52.833] <TB2> INFO: frame (failed synchr.): 0
[12:31:52.833] <TB2> INFO: idle data (no TBM trl): 0
[12:31:52.833] <TB2> INFO: no data (only TBM hdr): 0
[12:31:52.833] <TB2> INFO: TBM errors: 0
[12:31:52.833] <TB2> INFO: flawed TBM headers: 0
[12:31:52.833] <TB2> INFO: flawed TBM trailers: 0
[12:31:52.833] <TB2> INFO: event ID mismatches: 0
[12:31:52.833] <TB2> INFO: ROC errors: 0
[12:31:52.833] <TB2> INFO: missing ROC header(s): 0
[12:31:52.833] <TB2> INFO: misplaced readback start: 0
[12:31:52.833] <TB2> INFO: Pixel decoding errors: 0
[12:31:52.833] <TB2> INFO: pixel data incomplete: 0
[12:31:52.833] <TB2> INFO: pixel address: 0
[12:31:52.833] <TB2> INFO: pulse height fill bit: 0
[12:31:52.833] <TB2> INFO: buffer corruption: 0
[12:31:52.903] <TB2> INFO: ######################################################################
[12:31:52.903] <TB2> INFO: PixTestTrim::doTest()
[12:31:52.903] <TB2> INFO: ######################################################################
[12:31:52.904] <TB2> INFO: ----------------------------------------------------------------------
[12:31:52.905] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:31:52.905] <TB2> INFO: ----------------------------------------------------------------------
[12:31:52.950] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:31:52.950] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:31:52.965] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:31:52.965] <TB2> INFO: run 1 of 1
[12:31:53.241] <TB2> INFO: Expecting 5025280 events.
[12:32:24.322] <TB2> INFO: 829448 events read in total (30482ms).
[12:32:54.217] <TB2> INFO: 1655456 events read in total (60377ms).
[12:33:24.168] <TB2> INFO: 2478712 events read in total (90328ms).
[12:33:54.152] <TB2> INFO: 3296616 events read in total (120312ms).
[12:34:24.201] <TB2> INFO: 4111088 events read in total (150361ms).
[12:34:54.173] <TB2> INFO: 4924440 events read in total (180333ms).
[12:34:58.261] <TB2> INFO: 5025280 events read in total (184421ms).
[12:34:58.316] <TB2> INFO: Test took 185352ms.
[12:35:14.121] <TB2> INFO: ROC 0 VthrComp = 131
[12:35:14.122] <TB2> INFO: ROC 1 VthrComp = 129
[12:35:14.122] <TB2> INFO: ROC 2 VthrComp = 129
[12:35:14.122] <TB2> INFO: ROC 3 VthrComp = 131
[12:35:14.122] <TB2> INFO: ROC 4 VthrComp = 128
[12:35:14.122] <TB2> INFO: ROC 5 VthrComp = 136
[12:35:14.122] <TB2> INFO: ROC 6 VthrComp = 121
[12:35:14.123] <TB2> INFO: ROC 7 VthrComp = 130
[12:35:14.123] <TB2> INFO: ROC 8 VthrComp = 133
[12:35:14.123] <TB2> INFO: ROC 9 VthrComp = 125
[12:35:14.125] <TB2> INFO: ROC 10 VthrComp = 131
[12:35:14.125] <TB2> INFO: ROC 11 VthrComp = 133
[12:35:14.125] <TB2> INFO: ROC 12 VthrComp = 122
[12:35:14.125] <TB2> INFO: ROC 13 VthrComp = 122
[12:35:14.126] <TB2> INFO: ROC 14 VthrComp = 116
[12:35:14.126] <TB2> INFO: ROC 15 VthrComp = 131
[12:35:14.453] <TB2> INFO: Expecting 41600 events.
[12:35:18.011] <TB2> INFO: 41600 events read in total (2967ms).
[12:35:18.012] <TB2> INFO: Test took 3883ms.
[12:35:18.023] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:35:18.023] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:35:18.036] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:35:18.036] <TB2> INFO: run 1 of 1
[12:35:18.314] <TB2> INFO: Expecting 5025280 events.
[12:35:45.612] <TB2> INFO: 590952 events read in total (26707ms).
[12:36:11.479] <TB2> INFO: 1180304 events read in total (52574ms).
[12:36:37.255] <TB2> INFO: 1769280 events read in total (78350ms).
[12:37:03.067] <TB2> INFO: 2357600 events read in total (104162ms).
[12:37:28.002] <TB2> INFO: 2943800 events read in total (130097ms).
[12:37:54.602] <TB2> INFO: 3528240 events read in total (155697ms).
[12:38:20.595] <TB2> INFO: 4112536 events read in total (181690ms).
[12:38:46.645] <TB2> INFO: 4696272 events read in total (207740ms).
[12:39:01.372] <TB2> INFO: 5025280 events read in total (222467ms).
[12:39:01.516] <TB2> INFO: Test took 223481ms.
[12:39:25.278] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 66.1298 for pixel 2/73 mean/min/max = 49.5175/32.8707/66.1644
[12:39:25.278] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 62.8745 for pixel 12/79 mean/min/max = 49.0404/35.1601/62.9207
[12:39:25.279] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 65.893 for pixel 3/74 mean/min/max = 48.5807/30.8835/66.2779
[12:39:25.279] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 65.6055 for pixel 2/72 mean/min/max = 51.3551/36.9523/65.7579
[12:39:25.280] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 58.1926 for pixel 9/12 mean/min/max = 45.5216/32.5109/58.5324
[12:39:25.280] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 73.2568 for pixel 15/79 mean/min/max = 56.6934/40.0455/73.3412
[12:39:25.281] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 58.9408 for pixel 51/9 mean/min/max = 46.0295/33.008/59.0509
[12:39:25.281] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 56.9127 for pixel 9/5 mean/min/max = 44.6822/32.4095/56.9549
[12:39:25.282] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 63.9784 for pixel 0/19 mean/min/max = 48.7189/33.435/64.0028
[12:39:25.282] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 58.1088 for pixel 35/78 mean/min/max = 45.5607/32.9239/58.1975
[12:39:25.283] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 60.4693 for pixel 16/2 mean/min/max = 46.6141/32.7275/60.5006
[12:39:25.283] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 67.8013 for pixel 17/13 mean/min/max = 53.1641/38.4248/67.9035
[12:39:25.284] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 57.4998 for pixel 17/5 mean/min/max = 45.8066/34.0081/57.6051
[12:39:25.284] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 59.6222 for pixel 7/62 mean/min/max = 47.3321/34.9317/59.7326
[12:39:25.285] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 58.4209 for pixel 10/77 mean/min/max = 45.245/31.9278/58.5623
[12:39:25.285] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 57.5999 for pixel 0/36 mean/min/max = 44.6014/31.2294/57.9735
[12:39:25.286] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:39:25.374] <TB2> INFO: Expecting 411648 events.
[12:39:34.835] <TB2> INFO: 411648 events read in total (8869ms).
[12:39:34.845] <TB2> INFO: Expecting 411648 events.
[12:39:44.098] <TB2> INFO: 411648 events read in total (8850ms).
[12:39:44.109] <TB2> INFO: Expecting 411648 events.
[12:39:53.362] <TB2> INFO: 411648 events read in total (8850ms).
[12:39:53.374] <TB2> INFO: Expecting 411648 events.
[12:40:02.786] <TB2> INFO: 411648 events read in total (9009ms).
[12:40:02.802] <TB2> INFO: Expecting 411648 events.
[12:40:12.135] <TB2> INFO: 411648 events read in total (8930ms).
[12:40:12.155] <TB2> INFO: Expecting 411648 events.
[12:40:21.567] <TB2> INFO: 411648 events read in total (9009ms).
[12:40:21.590] <TB2> INFO: Expecting 411648 events.
[12:40:30.979] <TB2> INFO: 411648 events read in total (8986ms).
[12:40:31.004] <TB2> INFO: Expecting 411648 events.
[12:40:40.427] <TB2> INFO: 411648 events read in total (9020ms).
[12:40:40.464] <TB2> INFO: Expecting 411648 events.
[12:40:49.820] <TB2> INFO: 411648 events read in total (8953ms).
[12:40:49.850] <TB2> INFO: Expecting 411648 events.
[12:40:59.156] <TB2> INFO: 411648 events read in total (8903ms).
[12:40:59.197] <TB2> INFO: Expecting 411648 events.
[12:41:08.585] <TB2> INFO: 411648 events read in total (8984ms).
[12:41:08.622] <TB2> INFO: Expecting 411648 events.
[12:41:18.082] <TB2> INFO: 411648 events read in total (9056ms).
[12:41:18.120] <TB2> INFO: Expecting 411648 events.
[12:41:27.513] <TB2> INFO: 411648 events read in total (8990ms).
[12:41:27.563] <TB2> INFO: Expecting 411648 events.
[12:41:36.878] <TB2> INFO: 411648 events read in total (8912ms).
[12:41:36.924] <TB2> INFO: Expecting 411648 events.
[12:41:46.300] <TB2> INFO: 411648 events read in total (8972ms).
[12:41:46.359] <TB2> INFO: Expecting 411648 events.
[12:41:55.811] <TB2> INFO: 411648 events read in total (9049ms).
[12:41:55.867] <TB2> INFO: Test took 150581ms.
[12:41:56.684] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:41:56.700] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:41:56.700] <TB2> INFO: run 1 of 1
[12:41:56.938] <TB2> INFO: Expecting 5025280 events.
[12:42:23.158] <TB2> INFO: 585752 events read in total (25629ms).
[12:42:49.015] <TB2> INFO: 1169896 events read in total (51486ms).
[12:43:15.347] <TB2> INFO: 1754144 events read in total (77819ms).
[12:43:41.149] <TB2> INFO: 2337856 events read in total (103620ms).
[12:44:07.363] <TB2> INFO: 2920640 events read in total (129835ms).
[12:44:33.552] <TB2> INFO: 3504288 events read in total (156023ms).
[12:44:59.987] <TB2> INFO: 4086368 events read in total (182458ms).
[12:45:26.394] <TB2> INFO: 4669744 events read in total (208865ms).
[12:45:42.495] <TB2> INFO: 5025280 events read in total (224966ms).
[12:45:42.696] <TB2> INFO: Test took 225998ms.
[12:46:08.214] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 11.739320 .. 147.013460
[12:46:08.484] <TB2> INFO: Expecting 208000 events.
[12:46:18.452] <TB2> INFO: 208000 events read in total (9376ms).
[12:46:18.454] <TB2> INFO: Test took 10238ms.
[12:46:18.504] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 157 (-1/-1) hits flags = 528 (plus default)
[12:46:18.517] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:46:18.517] <TB2> INFO: run 1 of 1
[12:46:18.795] <TB2> INFO: Expecting 5224960 events.
[12:46:44.948] <TB2> INFO: 583824 events read in total (25561ms).
[12:47:10.813] <TB2> INFO: 1167704 events read in total (51427ms).
[12:47:36.921] <TB2> INFO: 1751424 events read in total (77534ms).
[12:48:02.586] <TB2> INFO: 2335432 events read in total (103200ms).
[12:48:28.825] <TB2> INFO: 2919216 events read in total (129438ms).
[12:48:54.661] <TB2> INFO: 3502128 events read in total (155274ms).
[12:49:20.962] <TB2> INFO: 4084880 events read in total (181575ms).
[12:49:46.908] <TB2> INFO: 4666832 events read in total (207521ms).
[12:50:12.183] <TB2> INFO: 5224960 events read in total (232796ms).
[12:50:12.360] <TB2> INFO: Test took 233843ms.
[12:50:38.551] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 26.335059 .. 48.732292
[12:50:38.789] <TB2> INFO: Expecting 208000 events.
[12:50:48.497] <TB2> INFO: 208000 events read in total (9115ms).
[12:50:48.498] <TB2> INFO: Test took 9946ms.
[12:50:48.554] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 58 (-1/-1) hits flags = 528 (plus default)
[12:50:48.567] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:50:48.567] <TB2> INFO: run 1 of 1
[12:50:48.845] <TB2> INFO: Expecting 1431040 events.
[12:51:17.211] <TB2> INFO: 652872 events read in total (27774ms).
[12:51:44.692] <TB2> INFO: 1304200 events read in total (55255ms).
[12:51:50.320] <TB2> INFO: 1431040 events read in total (60883ms).
[12:51:50.366] <TB2> INFO: Test took 61799ms.
[12:52:05.529] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 26.950155 .. 49.652530
[12:52:05.785] <TB2> INFO: Expecting 208000 events.
[12:52:15.726] <TB2> INFO: 208000 events read in total (9348ms).
[12:52:15.727] <TB2> INFO: Test took 10196ms.
[12:52:15.776] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 59 (-1/-1) hits flags = 528 (plus default)
[12:52:15.789] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:52:15.789] <TB2> INFO: run 1 of 1
[12:52:16.071] <TB2> INFO: Expecting 1464320 events.
[12:52:44.361] <TB2> INFO: 649160 events read in total (27699ms).
[12:53:11.865] <TB2> INFO: 1298304 events read in total (55203ms).
[12:53:19.307] <TB2> INFO: 1464320 events read in total (62645ms).
[12:53:19.350] <TB2> INFO: Test took 63562ms.
[12:53:32.395] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 24.192428 .. 53.211295
[12:53:32.633] <TB2> INFO: Expecting 208000 events.
[12:53:42.590] <TB2> INFO: 208000 events read in total (9365ms).
[12:53:42.592] <TB2> INFO: Test took 10196ms.
[12:53:42.672] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 63 (-1/-1) hits flags = 528 (plus default)
[12:53:42.686] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:53:42.686] <TB2> INFO: run 1 of 1
[12:53:42.964] <TB2> INFO: Expecting 1664000 events.
[12:54:10.612] <TB2> INFO: 644808 events read in total (27057ms).
[12:54:37.709] <TB2> INFO: 1289928 events read in total (54154ms).
[12:54:53.785] <TB2> INFO: 1664000 events read in total (70230ms).
[12:54:53.822] <TB2> INFO: Test took 71137ms.
[12:55:08.977] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:55:08.977] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:55:08.990] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:55:08.990] <TB2> INFO: run 1 of 1
[12:55:09.229] <TB2> INFO: Expecting 1364480 events.
[12:55:38.105] <TB2> INFO: 667680 events read in total (28284ms).
[12:56:06.865] <TB2> INFO: 1335496 events read in total (57044ms).
[12:56:08.518] <TB2> INFO: 1364480 events read in total (58697ms).
[12:56:08.546] <TB2> INFO: Test took 59555ms.
[12:56:21.354] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C0.dat
[12:56:21.354] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C1.dat
[12:56:21.354] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C2.dat
[12:56:21.354] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C3.dat
[12:56:21.354] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C4.dat
[12:56:21.354] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C5.dat
[12:56:21.354] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C6.dat
[12:56:21.355] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C7.dat
[12:56:21.355] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C8.dat
[12:56:21.355] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C9.dat
[12:56:21.355] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C10.dat
[12:56:21.355] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C11.dat
[12:56:21.355] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C12.dat
[12:56:21.355] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C13.dat
[12:56:21.355] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C14.dat
[12:56:21.355] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C15.dat
[12:56:21.355] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C0.dat
[12:56:21.360] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C1.dat
[12:56:21.365] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C2.dat
[12:56:21.370] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C3.dat
[12:56:21.376] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C4.dat
[12:56:21.381] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C5.dat
[12:56:21.386] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C6.dat
[12:56:21.391] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C7.dat
[12:56:21.396] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C8.dat
[12:56:21.401] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C9.dat
[12:56:21.405] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C10.dat
[12:56:21.411] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C11.dat
[12:56:21.415] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C12.dat
[12:56:21.420] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C13.dat
[12:56:21.426] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C14.dat
[12:56:21.430] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C15.dat
[12:56:21.435] <TB2> INFO: PixTestTrim::trimTest() done
[12:56:21.435] <TB2> INFO: vtrim: 166 142 141 149 121 177 116 118 133 122 134 189 117 121 126 122
[12:56:21.435] <TB2> INFO: vthrcomp: 131 129 129 131 128 136 121 130 133 125 131 133 122 122 116 131
[12:56:21.435] <TB2> INFO: vcal mean: 35.07 35.11 35.30 35.03 34.95 35.72 34.96 34.95 35.09 34.98 35.17 35.05 34.97 34.90 34.98 34.94
[12:56:21.435] <TB2> INFO: vcal RMS: 1.18 1.23 1.35 1.11 1.02 2.25 1.03 0.98 1.15 1.08 1.29 1.16 1.05 1.16 0.99 1.01
[12:56:21.435] <TB2> INFO: bits mean: 9.18 8.69 9.29 7.87 9.40 7.91 9.37 9.76 8.09 9.71 9.45 7.78 9.35 8.74 9.47 9.37
[12:56:21.435] <TB2> INFO: bits RMS: 2.49 2.47 2.88 2.31 2.74 2.31 2.65 2.60 2.94 2.54 2.69 2.09 2.56 2.59 2.81 3.03
[12:56:21.444] <TB2> INFO: ----------------------------------------------------------------------
[12:56:21.444] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:56:21.444] <TB2> INFO: ----------------------------------------------------------------------
[12:56:21.447] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:56:21.460] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:56:21.460] <TB2> INFO: run 1 of 1
[12:56:21.717] <TB2> INFO: Expecting 4160000 events.
[12:56:54.835] <TB2> INFO: 768790 events read in total (32526ms).
[12:57:26.899] <TB2> INFO: 1530705 events read in total (64590ms).
[12:57:59.024] <TB2> INFO: 2287585 events read in total (96715ms).
[12:58:30.923] <TB2> INFO: 3040135 events read in total (128614ms).
[12:59:02.677] <TB2> INFO: 3789970 events read in total (160368ms).
[12:59:18.788] <TB2> INFO: 4160000 events read in total (176479ms).
[12:59:18.851] <TB2> INFO: Test took 177390ms.
[12:59:45.422] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 210 (-1/-1) hits flags = 528 (plus default)
[12:59:45.436] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:59:45.436] <TB2> INFO: run 1 of 1
[12:59:45.674] <TB2> INFO: Expecting 4388800 events.
[13:00:17.631] <TB2> INFO: 728880 events read in total (31365ms).
[13:00:49.021] <TB2> INFO: 1452525 events read in total (62755ms).
[13:01:20.718] <TB2> INFO: 2173135 events read in total (94452ms).
[13:01:52.218] <TB2> INFO: 2889930 events read in total (125952ms).
[13:02:23.506] <TB2> INFO: 3604550 events read in total (157240ms).
[13:02:54.130] <TB2> INFO: 4319245 events read in total (187864ms).
[13:02:57.485] <TB2> INFO: 4388800 events read in total (191219ms).
[13:02:57.588] <TB2> INFO: Test took 192152ms.
[13:03:24.590] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[13:03:24.604] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:03:24.604] <TB2> INFO: run 1 of 1
[13:03:24.846] <TB2> INFO: Expecting 4472000 events.
[13:03:56.669] <TB2> INFO: 724850 events read in total (31231ms).
[13:04:27.963] <TB2> INFO: 1443880 events read in total (62525ms).
[13:04:59.380] <TB2> INFO: 2160680 events read in total (93942ms).
[13:05:30.564] <TB2> INFO: 2873395 events read in total (125127ms).
[13:06:01.472] <TB2> INFO: 3583850 events read in total (156034ms).
[13:06:33.202] <TB2> INFO: 4294210 events read in total (187764ms).
[13:06:41.239] <TB2> INFO: 4472000 events read in total (195801ms).
[13:06:41.341] <TB2> INFO: Test took 196737ms.
[13:07:14.220] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[13:07:14.234] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:07:14.234] <TB2> INFO: run 1 of 1
[13:07:14.512] <TB2> INFO: Expecting 4430400 events.
[13:07:46.363] <TB2> INFO: 727255 events read in total (31259ms).
[13:08:18.049] <TB2> INFO: 1449290 events read in total (62945ms).
[13:08:49.200] <TB2> INFO: 2168445 events read in total (94096ms).
[13:09:20.767] <TB2> INFO: 2883870 events read in total (125663ms).
[13:09:51.803] <TB2> INFO: 3597230 events read in total (156699ms).
[13:10:22.821] <TB2> INFO: 4309915 events read in total (187717ms).
[13:10:28.703] <TB2> INFO: 4430400 events read in total (193599ms).
[13:10:28.812] <TB2> INFO: Test took 194578ms.
[13:10:56.117] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[13:10:56.131] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:10:56.131] <TB2> INFO: run 1 of 1
[13:10:56.423] <TB2> INFO: Expecting 4430400 events.
[13:11:28.321] <TB2> INFO: 727925 events read in total (31306ms).
[13:11:59.630] <TB2> INFO: 1450400 events read in total (62615ms).
[13:12:30.842] <TB2> INFO: 2169810 events read in total (93827ms).
[13:13:01.923] <TB2> INFO: 2885470 events read in total (124908ms).
[13:13:33.337] <TB2> INFO: 3598950 events read in total (156322ms).
[13:14:05.738] <TB2> INFO: 4311970 events read in total (188723ms).
[13:14:11.355] <TB2> INFO: 4430400 events read in total (194340ms).
[13:14:11.436] <TB2> INFO: Test took 195305ms.
[13:14:36.826] <TB2> INFO: PixTestTrim::trimBitTest() done
[13:14:36.827] <TB2> INFO: PixTestTrim::doTest() done, duration: 2563 seconds
[13:14:36.827] <TB2> INFO: Decoding statistics:
[13:14:36.827] <TB2> INFO: General information:
[13:14:36.827] <TB2> INFO: 16bit words read: 0
[13:14:36.827] <TB2> INFO: valid events total: 0
[13:14:36.827] <TB2> INFO: empty events: 0
[13:14:36.827] <TB2> INFO: valid events with pixels: 0
[13:14:36.827] <TB2> INFO: valid pixel hits: 0
[13:14:36.827] <TB2> INFO: Event errors: 0
[13:14:36.827] <TB2> INFO: start marker: 0
[13:14:36.827] <TB2> INFO: stop marker: 0
[13:14:36.827] <TB2> INFO: overflow: 0
[13:14:36.827] <TB2> INFO: invalid 5bit words: 0
[13:14:36.827] <TB2> INFO: invalid XOR eye diagram: 0
[13:14:36.827] <TB2> INFO: frame (failed synchr.): 0
[13:14:36.827] <TB2> INFO: idle data (no TBM trl): 0
[13:14:36.827] <TB2> INFO: no data (only TBM hdr): 0
[13:14:36.827] <TB2> INFO: TBM errors: 0
[13:14:36.827] <TB2> INFO: flawed TBM headers: 0
[13:14:36.827] <TB2> INFO: flawed TBM trailers: 0
[13:14:36.827] <TB2> INFO: event ID mismatches: 0
[13:14:36.827] <TB2> INFO: ROC errors: 0
[13:14:36.827] <TB2> INFO: missing ROC header(s): 0
[13:14:36.827] <TB2> INFO: misplaced readback start: 0
[13:14:36.827] <TB2> INFO: Pixel decoding errors: 0
[13:14:36.827] <TB2> INFO: pixel data incomplete: 0
[13:14:36.827] <TB2> INFO: pixel address: 0
[13:14:36.827] <TB2> INFO: pulse height fill bit: 0
[13:14:36.827] <TB2> INFO: buffer corruption: 0
[13:14:37.597] <TB2> INFO: ######################################################################
[13:14:37.597] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:14:37.597] <TB2> INFO: ######################################################################
[13:14:37.837] <TB2> INFO: Expecting 41600 events.
[13:14:41.289] <TB2> INFO: 41600 events read in total (2861ms).
[13:14:41.291] <TB2> INFO: Test took 3693ms.
[13:14:41.736] <TB2> INFO: Expecting 41600 events.
[13:14:45.242] <TB2> INFO: 41600 events read in total (2914ms).
[13:14:45.243] <TB2> INFO: Test took 3746ms.
[13:14:45.532] <TB2> INFO: Expecting 41600 events.
[13:14:49.105] <TB2> INFO: 41600 events read in total (2981ms).
[13:14:49.107] <TB2> INFO: Test took 3840ms.
[13:14:49.399] <TB2> INFO: Expecting 41600 events.
[13:14:53.004] <TB2> INFO: 41600 events read in total (3013ms).
[13:14:53.005] <TB2> INFO: Test took 3872ms.
[13:14:53.295] <TB2> INFO: Expecting 41600 events.
[13:14:56.845] <TB2> INFO: 41600 events read in total (2958ms).
[13:14:56.846] <TB2> INFO: Test took 3816ms.
[13:14:57.135] <TB2> INFO: Expecting 41600 events.
[13:15:00.638] <TB2> INFO: 41600 events read in total (2911ms).
[13:15:00.639] <TB2> INFO: Test took 3769ms.
[13:15:00.929] <TB2> INFO: Expecting 41600 events.
[13:15:04.447] <TB2> INFO: 41600 events read in total (2927ms).
[13:15:04.447] <TB2> INFO: Test took 3784ms.
[13:15:04.737] <TB2> INFO: Expecting 41600 events.
[13:15:08.363] <TB2> INFO: 41600 events read in total (3035ms).
[13:15:08.364] <TB2> INFO: Test took 3893ms.
[13:15:08.653] <TB2> INFO: Expecting 41600 events.
[13:15:12.185] <TB2> INFO: 41600 events read in total (2940ms).
[13:15:12.186] <TB2> INFO: Test took 3797ms.
[13:15:12.479] <TB2> INFO: Expecting 41600 events.
[13:15:16.020] <TB2> INFO: 41600 events read in total (2949ms).
[13:15:16.021] <TB2> INFO: Test took 3807ms.
[13:15:16.313] <TB2> INFO: Expecting 41600 events.
[13:15:19.847] <TB2> INFO: 41600 events read in total (2943ms).
[13:15:19.848] <TB2> INFO: Test took 3800ms.
[13:15:20.159] <TB2> INFO: Expecting 41600 events.
[13:15:23.777] <TB2> INFO: 41600 events read in total (3026ms).
[13:15:23.778] <TB2> INFO: Test took 3903ms.
[13:15:24.067] <TB2> INFO: Expecting 41600 events.
[13:15:27.568] <TB2> INFO: 41600 events read in total (2909ms).
[13:15:27.569] <TB2> INFO: Test took 3766ms.
[13:15:27.858] <TB2> INFO: Expecting 41600 events.
[13:15:31.357] <TB2> INFO: 41600 events read in total (2907ms).
[13:15:31.358] <TB2> INFO: Test took 3765ms.
[13:15:31.647] <TB2> INFO: Expecting 41600 events.
[13:15:35.128] <TB2> INFO: 41600 events read in total (2889ms).
[13:15:35.129] <TB2> INFO: Test took 3747ms.
[13:15:35.421] <TB2> INFO: Expecting 41600 events.
[13:15:38.951] <TB2> INFO: 41600 events read in total (2939ms).
[13:15:38.952] <TB2> INFO: Test took 3796ms.
[13:15:39.282] <TB2> INFO: Expecting 41600 events.
[13:15:42.855] <TB2> INFO: 41600 events read in total (2982ms).
[13:15:42.855] <TB2> INFO: Test took 3879ms.
[13:15:43.145] <TB2> INFO: Expecting 41600 events.
[13:15:46.674] <TB2> INFO: 41600 events read in total (2937ms).
[13:15:46.675] <TB2> INFO: Test took 3794ms.
[13:15:46.967] <TB2> INFO: Expecting 41600 events.
[13:15:50.495] <TB2> INFO: 41600 events read in total (2936ms).
[13:15:50.496] <TB2> INFO: Test took 3794ms.
[13:15:50.788] <TB2> INFO: Expecting 41600 events.
[13:15:54.362] <TB2> INFO: 41600 events read in total (2983ms).
[13:15:54.363] <TB2> INFO: Test took 3840ms.
[13:15:54.655] <TB2> INFO: Expecting 41600 events.
[13:15:58.152] <TB2> INFO: 41600 events read in total (2905ms).
[13:15:58.152] <TB2> INFO: Test took 3763ms.
[13:15:58.457] <TB2> INFO: Expecting 41600 events.
[13:16:02.221] <TB2> INFO: 41600 events read in total (3172ms).
[13:16:02.222] <TB2> INFO: Test took 4045ms.
[13:16:02.525] <TB2> INFO: Expecting 41600 events.
[13:16:06.054] <TB2> INFO: 41600 events read in total (2937ms).
[13:16:06.055] <TB2> INFO: Test took 3806ms.
[13:16:06.347] <TB2> INFO: Expecting 41600 events.
[13:16:09.979] <TB2> INFO: 41600 events read in total (3040ms).
[13:16:09.980] <TB2> INFO: Test took 3898ms.
[13:16:10.271] <TB2> INFO: Expecting 41600 events.
[13:16:13.770] <TB2> INFO: 41600 events read in total (2907ms).
[13:16:13.772] <TB2> INFO: Test took 3767ms.
[13:16:14.063] <TB2> INFO: Expecting 41600 events.
[13:16:17.586] <TB2> INFO: 41600 events read in total (2932ms).
[13:16:17.587] <TB2> INFO: Test took 3789ms.
[13:16:17.880] <TB2> INFO: Expecting 2560 events.
[13:16:18.765] <TB2> INFO: 2560 events read in total (293ms).
[13:16:18.766] <TB2> INFO: Test took 1163ms.
[13:16:19.074] <TB2> INFO: Expecting 2560 events.
[13:16:19.969] <TB2> INFO: 2560 events read in total (303ms).
[13:16:19.970] <TB2> INFO: Test took 1204ms.
[13:16:20.277] <TB2> INFO: Expecting 2560 events.
[13:16:21.174] <TB2> INFO: 2560 events read in total (306ms).
[13:16:21.174] <TB2> INFO: Test took 1204ms.
[13:16:21.482] <TB2> INFO: Expecting 2560 events.
[13:16:22.378] <TB2> INFO: 2560 events read in total (304ms).
[13:16:22.379] <TB2> INFO: Test took 1204ms.
[13:16:22.686] <TB2> INFO: Expecting 2560 events.
[13:16:23.575] <TB2> INFO: 2560 events read in total (297ms).
[13:16:23.575] <TB2> INFO: Test took 1196ms.
[13:16:23.882] <TB2> INFO: Expecting 2560 events.
[13:16:24.767] <TB2> INFO: 2560 events read in total (294ms).
[13:16:24.767] <TB2> INFO: Test took 1191ms.
[13:16:25.076] <TB2> INFO: Expecting 2560 events.
[13:16:25.959] <TB2> INFO: 2560 events read in total (291ms).
[13:16:25.959] <TB2> INFO: Test took 1191ms.
[13:16:26.268] <TB2> INFO: Expecting 2560 events.
[13:16:27.159] <TB2> INFO: 2560 events read in total (299ms).
[13:16:27.160] <TB2> INFO: Test took 1200ms.
[13:16:27.466] <TB2> INFO: Expecting 2560 events.
[13:16:28.350] <TB2> INFO: 2560 events read in total (292ms).
[13:16:28.350] <TB2> INFO: Test took 1189ms.
[13:16:28.658] <TB2> INFO: Expecting 2560 events.
[13:16:29.541] <TB2> INFO: 2560 events read in total (291ms).
[13:16:29.541] <TB2> INFO: Test took 1191ms.
[13:16:29.850] <TB2> INFO: Expecting 2560 events.
[13:16:30.737] <TB2> INFO: 2560 events read in total (295ms).
[13:16:30.738] <TB2> INFO: Test took 1197ms.
[13:16:31.045] <TB2> INFO: Expecting 2560 events.
[13:16:31.935] <TB2> INFO: 2560 events read in total (298ms).
[13:16:31.935] <TB2> INFO: Test took 1196ms.
[13:16:32.243] <TB2> INFO: Expecting 2560 events.
[13:16:33.135] <TB2> INFO: 2560 events read in total (301ms).
[13:16:33.135] <TB2> INFO: Test took 1200ms.
[13:16:33.442] <TB2> INFO: Expecting 2560 events.
[13:16:34.336] <TB2> INFO: 2560 events read in total (303ms).
[13:16:34.336] <TB2> INFO: Test took 1200ms.
[13:16:34.643] <TB2> INFO: Expecting 2560 events.
[13:16:35.535] <TB2> INFO: 2560 events read in total (301ms).
[13:16:35.535] <TB2> INFO: Test took 1198ms.
[13:16:35.844] <TB2> INFO: Expecting 2560 events.
[13:16:36.730] <TB2> INFO: 2560 events read in total (295ms).
[13:16:36.730] <TB2> INFO: Test took 1194ms.
[13:16:36.734] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:37.038] <TB2> INFO: Expecting 655360 events.
[13:16:51.850] <TB2> INFO: 655360 events read in total (14220ms).
[13:16:51.865] <TB2> INFO: Expecting 655360 events.
[13:17:06.313] <TB2> INFO: 655360 events read in total (14045ms).
[13:17:06.330] <TB2> INFO: Expecting 655360 events.
[13:17:20.901] <TB2> INFO: 655360 events read in total (14168ms).
[13:17:20.921] <TB2> INFO: Expecting 655360 events.
[13:17:35.340] <TB2> INFO: 655360 events read in total (14016ms).
[13:17:35.366] <TB2> INFO: Expecting 655360 events.
[13:17:49.921] <TB2> INFO: 655360 events read in total (14151ms).
[13:17:49.951] <TB2> INFO: Expecting 655360 events.
[13:18:04.498] <TB2> INFO: 655360 events read in total (14143ms).
[13:18:04.536] <TB2> INFO: Expecting 655360 events.
[13:18:19.126] <TB2> INFO: 655360 events read in total (14187ms).
[13:18:19.169] <TB2> INFO: Expecting 655360 events.
[13:18:33.658] <TB2> INFO: 655360 events read in total (14086ms).
[13:18:33.701] <TB2> INFO: Expecting 655360 events.
[13:18:48.241] <TB2> INFO: 655360 events read in total (14137ms).
[13:18:48.290] <TB2> INFO: Expecting 655360 events.
[13:19:02.795] <TB2> INFO: 655360 events read in total (14102ms).
[13:19:02.848] <TB2> INFO: Expecting 655360 events.
[13:19:17.410] <TB2> INFO: 655360 events read in total (14159ms).
[13:19:17.512] <TB2> INFO: Expecting 655360 events.
[13:19:32.028] <TB2> INFO: 655360 events read in total (14113ms).
[13:19:32.131] <TB2> INFO: Expecting 655360 events.
[13:19:46.736] <TB2> INFO: 655360 events read in total (14202ms).
[13:19:46.846] <TB2> INFO: Expecting 655360 events.
[13:20:01.381] <TB2> INFO: 655360 events read in total (14132ms).
[13:20:01.504] <TB2> INFO: Expecting 655360 events.
[13:20:15.964] <TB2> INFO: 655360 events read in total (14056ms).
[13:20:16.056] <TB2> INFO: Expecting 655360 events.
[13:20:30.586] <TB2> INFO: 655360 events read in total (14127ms).
[13:20:30.733] <TB2> INFO: Test took 233999ms.
[13:20:30.829] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:31.087] <TB2> INFO: Expecting 655360 events.
[13:20:45.784] <TB2> INFO: 655360 events read in total (14105ms).
[13:20:45.797] <TB2> INFO: Expecting 655360 events.
[13:20:59.951] <TB2> INFO: 655360 events read in total (13751ms).
[13:20:59.974] <TB2> INFO: Expecting 655360 events.
[13:21:14.323] <TB2> INFO: 655360 events read in total (13946ms).
[13:21:14.343] <TB2> INFO: Expecting 655360 events.
[13:21:28.795] <TB2> INFO: 655360 events read in total (14049ms).
[13:21:28.820] <TB2> INFO: Expecting 655360 events.
[13:21:43.037] <TB2> INFO: 655360 events read in total (13814ms).
[13:21:43.068] <TB2> INFO: Expecting 655360 events.
[13:21:57.461] <TB2> INFO: 655360 events read in total (13990ms).
[13:21:57.506] <TB2> INFO: Expecting 655360 events.
[13:22:11.504] <TB2> INFO: 655360 events read in total (13594ms).
[13:22:11.544] <TB2> INFO: Expecting 655360 events.
[13:22:25.899] <TB2> INFO: 655360 events read in total (13952ms).
[13:22:25.942] <TB2> INFO: Expecting 655360 events.
[13:22:40.212] <TB2> INFO: 655360 events read in total (13867ms).
[13:22:40.267] <TB2> INFO: Expecting 655360 events.
[13:22:54.493] <TB2> INFO: 655360 events read in total (13823ms).
[13:22:54.549] <TB2> INFO: Expecting 655360 events.
[13:23:08.989] <TB2> INFO: 655360 events read in total (14036ms).
[13:23:09.056] <TB2> INFO: Expecting 655360 events.
[13:23:23.256] <TB2> INFO: 655360 events read in total (13797ms).
[13:23:23.350] <TB2> INFO: Expecting 655360 events.
[13:23:37.669] <TB2> INFO: 655360 events read in total (13916ms).
[13:23:37.748] <TB2> INFO: Expecting 655360 events.
[13:23:52.127] <TB2> INFO: 655360 events read in total (13976ms).
[13:23:52.231] <TB2> INFO: Expecting 655360 events.
[13:24:06.801] <TB2> INFO: 655360 events read in total (14167ms).
[13:24:06.892] <TB2> INFO: Expecting 655360 events.
[13:24:21.263] <TB2> INFO: 655360 events read in total (13967ms).
[13:24:21.408] <TB2> INFO: Test took 230579ms.
[13:24:21.610] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.617] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.624] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.631] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:24:21.638] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:24:21.646] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:24:21.653] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:24:21.659] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[13:24:21.665] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[13:24:21.671] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[13:24:21.677] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[13:24:21.684] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.690] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.696] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:24:21.702] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:24:21.709] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:24:21.715] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.721] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.728] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.734] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.740] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.746] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:24:21.752] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:24:21.759] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.765] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.772] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.780] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:24:21.786] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:24:21.793] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:24:21.800] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:24:21.807] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[13:24:21.815] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.822] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:24:21.829] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:24:21.836] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:24:21.844] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:24:21.851] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[13:24:21.859] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[13:24:21.866] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[13:24:21.873] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[13:24:21.879] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[13:24:21.885] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[13:24:21.893] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.900] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:21.906] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:24:21.941] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C0.dat
[13:24:21.941] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C1.dat
[13:24:21.941] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C2.dat
[13:24:21.941] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C3.dat
[13:24:21.941] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C4.dat
[13:24:21.941] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C5.dat
[13:24:21.941] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C6.dat
[13:24:21.941] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C7.dat
[13:24:21.942] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C8.dat
[13:24:21.942] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C9.dat
[13:24:21.942] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C10.dat
[13:24:21.942] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C11.dat
[13:24:21.942] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C12.dat
[13:24:21.942] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C13.dat
[13:24:21.942] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C14.dat
[13:24:21.942] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C15.dat
[13:24:22.186] <TB2> INFO: Expecting 41600 events.
[13:24:25.355] <TB2> INFO: 41600 events read in total (2577ms).
[13:24:25.356] <TB2> INFO: Test took 3411ms.
[13:24:25.810] <TB2> INFO: Expecting 41600 events.
[13:24:28.857] <TB2> INFO: 41600 events read in total (2455ms).
[13:24:28.858] <TB2> INFO: Test took 3287ms.
[13:24:29.316] <TB2> INFO: Expecting 41600 events.
[13:24:32.500] <TB2> INFO: 41600 events read in total (2592ms).
[13:24:32.501] <TB2> INFO: Test took 3425ms.
[13:24:32.718] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:32.807] <TB2> INFO: Expecting 2560 events.
[13:24:33.703] <TB2> INFO: 2560 events read in total (304ms).
[13:24:33.703] <TB2> INFO: Test took 985ms.
[13:24:33.706] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:34.011] <TB2> INFO: Expecting 2560 events.
[13:24:34.900] <TB2> INFO: 2560 events read in total (297ms).
[13:24:34.900] <TB2> INFO: Test took 1194ms.
[13:24:34.903] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:35.209] <TB2> INFO: Expecting 2560 events.
[13:24:36.104] <TB2> INFO: 2560 events read in total (303ms).
[13:24:36.104] <TB2> INFO: Test took 1201ms.
[13:24:36.108] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:36.413] <TB2> INFO: Expecting 2560 events.
[13:24:37.306] <TB2> INFO: 2560 events read in total (301ms).
[13:24:37.307] <TB2> INFO: Test took 1199ms.
[13:24:37.309] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:37.615] <TB2> INFO: Expecting 2560 events.
[13:24:38.507] <TB2> INFO: 2560 events read in total (301ms).
[13:24:38.508] <TB2> INFO: Test took 1199ms.
[13:24:38.510] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:38.816] <TB2> INFO: Expecting 2560 events.
[13:24:39.714] <TB2> INFO: 2560 events read in total (306ms).
[13:24:39.714] <TB2> INFO: Test took 1204ms.
[13:24:39.717] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:40.024] <TB2> INFO: Expecting 2560 events.
[13:24:40.922] <TB2> INFO: 2560 events read in total (307ms).
[13:24:40.922] <TB2> INFO: Test took 1205ms.
[13:24:40.926] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:41.231] <TB2> INFO: Expecting 2560 events.
[13:24:42.124] <TB2> INFO: 2560 events read in total (301ms).
[13:24:42.124] <TB2> INFO: Test took 1198ms.
[13:24:42.128] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:42.433] <TB2> INFO: Expecting 2560 events.
[13:24:43.323] <TB2> INFO: 2560 events read in total (299ms).
[13:24:43.323] <TB2> INFO: Test took 1195ms.
[13:24:43.326] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:43.633] <TB2> INFO: Expecting 2560 events.
[13:24:44.526] <TB2> INFO: 2560 events read in total (301ms).
[13:24:44.527] <TB2> INFO: Test took 1201ms.
[13:24:44.529] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:44.835] <TB2> INFO: Expecting 2560 events.
[13:24:45.724] <TB2> INFO: 2560 events read in total (297ms).
[13:24:45.725] <TB2> INFO: Test took 1196ms.
[13:24:45.727] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:46.033] <TB2> INFO: Expecting 2560 events.
[13:24:46.926] <TB2> INFO: 2560 events read in total (301ms).
[13:24:46.927] <TB2> INFO: Test took 1200ms.
[13:24:46.931] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:47.234] <TB2> INFO: Expecting 2560 events.
[13:24:48.124] <TB2> INFO: 2560 events read in total (298ms).
[13:24:48.125] <TB2> INFO: Test took 1194ms.
[13:24:48.127] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:48.433] <TB2> INFO: Expecting 2560 events.
[13:24:49.325] <TB2> INFO: 2560 events read in total (300ms).
[13:24:49.326] <TB2> INFO: Test took 1199ms.
[13:24:49.328] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:49.634] <TB2> INFO: Expecting 2560 events.
[13:24:50.524] <TB2> INFO: 2560 events read in total (298ms).
[13:24:50.524] <TB2> INFO: Test took 1196ms.
[13:24:50.527] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:50.833] <TB2> INFO: Expecting 2560 events.
[13:24:51.718] <TB2> INFO: 2560 events read in total (293ms).
[13:24:51.719] <TB2> INFO: Test took 1192ms.
[13:24:51.722] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:52.027] <TB2> INFO: Expecting 2560 events.
[13:24:52.921] <TB2> INFO: 2560 events read in total (304ms).
[13:24:52.922] <TB2> INFO: Test took 1200ms.
[13:24:52.926] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:53.230] <TB2> INFO: Expecting 2560 events.
[13:24:54.122] <TB2> INFO: 2560 events read in total (300ms).
[13:24:54.122] <TB2> INFO: Test took 1197ms.
[13:24:54.125] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:54.431] <TB2> INFO: Expecting 2560 events.
[13:24:55.317] <TB2> INFO: 2560 events read in total (295ms).
[13:24:55.318] <TB2> INFO: Test took 1193ms.
[13:24:55.321] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:55.624] <TB2> INFO: Expecting 2560 events.
[13:24:56.505] <TB2> INFO: 2560 events read in total (289ms).
[13:24:56.505] <TB2> INFO: Test took 1184ms.
[13:24:56.509] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:56.814] <TB2> INFO: Expecting 2560 events.
[13:24:57.703] <TB2> INFO: 2560 events read in total (297ms).
[13:24:57.703] <TB2> INFO: Test took 1194ms.
[13:24:57.706] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:58.012] <TB2> INFO: Expecting 2560 events.
[13:24:58.901] <TB2> INFO: 2560 events read in total (297ms).
[13:24:58.901] <TB2> INFO: Test took 1195ms.
[13:24:58.904] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:59.210] <TB2> INFO: Expecting 2560 events.
[13:25:00.090] <TB2> INFO: 2560 events read in total (288ms).
[13:25:00.090] <TB2> INFO: Test took 1186ms.
[13:25:00.095] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:00.399] <TB2> INFO: Expecting 2560 events.
[13:25:01.289] <TB2> INFO: 2560 events read in total (298ms).
[13:25:01.289] <TB2> INFO: Test took 1194ms.
[13:25:01.292] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:01.598] <TB2> INFO: Expecting 2560 events.
[13:25:02.490] <TB2> INFO: 2560 events read in total (301ms).
[13:25:02.490] <TB2> INFO: Test took 1198ms.
[13:25:02.494] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:02.799] <TB2> INFO: Expecting 2560 events.
[13:25:03.693] <TB2> INFO: 2560 events read in total (302ms).
[13:25:03.694] <TB2> INFO: Test took 1201ms.
[13:25:03.698] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:03.003] <TB2> INFO: Expecting 2560 events.
[13:25:04.894] <TB2> INFO: 2560 events read in total (299ms).
[13:25:04.895] <TB2> INFO: Test took 1197ms.
[13:25:04.897] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:05.204] <TB2> INFO: Expecting 2560 events.
[13:25:06.098] <TB2> INFO: 2560 events read in total (302ms).
[13:25:06.099] <TB2> INFO: Test took 1202ms.
[13:25:06.102] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:06.408] <TB2> INFO: Expecting 2560 events.
[13:25:07.307] <TB2> INFO: 2560 events read in total (307ms).
[13:25:07.307] <TB2> INFO: Test took 1205ms.
[13:25:07.311] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:07.615] <TB2> INFO: Expecting 2560 events.
[13:25:08.501] <TB2> INFO: 2560 events read in total (294ms).
[13:25:08.501] <TB2> INFO: Test took 1190ms.
[13:25:08.505] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:08.812] <TB2> INFO: Expecting 2560 events.
[13:25:09.708] <TB2> INFO: 2560 events read in total (304ms).
[13:25:09.709] <TB2> INFO: Test took 1204ms.
[13:25:09.713] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:10.017] <TB2> INFO: Expecting 2560 events.
[13:25:10.905] <TB2> INFO: 2560 events read in total (297ms).
[13:25:10.905] <TB2> INFO: Test took 1193ms.
[13:25:11.392] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 633 seconds
[13:25:11.392] <TB2> INFO: PH scale (per ROC): 33 35 42 49 49 35 51 45 58 41 46 46 48 36 40 46
[13:25:11.392] <TB2> INFO: PH offset (per ROC): 104 110 112 96 125 107 123 99 121 107 101 106 112 112 99 99
[13:25:11.402] <TB2> INFO: Decoding statistics:
[13:25:11.402] <TB2> INFO: General information:
[13:25:11.402] <TB2> INFO: 16bit words read: 127890
[13:25:11.402] <TB2> INFO: valid events total: 20480
[13:25:11.402] <TB2> INFO: empty events: 17975
[13:25:11.402] <TB2> INFO: valid events with pixels: 2505
[13:25:11.402] <TB2> INFO: valid pixel hits: 2505
[13:25:11.402] <TB2> INFO: Event errors: 0
[13:25:11.402] <TB2> INFO: start marker: 0
[13:25:11.402] <TB2> INFO: stop marker: 0
[13:25:11.402] <TB2> INFO: overflow: 0
[13:25:11.402] <TB2> INFO: invalid 5bit words: 0
[13:25:11.402] <TB2> INFO: invalid XOR eye diagram: 0
[13:25:11.402] <TB2> INFO: frame (failed synchr.): 0
[13:25:11.402] <TB2> INFO: idle data (no TBM trl): 0
[13:25:11.402] <TB2> INFO: no data (only TBM hdr): 0
[13:25:11.402] <TB2> INFO: TBM errors: 0
[13:25:11.402] <TB2> INFO: flawed TBM headers: 0
[13:25:11.402] <TB2> INFO: flawed TBM trailers: 0
[13:25:11.402] <TB2> INFO: event ID mismatches: 0
[13:25:11.402] <TB2> INFO: ROC errors: 0
[13:25:11.402] <TB2> INFO: missing ROC header(s): 0
[13:25:11.402] <TB2> INFO: misplaced readback start: 0
[13:25:11.402] <TB2> INFO: Pixel decoding errors: 0
[13:25:11.402] <TB2> INFO: pixel data incomplete: 0
[13:25:11.402] <TB2> INFO: pixel address: 0
[13:25:11.402] <TB2> INFO: pulse height fill bit: 0
[13:25:11.402] <TB2> INFO: buffer corruption: 0
[13:25:11.574] <TB2> INFO: ######################################################################
[13:25:11.574] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:25:11.574] <TB2> INFO: ######################################################################
[13:25:11.590] <TB2> INFO: scanning low vcal = 10
[13:25:11.869] <TB2> INFO: Expecting 41600 events.
[13:25:15.466] <TB2> INFO: 41600 events read in total (3006ms).
[13:25:15.467] <TB2> INFO: Test took 3877ms.
[13:25:15.470] <TB2> INFO: scanning low vcal = 20
[13:25:15.767] <TB2> INFO: Expecting 41600 events.
[13:25:19.360] <TB2> INFO: 41600 events read in total (3001ms).
[13:25:19.360] <TB2> INFO: Test took 3890ms.
[13:25:19.362] <TB2> INFO: scanning low vcal = 30
[13:25:19.660] <TB2> INFO: Expecting 41600 events.
[13:25:23.318] <TB2> INFO: 41600 events read in total (3067ms).
[13:25:23.319] <TB2> INFO: Test took 3957ms.
[13:25:23.322] <TB2> INFO: scanning low vcal = 40
[13:25:23.600] <TB2> INFO: Expecting 41600 events.
[13:25:27.600] <TB2> INFO: 41600 events read in total (3408ms).
[13:25:27.602] <TB2> INFO: Test took 4280ms.
[13:25:27.605] <TB2> INFO: scanning low vcal = 50
[13:25:27.882] <TB2> INFO: Expecting 41600 events.
[13:25:31.882] <TB2> INFO: 41600 events read in total (3408ms).
[13:25:31.883] <TB2> INFO: Test took 4277ms.
[13:25:31.886] <TB2> INFO: scanning low vcal = 60
[13:25:32.163] <TB2> INFO: Expecting 41600 events.
[13:25:36.163] <TB2> INFO: 41600 events read in total (3409ms).
[13:25:36.164] <TB2> INFO: Test took 4278ms.
[13:25:36.167] <TB2> INFO: scanning low vcal = 70
[13:25:36.444] <TB2> INFO: Expecting 41600 events.
[13:25:40.468] <TB2> INFO: 41600 events read in total (3433ms).
[13:25:40.469] <TB2> INFO: Test took 4302ms.
[13:25:40.472] <TB2> INFO: scanning low vcal = 80
[13:25:40.749] <TB2> INFO: Expecting 41600 events.
[13:25:44.801] <TB2> INFO: 41600 events read in total (3460ms).
[13:25:44.802] <TB2> INFO: Test took 4330ms.
[13:25:44.805] <TB2> INFO: scanning low vcal = 90
[13:25:45.082] <TB2> INFO: Expecting 41600 events.
[13:25:49.102] <TB2> INFO: 41600 events read in total (3428ms).
[13:25:49.102] <TB2> INFO: Test took 4297ms.
[13:25:49.107] <TB2> INFO: scanning low vcal = 100
[13:25:49.382] <TB2> INFO: Expecting 41600 events.
[13:25:53.392] <TB2> INFO: 41600 events read in total (3418ms).
[13:25:53.393] <TB2> INFO: Test took 4286ms.
[13:25:53.396] <TB2> INFO: scanning low vcal = 110
[13:25:53.673] <TB2> INFO: Expecting 41600 events.
[13:25:57.745] <TB2> INFO: 41600 events read in total (3481ms).
[13:25:57.746] <TB2> INFO: Test took 4350ms.
[13:25:57.749] <TB2> INFO: scanning low vcal = 120
[13:25:58.074] <TB2> INFO: Expecting 41600 events.
[13:26:02.037] <TB2> INFO: 41600 events read in total (3372ms).
[13:26:02.037] <TB2> INFO: Test took 4288ms.
[13:26:02.040] <TB2> INFO: scanning low vcal = 130
[13:26:02.317] <TB2> INFO: Expecting 41600 events.
[13:26:06.257] <TB2> INFO: 41600 events read in total (3349ms).
[13:26:06.258] <TB2> INFO: Test took 4218ms.
[13:26:06.261] <TB2> INFO: scanning low vcal = 140
[13:26:06.537] <TB2> INFO: Expecting 41600 events.
[13:26:10.493] <TB2> INFO: 41600 events read in total (3364ms).
[13:26:10.493] <TB2> INFO: Test took 4232ms.
[13:26:10.496] <TB2> INFO: scanning low vcal = 150
[13:26:10.773] <TB2> INFO: Expecting 41600 events.
[13:26:14.716] <TB2> INFO: 41600 events read in total (3351ms).
[13:26:14.717] <TB2> INFO: Test took 4220ms.
[13:26:14.721] <TB2> INFO: scanning low vcal = 160
[13:26:14.997] <TB2> INFO: Expecting 41600 events.
[13:26:18.935] <TB2> INFO: 41600 events read in total (3346ms).
[13:26:18.936] <TB2> INFO: Test took 4215ms.
[13:26:18.939] <TB2> INFO: scanning low vcal = 170
[13:26:19.216] <TB2> INFO: Expecting 41600 events.
[13:26:23.152] <TB2> INFO: 41600 events read in total (3345ms).
[13:26:23.153] <TB2> INFO: Test took 4214ms.
[13:26:23.159] <TB2> INFO: scanning low vcal = 180
[13:26:23.433] <TB2> INFO: Expecting 41600 events.
[13:26:27.427] <TB2> INFO: 41600 events read in total (3403ms).
[13:26:27.428] <TB2> INFO: Test took 4269ms.
[13:26:27.431] <TB2> INFO: scanning low vcal = 190
[13:26:27.708] <TB2> INFO: Expecting 41600 events.
[13:26:31.719] <TB2> INFO: 41600 events read in total (3419ms).
[13:26:31.720] <TB2> INFO: Test took 4289ms.
[13:26:31.723] <TB2> INFO: scanning low vcal = 200
[13:26:31.000] <TB2> INFO: Expecting 41600 events.
[13:26:35.986] <TB2> INFO: 41600 events read in total (3395ms).
[13:26:35.986] <TB2> INFO: Test took 4263ms.
[13:26:35.989] <TB2> INFO: scanning low vcal = 210
[13:26:36.266] <TB2> INFO: Expecting 41600 events.
[13:26:40.221] <TB2> INFO: 41600 events read in total (3363ms).
[13:26:40.223] <TB2> INFO: Test took 4233ms.
[13:26:40.226] <TB2> INFO: scanning low vcal = 220
[13:26:40.503] <TB2> INFO: Expecting 41600 events.
[13:26:44.493] <TB2> INFO: 41600 events read in total (3399ms).
[13:26:44.494] <TB2> INFO: Test took 4268ms.
[13:26:44.498] <TB2> INFO: scanning low vcal = 230
[13:26:44.773] <TB2> INFO: Expecting 41600 events.
[13:26:48.756] <TB2> INFO: 41600 events read in total (3391ms).
[13:26:48.757] <TB2> INFO: Test took 4259ms.
[13:26:48.760] <TB2> INFO: scanning low vcal = 240
[13:26:49.037] <TB2> INFO: Expecting 41600 events.
[13:26:52.997] <TB2> INFO: 41600 events read in total (3368ms).
[13:26:52.998] <TB2> INFO: Test took 4238ms.
[13:26:52.002] <TB2> INFO: scanning low vcal = 250
[13:26:53.278] <TB2> INFO: Expecting 41600 events.
[13:26:57.283] <TB2> INFO: 41600 events read in total (3413ms).
[13:26:57.283] <TB2> INFO: Test took 4281ms.
[13:26:57.287] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[13:26:57.564] <TB2> INFO: Expecting 41600 events.
[13:27:01.551] <TB2> INFO: 41600 events read in total (3395ms).
[13:27:01.552] <TB2> INFO: Test took 4264ms.
[13:27:01.555] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[13:27:01.832] <TB2> INFO: Expecting 41600 events.
[13:27:05.842] <TB2> INFO: 41600 events read in total (3418ms).
[13:27:05.843] <TB2> INFO: Test took 4288ms.
[13:27:05.846] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[13:27:06.124] <TB2> INFO: Expecting 41600 events.
[13:27:10.099] <TB2> INFO: 41600 events read in total (3383ms).
[13:27:10.099] <TB2> INFO: Test took 4252ms.
[13:27:10.103] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[13:27:10.379] <TB2> INFO: Expecting 41600 events.
[13:27:14.338] <TB2> INFO: 41600 events read in total (3367ms).
[13:27:14.339] <TB2> INFO: Test took 4236ms.
[13:27:14.343] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:27:14.618] <TB2> INFO: Expecting 41600 events.
[13:27:18.587] <TB2> INFO: 41600 events read in total (3377ms).
[13:27:18.589] <TB2> INFO: Test took 4246ms.
[13:27:19.125] <TB2> INFO: PixTestGainPedestal::measure() done
[13:27:57.980] <TB2> INFO: PixTestGainPedestal::fit() done
[13:27:57.980] <TB2> INFO: non-linearity mean: 0.915 0.917 0.942 0.945 0.980 0.936 0.982 0.924 0.982 0.923 0.964 0.922 0.972 0.931 0.917 0.944
[13:27:57.980] <TB2> INFO: non-linearity RMS: 0.150 0.094 0.044 0.042 0.005 0.097 0.003 0.073 0.005 0.137 0.027 0.107 0.012 0.094 0.086 0.057
[13:27:57.980] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[13:27:57.001] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[13:27:58.023] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[13:27:58.044] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[13:27:58.066] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[13:27:58.087] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[13:27:58.109] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[13:27:58.130] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[13:27:58.151] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[13:27:58.172] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[13:27:58.194] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[13:27:58.215] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[13:27:58.237] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[13:27:58.258] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[13:27:58.279] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[13:27:58.301] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[13:27:58.322] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 166 seconds
[13:27:58.322] <TB2> INFO: Decoding statistics:
[13:27:58.322] <TB2> INFO: General information:
[13:27:58.322] <TB2> INFO: 16bit words read: 3297630
[13:27:58.322] <TB2> INFO: valid events total: 332800
[13:27:58.322] <TB2> INFO: empty events: 97
[13:27:58.322] <TB2> INFO: valid events with pixels: 332703
[13:27:58.322] <TB2> INFO: valid pixel hits: 650415
[13:27:58.322] <TB2> INFO: Event errors: 0
[13:27:58.322] <TB2> INFO: start marker: 0
[13:27:58.322] <TB2> INFO: stop marker: 0
[13:27:58.322] <TB2> INFO: overflow: 0
[13:27:58.322] <TB2> INFO: invalid 5bit words: 0
[13:27:58.322] <TB2> INFO: invalid XOR eye diagram: 0
[13:27:58.322] <TB2> INFO: frame (failed synchr.): 0
[13:27:58.323] <TB2> INFO: idle data (no TBM trl): 0
[13:27:58.323] <TB2> INFO: no data (only TBM hdr): 0
[13:27:58.323] <TB2> INFO: TBM errors: 0
[13:27:58.323] <TB2> INFO: flawed TBM headers: 0
[13:27:58.323] <TB2> INFO: flawed TBM trailers: 0
[13:27:58.323] <TB2> INFO: event ID mismatches: 0
[13:27:58.323] <TB2> INFO: ROC errors: 0
[13:27:58.323] <TB2> INFO: missing ROC header(s): 0
[13:27:58.323] <TB2> INFO: misplaced readback start: 0
[13:27:58.323] <TB2> INFO: Pixel decoding errors: 0
[13:27:58.323] <TB2> INFO: pixel data incomplete: 0
[13:27:58.323] <TB2> INFO: pixel address: 0
[13:27:58.323] <TB2> INFO: pulse height fill bit: 0
[13:27:58.323] <TB2> INFO: buffer corruption: 0
[13:27:58.346] <TB2> INFO: Decoding statistics:
[13:27:58.346] <TB2> INFO: General information:
[13:27:58.346] <TB2> INFO: 16bit words read: 3427056
[13:27:58.346] <TB2> INFO: valid events total: 353536
[13:27:58.346] <TB2> INFO: empty events: 18328
[13:27:58.346] <TB2> INFO: valid events with pixels: 335208
[13:27:58.346] <TB2> INFO: valid pixel hits: 652920
[13:27:58.346] <TB2> INFO: Event errors: 0
[13:27:58.346] <TB2> INFO: start marker: 0
[13:27:58.346] <TB2> INFO: stop marker: 0
[13:27:58.346] <TB2> INFO: overflow: 0
[13:27:58.346] <TB2> INFO: invalid 5bit words: 0
[13:27:58.346] <TB2> INFO: invalid XOR eye diagram: 0
[13:27:58.346] <TB2> INFO: frame (failed synchr.): 0
[13:27:58.346] <TB2> INFO: idle data (no TBM trl): 0
[13:27:58.346] <TB2> INFO: no data (only TBM hdr): 0
[13:27:58.346] <TB2> INFO: TBM errors: 0
[13:27:58.346] <TB2> INFO: flawed TBM headers: 0
[13:27:58.346] <TB2> INFO: flawed TBM trailers: 0
[13:27:58.346] <TB2> INFO: event ID mismatches: 0
[13:27:58.346] <TB2> INFO: ROC errors: 0
[13:27:58.346] <TB2> INFO: missing ROC header(s): 0
[13:27:58.346] <TB2> INFO: misplaced readback start: 0
[13:27:58.346] <TB2> INFO: Pixel decoding errors: 0
[13:27:58.346] <TB2> INFO: pixel data incomplete: 0
[13:27:58.346] <TB2> INFO: pixel address: 0
[13:27:58.346] <TB2> INFO: pulse height fill bit: 0
[13:27:58.346] <TB2> INFO: buffer corruption: 0
[13:27:58.346] <TB2> INFO: enter test to run
[13:27:58.346] <TB2> INFO: test: trim80 no parameter change
[13:27:58.346] <TB2> INFO: running: trim80
[13:27:58.348] <TB2> INFO: ######################################################################
[13:27:58.348] <TB2> INFO: PixTestTrim80::doTest()
[13:27:58.348] <TB2> INFO: ######################################################################
[13:27:58.349] <TB2> INFO: ----------------------------------------------------------------------
[13:27:58.349] <TB2> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[13:27:58.349] <TB2> INFO: ----------------------------------------------------------------------
[13:27:58.417] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:27:58.417] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:27:58.431] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:27:58.431] <TB2> INFO: run 1 of 1
[13:27:58.755] <TB2> INFO: Expecting 5025280 events.
[13:28:26.528] <TB2> INFO: 677272 events read in total (27181ms).
[13:28:53.471] <TB2> INFO: 1350056 events read in total (54124ms).
[13:29:20.655] <TB2> INFO: 2020464 events read in total (81308ms).
[13:29:48.173] <TB2> INFO: 2688704 events read in total (108826ms).
[13:30:15.132] <TB2> INFO: 3356496 events read in total (135786ms).
[13:30:42.585] <TB2> INFO: 4022784 events read in total (163238ms).
[13:31:09.948] <TB2> INFO: 4689176 events read in total (190601ms).
[13:31:23.732] <TB2> INFO: 5025280 events read in total (204385ms).
[13:31:23.814] <TB2> INFO: Test took 205383ms.
[13:31:47.563] <TB2> INFO: ROC 0 VthrComp = 81
[13:31:47.563] <TB2> INFO: ROC 1 VthrComp = 80
[13:31:47.563] <TB2> INFO: ROC 2 VthrComp = 77
[13:31:47.563] <TB2> INFO: ROC 3 VthrComp = 85
[13:31:47.564] <TB2> INFO: ROC 4 VthrComp = 78
[13:31:47.565] <TB2> INFO: ROC 5 VthrComp = 94
[13:31:47.565] <TB2> INFO: ROC 6 VthrComp = 72
[13:31:47.565] <TB2> INFO: ROC 7 VthrComp = 76
[13:31:47.565] <TB2> INFO: ROC 8 VthrComp = 82
[13:31:47.566] <TB2> INFO: ROC 9 VthrComp = 75
[13:31:47.566] <TB2> INFO: ROC 10 VthrComp = 79
[13:31:47.566] <TB2> INFO: ROC 11 VthrComp = 88
[13:31:47.566] <TB2> INFO: ROC 12 VthrComp = 73
[13:31:47.567] <TB2> INFO: ROC 13 VthrComp = 76
[13:31:47.568] <TB2> INFO: ROC 14 VthrComp = 67
[13:31:47.568] <TB2> INFO: ROC 15 VthrComp = 76
[13:31:47.894] <TB2> INFO: Expecting 41600 events.
[13:31:51.616] <TB2> INFO: 41600 events read in total (3130ms).
[13:31:51.617] <TB2> INFO: Test took 4047ms.
[13:31:51.630] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:31:51.630] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:31:51.644] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:31:51.644] <TB2> INFO: run 1 of 1
[13:31:51.931] <TB2> INFO: Expecting 5025280 events.
[13:32:20.536] <TB2> INFO: 687104 events read in total (28013ms).
[13:32:47.886] <TB2> INFO: 1373032 events read in total (55363ms).
[13:33:15.778] <TB2> INFO: 2057904 events read in total (83255ms).
[13:33:43.481] <TB2> INFO: 2739240 events read in total (110958ms).
[13:34:10.670] <TB2> INFO: 3416600 events read in total (138147ms).
[13:34:38.219] <TB2> INFO: 4091728 events read in total (165696ms).
[13:35:05.894] <TB2> INFO: 4764792 events read in total (193371ms).
[13:35:16.690] <TB2> INFO: 5025280 events read in total (204167ms).
[13:35:16.767] <TB2> INFO: Test took 205123ms.
[13:35:44.831] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 112.824 for pixel 16/76 mean/min/max = 93.3402/73.7828/112.898
[13:35:44.831] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 108.826 for pixel 12/79 mean/min/max = 92.2135/75.5761/108.851
[13:35:44.832] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 120.092 for pixel 3/79 mean/min/max = 98.1886/76.1468/120.23
[13:35:44.833] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 106.768 for pixel 19/72 mean/min/max = 90.9246/75.0762/106.773
[13:35:44.833] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 109.004 for pixel 0/71 mean/min/max = 93.815/78.6208/109.009
[13:35:44.834] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 109.388 for pixel 11/63 mean/min/max = 91.6542/73.8444/109.464
[13:35:44.834] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 109.395 for pixel 0/78 mean/min/max = 93.3232/77.2261/109.42
[13:35:44.835] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 107.783 for pixel 15/77 mean/min/max = 93.0428/78.1495/107.936
[13:35:44.836] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 111 for pixel 0/32 mean/min/max = 92.4116/73.8154/111.008
[13:35:44.836] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 108.265 for pixel 0/9 mean/min/max = 93.2515/78.2076/108.295
[13:35:44.837] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 110.606 for pixel 0/11 mean/min/max = 94.0974/77.5795/110.615
[13:35:44.837] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 108.266 for pixel 1/5 mean/min/max = 92.4937/76.7143/108.273
[13:35:44.838] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 106.343 for pixel 51/67 mean/min/max = 91.8385/77.3093/106.368
[13:35:44.838] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 107.972 for pixel 23/18 mean/min/max = 93.6081/79.0157/108.201
[13:35:44.839] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 107.436 for pixel 11/73 mean/min/max = 90.8035/73.8238/107.783
[13:35:44.839] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 109.022 for pixel 51/33 mean/min/max = 94.0715/79.1188/109.024
[13:35:44.840] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:35:44.928] <TB2> INFO: Expecting 411648 events.
[13:35:54.340] <TB2> INFO: 411648 events read in total (8809ms).
[13:35:54.348] <TB2> INFO: Expecting 411648 events.
[13:36:03.655] <TB2> INFO: 411648 events read in total (8904ms).
[13:36:03.666] <TB2> INFO: Expecting 411648 events.
[13:36:13.046] <TB2> INFO: 411648 events read in total (8977ms).
[13:36:13.060] <TB2> INFO: Expecting 411648 events.
[13:36:22.441] <TB2> INFO: 411648 events read in total (8978ms).
[13:36:22.457] <TB2> INFO: Expecting 411648 events.
[13:36:31.819] <TB2> INFO: 411648 events read in total (8959ms).
[13:36:31.844] <TB2> INFO: Expecting 411648 events.
[13:36:41.222] <TB2> INFO: 411648 events read in total (8975ms).
[13:36:41.244] <TB2> INFO: Expecting 411648 events.
[13:36:50.589] <TB2> INFO: 411648 events read in total (8942ms).
[13:36:50.614] <TB2> INFO: Expecting 411648 events.
[13:37:00.060] <TB2> INFO: 411648 events read in total (9043ms).
[13:37:00.087] <TB2> INFO: Expecting 411648 events.
[13:37:09.407] <TB2> INFO: 411648 events read in total (8917ms).
[13:37:09.438] <TB2> INFO: Expecting 411648 events.
[13:37:18.691] <TB2> INFO: 411648 events read in total (8850ms).
[13:37:18.738] <TB2> INFO: Expecting 411648 events.
[13:37:28.268] <TB2> INFO: 411648 events read in total (9127ms).
[13:37:28.318] <TB2> INFO: Expecting 411648 events.
[13:37:37.639] <TB2> INFO: 411648 events read in total (8918ms).
[13:37:37.711] <TB2> INFO: Expecting 411648 events.
[13:37:46.980] <TB2> INFO: 411648 events read in total (8866ms).
[13:37:47.022] <TB2> INFO: Expecting 411648 events.
[13:37:56.439] <TB2> INFO: 411648 events read in total (9014ms).
[13:37:56.494] <TB2> INFO: Expecting 411648 events.
[13:38:05.763] <TB2> INFO: 411648 events read in total (8866ms).
[13:38:05.847] <TB2> INFO: Expecting 411648 events.
[13:38:15.232] <TB2> INFO: 411648 events read in total (8981ms).
[13:38:15.314] <TB2> INFO: Test took 150474ms.
[13:38:16.913] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:38:16.926] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:38:16.926] <TB2> INFO: run 1 of 1
[13:38:17.162] <TB2> INFO: Expecting 5025280 events.
[13:38:45.537] <TB2> INFO: 671184 events read in total (27783ms).
[13:39:13.029] <TB2> INFO: 1340048 events read in total (55275ms).
[13:39:40.697] <TB2> INFO: 2008664 events read in total (82943ms).
[13:40:08.198] <TB2> INFO: 2673456 events read in total (110444ms).
[13:40:36.419] <TB2> INFO: 3332712 events read in total (138665ms).
[13:41:03.284] <TB2> INFO: 3990216 events read in total (165530ms).
[13:41:30.669] <TB2> INFO: 4645496 events read in total (192915ms).
[13:41:46.925] <TB2> INFO: 5025280 events read in total (209171ms).
[13:41:46.991] <TB2> INFO: Test took 210066ms.
[13:42:14.311] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 53.461079 .. 109.856078
[13:42:14.639] <TB2> INFO: Expecting 208000 events.
[13:42:24.988] <TB2> INFO: 208000 events read in total (9756ms).
[13:42:24.989] <TB2> INFO: Test took 10676ms.
[13:42:25.055] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 43 .. 119 (-1/-1) hits flags = 528 (plus default)
[13:42:25.068] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:42:25.068] <TB2> INFO: run 1 of 1
[13:42:25.346] <TB2> INFO: Expecting 2562560 events.
[13:42:53.638] <TB2> INFO: 666120 events read in total (27698ms).
[13:43:21.108] <TB2> INFO: 1332704 events read in total (55168ms).
[13:43:48.630] <TB2> INFO: 1993464 events read in total (82690ms).
[13:44:13.044] <TB2> INFO: 2562560 events read in total (107104ms).
[13:44:13.096] <TB2> INFO: Test took 108028ms.
[13:44:36.224] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 61.637934 .. 100.369751
[13:44:36.471] <TB2> INFO: Expecting 208000 events.
[13:44:46.379] <TB2> INFO: 208000 events read in total (9316ms).
[13:44:46.381] <TB2> INFO: Test took 10154ms.
[13:44:46.431] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 51 .. 110 (-1/-1) hits flags = 528 (plus default)
[13:44:46.444] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:44:46.444] <TB2> INFO: run 1 of 1
[13:44:46.725] <TB2> INFO: Expecting 1996800 events.
[13:45:15.635] <TB2> INFO: 664784 events read in total (28310ms).
[13:45:43.778] <TB2> INFO: 1329592 events read in total (56453ms).
[13:46:13.362] <TB2> INFO: 1993832 events read in total (86037ms).
[13:46:13.907] <TB2> INFO: 1996800 events read in total (86582ms).
[13:46:13.941] <TB2> INFO: Test took 87498ms.
[13:46:32.043] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 66.233725 .. 95.035680
[13:46:32.285] <TB2> INFO: Expecting 208000 events.
[13:46:42.116] <TB2> INFO: 208000 events read in total (9239ms).
[13:46:42.117] <TB2> INFO: Test took 10072ms.
[13:46:42.165] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 56 .. 105 (-1/-1) hits flags = 528 (plus default)
[13:46:42.178] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:46:42.179] <TB2> INFO: run 1 of 1
[13:46:42.458] <TB2> INFO: Expecting 1664000 events.
[13:47:11.128] <TB2> INFO: 665232 events read in total (28079ms).
[13:47:39.936] <TB2> INFO: 1330008 events read in total (56887ms).
[13:47:54.180] <TB2> INFO: 1664000 events read in total (71131ms).
[13:47:54.214] <TB2> INFO: Test took 72036ms.
[13:48:12.065] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 69.715005 .. 90.184450
[13:48:12.304] <TB2> INFO: Expecting 208000 events.
[13:48:22.012] <TB2> INFO: 208000 events read in total (9116ms).
[13:48:22.014] <TB2> INFO: Test took 9947ms.
[13:48:22.082] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 59 .. 100 (-1/-1) hits flags = 528 (plus default)
[13:48:22.096] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:48:22.096] <TB2> INFO: run 1 of 1
[13:48:22.375] <TB2> INFO: Expecting 1397760 events.
[13:48:51.664] <TB2> INFO: 674032 events read in total (28697ms).
[13:49:19.482] <TB2> INFO: 1347272 events read in total (56515ms).
[13:49:22.016] <TB2> INFO: 1397760 events read in total (59049ms).
[13:49:22.043] <TB2> INFO: Test took 59947ms.
[13:49:40.186] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[13:49:40.186] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[13:49:40.199] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:49:40.199] <TB2> INFO: run 1 of 1
[13:49:40.473] <TB2> INFO: Expecting 1364480 events.
[13:50:08.594] <TB2> INFO: 668448 events read in total (27529ms).
[13:50:36.944] <TB2> INFO: 1336544 events read in total (55879ms).
[13:50:38.542] <TB2> INFO: 1364480 events read in total (57477ms).
[13:50:38.577] <TB2> INFO: Test took 58378ms.
[13:50:57.982] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C0.dat
[13:50:57.982] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C1.dat
[13:50:57.982] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C2.dat
[13:50:57.982] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C3.dat
[13:50:57.982] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C4.dat
[13:50:57.982] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C5.dat
[13:50:57.982] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C6.dat
[13:50:57.982] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C7.dat
[13:50:57.982] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C8.dat
[13:50:57.982] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C9.dat
[13:50:57.982] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C10.dat
[13:50:57.983] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C11.dat
[13:50:57.983] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C12.dat
[13:50:57.983] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C13.dat
[13:50:57.983] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C14.dat
[13:50:57.983] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C15.dat
[13:50:57.983] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C0.dat
[13:50:57.988] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C1.dat
[13:50:57.992] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C2.dat
[13:50:57.997] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C3.dat
[13:50:57.002] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C4.dat
[13:50:58.007] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C5.dat
[13:50:58.011] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C6.dat
[13:50:58.016] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C7.dat
[13:50:58.021] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C8.dat
[13:50:58.025] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C9.dat
[13:50:58.030] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C10.dat
[13:50:58.035] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C11.dat
[13:50:58.040] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C12.dat
[13:50:58.044] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C13.dat
[13:50:58.049] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C14.dat
[13:50:58.054] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1102_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C15.dat
[13:50:58.058] <TB2> INFO: PixTestTrim80::trimTest() done
[13:50:58.058] <TB2> INFO: vtrim: 123 102 123 99 94 100 99 86 98 90 104 113 85 99 100 107
[13:50:58.059] <TB2> INFO: vthrcomp: 81 80 77 85 78 94 72 76 82 75 79 88 73 76 67 76
[13:50:58.059] <TB2> INFO: vcal mean: 79.97 80.00 79.98 80.00 80.03 79.96 80.00 80.01 79.98 79.96 80.00 79.97 79.99 80.02 79.97 79.99
[13:50:58.059] <TB2> INFO: vcal RMS: 0.82 0.72 0.82 0.75 0.71 0.82 0.72 0.70 0.76 0.73 0.71 0.72 0.69 0.73 0.73 0.70
[13:50:58.059] <TB2> INFO: bits mean: 10.02 9.95 8.98 10.09 8.64 9.91 9.64 8.67 9.40 8.72 9.00 9.52 9.37 9.28 10.22 8.70
[13:50:58.059] <TB2> INFO: bits RMS: 2.51 2.32 2.59 2.42 2.43 2.61 2.23 2.49 2.81 2.51 2.42 2.31 2.35 2.13 2.54 2.38
[13:50:58.065] <TB2> INFO: ----------------------------------------------------------------------
[13:50:58.065] <TB2> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:50:58.065] <TB2> INFO: ----------------------------------------------------------------------
[13:50:58.068] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:50:58.079] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:50:58.079] <TB2> INFO: run 1 of 1
[13:50:58.318] <TB2> INFO: Expecting 4160000 events.
[13:51:30.911] <TB2> INFO: 769150 events read in total (32002ms).
[13:52:02.559] <TB2> INFO: 1531790 events read in total (63650ms).
[13:52:34.505] <TB2> INFO: 2288715 events read in total (95596ms).
[13:53:06.556] <TB2> INFO: 3041535 events read in total (127647ms).
[13:53:38.497] <TB2> INFO: 3791550 events read in total (159588ms).
[13:53:54.406] <TB2> INFO: 4160000 events read in total (175497ms).
[13:53:54.476] <TB2> INFO: Test took 176396ms.
[13:54:20.931] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 224 (-1/-1) hits flags = 528 (plus default)
[13:54:20.944] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:54:20.944] <TB2> INFO: run 1 of 1
[13:54:21.181] <TB2> INFO: Expecting 4680000 events.
[13:54:53.100] <TB2> INFO: 713045 events read in total (31328ms).
[13:55:24.195] <TB2> INFO: 1421095 events read in total (62423ms).
[13:55:55.256] <TB2> INFO: 2127080 events read in total (93484ms).
[13:56:26.208] <TB2> INFO: 2829665 events read in total (124436ms).
[13:56:57.167] <TB2> INFO: 3529715 events read in total (155395ms).
[13:57:28.396] <TB2> INFO: 4228550 events read in total (186624ms).
[13:57:48.422] <TB2> INFO: 4680000 events read in total (206650ms).
[13:57:48.551] <TB2> INFO: Test took 207607ms.
[13:58:16.843] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[13:58:16.856] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:58:16.856] <TB2> INFO: run 1 of 1
[13:58:17.101] <TB2> INFO: Expecting 4472000 events.
[13:58:49.308] <TB2> INFO: 724730 events read in total (31616ms).
[13:59:20.727] <TB2> INFO: 1444080 events read in total (63035ms).
[13:59:52.402] <TB2> INFO: 2161010 events read in total (94710ms).
[14:00:23.003] <TB2> INFO: 2873570 events read in total (126311ms).
[14:00:55.803] <TB2> INFO: 3584095 events read in total (158111ms).
[14:01:26.903] <TB2> INFO: 4294560 events read in total (189211ms).
[14:01:35.290] <TB2> INFO: 4472000 events read in total (197598ms).
[14:01:35.407] <TB2> INFO: Test took 198552ms.
[14:02:01.222] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[14:02:01.235] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:02:01.235] <TB2> INFO: run 1 of 1
[14:02:01.472] <TB2> INFO: Expecting 4430400 events.
[14:02:33.413] <TB2> INFO: 727830 events read in total (31349ms).
[14:03:04.795] <TB2> INFO: 1450130 events read in total (62731ms).
[14:03:36.097] <TB2> INFO: 2169240 events read in total (94033ms).
[14:04:07.417] <TB2> INFO: 2884890 events read in total (125353ms).
[14:04:38.729] <TB2> INFO: 3598320 events read in total (156665ms).
[14:05:10.087] <TB2> INFO: 4311045 events read in total (188023ms).
[14:05:15.690] <TB2> INFO: 4430400 events read in total (193626ms).
[14:05:15.810] <TB2> INFO: Test took 194574ms.
[14:05:44.369] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[14:05:44.383] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:05:44.383] <TB2> INFO: run 1 of 1
[14:05:44.619] <TB2> INFO: Expecting 4430400 events.
[14:06:16.788] <TB2> INFO: 727910 events read in total (31577ms).
[14:06:48.147] <TB2> INFO: 1450475 events read in total (62936ms).
[14:07:19.341] <TB2> INFO: 2170240 events read in total (94130ms).
[14:07:52.127] <TB2> INFO: 2886025 events read in total (126916ms).
[14:08:23.341] <TB2> INFO: 3599610 events read in total (158130ms).
[14:08:53.621] <TB2> INFO: 4312885 events read in total (188410ms).
[14:08:58.848] <TB2> INFO: 4430400 events read in total (193637ms).
[14:08:59.004] <TB2> INFO: Test took 194621ms.
[14:09:22.582] <TB2> INFO: PixTestTrim80::trimBitTest() done
[14:09:22.583] <TB2> INFO: PixTestTrim80::doTest() done, duration: 2484 seconds
[14:09:23.205] <TB2> INFO: enter test to run
[14:09:23.205] <TB2> INFO: test: exit no parameter change
[14:09:23.396] <TB2> QUIET: Connection to board 149 closed.
[14:09:23.397] <TB2> INFO: pXar: this is the end, my friend