[10:29:17.804] <TB1> INFO: *** Welcome to pxar ***
[10:29:17.804] <TB1> INFO: *** Today: 2016/11/02
[10:29:17.811] <TB1> INFO: *** Version: c8ba-dirty
[10:29:17.811] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C15.dat
[10:29:17.811] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//tbmParameters_C1b.dat
[10:29:17.811] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//defaultMaskFile.dat
[10:29:17.811] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters_C15.dat
[10:29:17.873] <TB1> INFO: clk: 4
[10:29:17.873] <TB1> INFO: ctr: 4
[10:29:17.873] <TB1> INFO: sda: 19
[10:29:17.873] <TB1> INFO: tin: 9
[10:29:17.873] <TB1> INFO: level: 15
[10:29:17.873] <TB1> INFO: triggerdelay: 0
[10:29:17.874] <TB1> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[10:29:17.874] <TB1> INFO: Log level: INFO
[10:29:17.882] <TB1> INFO: Found DTB DTB_WXC03A
[10:29:17.893] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[10:29:17.895] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
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[10:29:17.897] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[10:29:19.454] <TB1> INFO: DUT info:
[10:29:19.454] <TB1> INFO: The DUT currently contains the following objects:
[10:29:19.454] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[10:29:19.454] <TB1> INFO: TBM Core alpha (0): 7 registers set
[10:29:19.454] <TB1> INFO: TBM Core beta (1): 7 registers set
[10:29:19.454] <TB1> INFO: TBM Core alpha (2): 7 registers set
[10:29:19.454] <TB1> INFO: TBM Core beta (3): 7 registers set
[10:29:19.454] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[10:29:19.454] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.455] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[10:29:19.856] <TB1> INFO: enter 'restricted' command line mode
[10:29:19.856] <TB1> INFO: enter test to run
[10:29:19.856] <TB1> INFO: test: pretest no parameter change
[10:29:19.856] <TB1> INFO: running: pretest
[10:29:19.860] <TB1> INFO: ######################################################################
[10:29:19.861] <TB1> INFO: PixTestPretest::doTest()
[10:29:19.861] <TB1> INFO: ######################################################################
[10:29:19.862] <TB1> INFO: ----------------------------------------------------------------------
[10:29:19.862] <TB1> INFO: PixTestPretest::programROC()
[10:29:19.862] <TB1> INFO: ----------------------------------------------------------------------
[10:29:37.876] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[10:29:37.876] <TB1> INFO: IA differences per ROC: 16.9 17.7 20.9 16.1 21.7 21.7 19.3 17.7 16.1 18.5 17.7 20.9 20.9 17.7 18.5 18.5
[10:29:37.945] <TB1> INFO: ----------------------------------------------------------------------
[10:29:37.945] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[10:29:37.945] <TB1> INFO: ----------------------------------------------------------------------
[10:29:59.242] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 390.7 mA = 24.4187 mA/ROC
[10:29:59.242] <TB1> INFO: i(loss) [mA/ROC]: 20.1 20.9 20.1 20.1 20.1 19.3 19.3 20.1 19.3 20.9 19.3 20.1 19.3 19.3 20.1 20.1
[10:29:59.275] <TB1> INFO: ----------------------------------------------------------------------
[10:29:59.275] <TB1> INFO: PixTestPretest::findTiming()
[10:29:59.275] <TB1> INFO: ----------------------------------------------------------------------
[10:29:59.275] <TB1> INFO: PixTestCmd::init()

[10:30:31.412] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[10:30:31.412] <TB1> INFO: (success/tries = 100/100), width = 3
[10:30:32.898] <TB1> INFO: ----------------------------------------------------------------------
[10:30:32.898] <TB1> INFO: PixTestPretest::findWorkingPixel()
[10:30:32.898] <TB1> INFO: ----------------------------------------------------------------------
[10:30:32.993] <TB1> INFO: Expecting 231680 events.
[10:30:42.977] <TB1> INFO: 231680 events read in total (9393ms).
[10:30:42.987] <TB1> INFO: Test took 10085ms.
[10:30:43.237] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[10:30:43.275] <TB1> INFO: ----------------------------------------------------------------------
[10:30:43.275] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[10:30:43.275] <TB1> INFO: ----------------------------------------------------------------------
[10:30:43.371] <TB1> INFO: Expecting 231680 events.
[10:30:53.333] <TB1> INFO: 231680 events read in total (9370ms).
[10:30:53.343] <TB1> INFO: Test took 10062ms.
[10:30:53.608] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[10:30:53.608] <TB1> INFO: CalDel: 94 92 102 81 86 97 90 97 94 119 129 114 73 102 111 101
[10:30:53.608] <TB1> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[10:30:53.616] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C0.dat
[10:30:53.616] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C1.dat
[10:30:53.616] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C2.dat
[10:30:53.616] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C3.dat
[10:30:53.616] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C4.dat
[10:30:53.616] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C5.dat
[10:30:53.616] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C6.dat
[10:30:53.616] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C7.dat
[10:30:53.616] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C8.dat
[10:30:53.616] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C9.dat
[10:30:53.617] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C10.dat
[10:30:53.617] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C11.dat
[10:30:53.617] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C12.dat
[10:30:53.617] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C13.dat
[10:30:53.617] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C14.dat
[10:30:53.617] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters_C15.dat
[10:30:53.617] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//tbmParameters_C0a.dat
[10:30:53.617] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//tbmParameters_C0b.dat
[10:30:53.617] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//tbmParameters_C1a.dat
[10:30:53.617] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//tbmParameters_C1b.dat
[10:30:53.617] <TB1> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[10:30:53.700] <TB1> INFO: enter test to run
[10:30:53.700] <TB1> INFO: test: FullTest no parameter change
[10:30:53.700] <TB1> INFO: running: fulltest
[10:30:53.700] <TB1> INFO: ######################################################################
[10:30:53.700] <TB1> INFO: PixTestFullTest::doTest()
[10:30:53.700] <TB1> INFO: ######################################################################
[10:30:53.701] <TB1> INFO: ######################################################################
[10:30:53.701] <TB1> INFO: PixTestAlive::doTest()
[10:30:53.701] <TB1> INFO: ######################################################################
[10:30:53.702] <TB1> INFO: ----------------------------------------------------------------------
[10:30:53.702] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:30:53.702] <TB1> INFO: ----------------------------------------------------------------------
[10:30:53.941] <TB1> INFO: Expecting 41600 events.
[10:30:57.611] <TB1> INFO: 41600 events read in total (3078ms).
[10:30:57.611] <TB1> INFO: Test took 3907ms.
[10:30:57.843] <TB1> INFO: PixTestAlive::aliveTest() done
[10:30:57.843] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
[10:30:57.844] <TB1> INFO: ----------------------------------------------------------------------
[10:30:57.844] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:30:57.844] <TB1> INFO: ----------------------------------------------------------------------
[10:30:58.088] <TB1> INFO: Expecting 41600 events.
[10:31:01.057] <TB1> INFO: 41600 events read in total (2377ms).
[10:31:01.057] <TB1> INFO: Test took 3211ms.
[10:31:01.058] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[10:31:01.300] <TB1> INFO: PixTestAlive::maskTest() done
[10:31:01.300] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:31:01.301] <TB1> INFO: ----------------------------------------------------------------------
[10:31:01.301] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:31:01.301] <TB1> INFO: ----------------------------------------------------------------------
[10:31:01.542] <TB1> INFO: Expecting 41600 events.
[10:31:05.088] <TB1> INFO: 41600 events read in total (2955ms).
[10:31:05.088] <TB1> INFO: Test took 3784ms.
[10:31:05.325] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[10:31:05.325] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:31:05.325] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[10:31:05.325] <TB1> INFO: Decoding statistics:
[10:31:05.325] <TB1> INFO: General information:
[10:31:05.325] <TB1> INFO: 16bit words read: 0
[10:31:05.325] <TB1> INFO: valid events total: 0
[10:31:05.325] <TB1> INFO: empty events: 0
[10:31:05.325] <TB1> INFO: valid events with pixels: 0
[10:31:05.325] <TB1> INFO: valid pixel hits: 0
[10:31:05.325] <TB1> INFO: Event errors: 0
[10:31:05.325] <TB1> INFO: start marker: 0
[10:31:05.325] <TB1> INFO: stop marker: 0
[10:31:05.325] <TB1> INFO: overflow: 0
[10:31:05.326] <TB1> INFO: invalid 5bit words: 0
[10:31:05.326] <TB1> INFO: invalid XOR eye diagram: 0
[10:31:05.326] <TB1> INFO: frame (failed synchr.): 0
[10:31:05.326] <TB1> INFO: idle data (no TBM trl): 0
[10:31:05.326] <TB1> INFO: no data (only TBM hdr): 0
[10:31:05.326] <TB1> INFO: TBM errors: 0
[10:31:05.326] <TB1> INFO: flawed TBM headers: 0
[10:31:05.326] <TB1> INFO: flawed TBM trailers: 0
[10:31:05.326] <TB1> INFO: event ID mismatches: 0
[10:31:05.326] <TB1> INFO: ROC errors: 0
[10:31:05.326] <TB1> INFO: missing ROC header(s): 0
[10:31:05.326] <TB1> INFO: misplaced readback start: 0
[10:31:05.326] <TB1> INFO: Pixel decoding errors: 0
[10:31:05.326] <TB1> INFO: pixel data incomplete: 0
[10:31:05.326] <TB1> INFO: pixel address: 0
[10:31:05.326] <TB1> INFO: pulse height fill bit: 0
[10:31:05.326] <TB1> INFO: buffer corruption: 0
[10:31:05.334] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C15.dat
[10:31:05.334] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[10:31:05.334] <TB1> INFO: ######################################################################
[10:31:05.334] <TB1> INFO: PixTestReadback::doTest()
[10:31:05.334] <TB1> INFO: ######################################################################
[10:31:05.335] <TB1> INFO: ----------------------------------------------------------------------
[10:31:05.335] <TB1> INFO: PixTestReadback::CalibrateVd()
[10:31:05.335] <TB1> INFO: ----------------------------------------------------------------------
[10:31:15.298] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C0.dat
[10:31:15.298] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C1.dat
[10:31:15.298] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C2.dat
[10:31:15.298] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C3.dat
[10:31:15.298] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C4.dat
[10:31:15.299] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C5.dat
[10:31:15.299] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C6.dat
[10:31:15.299] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C7.dat
[10:31:15.299] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C8.dat
[10:31:15.299] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C9.dat
[10:31:15.299] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C10.dat
[10:31:15.299] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C11.dat
[10:31:15.299] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C12.dat
[10:31:15.299] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C13.dat
[10:31:15.299] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C14.dat
[10:31:15.299] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C15.dat
[10:31:15.329] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:31:15.329] <TB1> INFO: ----------------------------------------------------------------------
[10:31:15.329] <TB1> INFO: PixTestReadback::CalibrateVa()
[10:31:15.329] <TB1> INFO: ----------------------------------------------------------------------
[10:31:25.260] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C0.dat
[10:31:25.260] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C1.dat
[10:31:25.260] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C2.dat
[10:31:25.261] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C3.dat
[10:31:25.261] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C4.dat
[10:31:25.261] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C5.dat
[10:31:25.261] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C6.dat
[10:31:25.261] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C7.dat
[10:31:25.261] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C8.dat
[10:31:25.261] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C9.dat
[10:31:25.261] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C10.dat
[10:31:25.261] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C11.dat
[10:31:25.261] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C12.dat
[10:31:25.261] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C13.dat
[10:31:25.261] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C14.dat
[10:31:25.261] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C15.dat
[10:31:25.289] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:31:25.289] <TB1> INFO: ----------------------------------------------------------------------
[10:31:25.289] <TB1> INFO: PixTestReadback::readbackVbg()
[10:31:25.289] <TB1> INFO: ----------------------------------------------------------------------
[10:31:32.958] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:31:32.958] <TB1> INFO: ----------------------------------------------------------------------
[10:31:32.958] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[10:31:32.958] <TB1> INFO: ----------------------------------------------------------------------
[10:31:32.958] <TB1> INFO: Vbg will be calibrated using Vd calibration
[10:31:32.958] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 154.5calibrated Vbg = 1.19074 :::*/*/*/*/
[10:31:32.958] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 158.1calibrated Vbg = 1.1839 :::*/*/*/*/
[10:31:32.959] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 155.7calibrated Vbg = 1.18433 :::*/*/*/*/
[10:31:32.959] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 163.5calibrated Vbg = 1.17822 :::*/*/*/*/
[10:31:32.959] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 149.7calibrated Vbg = 1.1847 :::*/*/*/*/
[10:31:32.959] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 156calibrated Vbg = 1.19256 :::*/*/*/*/
[10:31:32.959] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 153.7calibrated Vbg = 1.19182 :::*/*/*/*/
[10:31:32.959] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 164.7calibrated Vbg = 1.19484 :::*/*/*/*/
[10:31:32.959] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 156.5calibrated Vbg = 1.18806 :::*/*/*/*/
[10:31:32.959] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 151.6calibrated Vbg = 1.18509 :::*/*/*/*/
[10:31:32.959] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 159.4calibrated Vbg = 1.18018 :::*/*/*/*/
[10:31:32.959] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 159.2calibrated Vbg = 1.17431 :::*/*/*/*/
[10:31:32.959] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 150.7calibrated Vbg = 1.17868 :::*/*/*/*/
[10:31:32.959] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 153.9calibrated Vbg = 1.17935 :::*/*/*/*/
[10:31:32.959] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 158.5calibrated Vbg = 1.19219 :::*/*/*/*/
[10:31:32.959] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 152.6calibrated Vbg = 1.19149 :::*/*/*/*/
[10:31:32.962] <TB1> INFO: ----------------------------------------------------------------------
[10:31:32.962] <TB1> INFO: PixTestReadback::CalibrateIa()
[10:31:32.962] <TB1> INFO: ----------------------------------------------------------------------
[10:34:13.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C0.dat
[10:34:13.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C1.dat
[10:34:13.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C2.dat
[10:34:13.812] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C3.dat
[10:34:13.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C4.dat
[10:34:13.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C5.dat
[10:34:13.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C6.dat
[10:34:13.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C7.dat
[10:34:13.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C8.dat
[10:34:13.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C9.dat
[10:34:13.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C10.dat
[10:34:13.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C11.dat
[10:34:13.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C12.dat
[10:34:13.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C13.dat
[10:34:13.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C14.dat
[10:34:13.813] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//readbackCal_C15.dat
[10:34:13.845] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:34:13.847] <TB1> INFO: PixTestReadback::doTest() done
[10:34:13.847] <TB1> INFO: Decoding statistics:
[10:34:13.847] <TB1> INFO: General information:
[10:34:13.847] <TB1> INFO: 16bit words read: 1536
[10:34:13.847] <TB1> INFO: valid events total: 256
[10:34:13.848] <TB1> INFO: empty events: 256
[10:34:13.848] <TB1> INFO: valid events with pixels: 0
[10:34:13.848] <TB1> INFO: valid pixel hits: 0
[10:34:13.848] <TB1> INFO: Event errors: 0
[10:34:13.848] <TB1> INFO: start marker: 0
[10:34:13.848] <TB1> INFO: stop marker: 0
[10:34:13.848] <TB1> INFO: overflow: 0
[10:34:13.848] <TB1> INFO: invalid 5bit words: 0
[10:34:13.848] <TB1> INFO: invalid XOR eye diagram: 0
[10:34:13.848] <TB1> INFO: frame (failed synchr.): 0
[10:34:13.848] <TB1> INFO: idle data (no TBM trl): 0
[10:34:13.848] <TB1> INFO: no data (only TBM hdr): 0
[10:34:13.848] <TB1> INFO: TBM errors: 0
[10:34:13.848] <TB1> INFO: flawed TBM headers: 0
[10:34:13.848] <TB1> INFO: flawed TBM trailers: 0
[10:34:13.848] <TB1> INFO: event ID mismatches: 0
[10:34:13.848] <TB1> INFO: ROC errors: 0
[10:34:13.848] <TB1> INFO: missing ROC header(s): 0
[10:34:13.848] <TB1> INFO: misplaced readback start: 0
[10:34:13.848] <TB1> INFO: Pixel decoding errors: 0
[10:34:13.848] <TB1> INFO: pixel data incomplete: 0
[10:34:13.848] <TB1> INFO: pixel address: 0
[10:34:13.848] <TB1> INFO: pulse height fill bit: 0
[10:34:13.848] <TB1> INFO: buffer corruption: 0
[10:34:13.901] <TB1> INFO: ######################################################################
[10:34:13.901] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[10:34:13.901] <TB1> INFO: ######################################################################
[10:34:13.903] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[10:34:13.948] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[10:34:13.948] <TB1> INFO: run 1 of 1
[10:34:14.191] <TB1> INFO: Expecting 3120000 events.
[10:34:44.845] <TB1> INFO: 653055 events read in total (30062ms).
[10:35:14.856] <TB1> INFO: 1297445 events read in total (60073ms).











[10:35:44.500] <TB1> INFO: 1938215 events read in total (89717ms).











[10:36:14.164] <TB1> INFO: 2578900 events read in total (119381ms).











[10:36:39.476] <TB1> INFO: 3120000 events read in total (144693ms).
[10:36:39.550] <TB1> INFO: Test took 145601ms.
[10:37:08.360] <TB1> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 174 seconds
[10:37:08.361] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0
[10:37:08.361] <TB1> INFO: separation cut (per ROC): 106 104 108 103 102 103 105 102 91 97 91 100 106 91 94 97
[10:37:08.361] <TB1> INFO: Decoding statistics:
[10:37:08.361] <TB1> INFO: General information:
[10:37:08.361] <TB1> INFO: 16bit words read: 0
[10:37:08.361] <TB1> INFO: valid events total: 0
[10:37:08.361] <TB1> INFO: empty events: 0
[10:37:08.361] <TB1> INFO: valid events with pixels: 0
[10:37:08.361] <TB1> INFO: valid pixel hits: 0
[10:37:08.361] <TB1> INFO: Event errors: 0
[10:37:08.361] <TB1> INFO: start marker: 0
[10:37:08.361] <TB1> INFO: stop marker: 0
[10:37:08.361] <TB1> INFO: overflow: 0
[10:37:08.361] <TB1> INFO: invalid 5bit words: 0
[10:37:08.361] <TB1> INFO: invalid XOR eye diagram: 0
[10:37:08.361] <TB1> INFO: frame (failed synchr.): 0
[10:37:08.361] <TB1> INFO: idle data (no TBM trl): 0
[10:37:08.361] <TB1> INFO: no data (only TBM hdr): 0
[10:37:08.361] <TB1> INFO: TBM errors: 0
[10:37:08.361] <TB1> INFO: flawed TBM headers: 0
[10:37:08.361] <TB1> INFO: flawed TBM trailers: 0
[10:37:08.361] <TB1> INFO: event ID mismatches: 0
[10:37:08.361] <TB1> INFO: ROC errors: 0
[10:37:08.361] <TB1> INFO: missing ROC header(s): 0
[10:37:08.361] <TB1> INFO: misplaced readback start: 0
[10:37:08.361] <TB1> INFO: Pixel decoding errors: 0
[10:37:08.361] <TB1> INFO: pixel data incomplete: 0
[10:37:08.361] <TB1> INFO: pixel address: 0
[10:37:08.361] <TB1> INFO: pulse height fill bit: 0
[10:37:08.361] <TB1> INFO: buffer corruption: 0
[10:37:08.416] <TB1> INFO: ######################################################################
[10:37:08.416] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:37:08.416] <TB1> INFO: ######################################################################
[10:37:08.416] <TB1> INFO: ----------------------------------------------------------------------
[10:37:08.416] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:37:08.416] <TB1> INFO: ----------------------------------------------------------------------
[10:37:08.416] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[10:37:08.430] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[10:37:08.430] <TB1> INFO: run 1 of 1
[10:37:08.756] <TB1> INFO: Expecting 36608000 events.
[10:37:32.805] <TB1> INFO: 668750 events read in total (23458ms).
[10:37:55.742] <TB1> INFO: 1324550 events read in total (46395ms).
[10:38:18.810] <TB1> INFO: 1979850 events read in total (69463ms).
[10:38:41.964] <TB1> INFO: 2635600 events read in total (92617ms).
[10:39:05.013] <TB1> INFO: 3291150 events read in total (115666ms).
[10:39:28.194] <TB1> INFO: 3946900 events read in total (138847ms).
[10:39:51.285] <TB1> INFO: 4601250 events read in total (161938ms).
[10:40:14.210] <TB1> INFO: 5258500 events read in total (184863ms).
[10:40:37.109] <TB1> INFO: 5912900 events read in total (207762ms).
[10:41:00.321] <TB1> INFO: 6568750 events read in total (230974ms).
[10:41:23.429] <TB1> INFO: 7223150 events read in total (254082ms).
[10:41:46.380] <TB1> INFO: 7876550 events read in total (277033ms).
[10:42:09.193] <TB1> INFO: 8530200 events read in total (299846ms).
[10:42:32.246] <TB1> INFO: 9184400 events read in total (322899ms).
[10:42:55.062] <TB1> INFO: 9838250 events read in total (345715ms).
[10:43:17.883] <TB1> INFO: 10494300 events read in total (368536ms).
[10:43:40.633] <TB1> INFO: 11147850 events read in total (391286ms).
[10:44:03.458] <TB1> INFO: 11801650 events read in total (414111ms).
[10:44:26.322] <TB1> INFO: 12456200 events read in total (436975ms).
[10:44:49.105] <TB1> INFO: 13108150 events read in total (459758ms).
[10:45:11.894] <TB1> INFO: 13759450 events read in total (482547ms).
[10:45:34.816] <TB1> INFO: 14411850 events read in total (505469ms).
[10:45:57.655] <TB1> INFO: 15064200 events read in total (528308ms).
[10:46:20.313] <TB1> INFO: 15718000 events read in total (550966ms).
[10:46:43.107] <TB1> INFO: 16371650 events read in total (573760ms).
[10:47:05.894] <TB1> INFO: 17024000 events read in total (596547ms).
[10:47:28.687] <TB1> INFO: 17676200 events read in total (619340ms).
[10:47:51.446] <TB1> INFO: 18327400 events read in total (642099ms).
[10:48:14.037] <TB1> INFO: 18975600 events read in total (664690ms).
[10:48:36.525] <TB1> INFO: 19622200 events read in total (687178ms).
[10:48:59.483] <TB1> INFO: 20271950 events read in total (710136ms).
[10:49:22.204] <TB1> INFO: 20920450 events read in total (732857ms).
[10:49:44.968] <TB1> INFO: 21568750 events read in total (755621ms).
[10:50:07.775] <TB1> INFO: 22217800 events read in total (778428ms).
[10:50:30.333] <TB1> INFO: 22865800 events read in total (800986ms).
[10:50:52.881] <TB1> INFO: 23512350 events read in total (823534ms).
[10:51:15.489] <TB1> INFO: 24161700 events read in total (846142ms).
[10:51:38.204] <TB1> INFO: 24811300 events read in total (868857ms).
[10:52:00.860] <TB1> INFO: 25458500 events read in total (891513ms).
[10:52:23.831] <TB1> INFO: 26108200 events read in total (914484ms).
[10:52:46.628] <TB1> INFO: 26758150 events read in total (937281ms).
[10:53:09.129] <TB1> INFO: 27404800 events read in total (959782ms).
[10:53:31.539] <TB1> INFO: 28051500 events read in total (982192ms).
[10:53:54.007] <TB1> INFO: 28698950 events read in total (1004660ms).
[10:54:16.322] <TB1> INFO: 29347600 events read in total (1026975ms).
[10:54:38.832] <TB1> INFO: 29995900 events read in total (1049485ms).
[10:55:01.384] <TB1> INFO: 30641950 events read in total (1072037ms).
[10:55:23.835] <TB1> INFO: 31290800 events read in total (1094488ms).
[10:55:46.362] <TB1> INFO: 31939500 events read in total (1117015ms).
[10:56:09.414] <TB1> INFO: 32586550 events read in total (1140067ms).
[10:56:32.003] <TB1> INFO: 33236600 events read in total (1162656ms).
[10:56:54.601] <TB1> INFO: 33884550 events read in total (1185254ms).
[10:57:17.371] <TB1> INFO: 34533850 events read in total (1208024ms).
[10:57:39.958] <TB1> INFO: 35181300 events read in total (1230611ms).
[10:58:02.642] <TB1> INFO: 35830550 events read in total (1253295ms).
[10:58:25.615] <TB1> INFO: 36488650 events read in total (1276268ms).
[10:58:30.046] <TB1> INFO: 36608000 events read in total (1280699ms).
[10:58:30.128] <TB1> INFO: Test took 1281698ms.
[10:58:30.690] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:32.625] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:34.199] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:35.746] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:37.310] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:38.811] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:40.298] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:41.863] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:43.306] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:44.811] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:46.480] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:47.950] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:49.623] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:51.630] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:53.085] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:54.822] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:58:56.415] <TB1> INFO: PixTestScurves::scurves() done
[10:58:56.415] <TB1> INFO: Vcal mean: 112.61 113.56 114.24 109.10 100.91 109.86 112.44 113.74 105.89 110.15 113.47 108.77 113.05 99.37 111.45 108.18
[10:58:56.415] <TB1> INFO: Vcal RMS: 5.53 4.89 6.02 5.00 5.39 4.60 5.17 5.27 4.93 5.29 6.85 4.94 5.21 4.70 5.15 5.48
[10:58:56.415] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1308 seconds
[10:58:56.415] <TB1> INFO: Decoding statistics:
[10:58:56.415] <TB1> INFO: General information:
[10:58:56.415] <TB1> INFO: 16bit words read: 0
[10:58:56.415] <TB1> INFO: valid events total: 0
[10:58:56.415] <TB1> INFO: empty events: 0
[10:58:56.415] <TB1> INFO: valid events with pixels: 0
[10:58:56.415] <TB1> INFO: valid pixel hits: 0
[10:58:56.415] <TB1> INFO: Event errors: 0
[10:58:56.415] <TB1> INFO: start marker: 0
[10:58:56.415] <TB1> INFO: stop marker: 0
[10:58:56.415] <TB1> INFO: overflow: 0
[10:58:56.415] <TB1> INFO: invalid 5bit words: 0
[10:58:56.415] <TB1> INFO: invalid XOR eye diagram: 0
[10:58:56.415] <TB1> INFO: frame (failed synchr.): 0
[10:58:56.415] <TB1> INFO: idle data (no TBM trl): 0
[10:58:56.415] <TB1> INFO: no data (only TBM hdr): 0
[10:58:56.415] <TB1> INFO: TBM errors: 0
[10:58:56.415] <TB1> INFO: flawed TBM headers: 0
[10:58:56.415] <TB1> INFO: flawed TBM trailers: 0
[10:58:56.415] <TB1> INFO: event ID mismatches: 0
[10:58:56.415] <TB1> INFO: ROC errors: 0
[10:58:56.415] <TB1> INFO: missing ROC header(s): 0
[10:58:56.415] <TB1> INFO: misplaced readback start: 0
[10:58:56.415] <TB1> INFO: Pixel decoding errors: 0
[10:58:56.415] <TB1> INFO: pixel data incomplete: 0
[10:58:56.415] <TB1> INFO: pixel address: 0
[10:58:56.415] <TB1> INFO: pulse height fill bit: 0
[10:58:56.415] <TB1> INFO: buffer corruption: 0
[10:58:56.493] <TB1> INFO: ######################################################################
[10:58:56.493] <TB1> INFO: PixTestTrim::doTest()
[10:58:56.493] <TB1> INFO: ######################################################################
[10:58:56.494] <TB1> INFO: ----------------------------------------------------------------------
[10:58:56.494] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[10:58:56.494] <TB1> INFO: ----------------------------------------------------------------------
[10:58:56.538] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[10:58:56.538] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:58:56.553] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:58:56.553] <TB1> INFO: run 1 of 1
[10:58:56.798] <TB1> INFO: Expecting 5025280 events.
[10:59:27.220] <TB1> INFO: 814872 events read in total (29819ms).
[10:59:57.165] <TB1> INFO: 1627136 events read in total (59765ms).
[11:00:26.856] <TB1> INFO: 2436912 events read in total (89456ms).
[11:00:56.708] <TB1> INFO: 3241496 events read in total (119307ms).
[11:01:26.827] <TB1> INFO: 4044592 events read in total (149426ms).
[11:01:56.993] <TB1> INFO: 4846344 events read in total (179592ms).
[11:02:03.897] <TB1> INFO: 5025280 events read in total (186496ms).
[11:02:03.969] <TB1> INFO: Test took 187415ms.
[11:02:21.278] <TB1> INFO: ROC 0 VthrComp = 119
[11:02:21.278] <TB1> INFO: ROC 1 VthrComp = 124
[11:02:21.278] <TB1> INFO: ROC 2 VthrComp = 123
[11:02:21.278] <TB1> INFO: ROC 3 VthrComp = 117
[11:02:21.278] <TB1> INFO: ROC 4 VthrComp = 113
[11:02:21.278] <TB1> INFO: ROC 5 VthrComp = 121
[11:02:21.279] <TB1> INFO: ROC 6 VthrComp = 122
[11:02:21.279] <TB1> INFO: ROC 7 VthrComp = 117
[11:02:21.279] <TB1> INFO: ROC 8 VthrComp = 107
[11:02:21.279] <TB1> INFO: ROC 9 VthrComp = 116
[11:02:21.279] <TB1> INFO: ROC 10 VthrComp = 113
[11:02:21.279] <TB1> INFO: ROC 11 VthrComp = 120
[11:02:21.279] <TB1> INFO: ROC 12 VthrComp = 128
[11:02:21.279] <TB1> INFO: ROC 13 VthrComp = 107
[11:02:21.279] <TB1> INFO: ROC 14 VthrComp = 115
[11:02:21.279] <TB1> INFO: ROC 15 VthrComp = 118
[11:02:21.549] <TB1> INFO: Expecting 41600 events.
[11:02:25.258] <TB1> INFO: 41600 events read in total (3117ms).
[11:02:25.259] <TB1> INFO: Test took 3978ms.
[11:02:25.272] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[11:02:25.272] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:02:25.287] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:02:25.287] <TB1> INFO: run 1 of 1
[11:02:25.565] <TB1> INFO: Expecting 5025280 events.
[11:02:51.606] <TB1> INFO: 590416 events read in total (25449ms).
[11:03:17.440] <TB1> INFO: 1178984 events read in total (51283ms).
[11:03:42.964] <TB1> INFO: 1767864 events read in total (76807ms).
[11:04:09.372] <TB1> INFO: 2356232 events read in total (103215ms).
[11:04:35.305] <TB1> INFO: 2942664 events read in total (129148ms).
[11:05:01.192] <TB1> INFO: 3528048 events read in total (155035ms).
[11:05:26.970] <TB1> INFO: 4112704 events read in total (180813ms).
[11:05:53.160] <TB1> INFO: 4696744 events read in total (207003ms).
[11:06:08.107] <TB1> INFO: 5025280 events read in total (221950ms).
[11:06:08.207] <TB1> INFO: Test took 222920ms.
[11:06:32.765] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 59.0835 for pixel 42/74 mean/min/max = 45.3708/31.4956/59.2459
[11:06:32.765] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 57.3384 for pixel 7/79 mean/min/max = 44.9226/32.2508/57.5944
[11:06:32.766] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 61.2064 for pixel 28/77 mean/min/max = 46.4701/31.616/61.3242
[11:06:32.766] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 57.4396 for pixel 0/2 mean/min/max = 44.6/31.7124/57.4875
[11:06:32.767] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 58.0453 for pixel 8/23 mean/min/max = 45.1227/32.1039/58.1415
[11:06:32.767] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 56.9292 for pixel 21/6 mean/min/max = 45.3055/33.4867/57.1243
[11:06:32.768] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 58.0319 for pixel 16/8 mean/min/max = 44.894/31.6247/58.1634
[11:06:32.768] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 60.62 for pixel 18/1 mean/min/max = 46.2042/31.6226/60.7858
[11:06:32.768] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 62.5243 for pixel 20/3 mean/min/max = 48.3968/34.1297/62.6638
[11:06:32.769] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 61.6908 for pixel 13/0 mean/min/max = 46.5281/31.2291/61.827
[11:06:32.769] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 63.7377 for pixel 15/5 mean/min/max = 47.2873/30.7265/63.8481
[11:06:32.770] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 58.6994 for pixel 2/41 mean/min/max = 45.4589/31.951/58.9668
[11:06:32.770] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 57.928 for pixel 23/79 mean/min/max = 44.6646/31.2944/58.0347
[11:06:32.771] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 58.3598 for pixel 0/13 mean/min/max = 46.4424/34.241/58.6438
[11:06:32.771] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 61.1329 for pixel 29/7 mean/min/max = 46.2622/31.3687/61.1557
[11:06:32.771] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 58.7275 for pixel 0/46 mean/min/max = 44.8992/30.992/58.8065
[11:06:32.772] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:06:32.861] <TB1> INFO: Expecting 411648 events.
[11:06:42.098] <TB1> INFO: 411648 events read in total (8646ms).
[11:06:42.105] <TB1> INFO: Expecting 411648 events.
[11:06:51.359] <TB1> INFO: 411648 events read in total (8851ms).
[11:06:51.370] <TB1> INFO: Expecting 411648 events.
[11:07:00.495] <TB1> INFO: 411648 events read in total (8722ms).
[11:07:00.511] <TB1> INFO: Expecting 411648 events.
[11:07:09.733] <TB1> INFO: 411648 events read in total (8819ms).
[11:07:09.749] <TB1> INFO: Expecting 411648 events.
[11:07:19.108] <TB1> INFO: 411648 events read in total (8956ms).
[11:07:19.128] <TB1> INFO: Expecting 411648 events.
[11:07:28.535] <TB1> INFO: 411648 events read in total (9004ms).
[11:07:28.563] <TB1> INFO: Expecting 411648 events.
[11:07:37.936] <TB1> INFO: 411648 events read in total (8970ms).
[11:07:37.971] <TB1> INFO: Expecting 411648 events.
[11:07:47.418] <TB1> INFO: 411648 events read in total (9044ms).
[11:07:47.446] <TB1> INFO: Expecting 411648 events.
[11:07:56.794] <TB1> INFO: 411648 events read in total (8945ms).
[11:07:56.825] <TB1> INFO: Expecting 411648 events.
[11:08:06.261] <TB1> INFO: 411648 events read in total (9033ms).
[11:08:06.296] <TB1> INFO: Expecting 411648 events.
[11:08:15.693] <TB1> INFO: 411648 events read in total (8994ms).
[11:08:15.729] <TB1> INFO: Expecting 411648 events.
[11:08:25.051] <TB1> INFO: 411648 events read in total (8915ms).
[11:08:25.098] <TB1> INFO: Expecting 411648 events.
[11:08:34.537] <TB1> INFO: 411648 events read in total (9036ms).
[11:08:34.579] <TB1> INFO: Expecting 411648 events.
[11:08:43.864] <TB1> INFO: 411648 events read in total (8882ms).
[11:08:43.918] <TB1> INFO: Expecting 411648 events.
[11:08:53.369] <TB1> INFO: 411648 events read in total (9048ms).
[11:08:53.420] <TB1> INFO: Expecting 411648 events.
[11:09:02.667] <TB1> INFO: 411648 events read in total (8844ms).
[11:09:02.825] <TB1> INFO: Test took 150053ms.
[11:09:03.725] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[11:09:03.739] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:09:03.739] <TB1> INFO: run 1 of 1
[11:09:03.974] <TB1> INFO: Expecting 5025280 events.
[11:09:30.444] <TB1> INFO: 585112 events read in total (25878ms).
[11:09:56.323] <TB1> INFO: 1169896 events read in total (51757ms).
[11:10:22.757] <TB1> INFO: 1754272 events read in total (78191ms).
[11:10:49.011] <TB1> INFO: 2335968 events read in total (104445ms).
[11:11:14.894] <TB1> INFO: 2916880 events read in total (130328ms).
[11:11:40.967] <TB1> INFO: 3498200 events read in total (156401ms).
[11:12:06.794] <TB1> INFO: 4079056 events read in total (182228ms).
[11:12:32.931] <TB1> INFO: 4659408 events read in total (208365ms).
[11:12:49.928] <TB1> INFO: 5025280 events read in total (225363ms).
[11:12:50.127] <TB1> INFO: Test took 226390ms.
[11:13:11.960] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 2.656093 .. 145.478473
[11:13:12.203] <TB1> INFO: Expecting 208000 events.
[11:13:21.863] <TB1> INFO: 208000 events read in total (9068ms).
[11:13:21.864] <TB1> INFO: Test took 9903ms.
[11:13:21.914] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 155 (-1/-1) hits flags = 528 (plus default)
[11:13:21.928] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:13:21.928] <TB1> INFO: run 1 of 1
[11:13:22.206] <TB1> INFO: Expecting 5125120 events.
[11:13:48.253] <TB1> INFO: 583240 events read in total (25456ms).
[11:14:13.703] <TB1> INFO: 1165960 events read in total (50906ms).
[11:14:39.572] <TB1> INFO: 1748928 events read in total (76775ms).
[11:15:05.261] <TB1> INFO: 2331760 events read in total (102464ms).
[11:15:30.875] <TB1> INFO: 2914616 events read in total (128078ms).
[11:15:56.491] <TB1> INFO: 3496992 events read in total (153694ms).
[11:16:22.196] <TB1> INFO: 4079192 events read in total (179399ms).
[11:16:48.038] <TB1> INFO: 4661024 events read in total (205242ms).
[11:17:09.036] <TB1> INFO: 5125120 events read in total (226239ms).
[11:17:09.126] <TB1> INFO: Test took 227199ms.
[11:17:32.892] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.277345 .. 48.784981
[11:17:33.129] <TB1> INFO: Expecting 208000 events.
[11:17:43.010] <TB1> INFO: 208000 events read in total (9290ms).
[11:17:43.011] <TB1> INFO: Test took 10117ms.
[11:17:43.082] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 58 (-1/-1) hits flags = 528 (plus default)
[11:17:43.096] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:17:43.096] <TB1> INFO: run 1 of 1
[11:17:43.374] <TB1> INFO: Expecting 1397760 events.
[11:18:11.741] <TB1> INFO: 648040 events read in total (27775ms).
[11:18:38.554] <TB1> INFO: 1293344 events read in total (54588ms).
[11:18:43.252] <TB1> INFO: 1397760 events read in total (59286ms).
[11:18:43.282] <TB1> INFO: Test took 60187ms.
[11:18:56.947] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 25.127306 .. 46.655431
[11:18:57.186] <TB1> INFO: Expecting 208000 events.
[11:19:07.114] <TB1> INFO: 208000 events read in total (9336ms).
[11:19:07.116] <TB1> INFO: Test took 10167ms.
[11:19:07.185] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 56 (-1/-1) hits flags = 528 (plus default)
[11:19:07.200] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:19:07.200] <TB1> INFO: run 1 of 1
[11:19:07.478] <TB1> INFO: Expecting 1397760 events.
[11:19:36.043] <TB1> INFO: 663800 events read in total (27973ms).
[11:20:03.729] <TB1> INFO: 1326224 events read in total (55660ms).
[11:20:07.122] <TB1> INFO: 1397760 events read in total (59052ms).
[11:20:07.159] <TB1> INFO: Test took 59959ms.
[11:20:19.619] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 25.242332 .. 46.655431
[11:20:19.859] <TB1> INFO: Expecting 208000 events.
[11:20:29.477] <TB1> INFO: 208000 events read in total (9027ms).
[11:20:29.478] <TB1> INFO: Test took 9857ms.
[11:20:29.524] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 56 (-1/-1) hits flags = 528 (plus default)
[11:20:29.538] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:20:29.538] <TB1> INFO: run 1 of 1
[11:20:29.817] <TB1> INFO: Expecting 1397760 events.
[11:20:57.786] <TB1> INFO: 663128 events read in total (27377ms).
[11:21:25.601] <TB1> INFO: 1325912 events read in total (55192ms).
[11:21:28.959] <TB1> INFO: 1397760 events read in total (58550ms).
[11:21:28.990] <TB1> INFO: Test took 59452ms.
[11:21:45.613] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[11:21:45.613] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[11:21:45.627] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:21:45.627] <TB1> INFO: run 1 of 1
[11:21:45.863] <TB1> INFO: Expecting 1364480 events.
[11:22:14.521] <TB1> INFO: 667160 events read in total (28067ms).
[11:22:41.869] <TB1> INFO: 1333368 events read in total (55416ms).
[11:22:43.559] <TB1> INFO: 1364480 events read in total (57105ms).
[11:22:43.590] <TB1> INFO: Test took 57963ms.
[11:22:56.956] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C0.dat
[11:22:56.956] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C1.dat
[11:22:56.956] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C2.dat
[11:22:56.956] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C3.dat
[11:22:56.956] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C4.dat
[11:22:56.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C5.dat
[11:22:56.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C6.dat
[11:22:56.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C7.dat
[11:22:56.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C8.dat
[11:22:56.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C9.dat
[11:22:56.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C10.dat
[11:22:56.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C11.dat
[11:22:56.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C12.dat
[11:22:56.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C13.dat
[11:22:56.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C14.dat
[11:22:56.957] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C15.dat
[11:22:56.958] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C0.dat
[11:22:56.965] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C1.dat
[11:22:56.972] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C2.dat
[11:22:56.979] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C3.dat
[11:22:56.986] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C4.dat
[11:22:56.993] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C5.dat
[11:22:56.000] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C6.dat
[11:22:57.007] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C7.dat
[11:22:57.014] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C8.dat
[11:22:57.021] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C9.dat
[11:22:57.028] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C10.dat
[11:22:57.035] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C11.dat
[11:22:57.042] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C12.dat
[11:22:57.049] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C13.dat
[11:22:57.056] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C14.dat
[11:22:57.063] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//trimParameters35_C15.dat
[11:22:57.070] <TB1> INFO: PixTestTrim::trimTest() done
[11:22:57.070] <TB1> INFO: vtrim: 119 118 135 105 140 129 128 151 142 126 130 128 133 133 141 130
[11:22:57.070] <TB1> INFO: vthrcomp: 119 124 123 117 113 121 122 117 107 116 113 120 128 107 115 118
[11:22:57.070] <TB1> INFO: vcal mean: 34.95 34.98 34.92 34.92 34.95 35.01 34.95 34.96 35.01 34.99 35.01 34.97 34.93 34.96 34.99 34.92
[11:22:57.070] <TB1> INFO: vcal RMS: 1.00 0.99 1.05 0.94 1.07 0.94 0.99 1.09 0.99 1.08 1.12 0.99 1.02 0.95 1.06 1.04
[11:22:57.070] <TB1> INFO: bits mean: 9.67 8.98 9.59 9.14 9.62 9.42 9.73 10.09 9.01 9.54 9.61 9.50 9.77 9.06 9.69 9.57
[11:22:57.070] <TB1> INFO: bits RMS: 2.70 2.92 2.60 2.97 2.65 2.61 2.72 2.49 2.49 2.71 2.62 2.73 2.76 2.57 2.61 2.87
[11:22:57.078] <TB1> INFO: ----------------------------------------------------------------------
[11:22:57.078] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[11:22:57.078] <TB1> INFO: ----------------------------------------------------------------------
[11:22:57.081] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[11:22:57.095] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:22:57.095] <TB1> INFO: run 1 of 1
[11:22:57.419] <TB1> INFO: Expecting 4160000 events.
[11:23:29.442] <TB1> INFO: 732850 events read in total (31431ms).
[11:24:00.647] <TB1> INFO: 1461840 events read in total (62636ms).
[11:24:31.961] <TB1> INFO: 2186430 events read in total (93950ms).
[11:25:03.104] <TB1> INFO: 2906585 events read in total (125093ms).
[11:25:34.072] <TB1> INFO: 3626365 events read in total (156061ms).
[11:25:57.650] <TB1> INFO: 4160000 events read in total (179639ms).
[11:25:57.752] <TB1> INFO: Test took 180658ms.
[11:26:28.634] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 194 (-1/-1) hits flags = 528 (plus default)
[11:26:28.648] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:26:28.648] <TB1> INFO: run 1 of 1
[11:26:28.899] <TB1> INFO: Expecting 4056000 events.
[11:27:00.784] <TB1> INFO: 717465 events read in total (31293ms).
[11:27:31.615] <TB1> INFO: 1430870 events read in total (62124ms).
[11:28:02.831] <TB1> INFO: 2140955 events read in total (93340ms).
[11:28:33.582] <TB1> INFO: 2847260 events read in total (124091ms).
[11:29:04.795] <TB1> INFO: 3553100 events read in total (155304ms).
[11:29:26.894] <TB1> INFO: 4056000 events read in total (177403ms).
[11:29:26.995] <TB1> INFO: Test took 178346ms.
[11:29:55.845] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 179 (-1/-1) hits flags = 528 (plus default)
[11:29:55.859] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:29:55.859] <TB1> INFO: run 1 of 1
[11:29:56.096] <TB1> INFO: Expecting 3744000 events.
[11:30:28.356] <TB1> INFO: 738990 events read in total (31668ms).
[11:30:59.661] <TB1> INFO: 1473250 events read in total (62973ms).
[11:31:31.146] <TB1> INFO: 2202980 events read in total (94458ms).
[11:32:02.543] <TB1> INFO: 2929370 events read in total (125855ms).
[11:32:34.381] <TB1> INFO: 3656195 events read in total (157693ms).
[11:32:38.429] <TB1> INFO: 3744000 events read in total (161741ms).
[11:32:38.510] <TB1> INFO: Test took 162651ms.
[11:33:05.507] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 181 (-1/-1) hits flags = 528 (plus default)
[11:33:05.520] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:33:05.520] <TB1> INFO: run 1 of 1
[11:33:05.769] <TB1> INFO: Expecting 3785600 events.
[11:33:38.189] <TB1> INFO: 736050 events read in total (31828ms).
[11:34:09.580] <TB1> INFO: 1467180 events read in total (63219ms).
[11:34:40.867] <TB1> INFO: 2194240 events read in total (94506ms).
[11:35:12.327] <TB1> INFO: 2917955 events read in total (125966ms).
[11:35:43.319] <TB1> INFO: 3641660 events read in total (156958ms).
[11:35:49.749] <TB1> INFO: 3785600 events read in total (163388ms).
[11:35:49.841] <TB1> INFO: Test took 164321ms.
[11:36:12.209] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 180 (-1/-1) hits flags = 528 (plus default)
[11:36:12.223] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:36:12.223] <TB1> INFO: run 1 of 1
[11:36:12.495] <TB1> INFO: Expecting 3764800 events.
[11:36:44.435] <TB1> INFO: 737510 events read in total (31349ms).
[11:37:15.807] <TB1> INFO: 1470185 events read in total (62721ms).
[11:37:48.015] <TB1> INFO: 2198565 events read in total (94929ms).
[11:38:20.087] <TB1> INFO: 2923615 events read in total (127001ms).
[11:38:52.417] <TB1> INFO: 3648845 events read in total (159331ms).
[11:38:57.936] <TB1> INFO: 3764800 events read in total (164850ms).
[11:38:58.023] <TB1> INFO: Test took 165800ms.
[11:39:23.895] <TB1> INFO: PixTestTrim::trimBitTest() done
[11:39:23.896] <TB1> INFO: PixTestTrim::doTest() done, duration: 2427 seconds
[11:39:23.896] <TB1> INFO: Decoding statistics:
[11:39:23.896] <TB1> INFO: General information:
[11:39:23.897] <TB1> INFO: 16bit words read: 0
[11:39:23.897] <TB1> INFO: valid events total: 0
[11:39:23.897] <TB1> INFO: empty events: 0
[11:39:23.897] <TB1> INFO: valid events with pixels: 0
[11:39:23.897] <TB1> INFO: valid pixel hits: 0
[11:39:23.897] <TB1> INFO: Event errors: 0
[11:39:23.897] <TB1> INFO: start marker: 0
[11:39:23.897] <TB1> INFO: stop marker: 0
[11:39:23.897] <TB1> INFO: overflow: 0
[11:39:23.897] <TB1> INFO: invalid 5bit words: 0
[11:39:23.897] <TB1> INFO: invalid XOR eye diagram: 0
[11:39:23.897] <TB1> INFO: frame (failed synchr.): 0
[11:39:23.897] <TB1> INFO: idle data (no TBM trl): 0
[11:39:23.897] <TB1> INFO: no data (only TBM hdr): 0
[11:39:23.897] <TB1> INFO: TBM errors: 0
[11:39:23.897] <TB1> INFO: flawed TBM headers: 0
[11:39:23.897] <TB1> INFO: flawed TBM trailers: 0
[11:39:23.897] <TB1> INFO: event ID mismatches: 0
[11:39:23.897] <TB1> INFO: ROC errors: 0
[11:39:23.897] <TB1> INFO: missing ROC header(s): 0
[11:39:23.897] <TB1> INFO: misplaced readback start: 0
[11:39:23.897] <TB1> INFO: Pixel decoding errors: 0
[11:39:23.897] <TB1> INFO: pixel data incomplete: 0
[11:39:23.897] <TB1> INFO: pixel address: 0
[11:39:23.897] <TB1> INFO: pulse height fill bit: 0
[11:39:23.897] <TB1> INFO: buffer corruption: 0
[11:39:24.572] <TB1> INFO: ######################################################################
[11:39:24.572] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[11:39:24.572] <TB1> INFO: ######################################################################
[11:39:24.817] <TB1> INFO: Expecting 41600 events.
[11:39:28.337] <TB1> INFO: 41600 events read in total (2928ms).
[11:39:28.338] <TB1> INFO: Test took 3764ms.
[11:39:28.782] <TB1> INFO: Expecting 41600 events.
[11:39:32.325] <TB1> INFO: 41600 events read in total (2951ms).
[11:39:32.325] <TB1> INFO: Test took 3782ms.
[11:39:32.615] <TB1> INFO: Expecting 41600 events.
[11:39:36.126] <TB1> INFO: 41600 events read in total (2920ms).
[11:39:36.127] <TB1> INFO: Test took 3777ms.
[11:39:36.416] <TB1> INFO: Expecting 41600 events.
[11:39:39.943] <TB1> INFO: 41600 events read in total (2935ms).
[11:39:39.945] <TB1> INFO: Test took 3794ms.
[11:39:40.236] <TB1> INFO: Expecting 41600 events.
[11:39:43.815] <TB1> INFO: 41600 events read in total (2987ms).
[11:39:43.816] <TB1> INFO: Test took 3845ms.
[11:39:44.167] <TB1> INFO: Expecting 41600 events.
[11:39:47.708] <TB1> INFO: 41600 events read in total (2950ms).
[11:39:47.709] <TB1> INFO: Test took 3865ms.
[11:39:47.001] <TB1> INFO: Expecting 41600 events.
[11:39:51.646] <TB1> INFO: 41600 events read in total (3053ms).
[11:39:51.648] <TB1> INFO: Test took 3915ms.
[11:39:51.953] <TB1> INFO: Expecting 41600 events.
[11:39:55.463] <TB1> INFO: 41600 events read in total (2918ms).
[11:39:55.464] <TB1> INFO: Test took 3791ms.
[11:39:55.757] <TB1> INFO: Expecting 41600 events.
[11:39:59.560] <TB1> INFO: 41600 events read in total (3212ms).
[11:39:59.561] <TB1> INFO: Test took 4073ms.
[11:39:59.869] <TB1> INFO: Expecting 41600 events.
[11:40:03.550] <TB1> INFO: 41600 events read in total (3090ms).
[11:40:03.551] <TB1> INFO: Test took 3965ms.
[11:40:03.865] <TB1> INFO: Expecting 41600 events.
[11:40:07.475] <TB1> INFO: 41600 events read in total (3018ms).
[11:40:07.476] <TB1> INFO: Test took 3898ms.
[11:40:07.780] <TB1> INFO: Expecting 41600 events.
[11:40:11.361] <TB1> INFO: 41600 events read in total (2990ms).
[11:40:11.362] <TB1> INFO: Test took 3862ms.
[11:40:11.657] <TB1> INFO: Expecting 41600 events.
[11:40:15.210] <TB1> INFO: 41600 events read in total (2962ms).
[11:40:15.211] <TB1> INFO: Test took 3824ms.
[11:40:15.502] <TB1> INFO: Expecting 41600 events.
[11:40:19.053] <TB1> INFO: 41600 events read in total (2959ms).
[11:40:19.054] <TB1> INFO: Test took 3816ms.
[11:40:19.346] <TB1> INFO: Expecting 41600 events.
[11:40:22.884] <TB1> INFO: 41600 events read in total (2947ms).
[11:40:22.885] <TB1> INFO: Test took 3804ms.
[11:40:23.177] <TB1> INFO: Expecting 41600 events.
[11:40:26.654] <TB1> INFO: 41600 events read in total (2886ms).
[11:40:26.655] <TB1> INFO: Test took 3743ms.
[11:40:26.944] <TB1> INFO: Expecting 41600 events.
[11:40:30.437] <TB1> INFO: 41600 events read in total (2901ms).
[11:40:30.438] <TB1> INFO: Test took 3759ms.
[11:40:30.729] <TB1> INFO: Expecting 41600 events.
[11:40:34.210] <TB1> INFO: 41600 events read in total (2890ms).
[11:40:34.211] <TB1> INFO: Test took 3747ms.
[11:40:34.550] <TB1> INFO: Expecting 41600 events.
[11:40:38.026] <TB1> INFO: 41600 events read in total (2885ms).
[11:40:38.027] <TB1> INFO: Test took 3792ms.
[11:40:38.317] <TB1> INFO: Expecting 41600 events.
[11:40:41.852] <TB1> INFO: 41600 events read in total (2944ms).
[11:40:41.853] <TB1> INFO: Test took 3801ms.
[11:40:42.148] <TB1> INFO: Expecting 41600 events.
[11:40:45.864] <TB1> INFO: 41600 events read in total (3125ms).
[11:40:45.864] <TB1> INFO: Test took 3984ms.
[11:40:46.156] <TB1> INFO: Expecting 41600 events.
[11:40:49.705] <TB1> INFO: 41600 events read in total (2958ms).
[11:40:49.706] <TB1> INFO: Test took 3817ms.
[11:40:49.995] <TB1> INFO: Expecting 41600 events.
[11:40:53.616] <TB1> INFO: 41600 events read in total (3029ms).
[11:40:53.617] <TB1> INFO: Test took 3887ms.
[11:40:53.951] <TB1> INFO: Expecting 41600 events.
[11:40:57.494] <TB1> INFO: 41600 events read in total (2952ms).
[11:40:57.495] <TB1> INFO: Test took 3850ms.
[11:40:57.784] <TB1> INFO: Expecting 41600 events.
[11:41:01.373] <TB1> INFO: 41600 events read in total (2997ms).
[11:41:01.374] <TB1> INFO: Test took 3855ms.
[11:41:01.666] <TB1> INFO: Expecting 41600 events.
[11:41:05.203] <TB1> INFO: 41600 events read in total (2945ms).
[11:41:05.204] <TB1> INFO: Test took 3803ms.
[11:41:05.512] <TB1> INFO: Expecting 41600 events.
[11:41:09.146] <TB1> INFO: 41600 events read in total (3042ms).
[11:41:09.147] <TB1> INFO: Test took 3919ms.
[11:41:09.437] <TB1> INFO: Expecting 41600 events.
[11:41:12.963] <TB1> INFO: 41600 events read in total (2935ms).
[11:41:12.963] <TB1> INFO: Test took 3792ms.
[11:41:13.252] <TB1> INFO: Expecting 41600 events.
[11:41:16.788] <TB1> INFO: 41600 events read in total (2944ms).
[11:41:16.789] <TB1> INFO: Test took 3802ms.
[11:41:17.095] <TB1> INFO: Expecting 41600 events.
[11:41:20.628] <TB1> INFO: 41600 events read in total (2941ms).
[11:41:20.629] <TB1> INFO: Test took 3815ms.
[11:41:20.919] <TB1> INFO: Expecting 41600 events.
[11:41:24.455] <TB1> INFO: 41600 events read in total (2944ms).
[11:41:24.456] <TB1> INFO: Test took 3801ms.
[11:41:24.752] <TB1> INFO: Expecting 2560 events.
[11:41:25.644] <TB1> INFO: 2560 events read in total (302ms).
[11:41:25.645] <TB1> INFO: Test took 1170ms.
[11:41:25.953] <TB1> INFO: Expecting 2560 events.
[11:41:26.848] <TB1> INFO: 2560 events read in total (303ms).
[11:41:26.848] <TB1> INFO: Test took 1203ms.
[11:41:27.156] <TB1> INFO: Expecting 2560 events.
[11:41:28.047] <TB1> INFO: 2560 events read in total (299ms).
[11:41:28.048] <TB1> INFO: Test took 1199ms.
[11:41:28.355] <TB1> INFO: Expecting 2560 events.
[11:41:29.243] <TB1> INFO: 2560 events read in total (296ms).
[11:41:29.244] <TB1> INFO: Test took 1196ms.
[11:41:29.550] <TB1> INFO: Expecting 2560 events.
[11:41:30.439] <TB1> INFO: 2560 events read in total (297ms).
[11:41:30.439] <TB1> INFO: Test took 1195ms.
[11:41:30.747] <TB1> INFO: Expecting 2560 events.
[11:41:31.636] <TB1> INFO: 2560 events read in total (297ms).
[11:41:31.637] <TB1> INFO: Test took 1197ms.
[11:41:31.944] <TB1> INFO: Expecting 2560 events.
[11:41:32.830] <TB1> INFO: 2560 events read in total (294ms).
[11:41:32.831] <TB1> INFO: Test took 1194ms.
[11:41:33.139] <TB1> INFO: Expecting 2560 events.
[11:41:34.022] <TB1> INFO: 2560 events read in total (292ms).
[11:41:34.022] <TB1> INFO: Test took 1191ms.
[11:41:34.331] <TB1> INFO: Expecting 2560 events.
[11:41:35.222] <TB1> INFO: 2560 events read in total (299ms).
[11:41:35.222] <TB1> INFO: Test took 1199ms.
[11:41:35.529] <TB1> INFO: Expecting 2560 events.
[11:41:36.408] <TB1> INFO: 2560 events read in total (287ms).
[11:41:36.409] <TB1> INFO: Test took 1186ms.
[11:41:36.716] <TB1> INFO: Expecting 2560 events.
[11:41:37.600] <TB1> INFO: 2560 events read in total (292ms).
[11:41:37.601] <TB1> INFO: Test took 1192ms.
[11:41:37.908] <TB1> INFO: Expecting 2560 events.
[11:41:38.802] <TB1> INFO: 2560 events read in total (302ms).
[11:41:38.802] <TB1> INFO: Test took 1200ms.
[11:41:39.110] <TB1> INFO: Expecting 2560 events.
[11:41:39.000] <TB1> INFO: 2560 events read in total (298ms).
[11:41:39.001] <TB1> INFO: Test took 1198ms.
[11:41:40.308] <TB1> INFO: Expecting 2560 events.
[11:41:41.193] <TB1> INFO: 2560 events read in total (293ms).
[11:41:41.193] <TB1> INFO: Test took 1191ms.
[11:41:41.501] <TB1> INFO: Expecting 2560 events.
[11:41:42.394] <TB1> INFO: 2560 events read in total (301ms).
[11:41:42.394] <TB1> INFO: Test took 1200ms.
[11:41:42.702] <TB1> INFO: Expecting 2560 events.
[11:41:43.595] <TB1> INFO: 2560 events read in total (302ms).
[11:41:43.595] <TB1> INFO: Test took 1200ms.
[11:41:43.598] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:41:43.905] <TB1> INFO: Expecting 655360 events.
[11:41:58.902] <TB1> INFO: 655360 events read in total (14405ms).
[11:41:58.921] <TB1> INFO: Expecting 655360 events.
[11:42:13.618] <TB1> INFO: 655360 events read in total (14294ms).
[11:42:13.637] <TB1> INFO: Expecting 655360 events.
[11:42:28.340] <TB1> INFO: 655360 events read in total (14300ms).
[11:42:28.363] <TB1> INFO: Expecting 655360 events.
[11:42:43.024] <TB1> INFO: 655360 events read in total (14258ms).
[11:42:43.061] <TB1> INFO: Expecting 655360 events.
[11:42:57.696] <TB1> INFO: 655360 events read in total (14232ms).
[11:42:57.737] <TB1> INFO: Expecting 655360 events.
[11:43:12.372] <TB1> INFO: 655360 events read in total (14232ms).
[11:43:12.421] <TB1> INFO: Expecting 655360 events.
[11:43:27.043] <TB1> INFO: 655360 events read in total (14219ms).
[11:43:27.095] <TB1> INFO: Expecting 655360 events.
[11:43:41.652] <TB1> INFO: 655360 events read in total (14154ms).
[11:43:41.707] <TB1> INFO: Expecting 655360 events.
[11:43:56.344] <TB1> INFO: 655360 events read in total (14234ms).
[11:43:56.399] <TB1> INFO: Expecting 655360 events.
[11:44:10.978] <TB1> INFO: 655360 events read in total (14176ms).
[11:44:11.065] <TB1> INFO: Expecting 655360 events.
[11:44:25.903] <TB1> INFO: 655360 events read in total (14435ms).
[11:44:25.984] <TB1> INFO: Expecting 655360 events.
[11:44:40.755] <TB1> INFO: 655360 events read in total (14368ms).
[11:44:40.831] <TB1> INFO: Expecting 655360 events.
[11:44:55.326] <TB1> INFO: 655360 events read in total (14091ms).
[11:44:55.421] <TB1> INFO: Expecting 655360 events.
[11:45:09.872] <TB1> INFO: 655360 events read in total (14048ms).
[11:45:09.960] <TB1> INFO: Expecting 655360 events.
[11:45:24.532] <TB1> INFO: 655360 events read in total (14169ms).
[11:45:24.662] <TB1> INFO: Expecting 655360 events.
[11:45:39.296] <TB1> INFO: 655360 events read in total (14231ms).
[11:45:39.433] <TB1> INFO: Test took 235835ms.
[11:45:39.530] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:45:39.786] <TB1> INFO: Expecting 655360 events.
[11:45:54.402] <TB1> INFO: 655360 events read in total (14024ms).
[11:45:54.416] <TB1> INFO: Expecting 655360 events.
[11:46:08.819] <TB1> INFO: 655360 events read in total (14000ms).
[11:46:08.839] <TB1> INFO: Expecting 655360 events.
[11:46:23.126] <TB1> INFO: 655360 events read in total (13884ms).
[11:46:23.148] <TB1> INFO: Expecting 655360 events.
[11:46:37.726] <TB1> INFO: 655360 events read in total (14175ms).
[11:46:37.754] <TB1> INFO: Expecting 655360 events.
[11:46:52.364] <TB1> INFO: 655360 events read in total (14207ms).
[11:46:52.396] <TB1> INFO: Expecting 655360 events.
[11:47:06.758] <TB1> INFO: 655360 events read in total (13959ms).
[11:47:06.804] <TB1> INFO: Expecting 655360 events.
[11:47:21.153] <TB1> INFO: 655360 events read in total (13946ms).
[11:47:21.193] <TB1> INFO: Expecting 655360 events.
[11:47:35.678] <TB1> INFO: 655360 events read in total (14082ms).
[11:47:35.730] <TB1> INFO: Expecting 655360 events.
[11:47:50.326] <TB1> INFO: 655360 events read in total (14192ms).
[11:47:50.377] <TB1> INFO: Expecting 655360 events.
[11:48:04.746] <TB1> INFO: 655360 events read in total (13966ms).
[11:48:04.824] <TB1> INFO: Expecting 655360 events.
[11:48:19.327] <TB1> INFO: 655360 events read in total (14099ms).
[11:48:19.436] <TB1> INFO: Expecting 655360 events.
[11:48:33.958] <TB1> INFO: 655360 events read in total (14119ms).
[11:48:34.065] <TB1> INFO: Expecting 655360 events.
[11:48:48.483] <TB1> INFO: 655360 events read in total (14015ms).
[11:48:48.588] <TB1> INFO: Expecting 655360 events.
[11:49:02.936] <TB1> INFO: 655360 events read in total (13940ms).
[11:49:03.026] <TB1> INFO: Expecting 655360 events.
[11:49:17.463] <TB1> INFO: 655360 events read in total (14034ms).
[11:49:17.607] <TB1> INFO: Expecting 655360 events.
[11:49:32.193] <TB1> INFO: 655360 events read in total (14183ms).
[11:49:32.298] <TB1> INFO: Test took 232768ms.
[11:49:32.478] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.484] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.490] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.495] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.501] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.507] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.512] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.518] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:49:32.524] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:49:32.529] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.535] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:49:32.541] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.546] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.552] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.557] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.563] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:49:32.568] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:49:32.575] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.580] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.587] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.593] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:49:32.599] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:49:32.605] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[11:49:32.611] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[11:49:32.617] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[11:49:32.623] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[11:49:32.629] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:49:32.667] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C0.dat
[11:49:32.667] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C1.dat
[11:49:32.667] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C2.dat
[11:49:32.668] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C3.dat
[11:49:32.668] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C4.dat
[11:49:32.668] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C5.dat
[11:49:32.668] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C6.dat
[11:49:32.668] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C7.dat
[11:49:32.668] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C8.dat
[11:49:32.669] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C9.dat
[11:49:32.669] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C10.dat
[11:49:32.669] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C11.dat
[11:49:32.669] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C12.dat
[11:49:32.669] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C13.dat
[11:49:32.670] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C14.dat
[11:49:32.670] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//dacParameters35_C15.dat
[11:49:32.910] <TB1> INFO: Expecting 41600 events.
[11:49:36.105] <TB1> INFO: 41600 events read in total (2603ms).
[11:49:36.106] <TB1> INFO: Test took 3433ms.
[11:49:36.563] <TB1> INFO: Expecting 41600 events.
[11:49:39.639] <TB1> INFO: 41600 events read in total (2484ms).
[11:49:39.639] <TB1> INFO: Test took 3318ms.
[11:49:40.128] <TB1> INFO: Expecting 41600 events.
[11:49:43.312] <TB1> INFO: 41600 events read in total (2592ms).
[11:49:43.313] <TB1> INFO: Test took 3459ms.
[11:49:43.536] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:43.625] <TB1> INFO: Expecting 2560 events.
[11:49:44.512] <TB1> INFO: 2560 events read in total (295ms).
[11:49:44.512] <TB1> INFO: Test took 976ms.
[11:49:44.514] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:44.822] <TB1> INFO: Expecting 2560 events.
[11:49:45.713] <TB1> INFO: 2560 events read in total (299ms).
[11:49:45.714] <TB1> INFO: Test took 1200ms.
[11:49:45.717] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:46.021] <TB1> INFO: Expecting 2560 events.
[11:49:46.915] <TB1> INFO: 2560 events read in total (302ms).
[11:49:46.915] <TB1> INFO: Test took 1200ms.
[11:49:46.918] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:47.225] <TB1> INFO: Expecting 2560 events.
[11:49:48.116] <TB1> INFO: 2560 events read in total (300ms).
[11:49:48.117] <TB1> INFO: Test took 1199ms.
[11:49:48.120] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:48.425] <TB1> INFO: Expecting 2560 events.
[11:49:49.318] <TB1> INFO: 2560 events read in total (301ms).
[11:49:49.319] <TB1> INFO: Test took 1199ms.
[11:49:49.323] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:49.627] <TB1> INFO: Expecting 2560 events.
[11:49:50.523] <TB1> INFO: 2560 events read in total (304ms).
[11:49:50.523] <TB1> INFO: Test took 1201ms.
[11:49:50.526] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:50.831] <TB1> INFO: Expecting 2560 events.
[11:49:51.725] <TB1> INFO: 2560 events read in total (302ms).
[11:49:51.726] <TB1> INFO: Test took 1200ms.
[11:49:51.728] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:52.033] <TB1> INFO: Expecting 2560 events.
[11:49:52.925] <TB1> INFO: 2560 events read in total (300ms).
[11:49:52.925] <TB1> INFO: Test took 1197ms.
[11:49:52.928] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:53.233] <TB1> INFO: Expecting 2560 events.
[11:49:54.123] <TB1> INFO: 2560 events read in total (299ms).
[11:49:54.123] <TB1> INFO: Test took 1195ms.
[11:49:54.128] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:54.431] <TB1> INFO: Expecting 2560 events.
[11:49:55.317] <TB1> INFO: 2560 events read in total (294ms).
[11:49:55.317] <TB1> INFO: Test took 1189ms.
[11:49:55.319] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:55.626] <TB1> INFO: Expecting 2560 events.
[11:49:56.506] <TB1> INFO: 2560 events read in total (288ms).
[11:49:56.506] <TB1> INFO: Test took 1187ms.
[11:49:56.509] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:56.816] <TB1> INFO: Expecting 2560 events.
[11:49:57.695] <TB1> INFO: 2560 events read in total (288ms).
[11:49:57.695] <TB1> INFO: Test took 1187ms.
[11:49:57.698] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:58.008] <TB1> INFO: Expecting 2560 events.
[11:49:58.901] <TB1> INFO: 2560 events read in total (301ms).
[11:49:58.901] <TB1> INFO: Test took 1203ms.
[11:49:58.903] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:59.210] <TB1> INFO: Expecting 2560 events.
[11:50:00.096] <TB1> INFO: 2560 events read in total (295ms).
[11:50:00.096] <TB1> INFO: Test took 1193ms.
[11:50:00.098] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:00.407] <TB1> INFO: Expecting 2560 events.
[11:50:01.294] <TB1> INFO: 2560 events read in total (295ms).
[11:50:01.295] <TB1> INFO: Test took 1197ms.
[11:50:01.297] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:01.603] <TB1> INFO: Expecting 2560 events.
[11:50:02.486] <TB1> INFO: 2560 events read in total (291ms).
[11:50:02.487] <TB1> INFO: Test took 1190ms.
[11:50:02.491] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:02.794] <TB1> INFO: Expecting 2560 events.
[11:50:03.686] <TB1> INFO: 2560 events read in total (300ms).
[11:50:03.686] <TB1> INFO: Test took 1195ms.
[11:50:03.689] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:03.994] <TB1> INFO: Expecting 2560 events.
[11:50:04.886] <TB1> INFO: 2560 events read in total (300ms).
[11:50:04.887] <TB1> INFO: Test took 1199ms.
[11:50:04.890] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:05.194] <TB1> INFO: Expecting 2560 events.
[11:50:06.075] <TB1> INFO: 2560 events read in total (289ms).
[11:50:06.075] <TB1> INFO: Test took 1185ms.
[11:50:06.077] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:06.384] <TB1> INFO: Expecting 2560 events.
[11:50:07.274] <TB1> INFO: 2560 events read in total (298ms).
[11:50:07.274] <TB1> INFO: Test took 1197ms.
[11:50:07.277] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:07.583] <TB1> INFO: Expecting 2560 events.
[11:50:08.474] <TB1> INFO: 2560 events read in total (300ms).
[11:50:08.475] <TB1> INFO: Test took 1198ms.
[11:50:08.478] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:08.783] <TB1> INFO: Expecting 2560 events.
[11:50:09.665] <TB1> INFO: 2560 events read in total (290ms).
[11:50:09.666] <TB1> INFO: Test took 1188ms.
[11:50:09.668] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:09.974] <TB1> INFO: Expecting 2560 events.
[11:50:10.863] <TB1> INFO: 2560 events read in total (297ms).
[11:50:10.864] <TB1> INFO: Test took 1196ms.
[11:50:10.867] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:11.171] <TB1> INFO: Expecting 2560 events.
[11:50:12.064] <TB1> INFO: 2560 events read in total (301ms).
[11:50:12.065] <TB1> INFO: Test took 1198ms.
[11:50:12.067] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:12.373] <TB1> INFO: Expecting 2560 events.
[11:50:13.263] <TB1> INFO: 2560 events read in total (299ms).
[11:50:13.264] <TB1> INFO: Test took 1197ms.
[11:50:13.268] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:13.572] <TB1> INFO: Expecting 2560 events.
[11:50:14.465] <TB1> INFO: 2560 events read in total (301ms).
[11:50:14.466] <TB1> INFO: Test took 1198ms.
[11:50:14.469] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:14.775] <TB1> INFO: Expecting 2560 events.
[11:50:15.669] <TB1> INFO: 2560 events read in total (302ms).
[11:50:15.669] <TB1> INFO: Test took 1201ms.
[11:50:15.673] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:15.976] <TB1> INFO: Expecting 2560 events.
[11:50:16.863] <TB1> INFO: 2560 events read in total (295ms).
[11:50:16.864] <TB1> INFO: Test took 1192ms.
[11:50:16.867] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:17.171] <TB1> INFO: Expecting 2560 events.
[11:50:18.059] <TB1> INFO: 2560 events read in total (297ms).
[11:50:18.059] <TB1> INFO: Test took 1192ms.
[11:50:18.062] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:18.367] <TB1> INFO: Expecting 2560 events.
[11:50:19.257] <TB1> INFO: 2560 events read in total (297ms).
[11:50:19.258] <TB1> INFO: Test took 1196ms.
[11:50:19.261] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:19.567] <TB1> INFO: Expecting 2560 events.
[11:50:20.452] <TB1> INFO: 2560 events read in total (293ms).
[11:50:20.452] <TB1> INFO: Test took 1191ms.
[11:50:20.454] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:50:20.761] <TB1> INFO: Expecting 2560 events.
[11:50:21.647] <TB1> INFO: 2560 events read in total (294ms).
[11:50:21.647] <TB1> INFO: Test took 1193ms.
[11:50:22.131] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 657 seconds
[11:50:22.131] <TB1> INFO: PH scale (per ROC): 47 46 49 66 63 63 65 52 48 40 48 43 54 47 42 53
[11:50:22.131] <TB1> INFO: PH offset (per ROC): 87 91 108 125 115 124 112 95 100 106 82 81 112 87 103 135
[11:50:22.140] <TB1> INFO: Decoding statistics:
[11:50:22.140] <TB1> INFO: General information:
[11:50:22.140] <TB1> INFO: 16bit words read: 127888
[11:50:22.140] <TB1> INFO: valid events total: 20480
[11:50:22.140] <TB1> INFO: empty events: 17976
[11:50:22.140] <TB1> INFO: valid events with pixels: 2504
[11:50:22.140] <TB1> INFO: valid pixel hits: 2504
[11:50:22.140] <TB1> INFO: Event errors: 0
[11:50:22.140] <TB1> INFO: start marker: 0
[11:50:22.140] <TB1> INFO: stop marker: 0
[11:50:22.140] <TB1> INFO: overflow: 0
[11:50:22.140] <TB1> INFO: invalid 5bit words: 0
[11:50:22.140] <TB1> INFO: invalid XOR eye diagram: 0
[11:50:22.140] <TB1> INFO: frame (failed synchr.): 0
[11:50:22.140] <TB1> INFO: idle data (no TBM trl): 0
[11:50:22.140] <TB1> INFO: no data (only TBM hdr): 0
[11:50:22.140] <TB1> INFO: TBM errors: 0
[11:50:22.140] <TB1> INFO: flawed TBM headers: 0
[11:50:22.140] <TB1> INFO: flawed TBM trailers: 0
[11:50:22.141] <TB1> INFO: event ID mismatches: 0
[11:50:22.141] <TB1> INFO: ROC errors: 0
[11:50:22.141] <TB1> INFO: missing ROC header(s): 0
[11:50:22.141] <TB1> INFO: misplaced readback start: 0
[11:50:22.141] <TB1> INFO: Pixel decoding errors: 0
[11:50:22.141] <TB1> INFO: pixel data incomplete: 0
[11:50:22.141] <TB1> INFO: pixel address: 0
[11:50:22.141] <TB1> INFO: pulse height fill bit: 0
[11:50:22.141] <TB1> INFO: buffer corruption: 0
[11:50:22.342] <TB1> INFO: ######################################################################
[11:50:22.342] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[11:50:22.342] <TB1> INFO: ######################################################################
[11:50:22.357] <TB1> INFO: scanning low vcal = 10
[11:50:22.601] <TB1> INFO: Expecting 41600 events.
[11:50:26.205] <TB1> INFO: 41600 events read in total (3012ms).
[11:50:26.205] <TB1> INFO: Test took 3848ms.
[11:50:26.207] <TB1> INFO: scanning low vcal = 20
[11:50:26.500] <TB1> INFO: Expecting 41600 events.
[11:50:30.110] <TB1> INFO: 41600 events read in total (3017ms).
[11:50:30.111] <TB1> INFO: Test took 3904ms.
[11:50:30.112] <TB1> INFO: scanning low vcal = 30
[11:50:30.407] <TB1> INFO: Expecting 41600 events.
[11:50:34.085] <TB1> INFO: 41600 events read in total (3086ms).
[11:50:34.086] <TB1> INFO: Test took 3974ms.
[11:50:34.088] <TB1> INFO: scanning low vcal = 40
[11:50:34.366] <TB1> INFO: Expecting 41600 events.
[11:50:38.396] <TB1> INFO: 41600 events read in total (3438ms).
[11:50:38.397] <TB1> INFO: Test took 4309ms.
[11:50:38.401] <TB1> INFO: scanning low vcal = 50
[11:50:38.679] <TB1> INFO: Expecting 41600 events.
[11:50:42.758] <TB1> INFO: 41600 events read in total (3487ms).
[11:50:42.760] <TB1> INFO: Test took 4359ms.
[11:50:42.763] <TB1> INFO: scanning low vcal = 60
[11:50:43.080] <TB1> INFO: Expecting 41600 events.
[11:50:47.132] <TB1> INFO: 41600 events read in total (3461ms).
[11:50:47.133] <TB1> INFO: Test took 4370ms.
[11:50:47.136] <TB1> INFO: scanning low vcal = 70
[11:50:47.413] <TB1> INFO: Expecting 41600 events.
[11:50:51.444] <TB1> INFO: 41600 events read in total (3439ms).
[11:50:51.445] <TB1> INFO: Test took 4309ms.
[11:50:51.448] <TB1> INFO: scanning low vcal = 80
[11:50:51.725] <TB1> INFO: Expecting 41600 events.
[11:50:55.787] <TB1> INFO: 41600 events read in total (3470ms).
[11:50:55.788] <TB1> INFO: Test took 4340ms.
[11:50:55.792] <TB1> INFO: scanning low vcal = 90
[11:50:56.108] <TB1> INFO: Expecting 41600 events.
[11:51:00.126] <TB1> INFO: 41600 events read in total (3427ms).
[11:51:00.127] <TB1> INFO: Test took 4335ms.
[11:51:00.132] <TB1> INFO: scanning low vcal = 100
[11:51:00.408] <TB1> INFO: Expecting 41600 events.
[11:51:04.418] <TB1> INFO: 41600 events read in total (3419ms).
[11:51:04.419] <TB1> INFO: Test took 4287ms.
[11:51:04.422] <TB1> INFO: scanning low vcal = 110
[11:51:04.699] <TB1> INFO: Expecting 41600 events.
[11:51:08.712] <TB1> INFO: 41600 events read in total (3420ms).
[11:51:08.713] <TB1> INFO: Test took 4290ms.
[11:51:08.716] <TB1> INFO: scanning low vcal = 120
[11:51:08.993] <TB1> INFO: Expecting 41600 events.
[11:51:13.046] <TB1> INFO: 41600 events read in total (3461ms).
[11:51:13.047] <TB1> INFO: Test took 4331ms.
[11:51:13.051] <TB1> INFO: scanning low vcal = 130
[11:51:13.328] <TB1> INFO: Expecting 41600 events.
[11:51:17.440] <TB1> INFO: 41600 events read in total (3520ms).
[11:51:17.441] <TB1> INFO: Test took 4389ms.
[11:51:17.444] <TB1> INFO: scanning low vcal = 140
[11:51:17.722] <TB1> INFO: Expecting 41600 events.
[11:51:21.778] <TB1> INFO: 41600 events read in total (3465ms).
[11:51:21.779] <TB1> INFO: Test took 4335ms.
[11:51:21.782] <TB1> INFO: scanning low vcal = 150
[11:51:22.060] <TB1> INFO: Expecting 41600 events.
[11:51:26.103] <TB1> INFO: 41600 events read in total (3451ms).
[11:51:26.104] <TB1> INFO: Test took 4322ms.
[11:51:26.108] <TB1> INFO: scanning low vcal = 160
[11:51:26.388] <TB1> INFO: Expecting 41600 events.
[11:51:30.477] <TB1> INFO: 41600 events read in total (3497ms).
[11:51:30.478] <TB1> INFO: Test took 4370ms.
[11:51:30.481] <TB1> INFO: scanning low vcal = 170
[11:51:30.758] <TB1> INFO: Expecting 41600 events.
[11:51:34.800] <TB1> INFO: 41600 events read in total (3450ms).
[11:51:34.801] <TB1> INFO: Test took 4320ms.
[11:51:34.806] <TB1> INFO: scanning low vcal = 180
[11:51:35.086] <TB1> INFO: Expecting 41600 events.
[11:51:39.187] <TB1> INFO: 41600 events read in total (3509ms).
[11:51:39.188] <TB1> INFO: Test took 4382ms.
[11:51:39.191] <TB1> INFO: scanning low vcal = 190
[11:51:39.468] <TB1> INFO: Expecting 41600 events.
[11:51:43.509] <TB1> INFO: 41600 events read in total (3450ms).
[11:51:43.510] <TB1> INFO: Test took 4319ms.
[11:51:43.513] <TB1> INFO: scanning low vcal = 200
[11:51:43.790] <TB1> INFO: Expecting 41600 events.
[11:51:47.726] <TB1> INFO: 41600 events read in total (3344ms).
[11:51:47.727] <TB1> INFO: Test took 4214ms.
[11:51:47.731] <TB1> INFO: scanning low vcal = 210
[11:51:48.006] <TB1> INFO: Expecting 41600 events.
[11:51:51.950] <TB1> INFO: 41600 events read in total (3352ms).
[11:51:51.951] <TB1> INFO: Test took 4220ms.
[11:51:51.955] <TB1> INFO: scanning low vcal = 220
[11:51:52.231] <TB1> INFO: Expecting 41600 events.
[11:51:56.168] <TB1> INFO: 41600 events read in total (3345ms).
[11:51:56.169] <TB1> INFO: Test took 4214ms.
[11:51:56.173] <TB1> INFO: scanning low vcal = 230
[11:51:56.448] <TB1> INFO: Expecting 41600 events.
[11:52:00.405] <TB1> INFO: 41600 events read in total (3365ms).
[11:52:00.406] <TB1> INFO: Test took 4233ms.
[11:52:00.409] <TB1> INFO: scanning low vcal = 240
[11:52:00.686] <TB1> INFO: Expecting 41600 events.
[11:52:04.627] <TB1> INFO: 41600 events read in total (3350ms).
[11:52:04.628] <TB1> INFO: Test took 4219ms.
[11:52:04.631] <TB1> INFO: scanning low vcal = 250
[11:52:04.907] <TB1> INFO: Expecting 41600 events.
[11:52:08.845] <TB1> INFO: 41600 events read in total (3346ms).
[11:52:08.846] <TB1> INFO: Test took 4215ms.
[11:52:08.850] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[11:52:09.125] <TB1> INFO: Expecting 41600 events.
[11:52:13.079] <TB1> INFO: 41600 events read in total (3362ms).
[11:52:13.080] <TB1> INFO: Test took 4230ms.
[11:52:13.083] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[11:52:13.359] <TB1> INFO: Expecting 41600 events.
[11:52:17.312] <TB1> INFO: 41600 events read in total (3361ms).
[11:52:17.312] <TB1> INFO: Test took 4229ms.
[11:52:17.316] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[11:52:17.592] <TB1> INFO: Expecting 41600 events.
[11:52:21.669] <TB1> INFO: 41600 events read in total (3485ms).
[11:52:21.670] <TB1> INFO: Test took 4354ms.
[11:52:21.673] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[11:52:21.950] <TB1> INFO: Expecting 41600 events.
[11:52:25.003] <TB1> INFO: 41600 events read in total (3462ms).
[11:52:26.004] <TB1> INFO: Test took 4330ms.
[11:52:26.008] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[11:52:26.284] <TB1> INFO: Expecting 41600 events.
[11:52:30.336] <TB1> INFO: 41600 events read in total (3460ms).
[11:52:30.337] <TB1> INFO: Test took 4329ms.
[11:52:30.754] <TB1> INFO: PixTestGainPedestal::measure() done
[11:53:05.432] <TB1> INFO: PixTestGainPedestal::fit() done
[11:53:05.432] <TB1> INFO: non-linearity mean: 0.917 0.938 0.961 0.985 0.968 0.980 0.983 0.971 0.926 0.976 0.937 0.987 0.965 0.997 0.925 0.973
[11:53:05.432] <TB1> INFO: non-linearity RMS: 0.103 0.193 0.034 0.003 0.011 0.004 0.002 0.011 0.121 0.185 0.099 0.196 0.018 0.171 0.136 0.007
[11:53:05.432] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[11:53:05.446] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[11:53:05.459] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[11:53:05.473] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[11:53:05.486] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[11:53:05.499] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[11:53:05.513] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[11:53:05.527] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[11:53:05.541] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[11:53:05.555] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[11:53:05.569] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[11:53:05.583] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[11:53:05.596] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[11:53:05.610] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[11:53:05.624] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[11:53:05.637] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[11:53:05.650] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 163 seconds
[11:53:05.650] <TB1> INFO: Decoding statistics:
[11:53:05.650] <TB1> INFO: General information:
[11:53:05.650] <TB1> INFO: 16bit words read: 3327952
[11:53:05.650] <TB1> INFO: valid events total: 332800
[11:53:05.650] <TB1> INFO: empty events: 0
[11:53:05.650] <TB1> INFO: valid events with pixels: 332800
[11:53:05.650] <TB1> INFO: valid pixel hits: 665576
[11:53:05.650] <TB1> INFO: Event errors: 0
[11:53:05.650] <TB1> INFO: start marker: 0
[11:53:05.650] <TB1> INFO: stop marker: 0
[11:53:05.650] <TB1> INFO: overflow: 0
[11:53:05.650] <TB1> INFO: invalid 5bit words: 0
[11:53:05.650] <TB1> INFO: invalid XOR eye diagram: 0
[11:53:05.650] <TB1> INFO: frame (failed synchr.): 0
[11:53:05.650] <TB1> INFO: idle data (no TBM trl): 0
[11:53:05.650] <TB1> INFO: no data (only TBM hdr): 0
[11:53:05.650] <TB1> INFO: TBM errors: 0
[11:53:05.650] <TB1> INFO: flawed TBM headers: 0
[11:53:05.650] <TB1> INFO: flawed TBM trailers: 0
[11:53:05.650] <TB1> INFO: event ID mismatches: 0
[11:53:05.651] <TB1> INFO: ROC errors: 0
[11:53:05.651] <TB1> INFO: missing ROC header(s): 0
[11:53:05.651] <TB1> INFO: misplaced readback start: 0
[11:53:05.651] <TB1> INFO: Pixel decoding errors: 0
[11:53:05.651] <TB1> INFO: pixel data incomplete: 0
[11:53:05.651] <TB1> INFO: pixel address: 0
[11:53:05.651] <TB1> INFO: pulse height fill bit: 0
[11:53:05.651] <TB1> INFO: buffer corruption: 0
[11:53:05.668] <TB1> INFO: Decoding statistics:
[11:53:05.668] <TB1> INFO: General information:
[11:53:05.668] <TB1> INFO: 16bit words read: 3457376
[11:53:05.669] <TB1> INFO: valid events total: 353536
[11:53:05.669] <TB1> INFO: empty events: 18232
[11:53:05.669] <TB1> INFO: valid events with pixels: 335304
[11:53:05.669] <TB1> INFO: valid pixel hits: 668080
[11:53:05.669] <TB1> INFO: Event errors: 0
[11:53:05.669] <TB1> INFO: start marker: 0
[11:53:05.669] <TB1> INFO: stop marker: 0
[11:53:05.669] <TB1> INFO: overflow: 0
[11:53:05.669] <TB1> INFO: invalid 5bit words: 0
[11:53:05.669] <TB1> INFO: invalid XOR eye diagram: 0
[11:53:05.669] <TB1> INFO: frame (failed synchr.): 0
[11:53:05.669] <TB1> INFO: idle data (no TBM trl): 0
[11:53:05.669] <TB1> INFO: no data (only TBM hdr): 0
[11:53:05.669] <TB1> INFO: TBM errors: 0
[11:53:05.669] <TB1> INFO: flawed TBM headers: 0
[11:53:05.669] <TB1> INFO: flawed TBM trailers: 0
[11:53:05.669] <TB1> INFO: event ID mismatches: 0
[11:53:05.669] <TB1> INFO: ROC errors: 0
[11:53:05.669] <TB1> INFO: missing ROC header(s): 0
[11:53:05.669] <TB1> INFO: misplaced readback start: 0
[11:53:05.669] <TB1> INFO: Pixel decoding errors: 0
[11:53:05.669] <TB1> INFO: pixel data incomplete: 0
[11:53:05.669] <TB1> INFO: pixel address: 0
[11:53:05.669] <TB1> INFO: pulse height fill bit: 0
[11:53:05.669] <TB1> INFO: buffer corruption: 0
[11:53:05.669] <TB1> INFO: enter test to run
[11:53:05.669] <TB1> INFO: test: exit no parameter change
[11:53:05.801] <TB1> QUIET: Connection to board 154 closed.
[11:53:05.802] <TB1> INFO: pXar: this is the end, my friend