[12:02:48.583] <TB1> INFO: *** Welcome to pxar ***
[12:02:48.583] <TB1> INFO: *** Today: 2016/11/02
[12:02:48.589] <TB1> INFO: *** Version: c8ba-dirty
[12:02:48.589] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:02:48.590] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:02:48.590] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//defaultMaskFile.dat
[12:02:48.590] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters_C15.dat
[12:02:48.653] <TB1> INFO: clk: 4
[12:02:48.653] <TB1> INFO: ctr: 4
[12:02:48.653] <TB1> INFO: sda: 19
[12:02:48.653] <TB1> INFO: tin: 9
[12:02:48.653] <TB1> INFO: level: 15
[12:02:48.653] <TB1> INFO: triggerdelay: 0
[12:02:48.653] <TB1> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[12:02:48.653] <TB1> INFO: Log level: INFO
[12:02:48.662] <TB1> INFO: Found DTB DTB_WXC03A
[12:02:48.673] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[12:02:48.675] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
------------------------------------------------------
[12:02:48.677] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[12:02:50.168] <TB1> INFO: DUT info:
[12:02:50.168] <TB1> INFO: The DUT currently contains the following objects:
[12:02:50.168] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[12:02:50.168] <TB1> INFO: TBM Core alpha (0): 7 registers set
[12:02:50.168] <TB1> INFO: TBM Core beta (1): 7 registers set
[12:02:50.168] <TB1> INFO: TBM Core alpha (2): 7 registers set
[12:02:50.168] <TB1> INFO: TBM Core beta (3): 7 registers set
[12:02:50.168] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[12:02:50.168] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.168] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.168] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.168] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.168] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.168] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.168] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.168] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.168] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.168] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.168] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.168] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.168] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.169] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.169] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.169] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:50.569] <TB1> INFO: enter 'restricted' command line mode
[12:02:50.569] <TB1> INFO: enter test to run
[12:02:50.569] <TB1> INFO: test: pretest no parameter change
[12:02:50.569] <TB1> INFO: running: pretest
[12:02:50.576] <TB1> INFO: ######################################################################
[12:02:50.576] <TB1> INFO: PixTestPretest::doTest()
[12:02:50.576] <TB1> INFO: ######################################################################
[12:02:50.577] <TB1> INFO: ----------------------------------------------------------------------
[12:02:50.577] <TB1> INFO: PixTestPretest::programROC()
[12:02:50.577] <TB1> INFO: ----------------------------------------------------------------------
[12:03:08.590] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:03:08.590] <TB1> INFO: IA differences per ROC: 16.9 17.7 20.9 16.1 20.9 20.9 18.5 18.5 16.9 18.5 17.7 20.1 20.1 16.9 18.5 18.5
[12:03:08.647] <TB1> INFO: ----------------------------------------------------------------------
[12:03:08.648] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:03:08.648] <TB1> INFO: ----------------------------------------------------------------------
[12:03:29.943] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 393.1 mA = 24.5688 mA/ROC
[12:03:29.943] <TB1> INFO: i(loss) [mA/ROC]: 19.3 20.9 19.3 20.1 19.3 19.3 20.1 20.1 19.3 20.1 20.1 20.1 18.5 19.3 19.3 20.1
[12:03:29.976] <TB1> INFO: ----------------------------------------------------------------------
[12:03:29.976] <TB1> INFO: PixTestPretest::findTiming()
[12:03:29.976] <TB1> INFO: ----------------------------------------------------------------------
[12:03:29.977] <TB1> INFO: PixTestCmd::init()

[12:04:02.255] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:04:02.255] <TB1> INFO: (success/tries = 100/100), width = 4
[12:04:03.758] <TB1> INFO: ----------------------------------------------------------------------
[12:04:03.758] <TB1> INFO: PixTestPretest::findWorkingPixel()
[12:04:03.758] <TB1> INFO: ----------------------------------------------------------------------
[12:04:03.851] <TB1> INFO: Expecting 231680 events.
[12:04:14.009] <TB1> INFO: 231680 events read in total (9567ms).
[12:04:14.019] <TB1> INFO: Test took 10257ms.
[12:04:14.265] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:04:14.303] <TB1> INFO: ----------------------------------------------------------------------
[12:04:14.303] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[12:04:14.303] <TB1> INFO: ----------------------------------------------------------------------
[12:04:14.397] <TB1> INFO: Expecting 231680 events.
[12:04:24.512] <TB1> INFO: 231680 events read in total (9524ms).
[12:04:24.519] <TB1> INFO: Test took 10212ms.
[12:04:24.784] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[12:04:24.784] <TB1> INFO: CalDel: 82 81 90 75 77 84 80 85 84 108 115 102 64 92 101 90
[12:04:24.784] <TB1> INFO: VthrComp: 51 51 51 52 51 51 51 51 51 51 52 51 53 51 51 51
[12:04:24.788] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C0.dat
[12:04:24.788] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C1.dat
[12:04:24.788] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C2.dat
[12:04:24.788] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C3.dat
[12:04:24.788] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C4.dat
[12:04:24.789] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C5.dat
[12:04:24.789] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C6.dat
[12:04:24.789] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C7.dat
[12:04:24.789] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C8.dat
[12:04:24.789] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C9.dat
[12:04:24.789] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C10.dat
[12:04:24.789] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C11.dat
[12:04:24.789] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C12.dat
[12:04:24.789] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C13.dat
[12:04:24.789] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C14.dat
[12:04:24.789] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:04:24.790] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[12:04:24.790] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[12:04:24.790] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[12:04:24.790] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:04:24.790] <TB1> INFO: PixTestPretest::doTest() done, duration: 94 seconds
[12:04:24.841] <TB1> INFO: enter test to run
[12:04:24.841] <TB1> INFO: test: fulltest no parameter change
[12:04:24.841] <TB1> INFO: running: fulltest
[12:04:24.841] <TB1> INFO: ######################################################################
[12:04:24.841] <TB1> INFO: PixTestFullTest::doTest()
[12:04:24.841] <TB1> INFO: ######################################################################
[12:04:24.842] <TB1> INFO: ######################################################################
[12:04:24.842] <TB1> INFO: PixTestAlive::doTest()
[12:04:24.842] <TB1> INFO: ######################################################################
[12:04:24.843] <TB1> INFO: ----------------------------------------------------------------------
[12:04:24.843] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:04:24.843] <TB1> INFO: ----------------------------------------------------------------------
[12:04:25.091] <TB1> INFO: Expecting 41600 events.
[12:04:28.561] <TB1> INFO: 41600 events read in total (2879ms).
[12:04:28.562] <TB1> INFO: Test took 3717ms.
[12:04:28.790] <TB1> INFO: PixTestAlive::aliveTest() done
[12:04:28.790] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
[12:04:28.791] <TB1> INFO: ----------------------------------------------------------------------
[12:04:28.792] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:04:28.792] <TB1> INFO: ----------------------------------------------------------------------
[12:04:29.032] <TB1> INFO: Expecting 41600 events.
[12:04:32.077] <TB1> INFO: 41600 events read in total (2453ms).
[12:04:32.077] <TB1> INFO: Test took 3285ms.
[12:04:32.078] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:04:32.311] <TB1> INFO: PixTestAlive::maskTest() done
[12:04:32.311] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:04:32.312] <TB1> INFO: ----------------------------------------------------------------------
[12:04:32.312] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:04:32.312] <TB1> INFO: ----------------------------------------------------------------------
[12:04:32.583] <TB1> INFO: Expecting 41600 events.
[12:04:36.208] <TB1> INFO: 41600 events read in total (3033ms).
[12:04:36.208] <TB1> INFO: Test took 3893ms.
[12:04:36.442] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[12:04:36.442] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:04:36.443] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:04:36.443] <TB1> INFO: Decoding statistics:
[12:04:36.443] <TB1> INFO: General information:
[12:04:36.443] <TB1> INFO: 16bit words read: 0
[12:04:36.443] <TB1> INFO: valid events total: 0
[12:04:36.443] <TB1> INFO: empty events: 0
[12:04:36.443] <TB1> INFO: valid events with pixels: 0
[12:04:36.443] <TB1> INFO: valid pixel hits: 0
[12:04:36.443] <TB1> INFO: Event errors: 0
[12:04:36.443] <TB1> INFO: start marker: 0
[12:04:36.443] <TB1> INFO: stop marker: 0
[12:04:36.443] <TB1> INFO: overflow: 0
[12:04:36.443] <TB1> INFO: invalid 5bit words: 0
[12:04:36.443] <TB1> INFO: invalid XOR eye diagram: 0
[12:04:36.443] <TB1> INFO: frame (failed synchr.): 0
[12:04:36.443] <TB1> INFO: idle data (no TBM trl): 0
[12:04:36.443] <TB1> INFO: no data (only TBM hdr): 0
[12:04:36.443] <TB1> INFO: TBM errors: 0
[12:04:36.443] <TB1> INFO: flawed TBM headers: 0
[12:04:36.443] <TB1> INFO: flawed TBM trailers: 0
[12:04:36.443] <TB1> INFO: event ID mismatches: 0
[12:04:36.443] <TB1> INFO: ROC errors: 0
[12:04:36.443] <TB1> INFO: missing ROC header(s): 0
[12:04:36.443] <TB1> INFO: misplaced readback start: 0
[12:04:36.443] <TB1> INFO: Pixel decoding errors: 0
[12:04:36.443] <TB1> INFO: pixel data incomplete: 0
[12:04:36.443] <TB1> INFO: pixel address: 0
[12:04:36.443] <TB1> INFO: pulse height fill bit: 0
[12:04:36.443] <TB1> INFO: buffer corruption: 0
[12:04:36.449] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:04:36.450] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[12:04:36.450] <TB1> INFO: ######################################################################
[12:04:36.450] <TB1> INFO: PixTestReadback::doTest()
[12:04:36.450] <TB1> INFO: ######################################################################
[12:04:36.450] <TB1> INFO: ----------------------------------------------------------------------
[12:04:36.450] <TB1> INFO: PixTestReadback::CalibrateVd()
[12:04:36.450] <TB1> INFO: ----------------------------------------------------------------------
[12:04:46.408] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:04:46.409] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:04:46.409] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:04:46.409] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:04:46.409] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:04:46.409] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:04:46.409] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:04:46.409] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:04:46.410] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:04:46.410] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:04:46.410] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:04:46.410] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:04:46.410] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:04:46.410] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:04:46.410] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:04:46.411] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:04:46.439] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:04:46.439] <TB1> INFO: ----------------------------------------------------------------------
[12:04:46.439] <TB1> INFO: PixTestReadback::CalibrateVa()
[12:04:46.439] <TB1> INFO: ----------------------------------------------------------------------
[12:04:56.363] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:04:56.363] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:04:56.363] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:04:56.363] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:04:56.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:04:56.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:04:56.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:04:56.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:04:56.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:04:56.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:04:56.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:04:56.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:04:56.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:04:56.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:04:56.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:04:56.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:04:56.395] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:04:56.395] <TB1> INFO: ----------------------------------------------------------------------
[12:04:56.395] <TB1> INFO: PixTestReadback::readbackVbg()
[12:04:56.395] <TB1> INFO: ----------------------------------------------------------------------
[12:05:04.073] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:05:04.073] <TB1> INFO: ----------------------------------------------------------------------
[12:05:04.073] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[12:05:04.073] <TB1> INFO: ----------------------------------------------------------------------
[12:05:04.073] <TB1> INFO: Vbg will be calibrated using Vd calibration
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 155.3calibrated Vbg = 1.20951 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 158calibrated Vbg = 1.19777 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 155.6calibrated Vbg = 1.20016 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 162.9calibrated Vbg = 1.19793 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 150.4calibrated Vbg = 1.20246 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 156calibrated Vbg = 1.2074 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 154.1calibrated Vbg = 1.21222 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 164.7calibrated Vbg = 1.2124 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 157.2calibrated Vbg = 1.20595 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 152.2calibrated Vbg = 1.20205 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 160calibrated Vbg = 1.19787 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 159.4calibrated Vbg = 1.19235 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 151.7calibrated Vbg = 1.19885 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 155.2calibrated Vbg = 1.20118 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 158.7calibrated Vbg = 1.21062 :::*/*/*/*/
[12:05:04.073] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 153.1calibrated Vbg = 1.20908 :::*/*/*/*/
[12:05:04.076] <TB1> INFO: ----------------------------------------------------------------------
[12:05:04.076] <TB1> INFO: PixTestReadback::CalibrateIa()
[12:05:04.076] <TB1> INFO: ----------------------------------------------------------------------
[12:07:44.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:07:44.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:07:44.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:07:44.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:07:44.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:07:44.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:07:44.870] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:07:44.871] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:07:44.871] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:07:44.871] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:07:44.871] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:07:44.871] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:07:44.871] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:07:44.871] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:07:44.871] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:07:44.871] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:07:44.901] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:07:44.902] <TB1> INFO: PixTestReadback::doTest() done
[12:07:44.902] <TB1> INFO: Decoding statistics:
[12:07:44.902] <TB1> INFO: General information:
[12:07:44.902] <TB1> INFO: 16bit words read: 1536
[12:07:44.902] <TB1> INFO: valid events total: 256
[12:07:44.902] <TB1> INFO: empty events: 256
[12:07:44.902] <TB1> INFO: valid events with pixels: 0
[12:07:44.902] <TB1> INFO: valid pixel hits: 0
[12:07:44.902] <TB1> INFO: Event errors: 0
[12:07:44.902] <TB1> INFO: start marker: 0
[12:07:44.902] <TB1> INFO: stop marker: 0
[12:07:44.902] <TB1> INFO: overflow: 0
[12:07:44.903] <TB1> INFO: invalid 5bit words: 0
[12:07:44.903] <TB1> INFO: invalid XOR eye diagram: 0
[12:07:44.903] <TB1> INFO: frame (failed synchr.): 0
[12:07:44.903] <TB1> INFO: idle data (no TBM trl): 0
[12:07:44.903] <TB1> INFO: no data (only TBM hdr): 0
[12:07:44.903] <TB1> INFO: TBM errors: 0
[12:07:44.903] <TB1> INFO: flawed TBM headers: 0
[12:07:44.903] <TB1> INFO: flawed TBM trailers: 0
[12:07:44.903] <TB1> INFO: event ID mismatches: 0
[12:07:44.903] <TB1> INFO: ROC errors: 0
[12:07:44.903] <TB1> INFO: missing ROC header(s): 0
[12:07:44.903] <TB1> INFO: misplaced readback start: 0
[12:07:44.903] <TB1> INFO: Pixel decoding errors: 0
[12:07:44.903] <TB1> INFO: pixel data incomplete: 0
[12:07:44.903] <TB1> INFO: pixel address: 0
[12:07:44.903] <TB1> INFO: pulse height fill bit: 0
[12:07:44.903] <TB1> INFO: buffer corruption: 0
[12:07:44.954] <TB1> INFO: ######################################################################
[12:07:44.954] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:07:44.954] <TB1> INFO: ######################################################################
[12:07:44.956] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:07:44.980] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:07:44.980] <TB1> INFO: run 1 of 1
[12:07:45.220] <TB1> INFO: Expecting 3120000 events.
[12:08:16.063] <TB1> INFO: 664930 events read in total (30252ms).











[12:08:46.005] <TB1> INFO: 1320210 events read in total (60194ms).











[12:09:15.786] <TB1> INFO: 1969320 events read in total (89975ms).
[12:09:45.684] <TB1> INFO: 2618680 events read in total (119873ms).











[12:10:08.927] <TB1> INFO: 3120000 events read in total (143116ms).
[12:10:08.994] <TB1> INFO: Test took 144014ms.
[12:10:30.975] <TB1> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 166 seconds
[12:10:30.975] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
[12:10:30.975] <TB1> INFO: separation cut (per ROC): 104 108 107 104 104 104 114 104 96 102 102 106 108 96 94 105
[12:10:30.975] <TB1> INFO: Decoding statistics:
[12:10:30.975] <TB1> INFO: General information:
[12:10:30.975] <TB1> INFO: 16bit words read: 0
[12:10:30.975] <TB1> INFO: valid events total: 0
[12:10:30.975] <TB1> INFO: empty events: 0
[12:10:30.975] <TB1> INFO: valid events with pixels: 0
[12:10:30.976] <TB1> INFO: valid pixel hits: 0
[12:10:30.976] <TB1> INFO: Event errors: 0
[12:10:30.976] <TB1> INFO: start marker: 0
[12:10:30.976] <TB1> INFO: stop marker: 0
[12:10:30.976] <TB1> INFO: overflow: 0
[12:10:30.976] <TB1> INFO: invalid 5bit words: 0
[12:10:30.976] <TB1> INFO: invalid XOR eye diagram: 0
[12:10:30.976] <TB1> INFO: frame (failed synchr.): 0
[12:10:30.976] <TB1> INFO: idle data (no TBM trl): 0
[12:10:30.976] <TB1> INFO: no data (only TBM hdr): 0
[12:10:30.976] <TB1> INFO: TBM errors: 0
[12:10:30.976] <TB1> INFO: flawed TBM headers: 0
[12:10:30.976] <TB1> INFO: flawed TBM trailers: 0
[12:10:30.976] <TB1> INFO: event ID mismatches: 0
[12:10:30.976] <TB1> INFO: ROC errors: 0
[12:10:30.976] <TB1> INFO: missing ROC header(s): 0
[12:10:30.976] <TB1> INFO: misplaced readback start: 0
[12:10:30.976] <TB1> INFO: Pixel decoding errors: 0
[12:10:30.976] <TB1> INFO: pixel data incomplete: 0
[12:10:30.976] <TB1> INFO: pixel address: 0
[12:10:30.976] <TB1> INFO: pulse height fill bit: 0
[12:10:30.976] <TB1> INFO: buffer corruption: 0
[12:10:31.021] <TB1> INFO: ######################################################################
[12:10:31.021] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:10:31.021] <TB1> INFO: ######################################################################
[12:10:31.021] <TB1> INFO: ----------------------------------------------------------------------
[12:10:31.021] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:10:31.021] <TB1> INFO: ----------------------------------------------------------------------
[12:10:31.021] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:10:31.036] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[12:10:31.036] <TB1> INFO: run 1 of 1
[12:10:31.275] <TB1> INFO: Expecting 36608000 events.
[12:10:55.819] <TB1> INFO: 691750 events read in total (23952ms).
[12:11:18.608] <TB1> INFO: 1362950 events read in total (46741ms).
[12:11:41.936] <TB1> INFO: 2039400 events read in total (70069ms).
[12:12:05.181] <TB1> INFO: 2710800 events read in total (93314ms).
[12:12:28.116] <TB1> INFO: 3385700 events read in total (116249ms).
[12:12:51.443] <TB1> INFO: 4058850 events read in total (139576ms).
[12:13:14.712] <TB1> INFO: 4732050 events read in total (162845ms).
[12:13:38.064] <TB1> INFO: 5404200 events read in total (186197ms).
[12:14:01.115] <TB1> INFO: 6078950 events read in total (209248ms).
[12:14:24.944] <TB1> INFO: 6753000 events read in total (233077ms).
[12:14:48.718] <TB1> INFO: 7425700 events read in total (256851ms).
[12:15:12.325] <TB1> INFO: 8098950 events read in total (280458ms).
[12:15:35.561] <TB1> INFO: 8771900 events read in total (303694ms).
[12:15:59.082] <TB1> INFO: 9444700 events read in total (327215ms).
[12:16:22.654] <TB1> INFO: 10117200 events read in total (350787ms).
[12:16:45.671] <TB1> INFO: 10789850 events read in total (373804ms).
[12:17:08.722] <TB1> INFO: 11462000 events read in total (396855ms).
[12:17:31.674] <TB1> INFO: 12132650 events read in total (419807ms).
[12:17:54.691] <TB1> INFO: 12802550 events read in total (442824ms).
[12:18:17.527] <TB1> INFO: 13471400 events read in total (465660ms).
[12:18:40.470] <TB1> INFO: 14139600 events read in total (488603ms).
[12:19:03.548] <TB1> INFO: 14809200 events read in total (511681ms).
[12:19:27.378] <TB1> INFO: 15478200 events read in total (535511ms).
[12:19:50.850] <TB1> INFO: 16147850 events read in total (558983ms).
[12:20:14.767] <TB1> INFO: 16816750 events read in total (582900ms).
[12:20:38.276] <TB1> INFO: 17485900 events read in total (606409ms).
[12:21:01.237] <TB1> INFO: 18153700 events read in total (629370ms).
[12:21:24.019] <TB1> INFO: 18820150 events read in total (652152ms).
[12:21:46.786] <TB1> INFO: 19483950 events read in total (674919ms).
[12:22:09.723] <TB1> INFO: 20149200 events read in total (697856ms).
[12:22:32.714] <TB1> INFO: 20813950 events read in total (720847ms).
[12:22:55.587] <TB1> INFO: 21478750 events read in total (743720ms).
[12:23:18.800] <TB1> INFO: 22144150 events read in total (766933ms).
[12:23:41.745] <TB1> INFO: 22807650 events read in total (789878ms).
[12:24:04.646] <TB1> INFO: 23470750 events read in total (812779ms).
[12:24:27.725] <TB1> INFO: 24136100 events read in total (835858ms).
[12:24:50.402] <TB1> INFO: 24801250 events read in total (858535ms).
[12:25:13.346] <TB1> INFO: 25465400 events read in total (881479ms).
[12:25:36.362] <TB1> INFO: 26131950 events read in total (904495ms).
[12:25:59.345] <TB1> INFO: 26796550 events read in total (927478ms).
[12:26:22.104] <TB1> INFO: 27460250 events read in total (950237ms).
[12:26:44.896] <TB1> INFO: 28121850 events read in total (973029ms).
[12:27:07.802] <TB1> INFO: 28784550 events read in total (995935ms).
[12:27:30.710] <TB1> INFO: 29449700 events read in total (1018843ms).
[12:27:53.321] <TB1> INFO: 30111400 events read in total (1041454ms).
[12:28:16.382] <TB1> INFO: 30773400 events read in total (1064515ms).
[12:28:39.145] <TB1> INFO: 31438200 events read in total (1087278ms).
[12:29:02.081] <TB1> INFO: 32100650 events read in total (1110214ms).
[12:29:24.572] <TB1> INFO: 32764800 events read in total (1132705ms).
[12:29:47.714] <TB1> INFO: 33429450 events read in total (1155847ms).
[12:30:10.702] <TB1> INFO: 34091800 events read in total (1178835ms).
[12:30:33.448] <TB1> INFO: 34757400 events read in total (1201581ms).
[12:30:56.475] <TB1> INFO: 35421950 events read in total (1224608ms).
[12:31:19.215] <TB1> INFO: 36089900 events read in total (1247348ms).
[12:31:37.438] <TB1> INFO: 36608000 events read in total (1265571ms).
[12:31:37.541] <TB1> INFO: Test took 1266505ms.
[12:31:37.989] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:31:39.779] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:31:41.918] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:31:43.984] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:31:46.033] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:31:48.106] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:31:50.060] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:31:52.158] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:31:53.914] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:31:55.326] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:31:56.745] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:31:58.219] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:32:00.045] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:32:01.484] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:32:02.908] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:32:04.766] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:32:06.564] <TB1> INFO: PixTestScurves::scurves() done
[12:32:06.564] <TB1> INFO: Vcal mean: 125.18 126.39 124.36 121.53 110.71 117.83 130.06 125.60 116.28 119.55 127.57 119.23 122.74 110.38 118.65 119.02
[12:32:06.564] <TB1> INFO: Vcal RMS: 6.53 5.61 6.83 6.08 5.14 5.32 6.64 6.22 5.06 5.84 7.78 5.63 5.91 4.25 5.53 6.28
[12:32:06.564] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1295 seconds
[12:32:06.564] <TB1> INFO: Decoding statistics:
[12:32:06.564] <TB1> INFO: General information:
[12:32:06.564] <TB1> INFO: 16bit words read: 0
[12:32:06.564] <TB1> INFO: valid events total: 0
[12:32:06.564] <TB1> INFO: empty events: 0
[12:32:06.564] <TB1> INFO: valid events with pixels: 0
[12:32:06.564] <TB1> INFO: valid pixel hits: 0
[12:32:06.564] <TB1> INFO: Event errors: 0
[12:32:06.564] <TB1> INFO: start marker: 0
[12:32:06.564] <TB1> INFO: stop marker: 0
[12:32:06.564] <TB1> INFO: overflow: 0
[12:32:06.564] <TB1> INFO: invalid 5bit words: 0
[12:32:06.564] <TB1> INFO: invalid XOR eye diagram: 0
[12:32:06.564] <TB1> INFO: frame (failed synchr.): 0
[12:32:06.564] <TB1> INFO: idle data (no TBM trl): 0
[12:32:06.564] <TB1> INFO: no data (only TBM hdr): 0
[12:32:06.564] <TB1> INFO: TBM errors: 0
[12:32:06.564] <TB1> INFO: flawed TBM headers: 0
[12:32:06.564] <TB1> INFO: flawed TBM trailers: 0
[12:32:06.564] <TB1> INFO: event ID mismatches: 0
[12:32:06.564] <TB1> INFO: ROC errors: 0
[12:32:06.564] <TB1> INFO: missing ROC header(s): 0
[12:32:06.564] <TB1> INFO: misplaced readback start: 0
[12:32:06.564] <TB1> INFO: Pixel decoding errors: 0
[12:32:06.564] <TB1> INFO: pixel data incomplete: 0
[12:32:06.564] <TB1> INFO: pixel address: 0
[12:32:06.564] <TB1> INFO: pulse height fill bit: 0
[12:32:06.564] <TB1> INFO: buffer corruption: 0
[12:32:06.632] <TB1> INFO: ######################################################################
[12:32:06.632] <TB1> INFO: PixTestTrim::doTest()
[12:32:06.632] <TB1> INFO: ######################################################################
[12:32:06.633] <TB1> INFO: ----------------------------------------------------------------------
[12:32:06.633] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:32:06.633] <TB1> INFO: ----------------------------------------------------------------------
[12:32:06.676] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:32:06.676] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:32:06.689] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:32:06.689] <TB1> INFO: run 1 of 1
[12:32:06.931] <TB1> INFO: Expecting 5025280 events.
[12:32:38.607] <TB1> INFO: 827960 events read in total (31074ms).
[12:33:09.583] <TB1> INFO: 1652824 events read in total (62050ms).
[12:33:40.529] <TB1> INFO: 2474392 events read in total (92996ms).
[12:34:11.057] <TB1> INFO: 3290840 events read in total (123524ms).
[12:34:42.151] <TB1> INFO: 4105200 events read in total (154618ms).
[12:35:12.352] <TB1> INFO: 4917960 events read in total (184819ms).
[12:35:16.720] <TB1> INFO: 5025280 events read in total (189187ms).
[12:35:16.777] <TB1> INFO: Test took 190085ms.
[12:35:33.533] <TB1> INFO: ROC 0 VthrComp = 127
[12:35:33.533] <TB1> INFO: ROC 1 VthrComp = 131
[12:35:33.534] <TB1> INFO: ROC 2 VthrComp = 127
[12:35:33.534] <TB1> INFO: ROC 3 VthrComp = 128
[12:35:33.534] <TB1> INFO: ROC 4 VthrComp = 119
[12:35:33.536] <TB1> INFO: ROC 5 VthrComp = 127
[12:35:33.538] <TB1> INFO: ROC 6 VthrComp = 133
[12:35:33.538] <TB1> INFO: ROC 7 VthrComp = 126
[12:35:33.538] <TB1> INFO: ROC 8 VthrComp = 116
[12:35:33.538] <TB1> INFO: ROC 9 VthrComp = 123
[12:35:33.538] <TB1> INFO: ROC 10 VthrComp = 127
[12:35:33.538] <TB1> INFO: ROC 11 VthrComp = 128
[12:35:33.538] <TB1> INFO: ROC 12 VthrComp = 133
[12:35:33.539] <TB1> INFO: ROC 13 VthrComp = 114
[12:35:33.539] <TB1> INFO: ROC 14 VthrComp = 116
[12:35:33.539] <TB1> INFO: ROC 15 VthrComp = 124
[12:35:33.800] <TB1> INFO: Expecting 41600 events.
[12:35:37.343] <TB1> INFO: 41600 events read in total (2952ms).
[12:35:37.344] <TB1> INFO: Test took 3804ms.
[12:35:37.353] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:35:37.353] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:35:37.367] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:35:37.367] <TB1> INFO: run 1 of 1
[12:35:37.645] <TB1> INFO: Expecting 5025280 events.
[12:36:04.720] <TB1> INFO: 591344 events read in total (26480ms).
[12:36:30.986] <TB1> INFO: 1181184 events read in total (52746ms).
[12:36:57.477] <TB1> INFO: 1770872 events read in total (79237ms).
[12:37:23.535] <TB1> INFO: 2359368 events read in total (105295ms).
[12:37:49.358] <TB1> INFO: 2945552 events read in total (131118ms).
[12:38:15.664] <TB1> INFO: 3530616 events read in total (157424ms).
[12:38:42.242] <TB1> INFO: 4115128 events read in total (184002ms).
[12:39:08.463] <TB1> INFO: 4698624 events read in total (210223ms).
[12:39:23.347] <TB1> INFO: 5025280 events read in total (225107ms).
[12:39:23.453] <TB1> INFO: Test took 226086ms.
[12:39:51.604] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 59.3067 for pixel 17/79 mean/min/max = 45.5177/31.6041/59.4313
[12:39:51.604] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 58.3053 for pixel 5/13 mean/min/max = 45.8019/33.1016/58.5022
[12:39:51.605] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 62.0803 for pixel 9/7 mean/min/max = 47.2043/32.3035/62.1052
[12:39:51.605] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 57.5174 for pixel 0/16 mean/min/max = 44.8079/31.7307/57.885
[12:39:51.606] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 58.7969 for pixel 8/39 mean/min/max = 45.278/31.7298/58.8261
[12:39:51.606] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 56.8004 for pixel 0/49 mean/min/max = 44.7341/32.6396/56.8286
[12:39:51.607] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 61.4389 for pixel 3/69 mean/min/max = 48.163/34.8144/61.5116
[12:39:51.607] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 61.3191 for pixel 13/0 mean/min/max = 46.3874/31.3452/61.4295
[12:39:51.608] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 60.9712 for pixel 0/4 mean/min/max = 46.7629/32.5084/61.0175
[12:39:51.608] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 62.112 for pixel 23/4 mean/min/max = 47.0842/31.983/62.1855
[12:39:51.608] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 63.5815 for pixel 23/5 mean/min/max = 46.7966/29.7564/63.8368
[12:39:51.609] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 59.3391 for pixel 12/4 mean/min/max = 45.5536/31.6845/59.4228
[12:39:51.609] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 59.7159 for pixel 20/76 mean/min/max = 47.0749/34.1431/60.0067
[12:39:51.610] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 58.6055 for pixel 3/1 mean/min/max = 46.0615/33.2787/58.8443
[12:39:51.610] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 62.5921 for pixel 38/4 mean/min/max = 47.3797/32.0987/62.6608
[12:39:51.611] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 59.9807 for pixel 15/8 mean/min/max = 46.0401/31.9749/60.1053
[12:39:51.611] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:39:51.700] <TB1> INFO: Expecting 411648 events.
[12:40:01.262] <TB1> INFO: 411648 events read in total (8971ms).
[12:40:01.270] <TB1> INFO: Expecting 411648 events.
[12:40:10.547] <TB1> INFO: 411648 events read in total (8874ms).
[12:40:10.557] <TB1> INFO: Expecting 411648 events.
[12:40:19.913] <TB1> INFO: 411648 events read in total (8953ms).
[12:40:19.927] <TB1> INFO: Expecting 411648 events.
[12:40:29.263] <TB1> INFO: 411648 events read in total (8933ms).
[12:40:29.278] <TB1> INFO: Expecting 411648 events.
[12:40:38.643] <TB1> INFO: 411648 events read in total (8962ms).
[12:40:38.662] <TB1> INFO: Expecting 411648 events.
[12:40:47.957] <TB1> INFO: 411648 events read in total (8892ms).
[12:40:47.978] <TB1> INFO: Expecting 411648 events.
[12:40:57.347] <TB1> INFO: 411648 events read in total (8966ms).
[12:40:57.372] <TB1> INFO: Expecting 411648 events.
[12:41:06.649] <TB1> INFO: 411648 events read in total (8874ms).
[12:41:06.677] <TB1> INFO: Expecting 411648 events.
[12:41:15.971] <TB1> INFO: 411648 events read in total (8891ms).
[12:41:15.000] <TB1> INFO: Expecting 411648 events.
[12:41:25.321] <TB1> INFO: 411648 events read in total (8918ms).
[12:41:25.361] <TB1> INFO: Expecting 411648 events.
[12:41:34.716] <TB1> INFO: 411648 events read in total (8952ms).
[12:41:34.752] <TB1> INFO: Expecting 411648 events.
[12:41:44.080] <TB1> INFO: 411648 events read in total (8925ms).
[12:41:44.121] <TB1> INFO: Expecting 411648 events.
[12:41:53.475] <TB1> INFO: 411648 events read in total (8950ms).
[12:41:53.588] <TB1> INFO: Expecting 411648 events.
[12:42:02.943] <TB1> INFO: 411648 events read in total (8953ms).
[12:42:03.006] <TB1> INFO: Expecting 411648 events.
[12:42:12.278] <TB1> INFO: 411648 events read in total (8869ms).
[12:42:12.326] <TB1> INFO: Expecting 411648 events.
[12:42:21.460] <TB1> INFO: 411648 events read in total (8730ms).
[12:42:21.625] <TB1> INFO: Test took 150014ms.
[12:42:22.506] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:42:22.521] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:42:22.521] <TB1> INFO: run 1 of 1
[12:42:22.820] <TB1> INFO: Expecting 5025280 events.
[12:42:49.768] <TB1> INFO: 587264 events read in total (26356ms).
[12:43:15.948] <TB1> INFO: 1172896 events read in total (52536ms).
[12:43:42.205] <TB1> INFO: 1758232 events read in total (78794ms).
[12:44:08.267] <TB1> INFO: 2341496 events read in total (104855ms).
[12:44:34.769] <TB1> INFO: 2924480 events read in total (131357ms).
[12:45:01.493] <TB1> INFO: 3509200 events read in total (158081ms).
[12:45:28.109] <TB1> INFO: 4093832 events read in total (184697ms).
[12:45:54.466] <TB1> INFO: 4678864 events read in total (211054ms).
[12:46:10.984] <TB1> INFO: 5025280 events read in total (227572ms).
[12:46:11.118] <TB1> INFO: Test took 228598ms.
[12:46:38.211] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 6.957692 .. 147.840109
[12:46:38.448] <TB1> INFO: Expecting 208000 events.
[12:46:48.062] <TB1> INFO: 208000 events read in total (9022ms).
[12:46:48.063] <TB1> INFO: Test took 9851ms.
[12:46:48.112] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 6 .. 157 (-1/-1) hits flags = 528 (plus default)
[12:46:48.125] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:46:48.125] <TB1> INFO: run 1 of 1
[12:46:48.403] <TB1> INFO: Expecting 5058560 events.
[12:47:14.595] <TB1> INFO: 577328 events read in total (25600ms).
[12:47:40.499] <TB1> INFO: 1155056 events read in total (51504ms).
[12:48:06.394] <TB1> INFO: 1732808 events read in total (77399ms).
[12:48:31.888] <TB1> INFO: 2310112 events read in total (102893ms).
[12:48:57.869] <TB1> INFO: 2887352 events read in total (128874ms).
[12:49:23.647] <TB1> INFO: 3464016 events read in total (154652ms).
[12:49:49.195] <TB1> INFO: 4040064 events read in total (180200ms).
[12:50:15.844] <TB1> INFO: 4615536 events read in total (206849ms).
[12:50:36.593] <TB1> INFO: 5058560 events read in total (227598ms).
[12:50:36.690] <TB1> INFO: Test took 228566ms.
[12:51:05.335] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 28.475484 .. 47.585559
[12:51:05.576] <TB1> INFO: Expecting 208000 events.
[12:51:15.553] <TB1> INFO: 208000 events read in total (9386ms).
[12:51:15.554] <TB1> INFO: Test took 10218ms.
[12:51:15.623] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 18 .. 57 (-1/-1) hits flags = 528 (plus default)
[12:51:15.635] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:51:15.635] <TB1> INFO: run 1 of 1
[12:51:15.914] <TB1> INFO: Expecting 1331200 events.
[12:51:45.049] <TB1> INFO: 647864 events read in total (28544ms).
[12:52:12.236] <TB1> INFO: 1293416 events read in total (55731ms).
[12:52:14.393] <TB1> INFO: 1331200 events read in total (57888ms).
[12:52:14.430] <TB1> INFO: Test took 58795ms.
[12:52:28.819] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 24.728280 .. 47.746032
[12:52:29.093] <TB1> INFO: Expecting 208000 events.
[12:52:38.754] <TB1> INFO: 208000 events read in total (9070ms).
[12:52:38.755] <TB1> INFO: Test took 9934ms.
[12:52:38.802] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 14 .. 57 (-1/-1) hits flags = 528 (plus default)
[12:52:38.815] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:52:38.815] <TB1> INFO: run 1 of 1
[12:52:39.094] <TB1> INFO: Expecting 1464320 events.
[12:53:07.590] <TB1> INFO: 664648 events read in total (27904ms).
[12:53:35.545] <TB1> INFO: 1328600 events read in total (55859ms).
[12:53:41.766] <TB1> INFO: 1464320 events read in total (62080ms).
[12:53:41.809] <TB1> INFO: Test took 62994ms.
[12:53:54.869] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 24.263446 .. 49.560730
[12:53:55.113] <TB1> INFO: Expecting 208000 events.
[12:54:04.743] <TB1> INFO: 208000 events read in total (9038ms).
[12:54:04.744] <TB1> INFO: Test took 9873ms.
[12:54:04.793] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 59 (-1/-1) hits flags = 528 (plus default)
[12:54:04.806] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:54:04.806] <TB1> INFO: run 1 of 1
[12:54:05.084] <TB1> INFO: Expecting 1530880 events.
[12:54:33.436] <TB1> INFO: 657864 events read in total (27761ms).
[12:55:01.125] <TB1> INFO: 1315168 events read in total (55450ms).
[12:55:10.657] <TB1> INFO: 1530880 events read in total (64982ms).
[12:55:10.690] <TB1> INFO: Test took 65885ms.
[12:55:24.196] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:55:24.196] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:55:24.209] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:55:24.209] <TB1> INFO: run 1 of 1
[12:55:24.470] <TB1> INFO: Expecting 1364480 events.
[12:55:52.736] <TB1> INFO: 668568 events read in total (27674ms).
[12:56:21.718] <TB1> INFO: 1337152 events read in total (56656ms).
[12:56:23.252] <TB1> INFO: 1364480 events read in total (58191ms).
[12:56:23.280] <TB1> INFO: Test took 59072ms.
[12:56:35.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C0.dat
[12:56:35.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C1.dat
[12:56:35.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C2.dat
[12:56:35.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C3.dat
[12:56:35.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C4.dat
[12:56:35.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C5.dat
[12:56:35.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C6.dat
[12:56:35.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C7.dat
[12:56:35.470] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C8.dat
[12:56:35.471] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C9.dat
[12:56:35.471] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C10.dat
[12:56:35.471] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C11.dat
[12:56:35.471] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C12.dat
[12:56:35.471] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C13.dat
[12:56:35.471] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C14.dat
[12:56:35.471] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C15.dat
[12:56:35.471] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C0.dat
[12:56:35.480] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C1.dat
[12:56:35.485] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C2.dat
[12:56:35.491] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C3.dat
[12:56:35.496] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C4.dat
[12:56:35.501] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C5.dat
[12:56:35.506] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C6.dat
[12:56:35.511] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C7.dat
[12:56:35.516] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C8.dat
[12:56:35.521] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C9.dat
[12:56:35.526] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C10.dat
[12:56:35.531] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C11.dat
[12:56:35.536] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C12.dat
[12:56:35.541] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C13.dat
[12:56:35.546] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C14.dat
[12:56:35.552] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C15.dat
[12:56:35.557] <TB1> INFO: PixTestTrim::trimTest() done
[12:56:35.557] <TB1> INFO: vtrim: 121 129 129 101 137 118 155 141 121 124 131 135 147 135 136 136
[12:56:35.557] <TB1> INFO: vthrcomp: 127 131 127 128 119 127 133 126 116 123 127 128 133 114 116 124
[12:56:35.557] <TB1> INFO: vcal mean: 34.97 35.03 35.35 35.08 34.98 35.02 35.04 35.06 35.01 35.01 35.21 34.97 35.03 35.05 35.07 34.98
[12:56:35.557] <TB1> INFO: vcal RMS: 1.03 1.00 1.44 0.98 1.13 0.99 1.03 1.18 1.01 1.09 1.34 1.03 1.08 1.02 1.09 1.08
[12:56:35.557] <TB1> INFO: bits mean: 9.84 9.20 9.46 9.01 9.66 9.60 8.93 9.73 8.91 9.16 9.79 9.70 9.14 9.52 9.32 9.48
[12:56:35.557] <TB1> INFO: bits RMS: 2.66 2.68 2.71 3.08 2.72 2.73 2.45 2.76 2.91 2.79 2.78 2.72 2.55 2.62 2.68 2.75
[12:56:35.565] <TB1> INFO: ----------------------------------------------------------------------
[12:56:35.565] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:56:35.565] <TB1> INFO: ----------------------------------------------------------------------
[12:56:35.567] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:56:35.583] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:56:35.583] <TB1> INFO: run 1 of 1
[12:56:35.823] <TB1> INFO: Expecting 4160000 events.
[12:57:08.681] <TB1> INFO: 755980 events read in total (32266ms).
[12:57:40.638] <TB1> INFO: 1507985 events read in total (64223ms).
[12:58:12.622] <TB1> INFO: 2254505 events read in total (96207ms).
[12:58:44.389] <TB1> INFO: 2996530 events read in total (127975ms).
[12:59:16.540] <TB1> INFO: 3737145 events read in total (160125ms).
[12:59:34.938] <TB1> INFO: 4160000 events read in total (178523ms).
[12:59:35.018] <TB1> INFO: Test took 179435ms.
[13:00:01.610] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[13:00:01.623] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:00:01.623] <TB1> INFO: run 1 of 1
[13:00:01.860] <TB1> INFO: Expecting 4326400 events.
[13:00:33.830] <TB1> INFO: 723645 events read in total (31379ms).
[13:01:05.500] <TB1> INFO: 1444055 events read in total (63049ms).
[13:01:36.805] <TB1> INFO: 2160235 events read in total (94354ms).
[13:02:08.267] <TB1> INFO: 2871370 events read in total (125816ms).
[13:02:38.954] <TB1> INFO: 3582140 events read in total (156503ms).
[13:03:10.211] <TB1> INFO: 4294070 events read in total (187760ms).
[13:03:12.148] <TB1> INFO: 4326400 events read in total (189697ms).
[13:03:12.242] <TB1> INFO: Test took 190619ms.
[13:03:38.626] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 200 (-1/-1) hits flags = 528 (plus default)
[13:03:38.639] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:03:38.639] <TB1> INFO: run 1 of 1
[13:03:38.875] <TB1> INFO: Expecting 4180800 events.
[13:04:11.014] <TB1> INFO: 732910 events read in total (31547ms).
[13:04:42.423] <TB1> INFO: 1461990 events read in total (62956ms).
[13:05:13.845] <TB1> INFO: 2186870 events read in total (94378ms).
[13:05:45.326] <TB1> INFO: 2906930 events read in total (125859ms).
[13:06:16.834] <TB1> INFO: 3625760 events read in total (157367ms).
[13:06:41.264] <TB1> INFO: 4180800 events read in total (181797ms).
[13:06:41.372] <TB1> INFO: Test took 182733ms.
[13:07:07.970] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 200 (-1/-1) hits flags = 528 (plus default)
[13:07:07.983] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:07:07.983] <TB1> INFO: run 1 of 1
[13:07:08.240] <TB1> INFO: Expecting 4180800 events.
[13:07:41.108] <TB1> INFO: 732620 events read in total (32277ms).
[13:08:12.936] <TB1> INFO: 1462170 events read in total (64105ms).
[13:08:44.823] <TB1> INFO: 2187115 events read in total (95992ms).
[13:09:16.510] <TB1> INFO: 2906930 events read in total (127679ms).
[13:09:48.065] <TB1> INFO: 3626310 events read in total (159234ms).
[13:10:12.298] <TB1> INFO: 4180800 events read in total (183467ms).
[13:10:12.397] <TB1> INFO: Test took 184413ms.
[13:10:39.975] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 200 (-1/-1) hits flags = 528 (plus default)
[13:10:39.989] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:10:39.989] <TB1> INFO: run 1 of 1
[13:10:40.267] <TB1> INFO: Expecting 4180800 events.
[13:11:12.405] <TB1> INFO: 733160 events read in total (31546ms).
[13:11:43.667] <TB1> INFO: 1462935 events read in total (62808ms).
[13:12:15.069] <TB1> INFO: 2187695 events read in total (94210ms).
[13:12:46.093] <TB1> INFO: 2907455 events read in total (125234ms).
[13:13:17.730] <TB1> INFO: 3627025 events read in total (156871ms).
[13:13:42.180] <TB1> INFO: 4180800 events read in total (181321ms).
[13:13:42.280] <TB1> INFO: Test took 182290ms.
[13:14:11.014] <TB1> INFO: PixTestTrim::trimBitTest() done
[13:14:11.015] <TB1> INFO: PixTestTrim::doTest() done, duration: 2524 seconds
[13:14:11.015] <TB1> INFO: Decoding statistics:
[13:14:11.015] <TB1> INFO: General information:
[13:14:11.015] <TB1> INFO: 16bit words read: 0
[13:14:11.015] <TB1> INFO: valid events total: 0
[13:14:11.015] <TB1> INFO: empty events: 0
[13:14:11.015] <TB1> INFO: valid events with pixels: 0
[13:14:11.015] <TB1> INFO: valid pixel hits: 0
[13:14:11.015] <TB1> INFO: Event errors: 0
[13:14:11.015] <TB1> INFO: start marker: 0
[13:14:11.015] <TB1> INFO: stop marker: 0
[13:14:11.015] <TB1> INFO: overflow: 0
[13:14:11.015] <TB1> INFO: invalid 5bit words: 0
[13:14:11.015] <TB1> INFO: invalid XOR eye diagram: 0
[13:14:11.015] <TB1> INFO: frame (failed synchr.): 0
[13:14:11.015] <TB1> INFO: idle data (no TBM trl): 0
[13:14:11.015] <TB1> INFO: no data (only TBM hdr): 0
[13:14:11.015] <TB1> INFO: TBM errors: 0
[13:14:11.015] <TB1> INFO: flawed TBM headers: 0
[13:14:11.015] <TB1> INFO: flawed TBM trailers: 0
[13:14:11.015] <TB1> INFO: event ID mismatches: 0
[13:14:11.015] <TB1> INFO: ROC errors: 0
[13:14:11.015] <TB1> INFO: missing ROC header(s): 0
[13:14:11.015] <TB1> INFO: misplaced readback start: 0
[13:14:11.015] <TB1> INFO: Pixel decoding errors: 0
[13:14:11.015] <TB1> INFO: pixel data incomplete: 0
[13:14:11.015] <TB1> INFO: pixel address: 0
[13:14:11.015] <TB1> INFO: pulse height fill bit: 0
[13:14:11.015] <TB1> INFO: buffer corruption: 0
[13:14:11.733] <TB1> INFO: ######################################################################
[13:14:11.733] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:14:11.733] <TB1> INFO: ######################################################################
[13:14:11.983] <TB1> INFO: Expecting 41600 events.
[13:14:15.477] <TB1> INFO: 41600 events read in total (2903ms).
[13:14:15.478] <TB1> INFO: Test took 3743ms.
[13:14:15.920] <TB1> INFO: Expecting 41600 events.
[13:14:19.396] <TB1> INFO: 41600 events read in total (2884ms).
[13:14:19.398] <TB1> INFO: Test took 3717ms.
[13:14:19.687] <TB1> INFO: Expecting 41600 events.
[13:14:23.210] <TB1> INFO: 41600 events read in total (2932ms).
[13:14:23.212] <TB1> INFO: Test took 3790ms.
[13:14:23.504] <TB1> INFO: Expecting 41600 events.
[13:14:27.016] <TB1> INFO: 41600 events read in total (2921ms).
[13:14:27.017] <TB1> INFO: Test took 3778ms.
[13:14:27.307] <TB1> INFO: Expecting 41600 events.
[13:14:30.832] <TB1> INFO: 41600 events read in total (2933ms).
[13:14:30.833] <TB1> INFO: Test took 3791ms.
[13:14:31.127] <TB1> INFO: Expecting 41600 events.
[13:14:34.741] <TB1> INFO: 41600 events read in total (3022ms).
[13:14:34.742] <TB1> INFO: Test took 3883ms.
[13:14:35.032] <TB1> INFO: Expecting 41600 events.
[13:14:38.600] <TB1> INFO: 41600 events read in total (2978ms).
[13:14:38.602] <TB1> INFO: Test took 3835ms.
[13:14:38.917] <TB1> INFO: Expecting 41600 events.
[13:14:42.461] <TB1> INFO: 41600 events read in total (2952ms).
[13:14:42.462] <TB1> INFO: Test took 3836ms.
[13:14:42.753] <TB1> INFO: Expecting 41600 events.
[13:14:46.256] <TB1> INFO: 41600 events read in total (2911ms).
[13:14:46.257] <TB1> INFO: Test took 3769ms.
[13:14:46.547] <TB1> INFO: Expecting 41600 events.
[13:14:50.056] <TB1> INFO: 41600 events read in total (2917ms).
[13:14:50.057] <TB1> INFO: Test took 3776ms.
[13:14:50.347] <TB1> INFO: Expecting 41600 events.
[13:14:53.864] <TB1> INFO: 41600 events read in total (2926ms).
[13:14:53.865] <TB1> INFO: Test took 3784ms.
[13:14:54.155] <TB1> INFO: Expecting 41600 events.
[13:14:57.728] <TB1> INFO: 41600 events read in total (2981ms).
[13:14:57.729] <TB1> INFO: Test took 3840ms.
[13:14:58.019] <TB1> INFO: Expecting 41600 events.
[13:15:01.541] <TB1> INFO: 41600 events read in total (2930ms).
[13:15:01.543] <TB1> INFO: Test took 3790ms.
[13:15:01.836] <TB1> INFO: Expecting 41600 events.
[13:15:05.430] <TB1> INFO: 41600 events read in total (3002ms).
[13:15:05.431] <TB1> INFO: Test took 3861ms.
[13:15:05.721] <TB1> INFO: Expecting 41600 events.
[13:15:09.318] <TB1> INFO: 41600 events read in total (3006ms).
[13:15:09.319] <TB1> INFO: Test took 3864ms.
[13:15:09.622] <TB1> INFO: Expecting 41600 events.
[13:15:13.200] <TB1> INFO: 41600 events read in total (2986ms).
[13:15:13.202] <TB1> INFO: Test took 3858ms.
[13:15:13.493] <TB1> INFO: Expecting 41600 events.
[13:15:16.973] <TB1> INFO: 41600 events read in total (2888ms).
[13:15:16.975] <TB1> INFO: Test took 3748ms.
[13:15:17.267] <TB1> INFO: Expecting 41600 events.
[13:15:20.804] <TB1> INFO: 41600 events read in total (2945ms).
[13:15:20.805] <TB1> INFO: Test took 3803ms.
[13:15:21.095] <TB1> INFO: Expecting 41600 events.
[13:15:24.593] <TB1> INFO: 41600 events read in total (2906ms).
[13:15:24.594] <TB1> INFO: Test took 3765ms.
[13:15:24.887] <TB1> INFO: Expecting 41600 events.
[13:15:28.398] <TB1> INFO: 41600 events read in total (2919ms).
[13:15:28.399] <TB1> INFO: Test took 3777ms.
[13:15:28.708] <TB1> INFO: Expecting 41600 events.
[13:15:32.283] <TB1> INFO: 41600 events read in total (2983ms).
[13:15:32.284] <TB1> INFO: Test took 3860ms.
[13:15:32.573] <TB1> INFO: Expecting 41600 events.
[13:15:36.050] <TB1> INFO: 41600 events read in total (2885ms).
[13:15:36.051] <TB1> INFO: Test took 3743ms.
[13:15:36.344] <TB1> INFO: Expecting 41600 events.
[13:15:39.918] <TB1> INFO: 41600 events read in total (2983ms).
[13:15:39.919] <TB1> INFO: Test took 3841ms.
[13:15:40.208] <TB1> INFO: Expecting 41600 events.
[13:15:43.750] <TB1> INFO: 41600 events read in total (2950ms).
[13:15:43.751] <TB1> INFO: Test took 3808ms.
[13:15:44.041] <TB1> INFO: Expecting 41600 events.
[13:15:47.655] <TB1> INFO: 41600 events read in total (3023ms).
[13:15:47.656] <TB1> INFO: Test took 3881ms.
[13:15:47.963] <TB1> INFO: Expecting 41600 events.
[13:15:51.584] <TB1> INFO: 41600 events read in total (3029ms).
[13:15:51.585] <TB1> INFO: Test took 3904ms.
[13:15:51.875] <TB1> INFO: Expecting 41600 events.
[13:15:55.382] <TB1> INFO: 41600 events read in total (2915ms).
[13:15:55.383] <TB1> INFO: Test took 3773ms.
[13:15:55.673] <TB1> INFO: Expecting 41600 events.
[13:15:59.244] <TB1> INFO: 41600 events read in total (2979ms).
[13:15:59.245] <TB1> INFO: Test took 3838ms.
[13:15:59.534] <TB1> INFO: Expecting 41600 events.
[13:16:03.104] <TB1> INFO: 41600 events read in total (2978ms).
[13:16:03.105] <TB1> INFO: Test took 3835ms.
[13:16:03.401] <TB1> INFO: Expecting 41600 events.
[13:16:07.044] <TB1> INFO: 41600 events read in total (3052ms).
[13:16:07.045] <TB1> INFO: Test took 3910ms.
[13:16:07.336] <TB1> INFO: Expecting 2560 events.
[13:16:08.227] <TB1> INFO: 2560 events read in total (299ms).
[13:16:08.228] <TB1> INFO: Test took 1170ms.
[13:16:08.536] <TB1> INFO: Expecting 2560 events.
[13:16:09.423] <TB1> INFO: 2560 events read in total (295ms).
[13:16:09.424] <TB1> INFO: Test took 1196ms.
[13:16:09.731] <TB1> INFO: Expecting 2560 events.
[13:16:10.619] <TB1> INFO: 2560 events read in total (296ms).
[13:16:10.620] <TB1> INFO: Test took 1196ms.
[13:16:10.927] <TB1> INFO: Expecting 2560 events.
[13:16:11.815] <TB1> INFO: 2560 events read in total (298ms).
[13:16:11.816] <TB1> INFO: Test took 1195ms.
[13:16:12.124] <TB1> INFO: Expecting 2560 events.
[13:16:13.004] <TB1> INFO: 2560 events read in total (288ms).
[13:16:13.004] <TB1> INFO: Test took 1188ms.
[13:16:13.312] <TB1> INFO: Expecting 2560 events.
[13:16:14.197] <TB1> INFO: 2560 events read in total (293ms).
[13:16:14.197] <TB1> INFO: Test took 1192ms.
[13:16:14.504] <TB1> INFO: Expecting 2560 events.
[13:16:15.397] <TB1> INFO: 2560 events read in total (301ms).
[13:16:15.397] <TB1> INFO: Test took 1199ms.
[13:16:15.706] <TB1> INFO: Expecting 2560 events.
[13:16:16.588] <TB1> INFO: 2560 events read in total (290ms).
[13:16:16.588] <TB1> INFO: Test took 1190ms.
[13:16:16.895] <TB1> INFO: Expecting 2560 events.
[13:16:17.779] <TB1> INFO: 2560 events read in total (292ms).
[13:16:17.780] <TB1> INFO: Test took 1191ms.
[13:16:18.087] <TB1> INFO: Expecting 2560 events.
[13:16:18.969] <TB1> INFO: 2560 events read in total (290ms).
[13:16:18.969] <TB1> INFO: Test took 1188ms.
[13:16:19.277] <TB1> INFO: Expecting 2560 events.
[13:16:20.166] <TB1> INFO: 2560 events read in total (296ms).
[13:16:20.166] <TB1> INFO: Test took 1196ms.
[13:16:20.473] <TB1> INFO: Expecting 2560 events.
[13:16:21.364] <TB1> INFO: 2560 events read in total (299ms).
[13:16:21.364] <TB1> INFO: Test took 1197ms.
[13:16:21.672] <TB1> INFO: Expecting 2560 events.
[13:16:22.565] <TB1> INFO: 2560 events read in total (301ms).
[13:16:22.566] <TB1> INFO: Test took 1201ms.
[13:16:22.873] <TB1> INFO: Expecting 2560 events.
[13:16:23.766] <TB1> INFO: 2560 events read in total (301ms).
[13:16:23.767] <TB1> INFO: Test took 1201ms.
[13:16:24.074] <TB1> INFO: Expecting 2560 events.
[13:16:24.966] <TB1> INFO: 2560 events read in total (301ms).
[13:16:24.967] <TB1> INFO: Test took 1200ms.
[13:16:25.275] <TB1> INFO: Expecting 2560 events.
[13:16:26.166] <TB1> INFO: 2560 events read in total (299ms).
[13:16:26.166] <TB1> INFO: Test took 1199ms.
[13:16:26.172] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:16:26.474] <TB1> INFO: Expecting 655360 events.
[13:16:41.741] <TB1> INFO: 655360 events read in total (14676ms).
[13:16:41.756] <TB1> INFO: Expecting 655360 events.
[13:16:56.513] <TB1> INFO: 655360 events read in total (14354ms).
[13:16:56.530] <TB1> INFO: Expecting 655360 events.
[13:17:11.271] <TB1> INFO: 655360 events read in total (14338ms).
[13:17:11.292] <TB1> INFO: Expecting 655360 events.
[13:17:25.958] <TB1> INFO: 655360 events read in total (14263ms).
[13:17:25.984] <TB1> INFO: Expecting 655360 events.
[13:17:40.798] <TB1> INFO: 655360 events read in total (14411ms).
[13:17:40.837] <TB1> INFO: Expecting 655360 events.
[13:17:55.653] <TB1> INFO: 655360 events read in total (14413ms).
[13:17:55.689] <TB1> INFO: Expecting 655360 events.
[13:18:10.538] <TB1> INFO: 655360 events read in total (14446ms).
[13:18:10.578] <TB1> INFO: Expecting 655360 events.
[13:18:25.347] <TB1> INFO: 655360 events read in total (14365ms).
[13:18:25.391] <TB1> INFO: Expecting 655360 events.
[13:18:40.191] <TB1> INFO: 655360 events read in total (14397ms).
[13:18:40.253] <TB1> INFO: Expecting 655360 events.
[13:18:55.107] <TB1> INFO: 655360 events read in total (14451ms).
[13:18:55.203] <TB1> INFO: Expecting 655360 events.
[13:19:10.009] <TB1> INFO: 655360 events read in total (14403ms).
[13:19:10.157] <TB1> INFO: Expecting 655360 events.
[13:19:24.971] <TB1> INFO: 655360 events read in total (14411ms).
[13:19:25.070] <TB1> INFO: Expecting 655360 events.
[13:19:39.790] <TB1> INFO: 655360 events read in total (14317ms).
[13:19:39.887] <TB1> INFO: Expecting 655360 events.
[13:19:54.822] <TB1> INFO: 655360 events read in total (14532ms).
[13:19:54.951] <TB1> INFO: Expecting 655360 events.
[13:20:09.777] <TB1> INFO: 655360 events read in total (14423ms).
[13:20:09.878] <TB1> INFO: Expecting 655360 events.
[13:20:24.728] <TB1> INFO: 655360 events read in total (14447ms).
[13:20:24.831] <TB1> INFO: Test took 238659ms.
[13:20:24.930] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:25.184] <TB1> INFO: Expecting 655360 events.
[13:20:40.262] <TB1> INFO: 655360 events read in total (14486ms).
[13:20:40.275] <TB1> INFO: Expecting 655360 events.
[13:20:55.009] <TB1> INFO: 655360 events read in total (14331ms).
[13:20:55.026] <TB1> INFO: Expecting 655360 events.
[13:21:09.525] <TB1> INFO: 655360 events read in total (14096ms).
[13:21:09.552] <TB1> INFO: Expecting 655360 events.
[13:21:24.405] <TB1> INFO: 655360 events read in total (14450ms).
[13:21:24.430] <TB1> INFO: Expecting 655360 events.
[13:21:39.104] <TB1> INFO: 655360 events read in total (14270ms).
[13:21:39.134] <TB1> INFO: Expecting 655360 events.
[13:21:53.655] <TB1> INFO: 655360 events read in total (14118ms).
[13:21:53.690] <TB1> INFO: Expecting 655360 events.
[13:22:08.327] <TB1> INFO: 655360 events read in total (14234ms).
[13:22:08.366] <TB1> INFO: Expecting 655360 events.
[13:22:22.940] <TB1> INFO: 655360 events read in total (14171ms).
[13:22:22.982] <TB1> INFO: Expecting 655360 events.
[13:22:37.542] <TB1> INFO: 655360 events read in total (14156ms).
[13:22:37.593] <TB1> INFO: Expecting 655360 events.
[13:22:51.970] <TB1> INFO: 655360 events read in total (13974ms).
[13:22:52.054] <TB1> INFO: Expecting 655360 events.
[13:23:06.565] <TB1> INFO: 655360 events read in total (14108ms).
[13:23:06.635] <TB1> INFO: Expecting 655360 events.
[13:23:21.459] <TB1> INFO: 655360 events read in total (14421ms).
[13:23:21.561] <TB1> INFO: Expecting 655360 events.
[13:23:36.244] <TB1> INFO: 655360 events read in total (14280ms).
[13:23:36.365] <TB1> INFO: Expecting 655360 events.
[13:23:51.031] <TB1> INFO: 655360 events read in total (14263ms).
[13:23:51.116] <TB1> INFO: Expecting 655360 events.
[13:24:05.610] <TB1> INFO: 655360 events read in total (14091ms).
[13:24:05.731] <TB1> INFO: Expecting 655360 events.
[13:24:20.306] <TB1> INFO: 655360 events read in total (14172ms).
[13:24:20.441] <TB1> INFO: Test took 235511ms.
[13:24:20.624] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.630] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.636] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.642] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.648] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.654] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.661] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:24:20.667] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:24:20.673] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:24:20.680] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:24:20.686] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:24:20.692] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.699] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.705] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:24:20.712] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:24:20.718] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:24:20.724] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:24:20.730] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.736] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.742] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.748] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.754] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.760] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.766] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.772] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:24:20.778] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:24:20.814] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C0.dat
[13:24:20.814] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C1.dat
[13:24:20.814] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C2.dat
[13:24:20.815] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C3.dat
[13:24:20.815] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C4.dat
[13:24:20.815] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C5.dat
[13:24:20.815] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C6.dat
[13:24:20.815] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C7.dat
[13:24:20.815] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C8.dat
[13:24:20.815] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C9.dat
[13:24:20.816] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C10.dat
[13:24:20.816] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C11.dat
[13:24:20.816] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C12.dat
[13:24:20.816] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C13.dat
[13:24:20.816] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C14.dat
[13:24:20.816] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C15.dat
[13:24:21.056] <TB1> INFO: Expecting 41600 events.
[13:24:24.302] <TB1> INFO: 41600 events read in total (2655ms).
[13:24:24.303] <TB1> INFO: Test took 3484ms.
[13:24:24.761] <TB1> INFO: Expecting 41600 events.
[13:24:27.934] <TB1> INFO: 41600 events read in total (2582ms).
[13:24:27.935] <TB1> INFO: Test took 3417ms.
[13:24:28.384] <TB1> INFO: Expecting 41600 events.
[13:24:31.622] <TB1> INFO: 41600 events read in total (2646ms).
[13:24:31.623] <TB1> INFO: Test took 3474ms.
[13:24:31.838] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:31.928] <TB1> INFO: Expecting 2560 events.
[13:24:32.824] <TB1> INFO: 2560 events read in total (305ms).
[13:24:32.825] <TB1> INFO: Test took 987ms.
[13:24:32.827] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:33.134] <TB1> INFO: Expecting 2560 events.
[13:24:34.025] <TB1> INFO: 2560 events read in total (299ms).
[13:24:34.025] <TB1> INFO: Test took 1198ms.
[13:24:34.027] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:34.334] <TB1> INFO: Expecting 2560 events.
[13:24:35.224] <TB1> INFO: 2560 events read in total (299ms).
[13:24:35.225] <TB1> INFO: Test took 1198ms.
[13:24:35.227] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:35.533] <TB1> INFO: Expecting 2560 events.
[13:24:36.422] <TB1> INFO: 2560 events read in total (297ms).
[13:24:36.423] <TB1> INFO: Test took 1196ms.
[13:24:36.425] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:36.731] <TB1> INFO: Expecting 2560 events.
[13:24:37.622] <TB1> INFO: 2560 events read in total (299ms).
[13:24:37.623] <TB1> INFO: Test took 1198ms.
[13:24:37.625] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:37.930] <TB1> INFO: Expecting 2560 events.
[13:24:38.827] <TB1> INFO: 2560 events read in total (305ms).
[13:24:38.828] <TB1> INFO: Test took 1203ms.
[13:24:38.830] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:39.135] <TB1> INFO: Expecting 2560 events.
[13:24:40.028] <TB1> INFO: 2560 events read in total (301ms).
[13:24:40.029] <TB1> INFO: Test took 1199ms.
[13:24:40.031] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:40.336] <TB1> INFO: Expecting 2560 events.
[13:24:41.227] <TB1> INFO: 2560 events read in total (299ms).
[13:24:41.227] <TB1> INFO: Test took 1196ms.
[13:24:41.230] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:41.535] <TB1> INFO: Expecting 2560 events.
[13:24:42.425] <TB1> INFO: 2560 events read in total (298ms).
[13:24:42.425] <TB1> INFO: Test took 1195ms.
[13:24:42.430] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:42.734] <TB1> INFO: Expecting 2560 events.
[13:24:43.624] <TB1> INFO: 2560 events read in total (299ms).
[13:24:43.625] <TB1> INFO: Test took 1195ms.
[13:24:43.628] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:43.932] <TB1> INFO: Expecting 2560 events.
[13:24:44.822] <TB1> INFO: 2560 events read in total (298ms).
[13:24:44.823] <TB1> INFO: Test took 1195ms.
[13:24:44.826] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:45.131] <TB1> INFO: Expecting 2560 events.
[13:24:46.018] <TB1> INFO: 2560 events read in total (295ms).
[13:24:46.019] <TB1> INFO: Test took 1193ms.
[13:24:46.022] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:46.326] <TB1> INFO: Expecting 2560 events.
[13:24:47.214] <TB1> INFO: 2560 events read in total (296ms).
[13:24:47.215] <TB1> INFO: Test took 1193ms.
[13:24:47.217] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:47.521] <TB1> INFO: Expecting 2560 events.
[13:24:48.411] <TB1> INFO: 2560 events read in total (298ms).
[13:24:48.411] <TB1> INFO: Test took 1194ms.
[13:24:48.416] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:48.720] <TB1> INFO: Expecting 2560 events.
[13:24:49.607] <TB1> INFO: 2560 events read in total (296ms).
[13:24:49.608] <TB1> INFO: Test took 1193ms.
[13:24:49.615] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:49.915] <TB1> INFO: Expecting 2560 events.
[13:24:50.803] <TB1> INFO: 2560 events read in total (296ms).
[13:24:50.804] <TB1> INFO: Test took 1189ms.
[13:24:50.807] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:51.112] <TB1> INFO: Expecting 2560 events.
[13:24:51.999] <TB1> INFO: 2560 events read in total (295ms).
[13:24:51.999] <TB1> INFO: Test took 1192ms.
[13:24:51.001] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:52.308] <TB1> INFO: Expecting 2560 events.
[13:24:53.201] <TB1> INFO: 2560 events read in total (301ms).
[13:24:53.202] <TB1> INFO: Test took 1201ms.
[13:24:53.205] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:53.510] <TB1> INFO: Expecting 2560 events.
[13:24:54.403] <TB1> INFO: 2560 events read in total (301ms).
[13:24:54.404] <TB1> INFO: Test took 1199ms.
[13:24:54.409] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:54.713] <TB1> INFO: Expecting 2560 events.
[13:24:55.601] <TB1> INFO: 2560 events read in total (297ms).
[13:24:55.602] <TB1> INFO: Test took 1193ms.
[13:24:55.604] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:55.910] <TB1> INFO: Expecting 2560 events.
[13:24:56.798] <TB1> INFO: 2560 events read in total (296ms).
[13:24:56.800] <TB1> INFO: Test took 1196ms.
[13:24:56.803] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:57.106] <TB1> INFO: Expecting 2560 events.
[13:24:57.000] <TB1> INFO: 2560 events read in total (302ms).
[13:24:57.000] <TB1> INFO: Test took 1197ms.
[13:24:58.004] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:58.308] <TB1> INFO: Expecting 2560 events.
[13:24:59.198] <TB1> INFO: 2560 events read in total (298ms).
[13:24:59.199] <TB1> INFO: Test took 1196ms.
[13:24:59.204] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:24:59.508] <TB1> INFO: Expecting 2560 events.
[13:25:00.389] <TB1> INFO: 2560 events read in total (290ms).
[13:25:00.389] <TB1> INFO: Test took 1185ms.
[13:25:00.393] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:00.696] <TB1> INFO: Expecting 2560 events.
[13:25:01.588] <TB1> INFO: 2560 events read in total (300ms).
[13:25:01.588] <TB1> INFO: Test took 1196ms.
[13:25:01.593] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:01.897] <TB1> INFO: Expecting 2560 events.
[13:25:02.789] <TB1> INFO: 2560 events read in total (300ms).
[13:25:02.789] <TB1> INFO: Test took 1196ms.
[13:25:02.795] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:03.098] <TB1> INFO: Expecting 2560 events.
[13:25:03.993] <TB1> INFO: 2560 events read in total (303ms).
[13:25:03.993] <TB1> INFO: Test took 1198ms.
[13:25:03.997] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:04.301] <TB1> INFO: Expecting 2560 events.
[13:25:05.192] <TB1> INFO: 2560 events read in total (299ms).
[13:25:05.192] <TB1> INFO: Test took 1196ms.
[13:25:05.195] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:05.501] <TB1> INFO: Expecting 2560 events.
[13:25:06.391] <TB1> INFO: 2560 events read in total (298ms).
[13:25:06.391] <TB1> INFO: Test took 1196ms.
[13:25:06.394] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:06.700] <TB1> INFO: Expecting 2560 events.
[13:25:07.591] <TB1> INFO: 2560 events read in total (299ms).
[13:25:07.591] <TB1> INFO: Test took 1197ms.
[13:25:07.594] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:07.899] <TB1> INFO: Expecting 2560 events.
[13:25:08.784] <TB1> INFO: 2560 events read in total (293ms).
[13:25:08.784] <TB1> INFO: Test took 1191ms.
[13:25:08.788] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:25:09.093] <TB1> INFO: Expecting 2560 events.
[13:25:09.988] <TB1> INFO: 2560 events read in total (303ms).
[13:25:09.988] <TB1> INFO: Test took 1200ms.
[13:25:10.473] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 658 seconds
[13:25:10.473] <TB1> INFO: PH scale (per ROC): 37 37 47 46 51 46 33 43 43 35 41 33 48 37 43 47
[13:25:10.473] <TB1> INFO: PH offset (per ROC): 83 87 98 110 111 112 86 93 94 99 79 78 107 82 91 127
[13:25:10.483] <TB1> INFO: Decoding statistics:
[13:25:10.483] <TB1> INFO: General information:
[13:25:10.483] <TB1> INFO: 16bit words read: 127894
[13:25:10.483] <TB1> INFO: valid events total: 20480
[13:25:10.483] <TB1> INFO: empty events: 17973
[13:25:10.483] <TB1> INFO: valid events with pixels: 2507
[13:25:10.483] <TB1> INFO: valid pixel hits: 2507
[13:25:10.483] <TB1> INFO: Event errors: 0
[13:25:10.483] <TB1> INFO: start marker: 0
[13:25:10.483] <TB1> INFO: stop marker: 0
[13:25:10.483] <TB1> INFO: overflow: 0
[13:25:10.483] <TB1> INFO: invalid 5bit words: 0
[13:25:10.483] <TB1> INFO: invalid XOR eye diagram: 0
[13:25:10.483] <TB1> INFO: frame (failed synchr.): 0
[13:25:10.483] <TB1> INFO: idle data (no TBM trl): 0
[13:25:10.483] <TB1> INFO: no data (only TBM hdr): 0
[13:25:10.483] <TB1> INFO: TBM errors: 0
[13:25:10.483] <TB1> INFO: flawed TBM headers: 0
[13:25:10.483] <TB1> INFO: flawed TBM trailers: 0
[13:25:10.483] <TB1> INFO: event ID mismatches: 0
[13:25:10.483] <TB1> INFO: ROC errors: 0
[13:25:10.483] <TB1> INFO: missing ROC header(s): 0
[13:25:10.483] <TB1> INFO: misplaced readback start: 0
[13:25:10.483] <TB1> INFO: Pixel decoding errors: 0
[13:25:10.483] <TB1> INFO: pixel data incomplete: 0
[13:25:10.483] <TB1> INFO: pixel address: 0
[13:25:10.483] <TB1> INFO: pulse height fill bit: 0
[13:25:10.483] <TB1> INFO: buffer corruption: 0
[13:25:10.645] <TB1> INFO: ######################################################################
[13:25:10.645] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:25:10.645] <TB1> INFO: ######################################################################
[13:25:10.659] <TB1> INFO: scanning low vcal = 10
[13:25:10.901] <TB1> INFO: Expecting 41600 events.
[13:25:14.530] <TB1> INFO: 41600 events read in total (3037ms).
[13:25:14.530] <TB1> INFO: Test took 3871ms.
[13:25:14.532] <TB1> INFO: scanning low vcal = 20
[13:25:14.826] <TB1> INFO: Expecting 41600 events.
[13:25:18.447] <TB1> INFO: 41600 events read in total (3029ms).
[13:25:18.447] <TB1> INFO: Test took 3915ms.
[13:25:18.449] <TB1> INFO: scanning low vcal = 30
[13:25:18.740] <TB1> INFO: Expecting 41600 events.
[13:25:22.403] <TB1> INFO: 41600 events read in total (3072ms).
[13:25:22.404] <TB1> INFO: Test took 3955ms.
[13:25:22.407] <TB1> INFO: scanning low vcal = 40
[13:25:22.687] <TB1> INFO: Expecting 41600 events.
[13:25:26.666] <TB1> INFO: 41600 events read in total (3387ms).
[13:25:26.668] <TB1> INFO: Test took 4261ms.
[13:25:26.672] <TB1> INFO: scanning low vcal = 50
[13:25:26.949] <TB1> INFO: Expecting 41600 events.
[13:25:30.966] <TB1> INFO: 41600 events read in total (3425ms).
[13:25:30.968] <TB1> INFO: Test took 4296ms.
[13:25:30.972] <TB1> INFO: scanning low vcal = 60
[13:25:31.248] <TB1> INFO: Expecting 41600 events.
[13:25:35.250] <TB1> INFO: 41600 events read in total (3411ms).
[13:25:35.251] <TB1> INFO: Test took 4279ms.
[13:25:35.254] <TB1> INFO: scanning low vcal = 70
[13:25:35.531] <TB1> INFO: Expecting 41600 events.
[13:25:39.530] <TB1> INFO: 41600 events read in total (3407ms).
[13:25:39.531] <TB1> INFO: Test took 4276ms.
[13:25:39.534] <TB1> INFO: scanning low vcal = 80
[13:25:39.812] <TB1> INFO: Expecting 41600 events.
[13:25:43.803] <TB1> INFO: 41600 events read in total (3399ms).
[13:25:43.804] <TB1> INFO: Test took 4270ms.
[13:25:43.807] <TB1> INFO: scanning low vcal = 90
[13:25:44.084] <TB1> INFO: Expecting 41600 events.
[13:25:48.094] <TB1> INFO: 41600 events read in total (3418ms).
[13:25:48.095] <TB1> INFO: Test took 4288ms.
[13:25:48.100] <TB1> INFO: scanning low vcal = 100
[13:25:48.376] <TB1> INFO: Expecting 41600 events.
[13:25:52.422] <TB1> INFO: 41600 events read in total (3454ms).
[13:25:52.423] <TB1> INFO: Test took 4323ms.
[13:25:52.427] <TB1> INFO: scanning low vcal = 110
[13:25:52.708] <TB1> INFO: Expecting 41600 events.
[13:25:56.664] <TB1> INFO: 41600 events read in total (3364ms).
[13:25:56.665] <TB1> INFO: Test took 4238ms.
[13:25:56.668] <TB1> INFO: scanning low vcal = 120
[13:25:56.945] <TB1> INFO: Expecting 41600 events.
[13:26:00.887] <TB1> INFO: 41600 events read in total (3351ms).
[13:26:00.888] <TB1> INFO: Test took 4220ms.
[13:26:00.891] <TB1> INFO: scanning low vcal = 130
[13:26:01.167] <TB1> INFO: Expecting 41600 events.
[13:26:05.108] <TB1> INFO: 41600 events read in total (3349ms).
[13:26:05.109] <TB1> INFO: Test took 4218ms.
[13:26:05.112] <TB1> INFO: scanning low vcal = 140
[13:26:05.389] <TB1> INFO: Expecting 41600 events.
[13:26:09.328] <TB1> INFO: 41600 events read in total (3347ms).
[13:26:09.329] <TB1> INFO: Test took 4216ms.
[13:26:09.332] <TB1> INFO: scanning low vcal = 150
[13:26:09.608] <TB1> INFO: Expecting 41600 events.
[13:26:13.566] <TB1> INFO: 41600 events read in total (3366ms).
[13:26:13.567] <TB1> INFO: Test took 4235ms.
[13:26:13.570] <TB1> INFO: scanning low vcal = 160
[13:26:13.847] <TB1> INFO: Expecting 41600 events.
[13:26:17.823] <TB1> INFO: 41600 events read in total (3385ms).
[13:26:17.824] <TB1> INFO: Test took 4253ms.
[13:26:17.827] <TB1> INFO: scanning low vcal = 170
[13:26:18.103] <TB1> INFO: Expecting 41600 events.
[13:26:22.059] <TB1> INFO: 41600 events read in total (3364ms).
[13:26:22.060] <TB1> INFO: Test took 4233ms.
[13:26:22.066] <TB1> INFO: scanning low vcal = 180
[13:26:22.340] <TB1> INFO: Expecting 41600 events.
[13:26:26.281] <TB1> INFO: 41600 events read in total (3350ms).
[13:26:26.282] <TB1> INFO: Test took 4216ms.
[13:26:26.285] <TB1> INFO: scanning low vcal = 190
[13:26:26.563] <TB1> INFO: Expecting 41600 events.
[13:26:30.651] <TB1> INFO: 41600 events read in total (3496ms).
[13:26:30.652] <TB1> INFO: Test took 4367ms.
[13:26:30.655] <TB1> INFO: scanning low vcal = 200
[13:26:30.933] <TB1> INFO: Expecting 41600 events.
[13:26:35.015] <TB1> INFO: 41600 events read in total (3491ms).
[13:26:35.016] <TB1> INFO: Test took 4360ms.
[13:26:35.019] <TB1> INFO: scanning low vcal = 210
[13:26:35.297] <TB1> INFO: Expecting 41600 events.
[13:26:39.295] <TB1> INFO: 41600 events read in total (3407ms).
[13:26:39.296] <TB1> INFO: Test took 4277ms.
[13:26:39.299] <TB1> INFO: scanning low vcal = 220
[13:26:39.576] <TB1> INFO: Expecting 41600 events.
[13:26:43.576] <TB1> INFO: 41600 events read in total (3408ms).
[13:26:43.577] <TB1> INFO: Test took 4278ms.
[13:26:43.581] <TB1> INFO: scanning low vcal = 230
[13:26:43.857] <TB1> INFO: Expecting 41600 events.
[13:26:47.840] <TB1> INFO: 41600 events read in total (3391ms).
[13:26:47.842] <TB1> INFO: Test took 4261ms.
[13:26:47.845] <TB1> INFO: scanning low vcal = 240
[13:26:48.122] <TB1> INFO: Expecting 41600 events.
[13:26:52.082] <TB1> INFO: 41600 events read in total (3369ms).
[13:26:52.083] <TB1> INFO: Test took 4238ms.
[13:26:52.086] <TB1> INFO: scanning low vcal = 250
[13:26:52.364] <TB1> INFO: Expecting 41600 events.
[13:26:56.366] <TB1> INFO: 41600 events read in total (3410ms).
[13:26:56.366] <TB1> INFO: Test took 4279ms.
[13:26:56.371] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[13:26:56.647] <TB1> INFO: Expecting 41600 events.
[13:27:00.715] <TB1> INFO: 41600 events read in total (3477ms).
[13:27:00.716] <TB1> INFO: Test took 4345ms.
[13:27:00.719] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[13:27:00.997] <TB1> INFO: Expecting 41600 events.
[13:27:05.059] <TB1> INFO: 41600 events read in total (3470ms).
[13:27:05.060] <TB1> INFO: Test took 4341ms.
[13:27:05.063] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[13:27:05.340] <TB1> INFO: Expecting 41600 events.
[13:27:09.315] <TB1> INFO: 41600 events read in total (3383ms).
[13:27:09.316] <TB1> INFO: Test took 4252ms.
[13:27:09.319] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[13:27:09.596] <TB1> INFO: Expecting 41600 events.
[13:27:13.570] <TB1> INFO: 41600 events read in total (3384ms).
[13:27:13.572] <TB1> INFO: Test took 4252ms.
[13:27:13.575] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:27:13.852] <TB1> INFO: Expecting 41600 events.
[13:27:17.834] <TB1> INFO: 41600 events read in total (3390ms).
[13:27:17.835] <TB1> INFO: Test took 4260ms.
[13:27:18.287] <TB1> INFO: PixTestGainPedestal::measure() done
[13:28:00.774] <TB1> INFO: PixTestGainPedestal::fit() done
[13:28:00.774] <TB1> INFO: non-linearity mean: 0.921 0.954 0.969 0.946 0.967 0.959 0.972 0.966 0.934 0.977 0.932 1.018 0.963 1.007 0.951 0.972
[13:28:00.774] <TB1> INFO: non-linearity RMS: 0.131 0.195 0.034 0.056 0.014 0.037 0.195 0.016 0.127 0.185 0.105 0.202 0.019 0.174 0.143 0.007
[13:28:00.774] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[13:28:00.787] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[13:28:00.800] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[13:28:00.813] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[13:28:00.826] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[13:28:00.839] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[13:28:00.852] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[13:28:00.865] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[13:28:00.877] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[13:28:00.890] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[13:28:00.903] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[13:28:00.916] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[13:28:00.929] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[13:28:00.942] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[13:28:00.955] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[13:28:00.968] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[13:28:00.981] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 170 seconds
[13:28:00.981] <TB1> INFO: Decoding statistics:
[13:28:00.981] <TB1> INFO: General information:
[13:28:00.981] <TB1> INFO: 16bit words read: 3279976
[13:28:00.981] <TB1> INFO: valid events total: 332800
[13:28:00.981] <TB1> INFO: empty events: 323
[13:28:00.981] <TB1> INFO: valid events with pixels: 332477
[13:28:00.981] <TB1> INFO: valid pixel hits: 641588
[13:28:00.981] <TB1> INFO: Event errors: 0
[13:28:00.981] <TB1> INFO: start marker: 0
[13:28:00.981] <TB1> INFO: stop marker: 0
[13:28:00.981] <TB1> INFO: overflow: 0
[13:28:00.981] <TB1> INFO: invalid 5bit words: 0
[13:28:00.981] <TB1> INFO: invalid XOR eye diagram: 0
[13:28:00.981] <TB1> INFO: frame (failed synchr.): 0
[13:28:00.981] <TB1> INFO: idle data (no TBM trl): 0
[13:28:00.981] <TB1> INFO: no data (only TBM hdr): 0
[13:28:00.981] <TB1> INFO: TBM errors: 0
[13:28:00.981] <TB1> INFO: flawed TBM headers: 0
[13:28:00.981] <TB1> INFO: flawed TBM trailers: 0
[13:28:00.981] <TB1> INFO: event ID mismatches: 0
[13:28:00.981] <TB1> INFO: ROC errors: 0
[13:28:00.981] <TB1> INFO: missing ROC header(s): 0
[13:28:00.981] <TB1> INFO: misplaced readback start: 0
[13:28:00.981] <TB1> INFO: Pixel decoding errors: 0
[13:28:00.981] <TB1> INFO: pixel data incomplete: 0
[13:28:00.981] <TB1> INFO: pixel address: 0
[13:28:00.981] <TB1> INFO: pulse height fill bit: 0
[13:28:00.981] <TB1> INFO: buffer corruption: 0
[13:28:00.998] <TB1> INFO: Decoding statistics:
[13:28:00.999] <TB1> INFO: General information:
[13:28:00.999] <TB1> INFO: 16bit words read: 3409406
[13:28:00.999] <TB1> INFO: valid events total: 353536
[13:28:00.999] <TB1> INFO: empty events: 18552
[13:28:00.999] <TB1> INFO: valid events with pixels: 334984
[13:28:00.999] <TB1> INFO: valid pixel hits: 644095
[13:28:00.999] <TB1> INFO: Event errors: 0
[13:28:00.999] <TB1> INFO: start marker: 0
[13:28:00.999] <TB1> INFO: stop marker: 0
[13:28:00.999] <TB1> INFO: overflow: 0
[13:28:00.999] <TB1> INFO: invalid 5bit words: 0
[13:28:00.999] <TB1> INFO: invalid XOR eye diagram: 0
[13:28:00.999] <TB1> INFO: frame (failed synchr.): 0
[13:28:00.999] <TB1> INFO: idle data (no TBM trl): 0
[13:28:00.999] <TB1> INFO: no data (only TBM hdr): 0
[13:28:00.999] <TB1> INFO: TBM errors: 0
[13:28:00.999] <TB1> INFO: flawed TBM headers: 0
[13:28:00.999] <TB1> INFO: flawed TBM trailers: 0
[13:28:00.999] <TB1> INFO: event ID mismatches: 0
[13:28:00.999] <TB1> INFO: ROC errors: 0
[13:28:00.999] <TB1> INFO: missing ROC header(s): 0
[13:28:00.999] <TB1> INFO: misplaced readback start: 0
[13:28:00.999] <TB1> INFO: Pixel decoding errors: 0
[13:28:00.999] <TB1> INFO: pixel data incomplete: 0
[13:28:00.999] <TB1> INFO: pixel address: 0
[13:28:00.999] <TB1> INFO: pulse height fill bit: 0
[13:28:00.999] <TB1> INFO: buffer corruption: 0
[13:28:00.999] <TB1> INFO: enter test to run
[13:28:00.999] <TB1> INFO: test: trim80 no parameter change
[13:28:00.999] <TB1> INFO: running: trim80
[13:28:00.000] <TB1> INFO: ######################################################################
[13:28:00.000] <TB1> INFO: PixTestTrim80::doTest()
[13:28:00.000] <TB1> INFO: ######################################################################
[13:28:00.001] <TB1> INFO: ----------------------------------------------------------------------
[13:28:00.001] <TB1> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[13:28:00.001] <TB1> INFO: ----------------------------------------------------------------------
[13:28:01.042] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:28:01.042] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:28:01.055] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:28:01.055] <TB1> INFO: run 1 of 1
[13:28:01.291] <TB1> INFO: Expecting 5025280 events.
[13:28:29.284] <TB1> INFO: 671360 events read in total (27401ms).
[13:28:56.409] <TB1> INFO: 1339536 events read in total (54526ms).
[13:29:23.725] <TB1> INFO: 2005944 events read in total (81842ms).
[13:29:50.001] <TB1> INFO: 2671568 events read in total (109118ms).
[13:30:18.294] <TB1> INFO: 3337176 events read in total (136411ms).
[13:30:45.576] <TB1> INFO: 4001888 events read in total (163693ms).
[13:31:12.990] <TB1> INFO: 4666984 events read in total (191107ms).
[13:31:27.640] <TB1> INFO: 5025280 events read in total (205757ms).
[13:31:27.713] <TB1> INFO: Test took 206658ms.
[13:31:52.375] <TB1> INFO: ROC 0 VthrComp = 76
[13:31:52.375] <TB1> INFO: ROC 1 VthrComp = 79
[13:31:52.375] <TB1> INFO: ROC 2 VthrComp = 77
[13:31:52.375] <TB1> INFO: ROC 3 VthrComp = 75
[13:31:52.375] <TB1> INFO: ROC 4 VthrComp = 69
[13:31:52.375] <TB1> INFO: ROC 5 VthrComp = 74
[13:31:52.376] <TB1> INFO: ROC 6 VthrComp = 81
[13:31:52.376] <TB1> INFO: ROC 7 VthrComp = 76
[13:31:52.376] <TB1> INFO: ROC 8 VthrComp = 71
[13:31:52.376] <TB1> INFO: ROC 9 VthrComp = 73
[13:31:52.376] <TB1> INFO: ROC 10 VthrComp = 76
[13:31:52.376] <TB1> INFO: ROC 11 VthrComp = 74
[13:31:52.376] <TB1> INFO: ROC 12 VthrComp = 80
[13:31:52.376] <TB1> INFO: ROC 13 VthrComp = 69
[13:31:52.376] <TB1> INFO: ROC 14 VthrComp = 72
[13:31:52.376] <TB1> INFO: ROC 15 VthrComp = 73
[13:31:52.615] <TB1> INFO: Expecting 41600 events.
[13:31:56.211] <TB1> INFO: 41600 events read in total (3005ms).
[13:31:56.212] <TB1> INFO: Test took 3834ms.
[13:31:56.224] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:31:56.224] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:31:56.242] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:31:56.242] <TB1> INFO: run 1 of 1
[13:31:56.520] <TB1> INFO: Expecting 5025280 events.
[13:32:24.958] <TB1> INFO: 680976 events read in total (27846ms).
[13:32:52.465] <TB1> INFO: 1357672 events read in total (55353ms).
[13:33:20.076] <TB1> INFO: 2034976 events read in total (82964ms).
[13:33:47.578] <TB1> INFO: 2710432 events read in total (110466ms).
[13:34:15.004] <TB1> INFO: 3382824 events read in total (137892ms).
[13:34:42.475] <TB1> INFO: 4053792 events read in total (165363ms).
[13:35:10.776] <TB1> INFO: 4724888 events read in total (193664ms).
[13:35:23.259] <TB1> INFO: 5025280 events read in total (206147ms).
[13:35:23.339] <TB1> INFO: Test took 207097ms.
[13:35:53.546] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 109.917 for pixel 1/66 mean/min/max = 94.1287/78.273/109.984
[13:35:53.546] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 106.235 for pixel 0/53 mean/min/max = 92.1949/77.8957/106.494
[13:35:53.547] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 112.408 for pixel 0/4 mean/min/max = 94.4376/76.4242/112.451
[13:35:53.547] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 109.413 for pixel 0/64 mean/min/max = 93.7183/77.7512/109.685
[13:35:53.547] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 104.911 for pixel 0/69 mean/min/max = 89.4933/73.8224/105.164
[13:35:53.548] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 106.242 for pixel 25/75 mean/min/max = 91.6621/76.9497/106.374
[13:35:53.548] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 107.417 for pixel 0/78 mean/min/max = 91.0766/74.3283/107.825
[13:35:53.549] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 111.35 for pixel 0/45 mean/min/max = 94.7823/78.1781/111.386
[13:35:53.549] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 104.894 for pixel 51/45 mean/min/max = 90.3084/75.2969/105.32
[13:35:53.549] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 110.694 for pixel 8/33 mean/min/max = 94.2304/77.7635/110.697
[13:35:53.550] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 117.202 for pixel 49/0 mean/min/max = 96.8126/76.3801/117.245
[13:35:53.550] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 108.266 for pixel 21/0 mean/min/max = 93.1528/77.9777/108.328
[13:35:53.551] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 106.051 for pixel 31/79 mean/min/max = 90.6084/75.1499/106.067
[13:35:53.551] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 101.754 for pixel 10/79 mean/min/max = 88.2013/74.3691/102.034
[13:35:53.551] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 109.426 for pixel 29/16 mean/min/max = 92.9617/76.4783/109.445
[13:35:53.552] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 109.432 for pixel 0/77 mean/min/max = 92.631/75.8177/109.444
[13:35:53.552] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:35:53.642] <TB1> INFO: Expecting 411648 events.
[13:36:03.093] <TB1> INFO: 411648 events read in total (8859ms).
[13:36:03.101] <TB1> INFO: Expecting 411648 events.
[13:36:12.412] <TB1> INFO: 411648 events read in total (8908ms).
[13:36:12.437] <TB1> INFO: Expecting 411648 events.
[13:36:21.827] <TB1> INFO: 411648 events read in total (8987ms).
[13:36:21.842] <TB1> INFO: Expecting 411648 events.
[13:36:31.080] <TB1> INFO: 411648 events read in total (8835ms).
[13:36:31.102] <TB1> INFO: Expecting 411648 events.
[13:36:40.328] <TB1> INFO: 411648 events read in total (8823ms).
[13:36:40.355] <TB1> INFO: Expecting 411648 events.
[13:36:49.724] <TB1> INFO: 411648 events read in total (8965ms).
[13:36:49.766] <TB1> INFO: Expecting 411648 events.
[13:36:59.228] <TB1> INFO: 411648 events read in total (9059ms).
[13:36:59.259] <TB1> INFO: Expecting 411648 events.
[13:37:08.545] <TB1> INFO: 411648 events read in total (8883ms).
[13:37:08.579] <TB1> INFO: Expecting 411648 events.
[13:37:17.843] <TB1> INFO: 411648 events read in total (8861ms).
[13:37:17.881] <TB1> INFO: Expecting 411648 events.
[13:37:27.292] <TB1> INFO: 411648 events read in total (9008ms).
[13:37:27.338] <TB1> INFO: Expecting 411648 events.
[13:37:36.576] <TB1> INFO: 411648 events read in total (8835ms).
[13:37:36.641] <TB1> INFO: Expecting 411648 events.
[13:37:45.930] <TB1> INFO: 411648 events read in total (8886ms).
[13:37:45.001] <TB1> INFO: Expecting 411648 events.
[13:37:55.405] <TB1> INFO: 411648 events read in total (9001ms).
[13:37:55.483] <TB1> INFO: Expecting 411648 events.
[13:38:04.779] <TB1> INFO: 411648 events read in total (8893ms).
[13:38:04.878] <TB1> INFO: Expecting 411648 events.
[13:38:14.230] <TB1> INFO: 411648 events read in total (8949ms).
[13:38:14.331] <TB1> INFO: Expecting 411648 events.
[13:38:23.860] <TB1> INFO: 411648 events read in total (9126ms).
[13:38:23.963] <TB1> INFO: Test took 150411ms.
[13:38:25.516] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:38:25.530] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:38:25.530] <TB1> INFO: run 1 of 1
[13:38:25.782] <TB1> INFO: Expecting 5025280 events.
[13:38:54.265] <TB1> INFO: 670272 events read in total (27891ms).
[13:39:22.157] <TB1> INFO: 1338024 events read in total (55783ms).
[13:39:50.016] <TB1> INFO: 2005360 events read in total (83642ms).
[13:40:17.980] <TB1> INFO: 2671472 events read in total (111606ms).
[13:40:47.020] <TB1> INFO: 3334600 events read in total (140646ms).
[13:41:14.117] <TB1> INFO: 3995824 events read in total (167743ms).
[13:41:41.973] <TB1> INFO: 4656160 events read in total (195599ms).
[13:41:57.958] <TB1> INFO: 5025280 events read in total (211584ms).
[13:41:58.030] <TB1> INFO: Test took 212499ms.
[13:42:26.265] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 57.602997 .. 102.908523
[13:42:26.529] <TB1> INFO: Expecting 208000 events.
[13:42:36.596] <TB1> INFO: 208000 events read in total (9475ms).
[13:42:36.596] <TB1> INFO: Test took 10329ms.
[13:42:36.644] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 47 .. 112 (-1/-1) hits flags = 528 (plus default)
[13:42:36.658] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:42:36.658] <TB1> INFO: run 1 of 1
[13:42:36.936] <TB1> INFO: Expecting 2196480 events.
[13:43:05.402] <TB1> INFO: 672864 events read in total (27874ms).
[13:43:33.402] <TB1> INFO: 1342688 events read in total (55875ms).
[13:44:01.912] <TB1> INFO: 2009328 events read in total (84384ms).
[13:44:10.153] <TB1> INFO: 2196480 events read in total (92625ms).
[13:44:10.203] <TB1> INFO: Test took 93546ms.
[13:44:34.432] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 65.738064 .. 94.287793
[13:44:34.687] <TB1> INFO: Expecting 208000 events.
[13:44:44.820] <TB1> INFO: 208000 events read in total (9541ms).
[13:44:44.821] <TB1> INFO: Test took 10386ms.
[13:44:44.868] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 55 .. 104 (-1/-1) hits flags = 528 (plus default)
[13:44:44.882] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:44:44.882] <TB1> INFO: run 1 of 1
[13:44:45.160] <TB1> INFO: Expecting 1664000 events.
[13:45:14.598] <TB1> INFO: 671136 events read in total (28846ms).
[13:45:43.033] <TB1> INFO: 1342776 events read in total (57281ms).
[13:45:57.184] <TB1> INFO: 1664000 events read in total (71432ms).
[13:45:57.227] <TB1> INFO: Test took 72346ms.
[13:46:15.668] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 70.363632 .. 90.050410
[13:46:15.911] <TB1> INFO: Expecting 208000 events.
[13:46:26.412] <TB1> INFO: 208000 events read in total (9907ms).
[13:46:26.413] <TB1> INFO: Test took 10743ms.
[13:46:26.462] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[13:46:26.475] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:46:26.475] <TB1> INFO: run 1 of 1
[13:46:26.753] <TB1> INFO: Expecting 1364480 events.
[13:46:56.123] <TB1> INFO: 670280 events read in total (28778ms).
[13:47:24.192] <TB1> INFO: 1338952 events read in total (56848ms).
[13:47:25.658] <TB1> INFO: 1364480 events read in total (58313ms).
[13:47:25.687] <TB1> INFO: Test took 59212ms.
[13:47:43.133] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 72.200335 .. 90.050410
[13:47:43.370] <TB1> INFO: Expecting 208000 events.
[13:47:53.477] <TB1> INFO: 208000 events read in total (9515ms).
[13:47:53.478] <TB1> INFO: Test took 10344ms.
[13:47:53.526] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 62 .. 100 (-1/-1) hits flags = 528 (plus default)
[13:47:53.539] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:47:53.539] <TB1> INFO: run 1 of 1
[13:47:53.817] <TB1> INFO: Expecting 1297920 events.
[13:48:22.187] <TB1> INFO: 662520 events read in total (27778ms).
[13:48:49.456] <TB1> INFO: 1297920 events read in total (55047ms).
[13:48:49.490] <TB1> INFO: Test took 55951ms.
[13:49:05.885] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[13:49:05.885] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[13:49:05.899] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:49:05.899] <TB1> INFO: run 1 of 1
[13:49:06.136] <TB1> INFO: Expecting 1364480 events.
[13:49:34.891] <TB1> INFO: 667592 events read in total (28163ms).
[13:50:02.689] <TB1> INFO: 1335848 events read in total (55961ms).
[13:50:04.282] <TB1> INFO: 1364480 events read in total (57554ms).
[13:50:04.310] <TB1> INFO: Test took 58412ms.
[13:50:20.801] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C0.dat
[13:50:20.801] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C1.dat
[13:50:20.801] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C2.dat
[13:50:20.801] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C3.dat
[13:50:20.801] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C4.dat
[13:50:20.801] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C5.dat
[13:50:20.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C6.dat
[13:50:20.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C7.dat
[13:50:20.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C8.dat
[13:50:20.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C9.dat
[13:50:20.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C10.dat
[13:50:20.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C11.dat
[13:50:20.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C12.dat
[13:50:20.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C13.dat
[13:50:20.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C14.dat
[13:50:20.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C15.dat
[13:50:20.802] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C0.dat
[13:50:20.807] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C1.dat
[13:50:20.812] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C2.dat
[13:50:20.817] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C3.dat
[13:50:20.821] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C4.dat
[13:50:20.826] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C5.dat
[13:50:20.831] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C6.dat
[13:50:20.835] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C7.dat
[13:50:20.840] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C8.dat
[13:50:20.845] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C9.dat
[13:50:20.849] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C10.dat
[13:50:20.854] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C11.dat
[13:50:20.859] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C12.dat
[13:50:20.864] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C13.dat
[13:50:20.868] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C14.dat
[13:50:20.873] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1101_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C15.dat
[13:50:20.878] <TB1> INFO: PixTestTrim80::trimTest() done
[13:50:20.878] <TB1> INFO: vtrim: 102 99 107 96 93 98 102 110 84 97 113 110 103 82 104 109
[13:50:20.878] <TB1> INFO: vthrcomp: 76 79 77 75 69 74 81 76 71 73 76 74 80 69 72 73
[13:50:20.878] <TB1> INFO: vcal mean: 79.95 79.96 79.91 79.99 79.87 79.92 79.94 79.92 79.92 79.97 79.89 79.92 79.93 79.90 79.93 79.94
[13:50:20.878] <TB1> INFO: vcal RMS: 0.74 0.71 0.76 0.69 1.42 0.67 0.70 0.69 0.74 0.78 0.83 0.74 0.71 0.73 0.78 0.76
[13:50:20.878] <TB1> INFO: bits mean: 9.37 9.14 9.26 9.09 10.24 9.60 9.86 8.88 9.81 9.21 9.00 9.55 10.04 10.37 9.65 9.61
[13:50:20.878] <TB1> INFO: bits RMS: 2.24 2.40 2.42 2.35 2.58 2.33 2.56 2.38 2.55 2.31 2.41 2.20 2.48 2.52 2.33 2.43
[13:50:20.885] <TB1> INFO: ----------------------------------------------------------------------
[13:50:20.885] <TB1> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:50:20.885] <TB1> INFO: ----------------------------------------------------------------------
[13:50:20.888] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:50:20.900] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:50:20.900] <TB1> INFO: run 1 of 1
[13:50:21.137] <TB1> INFO: Expecting 4160000 events.
[13:50:53.634] <TB1> INFO: 756420 events read in total (31905ms).
[13:51:25.571] <TB1> INFO: 1508985 events read in total (63842ms).
[13:51:57.597] <TB1> INFO: 2255565 events read in total (95868ms).
[13:52:29.707] <TB1> INFO: 2997300 events read in total (127978ms).
[13:53:01.519] <TB1> INFO: 3737895 events read in total (159790ms).
[13:53:19.618] <TB1> INFO: 4160000 events read in total (177889ms).
[13:53:19.692] <TB1> INFO: Test took 178791ms.
[13:53:49.086] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[13:53:49.099] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:53:49.100] <TB1> INFO: run 1 of 1
[13:53:49.338] <TB1> INFO: Expecting 4326400 events.
[13:54:21.842] <TB1> INFO: 723640 events read in total (31912ms).
[13:54:53.211] <TB1> INFO: 1444265 events read in total (63281ms).
[13:55:24.859] <TB1> INFO: 2160395 events read in total (94929ms).
[13:55:55.884] <TB1> INFO: 2871640 events read in total (125954ms).
[13:56:27.108] <TB1> INFO: 3582385 events read in total (157178ms).
[13:56:58.649] <TB1> INFO: 4293265 events read in total (188719ms).
[13:57:00.519] <TB1> INFO: 4326400 events read in total (190589ms).
[13:57:00.623] <TB1> INFO: Test took 191523ms.
[13:57:29.142] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:57:29.157] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:57:29.157] <TB1> INFO: run 1 of 1
[13:57:29.393] <TB1> INFO: Expecting 4160000 events.
[13:58:01.716] <TB1> INFO: 734425 events read in total (31731ms).
[13:58:33.332] <TB1> INFO: 1464825 events read in total (63347ms).
[13:59:05.048] <TB1> INFO: 2190940 events read in total (95063ms).
[13:59:36.302] <TB1> INFO: 2912405 events read in total (126317ms).
[14:00:07.692] <TB1> INFO: 3632420 events read in total (157707ms).
[14:00:30.001] <TB1> INFO: 4160000 events read in total (181016ms).
[14:00:31.087] <TB1> INFO: Test took 181931ms.
[14:00:56.911] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:00:56.924] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:00:56.924] <TB1> INFO: run 1 of 1
[14:00:57.161] <TB1> INFO: Expecting 4160000 events.
[14:01:29.295] <TB1> INFO: 734385 events read in total (31542ms).
[14:02:00.992] <TB1> INFO: 1465185 events read in total (63239ms).
[14:02:32.385] <TB1> INFO: 2191420 events read in total (94632ms).
[14:03:03.948] <TB1> INFO: 2912595 events read in total (126195ms).
[14:03:35.333] <TB1> INFO: 3632595 events read in total (157580ms).
[14:03:58.700] <TB1> INFO: 4160000 events read in total (180947ms).
[14:03:58.827] <TB1> INFO: Test took 181902ms.
[14:04:28.321] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[14:04:28.335] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:04:28.335] <TB1> INFO: run 1 of 1
[14:04:28.608] <TB1> INFO: Expecting 4139200 events.
[14:05:01.250] <TB1> INFO: 735645 events read in total (32051ms).
[14:05:32.835] <TB1> INFO: 1468105 events read in total (63636ms).
[14:06:04.919] <TB1> INFO: 2195310 events read in total (95720ms).
[14:06:36.383] <TB1> INFO: 2918430 events read in total (127184ms).
[14:07:07.968] <TB1> INFO: 3640405 events read in total (158769ms).
[14:07:29.654] <TB1> INFO: 4139200 events read in total (180455ms).
[14:07:29.727] <TB1> INFO: Test took 181393ms.
[14:07:57.990] <TB1> INFO: PixTestTrim80::trimBitTest() done
[14:07:57.991] <TB1> INFO: PixTestTrim80::doTest() done, duration: 2396 seconds
[14:07:58.613] <TB1> INFO: enter test to run
[14:07:58.613] <TB1> INFO: test: exit no parameter change
[14:07:58.813] <TB1> QUIET: Connection to board 154 closed.
[14:07:58.814] <TB1> INFO: pXar: this is the end, my friend