[12:02:38.560] <TB0> INFO: *** Welcome to pxar ***
[12:02:38.560] <TB0> INFO: *** Today: 2016/11/02
[12:02:38.568] <TB0> INFO: *** Version: c8ba-dirty
[12:02:38.569] <TB0> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:02:38.569] <TB0> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:02:38.569] <TB0> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//defaultMaskFile.dat
[12:02:38.569] <TB0> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters_C15.dat
[12:02:38.630] <TB0> INFO: clk: 4
[12:02:38.630] <TB0> INFO: ctr: 4
[12:02:38.630] <TB0> INFO: sda: 19
[12:02:38.630] <TB0> INFO: tin: 9
[12:02:38.630] <TB0> INFO: level: 15
[12:02:38.630] <TB0> INFO: triggerdelay: 0
[12:02:38.630] <TB0> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[12:02:38.630] <TB0> INFO: Log level: INFO
[12:02:38.639] <TB0> INFO: Found DTB DTB_WRQ4OZ
[12:02:38.649] <TB0> QUIET: Connection to board DTB_WRQ4OZ opened.
[12:02:38.651] <TB0> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 71
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WRQ4OZ
MAC address: 40D855118047
Hostname: pixelDTB071
Comment:
------------------------------------------------------
[12:02:38.653] <TB0> INFO: RPC call hashes of host and DTB match: 486171790
[12:02:40.142] <TB0> INFO: DUT info:
[12:02:40.142] <TB0> INFO: The DUT currently contains the following objects:
[12:02:40.142] <TB0> INFO: 4 TBM Cores tbm10c (4 ON)
[12:02:40.142] <TB0> INFO: TBM Core alpha (0): 7 registers set
[12:02:40.142] <TB0> INFO: TBM Core beta (1): 7 registers set
[12:02:40.142] <TB0> INFO: TBM Core alpha (2): 7 registers set
[12:02:40.142] <TB0> INFO: TBM Core beta (3): 7 registers set
[12:02:40.142] <TB0> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[12:02:40.142] <TB0> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.142] <TB0> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.142] <TB0> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.142] <TB0> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.142] <TB0> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.142] <TB0> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.142] <TB0> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.142] <TB0> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.142] <TB0> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.142] <TB0> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.142] <TB0> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.142] <TB0> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.142] <TB0> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.142] <TB0> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.142] <TB0> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.143] <TB0> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:02:40.543] <TB0> INFO: enter 'restricted' command line mode
[12:02:40.543] <TB0> INFO: enter test to run
[12:02:40.543] <TB0> INFO: test: pretest no parameter change
[12:02:40.543] <TB0> INFO: running: pretest
[12:02:40.548] <TB0> INFO: ######################################################################
[12:02:40.548] <TB0> INFO: PixTestPretest::doTest()
[12:02:40.548] <TB0> INFO: ######################################################################
[12:02:40.549] <TB0> INFO: ----------------------------------------------------------------------
[12:02:40.549] <TB0> INFO: PixTestPretest::programROC()
[12:02:40.549] <TB0> INFO: ----------------------------------------------------------------------
[12:02:58.563] <TB0> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:02:58.563] <TB0> INFO: IA differences per ROC: 18.5 18.5 17.7 18.5 23.3 20.1 17.7 19.3 18.5 19.3 20.1 20.9 20.9 19.3 19.3 18.5
[12:02:58.649] <TB0> INFO: ----------------------------------------------------------------------
[12:02:58.649] <TB0> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:02:58.649] <TB0> INFO: ----------------------------------------------------------------------
[12:03:05.732] <TB0> INFO: PixTestPretest::setVana() done, Module Ia 380.2 mA = 23.7625 mA/ROC
[12:03:05.732] <TB0> INFO: i(loss) [mA/ROC]: 18.4 19.3 18.4 19.3 19.3 19.3 18.4 18.4 18.4 18.4 19.3 19.3 18.4 18.4 18.4 18.4
[12:03:05.762] <TB0> INFO: ----------------------------------------------------------------------
[12:03:05.762] <TB0> INFO: PixTestPretest::findTiming()
[12:03:05.762] <TB0> INFO: ----------------------------------------------------------------------
[12:03:05.762] <TB0> INFO: PixTestCmd::init()

[12:03:38.188] <TB0> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:03:38.188] <TB0> INFO: (success/tries = 100/100), width = 4
[12:03:39.699] <TB0> INFO: ----------------------------------------------------------------------
[12:03:39.699] <TB0> INFO: PixTestPretest::findWorkingPixel()
[12:03:39.699] <TB0> INFO: ----------------------------------------------------------------------
[12:03:39.794] <TB0> INFO: Expecting 231680 events.
[12:03:50.174] <TB0> INFO: 231680 events read in total (9788ms).
[12:03:50.184] <TB0> INFO: Test took 10480ms.
[12:03:50.438] <TB0> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:03:50.476] <TB0> INFO: ----------------------------------------------------------------------
[12:03:50.476] <TB0> INFO: PixTestPretest::setVthrCompCalDel()
[12:03:50.476] <TB0> INFO: ----------------------------------------------------------------------
[12:03:50.571] <TB0> INFO: Expecting 231680 events.
[12:04:00.516] <TB0> INFO: 231680 events read in total (9354ms).
[12:04:00.525] <TB0> INFO: Test took 10044ms.
[12:04:00.788] <TB0> INFO: PixTestPretest::setVthrCompCalDel() done
[12:04:00.788] <TB0> INFO: CalDel: 85 88 86 79 94 87 77 91 94 83 90 80 69 89 93 94
[12:04:00.788] <TB0> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[12:04:00.792] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C0.dat
[12:04:00.792] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C1.dat
[12:04:00.793] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C2.dat
[12:04:00.793] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C3.dat
[12:04:00.793] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C4.dat
[12:04:00.793] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C5.dat
[12:04:00.793] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C6.dat
[12:04:00.794] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C7.dat
[12:04:00.794] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C8.dat
[12:04:00.794] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C9.dat
[12:04:00.794] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C10.dat
[12:04:00.794] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C11.dat
[12:04:00.795] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C12.dat
[12:04:00.795] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C13.dat
[12:04:00.795] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C14.dat
[12:04:00.795] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:04:00.795] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[12:04:00.795] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[12:04:00.796] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[12:04:00.796] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:04:00.796] <TB0> INFO: PixTestPretest::doTest() done, duration: 80 seconds
[12:04:00.858] <TB0> INFO: enter test to run
[12:04:00.858] <TB0> INFO: test: fulltest no parameter change
[12:04:00.858] <TB0> INFO: running: fulltest
[12:04:00.858] <TB0> INFO: ######################################################################
[12:04:00.858] <TB0> INFO: PixTestFullTest::doTest()
[12:04:00.858] <TB0> INFO: ######################################################################
[12:04:00.859] <TB0> INFO: ######################################################################
[12:04:00.859] <TB0> INFO: PixTestAlive::doTest()
[12:04:00.859] <TB0> INFO: ######################################################################
[12:04:00.860] <TB0> INFO: ----------------------------------------------------------------------
[12:04:00.860] <TB0> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:04:00.860] <TB0> INFO: ----------------------------------------------------------------------
[12:04:01.102] <TB0> INFO: Expecting 41600 events.
[12:04:04.629] <TB0> INFO: 41600 events read in total (2936ms).
[12:04:04.630] <TB0> INFO: Test took 3768ms.
[12:04:04.866] <TB0> INFO: PixTestAlive::aliveTest() done
[12:04:04.866] <TB0> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:04:04.867] <TB0> INFO: ----------------------------------------------------------------------
[12:04:04.867] <TB0> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:04:04.867] <TB0> INFO: ----------------------------------------------------------------------
[12:04:05.113] <TB0> INFO: Expecting 41600 events.
[12:04:08.077] <TB0> INFO: 41600 events read in total (2372ms).
[12:04:08.077] <TB0> INFO: Test took 3207ms.
[12:04:08.078] <TB0> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:04:08.317] <TB0> INFO: PixTestAlive::maskTest() done
[12:04:08.317] <TB0> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:04:08.318] <TB0> INFO: ----------------------------------------------------------------------
[12:04:08.318] <TB0> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:04:08.318] <TB0> INFO: ----------------------------------------------------------------------
[12:04:08.562] <TB0> INFO: Expecting 41600 events.
[12:04:12.068] <TB0> INFO: 41600 events read in total (2914ms).
[12:04:12.068] <TB0> INFO: Test took 3749ms.
[12:04:12.296] <TB0> INFO: PixTestAlive::addressDecodingTest() done
[12:04:12.296] <TB0> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:04:12.296] <TB0> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:04:12.296] <TB0> INFO: Decoding statistics:
[12:04:12.296] <TB0> INFO: General information:
[12:04:12.296] <TB0> INFO: 16bit words read: 0
[12:04:12.297] <TB0> INFO: valid events total: 0
[12:04:12.297] <TB0> INFO: empty events: 0
[12:04:12.297] <TB0> INFO: valid events with pixels: 0
[12:04:12.297] <TB0> INFO: valid pixel hits: 0
[12:04:12.297] <TB0> INFO: Event errors: 0
[12:04:12.297] <TB0> INFO: start marker: 0
[12:04:12.297] <TB0> INFO: stop marker: 0
[12:04:12.297] <TB0> INFO: overflow: 0
[12:04:12.297] <TB0> INFO: invalid 5bit words: 0
[12:04:12.297] <TB0> INFO: invalid XOR eye diagram: 0
[12:04:12.297] <TB0> INFO: frame (failed synchr.): 0
[12:04:12.297] <TB0> INFO: idle data (no TBM trl): 0
[12:04:12.297] <TB0> INFO: no data (only TBM hdr): 0
[12:04:12.297] <TB0> INFO: TBM errors: 0
[12:04:12.297] <TB0> INFO: flawed TBM headers: 0
[12:04:12.297] <TB0> INFO: flawed TBM trailers: 0
[12:04:12.297] <TB0> INFO: event ID mismatches: 0
[12:04:12.297] <TB0> INFO: ROC errors: 0
[12:04:12.297] <TB0> INFO: missing ROC header(s): 0
[12:04:12.297] <TB0> INFO: misplaced readback start: 0
[12:04:12.297] <TB0> INFO: Pixel decoding errors: 0
[12:04:12.297] <TB0> INFO: pixel data incomplete: 0
[12:04:12.297] <TB0> INFO: pixel address: 0
[12:04:12.297] <TB0> INFO: pulse height fill bit: 0
[12:04:12.297] <TB0> INFO: buffer corruption: 0
[12:04:12.306] <TB0> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:04:12.307] <TB0> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[12:04:12.307] <TB0> INFO: ######################################################################
[12:04:12.307] <TB0> INFO: PixTestReadback::doTest()
[12:04:12.307] <TB0> INFO: ######################################################################
[12:04:12.307] <TB0> INFO: ----------------------------------------------------------------------
[12:04:12.307] <TB0> INFO: PixTestReadback::CalibrateVd()
[12:04:12.307] <TB0> INFO: ----------------------------------------------------------------------
[12:04:22.265] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:04:22.265] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:04:22.265] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:04:22.266] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:04:22.266] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:04:22.266] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:04:22.266] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:04:22.266] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:04:22.266] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:04:22.266] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:04:22.266] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:04:22.266] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:04:22.266] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:04:22.266] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:04:22.266] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:04:22.266] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:04:22.294] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:04:22.294] <TB0> INFO: ----------------------------------------------------------------------
[12:04:22.294] <TB0> INFO: PixTestReadback::CalibrateVa()
[12:04:22.294] <TB0> INFO: ----------------------------------------------------------------------
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:04:32.225] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:04:32.254] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:04:32.254] <TB0> INFO: ----------------------------------------------------------------------
[12:04:32.254] <TB0> INFO: PixTestReadback::readbackVbg()
[12:04:32.254] <TB0> INFO: ----------------------------------------------------------------------
[12:04:39.913] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:04:39.913] <TB0> INFO: ----------------------------------------------------------------------
[12:04:39.913] <TB0> INFO: PixTestReadback::getCalibratedVbg()
[12:04:39.913] <TB0> INFO: ----------------------------------------------------------------------
[12:04:39.913] <TB0> INFO: Vbg will be calibrated using Vd calibration
[12:04:39.913] <TB0> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 147.6calibrated Vbg = 1.19108 :::*/*/*/*/
[12:04:39.913] <TB0> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 151.6calibrated Vbg = 1.18729 :::*/*/*/*/
[12:04:39.913] <TB0> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 156.1calibrated Vbg = 1.1813 :::*/*/*/*/
[12:04:39.913] <TB0> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 147.9calibrated Vbg = 1.17729 :::*/*/*/*/
[12:04:39.913] <TB0> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 150.3calibrated Vbg = 1.18473 :::*/*/*/*/
[12:04:39.913] <TB0> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 158.8calibrated Vbg = 1.18768 :::*/*/*/*/
[12:04:39.913] <TB0> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 158.1calibrated Vbg = 1.18785 :::*/*/*/*/
[12:04:39.914] <TB0> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 149.8calibrated Vbg = 1.19419 :::*/*/*/*/
[12:04:39.914] <TB0> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 151.8calibrated Vbg = 1.17887 :::*/*/*/*/
[12:04:39.914] <TB0> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 156.3calibrated Vbg = 1.18074 :::*/*/*/*/
[12:04:39.914] <TB0> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 154.7calibrated Vbg = 1.17543 :::*/*/*/*/
[12:04:39.914] <TB0> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 149.8calibrated Vbg = 1.17804 :::*/*/*/*/
[12:04:39.914] <TB0> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 157.4calibrated Vbg = 1.18478 :::*/*/*/*/
[12:04:39.914] <TB0> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 151.7calibrated Vbg = 1.18573 :::*/*/*/*/
[12:04:39.914] <TB0> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 146.8calibrated Vbg = 1.18717 :::*/*/*/*/
[12:04:39.914] <TB0> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 149.8calibrated Vbg = 1.19065 :::*/*/*/*/
[12:04:39.916] <TB0> INFO: ----------------------------------------------------------------------
[12:04:39.916] <TB0> INFO: PixTestReadback::CalibrateIa()
[12:04:39.916] <TB0> INFO: ----------------------------------------------------------------------
[12:07:20.745] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:07:20.745] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:07:20.745] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:07:20.745] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:07:20.745] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:07:20.745] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:07:20.745] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:07:20.745] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:07:20.746] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:07:20.746] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:07:20.746] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:07:20.746] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:07:20.746] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:07:20.746] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:07:20.746] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:07:20.746] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:07:20.779] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:07:20.781] <TB0> INFO: PixTestReadback::doTest() done
[12:07:20.782] <TB0> INFO: Decoding statistics:
[12:07:20.782] <TB0> INFO: General information:
[12:07:20.782] <TB0> INFO: 16bit words read: 1536
[12:07:20.782] <TB0> INFO: valid events total: 256
[12:07:20.782] <TB0> INFO: empty events: 256
[12:07:20.782] <TB0> INFO: valid events with pixels: 0
[12:07:20.782] <TB0> INFO: valid pixel hits: 0
[12:07:20.782] <TB0> INFO: Event errors: 0
[12:07:20.782] <TB0> INFO: start marker: 0
[12:07:20.782] <TB0> INFO: stop marker: 0
[12:07:20.782] <TB0> INFO: overflow: 0
[12:07:20.782] <TB0> INFO: invalid 5bit words: 0
[12:07:20.782] <TB0> INFO: invalid XOR eye diagram: 0
[12:07:20.782] <TB0> INFO: frame (failed synchr.): 0
[12:07:20.782] <TB0> INFO: idle data (no TBM trl): 0
[12:07:20.782] <TB0> INFO: no data (only TBM hdr): 0
[12:07:20.782] <TB0> INFO: TBM errors: 0
[12:07:20.782] <TB0> INFO: flawed TBM headers: 0
[12:07:20.782] <TB0> INFO: flawed TBM trailers: 0
[12:07:20.782] <TB0> INFO: event ID mismatches: 0
[12:07:20.782] <TB0> INFO: ROC errors: 0
[12:07:20.782] <TB0> INFO: missing ROC header(s): 0
[12:07:20.782] <TB0> INFO: misplaced readback start: 0
[12:07:20.782] <TB0> INFO: Pixel decoding errors: 0
[12:07:20.782] <TB0> INFO: pixel data incomplete: 0
[12:07:20.782] <TB0> INFO: pixel address: 0
[12:07:20.782] <TB0> INFO: pulse height fill bit: 0
[12:07:20.782] <TB0> INFO: buffer corruption: 0
[12:07:20.833] <TB0> INFO: ######################################################################
[12:07:20.833] <TB0> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:07:20.833] <TB0> INFO: ######################################################################
[12:07:20.835] <TB0> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:07:20.918] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:07:20.918] <TB0> INFO: run 1 of 1
[12:07:21.202] <TB0> INFO: Expecting 3120000 events.
[12:07:53.278] <TB0> INFO: 650205 events read in total (31484ms).











[12:08:23.292] <TB0> INFO: 1298555 events read in total (61498ms).











[12:08:52.989] <TB0> INFO: 1943615 events read in total (91195ms).




















[12:09:22.945] <TB0> INFO: 2589410 events read in total (121151ms).











[12:09:47.489] <TB0> INFO: 3120000 events read in total (145695ms).
[12:09:47.573] <TB0> INFO: Test took 146655ms.
[12:10:13.537] <TB0> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 172 seconds
[12:10:13.537] <TB0> INFO: number of dead bumps (per ROC): 0 0 0 0 0 2 0 0 0 0 5 0 0 7 5 0
[12:10:13.537] <TB0> INFO: separation cut (per ROC): 101 112 105 109 115 98 101 106 102 114 89 130 97 84 91 119
[12:10:13.537] <TB0> INFO: Decoding statistics:
[12:10:13.537] <TB0> INFO: General information:
[12:10:13.537] <TB0> INFO: 16bit words read: 0
[12:10:13.537] <TB0> INFO: valid events total: 0
[12:10:13.537] <TB0> INFO: empty events: 0
[12:10:13.537] <TB0> INFO: valid events with pixels: 0
[12:10:13.537] <TB0> INFO: valid pixel hits: 0
[12:10:13.537] <TB0> INFO: Event errors: 0
[12:10:13.537] <TB0> INFO: start marker: 0
[12:10:13.537] <TB0> INFO: stop marker: 0
[12:10:13.537] <TB0> INFO: overflow: 0
[12:10:13.537] <TB0> INFO: invalid 5bit words: 0
[12:10:13.537] <TB0> INFO: invalid XOR eye diagram: 0
[12:10:13.537] <TB0> INFO: frame (failed synchr.): 0
[12:10:13.537] <TB0> INFO: idle data (no TBM trl): 0
[12:10:13.537] <TB0> INFO: no data (only TBM hdr): 0
[12:10:13.537] <TB0> INFO: TBM errors: 0
[12:10:13.537] <TB0> INFO: flawed TBM headers: 0
[12:10:13.537] <TB0> INFO: flawed TBM trailers: 0
[12:10:13.537] <TB0> INFO: event ID mismatches: 0
[12:10:13.537] <TB0> INFO: ROC errors: 0
[12:10:13.537] <TB0> INFO: missing ROC header(s): 0
[12:10:13.537] <TB0> INFO: misplaced readback start: 0
[12:10:13.537] <TB0> INFO: Pixel decoding errors: 0
[12:10:13.537] <TB0> INFO: pixel data incomplete: 0
[12:10:13.537] <TB0> INFO: pixel address: 0
[12:10:13.537] <TB0> INFO: pulse height fill bit: 0
[12:10:13.537] <TB0> INFO: buffer corruption: 0
[12:10:13.579] <TB0> INFO: ######################################################################
[12:10:13.579] <TB0> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:10:13.579] <TB0> INFO: ######################################################################
[12:10:13.579] <TB0> INFO: ----------------------------------------------------------------------
[12:10:13.579] <TB0> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:10:13.579] <TB0> INFO: ----------------------------------------------------------------------
[12:10:13.579] <TB0> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:10:13.593] <TB0> INFO: dacScan split into 1 runs with ntrig = 50
[12:10:13.593] <TB0> INFO: run 1 of 1
[12:10:13.830] <TB0> INFO: Expecting 36608000 events.
[12:10:37.882] <TB0> INFO: 691150 events read in total (23460ms).
[12:11:01.322] <TB0> INFO: 1368450 events read in total (46900ms).
[12:11:24.732] <TB0> INFO: 2043050 events read in total (70310ms).
[12:11:48.327] <TB0> INFO: 2718350 events read in total (93905ms).
[12:12:12.205] <TB0> INFO: 3393800 events read in total (117783ms).
[12:12:35.708] <TB0> INFO: 4068900 events read in total (141286ms).
[12:12:58.926] <TB0> INFO: 4742100 events read in total (164504ms).
[12:13:22.252] <TB0> INFO: 5416050 events read in total (187830ms).
[12:13:45.934] <TB0> INFO: 6088550 events read in total (211512ms).
[12:14:09.798] <TB0> INFO: 6763150 events read in total (235376ms).
[12:14:33.625] <TB0> INFO: 7435050 events read in total (259203ms).
[12:14:57.170] <TB0> INFO: 8107700 events read in total (282748ms).
[12:15:20.683] <TB0> INFO: 8779400 events read in total (306261ms).
[12:15:44.364] <TB0> INFO: 9450350 events read in total (329942ms).
[12:16:08.454] <TB0> INFO: 10123200 events read in total (354032ms).
[12:16:31.381] <TB0> INFO: 10794900 events read in total (376959ms).
[12:16:55.168] <TB0> INFO: 11466100 events read in total (400746ms).
[12:17:18.492] <TB0> INFO: 12139750 events read in total (424070ms).
[12:17:41.778] <TB0> INFO: 12810150 events read in total (447356ms).
[12:18:04.881] <TB0> INFO: 13479900 events read in total (470459ms).
[12:18:28.024] <TB0> INFO: 14149550 events read in total (493602ms).
[12:18:51.647] <TB0> INFO: 14818200 events read in total (517225ms).
[12:19:15.085] <TB0> INFO: 15487550 events read in total (540663ms).
[12:19:38.754] <TB0> INFO: 16156550 events read in total (564332ms).
[12:20:02.590] <TB0> INFO: 16825250 events read in total (588168ms).
[12:20:26.217] <TB0> INFO: 17494300 events read in total (611795ms).
[12:20:49.108] <TB0> INFO: 18162800 events read in total (634686ms).
[12:21:11.864] <TB0> INFO: 18830500 events read in total (657442ms).
[12:21:34.663] <TB0> INFO: 19497550 events read in total (680241ms).
[12:21:57.570] <TB0> INFO: 20162850 events read in total (703148ms).
[12:22:20.646] <TB0> INFO: 20828100 events read in total (726224ms).
[12:22:43.408] <TB0> INFO: 21492650 events read in total (748986ms).
[12:23:06.588] <TB0> INFO: 22157250 events read in total (772166ms).
[12:23:29.413] <TB0> INFO: 22821250 events read in total (794991ms).
[12:23:52.328] <TB0> INFO: 23484200 events read in total (817906ms).
[12:24:15.266] <TB0> INFO: 24147550 events read in total (840844ms).
[12:24:38.376] <TB0> INFO: 24813050 events read in total (863954ms).
[12:25:01.172] <TB0> INFO: 25480300 events read in total (886750ms).
[12:25:24.148] <TB0> INFO: 26144100 events read in total (909726ms).
[12:25:47.292] <TB0> INFO: 26807600 events read in total (932870ms).
[12:26:09.979] <TB0> INFO: 27469650 events read in total (955557ms).
[12:26:32.637] <TB0> INFO: 28131200 events read in total (978215ms).
[12:26:55.548] <TB0> INFO: 28794600 events read in total (1001126ms).
[12:27:18.326] <TB0> INFO: 29459400 events read in total (1023904ms).
[12:27:41.325] <TB0> INFO: 30120400 events read in total (1046903ms).
[12:28:03.957] <TB0> INFO: 30781450 events read in total (1069535ms).
[12:28:26.962] <TB0> INFO: 31442100 events read in total (1092540ms).
[12:28:49.919] <TB0> INFO: 32105100 events read in total (1115497ms).
[12:29:12.541] <TB0> INFO: 32767500 events read in total (1138119ms).
[12:29:35.193] <TB0> INFO: 33428900 events read in total (1160771ms).
[12:29:58.350] <TB0> INFO: 34091450 events read in total (1183928ms).
[12:30:21.437] <TB0> INFO: 34755450 events read in total (1207015ms).
[12:30:44.187] <TB0> INFO: 35417750 events read in total (1229765ms).
[12:31:07.128] <TB0> INFO: 36084850 events read in total (1252706ms).
[12:31:24.878] <TB0> INFO: 36608000 events read in total (1270456ms).
[12:31:24.958] <TB0> INFO: Test took 1271365ms.
[12:31:25.411] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:26.909] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:28.402] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:29.897] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:31.379] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:32.871] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:34.360] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:35.893] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:38.331] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:40.219] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:42.149] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:43.866] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:45.330] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:47.134] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:49.037] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:51.029] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:31:52.961] <TB0> INFO: PixTestScurves::scurves() done
[12:31:52.961] <TB0> INFO: Vcal mean: 115.81 112.66 114.69 118.56 124.68 125.46 116.87 130.11 118.37 119.30 120.05 119.40 122.68 116.68 115.99 122.96
[12:31:52.961] <TB0> INFO: Vcal RMS: 5.95 4.84 5.07 5.72 6.08 5.96 5.87 6.81 5.59 5.96 6.08 5.76 6.13 5.46 5.70 6.61
[12:31:52.961] <TB0> INFO: PixTestScurves::fullTest() done, duration: 1299 seconds
[12:31:52.961] <TB0> INFO: Decoding statistics:
[12:31:52.961] <TB0> INFO: General information:
[12:31:52.961] <TB0> INFO: 16bit words read: 0
[12:31:52.962] <TB0> INFO: valid events total: 0
[12:31:52.962] <TB0> INFO: empty events: 0
[12:31:52.962] <TB0> INFO: valid events with pixels: 0
[12:31:52.962] <TB0> INFO: valid pixel hits: 0
[12:31:52.962] <TB0> INFO: Event errors: 0
[12:31:52.962] <TB0> INFO: start marker: 0
[12:31:52.962] <TB0> INFO: stop marker: 0
[12:31:52.962] <TB0> INFO: overflow: 0
[12:31:52.962] <TB0> INFO: invalid 5bit words: 0
[12:31:52.962] <TB0> INFO: invalid XOR eye diagram: 0
[12:31:52.962] <TB0> INFO: frame (failed synchr.): 0
[12:31:52.962] <TB0> INFO: idle data (no TBM trl): 0
[12:31:52.962] <TB0> INFO: no data (only TBM hdr): 0
[12:31:52.962] <TB0> INFO: TBM errors: 0
[12:31:52.962] <TB0> INFO: flawed TBM headers: 0
[12:31:52.962] <TB0> INFO: flawed TBM trailers: 0
[12:31:52.962] <TB0> INFO: event ID mismatches: 0
[12:31:52.962] <TB0> INFO: ROC errors: 0
[12:31:52.962] <TB0> INFO: missing ROC header(s): 0
[12:31:52.962] <TB0> INFO: misplaced readback start: 0
[12:31:52.962] <TB0> INFO: Pixel decoding errors: 0
[12:31:52.962] <TB0> INFO: pixel data incomplete: 0
[12:31:52.962] <TB0> INFO: pixel address: 0
[12:31:52.962] <TB0> INFO: pulse height fill bit: 0
[12:31:52.962] <TB0> INFO: buffer corruption: 0
[12:31:53.052] <TB0> INFO: ######################################################################
[12:31:53.052] <TB0> INFO: PixTestTrim::doTest()
[12:31:53.052] <TB0> INFO: ######################################################################
[12:31:53.053] <TB0> INFO: ----------------------------------------------------------------------
[12:31:53.053] <TB0> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:31:53.053] <TB0> INFO: ----------------------------------------------------------------------
[12:31:53.123] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:31:53.123] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:31:53.137] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:31:53.137] <TB0> INFO: run 1 of 1
[12:31:53.383] <TB0> INFO: Expecting 5025280 events.
[12:32:23.686] <TB0> INFO: 827928 events read in total (29703ms).
[12:32:53.778] <TB0> INFO: 1652904 events read in total (59795ms).
[12:33:23.811] <TB0> INFO: 2476080 events read in total (89829ms).
[12:33:53.950] <TB0> INFO: 3295704 events read in total (119967ms).
[12:34:23.746] <TB0> INFO: 4111840 events read in total (149763ms).
[12:34:53.738] <TB0> INFO: 4925424 events read in total (179755ms).
[12:34:57.877] <TB0> INFO: 5025280 events read in total (183894ms).
[12:34:57.934] <TB0> INFO: Test took 184797ms.
[12:35:14.619] <TB0> INFO: ROC 0 VthrComp = 116
[12:35:14.619] <TB0> INFO: ROC 1 VthrComp = 119
[12:35:14.619] <TB0> INFO: ROC 2 VthrComp = 114
[12:35:14.619] <TB0> INFO: ROC 3 VthrComp = 119
[12:35:14.619] <TB0> INFO: ROC 4 VthrComp = 131
[12:35:14.619] <TB0> INFO: ROC 5 VthrComp = 128
[12:35:14.619] <TB0> INFO: ROC 6 VthrComp = 114
[12:35:14.619] <TB0> INFO: ROC 7 VthrComp = 128
[12:35:14.619] <TB0> INFO: ROC 8 VthrComp = 118
[12:35:14.620] <TB0> INFO: ROC 9 VthrComp = 130
[12:35:14.620] <TB0> INFO: ROC 10 VthrComp = 121
[12:35:14.620] <TB0> INFO: ROC 11 VthrComp = 129
[12:35:14.620] <TB0> INFO: ROC 12 VthrComp = 129
[12:35:14.620] <TB0> INFO: ROC 13 VthrComp = 120
[12:35:14.620] <TB0> INFO: ROC 14 VthrComp = 117
[12:35:14.620] <TB0> INFO: ROC 15 VthrComp = 125
[12:35:14.860] <TB0> INFO: Expecting 41600 events.
[12:35:18.408] <TB0> INFO: 41600 events read in total (2956ms).
[12:35:18.409] <TB0> INFO: Test took 3787ms.
[12:35:18.417] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:35:18.418] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:35:18.431] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:35:18.431] <TB0> INFO: run 1 of 1
[12:35:18.708] <TB0> INFO: Expecting 5025280 events.
[12:35:45.053] <TB0> INFO: 591648 events read in total (25753ms).
[12:36:11.118] <TB0> INFO: 1182176 events read in total (51818ms).
[12:36:37.124] <TB0> INFO: 1772520 events read in total (77824ms).
[12:37:02.797] <TB0> INFO: 2361784 events read in total (103497ms).
[12:37:28.594] <TB0> INFO: 2949152 events read in total (129294ms).
[12:37:54.524] <TB0> INFO: 3535128 events read in total (155224ms).
[12:38:20.108] <TB0> INFO: 4120304 events read in total (180808ms).
[12:38:45.918] <TB0> INFO: 4704904 events read in total (206618ms).
[12:38:59.864] <TB0> INFO: 5025280 events read in total (220564ms).
[12:38:59.967] <TB0> INFO: Test took 221536ms.
[12:39:28.351] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 60.1538 for pixel 15/53 mean/min/max = 46.5351/32.817/60.2531
[12:39:28.351] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 56.8235 for pixel 18/1 mean/min/max = 44.542/32.0878/56.9961
[12:39:28.352] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 58.6807 for pixel 29/77 mean/min/max = 46.3586/33.523/59.1941
[12:39:28.352] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 59.9999 for pixel 20/41 mean/min/max = 46.7932/33.5732/60.0132
[12:39:28.353] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 59.3663 for pixel 51/13 mean/min/max = 45.9436/32.5054/59.3817
[12:39:28.353] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 58.7196 for pixel 35/73 mean/min/max = 45.2805/31.6771/58.8838
[12:39:28.353] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 61.6352 for pixel 51/75 mean/min/max = 47.0898/32.52/61.6597
[12:39:28.354] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 62.7165 for pixel 51/72 mean/min/max = 47.4714/32.0688/62.874
[12:39:28.354] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 59.3146 for pixel 2/6 mean/min/max = 46.5065/33.6781/59.3349
[12:39:28.355] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 56.4234 for pixel 26/79 mean/min/max = 45.2143/33.0327/57.3959
[12:39:28.355] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 61.5541 for pixel 1/44 mean/min/max = 47.8386/33.9876/61.6895
[12:39:28.356] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 57.6038 for pixel 25/8 mean/min/max = 44.9374/32.2644/57.6103
[12:39:28.356] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 58.9395 for pixel 18/3 mean/min/max = 46.2354/33.4197/59.051
[12:39:28.356] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 59.5264 for pixel 6/68 mean/min/max = 46.9792/34.4082/59.5501
[12:39:28.357] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 59.3357 for pixel 0/1 mean/min/max = 46.1453/32.9524/59.3382
[12:39:28.357] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 59.8079 for pixel 51/21 mean/min/max = 45.8494/31.8881/59.8107
[12:39:28.358] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:39:28.446] <TB0> INFO: Expecting 411648 events.
[12:39:37.923] <TB0> INFO: 411648 events read in total (8885ms).
[12:39:37.932] <TB0> INFO: Expecting 411648 events.
[12:39:47.284] <TB0> INFO: 411648 events read in total (8949ms).
[12:39:47.297] <TB0> INFO: Expecting 411648 events.
[12:39:56.761] <TB0> INFO: 411648 events read in total (9061ms).
[12:39:56.774] <TB0> INFO: Expecting 411648 events.
[12:40:06.265] <TB0> INFO: 411648 events read in total (9088ms).
[12:40:06.280] <TB0> INFO: Expecting 411648 events.
[12:40:15.833] <TB0> INFO: 411648 events read in total (9149ms).
[12:40:15.855] <TB0> INFO: Expecting 411648 events.
[12:40:25.386] <TB0> INFO: 411648 events read in total (9128ms).
[12:40:25.411] <TB0> INFO: Expecting 411648 events.
[12:40:34.896] <TB0> INFO: 411648 events read in total (9082ms).
[12:40:34.922] <TB0> INFO: Expecting 411648 events.
[12:40:44.500] <TB0> INFO: 411648 events read in total (9175ms).
[12:40:44.532] <TB0> INFO: Expecting 411648 events.
[12:40:53.999] <TB0> INFO: 411648 events read in total (9064ms).
[12:40:54.030] <TB0> INFO: Expecting 411648 events.
[12:41:03.475] <TB0> INFO: 411648 events read in total (9042ms).
[12:41:03.508] <TB0> INFO: Expecting 411648 events.
[12:41:13.030] <TB0> INFO: 411648 events read in total (9119ms).
[12:41:13.066] <TB0> INFO: Expecting 411648 events.
[12:41:22.548] <TB0> INFO: 411648 events read in total (9080ms).
[12:41:22.694] <TB0> INFO: Expecting 411648 events.
[12:41:32.191] <TB0> INFO: 411648 events read in total (9094ms).
[12:41:32.236] <TB0> INFO: Expecting 411648 events.
[12:41:41.611] <TB0> INFO: 411648 events read in total (8971ms).
[12:41:41.752] <TB0> INFO: Expecting 411648 events.
[12:41:51.106] <TB0> INFO: 411648 events read in total (8950ms).
[12:41:51.155] <TB0> INFO: Expecting 411648 events.
[12:42:00.569] <TB0> INFO: 411648 events read in total (9011ms).
[12:42:00.705] <TB0> INFO: Test took 152347ms.
[12:42:01.544] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:42:01.558] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:42:01.558] <TB0> INFO: run 1 of 1
[12:42:01.797] <TB0> INFO: Expecting 5025280 events.
[12:42:28.576] <TB0> INFO: 589160 events read in total (26188ms).
[12:42:55.126] <TB0> INFO: 1176776 events read in total (52739ms).
[12:43:21.638] <TB0> INFO: 1763832 events read in total (79250ms).
[12:43:47.966] <TB0> INFO: 2350296 events read in total (105578ms).
[12:44:14.870] <TB0> INFO: 2936664 events read in total (132482ms).
[12:44:41.441] <TB0> INFO: 3524352 events read in total (159053ms).
[12:45:08.135] <TB0> INFO: 4112136 events read in total (185747ms).
[12:45:34.972] <TB0> INFO: 4698576 events read in total (212584ms).
[12:45:49.871] <TB0> INFO: 5025280 events read in total (227483ms).
[12:45:50.014] <TB0> INFO: Test took 228457ms.
[12:46:15.849] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 1.500000 .. 136.815935
[12:46:16.174] <TB0> INFO: Expecting 208000 events.
[12:46:25.846] <TB0> INFO: 208000 events read in total (9080ms).
[12:46:25.848] <TB0> INFO: Test took 9998ms.
[12:46:25.897] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 146 (-1/-1) hits flags = 528 (plus default)
[12:46:25.910] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:46:25.910] <TB0> INFO: run 1 of 1
[12:46:26.188] <TB0> INFO: Expecting 4858880 events.
[12:46:53.139] <TB0> INFO: 587528 events read in total (26359ms).
[12:47:19.423] <TB0> INFO: 1175536 events read in total (52643ms).
[12:47:45.961] <TB0> INFO: 1763520 events read in total (79181ms).
[12:48:11.951] <TB0> INFO: 2351376 events read in total (105171ms).
[12:48:37.769] <TB0> INFO: 2938728 events read in total (130989ms).
[12:49:03.000] <TB0> INFO: 3526024 events read in total (157220ms).
[12:49:30.480] <TB0> INFO: 4113192 events read in total (183700ms).
[12:49:56.806] <TB0> INFO: 4699816 events read in total (210026ms).
[12:50:04.519] <TB0> INFO: 4858880 events read in total (217739ms).
[12:50:04.628] <TB0> INFO: Test took 218718ms.
[12:50:28.836] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 28.069397 .. 48.534129
[12:50:29.090] <TB0> INFO: Expecting 208000 events.
[12:50:39.172] <TB0> INFO: 208000 events read in total (9490ms).
[12:50:39.172] <TB0> INFO: Test took 10335ms.
[12:50:39.219] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 18 .. 58 (-1/-1) hits flags = 528 (plus default)
[12:50:39.233] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:50:39.233] <TB0> INFO: run 1 of 1
[12:50:39.511] <TB0> INFO: Expecting 1364480 events.
[12:51:07.998] <TB0> INFO: 645872 events read in total (27896ms).
[12:51:35.572] <TB0> INFO: 1289584 events read in total (55470ms).
[12:51:39.219] <TB0> INFO: 1364480 events read in total (59117ms).
[12:51:39.254] <TB0> INFO: Test took 60022ms.
[12:51:54.172] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 27.265003 .. 46.639373
[12:51:54.410] <TB0> INFO: Expecting 208000 events.
[12:52:04.296] <TB0> INFO: 208000 events read in total (9295ms).
[12:52:04.298] <TB0> INFO: Test took 10124ms.
[12:52:04.345] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[12:52:04.358] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:52:04.358] <TB0> INFO: run 1 of 1
[12:52:04.636] <TB0> INFO: Expecting 1331200 events.
[12:52:32.941] <TB0> INFO: 656768 events read in total (27713ms).
[12:53:00.839] <TB0> INFO: 1312456 events read in total (55612ms).
[12:53:02.095] <TB0> INFO: 1331200 events read in total (56868ms).
[12:53:02.124] <TB0> INFO: Test took 57767ms.
[12:53:14.537] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 24.968546 .. 46.184810
[12:53:14.776] <TB0> INFO: Expecting 208000 events.
[12:53:24.906] <TB0> INFO: 208000 events read in total (9538ms).
[12:53:24.909] <TB0> INFO: Test took 10371ms.
[12:53:24.988] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 56 (-1/-1) hits flags = 528 (plus default)
[12:53:24.002] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:53:24.002] <TB0> INFO: run 1 of 1
[12:53:25.328] <TB0> INFO: Expecting 1431040 events.
[12:53:53.956] <TB0> INFO: 667768 events read in total (28036ms).
[12:54:21.950] <TB0> INFO: 1335264 events read in total (56031ms).
[12:54:26.459] <TB0> INFO: 1431040 events read in total (60540ms).
[12:54:26.494] <TB0> INFO: Test took 61492ms.
[12:54:38.915] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:54:38.915] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:54:38.928] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:54:38.928] <TB0> INFO: run 1 of 1
[12:54:39.167] <TB0> INFO: Expecting 1364480 events.
[12:55:07.588] <TB0> INFO: 668504 events read in total (27830ms).
[12:55:35.794] <TB0> INFO: 1336104 events read in total (56037ms).
[12:55:37.447] <TB0> INFO: 1364480 events read in total (57689ms).
[12:55:37.477] <TB0> INFO: Test took 58549ms.
[12:55:51.591] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C0.dat
[12:55:51.591] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C1.dat
[12:55:51.592] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C2.dat
[12:55:51.592] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C3.dat
[12:55:51.592] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C4.dat
[12:55:51.592] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C5.dat
[12:55:51.592] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C6.dat
[12:55:51.592] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C7.dat
[12:55:51.592] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C8.dat
[12:55:51.592] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C9.dat
[12:55:51.592] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C10.dat
[12:55:51.592] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C11.dat
[12:55:51.592] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C12.dat
[12:55:51.592] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C13.dat
[12:55:51.592] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C14.dat
[12:55:51.592] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C15.dat
[12:55:51.592] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C0.dat
[12:55:51.598] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C1.dat
[12:55:51.603] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C2.dat
[12:55:51.608] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C3.dat
[12:55:51.613] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C4.dat
[12:55:51.618] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C5.dat
[12:55:51.623] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C6.dat
[12:55:51.628] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C7.dat
[12:55:51.633] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C8.dat
[12:55:51.638] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C9.dat
[12:55:51.643] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C10.dat
[12:55:51.648] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C11.dat
[12:55:51.652] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C12.dat
[12:55:51.657] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C13.dat
[12:55:51.662] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C14.dat
[12:55:51.667] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters35_C15.dat
[12:55:51.672] <TB0> INFO: PixTestTrim::trimTest() done
[12:55:51.672] <TB0> INFO: vtrim: 112 126 111 128 128 125 119 130 121 120 131 125 136 121 112 126
[12:55:51.672] <TB0> INFO: vthrcomp: 116 119 114 119 131 128 114 128 118 130 121 129 129 120 117 125
[12:55:51.672] <TB0> INFO: vcal mean: 35.07 34.95 34.92 35.07 34.96 34.95 34.99 34.99 35.08 35.00 35.37 34.86 34.92 35.21 34.93 35.02
[12:55:51.672] <TB0> INFO: vcal RMS: 1.17 0.97 1.06 1.08 0.99 1.09 1.14 1.21 1.21 1.02 1.44 1.10 1.02 1.27 1.00 1.11
[12:55:51.672] <TB0> INFO: bits mean: 9.10 10.13 9.12 8.94 9.35 9.80 9.31 8.84 9.46 8.84 8.90 9.67 9.23 8.66 8.53 9.70
[12:55:51.672] <TB0> INFO: bits RMS: 2.76 2.48 2.68 2.73 2.75 2.71 2.68 2.91 2.57 2.92 2.71 2.65 2.66 2.77 3.02 2.64
[12:55:51.680] <TB0> INFO: ----------------------------------------------------------------------
[12:55:51.680] <TB0> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:55:51.680] <TB0> INFO: ----------------------------------------------------------------------
[12:55:51.684] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:55:51.702] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:55:51.702] <TB0> INFO: run 1 of 1
[12:55:51.987] <TB0> INFO: Expecting 4160000 events.
[12:56:25.360] <TB0> INFO: 763930 events read in total (32781ms).
[12:56:57.668] <TB0> INFO: 1521235 events read in total (65089ms).
[12:57:29.915] <TB0> INFO: 2273520 events read in total (97336ms).
[12:58:01.788] <TB0> INFO: 3021210 events read in total (129209ms).
[12:58:33.707] <TB0> INFO: 3765120 events read in total (161128ms).
[12:58:50.783] <TB0> INFO: 4160000 events read in total (178204ms).
[12:58:50.879] <TB0> INFO: Test took 179176ms.
[12:59:17.963] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[12:59:17.976] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:59:17.976] <TB0> INFO: run 1 of 1
[12:59:18.212] <TB0> INFO: Expecting 4284800 events.
[12:59:51.399] <TB0> INFO: 730245 events read in total (32595ms).
[13:00:22.753] <TB0> INFO: 1455680 events read in total (63949ms).
[13:00:54.185] <TB0> INFO: 2177835 events read in total (95381ms).
[13:01:25.409] <TB0> INFO: 2894390 events read in total (126605ms).
[13:01:56.881] <TB0> INFO: 3608900 events read in total (158077ms).
[13:02:26.382] <TB0> INFO: 4284800 events read in total (187578ms).
[13:02:26.490] <TB0> INFO: Test took 188514ms.
[13:02:53.397] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 191 (-1/-1) hits flags = 528 (plus default)
[13:02:53.410] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:02:53.410] <TB0> INFO: run 1 of 1
[13:02:53.681] <TB0> INFO: Expecting 3993600 events.
[13:03:27.292] <TB0> INFO: 751215 events read in total (33019ms).
[13:03:59.257] <TB0> INFO: 1496195 events read in total (64984ms).
[13:04:31.058] <TB0> INFO: 2236550 events read in total (96785ms).
[13:05:02.659] <TB0> INFO: 2970980 events read in total (128386ms).
[13:05:34.125] <TB0> INFO: 3702700 events read in total (159852ms).
[13:05:46.838] <TB0> INFO: 3993600 events read in total (172565ms).
[13:05:46.925] <TB0> INFO: Test took 173514ms.
[13:06:10.816] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 193 (-1/-1) hits flags = 528 (plus default)
[13:06:10.829] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:06:10.830] <TB0> INFO: run 1 of 1
[13:06:11.106] <TB0> INFO: Expecting 4035200 events.
[13:06:43.720] <TB0> INFO: 747865 events read in total (32023ms).
[13:07:16.275] <TB0> INFO: 1490110 events read in total (64578ms).
[13:07:48.024] <TB0> INFO: 2227625 events read in total (96327ms).
[13:08:19.808] <TB0> INFO: 2959940 events read in total (128111ms).
[13:08:51.732] <TB0> INFO: 3688675 events read in total (160035ms).
[13:09:06.764] <TB0> INFO: 4035200 events read in total (175067ms).
[13:09:06.894] <TB0> INFO: Test took 176064ms.
[13:09:29.936] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[13:09:29.949] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:09:29.949] <TB0> INFO: run 1 of 1
[13:09:30.184] <TB0> INFO: Expecting 4097600 events.
[13:10:03.135] <TB0> INFO: 743450 events read in total (32359ms).
[13:10:35.914] <TB0> INFO: 1481205 events read in total (65138ms).
[13:11:07.352] <TB0> INFO: 2214985 events read in total (96577ms).
[13:11:38.811] <TB0> INFO: 2943355 events read in total (128035ms).
[13:12:10.250] <TB0> INFO: 3668190 events read in total (159474ms).
[13:12:28.931] <TB0> INFO: 4097600 events read in total (178155ms).
[13:12:29.011] <TB0> INFO: Test took 179063ms.
[13:12:55.791] <TB0> INFO: PixTestTrim::trimBitTest() done
[13:12:55.792] <TB0> INFO: PixTestTrim::doTest() done, duration: 2462 seconds
[13:12:55.792] <TB0> INFO: Decoding statistics:
[13:12:55.792] <TB0> INFO: General information:
[13:12:55.792] <TB0> INFO: 16bit words read: 0
[13:12:55.792] <TB0> INFO: valid events total: 0
[13:12:55.792] <TB0> INFO: empty events: 0
[13:12:55.792] <TB0> INFO: valid events with pixels: 0
[13:12:55.792] <TB0> INFO: valid pixel hits: 0
[13:12:55.792] <TB0> INFO: Event errors: 0
[13:12:55.792] <TB0> INFO: start marker: 0
[13:12:55.792] <TB0> INFO: stop marker: 0
[13:12:55.792] <TB0> INFO: overflow: 0
[13:12:55.792] <TB0> INFO: invalid 5bit words: 0
[13:12:55.792] <TB0> INFO: invalid XOR eye diagram: 0
[13:12:55.792] <TB0> INFO: frame (failed synchr.): 0
[13:12:55.792] <TB0> INFO: idle data (no TBM trl): 0
[13:12:55.792] <TB0> INFO: no data (only TBM hdr): 0
[13:12:55.792] <TB0> INFO: TBM errors: 0
[13:12:55.792] <TB0> INFO: flawed TBM headers: 0
[13:12:55.792] <TB0> INFO: flawed TBM trailers: 0
[13:12:55.792] <TB0> INFO: event ID mismatches: 0
[13:12:55.792] <TB0> INFO: ROC errors: 0
[13:12:55.792] <TB0> INFO: missing ROC header(s): 0
[13:12:55.792] <TB0> INFO: misplaced readback start: 0
[13:12:55.792] <TB0> INFO: Pixel decoding errors: 0
[13:12:55.792] <TB0> INFO: pixel data incomplete: 0
[13:12:55.792] <TB0> INFO: pixel address: 0
[13:12:55.792] <TB0> INFO: pulse height fill bit: 0
[13:12:55.792] <TB0> INFO: buffer corruption: 0
[13:12:56.411] <TB0> INFO: ######################################################################
[13:12:56.411] <TB0> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:12:56.411] <TB0> INFO: ######################################################################
[13:12:56.652] <TB0> INFO: Expecting 41600 events.
[13:13:00.113] <TB0> INFO: 41600 events read in total (2870ms).
[13:13:00.114] <TB0> INFO: Test took 3701ms.
[13:13:00.557] <TB0> INFO: Expecting 41600 events.
[13:13:04.055] <TB0> INFO: 41600 events read in total (2906ms).
[13:13:04.057] <TB0> INFO: Test took 3738ms.
[13:13:04.345] <TB0> INFO: Expecting 41600 events.
[13:13:07.913] <TB0> INFO: 41600 events read in total (2976ms).
[13:13:07.914] <TB0> INFO: Test took 3833ms.
[13:13:08.204] <TB0> INFO: Expecting 41600 events.
[13:13:11.765] <TB0> INFO: 41600 events read in total (2970ms).
[13:13:11.766] <TB0> INFO: Test took 3827ms.
[13:13:12.058] <TB0> INFO: Expecting 41600 events.
[13:13:15.664] <TB0> INFO: 41600 events read in total (3014ms).
[13:13:15.665] <TB0> INFO: Test took 3871ms.
[13:13:15.957] <TB0> INFO: Expecting 41600 events.
[13:13:19.545] <TB0> INFO: 41600 events read in total (2997ms).
[13:13:19.546] <TB0> INFO: Test took 3854ms.
[13:13:19.835] <TB0> INFO: Expecting 41600 events.
[13:13:23.440] <TB0> INFO: 41600 events read in total (3014ms).
[13:13:23.441] <TB0> INFO: Test took 3871ms.
[13:13:23.732] <TB0> INFO: Expecting 41600 events.
[13:13:27.303] <TB0> INFO: 41600 events read in total (2980ms).
[13:13:27.304] <TB0> INFO: Test took 3837ms.
[13:13:27.594] <TB0> INFO: Expecting 41600 events.
[13:13:31.063] <TB0> INFO: 41600 events read in total (2878ms).
[13:13:31.064] <TB0> INFO: Test took 3737ms.
[13:13:31.354] <TB0> INFO: Expecting 41600 events.
[13:13:34.933] <TB0> INFO: 41600 events read in total (2988ms).
[13:13:34.934] <TB0> INFO: Test took 3845ms.
[13:13:35.225] <TB0> INFO: Expecting 41600 events.
[13:13:38.763] <TB0> INFO: 41600 events read in total (2946ms).
[13:13:38.764] <TB0> INFO: Test took 3803ms.
[13:13:39.054] <TB0> INFO: Expecting 41600 events.
[13:13:42.637] <TB0> INFO: 41600 events read in total (2991ms).
[13:13:42.638] <TB0> INFO: Test took 3849ms.
[13:13:42.927] <TB0> INFO: Expecting 41600 events.
[13:13:46.421] <TB0> INFO: 41600 events read in total (2902ms).
[13:13:46.422] <TB0> INFO: Test took 3760ms.
[13:13:46.711] <TB0> INFO: Expecting 41600 events.
[13:13:50.294] <TB0> INFO: 41600 events read in total (2992ms).
[13:13:50.296] <TB0> INFO: Test took 3850ms.
[13:13:50.588] <TB0> INFO: Expecting 41600 events.
[13:13:54.134] <TB0> INFO: 41600 events read in total (2954ms).
[13:13:54.136] <TB0> INFO: Test took 3813ms.
[13:13:54.426] <TB0> INFO: Expecting 41600 events.
[13:13:58.004] <TB0> INFO: 41600 events read in total (2987ms).
[13:13:58.005] <TB0> INFO: Test took 3844ms.
[13:13:58.295] <TB0> INFO: Expecting 41600 events.
[13:14:01.821] <TB0> INFO: 41600 events read in total (2934ms).
[13:14:01.822] <TB0> INFO: Test took 3792ms.
[13:14:02.112] <TB0> INFO: Expecting 41600 events.
[13:14:05.673] <TB0> INFO: 41600 events read in total (2970ms).
[13:14:05.675] <TB0> INFO: Test took 3828ms.
[13:14:06.030] <TB0> INFO: Expecting 41600 events.
[13:14:09.768] <TB0> INFO: 41600 events read in total (3146ms).
[13:14:09.769] <TB0> INFO: Test took 4065ms.
[13:14:10.071] <TB0> INFO: Expecting 41600 events.
[13:14:13.626] <TB0> INFO: 41600 events read in total (2964ms).
[13:14:13.627] <TB0> INFO: Test took 3831ms.
[13:14:13.917] <TB0> INFO: Expecting 41600 events.
[13:14:17.704] <TB0> INFO: 41600 events read in total (3195ms).
[13:14:17.705] <TB0> INFO: Test took 4052ms.
[13:14:17.995] <TB0> INFO: Expecting 41600 events.
[13:14:21.665] <TB0> INFO: 41600 events read in total (3079ms).
[13:14:21.666] <TB0> INFO: Test took 3936ms.
[13:14:21.994] <TB0> INFO: Expecting 41600 events.
[13:14:25.483] <TB0> INFO: 41600 events read in total (2897ms).
[13:14:25.484] <TB0> INFO: Test took 3789ms.
[13:14:25.799] <TB0> INFO: Expecting 41600 events.
[13:14:29.378] <TB0> INFO: 41600 events read in total (2986ms).
[13:14:29.379] <TB0> INFO: Test took 3870ms.
[13:14:29.668] <TB0> INFO: Expecting 41600 events.
[13:14:33.140] <TB0> INFO: 41600 events read in total (2881ms).
[13:14:33.141] <TB0> INFO: Test took 3738ms.
[13:14:33.431] <TB0> INFO: Expecting 41600 events.
[13:14:36.910] <TB0> INFO: 41600 events read in total (2888ms).
[13:14:36.911] <TB0> INFO: Test took 3745ms.
[13:14:37.200] <TB0> INFO: Expecting 41600 events.
[13:14:40.749] <TB0> INFO: 41600 events read in total (2957ms).
[13:14:40.750] <TB0> INFO: Test took 3814ms.
[13:14:41.041] <TB0> INFO: Expecting 41600 events.
[13:14:44.575] <TB0> INFO: 41600 events read in total (2942ms).
[13:14:44.575] <TB0> INFO: Test took 3799ms.
[13:14:44.865] <TB0> INFO: Expecting 2560 events.
[13:14:45.757] <TB0> INFO: 2560 events read in total (300ms).
[13:14:45.757] <TB0> INFO: Test took 1168ms.
[13:14:46.066] <TB0> INFO: Expecting 2560 events.
[13:14:46.963] <TB0> INFO: 2560 events read in total (305ms).
[13:14:46.963] <TB0> INFO: Test took 1206ms.
[13:14:47.271] <TB0> INFO: Expecting 2560 events.
[13:14:48.156] <TB0> INFO: 2560 events read in total (293ms).
[13:14:48.156] <TB0> INFO: Test took 1192ms.
[13:14:48.464] <TB0> INFO: Expecting 2560 events.
[13:14:49.350] <TB0> INFO: 2560 events read in total (294ms).
[13:14:49.350] <TB0> INFO: Test took 1193ms.
[13:14:49.657] <TB0> INFO: Expecting 2560 events.
[13:14:50.548] <TB0> INFO: 2560 events read in total (299ms).
[13:14:50.548] <TB0> INFO: Test took 1197ms.
[13:14:50.856] <TB0> INFO: Expecting 2560 events.
[13:14:51.746] <TB0> INFO: 2560 events read in total (298ms).
[13:14:51.746] <TB0> INFO: Test took 1196ms.
[13:14:52.054] <TB0> INFO: Expecting 2560 events.
[13:14:52.934] <TB0> INFO: 2560 events read in total (288ms).
[13:14:52.934] <TB0> INFO: Test took 1188ms.
[13:14:53.243] <TB0> INFO: Expecting 2560 events.
[13:14:54.131] <TB0> INFO: 2560 events read in total (296ms).
[13:14:54.131] <TB0> INFO: Test took 1196ms.
[13:14:54.439] <TB0> INFO: Expecting 2560 events.
[13:14:55.329] <TB0> INFO: 2560 events read in total (299ms).
[13:14:55.330] <TB0> INFO: Test took 1198ms.
[13:14:55.637] <TB0> INFO: Expecting 2560 events.
[13:14:56.516] <TB0> INFO: 2560 events read in total (287ms).
[13:14:56.516] <TB0> INFO: Test took 1185ms.
[13:14:56.824] <TB0> INFO: Expecting 2560 events.
[13:14:57.710] <TB0> INFO: 2560 events read in total (294ms).
[13:14:57.711] <TB0> INFO: Test took 1195ms.
[13:14:58.019] <TB0> INFO: Expecting 2560 events.
[13:14:58.910] <TB0> INFO: 2560 events read in total (299ms).
[13:14:58.910] <TB0> INFO: Test took 1199ms.
[13:14:59.218] <TB0> INFO: Expecting 2560 events.
[13:15:00.103] <TB0> INFO: 2560 events read in total (293ms).
[13:15:00.103] <TB0> INFO: Test took 1192ms.
[13:15:00.411] <TB0> INFO: Expecting 2560 events.
[13:15:01.298] <TB0> INFO: 2560 events read in total (296ms).
[13:15:01.298] <TB0> INFO: Test took 1194ms.
[13:15:01.606] <TB0> INFO: Expecting 2560 events.
[13:15:02.503] <TB0> INFO: 2560 events read in total (306ms).
[13:15:02.503] <TB0> INFO: Test took 1204ms.
[13:15:02.812] <TB0> INFO: Expecting 2560 events.
[13:15:03.704] <TB0> INFO: 2560 events read in total (301ms).
[13:15:03.704] <TB0> INFO: Test took 1200ms.
[13:15:03.708] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:04.013] <TB0> INFO: Expecting 655360 events.
[13:15:18.993] <TB0> INFO: 655360 events read in total (14388ms).
[13:15:19.012] <TB0> INFO: Expecting 655360 events.
[13:15:33.955] <TB0> INFO: 655360 events read in total (14540ms).
[13:15:33.974] <TB0> INFO: Expecting 655360 events.
[13:15:48.800] <TB0> INFO: 655360 events read in total (14423ms).
[13:15:48.829] <TB0> INFO: Expecting 655360 events.
[13:16:03.670] <TB0> INFO: 655360 events read in total (14437ms).
[13:16:03.697] <TB0> INFO: Expecting 655360 events.
[13:16:18.716] <TB0> INFO: 655360 events read in total (14615ms).
[13:16:18.749] <TB0> INFO: Expecting 655360 events.
[13:16:34.018] <TB0> INFO: 655360 events read in total (14866ms).
[13:16:34.066] <TB0> INFO: Expecting 655360 events.
[13:16:48.714] <TB0> INFO: 655360 events read in total (14245ms).
[13:16:48.764] <TB0> INFO: Expecting 655360 events.
[13:17:03.447] <TB0> INFO: 655360 events read in total (14280ms).
[13:17:03.504] <TB0> INFO: Expecting 655360 events.
[13:17:18.173] <TB0> INFO: 655360 events read in total (14266ms).
[13:17:18.237] <TB0> INFO: Expecting 655360 events.
[13:17:32.932] <TB0> INFO: 655360 events read in total (14292ms).
[13:17:33.003] <TB0> INFO: Expecting 655360 events.
[13:17:47.667] <TB0> INFO: 655360 events read in total (14261ms).
[13:17:47.769] <TB0> INFO: Expecting 655360 events.
[13:18:02.477] <TB0> INFO: 655360 events read in total (14305ms).
[13:18:02.574] <TB0> INFO: Expecting 655360 events.
[13:18:17.219] <TB0> INFO: 655360 events read in total (14242ms).
[13:18:17.331] <TB0> INFO: Expecting 655360 events.
[13:18:32.036] <TB0> INFO: 655360 events read in total (14302ms).
[13:18:32.166] <TB0> INFO: Expecting 655360 events.
[13:18:46.810] <TB0> INFO: 655360 events read in total (14242ms).
[13:18:46.909] <TB0> INFO: Expecting 655360 events.
[13:19:01.536] <TB0> INFO: 655360 events read in total (14224ms).
[13:19:01.644] <TB0> INFO: Test took 237936ms.
[13:19:01.757] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:19:02.008] <TB0> INFO: Expecting 655360 events.
[13:19:16.642] <TB0> INFO: 655360 events read in total (14043ms).
[13:19:16.661] <TB0> INFO: Expecting 655360 events.
[13:19:31.268] <TB0> INFO: 655360 events read in total (14204ms).
[13:19:31.294] <TB0> INFO: Expecting 655360 events.
[13:19:45.899] <TB0> INFO: 655360 events read in total (14202ms).
[13:19:45.926] <TB0> INFO: Expecting 655360 events.
[13:20:00.477] <TB0> INFO: 655360 events read in total (14148ms).
[13:20:00.508] <TB0> INFO: Expecting 655360 events.
[13:20:15.163] <TB0> INFO: 655360 events read in total (14252ms).
[13:20:15.202] <TB0> INFO: Expecting 655360 events.
[13:20:29.686] <TB0> INFO: 655360 events read in total (14081ms).
[13:20:29.723] <TB0> INFO: Expecting 655360 events.
[13:20:44.211] <TB0> INFO: 655360 events read in total (14085ms).
[13:20:44.252] <TB0> INFO: Expecting 655360 events.
[13:20:58.669] <TB0> INFO: 655360 events read in total (14014ms).
[13:20:58.723] <TB0> INFO: Expecting 655360 events.
[13:21:13.099] <TB0> INFO: 655360 events read in total (13973ms).
[13:21:13.160] <TB0> INFO: Expecting 655360 events.
[13:21:27.578] <TB0> INFO: 655360 events read in total (14015ms).
[13:21:27.646] <TB0> INFO: Expecting 655360 events.
[13:21:42.005] <TB0> INFO: 655360 events read in total (13956ms).
[13:21:42.101] <TB0> INFO: Expecting 655360 events.
[13:21:56.627] <TB0> INFO: 655360 events read in total (14123ms).
[13:21:56.703] <TB0> INFO: Expecting 655360 events.
[13:22:11.054] <TB0> INFO: 655360 events read in total (13948ms).
[13:22:11.197] <TB0> INFO: Expecting 655360 events.
[13:22:25.445] <TB0> INFO: 655360 events read in total (13845ms).
[13:22:25.563] <TB0> INFO: Expecting 655360 events.
[13:22:39.959] <TB0> INFO: 655360 events read in total (13993ms).
[13:22:40.109] <TB0> INFO: Expecting 655360 events.
[13:22:54.217] <TB0> INFO: 655360 events read in total (13705ms).
[13:22:54.321] <TB0> INFO: Test took 232564ms.
[13:22:54.508] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.515] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.521] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[13:22:54.530] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.537] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[13:22:54.546] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[13:22:54.552] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[13:22:54.558] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[13:22:54.564] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[13:22:54.570] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[13:22:54.576] <TB0> INFO: safety margin for low PH: adding 7, margin is now 27
[13:22:54.581] <TB0> INFO: safety margin for low PH: adding 8, margin is now 28
[13:22:54.587] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.593] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.599] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[13:22:54.605] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[13:22:54.611] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[13:22:54.618] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[13:22:54.625] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[13:22:54.631] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[13:22:54.638] <TB0> INFO: safety margin for low PH: adding 7, margin is now 27
[13:22:54.645] <TB0> INFO: safety margin for low PH: adding 8, margin is now 28
[13:22:54.651] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.658] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.664] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[13:22:54.670] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[13:22:54.677] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.684] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[13:22:54.690] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[13:22:54.696] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.702] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.709] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.715] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.722] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.728] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[13:22:54.734] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[13:22:54.741] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[13:22:54.748] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[13:22:54.754] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[13:22:54.761] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[13:22:54.769] <TB0> INFO: safety margin for low PH: adding 7, margin is now 27
[13:22:54.777] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.785] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.794] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:22:54.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C0.dat
[13:22:54.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C1.dat
[13:22:54.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C2.dat
[13:22:54.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C3.dat
[13:22:54.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C4.dat
[13:22:54.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C5.dat
[13:22:54.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C6.dat
[13:22:54.831] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C7.dat
[13:22:54.832] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C8.dat
[13:22:54.832] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C9.dat
[13:22:54.832] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C10.dat
[13:22:54.832] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C11.dat
[13:22:54.832] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C12.dat
[13:22:54.832] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C13.dat
[13:22:54.832] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C14.dat
[13:22:54.832] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters35_C15.dat
[13:22:55.072] <TB0> INFO: Expecting 41600 events.
[13:22:58.219] <TB0> INFO: 41600 events read in total (2555ms).
[13:22:58.220] <TB0> INFO: Test took 3385ms.
[13:22:58.676] <TB0> INFO: Expecting 41600 events.
[13:23:01.737] <TB0> INFO: 41600 events read in total (2470ms).
[13:23:01.738] <TB0> INFO: Test took 3303ms.
[13:23:02.224] <TB0> INFO: Expecting 41600 events.
[13:23:05.338] <TB0> INFO: 41600 events read in total (2523ms).
[13:23:05.339] <TB0> INFO: Test took 3388ms.
[13:23:05.559] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:05.648] <TB0> INFO: Expecting 2560 events.
[13:23:06.534] <TB0> INFO: 2560 events read in total (294ms).
[13:23:06.535] <TB0> INFO: Test took 976ms.
[13:23:06.540] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:06.844] <TB0> INFO: Expecting 2560 events.
[13:23:07.729] <TB0> INFO: 2560 events read in total (294ms).
[13:23:07.730] <TB0> INFO: Test took 1190ms.
[13:23:07.734] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:08.037] <TB0> INFO: Expecting 2560 events.
[13:23:08.930] <TB0> INFO: 2560 events read in total (301ms).
[13:23:08.931] <TB0> INFO: Test took 1197ms.
[13:23:08.934] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:09.240] <TB0> INFO: Expecting 2560 events.
[13:23:10.133] <TB0> INFO: 2560 events read in total (301ms).
[13:23:10.134] <TB0> INFO: Test took 1200ms.
[13:23:10.137] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:10.442] <TB0> INFO: Expecting 2560 events.
[13:23:11.335] <TB0> INFO: 2560 events read in total (301ms).
[13:23:11.336] <TB0> INFO: Test took 1199ms.
[13:23:11.339] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:11.644] <TB0> INFO: Expecting 2560 events.
[13:23:12.535] <TB0> INFO: 2560 events read in total (299ms).
[13:23:12.536] <TB0> INFO: Test took 1197ms.
[13:23:12.539] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:12.843] <TB0> INFO: Expecting 2560 events.
[13:23:13.733] <TB0> INFO: 2560 events read in total (298ms).
[13:23:13.733] <TB0> INFO: Test took 1194ms.
[13:23:13.736] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:14.042] <TB0> INFO: Expecting 2560 events.
[13:23:14.927] <TB0> INFO: 2560 events read in total (294ms).
[13:23:14.928] <TB0> INFO: Test took 1192ms.
[13:23:14.930] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:15.236] <TB0> INFO: Expecting 2560 events.
[13:23:16.118] <TB0> INFO: 2560 events read in total (290ms).
[13:23:16.118] <TB0> INFO: Test took 1189ms.
[13:23:16.122] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:16.427] <TB0> INFO: Expecting 2560 events.
[13:23:17.307] <TB0> INFO: 2560 events read in total (288ms).
[13:23:17.307] <TB0> INFO: Test took 1185ms.
[13:23:17.311] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:17.616] <TB0> INFO: Expecting 2560 events.
[13:23:18.500] <TB0> INFO: 2560 events read in total (292ms).
[13:23:18.501] <TB0> INFO: Test took 1190ms.
[13:23:18.503] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:18.809] <TB0> INFO: Expecting 2560 events.
[13:23:19.691] <TB0> INFO: 2560 events read in total (290ms).
[13:23:19.691] <TB0> INFO: Test took 1188ms.
[13:23:19.694] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:19.000] <TB0> INFO: Expecting 2560 events.
[13:23:20.883] <TB0> INFO: 2560 events read in total (292ms).
[13:23:20.884] <TB0> INFO: Test took 1190ms.
[13:23:20.887] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:21.192] <TB0> INFO: Expecting 2560 events.
[13:23:22.074] <TB0> INFO: 2560 events read in total (290ms).
[13:23:22.074] <TB0> INFO: Test took 1188ms.
[13:23:22.078] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:22.381] <TB0> INFO: Expecting 2560 events.
[13:23:23.265] <TB0> INFO: 2560 events read in total (292ms).
[13:23:23.265] <TB0> INFO: Test took 1187ms.
[13:23:23.267] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:23.574] <TB0> INFO: Expecting 2560 events.
[13:23:24.463] <TB0> INFO: 2560 events read in total (298ms).
[13:23:24.463] <TB0> INFO: Test took 1196ms.
[13:23:24.467] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:24.771] <TB0> INFO: Expecting 2560 events.
[13:23:25.661] <TB0> INFO: 2560 events read in total (298ms).
[13:23:25.662] <TB0> INFO: Test took 1195ms.
[13:23:25.665] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:25.970] <TB0> INFO: Expecting 2560 events.
[13:23:26.860] <TB0> INFO: 2560 events read in total (298ms).
[13:23:26.861] <TB0> INFO: Test took 1197ms.
[13:23:26.864] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:27.169] <TB0> INFO: Expecting 2560 events.
[13:23:28.059] <TB0> INFO: 2560 events read in total (298ms).
[13:23:28.059] <TB0> INFO: Test took 1195ms.
[13:23:28.063] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:28.367] <TB0> INFO: Expecting 2560 events.
[13:23:29.253] <TB0> INFO: 2560 events read in total (294ms).
[13:23:29.253] <TB0> INFO: Test took 1190ms.
[13:23:29.255] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:29.561] <TB0> INFO: Expecting 2560 events.
[13:23:30.439] <TB0> INFO: 2560 events read in total (286ms).
[13:23:30.440] <TB0> INFO: Test took 1185ms.
[13:23:30.443] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:30.747] <TB0> INFO: Expecting 2560 events.
[13:23:31.627] <TB0> INFO: 2560 events read in total (288ms).
[13:23:31.627] <TB0> INFO: Test took 1184ms.
[13:23:31.630] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:31.935] <TB0> INFO: Expecting 2560 events.
[13:23:32.823] <TB0> INFO: 2560 events read in total (296ms).
[13:23:32.823] <TB0> INFO: Test took 1193ms.
[13:23:32.825] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:33.132] <TB0> INFO: Expecting 2560 events.
[13:23:34.018] <TB0> INFO: 2560 events read in total (295ms).
[13:23:34.018] <TB0> INFO: Test took 1193ms.
[13:23:34.020] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:34.326] <TB0> INFO: Expecting 2560 events.
[13:23:35.212] <TB0> INFO: 2560 events read in total (294ms).
[13:23:35.212] <TB0> INFO: Test took 1192ms.
[13:23:35.214] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:35.520] <TB0> INFO: Expecting 2560 events.
[13:23:36.408] <TB0> INFO: 2560 events read in total (296ms).
[13:23:36.409] <TB0> INFO: Test took 1195ms.
[13:23:36.413] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:36.717] <TB0> INFO: Expecting 2560 events.
[13:23:37.609] <TB0> INFO: 2560 events read in total (300ms).
[13:23:37.609] <TB0> INFO: Test took 1196ms.
[13:23:37.611] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:37.919] <TB0> INFO: Expecting 2560 events.
[13:23:38.813] <TB0> INFO: 2560 events read in total (302ms).
[13:23:38.813] <TB0> INFO: Test took 1202ms.
[13:23:38.816] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:39.121] <TB0> INFO: Expecting 2560 events.
[13:23:40.014] <TB0> INFO: 2560 events read in total (301ms).
[13:23:40.014] <TB0> INFO: Test took 1198ms.
[13:23:40.017] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:40.323] <TB0> INFO: Expecting 2560 events.
[13:23:41.215] <TB0> INFO: 2560 events read in total (300ms).
[13:23:41.216] <TB0> INFO: Test took 1199ms.
[13:23:41.220] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:41.524] <TB0> INFO: Expecting 2560 events.
[13:23:42.408] <TB0> INFO: 2560 events read in total (293ms).
[13:23:42.408] <TB0> INFO: Test took 1189ms.
[13:23:42.411] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:42.717] <TB0> INFO: Expecting 2560 events.
[13:23:43.605] <TB0> INFO: 2560 events read in total (296ms).
[13:23:43.605] <TB0> INFO: Test took 1194ms.
[13:23:44.079] <TB0> INFO: PixTestPhOptimization::doTest() done, duration: 647 seconds
[13:23:44.080] <TB0> INFO: PH scale (per ROC): 38 34 48 61 44 53 35 45 54 55 45 49 44 42 43 32
[13:23:44.080] <TB0> INFO: PH offset (per ROC): 99 100 113 122 99 113 100 111 124 125 109 125 107 115 110 93
[13:23:44.086] <TB0> INFO: Decoding statistics:
[13:23:44.087] <TB0> INFO: General information:
[13:23:44.087] <TB0> INFO: 16bit words read: 127880
[13:23:44.087] <TB0> INFO: valid events total: 20480
[13:23:44.087] <TB0> INFO: empty events: 17980
[13:23:44.087] <TB0> INFO: valid events with pixels: 2500
[13:23:44.087] <TB0> INFO: valid pixel hits: 2500
[13:23:44.087] <TB0> INFO: Event errors: 0
[13:23:44.087] <TB0> INFO: start marker: 0
[13:23:44.087] <TB0> INFO: stop marker: 0
[13:23:44.087] <TB0> INFO: overflow: 0
[13:23:44.087] <TB0> INFO: invalid 5bit words: 0
[13:23:44.087] <TB0> INFO: invalid XOR eye diagram: 0
[13:23:44.087] <TB0> INFO: frame (failed synchr.): 0
[13:23:44.087] <TB0> INFO: idle data (no TBM trl): 0
[13:23:44.087] <TB0> INFO: no data (only TBM hdr): 0
[13:23:44.087] <TB0> INFO: TBM errors: 0
[13:23:44.087] <TB0> INFO: flawed TBM headers: 0
[13:23:44.087] <TB0> INFO: flawed TBM trailers: 0
[13:23:44.087] <TB0> INFO: event ID mismatches: 0
[13:23:44.087] <TB0> INFO: ROC errors: 0
[13:23:44.087] <TB0> INFO: missing ROC header(s): 0
[13:23:44.087] <TB0> INFO: misplaced readback start: 0
[13:23:44.087] <TB0> INFO: Pixel decoding errors: 0
[13:23:44.087] <TB0> INFO: pixel data incomplete: 0
[13:23:44.087] <TB0> INFO: pixel address: 0
[13:23:44.087] <TB0> INFO: pulse height fill bit: 0
[13:23:44.087] <TB0> INFO: buffer corruption: 0
[13:23:44.250] <TB0> INFO: ######################################################################
[13:23:44.250] <TB0> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:23:44.250] <TB0> INFO: ######################################################################
[13:23:44.265] <TB0> INFO: scanning low vcal = 10
[13:23:44.509] <TB0> INFO: Expecting 41600 events.
[13:23:48.103] <TB0> INFO: 41600 events read in total (3002ms).
[13:23:48.104] <TB0> INFO: Test took 3839ms.
[13:23:48.106] <TB0> INFO: scanning low vcal = 20
[13:23:48.404] <TB0> INFO: Expecting 41600 events.
[13:23:51.988] <TB0> INFO: 41600 events read in total (2992ms).
[13:23:51.989] <TB0> INFO: Test took 3883ms.
[13:23:51.991] <TB0> INFO: scanning low vcal = 30
[13:23:52.285] <TB0> INFO: Expecting 41600 events.
[13:23:55.999] <TB0> INFO: 41600 events read in total (3122ms).
[13:23:55.000] <TB0> INFO: Test took 4009ms.
[13:23:55.002] <TB0> INFO: scanning low vcal = 40
[13:23:56.280] <TB0> INFO: Expecting 41600 events.
[13:24:00.226] <TB0> INFO: 41600 events read in total (3354ms).
[13:24:00.227] <TB0> INFO: Test took 4224ms.
[13:24:00.231] <TB0> INFO: scanning low vcal = 50
[13:24:00.508] <TB0> INFO: Expecting 41600 events.
[13:24:04.497] <TB0> INFO: 41600 events read in total (3398ms).
[13:24:04.498] <TB0> INFO: Test took 4267ms.
[13:24:04.501] <TB0> INFO: scanning low vcal = 60
[13:24:04.778] <TB0> INFO: Expecting 41600 events.
[13:24:08.821] <TB0> INFO: 41600 events read in total (3452ms).
[13:24:08.822] <TB0> INFO: Test took 4321ms.
[13:24:08.825] <TB0> INFO: scanning low vcal = 70
[13:24:09.112] <TB0> INFO: Expecting 41600 events.
[13:24:13.073] <TB0> INFO: 41600 events read in total (3369ms).
[13:24:13.073] <TB0> INFO: Test took 4247ms.
[13:24:13.077] <TB0> INFO: scanning low vcal = 80
[13:24:13.353] <TB0> INFO: Expecting 41600 events.
[13:24:17.341] <TB0> INFO: 41600 events read in total (3396ms).
[13:24:17.342] <TB0> INFO: Test took 4265ms.
[13:24:17.346] <TB0> INFO: scanning low vcal = 90
[13:24:17.622] <TB0> INFO: Expecting 41600 events.
[13:24:21.584] <TB0> INFO: 41600 events read in total (3370ms).
[13:24:21.586] <TB0> INFO: Test took 4240ms.
[13:24:21.593] <TB0> INFO: scanning low vcal = 100
[13:24:21.867] <TB0> INFO: Expecting 41600 events.
[13:24:25.867] <TB0> INFO: 41600 events read in total (3408ms).
[13:24:25.868] <TB0> INFO: Test took 4275ms.
[13:24:25.871] <TB0> INFO: scanning low vcal = 110
[13:24:26.148] <TB0> INFO: Expecting 41600 events.
[13:24:30.174] <TB0> INFO: 41600 events read in total (3434ms).
[13:24:30.175] <TB0> INFO: Test took 4304ms.
[13:24:30.178] <TB0> INFO: scanning low vcal = 120
[13:24:30.455] <TB0> INFO: Expecting 41600 events.
[13:24:34.502] <TB0> INFO: 41600 events read in total (3455ms).
[13:24:34.503] <TB0> INFO: Test took 4325ms.
[13:24:34.506] <TB0> INFO: scanning low vcal = 130
[13:24:34.783] <TB0> INFO: Expecting 41600 events.
[13:24:38.856] <TB0> INFO: 41600 events read in total (3481ms).
[13:24:38.857] <TB0> INFO: Test took 4351ms.
[13:24:38.860] <TB0> INFO: scanning low vcal = 140
[13:24:39.144] <TB0> INFO: Expecting 41600 events.
[13:24:43.198] <TB0> INFO: 41600 events read in total (3462ms).
[13:24:43.199] <TB0> INFO: Test took 4339ms.
[13:24:43.203] <TB0> INFO: scanning low vcal = 150
[13:24:43.480] <TB0> INFO: Expecting 41600 events.
[13:24:47.528] <TB0> INFO: 41600 events read in total (3456ms).
[13:24:47.529] <TB0> INFO: Test took 4326ms.
[13:24:47.532] <TB0> INFO: scanning low vcal = 160
[13:24:47.813] <TB0> INFO: Expecting 41600 events.
[13:24:51.853] <TB0> INFO: 41600 events read in total (3448ms).
[13:24:51.854] <TB0> INFO: Test took 4322ms.
[13:24:51.857] <TB0> INFO: scanning low vcal = 170
[13:24:52.135] <TB0> INFO: Expecting 41600 events.
[13:24:56.177] <TB0> INFO: 41600 events read in total (3450ms).
[13:24:56.177] <TB0> INFO: Test took 4320ms.
[13:24:56.183] <TB0> INFO: scanning low vcal = 180
[13:24:56.458] <TB0> INFO: Expecting 41600 events.
[13:25:00.489] <TB0> INFO: 41600 events read in total (3439ms).
[13:25:00.489] <TB0> INFO: Test took 4306ms.
[13:25:00.492] <TB0> INFO: scanning low vcal = 190
[13:25:00.770] <TB0> INFO: Expecting 41600 events.
[13:25:04.847] <TB0> INFO: 41600 events read in total (3485ms).
[13:25:04.848] <TB0> INFO: Test took 4355ms.
[13:25:04.851] <TB0> INFO: scanning low vcal = 200
[13:25:05.129] <TB0> INFO: Expecting 41600 events.
[13:25:09.217] <TB0> INFO: 41600 events read in total (3496ms).
[13:25:09.218] <TB0> INFO: Test took 4367ms.
[13:25:09.221] <TB0> INFO: scanning low vcal = 210
[13:25:09.499] <TB0> INFO: Expecting 41600 events.
[13:25:13.597] <TB0> INFO: 41600 events read in total (3506ms).
[13:25:13.597] <TB0> INFO: Test took 4376ms.
[13:25:13.600] <TB0> INFO: scanning low vcal = 220
[13:25:13.878] <TB0> INFO: Expecting 41600 events.
[13:25:17.924] <TB0> INFO: 41600 events read in total (3455ms).
[13:25:17.925] <TB0> INFO: Test took 4325ms.
[13:25:17.928] <TB0> INFO: scanning low vcal = 230
[13:25:18.205] <TB0> INFO: Expecting 41600 events.
[13:25:22.252] <TB0> INFO: 41600 events read in total (3455ms).
[13:25:22.253] <TB0> INFO: Test took 4324ms.
[13:25:22.256] <TB0> INFO: scanning low vcal = 240
[13:25:22.535] <TB0> INFO: Expecting 41600 events.
[13:25:26.547] <TB0> INFO: 41600 events read in total (3420ms).
[13:25:26.547] <TB0> INFO: Test took 4291ms.
[13:25:26.551] <TB0> INFO: scanning low vcal = 250
[13:25:26.827] <TB0> INFO: Expecting 41600 events.
[13:25:30.841] <TB0> INFO: 41600 events read in total (3422ms).
[13:25:30.842] <TB0> INFO: Test took 4291ms.
[13:25:30.846] <TB0> INFO: scanning high vcal = 30 (= 210 in low range)
[13:25:31.121] <TB0> INFO: Expecting 41600 events.
[13:25:35.160] <TB0> INFO: 41600 events read in total (3447ms).
[13:25:35.161] <TB0> INFO: Test took 4315ms.
[13:25:35.164] <TB0> INFO: scanning high vcal = 50 (= 350 in low range)
[13:25:35.441] <TB0> INFO: Expecting 41600 events.
[13:25:39.464] <TB0> INFO: 41600 events read in total (3431ms).
[13:25:39.465] <TB0> INFO: Test took 4300ms.
[13:25:39.471] <TB0> INFO: scanning high vcal = 70 (= 490 in low range)
[13:25:39.746] <TB0> INFO: Expecting 41600 events.
[13:25:43.771] <TB0> INFO: 41600 events read in total (3433ms).
[13:25:43.772] <TB0> INFO: Test took 4301ms.
[13:25:43.776] <TB0> INFO: scanning high vcal = 90 (= 630 in low range)
[13:25:44.053] <TB0> INFO: Expecting 41600 events.
[13:25:48.101] <TB0> INFO: 41600 events read in total (3457ms).
[13:25:48.102] <TB0> INFO: Test took 4326ms.
[13:25:48.105] <TB0> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:25:48.383] <TB0> INFO: Expecting 41600 events.
[13:25:52.390] <TB0> INFO: 41600 events read in total (3415ms).
[13:25:52.391] <TB0> INFO: Test took 4286ms.
[13:25:52.867] <TB0> INFO: PixTestGainPedestal::measure() done
[13:26:26.247] <TB0> INFO: PixTestGainPedestal::fit() done
[13:26:26.247] <TB0> INFO: non-linearity mean: 0.945 0.913 0.974 0.985 0.960 0.985 0.921 0.957 0.983 0.980 0.962 0.974 0.949 0.941 0.952 0.991
[13:26:26.247] <TB0> INFO: non-linearity RMS: 0.122 0.126 0.009 0.004 0.019 0.003 0.085 0.031 0.002 0.005 0.021 0.006 0.061 0.109 0.056 0.182
[13:26:26.247] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[13:26:26.267] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[13:26:26.286] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[13:26:26.305] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[13:26:26.324] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[13:26:26.343] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[13:26:26.361] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[13:26:26.374] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[13:26:26.387] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[13:26:26.401] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[13:26:26.414] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[13:26:26.427] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[13:26:26.440] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[13:26:26.454] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[13:26:26.467] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[13:26:26.480] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[13:26:26.494] <TB0> INFO: PixTestGainPedestal::fullTest() done, duration: 162 seconds
[13:26:26.494] <TB0> INFO: Decoding statistics:
[13:26:26.494] <TB0> INFO: General information:
[13:26:26.494] <TB0> INFO: 16bit words read: 3303026
[13:26:26.494] <TB0> INFO: valid events total: 332800
[13:26:26.494] <TB0> INFO: empty events: 711
[13:26:26.494] <TB0> INFO: valid events with pixels: 332089
[13:26:26.494] <TB0> INFO: valid pixel hits: 653113
[13:26:26.494] <TB0> INFO: Event errors: 0
[13:26:26.494] <TB0> INFO: start marker: 0
[13:26:26.494] <TB0> INFO: stop marker: 0
[13:26:26.494] <TB0> INFO: overflow: 0
[13:26:26.494] <TB0> INFO: invalid 5bit words: 0
[13:26:26.494] <TB0> INFO: invalid XOR eye diagram: 0
[13:26:26.494] <TB0> INFO: frame (failed synchr.): 0
[13:26:26.494] <TB0> INFO: idle data (no TBM trl): 0
[13:26:26.494] <TB0> INFO: no data (only TBM hdr): 0
[13:26:26.494] <TB0> INFO: TBM errors: 0
[13:26:26.494] <TB0> INFO: flawed TBM headers: 0
[13:26:26.494] <TB0> INFO: flawed TBM trailers: 0
[13:26:26.494] <TB0> INFO: event ID mismatches: 0
[13:26:26.494] <TB0> INFO: ROC errors: 0
[13:26:26.494] <TB0> INFO: missing ROC header(s): 0
[13:26:26.494] <TB0> INFO: misplaced readback start: 0
[13:26:26.494] <TB0> INFO: Pixel decoding errors: 0
[13:26:26.494] <TB0> INFO: pixel data incomplete: 0
[13:26:26.494] <TB0> INFO: pixel address: 0
[13:26:26.494] <TB0> INFO: pulse height fill bit: 0
[13:26:26.494] <TB0> INFO: buffer corruption: 0
[13:26:26.512] <TB0> INFO: Decoding statistics:
[13:26:26.512] <TB0> INFO: General information:
[13:26:26.512] <TB0> INFO: 16bit words read: 3432442
[13:26:26.512] <TB0> INFO: valid events total: 353536
[13:26:26.512] <TB0> INFO: empty events: 18947
[13:26:26.512] <TB0> INFO: valid events with pixels: 334589
[13:26:26.512] <TB0> INFO: valid pixel hits: 655613
[13:26:26.512] <TB0> INFO: Event errors: 0
[13:26:26.512] <TB0> INFO: start marker: 0
[13:26:26.512] <TB0> INFO: stop marker: 0
[13:26:26.512] <TB0> INFO: overflow: 0
[13:26:26.512] <TB0> INFO: invalid 5bit words: 0
[13:26:26.512] <TB0> INFO: invalid XOR eye diagram: 0
[13:26:26.512] <TB0> INFO: frame (failed synchr.): 0
[13:26:26.512] <TB0> INFO: idle data (no TBM trl): 0
[13:26:26.512] <TB0> INFO: no data (only TBM hdr): 0
[13:26:26.512] <TB0> INFO: TBM errors: 0
[13:26:26.512] <TB0> INFO: flawed TBM headers: 0
[13:26:26.512] <TB0> INFO: flawed TBM trailers: 0
[13:26:26.512] <TB0> INFO: event ID mismatches: 0
[13:26:26.512] <TB0> INFO: ROC errors: 0
[13:26:26.512] <TB0> INFO: missing ROC header(s): 0
[13:26:26.512] <TB0> INFO: misplaced readback start: 0
[13:26:26.512] <TB0> INFO: Pixel decoding errors: 0
[13:26:26.512] <TB0> INFO: pixel data incomplete: 0
[13:26:26.512] <TB0> INFO: pixel address: 0
[13:26:26.512] <TB0> INFO: pulse height fill bit: 0
[13:26:26.512] <TB0> INFO: buffer corruption: 0
[13:26:26.512] <TB0> INFO: enter test to run
[13:26:26.512] <TB0> INFO: test: trim80 no parameter change
[13:26:26.512] <TB0> INFO: running: trim80
[13:26:26.513] <TB0> INFO: ######################################################################
[13:26:26.513] <TB0> INFO: PixTestTrim80::doTest()
[13:26:26.513] <TB0> INFO: ######################################################################
[13:26:26.515] <TB0> INFO: ----------------------------------------------------------------------
[13:26:26.515] <TB0> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[13:26:26.515] <TB0> INFO: ----------------------------------------------------------------------
[13:26:26.556] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:26:26.556] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:26:26.570] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:26:26.570] <TB0> INFO: run 1 of 1
[13:26:26.805] <TB0> INFO: Expecting 5025280 events.
[13:26:55.926] <TB0> INFO: 681112 events read in total (28529ms).
[13:27:24.084] <TB0> INFO: 1358760 events read in total (56687ms).
[13:27:53.207] <TB0> INFO: 2034128 events read in total (85810ms).
[13:28:21.175] <TB0> INFO: 2709352 events read in total (113778ms).
[13:28:49.096] <TB0> INFO: 3384008 events read in total (141699ms).
[13:29:16.938] <TB0> INFO: 4057208 events read in total (169541ms).
[13:29:44.779] <TB0> INFO: 4729056 events read in total (197382ms).
[13:29:57.028] <TB0> INFO: 5025280 events read in total (209631ms).
[13:29:57.140] <TB0> INFO: Test took 210570ms.
[13:30:20.201] <TB0> INFO: ROC 0 VthrComp = 71
[13:30:20.202] <TB0> INFO: ROC 1 VthrComp = 70
[13:30:20.202] <TB0> INFO: ROC 2 VthrComp = 70
[13:30:20.202] <TB0> INFO: ROC 3 VthrComp = 72
[13:30:20.202] <TB0> INFO: ROC 4 VthrComp = 77
[13:30:20.202] <TB0> INFO: ROC 5 VthrComp = 77
[13:30:20.202] <TB0> INFO: ROC 6 VthrComp = 70
[13:30:20.202] <TB0> INFO: ROC 7 VthrComp = 79
[13:30:20.202] <TB0> INFO: ROC 8 VthrComp = 72
[13:30:20.202] <TB0> INFO: ROC 9 VthrComp = 74
[13:30:20.202] <TB0> INFO: ROC 10 VthrComp = 73
[13:30:20.202] <TB0> INFO: ROC 11 VthrComp = 74
[13:30:20.203] <TB0> INFO: ROC 12 VthrComp = 76
[13:30:20.203] <TB0> INFO: ROC 13 VthrComp = 72
[13:30:20.203] <TB0> INFO: ROC 14 VthrComp = 71
[13:30:20.203] <TB0> INFO: ROC 15 VthrComp = 75
[13:30:20.473] <TB0> INFO: Expecting 41600 events.
[13:30:24.088] <TB0> INFO: 41600 events read in total (3023ms).
[13:30:24.089] <TB0> INFO: Test took 3884ms.
[13:30:24.099] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:30:24.099] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:30:24.110] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:30:24.110] <TB0> INFO: run 1 of 1
[13:30:24.389] <TB0> INFO: Expecting 5025280 events.
[13:30:52.974] <TB0> INFO: 685008 events read in total (27993ms).
[13:31:20.766] <TB0> INFO: 1365496 events read in total (55785ms).
[13:31:49.815] <TB0> INFO: 2044600 events read in total (84834ms).
[13:32:17.477] <TB0> INFO: 2720928 events read in total (112496ms).
[13:32:44.984] <TB0> INFO: 3392040 events read in total (140004ms).
[13:33:12.416] <TB0> INFO: 4063120 events read in total (167435ms).
[13:33:39.930] <TB0> INFO: 4731816 events read in total (194949ms).
[13:33:52.445] <TB0> INFO: 5025280 events read in total (207464ms).
[13:33:52.542] <TB0> INFO: Test took 208431ms.
[13:34:17.098] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 107.24 for pixel 0/14 mean/min/max = 90.3178/73.1685/107.467
[13:34:17.098] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 104.142 for pixel 0/33 mean/min/max = 89.0771/73.9953/104.159
[13:34:17.099] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 104.871 for pixel 7/19 mean/min/max = 89.6315/74.2307/105.032
[13:34:17.100] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 110.031 for pixel 0/7 mean/min/max = 94.0797/77.4945/110.665
[13:34:17.101] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 109.806 for pixel 0/56 mean/min/max = 93.7851/77.527/110.043
[13:34:17.101] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 109.057 for pixel 13/67 mean/min/max = 93.9344/78.5182/109.351
[13:34:17.102] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 108.645 for pixel 8/77 mean/min/max = 91.4758/74.2987/108.653
[13:34:17.103] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 112.351 for pixel 0/11 mean/min/max = 94.7102/76.8975/112.523
[13:34:17.104] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 107.311 for pixel 0/77 mean/min/max = 92.1715/76.9592/107.384
[13:34:17.104] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 109.744 for pixel 0/56 mean/min/max = 93.7399/77.6685/109.811
[13:34:17.105] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 111.321 for pixel 19/75 mean/min/max = 94.3704/77.334/111.407
[13:34:17.105] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 108.77 for pixel 0/69 mean/min/max = 93.0786/77.3267/108.831
[13:34:17.106] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 109.636 for pixel 0/75 mean/min/max = 93.5097/77.2915/109.728
[13:34:17.107] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 107.786 for pixel 0/70 mean/min/max = 91.9313/76.0471/107.816
[13:34:17.107] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 106.262 for pixel 0/24 mean/min/max = 90.5234/74.5755/106.471
[13:34:17.108] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 110.018 for pixel 0/70 mean/min/max = 93.2545/76.2881/110.221
[13:34:17.108] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:34:17.198] <TB0> INFO: Expecting 411648 events.
[13:34:26.688] <TB0> INFO: 411648 events read in total (8898ms).
[13:34:26.697] <TB0> INFO: Expecting 411648 events.
[13:34:36.199] <TB0> INFO: 411648 events read in total (9098ms).
[13:34:36.213] <TB0> INFO: Expecting 411648 events.
[13:34:45.685] <TB0> INFO: 411648 events read in total (9069ms).
[13:34:45.702] <TB0> INFO: Expecting 411648 events.
[13:34:55.099] <TB0> INFO: 411648 events read in total (8993ms).
[13:34:55.120] <TB0> INFO: Expecting 411648 events.
[13:35:04.669] <TB0> INFO: 411648 events read in total (9146ms).
[13:35:04.689] <TB0> INFO: Expecting 411648 events.
[13:35:14.124] <TB0> INFO: 411648 events read in total (9032ms).
[13:35:14.146] <TB0> INFO: Expecting 411648 events.
[13:35:23.684] <TB0> INFO: 411648 events read in total (9135ms).
[13:35:23.713] <TB0> INFO: Expecting 411648 events.
[13:35:33.435] <TB0> INFO: 411648 events read in total (9319ms).
[13:35:33.470] <TB0> INFO: Expecting 411648 events.
[13:35:43.140] <TB0> INFO: 411648 events read in total (9267ms).
[13:35:43.257] <TB0> INFO: Expecting 411648 events.
[13:35:52.473] <TB0> INFO: 411648 events read in total (8813ms).
[13:35:52.518] <TB0> INFO: Expecting 411648 events.
[13:36:01.912] <TB0> INFO: 411648 events read in total (8991ms).
[13:36:01.960] <TB0> INFO: Expecting 411648 events.
[13:36:11.331] <TB0> INFO: 411648 events read in total (8968ms).
[13:36:11.424] <TB0> INFO: Expecting 411648 events.
[13:36:20.958] <TB0> INFO: 411648 events read in total (9131ms).
[13:36:21.045] <TB0> INFO: Expecting 411648 events.
[13:36:30.422] <TB0> INFO: 411648 events read in total (8974ms).
[13:36:30.516] <TB0> INFO: Expecting 411648 events.
[13:36:39.908] <TB0> INFO: 411648 events read in total (8989ms).
[13:36:39.975] <TB0> INFO: Expecting 411648 events.
[13:36:49.453] <TB0> INFO: 411648 events read in total (9075ms).
[13:36:49.518] <TB0> INFO: Test took 152410ms.
[13:36:51.143] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:36:51.156] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:36:51.156] <TB0> INFO: run 1 of 1
[13:36:51.393] <TB0> INFO: Expecting 5025280 events.
[13:37:19.949] <TB0> INFO: 671272 events read in total (27964ms).
[13:37:47.404] <TB0> INFO: 1339208 events read in total (55419ms).
[13:38:14.798] <TB0> INFO: 2006416 events read in total (82813ms).
[13:38:42.278] <TB0> INFO: 2671664 events read in total (110293ms).
[13:39:09.414] <TB0> INFO: 3332616 events read in total (137429ms).
[13:39:36.601] <TB0> INFO: 3991640 events read in total (164616ms).
[13:40:04.277] <TB0> INFO: 4648080 events read in total (192292ms).
[13:40:20.052] <TB0> INFO: 5025280 events read in total (208067ms).
[13:40:20.130] <TB0> INFO: Test took 208975ms.
[13:40:43.517] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 29.880185 .. 107.094787
[13:40:43.769] <TB0> INFO: Expecting 208000 events.
[13:40:53.496] <TB0> INFO: 208000 events read in total (9135ms).
[13:40:53.497] <TB0> INFO: Test took 9978ms.
[13:40:53.548] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 19 .. 117 (-1/-1) hits flags = 528 (plus default)
[13:40:53.561] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:40:53.561] <TB0> INFO: run 1 of 1
[13:40:53.842] <TB0> INFO: Expecting 3294720 events.
[13:41:22.933] <TB0> INFO: 713504 events read in total (28499ms).
[13:41:51.779] <TB0> INFO: 1425632 events read in total (57345ms).
[13:42:21.433] <TB0> INFO: 2133912 events read in total (86999ms).
[13:42:49.934] <TB0> INFO: 2839312 events read in total (115500ms).
[13:43:07.915] <TB0> INFO: 3294720 events read in total (133481ms).
[13:43:07.966] <TB0> INFO: Test took 134404ms.
[13:43:25.608] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 38.892735 .. 97.458420
[13:43:25.893] <TB0> INFO: Expecting 208000 events.
[13:43:35.711] <TB0> INFO: 208000 events read in total (9227ms).
[13:43:35.712] <TB0> INFO: Test took 10103ms.
[13:43:35.765] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 28 .. 107 (-1/-1) hits flags = 528 (plus default)
[13:43:35.778] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:43:35.778] <TB0> INFO: run 1 of 1
[13:43:36.056] <TB0> INFO: Expecting 2662400 events.
[13:44:05.696] <TB0> INFO: 723912 events read in total (29048ms).
[13:44:36.277] <TB0> INFO: 1447848 events read in total (59629ms).
[13:45:05.786] <TB0> INFO: 2170704 events read in total (89138ms).
[13:45:25.387] <TB0> INFO: 2662400 events read in total (108739ms).
[13:45:25.430] <TB0> INFO: Test took 109652ms.
[13:45:43.698] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 44.110369 .. 93.502954
[13:45:43.944] <TB0> INFO: Expecting 208000 events.
[13:45:54.223] <TB0> INFO: 208000 events read in total (9687ms).
[13:45:54.224] <TB0> INFO: Test took 10525ms.
[13:45:54.272] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 34 .. 103 (-1/-1) hits flags = 528 (plus default)
[13:45:54.285] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:45:54.285] <TB0> INFO: run 1 of 1
[13:45:54.568] <TB0> INFO: Expecting 2329600 events.
[13:46:24.718] <TB0> INFO: 727360 events read in total (29559ms).
[13:46:53.656] <TB0> INFO: 1455152 events read in total (58498ms).
[13:47:22.800] <TB0> INFO: 2182144 events read in total (87641ms).
[13:47:29.227] <TB0> INFO: 2329600 events read in total (94068ms).
[13:47:29.263] <TB0> INFO: Test took 94978ms.
[13:47:48.216] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 46.221588 .. 92.923721
[13:47:48.480] <TB0> INFO: Expecting 208000 events.
[13:47:57.936] <TB0> INFO: 208000 events read in total (8864ms).
[13:47:57.937] <TB0> INFO: Test took 9719ms.
[13:47:58.005] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 36 .. 102 (-1/-1) hits flags = 528 (plus default)
[13:47:58.019] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:47:58.019] <TB0> INFO: run 1 of 1
[13:47:58.297] <TB0> INFO: Expecting 2229760 events.
[13:48:27.332] <TB0> INFO: 728296 events read in total (28443ms).
[13:48:56.101] <TB0> INFO: 1456304 events read in total (57213ms).
[13:49:24.523] <TB0> INFO: 2183752 events read in total (85634ms).
[13:49:26.739] <TB0> INFO: 2229760 events read in total (87850ms).
[13:49:26.768] <TB0> INFO: Test took 88750ms.
[13:49:44.158] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[13:49:44.158] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[13:49:44.171] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:49:44.171] <TB0> INFO: run 1 of 1
[13:49:44.450] <TB0> INFO: Expecting 1364480 events.
[13:50:13.067] <TB0> INFO: 669048 events read in total (28026ms).
[13:50:40.732] <TB0> INFO: 1337744 events read in total (55691ms).
[13:50:42.329] <TB0> INFO: 1364480 events read in total (57288ms).
[13:50:42.355] <TB0> INFO: Test took 58184ms.
[13:51:00.930] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C0.dat
[13:51:00.931] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C1.dat
[13:51:00.931] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C2.dat
[13:51:00.931] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C3.dat
[13:51:00.931] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C4.dat
[13:51:00.931] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C5.dat
[13:51:00.932] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C6.dat
[13:51:00.932] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C7.dat
[13:51:00.932] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C8.dat
[13:51:00.932] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C9.dat
[13:51:00.932] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C10.dat
[13:51:00.932] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C11.dat
[13:51:00.932] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C12.dat
[13:51:00.933] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C13.dat
[13:51:00.933] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C14.dat
[13:51:00.933] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//dacParameters80_C15.dat
[13:51:00.933] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C0.dat
[13:51:00.943] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C1.dat
[13:51:00.948] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C2.dat
[13:51:00.952] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C3.dat
[13:51:00.957] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C4.dat
[13:51:00.962] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C5.dat
[13:51:00.966] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C6.dat
[13:51:00.971] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C7.dat
[13:51:00.976] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C8.dat
[13:51:00.980] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C9.dat
[13:51:00.985] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C10.dat
[13:51:00.990] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C11.dat
[13:51:00.994] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C12.dat
[13:51:00.999] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C13.dat
[13:51:01.004] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C14.dat
[13:51:01.008] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1100_FullQualification_2016-11-02_09h36m_1478075793//003_FulltestTrim80_p17//trimParameters80_C15.dat
[13:51:01.013] <TB0> INFO: PixTestTrim80::trimTest() done
[13:51:01.013] <TB0> INFO: vtrim: 91 80 81 103 103 108 92 118 93 100 118 102 104 98 91 97
[13:51:01.013] <TB0> INFO: vthrcomp: 71 70 70 72 77 77 70 79 72 74 73 74 76 72 71 75
[13:51:01.013] <TB0> INFO: vcal mean: 79.98 79.97 79.98 80.01 79.97 79.98 79.96 79.95 79.97 80.01 79.97 79.95 79.98 79.95 80.00 79.95
[13:51:01.013] <TB0> INFO: vcal RMS: 0.75 0.73 0.75 0.71 0.70 0.73 0.77 0.77 0.72 0.72 0.77 0.78 0.70 0.74 0.71 0.74
[13:51:01.013] <TB0> INFO: bits mean: 10.47 10.19 10.28 9.17 9.12 9.19 10.17 9.44 9.75 8.54 9.82 9.30 9.14 9.61 9.84 9.31
[13:51:01.013] <TB0> INFO: bits RMS: 2.45 2.58 2.46 2.36 2.40 2.27 2.42 2.33 2.23 2.53 2.10 2.33 2.41 2.41 2.66 2.46
[13:51:01.020] <TB0> INFO: ----------------------------------------------------------------------
[13:51:01.020] <TB0> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:51:01.020] <TB0> INFO: ----------------------------------------------------------------------
[13:51:01.023] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:51:01.035] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:51:01.036] <TB0> INFO: run 1 of 1
[13:51:01.278] <TB0> INFO: Expecting 4160000 events.
[13:51:34.617] <TB0> INFO: 764240 events read in total (32747ms).
[13:52:06.878] <TB0> INFO: 1521880 events read in total (65008ms).
[13:52:39.116] <TB0> INFO: 2274465 events read in total (97246ms).
[13:53:11.397] <TB0> INFO: 3022315 events read in total (129527ms).
[13:53:43.706] <TB0> INFO: 3766630 events read in total (161836ms).
[13:54:00.418] <TB0> INFO: 4160000 events read in total (178548ms).
[13:54:00.542] <TB0> INFO: Test took 179506ms.
[13:54:25.151] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[13:54:25.163] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:54:25.164] <TB0> INFO: run 1 of 1
[13:54:25.400] <TB0> INFO: Expecting 4243200 events.
[13:54:58.289] <TB0> INFO: 733250 events read in total (32297ms).
[13:55:30.247] <TB0> INFO: 1461120 events read in total (64255ms).
[13:56:01.915] <TB0> INFO: 2185765 events read in total (95923ms).
[13:56:33.522] <TB0> INFO: 2904885 events read in total (127531ms).
[13:57:04.804] <TB0> INFO: 3621020 events read in total (158812ms).
[13:57:31.641] <TB0> INFO: 4243200 events read in total (185649ms).
[13:57:31.763] <TB0> INFO: Test took 186600ms.
[13:57:57.182] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 194 (-1/-1) hits flags = 528 (plus default)
[13:57:57.196] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:57:57.196] <TB0> INFO: run 1 of 1
[13:57:57.434] <TB0> INFO: Expecting 4056000 events.
[13:58:29.784] <TB0> INFO: 745965 events read in total (31758ms).
[13:59:01.488] <TB0> INFO: 1486810 events read in total (63462ms).
[13:59:32.995] <TB0> INFO: 2223195 events read in total (94969ms).
[14:00:04.561] <TB0> INFO: 2954110 events read in total (126535ms).
[14:00:36.491] <TB0> INFO: 3681335 events read in total (158465ms).
[14:00:53.466] <TB0> INFO: 4056000 events read in total (175440ms).
[14:00:53.562] <TB0> INFO: Test took 176366ms.
[14:01:17.948] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 190 (-1/-1) hits flags = 528 (plus default)
[14:01:17.962] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:01:17.962] <TB0> INFO: run 1 of 1
[14:01:18.227] <TB0> INFO: Expecting 3972800 events.
[14:01:50.586] <TB0> INFO: 752270 events read in total (31767ms).
[14:02:23.319] <TB0> INFO: 1498975 events read in total (64500ms).
[14:02:55.752] <TB0> INFO: 2241110 events read in total (96933ms).
[14:03:27.907] <TB0> INFO: 2977080 events read in total (129088ms).
[14:03:59.944] <TB0> INFO: 3710170 events read in total (161125ms).
[14:04:12.015] <TB0> INFO: 3972800 events read in total (173196ms).
[14:04:12.092] <TB0> INFO: Test took 174129ms.
[14:04:38.915] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 194 (-1/-1) hits flags = 528 (plus default)
[14:04:38.928] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:04:38.928] <TB0> INFO: run 1 of 1
[14:04:39.165] <TB0> INFO: Expecting 4056000 events.
[14:05:11.913] <TB0> INFO: 746060 events read in total (32156ms).
[14:05:43.327] <TB0> INFO: 1486985 events read in total (63570ms).
[14:06:15.337] <TB0> INFO: 2223155 events read in total (95580ms).
[14:06:46.780] <TB0> INFO: 2954490 events read in total (127023ms).
[14:07:18.507] <TB0> INFO: 3682240 events read in total (158750ms).
[14:07:34.740] <TB0> INFO: 4056000 events read in total (174983ms).
[14:07:34.814] <TB0> INFO: Test took 175886ms.
[14:08:06.777] <TB0> INFO: PixTestTrim80::trimBitTest() done
[14:08:06.778] <TB0> INFO: PixTestTrim80::doTest() done, duration: 2500 seconds
[14:08:07.627] <TB0> INFO: enter test to run
[14:08:07.627] <TB0> INFO: test: exit no parameter change
[14:08:07.848] <TB0> QUIET: Connection to board 71 closed.
[14:08:07.849] <TB0> INFO: pXar: this is the end, my friend