[11:16:19.570] <TB2> INFO: *** Welcome to pxar ***
[11:16:19.570] <TB2> INFO: *** Today: 2016/10/31
[11:16:19.577] <TB2> INFO: *** Version: c8ba-dirty
[11:16:19.577] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C15.dat
[11:16:19.577] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//tbmParameters_C1b.dat
[11:16:19.577] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//defaultMaskFile.dat
[11:16:19.577] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters_C15.dat
[11:16:19.638] <TB2> INFO: clk: 4
[11:16:19.638] <TB2> INFO: ctr: 4
[11:16:19.638] <TB2> INFO: sda: 19
[11:16:19.638] <TB2> INFO: tin: 9
[11:16:19.638] <TB2> INFO: level: 15
[11:16:19.638] <TB2> INFO: triggerdelay: 0
[11:16:19.638] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[11:16:19.638] <TB2> INFO: Log level: INFO
[11:16:19.646] <TB2> INFO: Found DTB DTB_WWXUD2
[11:16:19.653] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[11:16:19.655] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[11:16:19.657] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[11:16:21.167] <TB2> INFO: DUT info:
[11:16:21.167] <TB2> INFO: The DUT currently contains the following objects:
[11:16:21.167] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[11:16:21.167] <TB2> INFO: TBM Core alpha (0): 7 registers set
[11:16:21.167] <TB2> INFO: TBM Core beta (1): 7 registers set
[11:16:21.167] <TB2> INFO: TBM Core alpha (2): 7 registers set
[11:16:21.167] <TB2> INFO: TBM Core beta (3): 7 registers set
[11:16:21.167] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:16:21.167] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.167] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.167] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.167] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.167] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.167] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.168] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.168] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.168] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.168] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.168] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.168] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.168] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.168] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.168] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.168] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:21.569] <TB2> INFO: enter 'restricted' command line mode
[11:16:21.569] <TB2> INFO: enter test to run
[11:16:21.569] <TB2> INFO: test: pretest no parameter change
[11:16:21.569] <TB2> INFO: running: pretest
[11:16:21.576] <TB2> INFO: ######################################################################
[11:16:21.576] <TB2> INFO: PixTestPretest::doTest()
[11:16:21.576] <TB2> INFO: ######################################################################
[11:16:21.577] <TB2> INFO: ----------------------------------------------------------------------
[11:16:21.577] <TB2> INFO: PixTestPretest::programROC()
[11:16:21.577] <TB2> INFO: ----------------------------------------------------------------------
[11:16:39.591] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:16:39.591] <TB2> INFO: IA differences per ROC: 18.5 19.3 20.9 19.3 16.9 18.5 18.5 16.9 19.3 17.7 20.1 20.1 16.1 20.1 18.5 18.5
[11:16:39.657] <TB2> INFO: ----------------------------------------------------------------------
[11:16:39.657] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:16:39.657] <TB2> INFO: ----------------------------------------------------------------------
[11:17:00.957] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 389.1 mA = 24.3188 mA/ROC
[11:17:00.957] <TB2> INFO: i(loss) [mA/ROC]: 19.3 19.3 19.3 19.3 20.1 18.5 18.5 19.3 20.1 20.1 19.3 19.3 19.3 19.3 20.1 18.5
[11:17:00.987] <TB2> INFO: ----------------------------------------------------------------------
[11:17:00.987] <TB2> INFO: PixTestPretest::findTiming()
[11:17:00.987] <TB2> INFO: ----------------------------------------------------------------------
[11:17:00.987] <TB2> INFO: PixTestCmd::init()

[11:17:33.235] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:17:33.236] <TB2> INFO: (success/tries = 100/100), width = 4
[11:17:34.743] <TB2> INFO: ----------------------------------------------------------------------
[11:17:34.743] <TB2> INFO: PixTestPretest::findWorkingPixel()
[11:17:34.743] <TB2> INFO: ----------------------------------------------------------------------
[11:17:34.838] <TB2> INFO: Expecting 231680 events.
[11:17:44.729] <TB2> INFO: 231680 events read in total (9299ms).
[11:17:44.739] <TB2> INFO: Test took 9991ms.
[11:17:44.987] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:17:45.021] <TB2> INFO: ----------------------------------------------------------------------
[11:17:45.021] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[11:17:45.021] <TB2> INFO: ----------------------------------------------------------------------
[11:17:45.117] <TB2> INFO: Expecting 231680 events.
[11:17:54.971] <TB2> INFO: 231680 events read in total (9263ms).
[11:17:54.979] <TB2> INFO: Test took 9953ms.
[11:17:55.236] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[11:17:55.236] <TB2> INFO: CalDel: 84 111 120 123 121 111 95 115 111 128 82 124 103 94 115 108
[11:17:55.236] <TB2> INFO: VthrComp: 52 51 52 51 51 51 51 51 51 51 51 51 52 51 51 51
[11:17:55.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C0.dat
[11:17:55.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C1.dat
[11:17:55.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C2.dat
[11:17:55.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C3.dat
[11:17:55.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C4.dat
[11:17:55.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C5.dat
[11:17:55.240] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C6.dat
[11:17:55.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C7.dat
[11:17:55.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C8.dat
[11:17:55.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C9.dat
[11:17:55.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C10.dat
[11:17:55.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C11.dat
[11:17:55.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C12.dat
[11:17:55.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C13.dat
[11:17:55.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C14.dat
[11:17:55.241] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C15.dat
[11:17:55.241] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//tbmParameters_C0a.dat
[11:17:55.242] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//tbmParameters_C0b.dat
[11:17:55.242] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//tbmParameters_C1a.dat
[11:17:55.242] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//tbmParameters_C1b.dat
[11:17:55.242] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[11:17:55.294] <TB2> INFO: enter test to run
[11:17:55.294] <TB2> INFO: test: FullTest no parameter change
[11:17:55.294] <TB2> INFO: running: fulltest
[11:17:55.294] <TB2> INFO: ######################################################################
[11:17:55.294] <TB2> INFO: PixTestFullTest::doTest()
[11:17:55.294] <TB2> INFO: ######################################################################
[11:17:55.297] <TB2> INFO: ######################################################################
[11:17:55.297] <TB2> INFO: PixTestAlive::doTest()
[11:17:55.297] <TB2> INFO: ######################################################################
[11:17:55.298] <TB2> INFO: ----------------------------------------------------------------------
[11:17:55.298] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:17:55.298] <TB2> INFO: ----------------------------------------------------------------------
[11:17:55.536] <TB2> INFO: Expecting 41600 events.
[11:17:59.092] <TB2> INFO: 41600 events read in total (2964ms).
[11:17:59.092] <TB2> INFO: Test took 3792ms.
[11:17:59.320] <TB2> INFO: PixTestAlive::aliveTest() done
[11:17:59.320] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:17:59.321] <TB2> INFO: ----------------------------------------------------------------------
[11:17:59.321] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:17:59.321] <TB2> INFO: ----------------------------------------------------------------------
[11:17:59.560] <TB2> INFO: Expecting 41600 events.
[11:18:02.524] <TB2> INFO: 41600 events read in total (2372ms).
[11:18:02.524] <TB2> INFO: Test took 3201ms.
[11:18:02.525] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:18:02.764] <TB2> INFO: PixTestAlive::maskTest() done
[11:18:02.765] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:18:02.766] <TB2> INFO: ----------------------------------------------------------------------
[11:18:02.766] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:18:02.766] <TB2> INFO: ----------------------------------------------------------------------
[11:18:03.010] <TB2> INFO: Expecting 41600 events.
[11:18:06.640] <TB2> INFO: 41600 events read in total (3038ms).
[11:18:06.641] <TB2> INFO: Test took 3872ms.
[11:18:06.872] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[11:18:06.872] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:18:06.872] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:18:06.872] <TB2> INFO: Decoding statistics:
[11:18:06.872] <TB2> INFO: General information:
[11:18:06.872] <TB2> INFO: 16bit words read: 0
[11:18:06.872] <TB2> INFO: valid events total: 0
[11:18:06.872] <TB2> INFO: empty events: 0
[11:18:06.872] <TB2> INFO: valid events with pixels: 0
[11:18:06.872] <TB2> INFO: valid pixel hits: 0
[11:18:06.872] <TB2> INFO: Event errors: 0
[11:18:06.872] <TB2> INFO: start marker: 0
[11:18:06.873] <TB2> INFO: stop marker: 0
[11:18:06.873] <TB2> INFO: overflow: 0
[11:18:06.873] <TB2> INFO: invalid 5bit words: 0
[11:18:06.873] <TB2> INFO: invalid XOR eye diagram: 0
[11:18:06.873] <TB2> INFO: frame (failed synchr.): 0
[11:18:06.873] <TB2> INFO: idle data (no TBM trl): 0
[11:18:06.873] <TB2> INFO: no data (only TBM hdr): 0
[11:18:06.873] <TB2> INFO: TBM errors: 0
[11:18:06.873] <TB2> INFO: flawed TBM headers: 0
[11:18:06.873] <TB2> INFO: flawed TBM trailers: 0
[11:18:06.873] <TB2> INFO: event ID mismatches: 0
[11:18:06.873] <TB2> INFO: ROC errors: 0
[11:18:06.873] <TB2> INFO: missing ROC header(s): 0
[11:18:06.873] <TB2> INFO: misplaced readback start: 0
[11:18:06.873] <TB2> INFO: Pixel decoding errors: 0
[11:18:06.873] <TB2> INFO: pixel data incomplete: 0
[11:18:06.873] <TB2> INFO: pixel address: 0
[11:18:06.873] <TB2> INFO: pulse height fill bit: 0
[11:18:06.873] <TB2> INFO: buffer corruption: 0
[11:18:06.878] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C15.dat
[11:18:06.879] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[11:18:06.879] <TB2> INFO: ######################################################################
[11:18:06.879] <TB2> INFO: PixTestReadback::doTest()
[11:18:06.879] <TB2> INFO: ######################################################################
[11:18:06.879] <TB2> INFO: ----------------------------------------------------------------------
[11:18:06.879] <TB2> INFO: PixTestReadback::CalibrateVd()
[11:18:06.879] <TB2> INFO: ----------------------------------------------------------------------
[11:18:16.850] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C0.dat
[11:18:16.850] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C1.dat
[11:18:16.850] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C2.dat
[11:18:16.850] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C3.dat
[11:18:16.850] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C4.dat
[11:18:16.850] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C5.dat
[11:18:16.850] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C6.dat
[11:18:16.850] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C7.dat
[11:18:16.851] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C8.dat
[11:18:16.851] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C9.dat
[11:18:16.851] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C10.dat
[11:18:16.851] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C11.dat
[11:18:16.851] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C12.dat
[11:18:16.851] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C13.dat
[11:18:16.851] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C14.dat
[11:18:16.851] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C15.dat
[11:18:16.882] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:18:16.882] <TB2> INFO: ----------------------------------------------------------------------
[11:18:16.882] <TB2> INFO: PixTestReadback::CalibrateVa()
[11:18:16.882] <TB2> INFO: ----------------------------------------------------------------------
[11:18:26.824] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C0.dat
[11:18:26.824] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C1.dat
[11:18:26.824] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C2.dat
[11:18:26.824] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C3.dat
[11:18:26.824] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C4.dat
[11:18:26.824] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C5.dat
[11:18:26.824] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C6.dat
[11:18:26.824] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C7.dat
[11:18:26.825] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C8.dat
[11:18:26.825] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C9.dat
[11:18:26.825] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C10.dat
[11:18:26.825] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C11.dat
[11:18:26.825] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C12.dat
[11:18:26.825] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C13.dat
[11:18:26.825] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C14.dat
[11:18:26.825] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C15.dat
[11:18:26.856] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:18:26.856] <TB2> INFO: ----------------------------------------------------------------------
[11:18:26.856] <TB2> INFO: PixTestReadback::readbackVbg()
[11:18:26.856] <TB2> INFO: ----------------------------------------------------------------------
[11:18:34.526] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:18:34.526] <TB2> INFO: ----------------------------------------------------------------------
[11:18:34.526] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[11:18:34.526] <TB2> INFO: ----------------------------------------------------------------------
[11:18:34.526] <TB2> INFO: Vbg will be calibrated using Vd calibration
[11:18:34.526] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 155calibrated Vbg = 1.17974 :::*/*/*/*/
[11:18:34.526] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 155.1calibrated Vbg = 1.1807 :::*/*/*/*/
[11:18:34.526] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 145calibrated Vbg = 1.17121 :::*/*/*/*/
[11:18:34.526] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 150.4calibrated Vbg = 1.17387 :::*/*/*/*/
[11:18:34.526] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 152.2calibrated Vbg = 1.17775 :::*/*/*/*/
[11:18:34.526] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 153.7calibrated Vbg = 1.18356 :::*/*/*/*/
[11:18:34.526] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 149.9calibrated Vbg = 1.19131 :::*/*/*/*/
[11:18:34.527] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 158.8calibrated Vbg = 1.18426 :::*/*/*/*/
[11:18:34.527] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 151calibrated Vbg = 1.18379 :::*/*/*/*/
[11:18:34.527] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 163calibrated Vbg = 1.17416 :::*/*/*/*/
[11:18:34.527] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 152.5calibrated Vbg = 1.16629 :::*/*/*/*/
[11:18:34.527] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 161.6calibrated Vbg = 1.16645 :::*/*/*/*/
[11:18:34.527] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 151.1calibrated Vbg = 1.16798 :::*/*/*/*/
[11:18:34.527] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 150.8calibrated Vbg = 1.17559 :::*/*/*/*/
[11:18:34.527] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 149.5calibrated Vbg = 1.17647 :::*/*/*/*/
[11:18:34.527] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 153.4calibrated Vbg = 1.18136 :::*/*/*/*/
[11:18:34.529] <TB2> INFO: ----------------------------------------------------------------------
[11:18:34.529] <TB2> INFO: PixTestReadback::CalibrateIa()
[11:18:34.529] <TB2> INFO: ----------------------------------------------------------------------
[11:21:15.353] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C0.dat
[11:21:15.354] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C1.dat
[11:21:15.354] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C2.dat
[11:21:15.354] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C3.dat
[11:21:15.354] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C4.dat
[11:21:15.354] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C5.dat
[11:21:15.354] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C6.dat
[11:21:15.354] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C7.dat
[11:21:15.354] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C8.dat
[11:21:15.354] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C9.dat
[11:21:15.354] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C10.dat
[11:21:15.354] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C11.dat
[11:21:15.354] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C12.dat
[11:21:15.355] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C13.dat
[11:21:15.355] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C14.dat
[11:21:15.355] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C15.dat
[11:21:15.381] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:21:15.382] <TB2> INFO: PixTestReadback::doTest() done
[11:21:15.383] <TB2> INFO: Decoding statistics:
[11:21:15.383] <TB2> INFO: General information:
[11:21:15.383] <TB2> INFO: 16bit words read: 1536
[11:21:15.383] <TB2> INFO: valid events total: 256
[11:21:15.383] <TB2> INFO: empty events: 256
[11:21:15.383] <TB2> INFO: valid events with pixels: 0
[11:21:15.383] <TB2> INFO: valid pixel hits: 0
[11:21:15.383] <TB2> INFO: Event errors: 0
[11:21:15.383] <TB2> INFO: start marker: 0
[11:21:15.383] <TB2> INFO: stop marker: 0
[11:21:15.383] <TB2> INFO: overflow: 0
[11:21:15.383] <TB2> INFO: invalid 5bit words: 0
[11:21:15.383] <TB2> INFO: invalid XOR eye diagram: 0
[11:21:15.383] <TB2> INFO: frame (failed synchr.): 0
[11:21:15.383] <TB2> INFO: idle data (no TBM trl): 0
[11:21:15.383] <TB2> INFO: no data (only TBM hdr): 0
[11:21:15.383] <TB2> INFO: TBM errors: 0
[11:21:15.383] <TB2> INFO: flawed TBM headers: 0
[11:21:15.383] <TB2> INFO: flawed TBM trailers: 0
[11:21:15.383] <TB2> INFO: event ID mismatches: 0
[11:21:15.383] <TB2> INFO: ROC errors: 0
[11:21:15.383] <TB2> INFO: missing ROC header(s): 0
[11:21:15.383] <TB2> INFO: misplaced readback start: 0
[11:21:15.383] <TB2> INFO: Pixel decoding errors: 0
[11:21:15.383] <TB2> INFO: pixel data incomplete: 0
[11:21:15.383] <TB2> INFO: pixel address: 0
[11:21:15.383] <TB2> INFO: pulse height fill bit: 0
[11:21:15.383] <TB2> INFO: buffer corruption: 0
[11:21:15.450] <TB2> INFO: ######################################################################
[11:21:15.450] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:21:15.450] <TB2> INFO: ######################################################################
[11:21:15.453] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:21:15.479] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:21:15.479] <TB2> INFO: run 1 of 1
[11:21:15.737] <TB2> INFO: Expecting 3120000 events.
[11:21:46.198] <TB2> INFO: 647775 events read in total (29869ms).











[11:22:15.762] <TB2> INFO: 1291195 events read in total (59433ms).











[11:22:45.497] <TB2> INFO: 1933650 events read in total (89168ms).











[11:23:15.114] <TB2> INFO: 2575900 events read in total (118785ms).











[11:23:41.427] <TB2> INFO: 3120000 events read in total (145098ms).
[11:23:41.523] <TB2> INFO: Test took 146045ms.
[11:24:08.006] <TB2> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 172 seconds
[11:24:08.006] <TB2> INFO: number of dead bumps (per ROC): 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:24:08.006] <TB2> INFO: separation cut (per ROC): 104 100 100 93 89 82 99 95 102 99 115 94 109 101 103 96
[11:24:08.006] <TB2> INFO: Decoding statistics:
[11:24:08.006] <TB2> INFO: General information:
[11:24:08.006] <TB2> INFO: 16bit words read: 0
[11:24:08.006] <TB2> INFO: valid events total: 0
[11:24:08.006] <TB2> INFO: empty events: 0
[11:24:08.006] <TB2> INFO: valid events with pixels: 0
[11:24:08.006] <TB2> INFO: valid pixel hits: 0
[11:24:08.006] <TB2> INFO: Event errors: 0
[11:24:08.006] <TB2> INFO: start marker: 0
[11:24:08.006] <TB2> INFO: stop marker: 0
[11:24:08.006] <TB2> INFO: overflow: 0
[11:24:08.006] <TB2> INFO: invalid 5bit words: 0
[11:24:08.006] <TB2> INFO: invalid XOR eye diagram: 0
[11:24:08.006] <TB2> INFO: frame (failed synchr.): 0
[11:24:08.006] <TB2> INFO: idle data (no TBM trl): 0
[11:24:08.006] <TB2> INFO: no data (only TBM hdr): 0
[11:24:08.006] <TB2> INFO: TBM errors: 0
[11:24:08.006] <TB2> INFO: flawed TBM headers: 0
[11:24:08.006] <TB2> INFO: flawed TBM trailers: 0
[11:24:08.006] <TB2> INFO: event ID mismatches: 0
[11:24:08.006] <TB2> INFO: ROC errors: 0
[11:24:08.006] <TB2> INFO: missing ROC header(s): 0
[11:24:08.006] <TB2> INFO: misplaced readback start: 0
[11:24:08.006] <TB2> INFO: Pixel decoding errors: 0
[11:24:08.006] <TB2> INFO: pixel data incomplete: 0
[11:24:08.006] <TB2> INFO: pixel address: 0
[11:24:08.006] <TB2> INFO: pulse height fill bit: 0
[11:24:08.006] <TB2> INFO: buffer corruption: 0
[11:24:08.042] <TB2> INFO: ######################################################################
[11:24:08.042] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:24:08.042] <TB2> INFO: ######################################################################
[11:24:08.043] <TB2> INFO: ----------------------------------------------------------------------
[11:24:08.043] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:24:08.043] <TB2> INFO: ----------------------------------------------------------------------
[11:24:08.043] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[11:24:08.056] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[11:24:08.057] <TB2> INFO: run 1 of 1
[11:24:08.295] <TB2> INFO: Expecting 36608000 events.
[11:24:31.926] <TB2> INFO: 664750 events read in total (23040ms).
[11:24:54.744] <TB2> INFO: 1316400 events read in total (45858ms).
[11:25:17.162] <TB2> INFO: 1967100 events read in total (68276ms).
[11:25:39.943] <TB2> INFO: 2617200 events read in total (91058ms).
[11:26:02.797] <TB2> INFO: 3268100 events read in total (113911ms).
[11:26:25.426] <TB2> INFO: 3916650 events read in total (136540ms).
[11:26:48.110] <TB2> INFO: 4565800 events read in total (159224ms).
[11:27:10.506] <TB2> INFO: 5215650 events read in total (181620ms).
[11:27:33.270] <TB2> INFO: 5865250 events read in total (204384ms).
[11:27:55.723] <TB2> INFO: 6515600 events read in total (226837ms).
[11:28:18.105] <TB2> INFO: 7162700 events read in total (249219ms).
[11:28:40.967] <TB2> INFO: 7811950 events read in total (272081ms).
[11:29:03.670] <TB2> INFO: 8460150 events read in total (294784ms).
[11:29:26.282] <TB2> INFO: 9109100 events read in total (317396ms).
[11:29:48.889] <TB2> INFO: 9758650 events read in total (340003ms).
[11:30:11.867] <TB2> INFO: 10408600 events read in total (362981ms).
[11:30:34.816] <TB2> INFO: 11058650 events read in total (385930ms).
[11:30:57.463] <TB2> INFO: 11708100 events read in total (408577ms).
[11:31:20.571] <TB2> INFO: 12355000 events read in total (431685ms).
[11:31:43.303] <TB2> INFO: 13003750 events read in total (454417ms).
[11:32:05.980] <TB2> INFO: 13651400 events read in total (477094ms).
[11:32:28.457] <TB2> INFO: 14298850 events read in total (499571ms).
[11:32:50.993] <TB2> INFO: 14944850 events read in total (522107ms).
[11:33:13.831] <TB2> INFO: 15590200 events read in total (544945ms).
[11:33:36.489] <TB2> INFO: 16234850 events read in total (567603ms).
[11:33:59.220] <TB2> INFO: 16880350 events read in total (590334ms).
[11:34:21.869] <TB2> INFO: 17527100 events read in total (612983ms).
[11:34:44.885] <TB2> INFO: 18172650 events read in total (635999ms).
[11:35:07.456] <TB2> INFO: 18818900 events read in total (658570ms).
[11:35:29.879] <TB2> INFO: 19462750 events read in total (680993ms).
[11:35:52.533] <TB2> INFO: 20106250 events read in total (703647ms).
[11:36:15.433] <TB2> INFO: 20749900 events read in total (726547ms).
[11:36:38.141] <TB2> INFO: 21392600 events read in total (749255ms).
[11:37:00.664] <TB2> INFO: 22036800 events read in total (771778ms).
[11:37:23.127] <TB2> INFO: 22679150 events read in total (794241ms).
[11:37:45.550] <TB2> INFO: 23320950 events read in total (816664ms).
[11:38:08.251] <TB2> INFO: 23961900 events read in total (839366ms).
[11:38:30.868] <TB2> INFO: 24604750 events read in total (861982ms).
[11:38:53.181] <TB2> INFO: 25246800 events read in total (884295ms).
[11:39:15.660] <TB2> INFO: 25890200 events read in total (906774ms).
[11:39:37.989] <TB2> INFO: 26534850 events read in total (929103ms).
[11:40:00.616] <TB2> INFO: 27178400 events read in total (951730ms).
[11:40:23.290] <TB2> INFO: 27821650 events read in total (974404ms).
[11:40:46.003] <TB2> INFO: 28465050 events read in total (997117ms).
[11:41:08.684] <TB2> INFO: 29107900 events read in total (1019798ms).
[11:41:31.220] <TB2> INFO: 29748850 events read in total (1042334ms).
[11:41:53.707] <TB2> INFO: 30388500 events read in total (1064821ms).
[11:42:16.086] <TB2> INFO: 31026600 events read in total (1087200ms).
[11:42:38.622] <TB2> INFO: 31667000 events read in total (1109736ms).
[11:43:01.184] <TB2> INFO: 32306450 events read in total (1132298ms).
[11:43:23.660] <TB2> INFO: 32947400 events read in total (1154774ms).
[11:43:46.287] <TB2> INFO: 33589400 events read in total (1177401ms).
[11:44:08.917] <TB2> INFO: 34232200 events read in total (1200031ms).
[11:44:31.441] <TB2> INFO: 34874400 events read in total (1222555ms).
[11:44:53.955] <TB2> INFO: 35517250 events read in total (1245069ms).
[11:45:16.368] <TB2> INFO: 36164200 events read in total (1267482ms).
[11:45:31.361] <TB2> INFO: 36608000 events read in total (1282475ms).
[11:45:31.536] <TB2> INFO: Test took 1283479ms.
[11:45:32.180] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:45:34.357] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:45:36.683] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:45:38.807] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:45:40.916] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:45:43.031] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:45:45.252] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:45:47.431] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:45:49.360] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:45:50.956] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:45:52.443] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:45:53.983] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:45:55.519] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:45:57.025] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:45:58.562] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:46:00.158] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:46:01.678] <TB2> INFO: PixTestScurves::scurves() done
[11:46:01.678] <TB2> INFO: Vcal mean: 114.73 107.46 117.14 106.60 107.17 96.96 104.71 108.79 113.62 118.34 108.85 110.20 121.79 106.33 113.44 95.48
[11:46:01.678] <TB2> INFO: Vcal RMS: 4.98 5.42 7.60 4.98 4.83 5.20 4.86 4.89 4.84 5.57 5.35 5.10 6.10 4.62 7.10 5.05
[11:46:01.678] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1313 seconds
[11:46:01.678] <TB2> INFO: Decoding statistics:
[11:46:01.678] <TB2> INFO: General information:
[11:46:01.678] <TB2> INFO: 16bit words read: 0
[11:46:01.678] <TB2> INFO: valid events total: 0
[11:46:01.678] <TB2> INFO: empty events: 0
[11:46:01.678] <TB2> INFO: valid events with pixels: 0
[11:46:01.678] <TB2> INFO: valid pixel hits: 0
[11:46:01.678] <TB2> INFO: Event errors: 0
[11:46:01.678] <TB2> INFO: start marker: 0
[11:46:01.678] <TB2> INFO: stop marker: 0
[11:46:01.678] <TB2> INFO: overflow: 0
[11:46:01.678] <TB2> INFO: invalid 5bit words: 0
[11:46:01.678] <TB2> INFO: invalid XOR eye diagram: 0
[11:46:01.678] <TB2> INFO: frame (failed synchr.): 0
[11:46:01.678] <TB2> INFO: idle data (no TBM trl): 0
[11:46:01.678] <TB2> INFO: no data (only TBM hdr): 0
[11:46:01.678] <TB2> INFO: TBM errors: 0
[11:46:01.678] <TB2> INFO: flawed TBM headers: 0
[11:46:01.678] <TB2> INFO: flawed TBM trailers: 0
[11:46:01.678] <TB2> INFO: event ID mismatches: 0
[11:46:01.678] <TB2> INFO: ROC errors: 0
[11:46:01.678] <TB2> INFO: missing ROC header(s): 0
[11:46:01.678] <TB2> INFO: misplaced readback start: 0
[11:46:01.678] <TB2> INFO: Pixel decoding errors: 0
[11:46:01.678] <TB2> INFO: pixel data incomplete: 0
[11:46:01.678] <TB2> INFO: pixel address: 0
[11:46:01.678] <TB2> INFO: pulse height fill bit: 0
[11:46:01.678] <TB2> INFO: buffer corruption: 0
[11:46:01.745] <TB2> INFO: ######################################################################
[11:46:01.745] <TB2> INFO: PixTestTrim::doTest()
[11:46:01.745] <TB2> INFO: ######################################################################
[11:46:01.746] <TB2> INFO: ----------------------------------------------------------------------
[11:46:01.746] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[11:46:01.746] <TB2> INFO: ----------------------------------------------------------------------
[11:46:01.790] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[11:46:01.790] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:46:01.803] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:46:01.803] <TB2> INFO: run 1 of 1
[11:46:02.044] <TB2> INFO: Expecting 5025280 events.
[11:46:32.971] <TB2> INFO: 818320 events read in total (30316ms).
[11:47:03.264] <TB2> INFO: 1634424 events read in total (60609ms).
[11:47:33.848] <TB2> INFO: 2448072 events read in total (91193ms).
[11:48:04.146] <TB2> INFO: 3260008 events read in total (121491ms).
[11:48:33.810] <TB2> INFO: 4069424 events read in total (151156ms).
[11:49:03.856] <TB2> INFO: 4876152 events read in total (181201ms).
[11:49:10.213] <TB2> INFO: 5025280 events read in total (187558ms).
[11:49:10.274] <TB2> INFO: Test took 188471ms.
[11:49:33.574] <TB2> INFO: ROC 0 VthrComp = 127
[11:49:33.574] <TB2> INFO: ROC 1 VthrComp = 115
[11:49:33.574] <TB2> INFO: ROC 2 VthrComp = 117
[11:49:33.575] <TB2> INFO: ROC 3 VthrComp = 111
[11:49:33.575] <TB2> INFO: ROC 4 VthrComp = 109
[11:49:33.575] <TB2> INFO: ROC 5 VthrComp = 101
[11:49:33.575] <TB2> INFO: ROC 6 VthrComp = 112
[11:49:33.575] <TB2> INFO: ROC 7 VthrComp = 114
[11:49:33.575] <TB2> INFO: ROC 8 VthrComp = 125
[11:49:33.575] <TB2> INFO: ROC 9 VthrComp = 118
[11:49:33.575] <TB2> INFO: ROC 10 VthrComp = 122
[11:49:33.575] <TB2> INFO: ROC 11 VthrComp = 112
[11:49:33.576] <TB2> INFO: ROC 12 VthrComp = 131
[11:49:33.576] <TB2> INFO: ROC 13 VthrComp = 116
[11:49:33.576] <TB2> INFO: ROC 14 VthrComp = 119
[11:49:33.576] <TB2> INFO: ROC 15 VthrComp = 103
[11:49:33.818] <TB2> INFO: Expecting 41600 events.
[11:49:37.444] <TB2> INFO: 41600 events read in total (3034ms).
[11:49:37.445] <TB2> INFO: Test took 3866ms.
[11:49:37.456] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[11:49:37.456] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:49:37.470] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:49:37.470] <TB2> INFO: run 1 of 1
[11:49:37.749] <TB2> INFO: Expecting 5025280 events.
[11:50:04.055] <TB2> INFO: 587912 events read in total (25712ms).
[11:50:29.465] <TB2> INFO: 1176152 events read in total (51122ms).
[11:50:55.465] <TB2> INFO: 1765000 events read in total (77122ms).
[11:51:21.227] <TB2> INFO: 2353536 events read in total (102884ms).
[11:51:46.709] <TB2> INFO: 2939800 events read in total (128366ms).
[11:52:12.315] <TB2> INFO: 3525296 events read in total (153972ms).
[11:52:38.219] <TB2> INFO: 4110120 events read in total (179876ms).
[11:53:03.470] <TB2> INFO: 4693944 events read in total (205127ms).
[11:53:18.344] <TB2> INFO: 5025280 events read in total (220001ms).
[11:53:18.528] <TB2> INFO: Test took 221057ms.
[11:53:47.158] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 59.4965 for pixel 16/7 mean/min/max = 45.5386/31.5225/59.5547
[11:53:47.158] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 61.5418 for pixel 33/1 mean/min/max = 46.1916/30.7789/61.6043
[11:53:47.159] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 67.5366 for pixel 51/26 mean/min/max = 48.5604/29.2251/67.8956
[11:53:47.159] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.2058 for pixel 0/17 mean/min/max = 47.0605/33.8141/60.307
[11:53:47.160] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 61.7745 for pixel 8/1 mean/min/max = 47.7988/33.5854/62.0121
[11:53:47.160] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 60.4553 for pixel 0/13 mean/min/max = 46.5994/32.6933/60.5054
[11:53:47.161] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 60.0565 for pixel 31/1 mean/min/max = 46.1844/32.208/60.1607
[11:53:47.162] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 61.5726 for pixel 0/55 mean/min/max = 46.6432/31.569/61.7175
[11:53:47.162] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 58.5986 for pixel 0/1 mean/min/max = 44.4901/30.33/58.6502
[11:53:47.163] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 62.6758 for pixel 38/40 mean/min/max = 47.221/31.2466/63.1955
[11:53:47.163] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 58.8663 for pixel 8/28 mean/min/max = 44.7868/30.572/59.0016
[11:53:47.164] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 62.8371 for pixel 4/5 mean/min/max = 47.5412/32.1593/62.9231
[11:53:47.164] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 60.4431 for pixel 0/3 mean/min/max = 45.9324/31.2687/60.5961
[11:53:47.165] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 56.2511 for pixel 51/61 mean/min/max = 44.3195/32.1268/56.5122
[11:53:47.165] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 65.4285 for pixel 15/2 mean/min/max = 47.5203/29.3659/65.6746
[11:53:47.166] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 59.133 for pixel 51/79 mean/min/max = 46.2923/33.4391/59.1454
[11:53:47.166] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:53:47.255] <TB2> INFO: Expecting 411648 events.
[11:53:56.847] <TB2> INFO: 411648 events read in total (9000ms).
[11:53:56.854] <TB2> INFO: Expecting 411648 events.
[11:54:06.210] <TB2> INFO: 411648 events read in total (8952ms).
[11:54:06.226] <TB2> INFO: Expecting 411648 events.
[11:54:15.581] <TB2> INFO: 411648 events read in total (8952ms).
[11:54:15.594] <TB2> INFO: Expecting 411648 events.
[11:54:24.873] <TB2> INFO: 411648 events read in total (8876ms).
[11:54:24.890] <TB2> INFO: Expecting 411648 events.
[11:54:34.168] <TB2> INFO: 411648 events read in total (8875ms).
[11:54:34.187] <TB2> INFO: Expecting 411648 events.
[11:54:43.489] <TB2> INFO: 411648 events read in total (8899ms).
[11:54:43.511] <TB2> INFO: Expecting 411648 events.
[11:54:52.927] <TB2> INFO: 411648 events read in total (9013ms).
[11:54:52.960] <TB2> INFO: Expecting 411648 events.
[11:55:02.217] <TB2> INFO: 411648 events read in total (8854ms).
[11:55:02.244] <TB2> INFO: Expecting 411648 events.
[11:55:11.619] <TB2> INFO: 411648 events read in total (8972ms).
[11:55:11.649] <TB2> INFO: Expecting 411648 events.
[11:55:21.010] <TB2> INFO: 411648 events read in total (8958ms).
[11:55:21.043] <TB2> INFO: Expecting 411648 events.
[11:55:30.393] <TB2> INFO: 411648 events read in total (8947ms).
[11:55:30.433] <TB2> INFO: Expecting 411648 events.
[11:55:39.785] <TB2> INFO: 411648 events read in total (8949ms).
[11:55:39.833] <TB2> INFO: Expecting 411648 events.
[11:55:49.003] <TB2> INFO: 411648 events read in total (8767ms).
[11:55:49.053] <TB2> INFO: Expecting 411648 events.
[11:55:58.302] <TB2> INFO: 411648 events read in total (8846ms).
[11:55:58.356] <TB2> INFO: Expecting 411648 events.
[11:56:07.720] <TB2> INFO: 411648 events read in total (8961ms).
[11:56:07.771] <TB2> INFO: Expecting 411648 events.
[11:56:16.001] <TB2> INFO: 411648 events read in total (8827ms).
[11:56:17.066] <TB2> INFO: Test took 149900ms.
[11:56:17.926] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[11:56:17.939] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:56:17.939] <TB2> INFO: run 1 of 1
[11:56:18.175] <TB2> INFO: Expecting 5025280 events.
[11:56:44.775] <TB2> INFO: 586704 events read in total (26009ms).
[11:57:10.431] <TB2> INFO: 1172896 events read in total (51665ms).
[11:57:36.212] <TB2> INFO: 1758200 events read in total (77446ms).
[11:58:02.114] <TB2> INFO: 2344072 events read in total (103348ms).
[11:58:28.293] <TB2> INFO: 2930032 events read in total (129527ms).
[11:58:54.239] <TB2> INFO: 3516112 events read in total (155473ms).
[11:59:20.465] <TB2> INFO: 4101704 events read in total (181699ms).
[11:59:46.690] <TB2> INFO: 4687232 events read in total (207924ms).
[12:00:02.115] <TB2> INFO: 5025280 events read in total (223349ms).
[12:00:02.315] <TB2> INFO: Test took 224378ms.
[12:00:28.418] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 5.913533 .. 136.737402
[12:00:28.655] <TB2> INFO: Expecting 208000 events.
[12:00:38.345] <TB2> INFO: 208000 events read in total (9098ms).
[12:00:38.347] <TB2> INFO: Test took 9927ms.
[12:00:38.414] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 5 .. 146 (-1/-1) hits flags = 528 (plus default)
[12:00:38.428] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:00:38.428] <TB2> INFO: run 1 of 1
[12:00:38.707] <TB2> INFO: Expecting 4725760 events.
[12:01:05.134] <TB2> INFO: 582112 events read in total (25835ms).
[12:01:30.499] <TB2> INFO: 1164392 events read in total (51200ms).
[12:01:56.295] <TB2> INFO: 1746144 events read in total (76997ms).
[12:02:22.039] <TB2> INFO: 2328408 events read in total (102740ms).
[12:02:47.864] <TB2> INFO: 2910520 events read in total (128565ms).
[12:03:13.475] <TB2> INFO: 3491512 events read in total (154176ms).
[12:03:39.198] <TB2> INFO: 4071320 events read in total (179899ms).
[12:04:05.242] <TB2> INFO: 4651536 events read in total (205943ms).
[12:04:08.994] <TB2> INFO: 4725760 events read in total (209696ms).
[12:04:09.159] <TB2> INFO: Test took 210730ms.
[12:04:36.136] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 28.167475 .. 46.836859
[12:04:36.402] <TB2> INFO: Expecting 208000 events.
[12:04:46.211] <TB2> INFO: 208000 events read in total (9218ms).
[12:04:46.212] <TB2> INFO: Test took 10074ms.
[12:04:46.263] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 18 .. 56 (-1/-1) hits flags = 528 (plus default)
[12:04:46.275] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:04:46.276] <TB2> INFO: run 1 of 1
[12:04:46.553] <TB2> INFO: Expecting 1297920 events.
[12:05:14.858] <TB2> INFO: 650792 events read in total (27713ms).
[12:05:42.087] <TB2> INFO: 1297920 events read in total (54943ms).
[12:05:42.120] <TB2> INFO: Test took 55844ms.
[12:05:56.501] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 25.514382 .. 45.824088
[12:05:56.777] <TB2> INFO: Expecting 208000 events.
[12:06:06.541] <TB2> INFO: 208000 events read in total (9172ms).
[12:06:06.542] <TB2> INFO: Test took 10040ms.
[12:06:06.591] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:06:06.604] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:06:06.604] <TB2> INFO: run 1 of 1
[12:06:06.886] <TB2> INFO: Expecting 1364480 events.
[12:06:35.298] <TB2> INFO: 667792 events read in total (27821ms).
[12:07:03.037] <TB2> INFO: 1334096 events read in total (55561ms).
[12:07:04.702] <TB2> INFO: 1364480 events read in total (57225ms).
[12:07:04.735] <TB2> INFO: Test took 58131ms.
[12:07:17.849] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 25.274847 .. 43.393113
[12:07:18.174] <TB2> INFO: Expecting 208000 events.
[12:07:27.982] <TB2> INFO: 208000 events read in total (9216ms).
[12:07:27.983] <TB2> INFO: Test took 10132ms.
[12:07:28.042] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 53 (-1/-1) hits flags = 528 (plus default)
[12:07:28.056] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:07:28.056] <TB2> INFO: run 1 of 1
[12:07:28.334] <TB2> INFO: Expecting 1297920 events.
[12:07:56.803] <TB2> INFO: 675840 events read in total (27878ms).
[12:08:22.523] <TB2> INFO: 1297920 events read in total (53598ms).
[12:08:22.552] <TB2> INFO: Test took 54496ms.
[12:08:37.573] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:08:37.573] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:08:37.586] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:08:37.586] <TB2> INFO: run 1 of 1
[12:08:37.864] <TB2> INFO: Expecting 1364480 events.
[12:09:06.429] <TB2> INFO: 667800 events read in total (27974ms).
[12:09:34.499] <TB2> INFO: 1334816 events read in total (56045ms).
[12:09:36.231] <TB2> INFO: 1364480 events read in total (57777ms).
[12:09:36.260] <TB2> INFO: Test took 58674ms.
[12:09:51.558] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C0.dat
[12:09:51.559] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C1.dat
[12:09:51.559] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C2.dat
[12:09:51.559] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C3.dat
[12:09:51.559] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C4.dat
[12:09:51.559] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C5.dat
[12:09:51.559] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C6.dat
[12:09:51.559] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C7.dat
[12:09:51.559] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C8.dat
[12:09:51.559] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C9.dat
[12:09:51.559] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C10.dat
[12:09:51.559] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C11.dat
[12:09:51.560] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C12.dat
[12:09:51.560] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C13.dat
[12:09:51.560] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C14.dat
[12:09:51.560] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C15.dat
[12:09:51.560] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C0.dat
[12:09:51.567] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C1.dat
[12:09:51.575] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C2.dat
[12:09:51.582] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C3.dat
[12:09:51.589] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C4.dat
[12:09:51.596] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C5.dat
[12:09:51.602] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C6.dat
[12:09:51.609] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C7.dat
[12:09:51.616] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C8.dat
[12:09:51.622] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C9.dat
[12:09:51.628] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C10.dat
[12:09:51.634] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C11.dat
[12:09:51.640] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C12.dat
[12:09:51.647] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C13.dat
[12:09:51.654] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C14.dat
[12:09:51.661] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C15.dat
[12:09:51.667] <TB2> INFO: PixTestTrim::trimTest() done
[12:09:51.667] <TB2> INFO: vtrim: 135 159 144 129 125 125 138 127 128 135 135 143 124 121 157 124
[12:09:51.667] <TB2> INFO: vthrcomp: 127 115 117 111 109 101 112 114 125 118 122 112 131 116 119 103
[12:09:51.667] <TB2> INFO: vcal mean: 34.99 34.93 35.03 35.03 35.03 34.99 34.96 34.99 34.95 35.07 34.94 34.99 35.00 34.95 34.97 34.98
[12:09:51.667] <TB2> INFO: vcal RMS: 1.06 1.03 1.19 0.96 1.02 0.98 0.99 1.13 1.07 1.23 1.03 1.11 1.11 0.95 1.15 0.95
[12:09:51.667] <TB2> INFO: bits mean: 10.02 9.92 8.92 8.28 8.91 9.17 9.42 9.05 9.54 9.69 9.97 9.47 8.86 9.57 9.50 8.68
[12:09:51.667] <TB2> INFO: bits RMS: 2.51 2.60 3.08 2.87 2.62 2.73 2.72 2.93 3.02 2.64 2.66 2.61 3.05 2.73 2.81 2.86
[12:09:51.675] <TB2> INFO: ----------------------------------------------------------------------
[12:09:51.675] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:09:51.675] <TB2> INFO: ----------------------------------------------------------------------
[12:09:51.678] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:09:51.691] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:09:51.691] <TB2> INFO: run 1 of 1
[12:09:51.992] <TB2> INFO: Expecting 4160000 events.
[12:10:24.196] <TB2> INFO: 728910 events read in total (31613ms).
[12:10:55.669] <TB2> INFO: 1453915 events read in total (63086ms).
[12:11:26.925] <TB2> INFO: 2174630 events read in total (94342ms).
[12:11:58.071] <TB2> INFO: 2890865 events read in total (125488ms).
[12:12:29.468] <TB2> INFO: 3605695 events read in total (156885ms).
[12:12:53.214] <TB2> INFO: 4160000 events read in total (180631ms).
[12:12:53.296] <TB2> INFO: Test took 181604ms.
[12:13:22.150] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[12:13:22.165] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:13:22.165] <TB2> INFO: run 1 of 1
[12:13:22.426] <TB2> INFO: Expecting 4243200 events.
[12:13:53.668] <TB2> INFO: 701425 events read in total (30648ms).
[12:14:24.413] <TB2> INFO: 1399910 events read in total (61393ms).
[12:14:55.024] <TB2> INFO: 2095040 events read in total (92004ms).
[12:15:25.490] <TB2> INFO: 2787195 events read in total (122470ms).
[12:15:56.032] <TB2> INFO: 3478150 events read in total (153012ms).
[12:16:26.726] <TB2> INFO: 4167950 events read in total (183706ms).
[12:16:30.382] <TB2> INFO: 4243200 events read in total (187362ms).
[12:16:30.502] <TB2> INFO: Test took 188337ms.
[12:17:00.140] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 190 (-1/-1) hits flags = 528 (plus default)
[12:17:00.155] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:17:00.155] <TB2> INFO: run 1 of 1
[12:17:00.489] <TB2> INFO: Expecting 3972800 events.
[12:17:32.180] <TB2> INFO: 717100 events read in total (31101ms).
[12:18:03.317] <TB2> INFO: 1430485 events read in total (62237ms).
[12:18:34.292] <TB2> INFO: 2140015 events read in total (93212ms).
[12:19:05.330] <TB2> INFO: 2846100 events read in total (124250ms).
[12:19:36.099] <TB2> INFO: 3550425 events read in total (155019ms).
[12:19:54.792] <TB2> INFO: 3972800 events read in total (173712ms).
[12:19:54.894] <TB2> INFO: Test took 174739ms.
[12:20:24.137] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 187 (-1/-1) hits flags = 528 (plus default)
[12:20:24.150] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:20:24.150] <TB2> INFO: run 1 of 1
[12:20:24.480] <TB2> INFO: Expecting 3910400 events.
[12:20:56.412] <TB2> INFO: 720890 events read in total (31340ms).
[12:21:27.427] <TB2> INFO: 1438255 events read in total (62355ms).
[12:21:58.332] <TB2> INFO: 2151260 events read in total (93260ms).
[12:22:29.374] <TB2> INFO: 2861100 events read in total (124302ms).
[12:23:00.358] <TB2> INFO: 3568970 events read in total (155286ms).
[12:23:16.144] <TB2> INFO: 3910400 events read in total (171072ms).
[12:23:16.306] <TB2> INFO: Test took 172156ms.
[12:23:41.916] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 187 (-1/-1) hits flags = 528 (plus default)
[12:23:41.930] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:23:41.930] <TB2> INFO: run 1 of 1
[12:23:42.176] <TB2> INFO: Expecting 3910400 events.
[12:24:14.168] <TB2> INFO: 720985 events read in total (31401ms).
[12:24:45.153] <TB2> INFO: 1438585 events read in total (62386ms).
[12:25:16.406] <TB2> INFO: 2151420 events read in total (93639ms).
[12:25:47.707] <TB2> INFO: 2861105 events read in total (124940ms).
[12:26:18.554] <TB2> INFO: 3568875 events read in total (155787ms).
[12:26:33.547] <TB2> INFO: 3910400 events read in total (170780ms).
[12:26:33.634] <TB2> INFO: Test took 171704ms.
[12:27:02.511] <TB2> INFO: PixTestTrim::trimBitTest() done
[12:27:02.513] <TB2> INFO: PixTestTrim::doTest() done, duration: 2460 seconds
[12:27:02.513] <TB2> INFO: Decoding statistics:
[12:27:02.513] <TB2> INFO: General information:
[12:27:02.513] <TB2> INFO: 16bit words read: 0
[12:27:02.513] <TB2> INFO: valid events total: 0
[12:27:02.513] <TB2> INFO: empty events: 0
[12:27:02.513] <TB2> INFO: valid events with pixels: 0
[12:27:02.513] <TB2> INFO: valid pixel hits: 0
[12:27:02.513] <TB2> INFO: Event errors: 0
[12:27:02.513] <TB2> INFO: start marker: 0
[12:27:02.513] <TB2> INFO: stop marker: 0
[12:27:02.513] <TB2> INFO: overflow: 0
[12:27:02.513] <TB2> INFO: invalid 5bit words: 0
[12:27:02.513] <TB2> INFO: invalid XOR eye diagram: 0
[12:27:02.513] <TB2> INFO: frame (failed synchr.): 0
[12:27:02.513] <TB2> INFO: idle data (no TBM trl): 0
[12:27:02.513] <TB2> INFO: no data (only TBM hdr): 0
[12:27:02.513] <TB2> INFO: TBM errors: 0
[12:27:02.513] <TB2> INFO: flawed TBM headers: 0
[12:27:02.513] <TB2> INFO: flawed TBM trailers: 0
[12:27:02.513] <TB2> INFO: event ID mismatches: 0
[12:27:02.513] <TB2> INFO: ROC errors: 0
[12:27:02.513] <TB2> INFO: missing ROC header(s): 0
[12:27:02.514] <TB2> INFO: misplaced readback start: 0
[12:27:02.514] <TB2> INFO: Pixel decoding errors: 0
[12:27:02.514] <TB2> INFO: pixel data incomplete: 0
[12:27:02.514] <TB2> INFO: pixel address: 0
[12:27:02.514] <TB2> INFO: pulse height fill bit: 0
[12:27:02.514] <TB2> INFO: buffer corruption: 0
[12:27:03.137] <TB2> INFO: ######################################################################
[12:27:03.137] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:27:03.137] <TB2> INFO: ######################################################################
[12:27:03.373] <TB2> INFO: Expecting 41600 events.
[12:27:06.833] <TB2> INFO: 41600 events read in total (2868ms).
[12:27:06.834] <TB2> INFO: Test took 3696ms.
[12:27:07.273] <TB2> INFO: Expecting 41600 events.
[12:27:10.858] <TB2> INFO: 41600 events read in total (2993ms).
[12:27:10.858] <TB2> INFO: Test took 3821ms.
[12:27:11.147] <TB2> INFO: Expecting 41600 events.
[12:27:14.757] <TB2> INFO: 41600 events read in total (3018ms).
[12:27:14.758] <TB2> INFO: Test took 3876ms.
[12:27:15.047] <TB2> INFO: Expecting 41600 events.
[12:27:18.565] <TB2> INFO: 41600 events read in total (2926ms).
[12:27:18.566] <TB2> INFO: Test took 3784ms.
[12:27:18.875] <TB2> INFO: Expecting 41600 events.
[12:27:22.444] <TB2> INFO: 41600 events read in total (2977ms).
[12:27:22.445] <TB2> INFO: Test took 3854ms.
[12:27:22.734] <TB2> INFO: Expecting 41600 events.
[12:27:26.289] <TB2> INFO: 41600 events read in total (2963ms).
[12:27:26.290] <TB2> INFO: Test took 3822ms.
[12:27:26.579] <TB2> INFO: Expecting 41600 events.
[12:27:30.212] <TB2> INFO: 41600 events read in total (3041ms).
[12:27:30.212] <TB2> INFO: Test took 3897ms.
[12:27:30.502] <TB2> INFO: Expecting 41600 events.
[12:27:34.036] <TB2> INFO: 41600 events read in total (2943ms).
[12:27:34.037] <TB2> INFO: Test took 3801ms.
[12:27:34.331] <TB2> INFO: Expecting 41600 events.
[12:27:37.980] <TB2> INFO: 41600 events read in total (3058ms).
[12:27:37.981] <TB2> INFO: Test took 3916ms.
[12:27:38.273] <TB2> INFO: Expecting 41600 events.
[12:27:41.812] <TB2> INFO: 41600 events read in total (2948ms).
[12:27:41.813] <TB2> INFO: Test took 3805ms.
[12:27:42.104] <TB2> INFO: Expecting 41600 events.
[12:27:45.605] <TB2> INFO: 41600 events read in total (2910ms).
[12:27:45.605] <TB2> INFO: Test took 3767ms.
[12:27:45.897] <TB2> INFO: Expecting 41600 events.
[12:27:49.527] <TB2> INFO: 41600 events read in total (3039ms).
[12:27:49.529] <TB2> INFO: Test took 3898ms.
[12:27:49.818] <TB2> INFO: Expecting 41600 events.
[12:27:53.345] <TB2> INFO: 41600 events read in total (2935ms).
[12:27:53.346] <TB2> INFO: Test took 3793ms.
[12:27:53.651] <TB2> INFO: Expecting 41600 events.
[12:27:57.358] <TB2> INFO: 41600 events read in total (3115ms).
[12:27:57.359] <TB2> INFO: Test took 3989ms.
[12:27:57.651] <TB2> INFO: Expecting 41600 events.
[12:28:01.180] <TB2> INFO: 41600 events read in total (2937ms).
[12:28:01.181] <TB2> INFO: Test took 3795ms.
[12:28:01.471] <TB2> INFO: Expecting 41600 events.
[12:28:05.011] <TB2> INFO: 41600 events read in total (2948ms).
[12:28:05.012] <TB2> INFO: Test took 3806ms.
[12:28:05.302] <TB2> INFO: Expecting 41600 events.
[12:28:08.925] <TB2> INFO: 41600 events read in total (3031ms).
[12:28:08.926] <TB2> INFO: Test took 3889ms.
[12:28:09.216] <TB2> INFO: Expecting 41600 events.
[12:28:12.760] <TB2> INFO: 41600 events read in total (2952ms).
[12:28:12.761] <TB2> INFO: Test took 3811ms.
[12:28:13.051] <TB2> INFO: Expecting 41600 events.
[12:28:16.612] <TB2> INFO: 41600 events read in total (2970ms).
[12:28:16.613] <TB2> INFO: Test took 3828ms.
[12:28:16.902] <TB2> INFO: Expecting 41600 events.
[12:28:20.415] <TB2> INFO: 41600 events read in total (2921ms).
[12:28:20.416] <TB2> INFO: Test took 3779ms.
[12:28:20.707] <TB2> INFO: Expecting 41600 events.
[12:28:24.322] <TB2> INFO: 41600 events read in total (3024ms).
[12:28:24.323] <TB2> INFO: Test took 3882ms.
[12:28:24.613] <TB2> INFO: Expecting 41600 events.
[12:28:28.219] <TB2> INFO: 41600 events read in total (3014ms).
[12:28:28.220] <TB2> INFO: Test took 3873ms.
[12:28:28.510] <TB2> INFO: Expecting 41600 events.
[12:28:32.089] <TB2> INFO: 41600 events read in total (2987ms).
[12:28:32.090] <TB2> INFO: Test took 3845ms.
[12:28:32.383] <TB2> INFO: Expecting 41600 events.
[12:28:35.927] <TB2> INFO: 41600 events read in total (2953ms).
[12:28:35.927] <TB2> INFO: Test took 3810ms.
[12:28:36.217] <TB2> INFO: Expecting 41600 events.
[12:28:39.846] <TB2> INFO: 41600 events read in total (3038ms).
[12:28:39.847] <TB2> INFO: Test took 3896ms.
[12:28:40.136] <TB2> INFO: Expecting 41600 events.
[12:28:43.714] <TB2> INFO: 41600 events read in total (2986ms).
[12:28:43.715] <TB2> INFO: Test took 3844ms.
[12:28:44.023] <TB2> INFO: Expecting 41600 events.
[12:28:47.586] <TB2> INFO: 41600 events read in total (2971ms).
[12:28:47.587] <TB2> INFO: Test took 3845ms.
[12:28:47.876] <TB2> INFO: Expecting 41600 events.
[12:28:51.460] <TB2> INFO: 41600 events read in total (2993ms).
[12:28:51.461] <TB2> INFO: Test took 3850ms.
[12:28:51.757] <TB2> INFO: Expecting 41600 events.
[12:28:55.354] <TB2> INFO: 41600 events read in total (3006ms).
[12:28:55.355] <TB2> INFO: Test took 3870ms.
[12:28:55.646] <TB2> INFO: Expecting 41600 events.
[12:28:59.214] <TB2> INFO: 41600 events read in total (2977ms).
[12:28:59.215] <TB2> INFO: Test took 3835ms.
[12:28:59.507] <TB2> INFO: Expecting 41600 events.
[12:29:03.044] <TB2> INFO: 41600 events read in total (2945ms).
[12:29:03.044] <TB2> INFO: Test took 3803ms.
[12:29:03.334] <TB2> INFO: Expecting 2560 events.
[12:29:04.220] <TB2> INFO: 2560 events read in total (294ms).
[12:29:04.220] <TB2> INFO: Test took 1163ms.
[12:29:04.529] <TB2> INFO: Expecting 2560 events.
[12:29:05.416] <TB2> INFO: 2560 events read in total (295ms).
[12:29:05.416] <TB2> INFO: Test took 1195ms.
[12:29:05.724] <TB2> INFO: Expecting 2560 events.
[12:29:06.616] <TB2> INFO: 2560 events read in total (300ms).
[12:29:06.616] <TB2> INFO: Test took 1199ms.
[12:29:06.924] <TB2> INFO: Expecting 2560 events.
[12:29:07.810] <TB2> INFO: 2560 events read in total (294ms).
[12:29:07.811] <TB2> INFO: Test took 1194ms.
[12:29:08.117] <TB2> INFO: Expecting 2560 events.
[12:29:09.006] <TB2> INFO: 2560 events read in total (297ms).
[12:29:09.006] <TB2> INFO: Test took 1195ms.
[12:29:09.313] <TB2> INFO: Expecting 2560 events.
[12:29:10.205] <TB2> INFO: 2560 events read in total (298ms).
[12:29:10.205] <TB2> INFO: Test took 1198ms.
[12:29:10.514] <TB2> INFO: Expecting 2560 events.
[12:29:11.403] <TB2> INFO: 2560 events read in total (297ms).
[12:29:11.403] <TB2> INFO: Test took 1197ms.
[12:29:11.711] <TB2> INFO: Expecting 2560 events.
[12:29:12.592] <TB2> INFO: 2560 events read in total (289ms).
[12:29:12.592] <TB2> INFO: Test took 1189ms.
[12:29:12.899] <TB2> INFO: Expecting 2560 events.
[12:29:13.793] <TB2> INFO: 2560 events read in total (302ms).
[12:29:13.793] <TB2> INFO: Test took 1200ms.
[12:29:14.100] <TB2> INFO: Expecting 2560 events.
[12:29:14.987] <TB2> INFO: 2560 events read in total (295ms).
[12:29:14.987] <TB2> INFO: Test took 1193ms.
[12:29:15.296] <TB2> INFO: Expecting 2560 events.
[12:29:16.178] <TB2> INFO: 2560 events read in total (290ms).
[12:29:16.179] <TB2> INFO: Test took 1191ms.
[12:29:16.486] <TB2> INFO: Expecting 2560 events.
[12:29:17.370] <TB2> INFO: 2560 events read in total (292ms).
[12:29:17.370] <TB2> INFO: Test took 1191ms.
[12:29:17.678] <TB2> INFO: Expecting 2560 events.
[12:29:18.565] <TB2> INFO: 2560 events read in total (295ms).
[12:29:18.565] <TB2> INFO: Test took 1194ms.
[12:29:18.873] <TB2> INFO: Expecting 2560 events.
[12:29:19.766] <TB2> INFO: 2560 events read in total (302ms).
[12:29:19.766] <TB2> INFO: Test took 1200ms.
[12:29:20.073] <TB2> INFO: Expecting 2560 events.
[12:29:20.966] <TB2> INFO: 2560 events read in total (301ms).
[12:29:20.966] <TB2> INFO: Test took 1199ms.
[12:29:21.274] <TB2> INFO: Expecting 2560 events.
[12:29:22.168] <TB2> INFO: 2560 events read in total (302ms).
[12:29:22.169] <TB2> INFO: Test took 1203ms.
[12:29:22.171] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:29:22.484] <TB2> INFO: Expecting 655360 events.
[12:29:37.136] <TB2> INFO: 655360 events read in total (14060ms).
[12:29:37.150] <TB2> INFO: Expecting 655360 events.
[12:29:51.777] <TB2> INFO: 655360 events read in total (14224ms).
[12:29:51.804] <TB2> INFO: Expecting 655360 events.
[12:30:06.197] <TB2> INFO: 655360 events read in total (13989ms).
[12:30:06.221] <TB2> INFO: Expecting 655360 events.
[12:30:20.710] <TB2> INFO: 655360 events read in total (14086ms).
[12:30:20.746] <TB2> INFO: Expecting 655360 events.
[12:30:35.254] <TB2> INFO: 655360 events read in total (14104ms).
[12:30:35.286] <TB2> INFO: Expecting 655360 events.
[12:30:49.898] <TB2> INFO: 655360 events read in total (14209ms).
[12:30:49.935] <TB2> INFO: Expecting 655360 events.
[12:31:04.384] <TB2> INFO: 655360 events read in total (14046ms).
[12:31:04.422] <TB2> INFO: Expecting 655360 events.
[12:31:18.993] <TB2> INFO: 655360 events read in total (14168ms).
[12:31:19.038] <TB2> INFO: Expecting 655360 events.
[12:31:33.433] <TB2> INFO: 655360 events read in total (13990ms).
[12:31:33.486] <TB2> INFO: Expecting 655360 events.
[12:31:48.151] <TB2> INFO: 655360 events read in total (14262ms).
[12:31:48.244] <TB2> INFO: Expecting 655360 events.
[12:32:02.674] <TB2> INFO: 655360 events read in total (14026ms).
[12:32:02.731] <TB2> INFO: Expecting 655360 events.
[12:32:17.337] <TB2> INFO: 655360 events read in total (14203ms).
[12:32:17.410] <TB2> INFO: Expecting 655360 events.
[12:32:31.997] <TB2> INFO: 655360 events read in total (14183ms).
[12:32:32.099] <TB2> INFO: Expecting 655360 events.
[12:32:46.603] <TB2> INFO: 655360 events read in total (14100ms).
[12:32:46.719] <TB2> INFO: Expecting 655360 events.
[12:33:01.288] <TB2> INFO: 655360 events read in total (14166ms).
[12:33:01.421] <TB2> INFO: Expecting 655360 events.
[12:33:16.048] <TB2> INFO: 655360 events read in total (14224ms).
[12:33:16.205] <TB2> INFO: Test took 234034ms.
[12:33:16.302] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:33:16.559] <TB2> INFO: Expecting 655360 events.
[12:33:31.005] <TB2> INFO: 655360 events read in total (13854ms).
[12:33:31.020] <TB2> INFO: Expecting 655360 events.
[12:33:45.375] <TB2> INFO: 655360 events read in total (13952ms).
[12:33:45.394] <TB2> INFO: Expecting 655360 events.
[12:33:59.634] <TB2> INFO: 655360 events read in total (13837ms).
[12:33:59.655] <TB2> INFO: Expecting 655360 events.
[12:34:14.122] <TB2> INFO: 655360 events read in total (14064ms).
[12:34:14.146] <TB2> INFO: Expecting 655360 events.
[12:34:28.682] <TB2> INFO: 655360 events read in total (14133ms).
[12:34:28.726] <TB2> INFO: Expecting 655360 events.
[12:34:43.300] <TB2> INFO: 655360 events read in total (14171ms).
[12:34:43.349] <TB2> INFO: Expecting 655360 events.
[12:34:57.643] <TB2> INFO: 655360 events read in total (13891ms).
[12:34:57.681] <TB2> INFO: Expecting 655360 events.
[12:35:12.122] <TB2> INFO: 655360 events read in total (14037ms).
[12:35:12.183] <TB2> INFO: Expecting 655360 events.
[12:35:26.535] <TB2> INFO: 655360 events read in total (13949ms).
[12:35:26.580] <TB2> INFO: Expecting 655360 events.
[12:35:40.845] <TB2> INFO: 655360 events read in total (13862ms).
[12:35:40.923] <TB2> INFO: Expecting 655360 events.
[12:35:55.309] <TB2> INFO: 655360 events read in total (13983ms).
[12:35:55.370] <TB2> INFO: Expecting 655360 events.
[12:36:09.749] <TB2> INFO: 655360 events read in total (13977ms).
[12:36:09.849] <TB2> INFO: Expecting 655360 events.
[12:36:24.184] <TB2> INFO: 655360 events read in total (13932ms).
[12:36:24.312] <TB2> INFO: Expecting 655360 events.
[12:36:38.899] <TB2> INFO: 655360 events read in total (14184ms).
[12:36:38.994] <TB2> INFO: Expecting 655360 events.
[12:36:53.434] <TB2> INFO: 655360 events read in total (14036ms).
[12:36:53.552] <TB2> INFO: Expecting 655360 events.
[12:37:08.177] <TB2> INFO: 655360 events read in total (14222ms).
[12:37:08.276] <TB2> INFO: Test took 231974ms.
[12:37:08.522] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.531] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.539] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.548] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:08.557] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:37:08.566] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:37:08.575] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:37:08.584] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[12:37:08.593] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[12:37:08.601] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[12:37:08.610] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.618] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:08.626] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:37:08.635] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:37:08.643] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:37:08.652] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[12:37:08.660] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[12:37:08.669] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.677] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:08.687] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:37:08.697] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.708] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:08.718] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:37:08.728] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:37:08.739] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:37:08.748] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[12:37:08.757] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[12:37:08.767] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[12:37:08.777] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.785] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.793] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:08.802] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:37:08.810] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.819] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.827] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.835] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.842] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:08.850] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.858] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:08.864] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:37:08.870] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:37:08.876] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:37:08.882] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[12:37:08.889] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[12:37:08.895] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[12:37:08.901] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[12:37:08.907] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[12:37:08.914] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[12:37:08.920] <TB2> INFO: safety margin for low PH: adding 11, margin is now 31
[12:37:08.926] <TB2> INFO: safety margin for low PH: adding 12, margin is now 32
[12:37:08.933] <TB2> INFO: safety margin for low PH: adding 13, margin is now 33
[12:37:08.939] <TB2> INFO: safety margin for low PH: adding 14, margin is now 34
[12:37:08.946] <TB2> INFO: safety margin for low PH: adding 15, margin is now 35
[12:37:08.953] <TB2> INFO: safety margin for low PH: adding 16, margin is now 36
[12:37:08.960] <TB2> INFO: safety margin for low PH: adding 17, margin is now 37
[12:37:08.967] <TB2> INFO: safety margin for low PH: adding 18, margin is now 38
[12:37:08.974] <TB2> INFO: safety margin for low PH: adding 19, margin is now 39
[12:37:08.980] <TB2> INFO: safety margin for low PH: adding 20, margin is now 40
[12:37:08.987] <TB2> INFO: safety margin for low PH: adding 21, margin is now 41
[12:37:08.994] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.002] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:09.009] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:09.048] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C0.dat
[12:37:09.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C1.dat
[12:37:09.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C2.dat
[12:37:09.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C3.dat
[12:37:09.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C4.dat
[12:37:09.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C5.dat
[12:37:09.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C6.dat
[12:37:09.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C7.dat
[12:37:09.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C8.dat
[12:37:09.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C9.dat
[12:37:09.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C10.dat
[12:37:09.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C11.dat
[12:37:09.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C12.dat
[12:37:09.050] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C13.dat
[12:37:09.050] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C14.dat
[12:37:09.050] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C15.dat
[12:37:09.294] <TB2> INFO: Expecting 41600 events.
[12:37:12.457] <TB2> INFO: 41600 events read in total (2571ms).
[12:37:12.457] <TB2> INFO: Test took 3403ms.
[12:37:12.910] <TB2> INFO: Expecting 41600 events.
[12:37:16.037] <TB2> INFO: 41600 events read in total (2535ms).
[12:37:16.038] <TB2> INFO: Test took 3367ms.
[12:37:16.489] <TB2> INFO: Expecting 41600 events.
[12:37:19.673] <TB2> INFO: 41600 events read in total (2592ms).
[12:37:19.673] <TB2> INFO: Test took 3424ms.
[12:37:19.893] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:19.983] <TB2> INFO: Expecting 2560 events.
[12:37:20.877] <TB2> INFO: 2560 events read in total (302ms).
[12:37:20.877] <TB2> INFO: Test took 984ms.
[12:37:20.880] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:21.186] <TB2> INFO: Expecting 2560 events.
[12:37:22.082] <TB2> INFO: 2560 events read in total (304ms).
[12:37:22.083] <TB2> INFO: Test took 1203ms.
[12:37:22.086] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:22.392] <TB2> INFO: Expecting 2560 events.
[12:37:23.285] <TB2> INFO: 2560 events read in total (301ms).
[12:37:23.285] <TB2> INFO: Test took 1199ms.
[12:37:23.289] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:23.593] <TB2> INFO: Expecting 2560 events.
[12:37:24.488] <TB2> INFO: 2560 events read in total (303ms).
[12:37:24.489] <TB2> INFO: Test took 1201ms.
[12:37:24.493] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:24.796] <TB2> INFO: Expecting 2560 events.
[12:37:25.687] <TB2> INFO: 2560 events read in total (299ms).
[12:37:25.687] <TB2> INFO: Test took 1194ms.
[12:37:25.690] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:25.996] <TB2> INFO: Expecting 2560 events.
[12:37:26.891] <TB2> INFO: 2560 events read in total (304ms).
[12:37:26.892] <TB2> INFO: Test took 1202ms.
[12:37:26.896] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:27.200] <TB2> INFO: Expecting 2560 events.
[12:37:28.098] <TB2> INFO: 2560 events read in total (306ms).
[12:37:28.098] <TB2> INFO: Test took 1203ms.
[12:37:28.102] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:28.406] <TB2> INFO: Expecting 2560 events.
[12:37:29.301] <TB2> INFO: 2560 events read in total (303ms).
[12:37:29.301] <TB2> INFO: Test took 1200ms.
[12:37:29.306] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:29.609] <TB2> INFO: Expecting 2560 events.
[12:37:30.497] <TB2> INFO: 2560 events read in total (296ms).
[12:37:30.498] <TB2> INFO: Test took 1192ms.
[12:37:30.501] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:30.806] <TB2> INFO: Expecting 2560 events.
[12:37:31.696] <TB2> INFO: 2560 events read in total (298ms).
[12:37:31.697] <TB2> INFO: Test took 1196ms.
[12:37:31.700] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:32.005] <TB2> INFO: Expecting 2560 events.
[12:37:32.897] <TB2> INFO: 2560 events read in total (300ms).
[12:37:32.898] <TB2> INFO: Test took 1198ms.
[12:37:32.902] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:33.206] <TB2> INFO: Expecting 2560 events.
[12:37:34.098] <TB2> INFO: 2560 events read in total (300ms).
[12:37:34.098] <TB2> INFO: Test took 1196ms.
[12:37:34.101] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:34.408] <TB2> INFO: Expecting 2560 events.
[12:37:35.297] <TB2> INFO: 2560 events read in total (297ms).
[12:37:35.298] <TB2> INFO: Test took 1197ms.
[12:37:35.301] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:35.605] <TB2> INFO: Expecting 2560 events.
[12:37:36.497] <TB2> INFO: 2560 events read in total (300ms).
[12:37:36.497] <TB2> INFO: Test took 1196ms.
[12:37:36.501] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:36.805] <TB2> INFO: Expecting 2560 events.
[12:37:37.699] <TB2> INFO: 2560 events read in total (300ms).
[12:37:37.700] <TB2> INFO: Test took 1199ms.
[12:37:37.703] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:38.007] <TB2> INFO: Expecting 2560 events.
[12:37:38.900] <TB2> INFO: 2560 events read in total (301ms).
[12:37:38.900] <TB2> INFO: Test took 1197ms.
[12:37:38.903] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:39.209] <TB2> INFO: Expecting 2560 events.
[12:37:40.100] <TB2> INFO: 2560 events read in total (300ms).
[12:37:40.100] <TB2> INFO: Test took 1198ms.
[12:37:40.104] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:40.408] <TB2> INFO: Expecting 2560 events.
[12:37:41.298] <TB2> INFO: 2560 events read in total (298ms).
[12:37:41.298] <TB2> INFO: Test took 1194ms.
[12:37:41.303] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:41.607] <TB2> INFO: Expecting 2560 events.
[12:37:42.495] <TB2> INFO: 2560 events read in total (296ms).
[12:37:42.495] <TB2> INFO: Test took 1192ms.
[12:37:42.497] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:42.805] <TB2> INFO: Expecting 2560 events.
[12:37:43.694] <TB2> INFO: 2560 events read in total (298ms).
[12:37:43.695] <TB2> INFO: Test took 1198ms.
[12:37:43.700] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:44.004] <TB2> INFO: Expecting 2560 events.
[12:37:44.898] <TB2> INFO: 2560 events read in total (302ms).
[12:37:44.899] <TB2> INFO: Test took 1199ms.
[12:37:44.902] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:45.207] <TB2> INFO: Expecting 2560 events.
[12:37:46.091] <TB2> INFO: 2560 events read in total (292ms).
[12:37:46.092] <TB2> INFO: Test took 1190ms.
[12:37:46.095] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:46.398] <TB2> INFO: Expecting 2560 events.
[12:37:47.289] <TB2> INFO: 2560 events read in total (299ms).
[12:37:47.289] <TB2> INFO: Test took 1194ms.
[12:37:47.292] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:47.598] <TB2> INFO: Expecting 2560 events.
[12:37:48.487] <TB2> INFO: 2560 events read in total (297ms).
[12:37:48.487] <TB2> INFO: Test took 1195ms.
[12:37:48.491] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:48.796] <TB2> INFO: Expecting 2560 events.
[12:37:49.687] <TB2> INFO: 2560 events read in total (299ms).
[12:37:49.687] <TB2> INFO: Test took 1196ms.
[12:37:49.692] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:49.995] <TB2> INFO: Expecting 2560 events.
[12:37:50.880] <TB2> INFO: 2560 events read in total (293ms).
[12:37:50.880] <TB2> INFO: Test took 1188ms.
[12:37:50.884] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:51.189] <TB2> INFO: Expecting 2560 events.
[12:37:52.083] <TB2> INFO: 2560 events read in total (303ms).
[12:37:52.084] <TB2> INFO: Test took 1200ms.
[12:37:52.092] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:52.392] <TB2> INFO: Expecting 2560 events.
[12:37:53.287] <TB2> INFO: 2560 events read in total (303ms).
[12:37:53.287] <TB2> INFO: Test took 1195ms.
[12:37:53.291] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:53.596] <TB2> INFO: Expecting 2560 events.
[12:37:54.485] <TB2> INFO: 2560 events read in total (297ms).
[12:37:54.485] <TB2> INFO: Test took 1195ms.
[12:37:54.489] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:54.793] <TB2> INFO: Expecting 2560 events.
[12:37:55.690] <TB2> INFO: 2560 events read in total (305ms).
[12:37:55.690] <TB2> INFO: Test took 1201ms.
[12:37:55.694] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:55.998] <TB2> INFO: Expecting 2560 events.
[12:37:56.886] <TB2> INFO: 2560 events read in total (296ms).
[12:37:56.887] <TB2> INFO: Test took 1194ms.
[12:37:56.889] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:57.195] <TB2> INFO: Expecting 2560 events.
[12:37:58.091] <TB2> INFO: 2560 events read in total (304ms).
[12:37:58.091] <TB2> INFO: Test took 1202ms.
[12:37:58.572] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 655 seconds
[12:37:58.572] <TB2> INFO: PH scale (per ROC): 42 53 49 58 45 48 54 47 49 66 64 49 39 66 46 46
[12:37:58.572] <TB2> INFO: PH offset (per ROC): 99 134 112 112 119 112 94 91 103 117 118 119 112 130 106 94
[12:37:58.579] <TB2> INFO: Decoding statistics:
[12:37:58.580] <TB2> INFO: General information:
[12:37:58.580] <TB2> INFO: 16bit words read: 127882
[12:37:58.580] <TB2> INFO: valid events total: 20480
[12:37:58.580] <TB2> INFO: empty events: 17979
[12:37:58.580] <TB2> INFO: valid events with pixels: 2501
[12:37:58.580] <TB2> INFO: valid pixel hits: 2501
[12:37:58.580] <TB2> INFO: Event errors: 0
[12:37:58.580] <TB2> INFO: start marker: 0
[12:37:58.580] <TB2> INFO: stop marker: 0
[12:37:58.580] <TB2> INFO: overflow: 0
[12:37:58.580] <TB2> INFO: invalid 5bit words: 0
[12:37:58.580] <TB2> INFO: invalid XOR eye diagram: 0
[12:37:58.580] <TB2> INFO: frame (failed synchr.): 0
[12:37:58.580] <TB2> INFO: idle data (no TBM trl): 0
[12:37:58.580] <TB2> INFO: no data (only TBM hdr): 0
[12:37:58.580] <TB2> INFO: TBM errors: 0
[12:37:58.580] <TB2> INFO: flawed TBM headers: 0
[12:37:58.580] <TB2> INFO: flawed TBM trailers: 0
[12:37:58.580] <TB2> INFO: event ID mismatches: 0
[12:37:58.580] <TB2> INFO: ROC errors: 0
[12:37:58.580] <TB2> INFO: missing ROC header(s): 0
[12:37:58.580] <TB2> INFO: misplaced readback start: 0
[12:37:58.580] <TB2> INFO: Pixel decoding errors: 0
[12:37:58.580] <TB2> INFO: pixel data incomplete: 0
[12:37:58.580] <TB2> INFO: pixel address: 0
[12:37:58.580] <TB2> INFO: pulse height fill bit: 0
[12:37:58.580] <TB2> INFO: buffer corruption: 0
[12:37:58.749] <TB2> INFO: ######################################################################
[12:37:58.749] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[12:37:58.749] <TB2> INFO: ######################################################################
[12:37:58.764] <TB2> INFO: scanning low vcal = 10
[12:37:59.021] <TB2> INFO: Expecting 41600 events.
[12:38:02.616] <TB2> INFO: 41600 events read in total (3004ms).
[12:38:02.616] <TB2> INFO: Test took 3852ms.
[12:38:02.618] <TB2> INFO: scanning low vcal = 20
[12:38:02.914] <TB2> INFO: Expecting 41600 events.
[12:38:06.513] <TB2> INFO: 41600 events read in total (3007ms).
[12:38:06.513] <TB2> INFO: Test took 3895ms.
[12:38:06.515] <TB2> INFO: scanning low vcal = 30
[12:38:06.809] <TB2> INFO: Expecting 41600 events.
[12:38:10.545] <TB2> INFO: 41600 events read in total (3145ms).
[12:38:10.546] <TB2> INFO: Test took 4030ms.
[12:38:10.549] <TB2> INFO: scanning low vcal = 40
[12:38:10.826] <TB2> INFO: Expecting 41600 events.
[12:38:14.809] <TB2> INFO: 41600 events read in total (3392ms).
[12:38:14.810] <TB2> INFO: Test took 4260ms.
[12:38:14.814] <TB2> INFO: scanning low vcal = 50
[12:38:15.091] <TB2> INFO: Expecting 41600 events.
[12:38:19.099] <TB2> INFO: 41600 events read in total (3416ms).
[12:38:19.100] <TB2> INFO: Test took 4286ms.
[12:38:19.104] <TB2> INFO: scanning low vcal = 60
[12:38:19.381] <TB2> INFO: Expecting 41600 events.
[12:38:23.367] <TB2> INFO: 41600 events read in total (3394ms).
[12:38:23.368] <TB2> INFO: Test took 4263ms.
[12:38:23.372] <TB2> INFO: scanning low vcal = 70
[12:38:23.647] <TB2> INFO: Expecting 41600 events.
[12:38:27.663] <TB2> INFO: 41600 events read in total (3424ms).
[12:38:27.664] <TB2> INFO: Test took 4292ms.
[12:38:27.667] <TB2> INFO: scanning low vcal = 80
[12:38:27.944] <TB2> INFO: Expecting 41600 events.
[12:38:31.967] <TB2> INFO: 41600 events read in total (3431ms).
[12:38:31.968] <TB2> INFO: Test took 4301ms.
[12:38:31.971] <TB2> INFO: scanning low vcal = 90
[12:38:32.248] <TB2> INFO: Expecting 41600 events.
[12:38:36.252] <TB2> INFO: 41600 events read in total (3412ms).
[12:38:36.253] <TB2> INFO: Test took 4282ms.
[12:38:36.259] <TB2> INFO: scanning low vcal = 100
[12:38:36.534] <TB2> INFO: Expecting 41600 events.
[12:38:40.537] <TB2> INFO: 41600 events read in total (3411ms).
[12:38:40.538] <TB2> INFO: Test took 4279ms.
[12:38:40.541] <TB2> INFO: scanning low vcal = 110
[12:38:40.818] <TB2> INFO: Expecting 41600 events.
[12:38:44.804] <TB2> INFO: 41600 events read in total (3394ms).
[12:38:44.805] <TB2> INFO: Test took 4264ms.
[12:38:44.808] <TB2> INFO: scanning low vcal = 120
[12:38:45.085] <TB2> INFO: Expecting 41600 events.
[12:38:49.066] <TB2> INFO: 41600 events read in total (3389ms).
[12:38:49.067] <TB2> INFO: Test took 4259ms.
[12:38:49.071] <TB2> INFO: scanning low vcal = 130
[12:38:49.347] <TB2> INFO: Expecting 41600 events.
[12:38:53.380] <TB2> INFO: 41600 events read in total (3441ms).
[12:38:53.381] <TB2> INFO: Test took 4310ms.
[12:38:53.385] <TB2> INFO: scanning low vcal = 140
[12:38:53.662] <TB2> INFO: Expecting 41600 events.
[12:38:57.679] <TB2> INFO: 41600 events read in total (3425ms).
[12:38:57.680] <TB2> INFO: Test took 4295ms.
[12:38:57.683] <TB2> INFO: scanning low vcal = 150
[12:38:57.960] <TB2> INFO: Expecting 41600 events.
[12:39:01.928] <TB2> INFO: 41600 events read in total (3376ms).
[12:39:01.929] <TB2> INFO: Test took 4246ms.
[12:39:01.932] <TB2> INFO: scanning low vcal = 160
[12:39:02.210] <TB2> INFO: Expecting 41600 events.
[12:39:06.205] <TB2> INFO: 41600 events read in total (3404ms).
[12:39:06.206] <TB2> INFO: Test took 4274ms.
[12:39:06.209] <TB2> INFO: scanning low vcal = 170
[12:39:06.487] <TB2> INFO: Expecting 41600 events.
[12:39:10.531] <TB2> INFO: 41600 events read in total (3453ms).
[12:39:10.532] <TB2> INFO: Test took 4323ms.
[12:39:10.538] <TB2> INFO: scanning low vcal = 180
[12:39:10.813] <TB2> INFO: Expecting 41600 events.
[12:39:14.803] <TB2> INFO: 41600 events read in total (3398ms).
[12:39:14.804] <TB2> INFO: Test took 4266ms.
[12:39:14.807] <TB2> INFO: scanning low vcal = 190
[12:39:15.084] <TB2> INFO: Expecting 41600 events.
[12:39:19.078] <TB2> INFO: 41600 events read in total (3402ms).
[12:39:19.080] <TB2> INFO: Test took 4273ms.
[12:39:19.084] <TB2> INFO: scanning low vcal = 200
[12:39:19.361] <TB2> INFO: Expecting 41600 events.
[12:39:23.365] <TB2> INFO: 41600 events read in total (3413ms).
[12:39:23.366] <TB2> INFO: Test took 4282ms.
[12:39:23.369] <TB2> INFO: scanning low vcal = 210
[12:39:23.647] <TB2> INFO: Expecting 41600 events.
[12:39:27.645] <TB2> INFO: 41600 events read in total (3406ms).
[12:39:27.646] <TB2> INFO: Test took 4277ms.
[12:39:27.649] <TB2> INFO: scanning low vcal = 220
[12:39:27.929] <TB2> INFO: Expecting 41600 events.
[12:39:31.921] <TB2> INFO: 41600 events read in total (3401ms).
[12:39:31.922] <TB2> INFO: Test took 4273ms.
[12:39:31.926] <TB2> INFO: scanning low vcal = 230
[12:39:32.202] <TB2> INFO: Expecting 41600 events.
[12:39:36.185] <TB2> INFO: 41600 events read in total (3391ms).
[12:39:36.186] <TB2> INFO: Test took 4260ms.
[12:39:36.189] <TB2> INFO: scanning low vcal = 240
[12:39:36.466] <TB2> INFO: Expecting 41600 events.
[12:39:40.414] <TB2> INFO: 41600 events read in total (3356ms).
[12:39:40.415] <TB2> INFO: Test took 4226ms.
[12:39:40.419] <TB2> INFO: scanning low vcal = 250
[12:39:40.695] <TB2> INFO: Expecting 41600 events.
[12:39:44.694] <TB2> INFO: 41600 events read in total (3407ms).
[12:39:44.694] <TB2> INFO: Test took 4276ms.
[12:39:44.699] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[12:39:44.974] <TB2> INFO: Expecting 41600 events.
[12:39:48.978] <TB2> INFO: 41600 events read in total (3412ms).
[12:39:48.979] <TB2> INFO: Test took 4281ms.
[12:39:48.983] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[12:39:49.307] <TB2> INFO: Expecting 41600 events.
[12:39:53.279] <TB2> INFO: 41600 events read in total (3380ms).
[12:39:53.279] <TB2> INFO: Test took 4296ms.
[12:39:53.283] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[12:39:53.559] <TB2> INFO: Expecting 41600 events.
[12:39:57.547] <TB2> INFO: 41600 events read in total (3396ms).
[12:39:57.547] <TB2> INFO: Test took 4264ms.
[12:39:57.553] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[12:39:57.886] <TB2> INFO: Expecting 41600 events.
[12:40:01.877] <TB2> INFO: 41600 events read in total (3399ms).
[12:40:01.878] <TB2> INFO: Test took 4325ms.
[12:40:01.881] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:40:02.157] <TB2> INFO: Expecting 41600 events.
[12:40:06.133] <TB2> INFO: 41600 events read in total (3384ms).
[12:40:06.134] <TB2> INFO: Test took 4252ms.
[12:40:06.829] <TB2> INFO: PixTestGainPedestal::measure() done
[12:40:55.130] <TB2> INFO: PixTestGainPedestal::fit() done
[12:40:55.130] <TB2> INFO: non-linearity mean: 0.896 0.975 0.940 0.959 0.912 0.945 0.953 0.927 0.931 0.987 0.971 0.938 1.011 0.982 0.943 0.934
[12:40:55.130] <TB2> INFO: non-linearity RMS: 0.159 0.007 0.069 0.021 0.098 0.033 0.040 0.141 0.092 0.002 0.013 0.066 0.193 0.003 0.084 0.064
[12:40:55.130] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[12:40:55.143] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[12:40:55.156] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[12:40:55.170] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[12:40:55.183] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[12:40:55.196] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[12:40:55.209] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[12:40:55.222] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[12:40:55.235] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[12:40:55.248] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[12:40:55.262] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[12:40:55.275] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[12:40:55.288] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[12:40:55.301] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[12:40:55.314] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[12:40:55.327] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[12:40:55.341] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 176 seconds
[12:40:55.341] <TB2> INFO: Decoding statistics:
[12:40:55.341] <TB2> INFO: General information:
[12:40:55.341] <TB2> INFO: 16bit words read: 3327386
[12:40:55.341] <TB2> INFO: valid events total: 332800
[12:40:55.341] <TB2> INFO: empty events: 0
[12:40:55.341] <TB2> INFO: valid events with pixels: 332800
[12:40:55.341] <TB2> INFO: valid pixel hits: 665293
[12:40:55.341] <TB2> INFO: Event errors: 0
[12:40:55.341] <TB2> INFO: start marker: 0
[12:40:55.341] <TB2> INFO: stop marker: 0
[12:40:55.341] <TB2> INFO: overflow: 0
[12:40:55.341] <TB2> INFO: invalid 5bit words: 0
[12:40:55.341] <TB2> INFO: invalid XOR eye diagram: 0
[12:40:55.341] <TB2> INFO: frame (failed synchr.): 0
[12:40:55.341] <TB2> INFO: idle data (no TBM trl): 0
[12:40:55.341] <TB2> INFO: no data (only TBM hdr): 0
[12:40:55.341] <TB2> INFO: TBM errors: 0
[12:40:55.341] <TB2> INFO: flawed TBM headers: 0
[12:40:55.341] <TB2> INFO: flawed TBM trailers: 0
[12:40:55.341] <TB2> INFO: event ID mismatches: 0
[12:40:55.341] <TB2> INFO: ROC errors: 0
[12:40:55.341] <TB2> INFO: missing ROC header(s): 0
[12:40:55.341] <TB2> INFO: misplaced readback start: 0
[12:40:55.341] <TB2> INFO: Pixel decoding errors: 0
[12:40:55.341] <TB2> INFO: pixel data incomplete: 0
[12:40:55.341] <TB2> INFO: pixel address: 0
[12:40:55.341] <TB2> INFO: pulse height fill bit: 0
[12:40:55.341] <TB2> INFO: buffer corruption: 0
[12:40:55.359] <TB2> INFO: Decoding statistics:
[12:40:55.359] <TB2> INFO: General information:
[12:40:55.359] <TB2> INFO: 16bit words read: 3456804
[12:40:55.359] <TB2> INFO: valid events total: 353536
[12:40:55.359] <TB2> INFO: empty events: 18235
[12:40:55.359] <TB2> INFO: valid events with pixels: 335301
[12:40:55.359] <TB2> INFO: valid pixel hits: 667794
[12:40:55.359] <TB2> INFO: Event errors: 0
[12:40:55.359] <TB2> INFO: start marker: 0
[12:40:55.359] <TB2> INFO: stop marker: 0
[12:40:55.359] <TB2> INFO: overflow: 0
[12:40:55.360] <TB2> INFO: invalid 5bit words: 0
[12:40:55.360] <TB2> INFO: invalid XOR eye diagram: 0
[12:40:55.360] <TB2> INFO: frame (failed synchr.): 0
[12:40:55.360] <TB2> INFO: idle data (no TBM trl): 0
[12:40:55.360] <TB2> INFO: no data (only TBM hdr): 0
[12:40:55.360] <TB2> INFO: TBM errors: 0
[12:40:55.360] <TB2> INFO: flawed TBM headers: 0
[12:40:55.360] <TB2> INFO: flawed TBM trailers: 0
[12:40:55.360] <TB2> INFO: event ID mismatches: 0
[12:40:55.360] <TB2> INFO: ROC errors: 0
[12:40:55.360] <TB2> INFO: missing ROC header(s): 0
[12:40:55.360] <TB2> INFO: misplaced readback start: 0
[12:40:55.360] <TB2> INFO: Pixel decoding errors: 0
[12:40:55.360] <TB2> INFO: pixel data incomplete: 0
[12:40:55.360] <TB2> INFO: pixel address: 0
[12:40:55.360] <TB2> INFO: pulse height fill bit: 0
[12:40:55.360] <TB2> INFO: buffer corruption: 0
[12:40:55.360] <TB2> INFO: enter test to run
[12:40:55.360] <TB2> INFO: test: exit no parameter change
[12:40:55.488] <TB2> QUIET: Connection to board 149 closed.
[12:40:55.489] <TB2> INFO: pXar: this is the end, my friend