[12:50:51.217] <TB2> INFO: *** Welcome to pxar ***
[12:50:51.217] <TB2> INFO: *** Today: 2016/10/31
[12:50:51.225] <TB2> INFO: *** Version: c8ba-dirty
[12:50:51.225] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:50:51.225] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:50:51.226] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//defaultMaskFile.dat
[12:50:51.226] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters_C15.dat
[12:50:51.294] <TB2> INFO: clk: 4
[12:50:51.294] <TB2> INFO: ctr: 4
[12:50:51.294] <TB2> INFO: sda: 19
[12:50:51.294] <TB2> INFO: tin: 9
[12:50:51.294] <TB2> INFO: level: 15
[12:50:51.294] <TB2> INFO: triggerdelay: 0
[12:50:51.294] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[12:50:51.294] <TB2> INFO: Log level: INFO
[12:50:51.302] <TB2> INFO: Found DTB DTB_WWXUD2
[12:50:51.309] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[12:50:51.311] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[12:50:51.313] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[12:50:52.808] <TB2> INFO: DUT info:
[12:50:52.808] <TB2> INFO: The DUT currently contains the following objects:
[12:50:52.808] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[12:50:52.808] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:50:52.808] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:50:52.808] <TB2> INFO: TBM Core alpha (2): 7 registers set
[12:50:52.808] <TB2> INFO: TBM Core beta (3): 7 registers set
[12:50:52.808] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[12:50:52.808] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:52.808] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:53.209] <TB2> INFO: enter 'restricted' command line mode
[12:50:53.209] <TB2> INFO: enter test to run
[12:50:53.209] <TB2> INFO: test: pretest no parameter change
[12:50:53.209] <TB2> INFO: running: pretest
[12:50:53.215] <TB2> INFO: ######################################################################
[12:50:53.215] <TB2> INFO: PixTestPretest::doTest()
[12:50:53.215] <TB2> INFO: ######################################################################
[12:50:53.217] <TB2> INFO: ----------------------------------------------------------------------
[12:50:53.217] <TB2> INFO: PixTestPretest::programROC()
[12:50:53.217] <TB2> INFO: ----------------------------------------------------------------------
[12:51:11.231] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:51:11.231] <TB2> INFO: IA differences per ROC: 18.5 19.3 20.9 19.3 17.7 18.5 19.3 16.9 19.3 18.5 19.3 19.3 16.9 20.1 18.5 18.5
[12:51:11.301] <TB2> INFO: ----------------------------------------------------------------------
[12:51:11.301] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:51:11.301] <TB2> INFO: ----------------------------------------------------------------------
[12:51:32.602] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 386.7 mA = 24.1687 mA/ROC
[12:51:32.602] <TB2> INFO: i(loss) [mA/ROC]: 20.1 20.1 20.1 19.3 18.5 19.3 19.3 20.1 19.3 19.3 20.1 19.3 19.3 19.3 19.3 19.3
[12:51:32.632] <TB2> INFO: ----------------------------------------------------------------------
[12:51:32.632] <TB2> INFO: PixTestPretest::findTiming()
[12:51:32.632] <TB2> INFO: ----------------------------------------------------------------------
[12:51:32.632] <TB2> INFO: PixTestCmd::init()

[12:52:04.676] <TB2> INFO: TBM phases: 160MHz: 7, 400MHz: 3, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:52:04.676] <TB2> INFO: (success/tries = 100/100), width = 4
[12:52:06.180] <TB2> INFO: ----------------------------------------------------------------------
[12:52:06.180] <TB2> INFO: PixTestPretest::findWorkingPixel()
[12:52:06.180] <TB2> INFO: ----------------------------------------------------------------------
[12:52:06.273] <TB2> INFO: Expecting 231680 events.
[12:52:16.243] <TB2> INFO: 231680 events read in total (9378ms).
[12:52:16.253] <TB2> INFO: Test took 10070ms.
[12:52:16.497] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:52:16.527] <TB2> INFO: ----------------------------------------------------------------------
[12:52:16.527] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[12:52:16.527] <TB2> INFO: ----------------------------------------------------------------------
[12:52:16.623] <TB2> INFO: Expecting 231680 events.
[12:52:26.708] <TB2> INFO: 231680 events read in total (9494ms).
[12:52:26.719] <TB2> INFO: Test took 10186ms.
[12:52:26.986] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[12:52:26.986] <TB2> INFO: CalDel: 78 101 109 111 110 101 88 107 102 114 76 112 91 83 106 96
[12:52:26.986] <TB2> INFO: VthrComp: 53 51 53 51 51 51 51 51 51 51 51 51 53 51 51 51
[12:52:26.989] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C0.dat
[12:52:26.989] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C1.dat
[12:52:26.990] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C2.dat
[12:52:26.990] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C3.dat
[12:52:26.990] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C4.dat
[12:52:26.990] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C5.dat
[12:52:26.990] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C6.dat
[12:52:26.990] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C7.dat
[12:52:26.990] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C8.dat
[12:52:26.991] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C9.dat
[12:52:26.991] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C10.dat
[12:52:26.991] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C11.dat
[12:52:26.991] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C12.dat
[12:52:26.991] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C13.dat
[12:52:26.991] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C14.dat
[12:52:26.991] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:52:26.991] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[12:52:26.992] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[12:52:26.992] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[12:52:26.992] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:52:26.992] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[12:52:27.048] <TB2> INFO: enter test to run
[12:52:27.048] <TB2> INFO: test: fulltest no parameter change
[12:52:27.048] <TB2> INFO: running: fulltest
[12:52:27.048] <TB2> INFO: ######################################################################
[12:52:27.048] <TB2> INFO: PixTestFullTest::doTest()
[12:52:27.048] <TB2> INFO: ######################################################################
[12:52:27.050] <TB2> INFO: ######################################################################
[12:52:27.050] <TB2> INFO: PixTestAlive::doTest()
[12:52:27.050] <TB2> INFO: ######################################################################
[12:52:27.052] <TB2> INFO: ----------------------------------------------------------------------
[12:52:27.052] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:52:27.052] <TB2> INFO: ----------------------------------------------------------------------
[12:52:27.338] <TB2> INFO: Expecting 41600 events.
[12:52:30.959] <TB2> INFO: 41600 events read in total (3029ms).
[12:52:30.960] <TB2> INFO: Test took 3907ms.
[12:52:31.196] <TB2> INFO: PixTestAlive::aliveTest() done
[12:52:31.197] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:52:31.198] <TB2> INFO: ----------------------------------------------------------------------
[12:52:31.198] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:52:31.198] <TB2> INFO: ----------------------------------------------------------------------
[12:52:31.443] <TB2> INFO: Expecting 41600 events.
[12:52:34.525] <TB2> INFO: 41600 events read in total (2490ms).
[12:52:34.526] <TB2> INFO: Test took 3325ms.
[12:52:34.526] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:52:34.768] <TB2> INFO: PixTestAlive::maskTest() done
[12:52:34.768] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:52:34.769] <TB2> INFO: ----------------------------------------------------------------------
[12:52:34.769] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:52:34.770] <TB2> INFO: ----------------------------------------------------------------------
[12:52:35.012] <TB2> INFO: Expecting 41600 events.
[12:52:38.543] <TB2> INFO: 41600 events read in total (2938ms).
[12:52:38.544] <TB2> INFO: Test took 3772ms.
[12:52:38.780] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[12:52:38.780] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:52:38.780] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:52:38.780] <TB2> INFO: Decoding statistics:
[12:52:38.780] <TB2> INFO: General information:
[12:52:38.780] <TB2> INFO: 16bit words read: 0
[12:52:38.780] <TB2> INFO: valid events total: 0
[12:52:38.780] <TB2> INFO: empty events: 0
[12:52:38.780] <TB2> INFO: valid events with pixels: 0
[12:52:38.780] <TB2> INFO: valid pixel hits: 0
[12:52:38.780] <TB2> INFO: Event errors: 0
[12:52:38.780] <TB2> INFO: start marker: 0
[12:52:38.780] <TB2> INFO: stop marker: 0
[12:52:38.780] <TB2> INFO: overflow: 0
[12:52:38.781] <TB2> INFO: invalid 5bit words: 0
[12:52:38.781] <TB2> INFO: invalid XOR eye diagram: 0
[12:52:38.781] <TB2> INFO: frame (failed synchr.): 0
[12:52:38.781] <TB2> INFO: idle data (no TBM trl): 0
[12:52:38.781] <TB2> INFO: no data (only TBM hdr): 0
[12:52:38.781] <TB2> INFO: TBM errors: 0
[12:52:38.781] <TB2> INFO: flawed TBM headers: 0
[12:52:38.781] <TB2> INFO: flawed TBM trailers: 0
[12:52:38.781] <TB2> INFO: event ID mismatches: 0
[12:52:38.781] <TB2> INFO: ROC errors: 0
[12:52:38.781] <TB2> INFO: missing ROC header(s): 0
[12:52:38.781] <TB2> INFO: misplaced readback start: 0
[12:52:38.781] <TB2> INFO: Pixel decoding errors: 0
[12:52:38.781] <TB2> INFO: pixel data incomplete: 0
[12:52:38.781] <TB2> INFO: pixel address: 0
[12:52:38.781] <TB2> INFO: pulse height fill bit: 0
[12:52:38.781] <TB2> INFO: buffer corruption: 0
[12:52:38.792] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:52:38.792] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[12:52:38.792] <TB2> INFO: ######################################################################
[12:52:38.792] <TB2> INFO: PixTestReadback::doTest()
[12:52:38.792] <TB2> INFO: ######################################################################
[12:52:38.792] <TB2> INFO: ----------------------------------------------------------------------
[12:52:38.792] <TB2> INFO: PixTestReadback::CalibrateVd()
[12:52:38.792] <TB2> INFO: ----------------------------------------------------------------------
[12:52:48.770] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:52:48.770] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:52:48.770] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:52:48.770] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:52:48.770] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:52:48.770] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:52:48.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:52:48.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:52:48.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:52:48.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:52:48.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:52:48.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:52:48.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:52:48.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:52:48.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:52:48.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:52:48.802] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:52:48.802] <TB2> INFO: ----------------------------------------------------------------------
[12:52:48.802] <TB2> INFO: PixTestReadback::CalibrateVa()
[12:52:48.802] <TB2> INFO: ----------------------------------------------------------------------
[12:52:58.737] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:52:58.738] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:52:58.771] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:52:58.771] <TB2> INFO: ----------------------------------------------------------------------
[12:52:58.771] <TB2> INFO: PixTestReadback::readbackVbg()
[12:52:58.771] <TB2> INFO: ----------------------------------------------------------------------
[12:53:06.445] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:53:06.445] <TB2> INFO: ----------------------------------------------------------------------
[12:53:06.445] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[12:53:06.445] <TB2> INFO: ----------------------------------------------------------------------
[12:53:06.445] <TB2> INFO: Vbg will be calibrated using Vd calibration
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 156.1calibrated Vbg = 1.19949 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 155.1calibrated Vbg = 1.1992 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 147.1calibrated Vbg = 1.19293 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 151.1calibrated Vbg = 1.19261 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 152.5calibrated Vbg = 1.19596 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 154.1calibrated Vbg = 1.20358 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 151calibrated Vbg = 1.20916 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 159calibrated Vbg = 1.20396 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 151.7calibrated Vbg = 1.20071 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 162.8calibrated Vbg = 1.1931 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 153.6calibrated Vbg = 1.18519 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 161.3calibrated Vbg = 1.1862 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 152.5calibrated Vbg = 1.18779 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152.3calibrated Vbg = 1.19569 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 150.4calibrated Vbg = 1.19627 :::*/*/*/*/
[12:53:06.445] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 153.4calibrated Vbg = 1.19845 :::*/*/*/*/
[12:53:06.448] <TB2> INFO: ----------------------------------------------------------------------
[12:53:06.448] <TB2> INFO: PixTestReadback::CalibrateIa()
[12:53:06.448] <TB2> INFO: ----------------------------------------------------------------------
[12:55:47.239] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:55:47.239] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:55:47.239] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:55:47.239] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:55:47.239] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:55:47.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:55:47.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:55:47.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:55:47.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:55:47.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:55:47.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:55:47.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:55:47.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:55:47.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:55:47.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:55:47.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:55:47.271] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:55:47.272] <TB2> INFO: PixTestReadback::doTest() done
[12:55:47.272] <TB2> INFO: Decoding statistics:
[12:55:47.272] <TB2> INFO: General information:
[12:55:47.272] <TB2> INFO: 16bit words read: 1536
[12:55:47.272] <TB2> INFO: valid events total: 256
[12:55:47.272] <TB2> INFO: empty events: 256
[12:55:47.272] <TB2> INFO: valid events with pixels: 0
[12:55:47.272] <TB2> INFO: valid pixel hits: 0
[12:55:47.272] <TB2> INFO: Event errors: 0
[12:55:47.272] <TB2> INFO: start marker: 0
[12:55:47.272] <TB2> INFO: stop marker: 0
[12:55:47.272] <TB2> INFO: overflow: 0
[12:55:47.272] <TB2> INFO: invalid 5bit words: 0
[12:55:47.272] <TB2> INFO: invalid XOR eye diagram: 0
[12:55:47.272] <TB2> INFO: frame (failed synchr.): 0
[12:55:47.272] <TB2> INFO: idle data (no TBM trl): 0
[12:55:47.272] <TB2> INFO: no data (only TBM hdr): 0
[12:55:47.272] <TB2> INFO: TBM errors: 0
[12:55:47.272] <TB2> INFO: flawed TBM headers: 0
[12:55:47.272] <TB2> INFO: flawed TBM trailers: 0
[12:55:47.272] <TB2> INFO: event ID mismatches: 0
[12:55:47.272] <TB2> INFO: ROC errors: 0
[12:55:47.272] <TB2> INFO: missing ROC header(s): 0
[12:55:47.272] <TB2> INFO: misplaced readback start: 0
[12:55:47.272] <TB2> INFO: Pixel decoding errors: 0
[12:55:47.272] <TB2> INFO: pixel data incomplete: 0
[12:55:47.272] <TB2> INFO: pixel address: 0
[12:55:47.272] <TB2> INFO: pulse height fill bit: 0
[12:55:47.272] <TB2> INFO: buffer corruption: 0
[12:55:47.337] <TB2> INFO: ######################################################################
[12:55:47.337] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:55:47.337] <TB2> INFO: ######################################################################
[12:55:47.340] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:55:47.415] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:55:47.415] <TB2> INFO: run 1 of 1
[12:55:47.651] <TB2> INFO: Expecting 3120000 events.
[12:56:18.986] <TB2> INFO: 663140 events read in total (30740ms).











[12:56:49.351] <TB2> INFO: 1321710 events read in total (61105ms).





















[12:57:19.591] <TB2> INFO: 1976370 events read in total (91345ms).











[12:57:49.763] <TB2> INFO: 2631690 events read in total (121517ms).











[12:58:12.641] <TB2> INFO: 3120000 events read in total (144395ms).
[12:58:12.735] <TB2> INFO: Test took 145320ms.
[12:58:36.560] <TB2> INFO: PixTestBBMap::doTest() done, duration: 169 seconds
[12:58:36.560] <TB2> INFO: number of dead bumps (per ROC): 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:58:36.560] <TB2> INFO: separation cut (per ROC): 104 107 109 99 89 91 104 103 104 102 120 101 108 106 103 105
[12:58:36.560] <TB2> INFO: Decoding statistics:
[12:58:36.560] <TB2> INFO: General information:
[12:58:36.560] <TB2> INFO: 16bit words read: 0
[12:58:36.560] <TB2> INFO: valid events total: 0
[12:58:36.560] <TB2> INFO: empty events: 0
[12:58:36.560] <TB2> INFO: valid events with pixels: 0
[12:58:36.560] <TB2> INFO: valid pixel hits: 0
[12:58:36.560] <TB2> INFO: Event errors: 0
[12:58:36.560] <TB2> INFO: start marker: 0
[12:58:36.560] <TB2> INFO: stop marker: 0
[12:58:36.560] <TB2> INFO: overflow: 0
[12:58:36.560] <TB2> INFO: invalid 5bit words: 0
[12:58:36.560] <TB2> INFO: invalid XOR eye diagram: 0
[12:58:36.560] <TB2> INFO: frame (failed synchr.): 0
[12:58:36.560] <TB2> INFO: idle data (no TBM trl): 0
[12:58:36.560] <TB2> INFO: no data (only TBM hdr): 0
[12:58:36.560] <TB2> INFO: TBM errors: 0
[12:58:36.560] <TB2> INFO: flawed TBM headers: 0
[12:58:36.560] <TB2> INFO: flawed TBM trailers: 0
[12:58:36.560] <TB2> INFO: event ID mismatches: 0
[12:58:36.560] <TB2> INFO: ROC errors: 0
[12:58:36.560] <TB2> INFO: missing ROC header(s): 0
[12:58:36.560] <TB2> INFO: misplaced readback start: 0
[12:58:36.560] <TB2> INFO: Pixel decoding errors: 0
[12:58:36.560] <TB2> INFO: pixel data incomplete: 0
[12:58:36.560] <TB2> INFO: pixel address: 0
[12:58:36.560] <TB2> INFO: pulse height fill bit: 0
[12:58:36.560] <TB2> INFO: buffer corruption: 0
[12:58:36.599] <TB2> INFO: ######################################################################
[12:58:36.600] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:58:36.600] <TB2> INFO: ######################################################################
[12:58:36.600] <TB2> INFO: ----------------------------------------------------------------------
[12:58:36.600] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:58:36.600] <TB2> INFO: ----------------------------------------------------------------------
[12:58:36.600] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:58:36.613] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[12:58:36.613] <TB2> INFO: run 1 of 1
[12:58:36.864] <TB2> INFO: Expecting 36608000 events.
[12:59:00.313] <TB2> INFO: 689950 events read in total (22858ms).
[12:59:23.048] <TB2> INFO: 1362850 events read in total (45593ms).
[12:59:46.229] <TB2> INFO: 2035250 events read in total (68774ms).
[13:00:09.469] <TB2> INFO: 2707600 events read in total (92014ms).
[13:00:32.154] <TB2> INFO: 3379050 events read in total (114699ms).
[13:00:55.533] <TB2> INFO: 4050500 events read in total (138078ms).
[13:01:18.522] <TB2> INFO: 4721550 events read in total (161067ms).
[13:01:41.427] <TB2> INFO: 5391900 events read in total (183972ms).
[13:02:04.728] <TB2> INFO: 6062800 events read in total (207273ms).
[13:02:27.324] <TB2> INFO: 6733750 events read in total (229870ms).
[13:02:50.544] <TB2> INFO: 7403450 events read in total (253089ms).
[13:03:13.429] <TB2> INFO: 8073650 events read in total (275974ms).
[13:03:36.298] <TB2> INFO: 8744100 events read in total (298843ms).
[13:03:59.104] <TB2> INFO: 9415050 events read in total (321649ms).
[13:04:22.031] <TB2> INFO: 10085350 events read in total (344576ms).
[13:04:45.274] <TB2> INFO: 10757250 events read in total (367819ms).
[13:05:08.031] <TB2> INFO: 11427650 events read in total (390576ms).
[13:05:30.000] <TB2> INFO: 12096800 events read in total (413545ms).
[13:05:53.790] <TB2> INFO: 12765250 events read in total (436335ms).
[13:06:17.012] <TB2> INFO: 13432900 events read in total (459557ms).
[13:06:40.120] <TB2> INFO: 14099300 events read in total (482665ms).
[13:07:02.754] <TB2> INFO: 14765650 events read in total (505299ms).
[13:07:25.454] <TB2> INFO: 15431700 events read in total (527999ms).
[13:07:48.120] <TB2> INFO: 16097350 events read in total (550665ms).
[13:08:11.241] <TB2> INFO: 16763100 events read in total (573786ms).
[13:08:34.375] <TB2> INFO: 17430300 events read in total (596920ms).
[13:08:57.143] <TB2> INFO: 18095400 events read in total (619688ms).
[13:09:20.150] <TB2> INFO: 18759800 events read in total (642695ms).
[13:09:42.759] <TB2> INFO: 19424100 events read in total (665304ms).
[13:10:05.393] <TB2> INFO: 20087050 events read in total (687938ms).
[13:10:28.299] <TB2> INFO: 20749100 events read in total (710844ms).
[13:10:51.300] <TB2> INFO: 21409800 events read in total (733845ms).
[13:11:14.056] <TB2> INFO: 22072700 events read in total (756601ms).
[13:11:36.717] <TB2> INFO: 22733400 events read in total (779262ms).
[13:11:59.618] <TB2> INFO: 23395350 events read in total (802163ms).
[13:12:22.401] <TB2> INFO: 24056350 events read in total (824946ms).
[13:12:45.245] <TB2> INFO: 24718000 events read in total (847790ms).
[13:13:08.038] <TB2> INFO: 25378650 events read in total (870583ms).
[13:13:30.926] <TB2> INFO: 26040200 events read in total (893471ms).
[13:13:53.837] <TB2> INFO: 26700600 events read in total (916382ms).
[13:14:16.878] <TB2> INFO: 27361350 events read in total (939423ms).
[13:14:39.481] <TB2> INFO: 28020500 events read in total (962026ms).
[13:15:02.226] <TB2> INFO: 28678900 events read in total (984771ms).
[13:15:24.601] <TB2> INFO: 29338100 events read in total (1007146ms).
[13:15:47.243] <TB2> INFO: 29997200 events read in total (1029788ms).
[13:16:10.024] <TB2> INFO: 30655900 events read in total (1052569ms).
[13:16:32.943] <TB2> INFO: 31314150 events read in total (1075488ms).
[13:16:55.559] <TB2> INFO: 31971750 events read in total (1098104ms).
[13:17:18.019] <TB2> INFO: 32629700 events read in total (1120564ms).
[13:17:40.651] <TB2> INFO: 33288300 events read in total (1143196ms).
[13:18:03.844] <TB2> INFO: 33948650 events read in total (1166389ms).
[13:18:26.720] <TB2> INFO: 34609000 events read in total (1189265ms).
[13:18:49.488] <TB2> INFO: 35268000 events read in total (1212033ms).
[13:19:12.282] <TB2> INFO: 35928550 events read in total (1234827ms).
[13:19:35.739] <TB2> INFO: 36599400 events read in total (1258284ms).
[13:19:36.451] <TB2> INFO: 36608000 events read in total (1258996ms).
[13:19:36.527] <TB2> INFO: Test took 1259913ms.
[13:19:36.990] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:19:39.278] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:19:41.320] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:19:43.100] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:19:44.958] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:19:46.393] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:19:47.835] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:19:49.253] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:19:50.693] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:19:52.092] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:19:53.702] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:19:55.512] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:19:57.396] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:19:59.248] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:20:01.401] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:20:03.366] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:20:05.467] <TB2> INFO: PixTestScurves::scurves() done
[13:20:05.467] <TB2> INFO: Vcal mean: 124.99 121.03 127.94 117.39 114.56 111.49 114.27 119.56 122.08 127.30 121.51 121.16 130.86 117.40 118.89 107.82
[13:20:05.467] <TB2> INFO: Vcal RMS: 5.46 6.14 8.05 5.54 5.07 5.15 4.76 5.79 5.56 5.66 6.23 5.92 6.20 5.18 7.69 4.91
[13:20:05.467] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1288 seconds
[13:20:05.467] <TB2> INFO: Decoding statistics:
[13:20:05.467] <TB2> INFO: General information:
[13:20:05.467] <TB2> INFO: 16bit words read: 0
[13:20:05.467] <TB2> INFO: valid events total: 0
[13:20:05.467] <TB2> INFO: empty events: 0
[13:20:05.467] <TB2> INFO: valid events with pixels: 0
[13:20:05.467] <TB2> INFO: valid pixel hits: 0
[13:20:05.467] <TB2> INFO: Event errors: 0
[13:20:05.467] <TB2> INFO: start marker: 0
[13:20:05.467] <TB2> INFO: stop marker: 0
[13:20:05.467] <TB2> INFO: overflow: 0
[13:20:05.467] <TB2> INFO: invalid 5bit words: 0
[13:20:05.467] <TB2> INFO: invalid XOR eye diagram: 0
[13:20:05.467] <TB2> INFO: frame (failed synchr.): 0
[13:20:05.467] <TB2> INFO: idle data (no TBM trl): 0
[13:20:05.467] <TB2> INFO: no data (only TBM hdr): 0
[13:20:05.467] <TB2> INFO: TBM errors: 0
[13:20:05.467] <TB2> INFO: flawed TBM headers: 0
[13:20:05.467] <TB2> INFO: flawed TBM trailers: 0
[13:20:05.467] <TB2> INFO: event ID mismatches: 0
[13:20:05.467] <TB2> INFO: ROC errors: 0
[13:20:05.467] <TB2> INFO: missing ROC header(s): 0
[13:20:05.467] <TB2> INFO: misplaced readback start: 0
[13:20:05.467] <TB2> INFO: Pixel decoding errors: 0
[13:20:05.467] <TB2> INFO: pixel data incomplete: 0
[13:20:05.467] <TB2> INFO: pixel address: 0
[13:20:05.467] <TB2> INFO: pulse height fill bit: 0
[13:20:05.467] <TB2> INFO: buffer corruption: 0
[13:20:05.548] <TB2> INFO: ######################################################################
[13:20:05.548] <TB2> INFO: PixTestTrim::doTest()
[13:20:05.548] <TB2> INFO: ######################################################################
[13:20:05.549] <TB2> INFO: ----------------------------------------------------------------------
[13:20:05.549] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[13:20:05.549] <TB2> INFO: ----------------------------------------------------------------------
[13:20:05.612] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:20:05.612] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:20:05.626] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:20:05.626] <TB2> INFO: run 1 of 1
[13:20:05.912] <TB2> INFO: Expecting 5025280 events.
[13:20:37.162] <TB2> INFO: 827504 events read in total (30649ms).
[13:21:07.415] <TB2> INFO: 1652808 events read in total (60902ms).
[13:21:37.884] <TB2> INFO: 2475280 events read in total (91372ms).
[13:22:08.311] <TB2> INFO: 3295696 events read in total (121798ms).
[13:22:38.633] <TB2> INFO: 4113512 events read in total (152121ms).
[13:23:09.522] <TB2> INFO: 4929024 events read in total (183009ms).
[13:23:13.424] <TB2> INFO: 5025280 events read in total (186911ms).
[13:23:13.487] <TB2> INFO: Test took 187861ms.
[13:23:30.577] <TB2> INFO: ROC 0 VthrComp = 134
[13:23:30.577] <TB2> INFO: ROC 1 VthrComp = 124
[13:23:30.577] <TB2> INFO: ROC 2 VthrComp = 124
[13:23:30.578] <TB2> INFO: ROC 3 VthrComp = 117
[13:23:30.578] <TB2> INFO: ROC 4 VthrComp = 109
[13:23:30.578] <TB2> INFO: ROC 5 VthrComp = 111
[13:23:30.578] <TB2> INFO: ROC 6 VthrComp = 120
[13:23:30.578] <TB2> INFO: ROC 7 VthrComp = 121
[13:23:30.580] <TB2> INFO: ROC 8 VthrComp = 123
[13:23:30.581] <TB2> INFO: ROC 9 VthrComp = 121
[13:23:30.581] <TB2> INFO: ROC 10 VthrComp = 128
[13:23:30.581] <TB2> INFO: ROC 11 VthrComp = 117
[13:23:30.581] <TB2> INFO: ROC 12 VthrComp = 131
[13:23:30.581] <TB2> INFO: ROC 13 VthrComp = 123
[13:23:30.581] <TB2> INFO: ROC 14 VthrComp = 115
[13:23:30.581] <TB2> INFO: ROC 15 VthrComp = 111
[13:23:30.828] <TB2> INFO: Expecting 41600 events.
[13:23:34.286] <TB2> INFO: 41600 events read in total (2866ms).
[13:23:34.286] <TB2> INFO: Test took 3702ms.
[13:23:34.296] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:23:34.296] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:23:34.308] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:23:34.308] <TB2> INFO: run 1 of 1
[13:23:34.587] <TB2> INFO: Expecting 5025280 events.
[13:24:01.375] <TB2> INFO: 591328 events read in total (26195ms).
[13:24:28.025] <TB2> INFO: 1182960 events read in total (52845ms).
[13:24:54.218] <TB2> INFO: 1775344 events read in total (79038ms).
[13:25:20.234] <TB2> INFO: 2367552 events read in total (105054ms).
[13:25:46.045] <TB2> INFO: 2957168 events read in total (130865ms).
[13:26:11.408] <TB2> INFO: 3545384 events read in total (156228ms).
[13:26:37.302] <TB2> INFO: 4132464 events read in total (182122ms).
[13:27:03.961] <TB2> INFO: 4719112 events read in total (208781ms).
[13:27:18.119] <TB2> INFO: 5025280 events read in total (222939ms).
[13:27:18.305] <TB2> INFO: Test took 223997ms.
[13:27:49.426] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 60.9608 for pixel 3/35 mean/min/max = 46.6815/32.3701/60.9928
[13:27:49.426] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 63.5357 for pixel 0/10 mean/min/max = 47.9951/32.1151/63.8751
[13:27:49.427] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 70.1731 for pixel 39/4 mean/min/max = 50.2713/30.2458/70.2969
[13:27:49.427] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.1554 for pixel 10/3 mean/min/max = 46.3867/32.5938/60.1796
[13:27:49.428] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 64.9453 for pixel 6/45 mean/min/max = 49.9062/34.7324/65.08
[13:27:49.428] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 63.1934 for pixel 0/79 mean/min/max = 48.465/33.6678/63.2621
[13:27:49.429] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 61.028 for pixel 0/8 mean/min/max = 46.6949/32.3593/61.0305
[13:27:49.430] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 63.8622 for pixel 51/1 mean/min/max = 48.4878/33.0802/63.8954
[13:27:49.430] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 60.3238 for pixel 42/2 mean/min/max = 46.5915/32.3123/60.8707
[13:27:49.431] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 64.7608 for pixel 43/4 mean/min/max = 48.8683/32.9234/64.8132
[13:27:49.431] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 61.0832 for pixel 6/61 mean/min/max = 47.4001/33.5766/61.2235
[13:27:49.432] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 63.7451 for pixel 25/1 mean/min/max = 48.2248/32.5576/63.892
[13:27:49.432] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 63.5052 for pixel 0/17 mean/min/max = 48.9636/34.395/63.5322
[13:27:49.433] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 57.2582 for pixel 38/9 mean/min/max = 45.2286/33.1516/57.3056
[13:27:49.433] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 67.9054 for pixel 0/10 mean/min/max = 49.4478/30.2036/68.6921
[13:27:49.434] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 60.9426 for pixel 0/0 mean/min/max = 47.8586/34.5567/61.1604
[13:27:49.434] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:27:49.523] <TB2> INFO: Expecting 411648 events.
[13:27:59.062] <TB2> INFO: 411648 events read in total (8947ms).
[13:27:59.070] <TB2> INFO: Expecting 411648 events.
[13:28:08.435] <TB2> INFO: 411648 events read in total (8961ms).
[13:28:08.449] <TB2> INFO: Expecting 411648 events.
[13:28:17.720] <TB2> INFO: 411648 events read in total (8868ms).
[13:28:17.738] <TB2> INFO: Expecting 411648 events.
[13:28:27.005] <TB2> INFO: 411648 events read in total (8864ms).
[13:28:27.024] <TB2> INFO: Expecting 411648 events.
[13:28:36.256] <TB2> INFO: 411648 events read in total (8829ms).
[13:28:36.279] <TB2> INFO: Expecting 411648 events.
[13:28:45.487] <TB2> INFO: 411648 events read in total (8805ms).
[13:28:45.512] <TB2> INFO: Expecting 411648 events.
[13:28:54.774] <TB2> INFO: 411648 events read in total (8859ms).
[13:28:54.813] <TB2> INFO: Expecting 411648 events.
[13:29:04.205] <TB2> INFO: 411648 events read in total (8989ms).
[13:29:04.242] <TB2> INFO: Expecting 411648 events.
[13:29:13.655] <TB2> INFO: 411648 events read in total (9010ms).
[13:29:13.694] <TB2> INFO: Expecting 411648 events.
[13:29:22.965] <TB2> INFO: 411648 events read in total (8868ms).
[13:29:23.007] <TB2> INFO: Expecting 411648 events.
[13:29:32.409] <TB2> INFO: 411648 events read in total (8999ms).
[13:29:32.477] <TB2> INFO: Expecting 411648 events.
[13:29:41.786] <TB2> INFO: 411648 events read in total (8906ms).
[13:29:41.892] <TB2> INFO: Expecting 411648 events.
[13:29:51.239] <TB2> INFO: 411648 events read in total (8944ms).
[13:29:51.368] <TB2> INFO: Expecting 411648 events.
[13:30:00.778] <TB2> INFO: 411648 events read in total (9007ms).
[13:30:00.864] <TB2> INFO: Expecting 411648 events.
[13:30:10.048] <TB2> INFO: 411648 events read in total (8781ms).
[13:30:10.180] <TB2> INFO: Expecting 411648 events.
[13:30:19.409] <TB2> INFO: 411648 events read in total (8826ms).
[13:30:19.528] <TB2> INFO: Test took 150094ms.
[13:30:20.260] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:30:20.275] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:30:20.276] <TB2> INFO: run 1 of 1
[13:30:20.552] <TB2> INFO: Expecting 5025280 events.
[13:30:47.120] <TB2> INFO: 588792 events read in total (25976ms).
[13:31:13.109] <TB2> INFO: 1176936 events read in total (51965ms).
[13:31:39.029] <TB2> INFO: 1765016 events read in total (77886ms).
[13:32:05.472] <TB2> INFO: 2351672 events read in total (104328ms).
[13:32:31.782] <TB2> INFO: 2940632 events read in total (130638ms).
[13:32:58.225] <TB2> INFO: 3529096 events read in total (157081ms).
[13:33:25.035] <TB2> INFO: 4117344 events read in total (183891ms).
[13:33:51.193] <TB2> INFO: 4706368 events read in total (210049ms).
[13:34:05.887] <TB2> INFO: 5025280 events read in total (224743ms).
[13:34:06.066] <TB2> INFO: Test took 225791ms.
[13:34:29.378] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 0.219312 .. 147.425392
[13:34:29.621] <TB2> INFO: Expecting 208000 events.
[13:34:39.468] <TB2> INFO: 208000 events read in total (9256ms).
[13:34:39.470] <TB2> INFO: Test took 10089ms.
[13:34:39.520] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 157 (-1/-1) hits flags = 528 (plus default)
[13:34:39.533] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:34:39.533] <TB2> INFO: run 1 of 1
[13:34:39.811] <TB2> INFO: Expecting 5258240 events.
[13:35:06.263] <TB2> INFO: 585424 events read in total (25861ms).
[13:35:32.397] <TB2> INFO: 1170624 events read in total (51995ms).
[13:35:58.141] <TB2> INFO: 1755696 events read in total (77739ms).
[13:36:23.846] <TB2> INFO: 2340832 events read in total (103444ms).
[13:36:49.550] <TB2> INFO: 2926616 events read in total (129148ms).
[13:37:15.385] <TB2> INFO: 3511944 events read in total (154983ms).
[13:37:41.131] <TB2> INFO: 4096536 events read in total (180729ms).
[13:38:07.340] <TB2> INFO: 4680992 events read in total (206938ms).
[13:38:32.966] <TB2> INFO: 5258240 events read in total (232564ms).
[13:38:33.073] <TB2> INFO: Test took 233541ms.
[13:38:56.827] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.500000 .. 47.216794
[13:38:57.081] <TB2> INFO: Expecting 208000 events.
[13:39:07.087] <TB2> INFO: 208000 events read in total (9415ms).
[13:39:07.087] <TB2> INFO: Test took 10258ms.
[13:39:07.135] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 57 (-1/-1) hits flags = 528 (plus default)
[13:39:07.150] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:39:07.150] <TB2> INFO: run 1 of 1
[13:39:07.428] <TB2> INFO: Expecting 1364480 events.
[13:39:35.908] <TB2> INFO: 654616 events read in total (27888ms).
[13:40:04.081] <TB2> INFO: 1309368 events read in total (56061ms).
[13:40:06.843] <TB2> INFO: 1364480 events read in total (58823ms).
[13:40:06.878] <TB2> INFO: Test took 59729ms.
[13:40:21.754] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 27.638038 .. 52.499992
[13:40:22.008] <TB2> INFO: Expecting 208000 events.
[13:40:31.923] <TB2> INFO: 208000 events read in total (9324ms).
[13:40:31.924] <TB2> INFO: Test took 10168ms.
[13:40:31.972] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 62 (-1/-1) hits flags = 528 (plus default)
[13:40:31.985] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:40:31.985] <TB2> INFO: run 1 of 1
[13:40:32.263] <TB2> INFO: Expecting 1530880 events.
[13:41:00.196] <TB2> INFO: 638592 events read in total (27340ms).
[13:41:27.297] <TB2> INFO: 1277224 events read in total (54442ms).
[13:41:38.141] <TB2> INFO: 1530880 events read in total (65285ms).
[13:41:38.181] <TB2> INFO: Test took 66197ms.
[13:41:52.649] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 24.483333 .. 57.357956
[13:41:52.897] <TB2> INFO: Expecting 208000 events.
[13:42:02.744] <TB2> INFO: 208000 events read in total (9256ms).
[13:42:02.746] <TB2> INFO: Test took 10095ms.
[13:42:02.800] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 67 (-1/-1) hits flags = 528 (plus default)
[13:42:02.812] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:42:02.812] <TB2> INFO: run 1 of 1
[13:42:03.090] <TB2> INFO: Expecting 1797120 events.
[13:42:30.699] <TB2> INFO: 635448 events read in total (27017ms).
[13:42:58.047] <TB2> INFO: 1270736 events read in total (54365ms).
[13:43:21.443] <TB2> INFO: 1797120 events read in total (77761ms).
[13:43:21.482] <TB2> INFO: Test took 78670ms.
[13:43:36.874] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[13:43:36.874] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[13:43:36.888] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:43:36.888] <TB2> INFO: run 1 of 1
[13:43:37.127] <TB2> INFO: Expecting 1364480 events.
[13:44:05.316] <TB2> INFO: 668808 events read in total (27597ms).
[13:44:34.021] <TB2> INFO: 1337416 events read in total (56302ms).
[13:44:35.632] <TB2> INFO: 1364480 events read in total (57914ms).
[13:44:35.671] <TB2> INFO: Test took 58783ms.
[13:44:50.517] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C0.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C1.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C2.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C3.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C4.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C5.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C6.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C7.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C8.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C9.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C10.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C11.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C12.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C13.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C14.dat
[13:44:50.518] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C15.dat
[13:44:50.519] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C0.dat
[13:44:50.523] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C1.dat
[13:44:50.528] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C2.dat
[13:44:50.533] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C3.dat
[13:44:50.538] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C4.dat
[13:44:50.542] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C5.dat
[13:44:50.548] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C6.dat
[13:44:50.556] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C7.dat
[13:44:50.563] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C8.dat
[13:44:50.571] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C9.dat
[13:44:50.578] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C10.dat
[13:44:50.586] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C11.dat
[13:44:50.592] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C12.dat
[13:44:50.597] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C13.dat
[13:44:50.601] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C14.dat
[13:44:50.606] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C15.dat
[13:44:50.611] <TB2> INFO: PixTestTrim::trimTest() done
[13:44:50.611] <TB2> INFO: vtrim: 129 142 164 139 135 117 136 151 142 138 145 138 135 125 134 141
[13:44:50.611] <TB2> INFO: vthrcomp: 134 124 124 117 109 111 120 121 123 121 128 117 131 123 115 111
[13:44:50.611] <TB2> INFO: vcal mean: 35.18 34.93 35.75 34.94 35.27 34.96 34.94 35.19 34.98 36.51 34.98 35.20 35.40 34.94 35.05 34.92
[13:44:50.611] <TB2> INFO: vcal RMS: 1.46 1.01 2.06 1.09 1.42 1.04 1.02 1.41 1.15 2.72 1.00 1.38 1.55 0.98 1.26 0.98
[13:44:50.611] <TB2> INFO: bits mean: 9.42 8.49 9.42 9.45 8.95 7.71 9.12 9.31 9.61 9.90 9.24 9.42 8.32 9.50 8.42 8.70
[13:44:50.611] <TB2> INFO: bits RMS: 2.76 2.97 2.83 2.67 2.49 3.03 2.85 2.60 2.66 2.59 2.47 2.67 2.85 2.61 3.14 2.58
[13:44:50.618] <TB2> INFO: ----------------------------------------------------------------------
[13:44:50.618] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:44:50.618] <TB2> INFO: ----------------------------------------------------------------------
[13:44:50.622] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:44:50.635] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:44:50.635] <TB2> INFO: run 1 of 1
[13:44:50.894] <TB2> INFO: Expecting 4160000 events.
[13:45:23.603] <TB2> INFO: 759860 events read in total (32118ms).
[13:45:56.103] <TB2> INFO: 1513980 events read in total (64618ms).
[13:46:28.297] <TB2> INFO: 2260355 events read in total (96812ms).
[13:47:00.640] <TB2> INFO: 3001645 events read in total (129155ms).
[13:47:32.098] <TB2> INFO: 3739300 events read in total (160613ms).
[13:47:50.406] <TB2> INFO: 4160000 events read in total (178921ms).
[13:47:50.561] <TB2> INFO: Test took 179925ms.
[13:48:14.261] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[13:48:14.275] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:48:14.275] <TB2> INFO: run 1 of 1
[13:48:14.542] <TB2> INFO: Expecting 4347200 events.
[13:48:46.677] <TB2> INFO: 723740 events read in total (31543ms).
[13:49:18.095] <TB2> INFO: 1443655 events read in total (62961ms).
[13:49:49.027] <TB2> INFO: 2157605 events read in total (93893ms).
[13:50:19.994] <TB2> INFO: 2866820 events read in total (124860ms).
[13:50:50.719] <TB2> INFO: 3573630 events read in total (155585ms).
[13:51:21.408] <TB2> INFO: 4280055 events read in total (186274ms).
[13:51:24.747] <TB2> INFO: 4347200 events read in total (189613ms).
[13:51:24.827] <TB2> INFO: Test took 190552ms.
[13:51:53.686] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[13:51:53.699] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:51:53.699] <TB2> INFO: run 1 of 1
[13:51:53.937] <TB2> INFO: Expecting 4305600 events.
[13:52:25.890] <TB2> INFO: 726515 events read in total (31361ms).
[13:52:57.088] <TB2> INFO: 1449700 events read in total (62559ms).
[13:53:28.250] <TB2> INFO: 2166630 events read in total (93721ms).
[13:53:59.701] <TB2> INFO: 2877855 events read in total (125172ms).
[13:54:30.600] <TB2> INFO: 3587045 events read in total (156071ms).
[13:55:02.223] <TB2> INFO: 4297135 events read in total (187694ms).
[13:55:02.991] <TB2> INFO: 4305600 events read in total (188462ms).
[13:55:03.093] <TB2> INFO: Test took 189394ms.
[13:55:28.528] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[13:55:28.541] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:55:28.542] <TB2> INFO: run 1 of 1
[13:55:28.779] <TB2> INFO: Expecting 4264000 events.
[13:56:00.781] <TB2> INFO: 728775 events read in total (31410ms).
[13:56:32.228] <TB2> INFO: 1454110 events read in total (62857ms).
[13:57:03.320] <TB2> INFO: 2173260 events read in total (93949ms).
[13:57:34.256] <TB2> INFO: 2887305 events read in total (124885ms).
[13:58:05.423] <TB2> INFO: 3598845 events read in total (156052ms).
[13:58:34.500] <TB2> INFO: 4264000 events read in total (185129ms).
[13:58:34.640] <TB2> INFO: Test took 186099ms.
[13:59:04.021] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[13:59:04.034] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:59:04.034] <TB2> INFO: run 1 of 1
[13:59:04.271] <TB2> INFO: Expecting 4264000 events.
[13:59:36.111] <TB2> INFO: 729475 events read in total (31249ms).
[14:00:07.071] <TB2> INFO: 1454810 events read in total (62209ms).
[14:00:38.271] <TB2> INFO: 2174095 events read in total (93409ms).
[14:01:10.081] <TB2> INFO: 2888160 events read in total (125219ms).
[14:01:41.057] <TB2> INFO: 3599825 events read in total (156195ms).
[14:02:10.079] <TB2> INFO: 4264000 events read in total (185217ms).
[14:02:10.186] <TB2> INFO: Test took 186151ms.
[14:02:39.450] <TB2> INFO: PixTestTrim::trimBitTest() done
[14:02:39.451] <TB2> INFO: PixTestTrim::doTest() done, duration: 2553 seconds
[14:02:39.451] <TB2> INFO: Decoding statistics:
[14:02:39.451] <TB2> INFO: General information:
[14:02:39.451] <TB2> INFO: 16bit words read: 0
[14:02:39.451] <TB2> INFO: valid events total: 0
[14:02:39.451] <TB2> INFO: empty events: 0
[14:02:39.451] <TB2> INFO: valid events with pixels: 0
[14:02:39.451] <TB2> INFO: valid pixel hits: 0
[14:02:39.451] <TB2> INFO: Event errors: 0
[14:02:39.451] <TB2> INFO: start marker: 0
[14:02:39.451] <TB2> INFO: stop marker: 0
[14:02:39.451] <TB2> INFO: overflow: 0
[14:02:39.451] <TB2> INFO: invalid 5bit words: 0
[14:02:39.451] <TB2> INFO: invalid XOR eye diagram: 0
[14:02:39.451] <TB2> INFO: frame (failed synchr.): 0
[14:02:39.451] <TB2> INFO: idle data (no TBM trl): 0
[14:02:39.451] <TB2> INFO: no data (only TBM hdr): 0
[14:02:39.451] <TB2> INFO: TBM errors: 0
[14:02:39.451] <TB2> INFO: flawed TBM headers: 0
[14:02:39.451] <TB2> INFO: flawed TBM trailers: 0
[14:02:39.451] <TB2> INFO: event ID mismatches: 0
[14:02:39.451] <TB2> INFO: ROC errors: 0
[14:02:39.451] <TB2> INFO: missing ROC header(s): 0
[14:02:39.451] <TB2> INFO: misplaced readback start: 0
[14:02:39.451] <TB2> INFO: Pixel decoding errors: 0
[14:02:39.451] <TB2> INFO: pixel data incomplete: 0
[14:02:39.451] <TB2> INFO: pixel address: 0
[14:02:39.451] <TB2> INFO: pulse height fill bit: 0
[14:02:39.451] <TB2> INFO: buffer corruption: 0
[14:02:40.263] <TB2> INFO: ######################################################################
[14:02:40.263] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[14:02:40.263] <TB2> INFO: ######################################################################
[14:02:40.504] <TB2> INFO: Expecting 41600 events.
[14:02:44.235] <TB2> INFO: 41600 events read in total (3139ms).
[14:02:44.236] <TB2> INFO: Test took 3971ms.
[14:02:44.679] <TB2> INFO: Expecting 41600 events.
[14:02:48.269] <TB2> INFO: 41600 events read in total (2998ms).
[14:02:48.272] <TB2> INFO: Test took 3828ms.
[14:02:48.575] <TB2> INFO: Expecting 41600 events.
[14:02:52.139] <TB2> INFO: 41600 events read in total (2972ms).
[14:02:52.140] <TB2> INFO: Test took 3844ms.
[14:02:52.430] <TB2> INFO: Expecting 41600 events.
[14:02:55.986] <TB2> INFO: 41600 events read in total (2965ms).
[14:02:55.987] <TB2> INFO: Test took 3822ms.
[14:02:56.276] <TB2> INFO: Expecting 41600 events.
[14:02:59.841] <TB2> INFO: 41600 events read in total (2973ms).
[14:02:59.842] <TB2> INFO: Test took 3830ms.
[14:03:00.149] <TB2> INFO: Expecting 41600 events.
[14:03:03.698] <TB2> INFO: 41600 events read in total (2958ms).
[14:03:03.699] <TB2> INFO: Test took 3833ms.
[14:03:03.988] <TB2> INFO: Expecting 41600 events.
[14:03:07.686] <TB2> INFO: 41600 events read in total (3106ms).
[14:03:07.686] <TB2> INFO: Test took 3964ms.
[14:03:07.976] <TB2> INFO: Expecting 41600 events.
[14:03:11.524] <TB2> INFO: 41600 events read in total (2956ms).
[14:03:11.524] <TB2> INFO: Test took 3814ms.
[14:03:11.814] <TB2> INFO: Expecting 41600 events.
[14:03:15.355] <TB2> INFO: 41600 events read in total (2949ms).
[14:03:15.356] <TB2> INFO: Test took 3807ms.
[14:03:15.646] <TB2> INFO: Expecting 41600 events.
[14:03:19.181] <TB2> INFO: 41600 events read in total (2944ms).
[14:03:19.182] <TB2> INFO: Test took 3802ms.
[14:03:19.475] <TB2> INFO: Expecting 41600 events.
[14:03:23.176] <TB2> INFO: 41600 events read in total (3110ms).
[14:03:23.177] <TB2> INFO: Test took 3971ms.
[14:03:23.466] <TB2> INFO: Expecting 41600 events.
[14:03:27.061] <TB2> INFO: 41600 events read in total (3003ms).
[14:03:27.063] <TB2> INFO: Test took 3862ms.
[14:03:27.352] <TB2> INFO: Expecting 41600 events.
[14:03:30.880] <TB2> INFO: 41600 events read in total (2936ms).
[14:03:30.881] <TB2> INFO: Test took 3794ms.
[14:03:31.170] <TB2> INFO: Expecting 41600 events.
[14:03:34.667] <TB2> INFO: 41600 events read in total (2905ms).
[14:03:34.668] <TB2> INFO: Test took 3764ms.
[14:03:34.960] <TB2> INFO: Expecting 41600 events.
[14:03:38.518] <TB2> INFO: 41600 events read in total (2965ms).
[14:03:38.519] <TB2> INFO: Test took 3824ms.
[14:03:38.808] <TB2> INFO: Expecting 41600 events.
[14:03:42.398] <TB2> INFO: 41600 events read in total (2999ms).
[14:03:42.399] <TB2> INFO: Test took 3856ms.
[14:03:42.688] <TB2> INFO: Expecting 41600 events.
[14:03:46.255] <TB2> INFO: 41600 events read in total (2976ms).
[14:03:46.256] <TB2> INFO: Test took 3833ms.
[14:03:46.545] <TB2> INFO: Expecting 41600 events.
[14:03:50.059] <TB2> INFO: 41600 events read in total (2922ms).
[14:03:50.060] <TB2> INFO: Test took 3780ms.
[14:03:50.349] <TB2> INFO: Expecting 41600 events.
[14:03:53.890] <TB2> INFO: 41600 events read in total (2949ms).
[14:03:53.891] <TB2> INFO: Test took 3806ms.
[14:03:54.180] <TB2> INFO: Expecting 41600 events.
[14:03:57.703] <TB2> INFO: 41600 events read in total (2932ms).
[14:03:57.704] <TB2> INFO: Test took 3789ms.
[14:03:57.994] <TB2> INFO: Expecting 41600 events.
[14:04:01.612] <TB2> INFO: 41600 events read in total (3026ms).
[14:04:01.613] <TB2> INFO: Test took 3885ms.
[14:04:01.921] <TB2> INFO: Expecting 41600 events.
[14:04:05.424] <TB2> INFO: 41600 events read in total (2912ms).
[14:04:05.425] <TB2> INFO: Test took 3788ms.
[14:04:05.714] <TB2> INFO: Expecting 41600 events.
[14:04:09.257] <TB2> INFO: 41600 events read in total (2951ms).
[14:04:09.258] <TB2> INFO: Test took 3809ms.
[14:04:09.548] <TB2> INFO: Expecting 41600 events.
[14:04:13.072] <TB2> INFO: 41600 events read in total (2933ms).
[14:04:13.073] <TB2> INFO: Test took 3791ms.
[14:04:13.380] <TB2> INFO: Expecting 41600 events.
[14:04:16.873] <TB2> INFO: 41600 events read in total (2901ms).
[14:04:16.874] <TB2> INFO: Test took 3776ms.
[14:04:17.163] <TB2> INFO: Expecting 41600 events.
[14:04:20.636] <TB2> INFO: 41600 events read in total (2881ms).
[14:04:20.637] <TB2> INFO: Test took 3739ms.
[14:04:20.925] <TB2> INFO: Expecting 41600 events.
[14:04:24.473] <TB2> INFO: 41600 events read in total (2956ms).
[14:04:24.474] <TB2> INFO: Test took 3814ms.
[14:04:24.764] <TB2> INFO: Expecting 41600 events.
[14:04:28.274] <TB2> INFO: 41600 events read in total (2919ms).
[14:04:28.274] <TB2> INFO: Test took 3775ms.
[14:04:28.565] <TB2> INFO: Expecting 41600 events.
[14:04:32.090] <TB2> INFO: 41600 events read in total (2933ms).
[14:04:32.091] <TB2> INFO: Test took 3791ms.
[14:04:32.385] <TB2> INFO: Expecting 2560 events.
[14:04:33.274] <TB2> INFO: 2560 events read in total (297ms).
[14:04:33.275] <TB2> INFO: Test took 1167ms.
[14:04:33.582] <TB2> INFO: Expecting 2560 events.
[14:04:34.473] <TB2> INFO: 2560 events read in total (299ms).
[14:04:34.474] <TB2> INFO: Test took 1198ms.
[14:04:34.781] <TB2> INFO: Expecting 2560 events.
[14:04:35.675] <TB2> INFO: 2560 events read in total (302ms).
[14:04:35.676] <TB2> INFO: Test took 1202ms.
[14:04:35.983] <TB2> INFO: Expecting 2560 events.
[14:04:36.881] <TB2> INFO: 2560 events read in total (306ms).
[14:04:36.881] <TB2> INFO: Test took 1205ms.
[14:04:37.188] <TB2> INFO: Expecting 2560 events.
[14:04:38.076] <TB2> INFO: 2560 events read in total (296ms).
[14:04:38.077] <TB2> INFO: Test took 1195ms.
[14:04:38.385] <TB2> INFO: Expecting 2560 events.
[14:04:39.275] <TB2> INFO: 2560 events read in total (298ms).
[14:04:39.275] <TB2> INFO: Test took 1198ms.
[14:04:39.582] <TB2> INFO: Expecting 2560 events.
[14:04:40.470] <TB2> INFO: 2560 events read in total (296ms).
[14:04:40.470] <TB2> INFO: Test took 1194ms.
[14:04:40.777] <TB2> INFO: Expecting 2560 events.
[14:04:41.665] <TB2> INFO: 2560 events read in total (296ms).
[14:04:41.665] <TB2> INFO: Test took 1194ms.
[14:04:41.973] <TB2> INFO: Expecting 2560 events.
[14:04:42.851] <TB2> INFO: 2560 events read in total (286ms).
[14:04:42.851] <TB2> INFO: Test took 1185ms.
[14:04:43.159] <TB2> INFO: Expecting 2560 events.
[14:04:44.038] <TB2> INFO: 2560 events read in total (287ms).
[14:04:44.038] <TB2> INFO: Test took 1186ms.
[14:04:44.346] <TB2> INFO: Expecting 2560 events.
[14:04:45.232] <TB2> INFO: 2560 events read in total (294ms).
[14:04:45.233] <TB2> INFO: Test took 1195ms.
[14:04:45.540] <TB2> INFO: Expecting 2560 events.
[14:04:46.428] <TB2> INFO: 2560 events read in total (296ms).
[14:04:46.428] <TB2> INFO: Test took 1194ms.
[14:04:46.736] <TB2> INFO: Expecting 2560 events.
[14:04:47.627] <TB2> INFO: 2560 events read in total (299ms).
[14:04:47.628] <TB2> INFO: Test took 1199ms.
[14:04:47.935] <TB2> INFO: Expecting 2560 events.
[14:04:48.829] <TB2> INFO: 2560 events read in total (302ms).
[14:04:48.829] <TB2> INFO: Test took 1201ms.
[14:04:49.136] <TB2> INFO: Expecting 2560 events.
[14:04:50.022] <TB2> INFO: 2560 events read in total (295ms).
[14:04:50.023] <TB2> INFO: Test took 1193ms.
[14:04:50.330] <TB2> INFO: Expecting 2560 events.
[14:04:51.217] <TB2> INFO: 2560 events read in total (295ms).
[14:04:51.218] <TB2> INFO: Test took 1195ms.
[14:04:51.224] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:04:51.526] <TB2> INFO: Expecting 655360 events.
[14:05:06.111] <TB2> INFO: 655360 events read in total (13993ms).
[14:05:06.126] <TB2> INFO: Expecting 655360 events.
[14:05:20.505] <TB2> INFO: 655360 events read in total (13976ms).
[14:05:20.521] <TB2> INFO: Expecting 655360 events.
[14:05:34.957] <TB2> INFO: 655360 events read in total (14033ms).
[14:05:34.977] <TB2> INFO: Expecting 655360 events.
[14:05:49.570] <TB2> INFO: 655360 events read in total (14189ms).
[14:05:49.594] <TB2> INFO: Expecting 655360 events.
[14:06:04.110] <TB2> INFO: 655360 events read in total (14112ms).
[14:06:04.141] <TB2> INFO: Expecting 655360 events.
[14:06:18.613] <TB2> INFO: 655360 events read in total (14068ms).
[14:06:18.648] <TB2> INFO: Expecting 655360 events.
[14:06:33.121] <TB2> INFO: 655360 events read in total (14069ms).
[14:06:33.172] <TB2> INFO: Expecting 655360 events.
[14:06:47.734] <TB2> INFO: 655360 events read in total (14159ms).
[14:06:47.778] <TB2> INFO: Expecting 655360 events.
[14:07:02.231] <TB2> INFO: 655360 events read in total (14050ms).
[14:07:02.277] <TB2> INFO: Expecting 655360 events.
[14:07:16.581] <TB2> INFO: 655360 events read in total (13901ms).
[14:07:16.669] <TB2> INFO: Expecting 655360 events.
[14:07:31.108] <TB2> INFO: 655360 events read in total (14035ms).
[14:07:31.167] <TB2> INFO: Expecting 655360 events.
[14:07:45.721] <TB2> INFO: 655360 events read in total (14150ms).
[14:07:45.801] <TB2> INFO: Expecting 655360 events.
[14:08:00.240] <TB2> INFO: 655360 events read in total (14036ms).
[14:08:00.331] <TB2> INFO: Expecting 655360 events.
[14:08:14.755] <TB2> INFO: 655360 events read in total (14021ms).
[14:08:14.881] <TB2> INFO: Expecting 655360 events.
[14:08:29.380] <TB2> INFO: 655360 events read in total (14096ms).
[14:08:29.484] <TB2> INFO: Expecting 655360 events.
[14:08:43.945] <TB2> INFO: 655360 events read in total (14057ms).
[14:08:44.082] <TB2> INFO: Test took 232858ms.
[14:08:44.184] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:08:44.440] <TB2> INFO: Expecting 655360 events.
[14:08:59.013] <TB2> INFO: 655360 events read in total (13981ms).
[14:08:59.025] <TB2> INFO: Expecting 655360 events.
[14:09:13.388] <TB2> INFO: 655360 events read in total (13960ms).
[14:09:13.404] <TB2> INFO: Expecting 655360 events.
[14:09:27.650] <TB2> INFO: 655360 events read in total (13843ms).
[14:09:27.671] <TB2> INFO: Expecting 655360 events.
[14:09:42.116] <TB2> INFO: 655360 events read in total (14042ms).
[14:09:42.141] <TB2> INFO: Expecting 655360 events.
[14:09:56.494] <TB2> INFO: 655360 events read in total (13950ms).
[14:09:56.529] <TB2> INFO: Expecting 655360 events.
[14:10:10.926] <TB2> INFO: 655360 events read in total (13994ms).
[14:10:10.962] <TB2> INFO: Expecting 655360 events.
[14:10:25.462] <TB2> INFO: 655360 events read in total (14097ms).
[14:10:25.499] <TB2> INFO: Expecting 655360 events.
[14:10:39.887] <TB2> INFO: 655360 events read in total (13985ms).
[14:10:39.932] <TB2> INFO: Expecting 655360 events.
[14:10:54.360] <TB2> INFO: 655360 events read in total (14025ms).
[14:10:54.421] <TB2> INFO: Expecting 655360 events.
[14:11:08.658] <TB2> INFO: 655360 events read in total (13833ms).
[14:11:08.775] <TB2> INFO: Expecting 655360 events.
[14:11:23.475] <TB2> INFO: 655360 events read in total (14297ms).
[14:11:23.533] <TB2> INFO: Expecting 655360 events.
[14:11:37.942] <TB2> INFO: 655360 events read in total (14004ms).
[14:11:38.030] <TB2> INFO: Expecting 655360 events.
[14:11:52.433] <TB2> INFO: 655360 events read in total (13999ms).
[14:11:52.512] <TB2> INFO: Expecting 655360 events.
[14:12:07.210] <TB2> INFO: 655360 events read in total (14295ms).
[14:12:07.297] <TB2> INFO: Expecting 655360 events.
[14:12:21.002] <TB2> INFO: 655360 events read in total (14302ms).
[14:12:22.096] <TB2> INFO: Expecting 655360 events.
[14:12:36.975] <TB2> INFO: 655360 events read in total (14476ms).
[14:12:37.107] <TB2> INFO: Test took 232923ms.
[14:12:37.330] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.335] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.341] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:12:37.346] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:12:37.352] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:12:37.358] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:12:37.363] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:12:37.369] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.374] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:12:37.380] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:12:37.385] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:12:37.391] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.397] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:12:37.402] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:12:37.408] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:12:37.413] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:12:37.419] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:12:37.425] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[14:12:37.430] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.435] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:12:37.441] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:12:37.447] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:12:37.452] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.458] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.463] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.469] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.475] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:12:37.480] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:12:37.487] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:12:37.493] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:12:37.498] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.505] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:12:37.511] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:12:37.516] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:12:37.523] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:12:37.528] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:12:37.535] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[14:12:37.541] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[14:12:37.546] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[14:12:37.553] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[14:12:37.559] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.564] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.571] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.576] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:12:37.582] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:12:37.589] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:12:37.594] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:12:37.600] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:12:37.606] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[14:12:37.612] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[14:12:37.618] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[14:12:37.624] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.630] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.636] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:12:37.642] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:12:37.648] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:37.686] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C0.dat
[14:12:37.686] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C1.dat
[14:12:37.686] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C2.dat
[14:12:37.687] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C3.dat
[14:12:37.687] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C4.dat
[14:12:37.687] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C5.dat
[14:12:37.687] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C6.dat
[14:12:37.687] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C7.dat
[14:12:37.688] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C8.dat
[14:12:37.688] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C9.dat
[14:12:37.688] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C10.dat
[14:12:37.688] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C11.dat
[14:12:37.688] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C12.dat
[14:12:37.689] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C13.dat
[14:12:37.689] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C14.dat
[14:12:37.689] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C15.dat
[14:12:37.935] <TB2> INFO: Expecting 41600 events.
[14:12:41.091] <TB2> INFO: 41600 events read in total (2564ms).
[14:12:41.092] <TB2> INFO: Test took 3399ms.
[14:12:41.545] <TB2> INFO: Expecting 41600 events.
[14:12:44.622] <TB2> INFO: 41600 events read in total (2485ms).
[14:12:44.623] <TB2> INFO: Test took 3318ms.
[14:12:45.083] <TB2> INFO: Expecting 41600 events.
[14:12:48.281] <TB2> INFO: 41600 events read in total (2606ms).
[14:12:48.282] <TB2> INFO: Test took 3445ms.
[14:12:48.497] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:48.586] <TB2> INFO: Expecting 2560 events.
[14:12:49.481] <TB2> INFO: 2560 events read in total (303ms).
[14:12:49.482] <TB2> INFO: Test took 985ms.
[14:12:49.486] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:49.789] <TB2> INFO: Expecting 2560 events.
[14:12:50.683] <TB2> INFO: 2560 events read in total (302ms).
[14:12:50.684] <TB2> INFO: Test took 1198ms.
[14:12:50.688] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:50.991] <TB2> INFO: Expecting 2560 events.
[14:12:51.885] <TB2> INFO: 2560 events read in total (302ms).
[14:12:51.886] <TB2> INFO: Test took 1198ms.
[14:12:51.889] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:52.194] <TB2> INFO: Expecting 2560 events.
[14:12:53.080] <TB2> INFO: 2560 events read in total (294ms).
[14:12:53.080] <TB2> INFO: Test took 1191ms.
[14:12:53.086] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:53.388] <TB2> INFO: Expecting 2560 events.
[14:12:54.275] <TB2> INFO: 2560 events read in total (295ms).
[14:12:54.276] <TB2> INFO: Test took 1190ms.
[14:12:54.279] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:54.584] <TB2> INFO: Expecting 2560 events.
[14:12:55.482] <TB2> INFO: 2560 events read in total (306ms).
[14:12:55.482] <TB2> INFO: Test took 1203ms.
[14:12:55.486] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:55.790] <TB2> INFO: Expecting 2560 events.
[14:12:56.676] <TB2> INFO: 2560 events read in total (294ms).
[14:12:56.677] <TB2> INFO: Test took 1191ms.
[14:12:56.678] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:56.986] <TB2> INFO: Expecting 2560 events.
[14:12:57.870] <TB2> INFO: 2560 events read in total (292ms).
[14:12:57.870] <TB2> INFO: Test took 1192ms.
[14:12:57.872] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:58.180] <TB2> INFO: Expecting 2560 events.
[14:12:59.071] <TB2> INFO: 2560 events read in total (299ms).
[14:12:59.072] <TB2> INFO: Test took 1200ms.
[14:12:59.076] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:59.379] <TB2> INFO: Expecting 2560 events.
[14:13:00.269] <TB2> INFO: 2560 events read in total (298ms).
[14:13:00.269] <TB2> INFO: Test took 1193ms.
[14:13:00.272] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:00.577] <TB2> INFO: Expecting 2560 events.
[14:13:01.463] <TB2> INFO: 2560 events read in total (294ms).
[14:13:01.464] <TB2> INFO: Test took 1192ms.
[14:13:01.465] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:01.772] <TB2> INFO: Expecting 2560 events.
[14:13:02.663] <TB2> INFO: 2560 events read in total (299ms).
[14:13:02.664] <TB2> INFO: Test took 1199ms.
[14:13:02.668] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:02.971] <TB2> INFO: Expecting 2560 events.
[14:13:03.862] <TB2> INFO: 2560 events read in total (299ms).
[14:13:03.862] <TB2> INFO: Test took 1194ms.
[14:13:03.866] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:04.169] <TB2> INFO: Expecting 2560 events.
[14:13:05.058] <TB2> INFO: 2560 events read in total (297ms).
[14:13:05.058] <TB2> INFO: Test took 1193ms.
[14:13:05.061] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:05.367] <TB2> INFO: Expecting 2560 events.
[14:13:06.259] <TB2> INFO: 2560 events read in total (301ms).
[14:13:06.259] <TB2> INFO: Test took 1198ms.
[14:13:06.261] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:06.568] <TB2> INFO: Expecting 2560 events.
[14:13:07.458] <TB2> INFO: 2560 events read in total (298ms).
[14:13:07.458] <TB2> INFO: Test took 1197ms.
[14:13:07.462] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:07.765] <TB2> INFO: Expecting 2560 events.
[14:13:08.655] <TB2> INFO: 2560 events read in total (298ms).
[14:13:08.656] <TB2> INFO: Test took 1194ms.
[14:13:08.660] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:08.964] <TB2> INFO: Expecting 2560 events.
[14:13:09.848] <TB2> INFO: 2560 events read in total (292ms).
[14:13:09.848] <TB2> INFO: Test took 1188ms.
[14:13:09.851] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:10.156] <TB2> INFO: Expecting 2560 events.
[14:13:11.047] <TB2> INFO: 2560 events read in total (299ms).
[14:13:11.047] <TB2> INFO: Test took 1196ms.
[14:13:11.050] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:11.356] <TB2> INFO: Expecting 2560 events.
[14:13:12.244] <TB2> INFO: 2560 events read in total (297ms).
[14:13:12.245] <TB2> INFO: Test took 1195ms.
[14:13:12.249] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:12.552] <TB2> INFO: Expecting 2560 events.
[14:13:13.443] <TB2> INFO: 2560 events read in total (299ms).
[14:13:13.444] <TB2> INFO: Test took 1195ms.
[14:13:13.446] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:13.751] <TB2> INFO: Expecting 2560 events.
[14:13:14.634] <TB2> INFO: 2560 events read in total (291ms).
[14:13:14.634] <TB2> INFO: Test took 1188ms.
[14:13:14.637] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:14.943] <TB2> INFO: Expecting 2560 events.
[14:13:15.833] <TB2> INFO: 2560 events read in total (298ms).
[14:13:15.834] <TB2> INFO: Test took 1197ms.
[14:13:15.837] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:16.143] <TB2> INFO: Expecting 2560 events.
[14:13:17.033] <TB2> INFO: 2560 events read in total (299ms).
[14:13:17.033] <TB2> INFO: Test took 1196ms.
[14:13:17.037] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:17.342] <TB2> INFO: Expecting 2560 events.
[14:13:18.233] <TB2> INFO: 2560 events read in total (299ms).
[14:13:18.233] <TB2> INFO: Test took 1196ms.
[14:13:18.236] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:18.543] <TB2> INFO: Expecting 2560 events.
[14:13:19.434] <TB2> INFO: 2560 events read in total (299ms).
[14:13:19.435] <TB2> INFO: Test took 1199ms.
[14:13:19.439] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:19.743] <TB2> INFO: Expecting 2560 events.
[14:13:20.634] <TB2> INFO: 2560 events read in total (299ms).
[14:13:20.635] <TB2> INFO: Test took 1196ms.
[14:13:20.638] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:20.942] <TB2> INFO: Expecting 2560 events.
[14:13:21.834] <TB2> INFO: 2560 events read in total (300ms).
[14:13:21.834] <TB2> INFO: Test took 1196ms.
[14:13:21.838] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:22.143] <TB2> INFO: Expecting 2560 events.
[14:13:23.036] <TB2> INFO: 2560 events read in total (301ms).
[14:13:23.036] <TB2> INFO: Test took 1198ms.
[14:13:23.040] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:23.344] <TB2> INFO: Expecting 2560 events.
[14:13:24.243] <TB2> INFO: 2560 events read in total (307ms).
[14:13:24.243] <TB2> INFO: Test took 1204ms.
[14:13:24.247] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:24.552] <TB2> INFO: Expecting 2560 events.
[14:13:25.446] <TB2> INFO: 2560 events read in total (302ms).
[14:13:25.446] <TB2> INFO: Test took 1199ms.
[14:13:25.451] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:25.755] <TB2> INFO: Expecting 2560 events.
[14:13:26.650] <TB2> INFO: 2560 events read in total (304ms).
[14:13:26.650] <TB2> INFO: Test took 1199ms.
[14:13:27.126] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 646 seconds
[14:13:27.126] <TB2> INFO: PH scale (per ROC): 35 48 42 48 36 38 47 36 44 32 52 46 30 54 37 35
[14:13:27.126] <TB2> INFO: PH offset (per ROC): 93 127 106 107 112 106 89 87 98 92 113 114 106 124 99 91
[14:13:27.135] <TB2> INFO: Decoding statistics:
[14:13:27.135] <TB2> INFO: General information:
[14:13:27.135] <TB2> INFO: 16bit words read: 127886
[14:13:27.135] <TB2> INFO: valid events total: 20480
[14:13:27.135] <TB2> INFO: empty events: 17977
[14:13:27.135] <TB2> INFO: valid events with pixels: 2503
[14:13:27.135] <TB2> INFO: valid pixel hits: 2503
[14:13:27.135] <TB2> INFO: Event errors: 0
[14:13:27.135] <TB2> INFO: start marker: 0
[14:13:27.135] <TB2> INFO: stop marker: 0
[14:13:27.135] <TB2> INFO: overflow: 0
[14:13:27.135] <TB2> INFO: invalid 5bit words: 0
[14:13:27.135] <TB2> INFO: invalid XOR eye diagram: 0
[14:13:27.135] <TB2> INFO: frame (failed synchr.): 0
[14:13:27.135] <TB2> INFO: idle data (no TBM trl): 0
[14:13:27.135] <TB2> INFO: no data (only TBM hdr): 0
[14:13:27.135] <TB2> INFO: TBM errors: 0
[14:13:27.135] <TB2> INFO: flawed TBM headers: 0
[14:13:27.135] <TB2> INFO: flawed TBM trailers: 0
[14:13:27.135] <TB2> INFO: event ID mismatches: 0
[14:13:27.135] <TB2> INFO: ROC errors: 0
[14:13:27.135] <TB2> INFO: missing ROC header(s): 0
[14:13:27.135] <TB2> INFO: misplaced readback start: 0
[14:13:27.135] <TB2> INFO: Pixel decoding errors: 0
[14:13:27.135] <TB2> INFO: pixel data incomplete: 0
[14:13:27.135] <TB2> INFO: pixel address: 0
[14:13:27.135] <TB2> INFO: pulse height fill bit: 0
[14:13:27.135] <TB2> INFO: buffer corruption: 0
[14:13:27.306] <TB2> INFO: ######################################################################
[14:13:27.306] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[14:13:27.306] <TB2> INFO: ######################################################################
[14:13:27.321] <TB2> INFO: scanning low vcal = 10
[14:13:27.557] <TB2> INFO: Expecting 41600 events.
[14:13:31.141] <TB2> INFO: 41600 events read in total (2992ms).
[14:13:31.141] <TB2> INFO: Test took 3820ms.
[14:13:31.143] <TB2> INFO: scanning low vcal = 20
[14:13:31.440] <TB2> INFO: Expecting 41600 events.
[14:13:35.049] <TB2> INFO: 41600 events read in total (3017ms).
[14:13:35.050] <TB2> INFO: Test took 3906ms.
[14:13:35.052] <TB2> INFO: scanning low vcal = 30
[14:13:35.343] <TB2> INFO: Expecting 41600 events.
[14:13:39.061] <TB2> INFO: 41600 events read in total (3126ms).
[14:13:39.063] <TB2> INFO: Test took 4011ms.
[14:13:39.066] <TB2> INFO: scanning low vcal = 40
[14:13:39.343] <TB2> INFO: Expecting 41600 events.
[14:13:43.376] <TB2> INFO: 41600 events read in total (3441ms).
[14:13:43.377] <TB2> INFO: Test took 4312ms.
[14:13:43.381] <TB2> INFO: scanning low vcal = 50
[14:13:43.658] <TB2> INFO: Expecting 41600 events.
[14:13:47.695] <TB2> INFO: 41600 events read in total (3445ms).
[14:13:47.695] <TB2> INFO: Test took 4314ms.
[14:13:47.699] <TB2> INFO: scanning low vcal = 60
[14:13:47.976] <TB2> INFO: Expecting 41600 events.
[14:13:52.051] <TB2> INFO: 41600 events read in total (3483ms).
[14:13:52.052] <TB2> INFO: Test took 4353ms.
[14:13:52.055] <TB2> INFO: scanning low vcal = 70
[14:13:52.332] <TB2> INFO: Expecting 41600 events.
[14:13:56.364] <TB2> INFO: 41600 events read in total (3441ms).
[14:13:56.365] <TB2> INFO: Test took 4310ms.
[14:13:56.368] <TB2> INFO: scanning low vcal = 80
[14:13:56.645] <TB2> INFO: Expecting 41600 events.
[14:14:00.679] <TB2> INFO: 41600 events read in total (3442ms).
[14:14:00.680] <TB2> INFO: Test took 4312ms.
[14:14:00.684] <TB2> INFO: scanning low vcal = 90
[14:14:00.961] <TB2> INFO: Expecting 41600 events.
[14:14:05.004] <TB2> INFO: 41600 events read in total (3449ms).
[14:14:05.005] <TB2> INFO: Test took 4321ms.
[14:14:05.009] <TB2> INFO: scanning low vcal = 100
[14:14:05.285] <TB2> INFO: Expecting 41600 events.
[14:14:09.246] <TB2> INFO: 41600 events read in total (3369ms).
[14:14:09.247] <TB2> INFO: Test took 4238ms.
[14:14:09.250] <TB2> INFO: scanning low vcal = 110
[14:14:09.527] <TB2> INFO: Expecting 41600 events.
[14:14:13.483] <TB2> INFO: 41600 events read in total (3362ms).
[14:14:13.484] <TB2> INFO: Test took 4234ms.
[14:14:13.487] <TB2> INFO: scanning low vcal = 120
[14:14:13.763] <TB2> INFO: Expecting 41600 events.
[14:14:17.707] <TB2> INFO: 41600 events read in total (3352ms).
[14:14:17.708] <TB2> INFO: Test took 4221ms.
[14:14:17.711] <TB2> INFO: scanning low vcal = 130
[14:14:17.988] <TB2> INFO: Expecting 41600 events.
[14:14:21.946] <TB2> INFO: 41600 events read in total (3366ms).
[14:14:21.947] <TB2> INFO: Test took 4235ms.
[14:14:21.951] <TB2> INFO: scanning low vcal = 140
[14:14:22.232] <TB2> INFO: Expecting 41600 events.
[14:14:26.181] <TB2> INFO: 41600 events read in total (3357ms).
[14:14:26.182] <TB2> INFO: Test took 4231ms.
[14:14:26.185] <TB2> INFO: scanning low vcal = 150
[14:14:26.461] <TB2> INFO: Expecting 41600 events.
[14:14:30.415] <TB2> INFO: 41600 events read in total (3362ms).
[14:14:30.416] <TB2> INFO: Test took 4231ms.
[14:14:30.419] <TB2> INFO: scanning low vcal = 160
[14:14:30.695] <TB2> INFO: Expecting 41600 events.
[14:14:34.658] <TB2> INFO: 41600 events read in total (3371ms).
[14:14:34.659] <TB2> INFO: Test took 4240ms.
[14:14:34.662] <TB2> INFO: scanning low vcal = 170
[14:14:34.938] <TB2> INFO: Expecting 41600 events.
[14:14:38.880] <TB2> INFO: 41600 events read in total (3350ms).
[14:14:38.880] <TB2> INFO: Test took 4218ms.
[14:14:38.887] <TB2> INFO: scanning low vcal = 180
[14:14:39.160] <TB2> INFO: Expecting 41600 events.
[14:14:43.266] <TB2> INFO: 41600 events read in total (3514ms).
[14:14:43.267] <TB2> INFO: Test took 4380ms.
[14:14:43.270] <TB2> INFO: scanning low vcal = 190
[14:14:43.547] <TB2> INFO: Expecting 41600 events.
[14:14:47.599] <TB2> INFO: 41600 events read in total (3460ms).
[14:14:47.600] <TB2> INFO: Test took 4330ms.
[14:14:47.603] <TB2> INFO: scanning low vcal = 200
[14:14:47.880] <TB2> INFO: Expecting 41600 events.
[14:14:51.892] <TB2> INFO: 41600 events read in total (3419ms).
[14:14:51.893] <TB2> INFO: Test took 4290ms.
[14:14:51.896] <TB2> INFO: scanning low vcal = 210
[14:14:52.173] <TB2> INFO: Expecting 41600 events.
[14:14:56.161] <TB2> INFO: 41600 events read in total (3397ms).
[14:14:56.162] <TB2> INFO: Test took 4266ms.
[14:14:56.166] <TB2> INFO: scanning low vcal = 220
[14:14:56.442] <TB2> INFO: Expecting 41600 events.
[14:15:00.435] <TB2> INFO: 41600 events read in total (3401ms).
[14:15:00.436] <TB2> INFO: Test took 4270ms.
[14:15:00.439] <TB2> INFO: scanning low vcal = 230
[14:15:00.717] <TB2> INFO: Expecting 41600 events.
[14:15:04.653] <TB2> INFO: 41600 events read in total (3345ms).
[14:15:04.654] <TB2> INFO: Test took 4215ms.
[14:15:04.658] <TB2> INFO: scanning low vcal = 240
[14:15:04.934] <TB2> INFO: Expecting 41600 events.
[14:15:08.877] <TB2> INFO: 41600 events read in total (3351ms).
[14:15:08.877] <TB2> INFO: Test took 4220ms.
[14:15:08.881] <TB2> INFO: scanning low vcal = 250
[14:15:09.157] <TB2> INFO: Expecting 41600 events.
[14:15:13.097] <TB2> INFO: 41600 events read in total (3348ms).
[14:15:13.098] <TB2> INFO: Test took 4217ms.
[14:15:13.102] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[14:15:13.378] <TB2> INFO: Expecting 41600 events.
[14:15:17.331] <TB2> INFO: 41600 events read in total (3361ms).
[14:15:17.332] <TB2> INFO: Test took 4230ms.
[14:15:17.336] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[14:15:17.612] <TB2> INFO: Expecting 41600 events.
[14:15:21.568] <TB2> INFO: 41600 events read in total (3364ms).
[14:15:21.569] <TB2> INFO: Test took 4233ms.
[14:15:21.573] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[14:15:21.849] <TB2> INFO: Expecting 41600 events.
[14:15:25.815] <TB2> INFO: 41600 events read in total (3374ms).
[14:15:25.816] <TB2> INFO: Test took 4243ms.
[14:15:25.820] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[14:15:26.097] <TB2> INFO: Expecting 41600 events.
[14:15:30.147] <TB2> INFO: 41600 events read in total (3459ms).
[14:15:30.148] <TB2> INFO: Test took 4328ms.
[14:15:30.153] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[14:15:30.485] <TB2> INFO: Expecting 41600 events.
[14:15:34.445] <TB2> INFO: 41600 events read in total (3368ms).
[14:15:34.446] <TB2> INFO: Test took 4292ms.
[14:15:34.955] <TB2> INFO: PixTestGainPedestal::measure() done
[14:16:15.103] <TB2> INFO: PixTestGainPedestal::fit() done
[14:16:15.103] <TB2> INFO: non-linearity mean: 0.890 0.976 0.929 0.961 0.907 0.920 0.950 0.926 0.936 1.011 0.968 0.960 1.068 0.982 0.946 0.921
[14:16:15.103] <TB2> INFO: non-linearity RMS: 0.153 0.005 0.097 0.022 0.107 0.074 0.045 0.138 0.097 0.186 0.015 0.024 0.147 0.003 0.090 0.087
[14:16:15.103] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[14:16:15.118] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[14:16:15.131] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[14:16:15.144] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[14:16:15.157] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[14:16:15.171] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[14:16:15.184] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[14:16:15.198] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[14:16:15.211] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[14:16:15.224] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[14:16:15.238] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[14:16:15.251] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[14:16:15.267] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[14:16:15.283] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[14:16:15.296] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[14:16:15.309] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[14:16:15.323] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 168 seconds
[14:16:15.323] <TB2> INFO: Decoding statistics:
[14:16:15.323] <TB2> INFO: General information:
[14:16:15.323] <TB2> INFO: 16bit words read: 3233826
[14:16:15.323] <TB2> INFO: valid events total: 332800
[14:16:15.323] <TB2> INFO: empty events: 602
[14:16:15.323] <TB2> INFO: valid events with pixels: 332198
[14:16:15.323] <TB2> INFO: valid pixel hits: 618513
[14:16:15.323] <TB2> INFO: Event errors: 0
[14:16:15.323] <TB2> INFO: start marker: 0
[14:16:15.323] <TB2> INFO: stop marker: 0
[14:16:15.323] <TB2> INFO: overflow: 0
[14:16:15.323] <TB2> INFO: invalid 5bit words: 0
[14:16:15.323] <TB2> INFO: invalid XOR eye diagram: 0
[14:16:15.323] <TB2> INFO: frame (failed synchr.): 0
[14:16:15.323] <TB2> INFO: idle data (no TBM trl): 0
[14:16:15.323] <TB2> INFO: no data (only TBM hdr): 0
[14:16:15.323] <TB2> INFO: TBM errors: 0
[14:16:15.323] <TB2> INFO: flawed TBM headers: 0
[14:16:15.323] <TB2> INFO: flawed TBM trailers: 0
[14:16:15.323] <TB2> INFO: event ID mismatches: 0
[14:16:15.323] <TB2> INFO: ROC errors: 0
[14:16:15.323] <TB2> INFO: missing ROC header(s): 0
[14:16:15.323] <TB2> INFO: misplaced readback start: 0
[14:16:15.323] <TB2> INFO: Pixel decoding errors: 0
[14:16:15.323] <TB2> INFO: pixel data incomplete: 0
[14:16:15.323] <TB2> INFO: pixel address: 0
[14:16:15.323] <TB2> INFO: pulse height fill bit: 0
[14:16:15.323] <TB2> INFO: buffer corruption: 0
[14:16:15.345] <TB2> INFO: Decoding statistics:
[14:16:15.345] <TB2> INFO: General information:
[14:16:15.345] <TB2> INFO: 16bit words read: 3363248
[14:16:15.345] <TB2> INFO: valid events total: 353536
[14:16:15.345] <TB2> INFO: empty events: 18835
[14:16:15.345] <TB2> INFO: valid events with pixels: 334701
[14:16:15.345] <TB2> INFO: valid pixel hits: 621016
[14:16:15.346] <TB2> INFO: Event errors: 0
[14:16:15.346] <TB2> INFO: start marker: 0
[14:16:15.346] <TB2> INFO: stop marker: 0
[14:16:15.346] <TB2> INFO: overflow: 0
[14:16:15.346] <TB2> INFO: invalid 5bit words: 0
[14:16:15.346] <TB2> INFO: invalid XOR eye diagram: 0
[14:16:15.346] <TB2> INFO: frame (failed synchr.): 0
[14:16:15.346] <TB2> INFO: idle data (no TBM trl): 0
[14:16:15.346] <TB2> INFO: no data (only TBM hdr): 0
[14:16:15.346] <TB2> INFO: TBM errors: 0
[14:16:15.346] <TB2> INFO: flawed TBM headers: 0
[14:16:15.346] <TB2> INFO: flawed TBM trailers: 0
[14:16:15.346] <TB2> INFO: event ID mismatches: 0
[14:16:15.346] <TB2> INFO: ROC errors: 0
[14:16:15.346] <TB2> INFO: missing ROC header(s): 0
[14:16:15.346] <TB2> INFO: misplaced readback start: 0
[14:16:15.346] <TB2> INFO: Pixel decoding errors: 0
[14:16:15.346] <TB2> INFO: pixel data incomplete: 0
[14:16:15.346] <TB2> INFO: pixel address: 0
[14:16:15.346] <TB2> INFO: pulse height fill bit: 0
[14:16:15.346] <TB2> INFO: buffer corruption: 0
[14:16:15.346] <TB2> INFO: enter test to run
[14:16:15.346] <TB2> INFO: test: trim80 no parameter change
[14:16:15.346] <TB2> INFO: running: trim80
[14:16:15.347] <TB2> INFO: ######################################################################
[14:16:15.347] <TB2> INFO: PixTestTrim80::doTest()
[14:16:15.347] <TB2> INFO: ######################################################################
[14:16:15.348] <TB2> INFO: ----------------------------------------------------------------------
[14:16:15.349] <TB2> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[14:16:15.349] <TB2> INFO: ----------------------------------------------------------------------
[14:16:15.389] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:16:15.389] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:16:15.400] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:16:15.401] <TB2> INFO: run 1 of 1
[14:16:15.637] <TB2> INFO: Expecting 5025280 events.
[14:16:43.714] <TB2> INFO: 679512 events read in total (27485ms).
[14:17:11.329] <TB2> INFO: 1355064 events read in total (55100ms).
[14:17:38.755] <TB2> INFO: 2029616 events read in total (82526ms).
[14:18:06.392] <TB2> INFO: 2702944 events read in total (110163ms).
[14:18:33.993] <TB2> INFO: 3375640 events read in total (137764ms).
[14:19:01.438] <TB2> INFO: 4046752 events read in total (165209ms).
[14:19:28.602] <TB2> INFO: 4718304 events read in total (192373ms).
[14:19:41.216] <TB2> INFO: 5025280 events read in total (204987ms).
[14:19:41.296] <TB2> INFO: Test took 205895ms.
[14:20:08.729] <TB2> INFO: ROC 0 VthrComp = 81
[14:20:08.729] <TB2> INFO: ROC 1 VthrComp = 74
[14:20:08.730] <TB2> INFO: ROC 2 VthrComp = 77
[14:20:08.730] <TB2> INFO: ROC 3 VthrComp = 72
[14:20:08.730] <TB2> INFO: ROC 4 VthrComp = 70
[14:20:08.730] <TB2> INFO: ROC 5 VthrComp = 67
[14:20:08.730] <TB2> INFO: ROC 6 VthrComp = 71
[14:20:08.730] <TB2> INFO: ROC 7 VthrComp = 73
[14:20:08.730] <TB2> INFO: ROC 8 VthrComp = 74
[14:20:08.731] <TB2> INFO: ROC 9 VthrComp = 77
[14:20:08.733] <TB2> INFO: ROC 10 VthrComp = 76
[14:20:08.734] <TB2> INFO: ROC 11 VthrComp = 74
[14:20:08.734] <TB2> INFO: ROC 12 VthrComp = 82
[14:20:08.734] <TB2> INFO: ROC 13 VthrComp = 73
[14:20:08.734] <TB2> INFO: ROC 14 VthrComp = 70
[14:20:08.734] <TB2> INFO: ROC 15 VthrComp = 65
[14:20:08.976] <TB2> INFO: Expecting 41600 events.
[14:20:12.454] <TB2> INFO: 41600 events read in total (2880ms).
[14:20:12.455] <TB2> INFO: Test took 3715ms.
[14:20:12.464] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:20:12.465] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:20:12.476] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:20:12.476] <TB2> INFO: run 1 of 1
[14:20:12.754] <TB2> INFO: Expecting 5025280 events.
[14:20:41.223] <TB2> INFO: 685792 events read in total (27877ms).
[14:21:08.946] <TB2> INFO: 1367944 events read in total (55600ms).
[14:21:36.744] <TB2> INFO: 2048592 events read in total (83398ms).
[14:22:03.834] <TB2> INFO: 2725144 events read in total (110488ms).
[14:22:31.047] <TB2> INFO: 3397864 events read in total (137701ms).
[14:22:58.557] <TB2> INFO: 4070312 events read in total (165211ms).
[14:23:25.773] <TB2> INFO: 4739376 events read in total (192427ms).
[14:23:38.048] <TB2> INFO: 5025280 events read in total (204702ms).
[14:23:38.132] <TB2> INFO: Test took 205655ms.
[14:24:00.474] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 106.144 for pixel 1/22 mean/min/max = 90.9814/75.7633/106.199
[14:24:00.474] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 111.225 for pixel 0/71 mean/min/max = 94.314/77.3534/111.275
[14:24:00.475] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 119.455 for pixel 0/10 mean/min/max = 97.9916/76.317/119.666
[14:24:00.475] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 107.458 for pixel 0/13 mean/min/max = 92.4021/77.1521/107.652
[14:24:00.476] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 104.867 for pixel 5/79 mean/min/max = 89.5046/74.0111/104.998
[14:24:00.477] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 106.738 for pixel 0/25 mean/min/max = 90.7693/74.7579/106.781
[14:24:00.478] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 105.211 for pixel 4/7 mean/min/max = 90.2022/75.1796/105.225
[14:24:00.478] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 110.124 for pixel 51/1 mean/min/max = 94.2147/77.9299/110.5
[14:24:00.479] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 108.9 for pixel 24/10 mean/min/max = 93.6506/78.3384/108.963
[14:24:00.480] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 108.585 for pixel 0/7 mean/min/max = 93.4914/78.3322/108.651
[14:24:00.480] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 108.742 for pixel 0/63 mean/min/max = 92.9479/77.0247/108.871
[14:24:00.481] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 109.016 for pixel 9/2 mean/min/max = 93.0591/76.94/109.178
[14:24:00.482] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 108.23 for pixel 7/74 mean/min/max = 91.7882/75.1957/108.381
[14:24:00.482] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 105.859 for pixel 0/44 mean/min/max = 91.9895/78.0564/105.923
[14:24:00.483] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 116.11 for pixel 0/14 mean/min/max = 94.9663/73.6209/116.312
[14:24:00.483] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 105.771 for pixel 0/23 mean/min/max = 90.415/75.033/105.797
[14:24:00.484] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:24:00.573] <TB2> INFO: Expecting 411648 events.
[14:24:10.136] <TB2> INFO: 411648 events read in total (8971ms).
[14:24:10.144] <TB2> INFO: Expecting 411648 events.
[14:24:19.475] <TB2> INFO: 411648 events read in total (8928ms).
[14:24:19.486] <TB2> INFO: Expecting 411648 events.
[14:24:28.890] <TB2> INFO: 411648 events read in total (9001ms).
[14:24:28.906] <TB2> INFO: Expecting 411648 events.
[14:24:38.239] <TB2> INFO: 411648 events read in total (8930ms).
[14:24:38.260] <TB2> INFO: Expecting 411648 events.
[14:24:47.626] <TB2> INFO: 411648 events read in total (8963ms).
[14:24:47.645] <TB2> INFO: Expecting 411648 events.
[14:24:57.091] <TB2> INFO: 411648 events read in total (9044ms).
[14:24:57.114] <TB2> INFO: Expecting 411648 events.
[14:25:06.455] <TB2> INFO: 411648 events read in total (8937ms).
[14:25:06.486] <TB2> INFO: Expecting 411648 events.
[14:25:15.755] <TB2> INFO: 411648 events read in total (8866ms).
[14:25:15.783] <TB2> INFO: Expecting 411648 events.
[14:25:25.084] <TB2> INFO: 411648 events read in total (8898ms).
[14:25:25.116] <TB2> INFO: Expecting 411648 events.
[14:25:34.468] <TB2> INFO: 411648 events read in total (8949ms).
[14:25:34.509] <TB2> INFO: Expecting 411648 events.
[14:25:43.774] <TB2> INFO: 411648 events read in total (8861ms).
[14:25:43.811] <TB2> INFO: Expecting 411648 events.
[14:25:53.232] <TB2> INFO: 411648 events read in total (9017ms).
[14:25:53.303] <TB2> INFO: Expecting 411648 events.
[14:26:02.721] <TB2> INFO: 411648 events read in total (9015ms).
[14:26:02.766] <TB2> INFO: Expecting 411648 events.
[14:26:12.015] <TB2> INFO: 411648 events read in total (8846ms).
[14:26:12.095] <TB2> INFO: Expecting 411648 events.
[14:26:21.302] <TB2> INFO: 411648 events read in total (8804ms).
[14:26:21.367] <TB2> INFO: Expecting 411648 events.
[14:26:30.723] <TB2> INFO: 411648 events read in total (8953ms).
[14:26:30.785] <TB2> INFO: Test took 150301ms.
[14:26:32.289] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:26:32.302] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:26:32.302] <TB2> INFO: run 1 of 1
[14:26:32.540] <TB2> INFO: Expecting 5025280 events.
[14:27:00.333] <TB2> INFO: 669920 events read in total (27201ms).
[14:27:27.422] <TB2> INFO: 1337496 events read in total (54290ms).
[14:27:54.573] <TB2> INFO: 2003784 events read in total (81441ms).
[14:28:21.348] <TB2> INFO: 2668848 events read in total (108216ms).
[14:28:49.099] <TB2> INFO: 3329040 events read in total (135967ms).
[14:29:16.202] <TB2> INFO: 3987824 events read in total (163070ms).
[14:29:43.668] <TB2> INFO: 4644712 events read in total (190536ms).
[14:29:59.370] <TB2> INFO: 5025280 events read in total (206238ms).
[14:29:59.456] <TB2> INFO: Test took 207154ms.
[14:30:25.301] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 51.912554 .. 104.291541
[14:30:25.539] <TB2> INFO: Expecting 208000 events.
[14:30:35.211] <TB2> INFO: 208000 events read in total (9079ms).
[14:30:35.212] <TB2> INFO: Test took 9909ms.
[14:30:35.259] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 41 .. 114 (-1/-1) hits flags = 528 (plus default)
[14:30:35.275] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:30:35.275] <TB2> INFO: run 1 of 1
[14:30:35.553] <TB2> INFO: Expecting 2462720 events.
[14:31:04.037] <TB2> INFO: 682512 events read in total (27892ms).
[14:31:31.831] <TB2> INFO: 1363848 events read in total (55686ms).
[14:31:59.548] <TB2> INFO: 2038832 events read in total (83403ms).
[14:32:17.101] <TB2> INFO: 2462720 events read in total (100956ms).
[14:32:17.146] <TB2> INFO: Test took 101871ms.
[14:32:38.294] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 61.002720 .. 93.620588
[14:32:38.532] <TB2> INFO: Expecting 208000 events.
[14:32:48.212] <TB2> INFO: 208000 events read in total (9088ms).
[14:32:48.213] <TB2> INFO: Test took 9917ms.
[14:32:48.261] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 51 .. 103 (-1/-1) hits flags = 528 (plus default)
[14:32:48.274] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:32:48.275] <TB2> INFO: run 1 of 1
[14:32:48.553] <TB2> INFO: Expecting 1763840 events.
[14:33:17.082] <TB2> INFO: 688336 events read in total (27937ms).
[14:33:45.464] <TB2> INFO: 1376312 events read in total (56319ms).
[14:34:01.522] <TB2> INFO: 1763840 events read in total (72377ms).
[14:34:01.556] <TB2> INFO: Test took 73282ms.
[14:34:19.622] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 66.959458 .. 90.494160
[14:34:19.947] <TB2> INFO: Expecting 208000 events.
[14:34:29.798] <TB2> INFO: 208000 events read in total (9259ms).
[14:34:29.799] <TB2> INFO: Test took 10176ms.
[14:34:29.848] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 56 .. 100 (-1/-1) hits flags = 528 (plus default)
[14:34:29.861] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:34:29.862] <TB2> INFO: run 1 of 1
[14:34:30.139] <TB2> INFO: Expecting 1497600 events.
[14:34:58.703] <TB2> INFO: 683632 events read in total (27972ms).
[14:35:27.715] <TB2> INFO: 1366640 events read in total (56984ms).
[14:35:33.343] <TB2> INFO: 1497600 events read in total (62612ms).
[14:35:33.380] <TB2> INFO: Test took 63519ms.
[14:35:50.092] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 69.066614 .. 90.357320
[14:35:50.337] <TB2> INFO: Expecting 208000 events.
[14:35:59.926] <TB2> INFO: 208000 events read in total (8998ms).
[14:35:59.927] <TB2> INFO: Test took 9834ms.
[14:35:59.996] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 59 .. 100 (-1/-1) hits flags = 528 (plus default)
[14:36:00.010] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:36:00.011] <TB2> INFO: run 1 of 1
[14:36:00.289] <TB2> INFO: Expecting 1397760 events.
[14:36:28.623] <TB2> INFO: 673888 events read in total (27743ms).
[14:36:56.140] <TB2> INFO: 1347224 events read in total (55261ms).
[14:36:58.640] <TB2> INFO: 1397760 events read in total (57760ms).
[14:36:58.676] <TB2> INFO: Test took 58666ms.
[14:37:18.896] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[14:37:18.896] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[14:37:18.910] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:37:18.910] <TB2> INFO: run 1 of 1
[14:37:19.235] <TB2> INFO: Expecting 1364480 events.
[14:37:47.767] <TB2> INFO: 668568 events read in total (27938ms).
[14:38:15.367] <TB2> INFO: 1337216 events read in total (55538ms).
[14:38:16.916] <TB2> INFO: 1364480 events read in total (57087ms).
[14:38:16.954] <TB2> INFO: Test took 58044ms.
[14:38:32.427] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C0.dat
[14:38:32.427] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C1.dat
[14:38:32.427] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C2.dat
[14:38:32.427] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C3.dat
[14:38:32.427] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C4.dat
[14:38:32.427] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C5.dat
[14:38:32.427] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C6.dat
[14:38:32.427] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C7.dat
[14:38:32.427] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C8.dat
[14:38:32.428] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C9.dat
[14:38:32.428] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C10.dat
[14:38:32.428] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C11.dat
[14:38:32.428] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C12.dat
[14:38:32.428] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C13.dat
[14:38:32.428] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C14.dat
[14:38:32.428] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C15.dat
[14:38:32.428] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C0.dat
[14:38:32.435] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C1.dat
[14:38:32.440] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C2.dat
[14:38:32.445] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C3.dat
[14:38:32.451] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C4.dat
[14:38:32.457] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C5.dat
[14:38:32.464] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C6.dat
[14:38:32.470] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C7.dat
[14:38:32.476] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C8.dat
[14:38:32.482] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C9.dat
[14:38:32.488] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C10.dat
[14:38:32.494] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C11.dat
[14:38:32.499] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C12.dat
[14:38:32.504] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C13.dat
[14:38:32.510] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C14.dat
[14:38:32.515] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1098_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C15.dat
[14:38:32.520] <TB2> INFO: PixTestTrim80::trimTest() done
[14:38:32.520] <TB2> INFO: vtrim: 90 108 133 107 81 89 98 112 106 86 95 101 103 96 116 93
[14:38:32.520] <TB2> INFO: vthrcomp: 81 74 77 72 70 67 71 73 74 77 76 74 82 73 70 65
[14:38:32.520] <TB2> INFO: vcal mean: 79.96 80.02 79.97 79.99 79.92 79.98 79.94 79.98 79.95 80.00 80.01 79.99 79.95 79.98 80.01 79.95
[14:38:32.520] <TB2> INFO: vcal RMS: 0.78 0.75 0.88 0.76 0.81 0.76 0.77 0.77 0.72 0.83 0.75 0.80 0.78 0.71 0.83 0.73
[14:38:32.520] <TB2> INFO: bits mean: 9.80 8.80 8.98 9.58 10.49 9.84 10.41 9.49 9.17 8.61 8.86 9.61 9.72 9.26 9.55 10.04
[14:38:32.520] <TB2> INFO: bits RMS: 2.45 2.59 2.48 2.31 2.46 2.60 2.28 2.19 2.24 2.56 2.64 2.36 2.53 2.36 2.61 2.48
[14:38:32.529] <TB2> INFO: ----------------------------------------------------------------------
[14:38:32.529] <TB2> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:38:32.529] <TB2> INFO: ----------------------------------------------------------------------
[14:38:32.532] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:38:32.548] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:38:32.548] <TB2> INFO: run 1 of 1
[14:38:32.793] <TB2> INFO: Expecting 4160000 events.
[14:39:05.937] <TB2> INFO: 759380 events read in total (32552ms).
[14:39:38.520] <TB2> INFO: 1513925 events read in total (65135ms).
[14:40:10.047] <TB2> INFO: 2260720 events read in total (96662ms).
[14:40:41.737] <TB2> INFO: 3001740 events read in total (128352ms).
[14:41:13.120] <TB2> INFO: 3739660 events read in total (159735ms).
[14:41:30.947] <TB2> INFO: 4160000 events read in total (177562ms).
[14:41:31.022] <TB2> INFO: Test took 178474ms.
[14:41:54.746] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[14:41:54.759] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:41:54.759] <TB2> INFO: run 1 of 1
[14:41:54.000] <TB2> INFO: Expecting 4472000 events.
[14:42:26.984] <TB2> INFO: 716015 events read in total (31392ms).
[14:42:58.501] <TB2> INFO: 1429170 events read in total (62909ms).
[14:43:28.915] <TB2> INFO: 2137185 events read in total (93324ms).
[14:44:00.295] <TB2> INFO: 2839820 events read in total (124703ms).
[14:44:31.448] <TB2> INFO: 3540925 events read in total (155856ms).
[14:45:02.591] <TB2> INFO: 4240280 events read in total (186999ms).
[14:45:13.026] <TB2> INFO: 4472000 events read in total (197434ms).
[14:45:13.111] <TB2> INFO: Test took 198351ms.
[14:45:42.543] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[14:45:42.556] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:45:42.556] <TB2> INFO: run 1 of 1
[14:45:42.795] <TB2> INFO: Expecting 4243200 events.
[14:46:14.734] <TB2> INFO: 730575 events read in total (31348ms).
[14:46:45.897] <TB2> INFO: 1456805 events read in total (62511ms).
[14:47:17.346] <TB2> INFO: 2176840 events read in total (93960ms).
[14:47:48.670] <TB2> INFO: 2892195 events read in total (125284ms).
[14:48:19.871] <TB2> INFO: 3604640 events read in total (156485ms).
[14:48:47.761] <TB2> INFO: 4243200 events read in total (184375ms).
[14:48:47.868] <TB2> INFO: Test took 185311ms.
[14:49:16.192] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[14:49:16.205] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:49:16.205] <TB2> INFO: run 1 of 1
[14:49:16.442] <TB2> INFO: Expecting 4264000 events.
[14:49:49.089] <TB2> INFO: 729145 events read in total (32056ms).
[14:50:19.985] <TB2> INFO: 1454120 events read in total (62952ms).
[14:50:51.485] <TB2> INFO: 2173505 events read in total (94452ms).
[14:51:22.792] <TB2> INFO: 2887720 events read in total (125759ms).
[14:51:54.023] <TB2> INFO: 3598935 events read in total (156990ms).
[14:52:23.517] <TB2> INFO: 4264000 events read in total (186484ms).
[14:52:23.596] <TB2> INFO: Test took 187391ms.
[14:52:53.942] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[14:52:53.954] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:52:53.954] <TB2> INFO: run 1 of 1
[14:52:54.201] <TB2> INFO: Expecting 4264000 events.
[14:53:26.620] <TB2> INFO: 728975 events read in total (31827ms).
[14:53:57.213] <TB2> INFO: 1453845 events read in total (62420ms).
[14:54:29.854] <TB2> INFO: 2173265 events read in total (95061ms).
[14:55:02.139] <TB2> INFO: 2887525 events read in total (127346ms).
[14:55:34.340] <TB2> INFO: 3599495 events read in total (159547ms).
[14:56:04.044] <TB2> INFO: 4264000 events read in total (189251ms).
[14:56:04.249] <TB2> INFO: Test took 190294ms.
[14:56:31.029] <TB2> INFO: PixTestTrim80::trimBitTest() done
[14:56:31.031] <TB2> INFO: PixTestTrim80::doTest() done, duration: 2415 seconds
[14:56:31.853] <TB2> INFO: enter test to run
[14:56:31.853] <TB2> INFO: test: exit no parameter change
[14:56:32.038] <TB2> QUIET: Connection to board 149 closed.
[14:56:32.039] <TB2> INFO: pXar: this is the end, my friend