[11:16:09.557] <TB1> INFO: *** Welcome to pxar ***
[11:16:09.558] <TB1> INFO: *** Today: 2016/10/31
[11:16:09.564] <TB1> INFO: *** Version: c8ba-dirty
[11:16:09.565] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C15.dat
[11:16:09.565] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//tbmParameters_C1b.dat
[11:16:09.565] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//defaultMaskFile.dat
[11:16:09.565] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters_C15.dat
[11:16:09.628] <TB1> INFO: clk: 4
[11:16:09.628] <TB1> INFO: ctr: 4
[11:16:09.628] <TB1> INFO: sda: 19
[11:16:09.628] <TB1> INFO: tin: 9
[11:16:09.628] <TB1> INFO: level: 15
[11:16:09.628] <TB1> INFO: triggerdelay: 0
[11:16:09.628] <TB1> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[11:16:09.628] <TB1> INFO: Log level: INFO
[11:16:09.636] <TB1> INFO: Found DTB DTB_WXC03A
[11:16:09.648] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[11:16:09.650] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
------------------------------------------------------
[11:16:09.651] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[11:16:11.212] <TB1> INFO: DUT info:
[11:16:11.212] <TB1> INFO: The DUT currently contains the following objects:
[11:16:11.213] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[11:16:11.213] <TB1> INFO: TBM Core alpha (0): 7 registers set
[11:16:11.213] <TB1> INFO: TBM Core beta (1): 7 registers set
[11:16:11.213] <TB1> INFO: TBM Core alpha (2): 7 registers set
[11:16:11.213] <TB1> INFO: TBM Core beta (3): 7 registers set
[11:16:11.213] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:16:11.213] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.213] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:16:11.614] <TB1> INFO: enter 'restricted' command line mode
[11:16:11.614] <TB1> INFO: enter test to run
[11:16:11.614] <TB1> INFO: test: pretest no parameter change
[11:16:11.614] <TB1> INFO: running: pretest
[11:16:11.619] <TB1> INFO: ######################################################################
[11:16:11.620] <TB1> INFO: PixTestPretest::doTest()
[11:16:11.620] <TB1> INFO: ######################################################################
[11:16:11.621] <TB1> INFO: ----------------------------------------------------------------------
[11:16:11.621] <TB1> INFO: PixTestPretest::programROC()
[11:16:11.621] <TB1> INFO: ----------------------------------------------------------------------
[11:16:29.634] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:16:29.635] <TB1> INFO: IA differences per ROC: 20.9 18.5 21.7 18.5 20.1 18.5 18.5 19.3 20.9 19.3 18.5 19.3 17.7 19.3 19.3 19.3
[11:16:29.691] <TB1> INFO: ----------------------------------------------------------------------
[11:16:29.691] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:16:29.691] <TB1> INFO: ----------------------------------------------------------------------
[11:16:50.998] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 385.9 mA = 24.1188 mA/ROC
[11:16:50.999] <TB1> INFO: i(loss) [mA/ROC]: 19.3 19.3 19.3 20.1 18.5 20.1 19.3 18.5 19.3 18.5 20.1 18.5 19.3 19.3 18.5 18.5
[11:16:51.034] <TB1> INFO: ----------------------------------------------------------------------
[11:16:51.034] <TB1> INFO: PixTestPretest::findTiming()
[11:16:51.034] <TB1> INFO: ----------------------------------------------------------------------
[11:16:51.034] <TB1> INFO: PixTestCmd::init()

[11:17:23.440] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:17:23.440] <TB1> INFO: (success/tries = 100/100), width = 4
[11:17:24.945] <TB1> INFO: ----------------------------------------------------------------------
[11:17:24.945] <TB1> INFO: PixTestPretest::findWorkingPixel()
[11:17:24.945] <TB1> INFO: ----------------------------------------------------------------------
[11:17:25.040] <TB1> INFO: Expecting 231680 events.
[11:17:34.950] <TB1> INFO: 231680 events read in total (9318ms).
[11:17:34.962] <TB1> INFO: Test took 10012ms.
[11:17:35.213] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:17:35.250] <TB1> INFO: ----------------------------------------------------------------------
[11:17:35.250] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[11:17:35.250] <TB1> INFO: ----------------------------------------------------------------------
[11:17:35.345] <TB1> INFO: Expecting 231680 events.
[11:17:45.239] <TB1> INFO: 231680 events read in total (9302ms).
[11:17:45.251] <TB1> INFO: Test took 9996ms.
[11:17:45.503] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[11:17:45.503] <TB1> INFO: CalDel: 103 106 112 83 91 87 101 94 94 88 79 125 90 87 91 80
[11:17:45.503] <TB1> INFO: VthrComp: 51 51 52 51 51 51 51 51 51 51 52 51 51 51 51 51
[11:17:45.508] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C0.dat
[11:17:45.508] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C1.dat
[11:17:45.508] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C2.dat
[11:17:45.509] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C3.dat
[11:17:45.509] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C4.dat
[11:17:45.509] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C5.dat
[11:17:45.509] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C6.dat
[11:17:45.509] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C7.dat
[11:17:45.509] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C8.dat
[11:17:45.510] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C9.dat
[11:17:45.510] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C10.dat
[11:17:45.510] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C11.dat
[11:17:45.510] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C12.dat
[11:17:45.510] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C13.dat
[11:17:45.510] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C14.dat
[11:17:45.510] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters_C15.dat
[11:17:45.511] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//tbmParameters_C0a.dat
[11:17:45.511] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//tbmParameters_C0b.dat
[11:17:45.511] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//tbmParameters_C1a.dat
[11:17:45.511] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//tbmParameters_C1b.dat
[11:17:45.511] <TB1> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[11:17:45.564] <TB1> INFO: enter test to run
[11:17:45.564] <TB1> INFO: test: FullTest no parameter change
[11:17:45.564] <TB1> INFO: running: fulltest
[11:17:45.564] <TB1> INFO: ######################################################################
[11:17:45.564] <TB1> INFO: PixTestFullTest::doTest()
[11:17:45.564] <TB1> INFO: ######################################################################
[11:17:45.565] <TB1> INFO: ######################################################################
[11:17:45.566] <TB1> INFO: PixTestAlive::doTest()
[11:17:45.566] <TB1> INFO: ######################################################################
[11:17:45.567] <TB1> INFO: ----------------------------------------------------------------------
[11:17:45.567] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:17:45.567] <TB1> INFO: ----------------------------------------------------------------------
[11:17:45.805] <TB1> INFO: Expecting 41600 events.
[11:17:49.295] <TB1> INFO: 41600 events read in total (2898ms).
[11:17:49.296] <TB1> INFO: Test took 3728ms.
[11:17:49.526] <TB1> INFO: PixTestAlive::aliveTest() done
[11:17:49.526] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
[11:17:49.528] <TB1> INFO: ----------------------------------------------------------------------
[11:17:49.528] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:17:49.528] <TB1> INFO: ----------------------------------------------------------------------
[11:17:49.771] <TB1> INFO: Expecting 41600 events.
[11:17:52.729] <TB1> INFO: 41600 events read in total (2366ms).
[11:17:52.729] <TB1> INFO: Test took 3199ms.
[11:17:52.730] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:17:52.969] <TB1> INFO: PixTestAlive::maskTest() done
[11:17:52.970] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:17:52.971] <TB1> INFO: ----------------------------------------------------------------------
[11:17:52.971] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:17:52.971] <TB1> INFO: ----------------------------------------------------------------------
[11:17:53.215] <TB1> INFO: Expecting 41600 events.
[11:17:56.739] <TB1> INFO: 41600 events read in total (2932ms).
[11:17:56.740] <TB1> INFO: Test took 3766ms.
[11:17:56.970] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[11:17:56.970] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:17:56.970] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:17:56.970] <TB1> INFO: Decoding statistics:
[11:17:56.971] <TB1> INFO: General information:
[11:17:56.971] <TB1> INFO: 16bit words read: 0
[11:17:56.971] <TB1> INFO: valid events total: 0
[11:17:56.971] <TB1> INFO: empty events: 0
[11:17:56.971] <TB1> INFO: valid events with pixels: 0
[11:17:56.971] <TB1> INFO: valid pixel hits: 0
[11:17:56.971] <TB1> INFO: Event errors: 0
[11:17:56.971] <TB1> INFO: start marker: 0
[11:17:56.971] <TB1> INFO: stop marker: 0
[11:17:56.971] <TB1> INFO: overflow: 0
[11:17:56.971] <TB1> INFO: invalid 5bit words: 0
[11:17:56.971] <TB1> INFO: invalid XOR eye diagram: 0
[11:17:56.971] <TB1> INFO: frame (failed synchr.): 0
[11:17:56.971] <TB1> INFO: idle data (no TBM trl): 0
[11:17:56.971] <TB1> INFO: no data (only TBM hdr): 0
[11:17:56.971] <TB1> INFO: TBM errors: 0
[11:17:56.971] <TB1> INFO: flawed TBM headers: 0
[11:17:56.971] <TB1> INFO: flawed TBM trailers: 0
[11:17:56.971] <TB1> INFO: event ID mismatches: 0
[11:17:56.971] <TB1> INFO: ROC errors: 0
[11:17:56.971] <TB1> INFO: missing ROC header(s): 0
[11:17:56.971] <TB1> INFO: misplaced readback start: 0
[11:17:56.971] <TB1> INFO: Pixel decoding errors: 0
[11:17:56.971] <TB1> INFO: pixel data incomplete: 0
[11:17:56.972] <TB1> INFO: pixel address: 0
[11:17:56.972] <TB1> INFO: pulse height fill bit: 0
[11:17:56.972] <TB1> INFO: buffer corruption: 0
[11:17:56.981] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C15.dat
[11:17:56.982] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[11:17:56.982] <TB1> INFO: ######################################################################
[11:17:56.982] <TB1> INFO: PixTestReadback::doTest()
[11:17:56.982] <TB1> INFO: ######################################################################
[11:17:56.982] <TB1> INFO: ----------------------------------------------------------------------
[11:17:56.982] <TB1> INFO: PixTestReadback::CalibrateVd()
[11:17:56.982] <TB1> INFO: ----------------------------------------------------------------------
[11:18:06.941] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C0.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C1.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C2.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C3.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C4.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C5.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C6.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C7.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C8.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C9.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C10.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C11.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C12.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C13.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C14.dat
[11:18:06.942] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C15.dat
[11:18:06.970] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:18:06.970] <TB1> INFO: ----------------------------------------------------------------------
[11:18:06.970] <TB1> INFO: PixTestReadback::CalibrateVa()
[11:18:06.970] <TB1> INFO: ----------------------------------------------------------------------
[11:18:16.907] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C0.dat
[11:18:16.907] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C1.dat
[11:18:16.907] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C2.dat
[11:18:16.907] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C3.dat
[11:18:16.907] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C4.dat
[11:18:16.908] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C5.dat
[11:18:16.908] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C6.dat
[11:18:16.908] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C7.dat
[11:18:16.908] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C8.dat
[11:18:16.908] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C9.dat
[11:18:16.908] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C10.dat
[11:18:16.908] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C11.dat
[11:18:16.908] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C12.dat
[11:18:16.908] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C13.dat
[11:18:16.908] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C14.dat
[11:18:16.908] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C15.dat
[11:18:16.938] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:18:16.939] <TB1> INFO: ----------------------------------------------------------------------
[11:18:16.939] <TB1> INFO: PixTestReadback::readbackVbg()
[11:18:16.939] <TB1> INFO: ----------------------------------------------------------------------
[11:18:24.611] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:18:24.611] <TB1> INFO: ----------------------------------------------------------------------
[11:18:24.611] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[11:18:24.611] <TB1> INFO: ----------------------------------------------------------------------
[11:18:24.611] <TB1> INFO: Vbg will be calibrated using Vd calibration
[11:18:24.611] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 146.3calibrated Vbg = 1.17644 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 145.6calibrated Vbg = 1.17229 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 153.2calibrated Vbg = 1.17545 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 151.2calibrated Vbg = 1.17075 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 148.1calibrated Vbg = 1.17226 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 164.7calibrated Vbg = 1.17676 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 149.3calibrated Vbg = 1.17708 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 147.7calibrated Vbg = 1.17757 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 152.7calibrated Vbg = 1.17307 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 155.1calibrated Vbg = 1.17128 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 158calibrated Vbg = 1.17292 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 153.9calibrated Vbg = 1.16695 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 156.4calibrated Vbg = 1.17767 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 155.4calibrated Vbg = 1.17574 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 159.9calibrated Vbg = 1.1745 :::*/*/*/*/
[11:18:24.612] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 164calibrated Vbg = 1.17765 :::*/*/*/*/
[11:18:24.616] <TB1> INFO: ----------------------------------------------------------------------
[11:18:24.616] <TB1> INFO: PixTestReadback::CalibrateIa()
[11:18:24.616] <TB1> INFO: ----------------------------------------------------------------------
[11:21:05.434] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C0.dat
[11:21:05.434] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C1.dat
[11:21:05.434] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C2.dat
[11:21:05.435] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C3.dat
[11:21:05.435] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C4.dat
[11:21:05.435] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C5.dat
[11:21:05.435] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C6.dat
[11:21:05.435] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C7.dat
[11:21:05.435] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C8.dat
[11:21:05.435] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C9.dat
[11:21:05.435] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C10.dat
[11:21:05.435] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C11.dat
[11:21:05.435] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C12.dat
[11:21:05.435] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C13.dat
[11:21:05.435] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C14.dat
[11:21:05.435] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//readbackCal_C15.dat
[11:21:05.463] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:21:05.466] <TB1> INFO: PixTestReadback::doTest() done
[11:21:05.466] <TB1> INFO: Decoding statistics:
[11:21:05.466] <TB1> INFO: General information:
[11:21:05.466] <TB1> INFO: 16bit words read: 1536
[11:21:05.466] <TB1> INFO: valid events total: 256
[11:21:05.466] <TB1> INFO: empty events: 256
[11:21:05.466] <TB1> INFO: valid events with pixels: 0
[11:21:05.466] <TB1> INFO: valid pixel hits: 0
[11:21:05.466] <TB1> INFO: Event errors: 0
[11:21:05.466] <TB1> INFO: start marker: 0
[11:21:05.466] <TB1> INFO: stop marker: 0
[11:21:05.466] <TB1> INFO: overflow: 0
[11:21:05.466] <TB1> INFO: invalid 5bit words: 0
[11:21:05.466] <TB1> INFO: invalid XOR eye diagram: 0
[11:21:05.466] <TB1> INFO: frame (failed synchr.): 0
[11:21:05.466] <TB1> INFO: idle data (no TBM trl): 0
[11:21:05.466] <TB1> INFO: no data (only TBM hdr): 0
[11:21:05.466] <TB1> INFO: TBM errors: 0
[11:21:05.466] <TB1> INFO: flawed TBM headers: 0
[11:21:05.466] <TB1> INFO: flawed TBM trailers: 0
[11:21:05.466] <TB1> INFO: event ID mismatches: 0
[11:21:05.466] <TB1> INFO: ROC errors: 0
[11:21:05.466] <TB1> INFO: missing ROC header(s): 0
[11:21:05.466] <TB1> INFO: misplaced readback start: 0
[11:21:05.466] <TB1> INFO: Pixel decoding errors: 0
[11:21:05.466] <TB1> INFO: pixel data incomplete: 0
[11:21:05.466] <TB1> INFO: pixel address: 0
[11:21:05.466] <TB1> INFO: pulse height fill bit: 0
[11:21:05.466] <TB1> INFO: buffer corruption: 0
[11:21:05.535] <TB1> INFO: ######################################################################
[11:21:05.535] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:21:05.535] <TB1> INFO: ######################################################################
[11:21:05.538] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:21:05.590] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:21:05.590] <TB1> INFO: run 1 of 1
[11:21:05.829] <TB1> INFO: Expecting 3120000 events.
[11:21:36.734] <TB1> INFO: 662755 events read in total (30313ms).











[11:22:06.823] <TB1> INFO: 1319065 events read in total (60403ms).
[11:22:36.946] <TB1> INFO: 1971270 events read in total (90525ms).











[11:23:06.770] <TB1> INFO: 2622520 events read in total (120349ms).











[11:23:29.776] <TB1> INFO: 3120000 events read in total (143355ms).
[11:23:29.876] <TB1> INFO: Test took 144286ms.
[11:23:58.269] <TB1> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 172 seconds
[11:23:58.269] <TB1> INFO: number of dead bumps (per ROC): 20 94 66 129 114 45 33 18 11 39 64 162 154 121 32 0
[11:23:58.269] <TB1> INFO: separation cut (per ROC): 96 90 110 100 83 98 88 90 103 89 98 85 82 97 97 110
[11:23:58.269] <TB1> INFO: Decoding statistics:
[11:23:58.269] <TB1> INFO: General information:
[11:23:58.269] <TB1> INFO: 16bit words read: 0
[11:23:58.269] <TB1> INFO: valid events total: 0
[11:23:58.269] <TB1> INFO: empty events: 0
[11:23:58.269] <TB1> INFO: valid events with pixels: 0
[11:23:58.269] <TB1> INFO: valid pixel hits: 0
[11:23:58.269] <TB1> INFO: Event errors: 0
[11:23:58.269] <TB1> INFO: start marker: 0
[11:23:58.269] <TB1> INFO: stop marker: 0
[11:23:58.269] <TB1> INFO: overflow: 0
[11:23:58.269] <TB1> INFO: invalid 5bit words: 0
[11:23:58.269] <TB1> INFO: invalid XOR eye diagram: 0
[11:23:58.269] <TB1> INFO: frame (failed synchr.): 0
[11:23:58.269] <TB1> INFO: idle data (no TBM trl): 0
[11:23:58.269] <TB1> INFO: no data (only TBM hdr): 0
[11:23:58.269] <TB1> INFO: TBM errors: 0
[11:23:58.269] <TB1> INFO: flawed TBM headers: 0
[11:23:58.269] <TB1> INFO: flawed TBM trailers: 0
[11:23:58.269] <TB1> INFO: event ID mismatches: 0
[11:23:58.269] <TB1> INFO: ROC errors: 0
[11:23:58.269] <TB1> INFO: missing ROC header(s): 0
[11:23:58.269] <TB1> INFO: misplaced readback start: 0
[11:23:58.269] <TB1> INFO: Pixel decoding errors: 0
[11:23:58.269] <TB1> INFO: pixel data incomplete: 0
[11:23:58.269] <TB1> INFO: pixel address: 0
[11:23:58.269] <TB1> INFO: pulse height fill bit: 0
[11:23:58.269] <TB1> INFO: buffer corruption: 0
[11:23:58.328] <TB1> INFO: ######################################################################
[11:23:58.328] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:23:58.328] <TB1> INFO: ######################################################################
[11:23:58.328] <TB1> INFO: ----------------------------------------------------------------------
[11:23:58.328] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:23:58.328] <TB1> INFO: ----------------------------------------------------------------------
[11:23:58.328] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[11:23:58.342] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[11:23:58.343] <TB1> INFO: run 1 of 1
[11:23:58.587] <TB1> INFO: Expecting 36608000 events.
[11:24:21.860] <TB1> INFO: 646000 events read in total (22681ms).
[11:24:44.223] <TB1> INFO: 1288850 events read in total (45044ms).
[11:25:06.644] <TB1> INFO: 1931050 events read in total (67465ms).
[11:25:29.190] <TB1> INFO: 2572700 events read in total (90011ms).
[11:25:51.834] <TB1> INFO: 3216050 events read in total (112655ms).
[11:26:14.293] <TB1> INFO: 3859550 events read in total (135114ms).
[11:26:36.876] <TB1> INFO: 4503250 events read in total (157697ms).
[11:26:59.358] <TB1> INFO: 5145750 events read in total (180179ms).
[11:27:22.021] <TB1> INFO: 5787350 events read in total (202842ms).
[11:27:44.604] <TB1> INFO: 6430500 events read in total (225425ms).
[11:28:07.140] <TB1> INFO: 7073650 events read in total (247961ms).
[11:28:29.605] <TB1> INFO: 7715650 events read in total (270426ms).
[11:28:52.865] <TB1> INFO: 8357450 events read in total (293686ms).
[11:29:15.608] <TB1> INFO: 9000800 events read in total (316429ms).
[11:29:38.123] <TB1> INFO: 9643900 events read in total (338944ms).
[11:30:00.623] <TB1> INFO: 10287200 events read in total (361444ms).
[11:30:23.261] <TB1> INFO: 10929300 events read in total (384082ms).
[11:30:45.909] <TB1> INFO: 11572400 events read in total (406730ms).
[11:31:08.411] <TB1> INFO: 12217000 events read in total (429232ms).
[11:31:31.172] <TB1> INFO: 12861750 events read in total (451993ms).
[11:31:53.671] <TB1> INFO: 13503800 events read in total (474492ms).
[11:32:16.131] <TB1> INFO: 14145850 events read in total (496952ms).
[11:32:38.577] <TB1> INFO: 14787950 events read in total (519398ms).
[11:33:00.905] <TB1> INFO: 15429700 events read in total (541726ms).
[11:33:23.383] <TB1> INFO: 16070100 events read in total (564204ms).
[11:33:45.876] <TB1> INFO: 16711150 events read in total (586697ms).
[11:34:08.345] <TB1> INFO: 17353050 events read in total (609166ms).
[11:34:30.871] <TB1> INFO: 17994200 events read in total (631692ms).
[11:34:53.317] <TB1> INFO: 18634950 events read in total (654139ms).
[11:35:16.221] <TB1> INFO: 19275350 events read in total (677042ms).
[11:35:38.905] <TB1> INFO: 19914050 events read in total (699726ms).
[11:36:01.687] <TB1> INFO: 20554550 events read in total (722508ms).
[11:36:24.159] <TB1> INFO: 21194900 events read in total (744980ms).
[11:36:46.678] <TB1> INFO: 21832500 events read in total (767499ms).
[11:37:09.397] <TB1> INFO: 22470250 events read in total (790218ms).
[11:37:32.025] <TB1> INFO: 23108600 events read in total (812846ms).
[11:37:54.430] <TB1> INFO: 23748750 events read in total (835251ms).
[11:38:16.762] <TB1> INFO: 24387350 events read in total (857583ms).
[11:38:38.957] <TB1> INFO: 25025100 events read in total (879778ms).
[11:39:01.304] <TB1> INFO: 25664050 events read in total (902125ms).
[11:39:23.802] <TB1> INFO: 26301400 events read in total (924623ms).
[11:39:46.142] <TB1> INFO: 26940300 events read in total (946963ms).
[11:40:08.604] <TB1> INFO: 27578000 events read in total (969425ms).
[11:40:31.279] <TB1> INFO: 28214950 events read in total (992100ms).
[11:40:54.036] <TB1> INFO: 28852450 events read in total (1014857ms).
[11:41:16.595] <TB1> INFO: 29490150 events read in total (1037416ms).
[11:41:39.111] <TB1> INFO: 30126700 events read in total (1059932ms).
[11:42:01.620] <TB1> INFO: 30763300 events read in total (1082441ms).
[11:42:24.221] <TB1> INFO: 31400700 events read in total (1105042ms).
[11:42:46.754] <TB1> INFO: 32036850 events read in total (1127575ms).
[11:43:09.454] <TB1> INFO: 32674700 events read in total (1150275ms).
[11:43:31.997] <TB1> INFO: 33313250 events read in total (1172818ms).
[11:43:54.497] <TB1> INFO: 33950100 events read in total (1195318ms).
[11:44:17.069] <TB1> INFO: 34588800 events read in total (1217890ms).
[11:44:39.573] <TB1> INFO: 35226350 events read in total (1240394ms).
[11:45:02.101] <TB1> INFO: 35864850 events read in total (1262922ms).
[11:45:24.775] <TB1> INFO: 36507800 events read in total (1285596ms).
[11:45:28.576] <TB1> INFO: 36608000 events read in total (1289397ms).
[11:45:28.675] <TB1> INFO: Test took 1290333ms.
[11:45:29.152] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:31.017] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:33.096] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:35.303] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:37.417] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:39.663] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:41.656] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:43.558] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:45.317] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:46.000] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:49.206] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:51.059] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:52.533] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:54.051] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:55.547] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:57.057] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:45:58.643] <TB1> INFO: PixTestScurves::scurves() done
[11:45:58.643] <TB1> INFO: Vcal mean: 106.69 95.50 125.98 114.49 92.64 105.91 102.36 97.33 107.70 101.63 109.30 98.99 105.35 114.05 112.01 108.73
[11:45:58.643] <TB1> INFO: Vcal RMS: 5.05 4.74 6.85 5.65 5.12 4.66 4.95 4.77 5.38 5.59 5.49 5.65 6.00 5.78 5.01 4.83
[11:45:58.643] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1320 seconds
[11:45:58.643] <TB1> INFO: Decoding statistics:
[11:45:58.643] <TB1> INFO: General information:
[11:45:58.643] <TB1> INFO: 16bit words read: 0
[11:45:58.643] <TB1> INFO: valid events total: 0
[11:45:58.643] <TB1> INFO: empty events: 0
[11:45:58.643] <TB1> INFO: valid events with pixels: 0
[11:45:58.643] <TB1> INFO: valid pixel hits: 0
[11:45:58.644] <TB1> INFO: Event errors: 0
[11:45:58.644] <TB1> INFO: start marker: 0
[11:45:58.644] <TB1> INFO: stop marker: 0
[11:45:58.644] <TB1> INFO: overflow: 0
[11:45:58.644] <TB1> INFO: invalid 5bit words: 0
[11:45:58.644] <TB1> INFO: invalid XOR eye diagram: 0
[11:45:58.644] <TB1> INFO: frame (failed synchr.): 0
[11:45:58.644] <TB1> INFO: idle data (no TBM trl): 0
[11:45:58.644] <TB1> INFO: no data (only TBM hdr): 0
[11:45:58.644] <TB1> INFO: TBM errors: 0
[11:45:58.644] <TB1> INFO: flawed TBM headers: 0
[11:45:58.644] <TB1> INFO: flawed TBM trailers: 0
[11:45:58.644] <TB1> INFO: event ID mismatches: 0
[11:45:58.644] <TB1> INFO: ROC errors: 0
[11:45:58.644] <TB1> INFO: missing ROC header(s): 0
[11:45:58.644] <TB1> INFO: misplaced readback start: 0
[11:45:58.644] <TB1> INFO: Pixel decoding errors: 0
[11:45:58.644] <TB1> INFO: pixel data incomplete: 0
[11:45:58.644] <TB1> INFO: pixel address: 0
[11:45:58.644] <TB1> INFO: pulse height fill bit: 0
[11:45:58.644] <TB1> INFO: buffer corruption: 0
[11:45:58.711] <TB1> INFO: ######################################################################
[11:45:58.711] <TB1> INFO: PixTestTrim::doTest()
[11:45:58.711] <TB1> INFO: ######################################################################
[11:45:58.713] <TB1> INFO: ----------------------------------------------------------------------
[11:45:58.713] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[11:45:58.713] <TB1> INFO: ----------------------------------------------------------------------
[11:45:58.755] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[11:45:58.755] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:45:58.768] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:45:58.768] <TB1> INFO: run 1 of 1
[11:45:59.011] <TB1> INFO: Expecting 5025280 events.
[11:46:29.303] <TB1> INFO: 805944 events read in total (29690ms).
[11:46:58.944] <TB1> INFO: 1609224 events read in total (59332ms).
[11:47:28.670] <TB1> INFO: 2411072 events read in total (89058ms).
[11:47:58.634] <TB1> INFO: 3209520 events read in total (119021ms).
[11:48:28.271] <TB1> INFO: 4005456 events read in total (148658ms).
[11:48:58.008] <TB1> INFO: 4799432 events read in total (178395ms).
[11:49:07.041] <TB1> INFO: 5025280 events read in total (187428ms).
[11:49:07.099] <TB1> INFO: Test took 188332ms.
[11:49:31.887] <TB1> INFO: ROC 0 VthrComp = 114
[11:49:31.887] <TB1> INFO: ROC 1 VthrComp = 107
[11:49:31.887] <TB1> INFO: ROC 2 VthrComp = 129
[11:49:31.887] <TB1> INFO: ROC 3 VthrComp = 122
[11:49:31.887] <TB1> INFO: ROC 4 VthrComp = 102
[11:49:31.887] <TB1> INFO: ROC 5 VthrComp = 125
[11:49:31.887] <TB1> INFO: ROC 6 VthrComp = 106
[11:49:31.888] <TB1> INFO: ROC 7 VthrComp = 106
[11:49:31.888] <TB1> INFO: ROC 8 VthrComp = 119
[11:49:31.888] <TB1> INFO: ROC 9 VthrComp = 109
[11:49:31.888] <TB1> INFO: ROC 10 VthrComp = 121
[11:49:31.888] <TB1> INFO: ROC 11 VthrComp = 107
[11:49:31.888] <TB1> INFO: ROC 12 VthrComp = 109
[11:49:31.889] <TB1> INFO: ROC 13 VthrComp = 119
[11:49:31.889] <TB1> INFO: ROC 14 VthrComp = 122
[11:49:31.889] <TB1> INFO: ROC 15 VthrComp = 121
[11:49:32.163] <TB1> INFO: Expecting 41600 events.
[11:49:35.631] <TB1> INFO: 41600 events read in total (2876ms).
[11:49:35.632] <TB1> INFO: Test took 3742ms.
[11:49:35.641] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[11:49:35.641] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:49:35.653] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:49:35.653] <TB1> INFO: run 1 of 1
[11:49:35.931] <TB1> INFO: Expecting 5025280 events.
[11:50:02.203] <TB1> INFO: 586992 events read in total (25680ms).
[11:50:28.241] <TB1> INFO: 1174408 events read in total (51719ms).
[11:50:54.454] <TB1> INFO: 1762216 events read in total (77931ms).
[11:51:20.091] <TB1> INFO: 2349272 events read in total (103568ms).
[11:51:45.404] <TB1> INFO: 2935128 events read in total (128881ms).
[11:52:11.338] <TB1> INFO: 3519656 events read in total (154815ms).
[11:52:36.796] <TB1> INFO: 4103288 events read in total (180273ms).
[11:53:03.157] <TB1> INFO: 4686464 events read in total (206634ms).
[11:53:18.458] <TB1> INFO: 5025280 events read in total (221935ms).
[11:53:18.593] <TB1> INFO: Test took 222940ms.
[11:53:45.358] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 57.7498 for pixel 11/14 mean/min/max = 44.9329/31.9939/57.872
[11:53:45.359] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 56.3843 for pixel 23/20 mean/min/max = 45.4712/34.2722/56.6702
[11:53:45.359] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 63.7709 for pixel 1/17 mean/min/max = 48.4075/32.6339/64.1811
[11:53:45.359] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 59.8461 for pixel 37/10 mean/min/max = 45.6669/31.3898/59.9439
[11:53:45.360] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 57.9656 for pixel 0/41 mean/min/max = 45.5843/32.9253/58.2433
[11:53:45.360] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 54.8936 for pixel 17/1 mean/min/max = 42.9553/30.8183/55.0923
[11:53:45.361] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 58.8023 for pixel 1/58 mean/min/max = 46.6104/34.3213/58.8995
[11:53:45.361] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 56.9007 for pixel 41/13 mean/min/max = 45.6399/34.3536/56.9263
[11:53:45.362] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 58.1481 for pixel 12/3 mean/min/max = 44.6136/30.9631/58.2641
[11:53:45.362] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 59.6558 for pixel 14/16 mean/min/max = 46.7694/33.8494/59.6893
[11:53:45.363] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 59.2412 for pixel 10/13 mean/min/max = 45.3674/31.4894/59.2453
[11:53:45.363] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 57.9106 for pixel 5/6 mean/min/max = 46.3128/34.5185/58.107
[11:53:45.364] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 62.2774 for pixel 10/5 mean/min/max = 47.8272/33.2855/62.369
[11:53:45.364] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 60.8255 for pixel 11/75 mean/min/max = 45.8043/30.6683/60.9403
[11:53:45.364] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 59.0462 for pixel 0/14 mean/min/max = 45.2087/31.1661/59.2514
[11:53:45.365] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 57.765 for pixel 12/78 mean/min/max = 45.0375/32.2085/57.8664
[11:53:45.365] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:53:45.453] <TB1> INFO: Expecting 411648 events.
[11:53:55.107] <TB1> INFO: 411648 events read in total (9062ms).
[11:53:55.116] <TB1> INFO: Expecting 411648 events.
[11:54:04.404] <TB1> INFO: 411648 events read in total (8884ms).
[11:54:04.414] <TB1> INFO: Expecting 411648 events.
[11:54:13.788] <TB1> INFO: 411648 events read in total (8971ms).
[11:54:13.810] <TB1> INFO: Expecting 411648 events.
[11:54:23.135] <TB1> INFO: 411648 events read in total (8922ms).
[11:54:23.158] <TB1> INFO: Expecting 411648 events.
[11:54:32.555] <TB1> INFO: 411648 events read in total (8993ms).
[11:54:32.576] <TB1> INFO: Expecting 411648 events.
[11:54:41.928] <TB1> INFO: 411648 events read in total (8949ms).
[11:54:41.952] <TB1> INFO: Expecting 411648 events.
[11:54:51.317] <TB1> INFO: 411648 events read in total (8962ms).
[11:54:51.341] <TB1> INFO: Expecting 411648 events.
[11:55:00.704] <TB1> INFO: 411648 events read in total (8960ms).
[11:55:00.733] <TB1> INFO: Expecting 411648 events.
[11:55:10.106] <TB1> INFO: 411648 events read in total (8970ms).
[11:55:10.144] <TB1> INFO: Expecting 411648 events.
[11:55:19.554] <TB1> INFO: 411648 events read in total (9007ms).
[11:55:19.606] <TB1> INFO: Expecting 411648 events.
[11:55:28.954] <TB1> INFO: 411648 events read in total (8945ms).
[11:55:28.996] <TB1> INFO: Expecting 411648 events.
[11:55:38.338] <TB1> INFO: 411648 events read in total (8939ms).
[11:55:38.390] <TB1> INFO: Expecting 411648 events.
[11:55:47.564] <TB1> INFO: 411648 events read in total (8771ms).
[11:55:47.609] <TB1> INFO: Expecting 411648 events.
[11:55:56.891] <TB1> INFO: 411648 events read in total (8879ms).
[11:55:57.038] <TB1> INFO: Expecting 411648 events.
[11:56:06.457] <TB1> INFO: 411648 events read in total (9015ms).
[11:56:06.520] <TB1> INFO: Expecting 411648 events.
[11:56:15.707] <TB1> INFO: 411648 events read in total (8784ms).
[11:56:15.841] <TB1> INFO: Test took 150476ms.
[11:56:16.724] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[11:56:16.737] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:56:16.737] <TB1> INFO: run 1 of 1
[11:56:16.974] <TB1> INFO: Expecting 5025280 events.
[11:56:43.217] <TB1> INFO: 583848 events read in total (25652ms).
[11:57:09.005] <TB1> INFO: 1166800 events read in total (51440ms).
[11:57:34.761] <TB1> INFO: 1749936 events read in total (77196ms).
[11:58:00.787] <TB1> INFO: 2332360 events read in total (103222ms).
[11:58:26.775] <TB1> INFO: 2913608 events read in total (129210ms).
[11:58:52.800] <TB1> INFO: 3494512 events read in total (155235ms).
[11:59:19.279] <TB1> INFO: 4074840 events read in total (181714ms).
[11:59:45.597] <TB1> INFO: 4654952 events read in total (208032ms).
[12:00:02.919] <TB1> INFO: 5025280 events read in total (225354ms).
[12:00:03.080] <TB1> INFO: Test took 226344ms.
[12:00:26.697] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 4.785841 .. 147.742925
[12:00:26.939] <TB1> INFO: Expecting 208000 events.
[12:00:36.623] <TB1> INFO: 208000 events read in total (9093ms).
[12:00:36.624] <TB1> INFO: Test took 9925ms.
[12:00:36.693] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 4 .. 157 (-1/-1) hits flags = 528 (plus default)
[12:00:36.707] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:00:36.707] <TB1> INFO: run 1 of 1
[12:00:36.985] <TB1> INFO: Expecting 5125120 events.
[12:01:03.818] <TB1> INFO: 579032 events read in total (26241ms).
[12:01:29.111] <TB1> INFO: 1158200 events read in total (51534ms).
[12:01:54.679] <TB1> INFO: 1737480 events read in total (77102ms).
[12:02:20.330] <TB1> INFO: 2316952 events read in total (102753ms).
[12:02:46.170] <TB1> INFO: 2896744 events read in total (128593ms).
[12:03:11.613] <TB1> INFO: 3475720 events read in total (154036ms).
[12:03:37.672] <TB1> INFO: 4054360 events read in total (180095ms).
[12:04:03.599] <TB1> INFO: 4632368 events read in total (206022ms).
[12:04:26.164] <TB1> INFO: 5125120 events read in total (228587ms).
[12:04:26.345] <TB1> INFO: Test took 229638ms.
[12:04:51.968] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 26.931054 .. 43.307719
[12:04:52.209] <TB1> INFO: Expecting 208000 events.
[12:05:02.036] <TB1> INFO: 208000 events read in total (9235ms).
[12:05:02.037] <TB1> INFO: Test took 10067ms.
[12:05:02.084] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 53 (-1/-1) hits flags = 528 (plus default)
[12:05:02.097] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:05:02.097] <TB1> INFO: run 1 of 1
[12:05:02.376] <TB1> INFO: Expecting 1264640 events.
[12:05:30.698] <TB1> INFO: 671744 events read in total (27731ms).
[12:05:56.223] <TB1> INFO: 1264640 events read in total (53256ms).
[12:05:56.261] <TB1> INFO: Test took 54164ms.
[12:06:08.273] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 24.740861 .. 44.633658
[12:06:08.511] <TB1> INFO: Expecting 208000 events.
[12:06:18.302] <TB1> INFO: 208000 events read in total (9199ms).
[12:06:18.303] <TB1> INFO: Test took 10029ms.
[12:06:18.352] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 14 .. 54 (-1/-1) hits flags = 528 (plus default)
[12:06:18.365] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:06:18.365] <TB1> INFO: run 1 of 1
[12:06:18.644] <TB1> INFO: Expecting 1364480 events.
[12:06:46.725] <TB1> INFO: 673672 events read in total (27489ms).
[12:07:15.624] <TB1> INFO: 1346752 events read in total (56388ms).
[12:07:16.850] <TB1> INFO: 1364480 events read in total (57615ms).
[12:07:16.884] <TB1> INFO: Test took 58520ms.
[12:07:31.543] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 23.823543 .. 41.565946
[12:07:31.782] <TB1> INFO: Expecting 208000 events.
[12:07:41.535] <TB1> INFO: 208000 events read in total (9161ms).
[12:07:41.536] <TB1> INFO: Test took 9991ms.
[12:07:41.583] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 13 .. 51 (-1/-1) hits flags = 528 (plus default)
[12:07:41.596] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:07:41.596] <TB1> INFO: run 1 of 1
[12:07:41.875] <TB1> INFO: Expecting 1297920 events.
[12:08:10.985] <TB1> INFO: 694040 events read in total (28519ms).
[12:08:36.801] <TB1> INFO: 1297920 events read in total (54335ms).
[12:08:36.844] <TB1> INFO: Test took 55248ms.
[12:08:48.647] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:08:48.647] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:08:48.660] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:08:48.660] <TB1> INFO: run 1 of 1
[12:08:48.895] <TB1> INFO: Expecting 1364480 events.
[12:09:17.372] <TB1> INFO: 667496 events read in total (27885ms).
[12:09:45.463] <TB1> INFO: 1334216 events read in total (55976ms).
[12:09:47.158] <TB1> INFO: 1364480 events read in total (57671ms).
[12:09:47.186] <TB1> INFO: Test took 58526ms.
[12:10:00.568] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C0.dat
[12:10:00.568] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C1.dat
[12:10:00.569] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C2.dat
[12:10:00.569] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C3.dat
[12:10:00.569] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C4.dat
[12:10:00.569] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C5.dat
[12:10:00.569] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C6.dat
[12:10:00.569] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C7.dat
[12:10:00.570] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C8.dat
[12:10:00.570] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C9.dat
[12:10:00.570] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C10.dat
[12:10:00.570] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C11.dat
[12:10:00.570] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C12.dat
[12:10:00.570] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C13.dat
[12:10:00.571] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C14.dat
[12:10:00.571] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C15.dat
[12:10:00.571] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C0.dat
[12:10:00.581] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C1.dat
[12:10:00.587] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C2.dat
[12:10:00.592] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C3.dat
[12:10:00.597] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C4.dat
[12:10:00.602] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C5.dat
[12:10:00.606] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C6.dat
[12:10:00.611] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C7.dat
[12:10:00.616] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C8.dat
[12:10:00.620] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C9.dat
[12:10:00.625] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C10.dat
[12:10:00.630] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C11.dat
[12:10:00.635] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C12.dat
[12:10:00.640] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C13.dat
[12:10:00.644] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C14.dat
[12:10:00.649] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//trimParameters35_C15.dat
[12:10:00.653] <TB1> INFO: PixTestTrim::trimTest() done
[12:10:00.653] <TB1> INFO: vtrim: 124 111 146 133 109 112 122 107 129 131 159 108 135 150 114 127
[12:10:00.653] <TB1> INFO: vthrcomp: 114 107 129 122 102 125 106 106 119 109 121 107 109 119 122 121
[12:10:00.653] <TB1> INFO: vcal mean: 34.95 35.01 35.01 34.96 34.99 34.91 35.02 35.01 34.97 35.04 34.96 34.99 34.94 34.93 35.00 34.96
[12:10:00.653] <TB1> INFO: vcal RMS: 0.96 0.84 1.04 1.05 0.93 0.99 0.92 0.87 1.15 0.97 1.13 0.93 1.05 1.14 1.06 1.00
[12:10:00.653] <TB1> INFO: bits mean: 9.69 9.22 8.67 10.00 8.85 10.28 8.79 9.29 9.73 9.00 10.12 8.80 9.00 10.09 9.56 9.74
[12:10:00.653] <TB1> INFO: bits RMS: 2.65 2.42 2.81 2.55 2.83 2.62 2.64 2.48 2.81 2.59 2.49 2.61 2.64 2.56 2.80 2.59
[12:10:00.661] <TB1> INFO: ----------------------------------------------------------------------
[12:10:00.661] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:10:00.661] <TB1> INFO: ----------------------------------------------------------------------
[12:10:00.663] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:10:00.680] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:10:00.680] <TB1> INFO: run 1 of 1
[12:10:00.921] <TB1> INFO: Expecting 4160000 events.
[12:10:33.448] <TB1> INFO: 716690 events read in total (31935ms).
[12:11:05.172] <TB1> INFO: 1433565 events read in total (63659ms).
[12:11:36.692] <TB1> INFO: 2146215 events read in total (95179ms).
[12:12:08.204] <TB1> INFO: 2855600 events read in total (126691ms).
[12:12:39.361] <TB1> INFO: 3562090 events read in total (157848ms).
[12:13:05.713] <TB1> INFO: 4160000 events read in total (184200ms).
[12:13:05.885] <TB1> INFO: Test took 185204ms.
[12:13:35.136] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[12:13:35.150] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:13:35.150] <TB1> INFO: run 1 of 1
[12:13:35.430] <TB1> INFO: Expecting 4097600 events.
[12:14:07.407] <TB1> INFO: 697450 events read in total (31385ms).
[12:14:38.704] <TB1> INFO: 1395530 events read in total (62682ms).
[12:15:09.779] <TB1> INFO: 2090330 events read in total (93757ms).
[12:15:41.430] <TB1> INFO: 2782515 events read in total (125408ms).
[12:16:12.127] <TB1> INFO: 3472580 events read in total (156105ms).
[12:16:40.757] <TB1> INFO: 4097600 events read in total (184735ms).
[12:16:40.939] <TB1> INFO: Test took 185789ms.
[12:17:10.191] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 184 (-1/-1) hits flags = 528 (plus default)
[12:17:10.204] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:17:10.204] <TB1> INFO: run 1 of 1
[12:17:10.445] <TB1> INFO: Expecting 3848000 events.
[12:17:42.799] <TB1> INFO: 712345 events read in total (31762ms).
[12:18:14.424] <TB1> INFO: 1424705 events read in total (63387ms).
[12:18:46.198] <TB1> INFO: 2133295 events read in total (95161ms).
[12:19:17.729] <TB1> INFO: 2838975 events read in total (126692ms).
[12:19:48.791] <TB1> INFO: 3542505 events read in total (157754ms).
[12:20:03.080] <TB1> INFO: 3848000 events read in total (172043ms).
[12:20:03.157] <TB1> INFO: Test took 172953ms.
[12:20:30.592] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 184 (-1/-1) hits flags = 528 (plus default)
[12:20:30.606] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:20:30.606] <TB1> INFO: run 1 of 1
[12:20:30.846] <TB1> INFO: Expecting 3848000 events.
[12:21:02.830] <TB1> INFO: 712560 events read in total (31392ms).
[12:21:34.307] <TB1> INFO: 1424970 events read in total (62869ms).
[12:22:05.934] <TB1> INFO: 2133430 events read in total (94496ms).
[12:22:37.780] <TB1> INFO: 2839225 events read in total (126342ms).
[12:23:09.435] <TB1> INFO: 3542790 events read in total (157997ms).
[12:23:23.214] <TB1> INFO: 3848000 events read in total (171776ms).
[12:23:23.291] <TB1> INFO: Test took 172685ms.
[12:23:48.459] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 185 (-1/-1) hits flags = 528 (plus default)
[12:23:48.473] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:23:48.473] <TB1> INFO: run 1 of 1
[12:23:48.729] <TB1> INFO: Expecting 3868800 events.
[12:24:20.473] <TB1> INFO: 711370 events read in total (31152ms).
[12:24:51.485] <TB1> INFO: 1422670 events read in total (62164ms).
[12:25:22.635] <TB1> INFO: 2129755 events read in total (93314ms).
[12:25:53.537] <TB1> INFO: 2834380 events read in total (124216ms).
[12:26:24.460] <TB1> INFO: 3536630 events read in total (155139ms).
[12:26:39.923] <TB1> INFO: 3868800 events read in total (170602ms).
[12:26:40.064] <TB1> INFO: Test took 171591ms.
[12:27:07.462] <TB1> INFO: PixTestTrim::trimBitTest() done
[12:27:07.463] <TB1> INFO: PixTestTrim::doTest() done, duration: 2468 seconds
[12:27:07.463] <TB1> INFO: Decoding statistics:
[12:27:07.463] <TB1> INFO: General information:
[12:27:07.463] <TB1> INFO: 16bit words read: 0
[12:27:07.463] <TB1> INFO: valid events total: 0
[12:27:07.463] <TB1> INFO: empty events: 0
[12:27:07.463] <TB1> INFO: valid events with pixels: 0
[12:27:07.463] <TB1> INFO: valid pixel hits: 0
[12:27:07.463] <TB1> INFO: Event errors: 0
[12:27:07.463] <TB1> INFO: start marker: 0
[12:27:07.463] <TB1> INFO: stop marker: 0
[12:27:07.463] <TB1> INFO: overflow: 0
[12:27:07.463] <TB1> INFO: invalid 5bit words: 0
[12:27:07.463] <TB1> INFO: invalid XOR eye diagram: 0
[12:27:07.463] <TB1> INFO: frame (failed synchr.): 0
[12:27:07.463] <TB1> INFO: idle data (no TBM trl): 0
[12:27:07.463] <TB1> INFO: no data (only TBM hdr): 0
[12:27:07.463] <TB1> INFO: TBM errors: 0
[12:27:07.463] <TB1> INFO: flawed TBM headers: 0
[12:27:07.463] <TB1> INFO: flawed TBM trailers: 0
[12:27:07.463] <TB1> INFO: event ID mismatches: 0
[12:27:07.463] <TB1> INFO: ROC errors: 0
[12:27:07.463] <TB1> INFO: missing ROC header(s): 0
[12:27:07.463] <TB1> INFO: misplaced readback start: 0
[12:27:07.463] <TB1> INFO: Pixel decoding errors: 0
[12:27:07.463] <TB1> INFO: pixel data incomplete: 0
[12:27:07.463] <TB1> INFO: pixel address: 0
[12:27:07.463] <TB1> INFO: pulse height fill bit: 0
[12:27:07.463] <TB1> INFO: buffer corruption: 0
[12:27:08.076] <TB1> INFO: ######################################################################
[12:27:08.076] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:27:08.076] <TB1> INFO: ######################################################################
[12:27:08.331] <TB1> INFO: Expecting 41600 events.
[12:27:11.830] <TB1> INFO: 41600 events read in total (2907ms).
[12:27:11.831] <TB1> INFO: Test took 3753ms.
[12:27:12.278] <TB1> INFO: Expecting 41600 events.
[12:27:15.813] <TB1> INFO: 41600 events read in total (2943ms).
[12:27:15.813] <TB1> INFO: Test took 3779ms.
[12:27:16.103] <TB1> INFO: Expecting 41600 events.
[12:27:19.884] <TB1> INFO: 41600 events read in total (3190ms).
[12:27:19.885] <TB1> INFO: Test took 4048ms.
[12:27:20.177] <TB1> INFO: Expecting 41600 events.
[12:27:23.815] <TB1> INFO: 41600 events read in total (3046ms).
[12:27:23.816] <TB1> INFO: Test took 3904ms.
[12:27:24.106] <TB1> INFO: Expecting 41600 events.
[12:27:27.710] <TB1> INFO: 41600 events read in total (3012ms).
[12:27:27.711] <TB1> INFO: Test took 3870ms.
[12:27:28.005] <TB1> INFO: Expecting 41600 events.
[12:27:31.662] <TB1> INFO: 41600 events read in total (3065ms).
[12:27:31.663] <TB1> INFO: Test took 3923ms.
[12:27:31.952] <TB1> INFO: Expecting 41600 events.
[12:27:35.622] <TB1> INFO: 41600 events read in total (3078ms).
[12:27:35.623] <TB1> INFO: Test took 3936ms.
[12:27:35.926] <TB1> INFO: Expecting 41600 events.
[12:27:39.593] <TB1> INFO: 41600 events read in total (3075ms).
[12:27:39.593] <TB1> INFO: Test took 3946ms.
[12:27:39.885] <TB1> INFO: Expecting 41600 events.
[12:27:43.417] <TB1> INFO: 41600 events read in total (2940ms).
[12:27:43.418] <TB1> INFO: Test took 3798ms.
[12:27:43.707] <TB1> INFO: Expecting 41600 events.
[12:27:47.350] <TB1> INFO: 41600 events read in total (3052ms).
[12:27:47.351] <TB1> INFO: Test took 3909ms.
[12:27:47.640] <TB1> INFO: Expecting 41600 events.
[12:27:51.173] <TB1> INFO: 41600 events read in total (2941ms).
[12:27:51.174] <TB1> INFO: Test took 3799ms.
[12:27:51.463] <TB1> INFO: Expecting 41600 events.
[12:27:55.155] <TB1> INFO: 41600 events read in total (3100ms).
[12:27:55.157] <TB1> INFO: Test took 3959ms.
[12:27:55.504] <TB1> INFO: Expecting 41600 events.
[12:27:59.053] <TB1> INFO: 41600 events read in total (2958ms).
[12:27:59.054] <TB1> INFO: Test took 3868ms.
[12:27:59.345] <TB1> INFO: Expecting 41600 events.
[12:28:02.957] <TB1> INFO: 41600 events read in total (3021ms).
[12:28:02.958] <TB1> INFO: Test took 3878ms.
[12:28:03.250] <TB1> INFO: Expecting 41600 events.
[12:28:06.885] <TB1> INFO: 41600 events read in total (3043ms).
[12:28:06.886] <TB1> INFO: Test took 3901ms.
[12:28:07.175] <TB1> INFO: Expecting 41600 events.
[12:28:10.719] <TB1> INFO: 41600 events read in total (2952ms).
[12:28:10.720] <TB1> INFO: Test took 3810ms.
[12:28:11.010] <TB1> INFO: Expecting 41600 events.
[12:28:14.551] <TB1> INFO: 41600 events read in total (2950ms).
[12:28:14.552] <TB1> INFO: Test took 3807ms.
[12:28:14.855] <TB1> INFO: Expecting 41600 events.
[12:28:18.495] <TB1> INFO: 41600 events read in total (3048ms).
[12:28:18.495] <TB1> INFO: Test took 3919ms.
[12:28:18.785] <TB1> INFO: Expecting 41600 events.
[12:28:22.317] <TB1> INFO: 41600 events read in total (2941ms).
[12:28:22.318] <TB1> INFO: Test took 3799ms.
[12:28:22.610] <TB1> INFO: Expecting 41600 events.
[12:28:26.249] <TB1> INFO: 41600 events read in total (3047ms).
[12:28:26.250] <TB1> INFO: Test took 3905ms.
[12:28:26.540] <TB1> INFO: Expecting 41600 events.
[12:28:30.099] <TB1> INFO: 41600 events read in total (2967ms).
[12:28:30.099] <TB1> INFO: Test took 3824ms.
[12:28:30.389] <TB1> INFO: Expecting 41600 events.
[12:28:33.939] <TB1> INFO: 41600 events read in total (2958ms).
[12:28:33.940] <TB1> INFO: Test took 3816ms.
[12:28:34.230] <TB1> INFO: Expecting 41600 events.
[12:28:37.758] <TB1> INFO: 41600 events read in total (2937ms).
[12:28:37.759] <TB1> INFO: Test took 3795ms.
[12:28:38.066] <TB1> INFO: Expecting 41600 events.
[12:28:41.605] <TB1> INFO: 41600 events read in total (2947ms).
[12:28:41.606] <TB1> INFO: Test took 3823ms.
[12:28:41.897] <TB1> INFO: Expecting 41600 events.
[12:28:45.622] <TB1> INFO: 41600 events read in total (3133ms).
[12:28:45.623] <TB1> INFO: Test took 3992ms.
[12:28:45.913] <TB1> INFO: Expecting 41600 events.
[12:28:49.515] <TB1> INFO: 41600 events read in total (3010ms).
[12:28:49.516] <TB1> INFO: Test took 3869ms.
[12:28:49.805] <TB1> INFO: Expecting 41600 events.
[12:28:53.374] <TB1> INFO: 41600 events read in total (2977ms).
[12:28:53.375] <TB1> INFO: Test took 3835ms.
[12:28:53.665] <TB1> INFO: Expecting 41600 events.
[12:28:57.232] <TB1> INFO: 41600 events read in total (2975ms).
[12:28:57.233] <TB1> INFO: Test took 3833ms.
[12:28:57.524] <TB1> INFO: Expecting 41600 events.
[12:29:01.066] <TB1> INFO: 41600 events read in total (2951ms).
[12:29:01.067] <TB1> INFO: Test took 3809ms.
[12:29:01.358] <TB1> INFO: Expecting 2560 events.
[12:29:02.247] <TB1> INFO: 2560 events read in total (298ms).
[12:29:02.247] <TB1> INFO: Test took 1167ms.
[12:29:02.556] <TB1> INFO: Expecting 2560 events.
[12:29:03.448] <TB1> INFO: 2560 events read in total (301ms).
[12:29:03.449] <TB1> INFO: Test took 1201ms.
[12:29:03.756] <TB1> INFO: Expecting 2560 events.
[12:29:04.647] <TB1> INFO: 2560 events read in total (300ms).
[12:29:04.647] <TB1> INFO: Test took 1197ms.
[12:29:04.955] <TB1> INFO: Expecting 2560 events.
[12:29:05.852] <TB1> INFO: 2560 events read in total (305ms).
[12:29:05.852] <TB1> INFO: Test took 1204ms.
[12:29:06.160] <TB1> INFO: Expecting 2560 events.
[12:29:07.044] <TB1> INFO: 2560 events read in total (293ms).
[12:29:07.044] <TB1> INFO: Test took 1192ms.
[12:29:07.353] <TB1> INFO: Expecting 2560 events.
[12:29:08.236] <TB1> INFO: 2560 events read in total (292ms).
[12:29:08.237] <TB1> INFO: Test took 1193ms.
[12:29:08.544] <TB1> INFO: Expecting 2560 events.
[12:29:09.425] <TB1> INFO: 2560 events read in total (289ms).
[12:29:09.425] <TB1> INFO: Test took 1187ms.
[12:29:09.733] <TB1> INFO: Expecting 2560 events.
[12:29:10.622] <TB1> INFO: 2560 events read in total (297ms).
[12:29:10.622] <TB1> INFO: Test took 1196ms.
[12:29:10.930] <TB1> INFO: Expecting 2560 events.
[12:29:11.822] <TB1> INFO: 2560 events read in total (300ms).
[12:29:11.823] <TB1> INFO: Test took 1200ms.
[12:29:12.130] <TB1> INFO: Expecting 2560 events.
[12:29:13.018] <TB1> INFO: 2560 events read in total (296ms).
[12:29:13.019] <TB1> INFO: Test took 1196ms.
[12:29:13.326] <TB1> INFO: Expecting 2560 events.
[12:29:14.216] <TB1> INFO: 2560 events read in total (298ms).
[12:29:14.216] <TB1> INFO: Test took 1197ms.
[12:29:14.524] <TB1> INFO: Expecting 2560 events.
[12:29:15.404] <TB1> INFO: 2560 events read in total (288ms).
[12:29:15.404] <TB1> INFO: Test took 1187ms.
[12:29:15.711] <TB1> INFO: Expecting 2560 events.
[12:29:16.598] <TB1> INFO: 2560 events read in total (295ms).
[12:29:16.598] <TB1> INFO: Test took 1193ms.
[12:29:16.905] <TB1> INFO: Expecting 2560 events.
[12:29:17.797] <TB1> INFO: 2560 events read in total (300ms).
[12:29:17.797] <TB1> INFO: Test took 1198ms.
[12:29:18.106] <TB1> INFO: Expecting 2560 events.
[12:29:18.994] <TB1> INFO: 2560 events read in total (297ms).
[12:29:18.995] <TB1> INFO: Test took 1197ms.
[12:29:19.302] <TB1> INFO: Expecting 2560 events.
[12:29:20.187] <TB1> INFO: 2560 events read in total (294ms).
[12:29:20.187] <TB1> INFO: Test took 1192ms.
[12:29:20.193] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:29:20.496] <TB1> INFO: Expecting 655360 events.
[12:29:35.451] <TB1> INFO: 655360 events read in total (14363ms).
[12:29:35.470] <TB1> INFO: Expecting 655360 events.
[12:29:50.261] <TB1> INFO: 655360 events read in total (14385ms).
[12:29:50.279] <TB1> INFO: Expecting 655360 events.
[12:30:04.962] <TB1> INFO: 655360 events read in total (14280ms).
[12:30:04.985] <TB1> INFO: Expecting 655360 events.
[12:30:19.578] <TB1> INFO: 655360 events read in total (14190ms).
[12:30:19.605] <TB1> INFO: Expecting 655360 events.
[12:30:34.175] <TB1> INFO: 655360 events read in total (14167ms).
[12:30:34.208] <TB1> INFO: Expecting 655360 events.
[12:30:48.732] <TB1> INFO: 655360 events read in total (14121ms).
[12:30:48.776] <TB1> INFO: Expecting 655360 events.
[12:31:03.377] <TB1> INFO: 655360 events read in total (14198ms).
[12:31:03.420] <TB1> INFO: Expecting 655360 events.
[12:31:18.236] <TB1> INFO: 655360 events read in total (14413ms).
[12:31:18.312] <TB1> INFO: Expecting 655360 events.
[12:31:32.816] <TB1> INFO: 655360 events read in total (14101ms).
[12:31:32.927] <TB1> INFO: Expecting 655360 events.
[12:31:47.571] <TB1> INFO: 655360 events read in total (14241ms).
[12:31:47.702] <TB1> INFO: Expecting 655360 events.
[12:32:02.142] <TB1> INFO: 655360 events read in total (14037ms).
[12:32:02.216] <TB1> INFO: Expecting 655360 events.
[12:32:16.776] <TB1> INFO: 655360 events read in total (14156ms).
[12:32:16.855] <TB1> INFO: Expecting 655360 events.
[12:32:31.429] <TB1> INFO: 655360 events read in total (14171ms).
[12:32:31.511] <TB1> INFO: Expecting 655360 events.
[12:32:46.036] <TB1> INFO: 655360 events read in total (14121ms).
[12:32:46.142] <TB1> INFO: Expecting 655360 events.
[12:33:00.782] <TB1> INFO: 655360 events read in total (14237ms).
[12:33:00.894] <TB1> INFO: Expecting 655360 events.
[12:33:15.567] <TB1> INFO: 655360 events read in total (14270ms).
[12:33:15.708] <TB1> INFO: Test took 235515ms.
[12:33:15.824] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:33:16.080] <TB1> INFO: Expecting 655360 events.
[12:33:30.874] <TB1> INFO: 655360 events read in total (14202ms).
[12:33:30.891] <TB1> INFO: Expecting 655360 events.
[12:33:45.568] <TB1> INFO: 655360 events read in total (14274ms).
[12:33:45.588] <TB1> INFO: Expecting 655360 events.
[12:34:00.039] <TB1> INFO: 655360 events read in total (14048ms).
[12:34:00.068] <TB1> INFO: Expecting 655360 events.
[12:34:14.646] <TB1> INFO: 655360 events read in total (14175ms).
[12:34:14.674] <TB1> INFO: Expecting 655360 events.
[12:34:29.234] <TB1> INFO: 655360 events read in total (14157ms).
[12:34:29.268] <TB1> INFO: Expecting 655360 events.
[12:34:43.500] <TB1> INFO: 655360 events read in total (13829ms).
[12:34:43.539] <TB1> INFO: Expecting 655360 events.
[12:34:57.934] <TB1> INFO: 655360 events read in total (13992ms).
[12:34:57.975] <TB1> INFO: Expecting 655360 events.
[12:35:12.354] <TB1> INFO: 655360 events read in total (13975ms).
[12:35:12.454] <TB1> INFO: Expecting 655360 events.
[12:35:26.920] <TB1> INFO: 655360 events read in total (14063ms).
[12:35:27.024] <TB1> INFO: Expecting 655360 events.
[12:35:41.340] <TB1> INFO: 655360 events read in total (13913ms).
[12:35:41.408] <TB1> INFO: Expecting 655360 events.
[12:35:55.830] <TB1> INFO: 655360 events read in total (14019ms).
[12:35:55.905] <TB1> INFO: Expecting 655360 events.
[12:36:10.194] <TB1> INFO: 655360 events read in total (13886ms).
[12:36:10.272] <TB1> INFO: Expecting 655360 events.
[12:36:24.459] <TB1> INFO: 655360 events read in total (13784ms).
[12:36:24.575] <TB1> INFO: Expecting 655360 events.
[12:36:39.219] <TB1> INFO: 655360 events read in total (14241ms).
[12:36:39.326] <TB1> INFO: Expecting 655360 events.
[12:36:53.727] <TB1> INFO: 655360 events read in total (13998ms).
[12:36:53.826] <TB1> INFO: Expecting 655360 events.
[12:37:08.561] <TB1> INFO: 655360 events read in total (14332ms).
[12:37:08.676] <TB1> INFO: Test took 232852ms.
[12:37:08.882] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.889] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:08.895] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:37:08.903] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.910] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.918] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:08.925] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:37:08.933] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:37:08.941] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[12:37:08.948] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[12:37:08.955] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[12:37:08.962] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[12:37:08.969] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.976] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:08.983] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.991] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:08.997] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:09.007] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:09.016] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:37:09.025] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:09.033] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:09.040] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:09.046] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:37:09.052] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:37:09.059] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[12:37:09.065] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[12:37:09.072] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[12:37:09.077] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[12:37:09.085] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[12:37:09.091] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[12:37:09.096] <TB1> INFO: safety margin for low PH: adding 10, margin is now 30
[12:37:09.102] <TB1> INFO: safety margin for low PH: adding 11, margin is now 31
[12:37:09.108] <TB1> INFO: safety margin for low PH: adding 12, margin is now 32
[12:37:09.114] <TB1> INFO: safety margin for low PH: adding 13, margin is now 33
[12:37:09.120] <TB1> INFO: safety margin for low PH: adding 14, margin is now 34
[12:37:09.125] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:09.131] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:09.137] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:09.143] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:09.149] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:09.155] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:09.160] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:37:09.166] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:37:09.200] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C0.dat
[12:37:09.201] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C1.dat
[12:37:09.201] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C2.dat
[12:37:09.201] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C3.dat
[12:37:09.201] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C4.dat
[12:37:09.201] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C5.dat
[12:37:09.201] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C6.dat
[12:37:09.201] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C7.dat
[12:37:09.201] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C8.dat
[12:37:09.201] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C9.dat
[12:37:09.202] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C10.dat
[12:37:09.202] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C11.dat
[12:37:09.202] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C12.dat
[12:37:09.202] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C13.dat
[12:37:09.202] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C14.dat
[12:37:09.202] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//dacParameters35_C15.dat
[12:37:09.444] <TB1> INFO: Expecting 41600 events.
[12:37:12.619] <TB1> INFO: 41600 events read in total (2584ms).
[12:37:12.620] <TB1> INFO: Test took 3415ms.
[12:37:13.116] <TB1> INFO: Expecting 41600 events.
[12:37:16.215] <TB1> INFO: 41600 events read in total (2508ms).
[12:37:16.217] <TB1> INFO: Test took 3386ms.
[12:37:16.666] <TB1> INFO: Expecting 41600 events.
[12:37:19.820] <TB1> INFO: 41600 events read in total (2562ms).
[12:37:19.821] <TB1> INFO: Test took 3392ms.
[12:37:20.038] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:20.128] <TB1> INFO: Expecting 2560 events.
[12:37:21.019] <TB1> INFO: 2560 events read in total (299ms).
[12:37:21.019] <TB1> INFO: Test took 981ms.
[12:37:21.022] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:21.327] <TB1> INFO: Expecting 2560 events.
[12:37:22.214] <TB1> INFO: 2560 events read in total (295ms).
[12:37:22.215] <TB1> INFO: Test took 1193ms.
[12:37:22.217] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:22.524] <TB1> INFO: Expecting 2560 events.
[12:37:23.411] <TB1> INFO: 2560 events read in total (295ms).
[12:37:23.412] <TB1> INFO: Test took 1195ms.
[12:37:23.415] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:23.720] <TB1> INFO: Expecting 2560 events.
[12:37:24.616] <TB1> INFO: 2560 events read in total (304ms).
[12:37:24.616] <TB1> INFO: Test took 1202ms.
[12:37:24.619] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:24.924] <TB1> INFO: Expecting 2560 events.
[12:37:25.818] <TB1> INFO: 2560 events read in total (302ms).
[12:37:25.819] <TB1> INFO: Test took 1200ms.
[12:37:25.821] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:26.125] <TB1> INFO: Expecting 2560 events.
[12:37:27.018] <TB1> INFO: 2560 events read in total (301ms).
[12:37:27.018] <TB1> INFO: Test took 1197ms.
[12:37:27.021] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:27.326] <TB1> INFO: Expecting 2560 events.
[12:37:28.217] <TB1> INFO: 2560 events read in total (299ms).
[12:37:28.218] <TB1> INFO: Test took 1197ms.
[12:37:28.221] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:28.525] <TB1> INFO: Expecting 2560 events.
[12:37:29.416] <TB1> INFO: 2560 events read in total (299ms).
[12:37:29.417] <TB1> INFO: Test took 1196ms.
[12:37:29.421] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:29.724] <TB1> INFO: Expecting 2560 events.
[12:37:30.617] <TB1> INFO: 2560 events read in total (302ms).
[12:37:30.618] <TB1> INFO: Test took 1197ms.
[12:37:30.621] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:30.926] <TB1> INFO: Expecting 2560 events.
[12:37:31.818] <TB1> INFO: 2560 events read in total (300ms).
[12:37:31.819] <TB1> INFO: Test took 1199ms.
[12:37:31.823] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:32.127] <TB1> INFO: Expecting 2560 events.
[12:37:33.016] <TB1> INFO: 2560 events read in total (297ms).
[12:37:33.017] <TB1> INFO: Test took 1194ms.
[12:37:33.020] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:33.325] <TB1> INFO: Expecting 2560 events.
[12:37:34.208] <TB1> INFO: 2560 events read in total (291ms).
[12:37:34.208] <TB1> INFO: Test took 1188ms.
[12:37:34.212] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:34.516] <TB1> INFO: Expecting 2560 events.
[12:37:35.407] <TB1> INFO: 2560 events read in total (299ms).
[12:37:35.408] <TB1> INFO: Test took 1196ms.
[12:37:35.411] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:35.714] <TB1> INFO: Expecting 2560 events.
[12:37:36.595] <TB1> INFO: 2560 events read in total (289ms).
[12:37:36.596] <TB1> INFO: Test took 1185ms.
[12:37:36.598] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:36.903] <TB1> INFO: Expecting 2560 events.
[12:37:37.793] <TB1> INFO: 2560 events read in total (297ms).
[12:37:37.793] <TB1> INFO: Test took 1195ms.
[12:37:37.797] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:38.101] <TB1> INFO: Expecting 2560 events.
[12:37:38.992] <TB1> INFO: 2560 events read in total (299ms).
[12:37:38.992] <TB1> INFO: Test took 1196ms.
[12:37:38.997] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:39.300] <TB1> INFO: Expecting 2560 events.
[12:37:40.193] <TB1> INFO: 2560 events read in total (301ms).
[12:37:40.194] <TB1> INFO: Test took 1197ms.
[12:37:40.196] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:40.502] <TB1> INFO: Expecting 2560 events.
[12:37:41.392] <TB1> INFO: 2560 events read in total (298ms).
[12:37:41.393] <TB1> INFO: Test took 1197ms.
[12:37:41.396] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:41.700] <TB1> INFO: Expecting 2560 events.
[12:37:42.592] <TB1> INFO: 2560 events read in total (300ms).
[12:37:42.593] <TB1> INFO: Test took 1198ms.
[12:37:42.597] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:42.900] <TB1> INFO: Expecting 2560 events.
[12:37:43.791] <TB1> INFO: 2560 events read in total (299ms).
[12:37:43.791] <TB1> INFO: Test took 1194ms.
[12:37:43.794] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:44.100] <TB1> INFO: Expecting 2560 events.
[12:37:44.992] <TB1> INFO: 2560 events read in total (300ms).
[12:37:44.992] <TB1> INFO: Test took 1198ms.
[12:37:44.997] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:45.299] <TB1> INFO: Expecting 2560 events.
[12:37:46.191] <TB1> INFO: 2560 events read in total (300ms).
[12:37:46.191] <TB1> INFO: Test took 1194ms.
[12:37:46.195] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:46.501] <TB1> INFO: Expecting 2560 events.
[12:37:47.392] <TB1> INFO: 2560 events read in total (300ms).
[12:37:47.393] <TB1> INFO: Test took 1198ms.
[12:37:47.396] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:47.700] <TB1> INFO: Expecting 2560 events.
[12:37:48.587] <TB1> INFO: 2560 events read in total (295ms).
[12:37:48.587] <TB1> INFO: Test took 1191ms.
[12:37:48.590] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:48.896] <TB1> INFO: Expecting 2560 events.
[12:37:49.791] <TB1> INFO: 2560 events read in total (303ms).
[12:37:49.792] <TB1> INFO: Test took 1202ms.
[12:37:49.795] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:50.099] <TB1> INFO: Expecting 2560 events.
[12:37:50.998] <TB1> INFO: 2560 events read in total (306ms).
[12:37:50.998] <TB1> INFO: Test took 1203ms.
[12:37:50.002] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:51.307] <TB1> INFO: Expecting 2560 events.
[12:37:52.194] <TB1> INFO: 2560 events read in total (295ms).
[12:37:52.195] <TB1> INFO: Test took 1194ms.
[12:37:52.199] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:52.502] <TB1> INFO: Expecting 2560 events.
[12:37:53.394] <TB1> INFO: 2560 events read in total (300ms).
[12:37:53.394] <TB1> INFO: Test took 1195ms.
[12:37:53.397] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:53.703] <TB1> INFO: Expecting 2560 events.
[12:37:54.597] <TB1> INFO: 2560 events read in total (302ms).
[12:37:54.598] <TB1> INFO: Test took 1201ms.
[12:37:54.601] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:54.905] <TB1> INFO: Expecting 2560 events.
[12:37:55.797] <TB1> INFO: 2560 events read in total (300ms).
[12:37:55.797] <TB1> INFO: Test took 1196ms.
[12:37:55.800] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:56.104] <TB1> INFO: Expecting 2560 events.
[12:37:56.995] <TB1> INFO: 2560 events read in total (299ms).
[12:37:56.995] <TB1> INFO: Test took 1195ms.
[12:37:56.997] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:37:57.303] <TB1> INFO: Expecting 2560 events.
[12:37:58.197] <TB1> INFO: 2560 events read in total (302ms).
[12:37:58.198] <TB1> INFO: Test took 1201ms.
[12:37:58.673] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 650 seconds
[12:37:58.673] <TB1> INFO: PH scale (per ROC): 45 58 47 62 61 69 52 73 48 71 43 65 49 68 48 66
[12:37:58.673] <TB1> INFO: PH offset (per ROC): 111 128 114 127 122 116 126 132 112 133 82 119 111 116 93 122
[12:37:58.680] <TB1> INFO: Decoding statistics:
[12:37:58.680] <TB1> INFO: General information:
[12:37:58.680] <TB1> INFO: 16bit words read: 127886
[12:37:58.680] <TB1> INFO: valid events total: 20480
[12:37:58.680] <TB1> INFO: empty events: 17977
[12:37:58.680] <TB1> INFO: valid events with pixels: 2503
[12:37:58.680] <TB1> INFO: valid pixel hits: 2503
[12:37:58.680] <TB1> INFO: Event errors: 0
[12:37:58.680] <TB1> INFO: start marker: 0
[12:37:58.680] <TB1> INFO: stop marker: 0
[12:37:58.680] <TB1> INFO: overflow: 0
[12:37:58.680] <TB1> INFO: invalid 5bit words: 0
[12:37:58.680] <TB1> INFO: invalid XOR eye diagram: 0
[12:37:58.680] <TB1> INFO: frame (failed synchr.): 0
[12:37:58.680] <TB1> INFO: idle data (no TBM trl): 0
[12:37:58.681] <TB1> INFO: no data (only TBM hdr): 0
[12:37:58.681] <TB1> INFO: TBM errors: 0
[12:37:58.681] <TB1> INFO: flawed TBM headers: 0
[12:37:58.681] <TB1> INFO: flawed TBM trailers: 0
[12:37:58.681] <TB1> INFO: event ID mismatches: 0
[12:37:58.681] <TB1> INFO: ROC errors: 0
[12:37:58.681] <TB1> INFO: missing ROC header(s): 0
[12:37:58.681] <TB1> INFO: misplaced readback start: 0
[12:37:58.681] <TB1> INFO: Pixel decoding errors: 0
[12:37:58.681] <TB1> INFO: pixel data incomplete: 0
[12:37:58.681] <TB1> INFO: pixel address: 0
[12:37:58.681] <TB1> INFO: pulse height fill bit: 0
[12:37:58.681] <TB1> INFO: buffer corruption: 0
[12:37:58.850] <TB1> INFO: ######################################################################
[12:37:58.850] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[12:37:58.850] <TB1> INFO: ######################################################################
[12:37:58.864] <TB1> INFO: scanning low vcal = 10
[12:37:59.101] <TB1> INFO: Expecting 41600 events.
[12:38:02.687] <TB1> INFO: 41600 events read in total (2994ms).
[12:38:02.687] <TB1> INFO: Test took 3823ms.
[12:38:02.690] <TB1> INFO: scanning low vcal = 20
[12:38:02.988] <TB1> INFO: Expecting 41600 events.
[12:38:06.572] <TB1> INFO: 41600 events read in total (2992ms).
[12:38:06.572] <TB1> INFO: Test took 3881ms.
[12:38:06.574] <TB1> INFO: scanning low vcal = 30
[12:38:06.872] <TB1> INFO: Expecting 41600 events.
[12:38:10.557] <TB1> INFO: 41600 events read in total (3093ms).
[12:38:10.559] <TB1> INFO: Test took 3985ms.
[12:38:10.561] <TB1> INFO: scanning low vcal = 40
[12:38:10.839] <TB1> INFO: Expecting 41600 events.
[12:38:14.820] <TB1> INFO: 41600 events read in total (3389ms).
[12:38:14.822] <TB1> INFO: Test took 4261ms.
[12:38:14.825] <TB1> INFO: scanning low vcal = 50
[12:38:15.103] <TB1> INFO: Expecting 41600 events.
[12:38:19.100] <TB1> INFO: 41600 events read in total (3405ms).
[12:38:19.101] <TB1> INFO: Test took 4276ms.
[12:38:19.105] <TB1> INFO: scanning low vcal = 60
[12:38:19.381] <TB1> INFO: Expecting 41600 events.
[12:38:23.412] <TB1> INFO: 41600 events read in total (3439ms).
[12:38:23.413] <TB1> INFO: Test took 4308ms.
[12:38:23.416] <TB1> INFO: scanning low vcal = 70
[12:38:23.693] <TB1> INFO: Expecting 41600 events.
[12:38:27.681] <TB1> INFO: 41600 events read in total (3396ms).
[12:38:27.681] <TB1> INFO: Test took 4265ms.
[12:38:27.684] <TB1> INFO: scanning low vcal = 80
[12:38:27.962] <TB1> INFO: Expecting 41600 events.
[12:38:31.963] <TB1> INFO: 41600 events read in total (3409ms).
[12:38:31.964] <TB1> INFO: Test took 4280ms.
[12:38:31.970] <TB1> INFO: scanning low vcal = 90
[12:38:32.244] <TB1> INFO: Expecting 41600 events.
[12:38:36.260] <TB1> INFO: 41600 events read in total (3424ms).
[12:38:36.261] <TB1> INFO: Test took 4291ms.
[12:38:36.264] <TB1> INFO: scanning low vcal = 100
[12:38:36.541] <TB1> INFO: Expecting 41600 events.
[12:38:40.572] <TB1> INFO: 41600 events read in total (3439ms).
[12:38:40.573] <TB1> INFO: Test took 4309ms.
[12:38:40.576] <TB1> INFO: scanning low vcal = 110
[12:38:40.855] <TB1> INFO: Expecting 41600 events.
[12:38:44.874] <TB1> INFO: 41600 events read in total (3428ms).
[12:38:44.875] <TB1> INFO: Test took 4298ms.
[12:38:44.879] <TB1> INFO: scanning low vcal = 120
[12:38:45.156] <TB1> INFO: Expecting 41600 events.
[12:38:49.129] <TB1> INFO: 41600 events read in total (3381ms).
[12:38:49.130] <TB1> INFO: Test took 4251ms.
[12:38:49.133] <TB1> INFO: scanning low vcal = 130
[12:38:49.410] <TB1> INFO: Expecting 41600 events.
[12:38:53.380] <TB1> INFO: 41600 events read in total (3378ms).
[12:38:53.380] <TB1> INFO: Test took 4247ms.
[12:38:53.384] <TB1> INFO: scanning low vcal = 140
[12:38:53.662] <TB1> INFO: Expecting 41600 events.
[12:38:57.645] <TB1> INFO: 41600 events read in total (3392ms).
[12:38:57.645] <TB1> INFO: Test took 4261ms.
[12:38:57.650] <TB1> INFO: scanning low vcal = 150
[12:38:57.926] <TB1> INFO: Expecting 41600 events.
[12:39:01.917] <TB1> INFO: 41600 events read in total (3400ms).
[12:39:01.918] <TB1> INFO: Test took 4268ms.
[12:39:01.921] <TB1> INFO: scanning low vcal = 160
[12:39:02.198] <TB1> INFO: Expecting 41600 events.
[12:39:06.198] <TB1> INFO: 41600 events read in total (3408ms).
[12:39:06.199] <TB1> INFO: Test took 4278ms.
[12:39:06.203] <TB1> INFO: scanning low vcal = 170
[12:39:06.480] <TB1> INFO: Expecting 41600 events.
[12:39:10.485] <TB1> INFO: 41600 events read in total (3413ms).
[12:39:10.486] <TB1> INFO: Test took 4283ms.
[12:39:10.492] <TB1> INFO: scanning low vcal = 180
[12:39:10.766] <TB1> INFO: Expecting 41600 events.
[12:39:14.791] <TB1> INFO: 41600 events read in total (3433ms).
[12:39:14.794] <TB1> INFO: Test took 4302ms.
[12:39:14.797] <TB1> INFO: scanning low vcal = 190
[12:39:15.075] <TB1> INFO: Expecting 41600 events.
[12:39:19.076] <TB1> INFO: 41600 events read in total (3410ms).
[12:39:19.077] <TB1> INFO: Test took 4280ms.
[12:39:19.081] <TB1> INFO: scanning low vcal = 200
[12:39:19.358] <TB1> INFO: Expecting 41600 events.
[12:39:23.353] <TB1> INFO: 41600 events read in total (3403ms).
[12:39:23.354] <TB1> INFO: Test took 4273ms.
[12:39:23.357] <TB1> INFO: scanning low vcal = 210
[12:39:23.634] <TB1> INFO: Expecting 41600 events.
[12:39:27.596] <TB1> INFO: 41600 events read in total (3370ms).
[12:39:27.597] <TB1> INFO: Test took 4240ms.
[12:39:27.601] <TB1> INFO: scanning low vcal = 220
[12:39:27.876] <TB1> INFO: Expecting 41600 events.
[12:39:31.863] <TB1> INFO: 41600 events read in total (3395ms).
[12:39:31.863] <TB1> INFO: Test took 4262ms.
[12:39:31.867] <TB1> INFO: scanning low vcal = 230
[12:39:32.143] <TB1> INFO: Expecting 41600 events.
[12:39:36.128] <TB1> INFO: 41600 events read in total (3393ms).
[12:39:36.130] <TB1> INFO: Test took 4263ms.
[12:39:36.134] <TB1> INFO: scanning low vcal = 240
[12:39:36.410] <TB1> INFO: Expecting 41600 events.
[12:39:40.380] <TB1> INFO: 41600 events read in total (3378ms).
[12:39:40.381] <TB1> INFO: Test took 4247ms.
[12:39:40.385] <TB1> INFO: scanning low vcal = 250
[12:39:40.661] <TB1> INFO: Expecting 41600 events.
[12:39:44.623] <TB1> INFO: 41600 events read in total (3370ms).
[12:39:44.624] <TB1> INFO: Test took 4238ms.
[12:39:44.628] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[12:39:44.904] <TB1> INFO: Expecting 41600 events.
[12:39:48.866] <TB1> INFO: 41600 events read in total (3371ms).
[12:39:48.867] <TB1> INFO: Test took 4238ms.
[12:39:48.871] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[12:39:49.148] <TB1> INFO: Expecting 41600 events.
[12:39:53.127] <TB1> INFO: 41600 events read in total (3388ms).
[12:39:53.128] <TB1> INFO: Test took 4257ms.
[12:39:53.131] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[12:39:53.407] <TB1> INFO: Expecting 41600 events.
[12:39:57.374] <TB1> INFO: 41600 events read in total (3375ms).
[12:39:57.375] <TB1> INFO: Test took 4244ms.
[12:39:57.380] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[12:39:57.655] <TB1> INFO: Expecting 41600 events.
[12:40:01.623] <TB1> INFO: 41600 events read in total (3376ms).
[12:40:01.624] <TB1> INFO: Test took 4243ms.
[12:40:01.627] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:40:01.952] <TB1> INFO: Expecting 41600 events.
[12:40:05.923] <TB1> INFO: 41600 events read in total (3380ms).
[12:40:05.924] <TB1> INFO: Test took 4297ms.
[12:40:06.581] <TB1> INFO: PixTestGainPedestal::measure() done
[12:40:53.117] <TB1> INFO: PixTestGainPedestal::fit() done
[12:40:53.117] <TB1> INFO: non-linearity mean: 0.929 0.979 0.944 0.979 0.979 0.981 0.979 0.985 0.929 0.983 0.989 0.983 0.939 0.984 0.902 0.977
[12:40:53.118] <TB1> INFO: non-linearity RMS: 0.156 0.005 0.057 0.004 0.004 0.005 0.004 0.003 0.149 0.003 0.184 0.004 0.071 0.003 0.142 0.004
[12:40:53.118] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[12:40:53.132] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[12:40:53.146] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[12:40:53.159] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[12:40:53.173] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[12:40:53.187] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[12:40:53.201] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[12:40:53.215] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[12:40:53.229] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[12:40:53.243] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[12:40:53.256] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[12:40:53.271] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[12:40:53.284] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[12:40:53.299] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[12:40:53.312] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[12:40:53.326] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1097_FullQualification_2016-10-31_10h24m_1477905852//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[12:40:53.340] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 174 seconds
[12:40:53.340] <TB1> INFO: Decoding statistics:
[12:40:53.340] <TB1> INFO: General information:
[12:40:53.340] <TB1> INFO: 16bit words read: 3327956
[12:40:53.340] <TB1> INFO: valid events total: 332800
[12:40:53.340] <TB1> INFO: empty events: 0
[12:40:53.340] <TB1> INFO: valid events with pixels: 332800
[12:40:53.340] <TB1> INFO: valid pixel hits: 665578
[12:40:53.340] <TB1> INFO: Event errors: 0
[12:40:53.340] <TB1> INFO: start marker: 0
[12:40:53.340] <TB1> INFO: stop marker: 0
[12:40:53.340] <TB1> INFO: overflow: 0
[12:40:53.340] <TB1> INFO: invalid 5bit words: 0
[12:40:53.340] <TB1> INFO: invalid XOR eye diagram: 0
[12:40:53.340] <TB1> INFO: frame (failed synchr.): 0
[12:40:53.340] <TB1> INFO: idle data (no TBM trl): 0
[12:40:53.340] <TB1> INFO: no data (only TBM hdr): 0
[12:40:53.340] <TB1> INFO: TBM errors: 0
[12:40:53.340] <TB1> INFO: flawed TBM headers: 0
[12:40:53.340] <TB1> INFO: flawed TBM trailers: 0
[12:40:53.340] <TB1> INFO: event ID mismatches: 0
[12:40:53.340] <TB1> INFO: ROC errors: 0
[12:40:53.340] <TB1> INFO: missing ROC header(s): 0
[12:40:53.340] <TB1> INFO: misplaced readback start: 0
[12:40:53.340] <TB1> INFO: Pixel decoding errors: 0
[12:40:53.340] <TB1> INFO: pixel data incomplete: 0
[12:40:53.340] <TB1> INFO: pixel address: 0
[12:40:53.340] <TB1> INFO: pulse height fill bit: 0
[12:40:53.340] <TB1> INFO: buffer corruption: 0
[12:40:53.358] <TB1> INFO: Decoding statistics:
[12:40:53.358] <TB1> INFO: General information:
[12:40:53.358] <TB1> INFO: 16bit words read: 3457378
[12:40:53.358] <TB1> INFO: valid events total: 353536
[12:40:53.358] <TB1> INFO: empty events: 18233
[12:40:53.358] <TB1> INFO: valid events with pixels: 335303
[12:40:53.358] <TB1> INFO: valid pixel hits: 668081
[12:40:53.358] <TB1> INFO: Event errors: 0
[12:40:53.358] <TB1> INFO: start marker: 0
[12:40:53.358] <TB1> INFO: stop marker: 0
[12:40:53.358] <TB1> INFO: overflow: 0
[12:40:53.358] <TB1> INFO: invalid 5bit words: 0
[12:40:53.358] <TB1> INFO: invalid XOR eye diagram: 0
[12:40:53.358] <TB1> INFO: frame (failed synchr.): 0
[12:40:53.358] <TB1> INFO: idle data (no TBM trl): 0
[12:40:53.358] <TB1> INFO: no data (only TBM hdr): 0
[12:40:53.358] <TB1> INFO: TBM errors: 0
[12:40:53.358] <TB1> INFO: flawed TBM headers: 0
[12:40:53.358] <TB1> INFO: flawed TBM trailers: 0
[12:40:53.358] <TB1> INFO: event ID mismatches: 0
[12:40:53.358] <TB1> INFO: ROC errors: 0
[12:40:53.358] <TB1> INFO: missing ROC header(s): 0
[12:40:53.358] <TB1> INFO: misplaced readback start: 0
[12:40:53.358] <TB1> INFO: Pixel decoding errors: 0
[12:40:53.358] <TB1> INFO: pixel data incomplete: 0
[12:40:53.359] <TB1> INFO: pixel address: 0
[12:40:53.359] <TB1> INFO: pulse height fill bit: 0
[12:40:53.359] <TB1> INFO: buffer corruption: 0
[12:40:53.359] <TB1> INFO: enter test to run
[12:40:53.359] <TB1> INFO: test: exit no parameter change
[12:40:53.482] <TB1> QUIET: Connection to board 154 closed.
[12:40:53.483] <TB1> INFO: pXar: this is the end, my friend