[19:47:48.707] <TB2> INFO: *** Welcome to pxar ***
[19:47:48.707] <TB2> INFO: *** Today: 2016/10/26
[19:47:48.715] <TB2> INFO: *** Version: c8ba-dirty
[19:47:48.715] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C15.dat
[19:47:48.716] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[19:47:48.716] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//defaultMaskFile.dat
[19:47:48.716] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters_C15.dat
[19:47:48.782] <TB2> INFO: clk: 4
[19:47:48.782] <TB2> INFO: ctr: 4
[19:47:48.782] <TB2> INFO: sda: 19
[19:47:48.782] <TB2> INFO: tin: 9
[19:47:48.782] <TB2> INFO: level: 15
[19:47:48.782] <TB2> INFO: triggerdelay: 0
[19:47:48.782] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[19:47:48.782] <TB2> INFO: Log level: INFO
[19:47:48.791] <TB2> INFO: Found DTB DTB_WWXUD2
[19:47:48.799] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[19:47:48.801] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[19:47:48.802] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[19:47:50.293] <TB2> INFO: DUT info:
[19:47:50.293] <TB2> INFO: The DUT currently contains the following objects:
[19:47:50.293] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[19:47:50.293] <TB2> INFO: TBM Core alpha (0): 7 registers set
[19:47:50.293] <TB2> INFO: TBM Core beta (1): 7 registers set
[19:47:50.293] <TB2> INFO: TBM Core alpha (2): 7 registers set
[19:47:50.293] <TB2> INFO: TBM Core beta (3): 7 registers set
[19:47:50.293] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[19:47:50.293] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.293] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[19:47:50.695] <TB2> INFO: enter 'restricted' command line mode
[19:47:50.695] <TB2> INFO: enter test to run
[19:47:50.695] <TB2> INFO: test: pretest no parameter change
[19:47:50.695] <TB2> INFO: running: pretest
[19:47:50.701] <TB2> INFO: ######################################################################
[19:47:50.701] <TB2> INFO: PixTestPretest::doTest()
[19:47:50.701] <TB2> INFO: ######################################################################
[19:47:50.702] <TB2> INFO: ----------------------------------------------------------------------
[19:47:50.702] <TB2> INFO: PixTestPretest::programROC()
[19:47:50.702] <TB2> INFO: ----------------------------------------------------------------------
[19:48:08.717] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[19:48:08.717] <TB2> INFO: IA differences per ROC: 18.5 18.5 20.1 20.1 17.7 19.3 19.3 19.3 20.1 17.7 19.3 18.5 17.7 19.3 20.1 17.7
[19:48:08.782] <TB2> INFO: ----------------------------------------------------------------------
[19:48:08.782] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[19:48:08.782] <TB2> INFO: ----------------------------------------------------------------------
[19:48:15.177] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 387.5 mA = 24.2188 mA/ROC
[19:48:15.177] <TB2> INFO: i(loss) [mA/ROC]: 18.5 19.3 20.1 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 18.5 19.3 19.3 19.3 19.3
[19:48:15.211] <TB2> INFO: ----------------------------------------------------------------------
[19:48:15.211] <TB2> INFO: PixTestPretest::findTiming()
[19:48:15.211] <TB2> INFO: ----------------------------------------------------------------------
[19:48:15.211] <TB2> INFO: PixTestCmd::init()

[19:48:47.387] <TB2> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[19:48:47.387] <TB2> INFO: (success/tries = 100/100), width = 4
[19:48:48.888] <TB2> INFO: ----------------------------------------------------------------------
[19:48:48.888] <TB2> INFO: PixTestPretest::findWorkingPixel()
[19:48:48.889] <TB2> INFO: ----------------------------------------------------------------------
[19:48:48.981] <TB2> INFO: Expecting 231680 events.
[19:48:58.789] <TB2> INFO: 231680 events read in total (9216ms).
[19:48:58.797] <TB2> INFO: Test took 9905ms.
[19:48:59.037] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[19:48:59.069] <TB2> INFO: ----------------------------------------------------------------------
[19:48:59.069] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[19:48:59.069] <TB2> INFO: ----------------------------------------------------------------------
[19:48:59.162] <TB2> INFO: Expecting 231680 events.
[19:49:09.073] <TB2> INFO: 231680 events read in total (9319ms).
[19:49:09.083] <TB2> INFO: Test took 10011ms.
[19:49:09.352] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[19:49:09.352] <TB2> INFO: CalDel: 80 74 81 77 74 81 105 94 89 90 93 83 97 96 101 77
[19:49:09.352] <TB2> INFO: VthrComp: 51 51 51 51 54 51 51 51 51 51 51 51 51 51 51 51
[19:49:09.356] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C0.dat
[19:49:09.356] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C1.dat
[19:49:09.356] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C2.dat
[19:49:09.357] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C3.dat
[19:49:09.357] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C4.dat
[19:49:09.357] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C5.dat
[19:49:09.357] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C6.dat
[19:49:09.357] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C7.dat
[19:49:09.357] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C8.dat
[19:49:09.357] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C9.dat
[19:49:09.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C10.dat
[19:49:09.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C11.dat
[19:49:09.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C12.dat
[19:49:09.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C13.dat
[19:49:09.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C14.dat
[19:49:09.358] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters_C15.dat
[19:49:09.358] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[19:49:09.358] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[19:49:09.359] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[19:49:09.359] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[19:49:09.359] <TB2> INFO: PixTestPretest::doTest() done, duration: 78 seconds
[19:49:09.412] <TB2> INFO: enter test to run
[19:49:09.412] <TB2> INFO: test: fulltest no parameter change
[19:49:09.412] <TB2> INFO: running: fulltest
[19:49:09.412] <TB2> INFO: ######################################################################
[19:49:09.412] <TB2> INFO: PixTestFullTest::doTest()
[19:49:09.413] <TB2> INFO: ######################################################################
[19:49:09.414] <TB2> INFO: ######################################################################
[19:49:09.414] <TB2> INFO: PixTestAlive::doTest()
[19:49:09.414] <TB2> INFO: ######################################################################
[19:49:09.415] <TB2> INFO: ----------------------------------------------------------------------
[19:49:09.415] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[19:49:09.415] <TB2> INFO: ----------------------------------------------------------------------
[19:49:09.654] <TB2> INFO: Expecting 41600 events.
[19:49:13.277] <TB2> INFO: 41600 events read in total (3031ms).
[19:49:13.278] <TB2> INFO: Test took 3861ms.
[19:49:13.510] <TB2> INFO: PixTestAlive::aliveTest() done
[19:49:13.510] <TB2> INFO: number of dead pixels (per ROC): 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0
[19:49:13.512] <TB2> INFO: ----------------------------------------------------------------------
[19:49:13.514] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[19:49:13.514] <TB2> INFO: ----------------------------------------------------------------------
[19:49:13.802] <TB2> INFO: Expecting 41600 events.
[19:49:16.833] <TB2> INFO: 41600 events read in total (2439ms).
[19:49:16.834] <TB2> INFO: Test took 3318ms.
[19:49:16.834] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[19:49:17.079] <TB2> INFO: PixTestAlive::maskTest() done
[19:49:17.079] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[19:49:17.081] <TB2> INFO: ----------------------------------------------------------------------
[19:49:17.081] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[19:49:17.081] <TB2> INFO: ----------------------------------------------------------------------
[19:49:17.325] <TB2> INFO: Expecting 41600 events.
[19:49:20.985] <TB2> INFO: 41600 events read in total (3068ms).
[19:49:20.986] <TB2> INFO: Test took 3904ms.
[19:49:21.219] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[19:49:21.219] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[19:49:21.219] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[19:49:21.219] <TB2> INFO: Decoding statistics:
[19:49:21.219] <TB2> INFO: General information:
[19:49:21.219] <TB2> INFO: 16bit words read: 0
[19:49:21.219] <TB2> INFO: valid events total: 0
[19:49:21.219] <TB2> INFO: empty events: 0
[19:49:21.219] <TB2> INFO: valid events with pixels: 0
[19:49:21.219] <TB2> INFO: valid pixel hits: 0
[19:49:21.219] <TB2> INFO: Event errors: 0
[19:49:21.219] <TB2> INFO: start marker: 0
[19:49:21.219] <TB2> INFO: stop marker: 0
[19:49:21.219] <TB2> INFO: overflow: 0
[19:49:21.219] <TB2> INFO: invalid 5bit words: 0
[19:49:21.219] <TB2> INFO: invalid XOR eye diagram: 0
[19:49:21.219] <TB2> INFO: frame (failed synchr.): 0
[19:49:21.220] <TB2> INFO: idle data (no TBM trl): 0
[19:49:21.220] <TB2> INFO: no data (only TBM hdr): 0
[19:49:21.220] <TB2> INFO: TBM errors: 0
[19:49:21.220] <TB2> INFO: flawed TBM headers: 0
[19:49:21.220] <TB2> INFO: flawed TBM trailers: 0
[19:49:21.220] <TB2> INFO: event ID mismatches: 0
[19:49:21.220] <TB2> INFO: ROC errors: 0
[19:49:21.220] <TB2> INFO: missing ROC header(s): 0
[19:49:21.220] <TB2> INFO: misplaced readback start: 0
[19:49:21.220] <TB2> INFO: Pixel decoding errors: 0
[19:49:21.220] <TB2> INFO: pixel data incomplete: 0
[19:49:21.220] <TB2> INFO: pixel address: 0
[19:49:21.220] <TB2> INFO: pulse height fill bit: 0
[19:49:21.220] <TB2> INFO: buffer corruption: 0
[19:49:21.229] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C15.dat
[19:49:21.230] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[19:49:21.230] <TB2> INFO: ######################################################################
[19:49:21.230] <TB2> INFO: PixTestReadback::doTest()
[19:49:21.230] <TB2> INFO: ######################################################################
[19:49:21.230] <TB2> INFO: ----------------------------------------------------------------------
[19:49:21.230] <TB2> INFO: PixTestReadback::CalibrateVd()
[19:49:21.230] <TB2> INFO: ----------------------------------------------------------------------
[19:49:31.209] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C0.dat
[19:49:31.209] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C1.dat
[19:49:31.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C2.dat
[19:49:31.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C3.dat
[19:49:31.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C4.dat
[19:49:31.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C5.dat
[19:49:31.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C6.dat
[19:49:31.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C7.dat
[19:49:31.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C8.dat
[19:49:31.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C9.dat
[19:49:31.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C10.dat
[19:49:31.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C11.dat
[19:49:31.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C12.dat
[19:49:31.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C13.dat
[19:49:31.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C14.dat
[19:49:31.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C15.dat
[19:49:31.243] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[19:49:31.243] <TB2> INFO: ----------------------------------------------------------------------
[19:49:31.243] <TB2> INFO: PixTestReadback::CalibrateVa()
[19:49:31.243] <TB2> INFO: ----------------------------------------------------------------------
[19:49:41.180] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C0.dat
[19:49:41.180] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C1.dat
[19:49:41.180] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C2.dat
[19:49:41.180] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C3.dat
[19:49:41.180] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C4.dat
[19:49:41.180] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C5.dat
[19:49:41.180] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C6.dat
[19:49:41.180] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C7.dat
[19:49:41.180] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C8.dat
[19:49:41.180] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C9.dat
[19:49:41.180] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C10.dat
[19:49:41.181] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C11.dat
[19:49:41.181] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C12.dat
[19:49:41.181] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C13.dat
[19:49:41.181] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C14.dat
[19:49:41.181] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C15.dat
[19:49:41.214] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[19:49:41.214] <TB2> INFO: ----------------------------------------------------------------------
[19:49:41.214] <TB2> INFO: PixTestReadback::readbackVbg()
[19:49:41.214] <TB2> INFO: ----------------------------------------------------------------------
[19:49:48.888] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[19:49:48.888] <TB2> INFO: ----------------------------------------------------------------------
[19:49:48.888] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[19:49:48.888] <TB2> INFO: ----------------------------------------------------------------------
[19:49:48.888] <TB2> INFO: Vbg will be calibrated using Vd calibration
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 151.9calibrated Vbg = 1.203 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 150.1calibrated Vbg = 1.19611 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 147.4calibrated Vbg = 1.19109 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 155calibrated Vbg = 1.18937 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 155.2calibrated Vbg = 1.18885 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 157.3calibrated Vbg = 1.20006 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 153.7calibrated Vbg = 1.20184 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 159.7calibrated Vbg = 1.20292 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 160calibrated Vbg = 1.19813 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 152.9calibrated Vbg = 1.18977 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 152.6calibrated Vbg = 1.18806 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 159calibrated Vbg = 1.18735 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 150.6calibrated Vbg = 1.19516 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 153.9calibrated Vbg = 1.19786 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 160.8calibrated Vbg = 1.19892 :::*/*/*/*/
[19:49:48.888] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 149.6calibrated Vbg = 1.1971 :::*/*/*/*/
[19:49:48.892] <TB2> INFO: ----------------------------------------------------------------------
[19:49:48.892] <TB2> INFO: PixTestReadback::CalibrateIa()
[19:49:48.892] <TB2> INFO: ----------------------------------------------------------------------
[19:52:29.729] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C0.dat
[19:52:29.730] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C1.dat
[19:52:29.730] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C2.dat
[19:52:29.730] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C3.dat
[19:52:29.730] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C4.dat
[19:52:29.730] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C5.dat
[19:52:29.730] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C6.dat
[19:52:29.730] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C7.dat
[19:52:29.730] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C8.dat
[19:52:29.730] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C9.dat
[19:52:29.730] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C10.dat
[19:52:29.731] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C11.dat
[19:52:29.731] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C12.dat
[19:52:29.731] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C13.dat
[19:52:29.731] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C14.dat
[19:52:29.731] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//readbackCal_C15.dat
[19:52:29.760] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[19:52:29.761] <TB2> INFO: PixTestReadback::doTest() done
[19:52:29.761] <TB2> INFO: Decoding statistics:
[19:52:29.761] <TB2> INFO: General information:
[19:52:29.761] <TB2> INFO: 16bit words read: 1536
[19:52:29.761] <TB2> INFO: valid events total: 256
[19:52:29.761] <TB2> INFO: empty events: 256
[19:52:29.761] <TB2> INFO: valid events with pixels: 0
[19:52:29.761] <TB2> INFO: valid pixel hits: 0
[19:52:29.761] <TB2> INFO: Event errors: 0
[19:52:29.761] <TB2> INFO: start marker: 0
[19:52:29.761] <TB2> INFO: stop marker: 0
[19:52:29.762] <TB2> INFO: overflow: 0
[19:52:29.762] <TB2> INFO: invalid 5bit words: 0
[19:52:29.762] <TB2> INFO: invalid XOR eye diagram: 0
[19:52:29.762] <TB2> INFO: frame (failed synchr.): 0
[19:52:29.762] <TB2> INFO: idle data (no TBM trl): 0
[19:52:29.762] <TB2> INFO: no data (only TBM hdr): 0
[19:52:29.762] <TB2> INFO: TBM errors: 0
[19:52:29.762] <TB2> INFO: flawed TBM headers: 0
[19:52:29.762] <TB2> INFO: flawed TBM trailers: 0
[19:52:29.762] <TB2> INFO: event ID mismatches: 0
[19:52:29.762] <TB2> INFO: ROC errors: 0
[19:52:29.762] <TB2> INFO: missing ROC header(s): 0
[19:52:29.762] <TB2> INFO: misplaced readback start: 0
[19:52:29.762] <TB2> INFO: Pixel decoding errors: 0
[19:52:29.762] <TB2> INFO: pixel data incomplete: 0
[19:52:29.762] <TB2> INFO: pixel address: 0
[19:52:29.762] <TB2> INFO: pulse height fill bit: 0
[19:52:29.762] <TB2> INFO: buffer corruption: 0
[19:52:29.809] <TB2> INFO: ######################################################################
[19:52:29.809] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[19:52:29.809] <TB2> INFO: ######################################################################
[19:52:29.811] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[19:52:29.826] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[19:52:29.826] <TB2> INFO: run 1 of 1
[19:52:30.063] <TB2> INFO: Expecting 3120000 events.
[19:53:00.833] <TB2> INFO: 665335 events read in total (30179ms).











[19:53:30.810] <TB2> INFO: 1327325 events read in total (60156ms).




















[19:54:00.854] <TB2> INFO: 1987200 events read in total (90200ms).











[19:54:31.092] <TB2> INFO: 2646590 events read in total (120438ms).




















[19:54:52.406] <TB2> INFO: 3120000 events read in total (141752ms).
[19:54:52.487] <TB2> INFO: Test took 142662ms.
[19:55:18.019] <TB2> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 168 seconds
[19:55:18.019] <TB2> INFO: number of dead bumps (per ROC): 88 11 7 3 9 0 1 0 0 3 10 47 58 7 1 47
[19:55:18.019] <TB2> INFO: separation cut (per ROC): 92 104 104 122 107 103 106 107 126 105 104 111 98 122 102 100
[19:55:18.019] <TB2> INFO: Decoding statistics:
[19:55:18.019] <TB2> INFO: General information:
[19:55:18.019] <TB2> INFO: 16bit words read: 0
[19:55:18.019] <TB2> INFO: valid events total: 0
[19:55:18.019] <TB2> INFO: empty events: 0
[19:55:18.019] <TB2> INFO: valid events with pixels: 0
[19:55:18.019] <TB2> INFO: valid pixel hits: 0
[19:55:18.019] <TB2> INFO: Event errors: 0
[19:55:18.019] <TB2> INFO: start marker: 0
[19:55:18.019] <TB2> INFO: stop marker: 0
[19:55:18.019] <TB2> INFO: overflow: 0
[19:55:18.019] <TB2> INFO: invalid 5bit words: 0
[19:55:18.019] <TB2> INFO: invalid XOR eye diagram: 0
[19:55:18.019] <TB2> INFO: frame (failed synchr.): 0
[19:55:18.019] <TB2> INFO: idle data (no TBM trl): 0
[19:55:18.019] <TB2> INFO: no data (only TBM hdr): 0
[19:55:18.019] <TB2> INFO: TBM errors: 0
[19:55:18.019] <TB2> INFO: flawed TBM headers: 0
[19:55:18.019] <TB2> INFO: flawed TBM trailers: 0
[19:55:18.019] <TB2> INFO: event ID mismatches: 0
[19:55:18.019] <TB2> INFO: ROC errors: 0
[19:55:18.019] <TB2> INFO: missing ROC header(s): 0
[19:55:18.019] <TB2> INFO: misplaced readback start: 0
[19:55:18.019] <TB2> INFO: Pixel decoding errors: 0
[19:55:18.019] <TB2> INFO: pixel data incomplete: 0
[19:55:18.019] <TB2> INFO: pixel address: 0
[19:55:18.019] <TB2> INFO: pulse height fill bit: 0
[19:55:18.019] <TB2> INFO: buffer corruption: 0
[19:55:18.068] <TB2> INFO: ######################################################################
[19:55:18.068] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[19:55:18.068] <TB2> INFO: ######################################################################
[19:55:18.069] <TB2> INFO: ----------------------------------------------------------------------
[19:55:18.069] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[19:55:18.069] <TB2> INFO: ----------------------------------------------------------------------
[19:55:18.069] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[19:55:18.083] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[19:55:18.083] <TB2> INFO: run 1 of 1
[19:55:18.332] <TB2> INFO: Expecting 36608000 events.
[19:55:41.737] <TB2> INFO: 683650 events read in total (22814ms).
[19:56:04.601] <TB2> INFO: 1354600 events read in total (45678ms).
[19:56:27.583] <TB2> INFO: 2026200 events read in total (68660ms).
[19:56:50.502] <TB2> INFO: 2696800 events read in total (91579ms).
[19:57:13.233] <TB2> INFO: 3367600 events read in total (114310ms).
[19:57:35.970] <TB2> INFO: 4037400 events read in total (137047ms).
[19:57:59.035] <TB2> INFO: 4707200 events read in total (160112ms).
[19:58:21.477] <TB2> INFO: 5376200 events read in total (182554ms).
[19:58:44.491] <TB2> INFO: 6046450 events read in total (205568ms).
[19:59:07.547] <TB2> INFO: 6715550 events read in total (228624ms).
[19:59:30.300] <TB2> INFO: 7383850 events read in total (251377ms).
[19:59:53.137] <TB2> INFO: 8053900 events read in total (274214ms).
[20:00:15.783] <TB2> INFO: 8725100 events read in total (296860ms).
[20:00:38.469] <TB2> INFO: 9394750 events read in total (319546ms).
[20:01:01.133] <TB2> INFO: 10063500 events read in total (342210ms).
[20:01:23.890] <TB2> INFO: 10731950 events read in total (364967ms).
[20:01:46.562] <TB2> INFO: 11399800 events read in total (387639ms).
[20:02:09.569] <TB2> INFO: 12069000 events read in total (410646ms).
[20:02:32.286] <TB2> INFO: 12736300 events read in total (433363ms).
[20:02:54.955] <TB2> INFO: 13402250 events read in total (456032ms).
[20:03:17.642] <TB2> INFO: 14068300 events read in total (478719ms).
[20:03:40.354] <TB2> INFO: 14733150 events read in total (501431ms).
[20:04:03.092] <TB2> INFO: 15398650 events read in total (524169ms).
[20:04:25.623] <TB2> INFO: 16064750 events read in total (546700ms).
[20:04:48.425] <TB2> INFO: 16728550 events read in total (569502ms).
[20:05:11.347] <TB2> INFO: 17393600 events read in total (592424ms).
[20:05:34.085] <TB2> INFO: 18057200 events read in total (615162ms).
[20:05:56.960] <TB2> INFO: 18719650 events read in total (638037ms).
[20:06:19.600] <TB2> INFO: 19380750 events read in total (660677ms).
[20:06:42.318] <TB2> INFO: 20042500 events read in total (683395ms).
[20:07:04.997] <TB2> INFO: 20702800 events read in total (706074ms).
[20:07:28.008] <TB2> INFO: 21363050 events read in total (729085ms).
[20:07:50.892] <TB2> INFO: 22023250 events read in total (751970ms).
[20:08:13.738] <TB2> INFO: 22683200 events read in total (774815ms).
[20:08:36.246] <TB2> INFO: 23343650 events read in total (797323ms).
[20:08:58.618] <TB2> INFO: 24003450 events read in total (819695ms).
[20:09:21.317] <TB2> INFO: 24660600 events read in total (842394ms).
[20:09:44.066] <TB2> INFO: 25317500 events read in total (865143ms).
[20:10:06.848] <TB2> INFO: 25976100 events read in total (887925ms).
[20:10:29.345] <TB2> INFO: 26633800 events read in total (910422ms).
[20:10:52.195] <TB2> INFO: 27292650 events read in total (933272ms).
[20:11:15.211] <TB2> INFO: 27950550 events read in total (956288ms).
[20:11:37.870] <TB2> INFO: 28608250 events read in total (978947ms).
[20:12:00.305] <TB2> INFO: 29265700 events read in total (1001382ms).
[20:12:23.041] <TB2> INFO: 29922600 events read in total (1024118ms).
[20:12:45.568] <TB2> INFO: 30579050 events read in total (1046645ms).
[20:13:08.006] <TB2> INFO: 31235700 events read in total (1069083ms).
[20:13:30.577] <TB2> INFO: 31890350 events read in total (1091654ms).
[20:13:53.275] <TB2> INFO: 32547750 events read in total (1114352ms).
[20:14:15.865] <TB2> INFO: 33204550 events read in total (1136942ms).
[20:14:38.453] <TB2> INFO: 33862300 events read in total (1159530ms).
[20:15:01.037] <TB2> INFO: 34520700 events read in total (1182114ms).
[20:15:23.560] <TB2> INFO: 35174850 events read in total (1204637ms).
[20:15:46.119] <TB2> INFO: 35833900 events read in total (1227196ms).
[20:16:09.256] <TB2> INFO: 36501750 events read in total (1250333ms).
[20:16:13.361] <TB2> INFO: 36608000 events read in total (1254438ms).
[20:16:13.440] <TB2> INFO: Test took 1255357ms.
[20:16:13.893] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:15.456] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:16.897] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:18.305] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:20.318] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:22.380] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:24.393] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:26.400] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:28.184] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:30.361] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:32.699] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:34.845] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:36.228] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:37.602] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:38.980] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:40.390] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[20:16:42.395] <TB2> INFO: PixTestScurves::scurves() done
[20:16:42.395] <TB2> INFO: Vcal mean: 109.02 115.77 116.03 120.57 126.22 126.14 111.20 114.09 138.38 128.72 117.66 119.90 119.42 119.95 114.58 119.77
[20:16:42.395] <TB2> INFO: Vcal RMS: 5.33 4.89 5.34 5.24 6.23 5.99 5.24 6.84 5.28 6.29 6.18 5.80 6.16 5.10 5.46 6.14
[20:16:42.395] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1284 seconds
[20:16:42.395] <TB2> INFO: Decoding statistics:
[20:16:42.395] <TB2> INFO: General information:
[20:16:42.395] <TB2> INFO: 16bit words read: 0
[20:16:42.395] <TB2> INFO: valid events total: 0
[20:16:42.395] <TB2> INFO: empty events: 0
[20:16:42.395] <TB2> INFO: valid events with pixels: 0
[20:16:42.395] <TB2> INFO: valid pixel hits: 0
[20:16:42.395] <TB2> INFO: Event errors: 0
[20:16:42.395] <TB2> INFO: start marker: 0
[20:16:42.395] <TB2> INFO: stop marker: 0
[20:16:42.395] <TB2> INFO: overflow: 0
[20:16:42.395] <TB2> INFO: invalid 5bit words: 0
[20:16:42.395] <TB2> INFO: invalid XOR eye diagram: 0
[20:16:42.395] <TB2> INFO: frame (failed synchr.): 0
[20:16:42.395] <TB2> INFO: idle data (no TBM trl): 0
[20:16:42.395] <TB2> INFO: no data (only TBM hdr): 0
[20:16:42.395] <TB2> INFO: TBM errors: 0
[20:16:42.395] <TB2> INFO: flawed TBM headers: 0
[20:16:42.396] <TB2> INFO: flawed TBM trailers: 0
[20:16:42.396] <TB2> INFO: event ID mismatches: 0
[20:16:42.396] <TB2> INFO: ROC errors: 0
[20:16:42.396] <TB2> INFO: missing ROC header(s): 0
[20:16:42.396] <TB2> INFO: misplaced readback start: 0
[20:16:42.396] <TB2> INFO: Pixel decoding errors: 0
[20:16:42.396] <TB2> INFO: pixel data incomplete: 0
[20:16:42.396] <TB2> INFO: pixel address: 0
[20:16:42.396] <TB2> INFO: pulse height fill bit: 0
[20:16:42.396] <TB2> INFO: buffer corruption: 0
[20:16:42.463] <TB2> INFO: ######################################################################
[20:16:42.463] <TB2> INFO: PixTestTrim::doTest()
[20:16:42.463] <TB2> INFO: ######################################################################
[20:16:42.464] <TB2> INFO: ----------------------------------------------------------------------
[20:16:42.464] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[20:16:42.464] <TB2> INFO: ----------------------------------------------------------------------
[20:16:42.508] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[20:16:42.509] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[20:16:42.522] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:16:42.522] <TB2> INFO: run 1 of 1
[20:16:42.789] <TB2> INFO: Expecting 5025280 events.
[20:17:13.632] <TB2> INFO: 825312 events read in total (30247ms).
[20:17:43.821] <TB2> INFO: 1647264 events read in total (60437ms).
[20:18:13.981] <TB2> INFO: 2463408 events read in total (90596ms).
[20:18:44.173] <TB2> INFO: 3273560 events read in total (120788ms).
[20:19:14.278] <TB2> INFO: 4080536 events read in total (150893ms).
[20:19:43.800] <TB2> INFO: 4886744 events read in total (180415ms).
[20:19:49.537] <TB2> INFO: 5025280 events read in total (186152ms).
[20:19:49.583] <TB2> INFO: Test took 187062ms.
[20:20:06.044] <TB2> INFO: ROC 0 VthrComp = 117
[20:20:06.044] <TB2> INFO: ROC 1 VthrComp = 123
[20:20:06.044] <TB2> INFO: ROC 2 VthrComp = 131
[20:20:06.044] <TB2> INFO: ROC 3 VthrComp = 136
[20:20:06.044] <TB2> INFO: ROC 4 VthrComp = 131
[20:20:06.044] <TB2> INFO: ROC 5 VthrComp = 131
[20:20:06.044] <TB2> INFO: ROC 6 VthrComp = 117
[20:20:06.044] <TB2> INFO: ROC 7 VthrComp = 117
[20:20:06.044] <TB2> INFO: ROC 8 VthrComp = 139
[20:20:06.045] <TB2> INFO: ROC 9 VthrComp = 128
[20:20:06.045] <TB2> INFO: ROC 10 VthrComp = 124
[20:20:06.045] <TB2> INFO: ROC 11 VthrComp = 122
[20:20:06.045] <TB2> INFO: ROC 12 VthrComp = 122
[20:20:06.045] <TB2> INFO: ROC 13 VthrComp = 124
[20:20:06.045] <TB2> INFO: ROC 14 VthrComp = 115
[20:20:06.045] <TB2> INFO: ROC 15 VthrComp = 123
[20:20:06.284] <TB2> INFO: Expecting 41600 events.
[20:20:09.794] <TB2> INFO: 41600 events read in total (2919ms).
[20:20:09.795] <TB2> INFO: Test took 3748ms.
[20:20:09.804] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[20:20:09.804] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[20:20:09.816] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:20:09.816] <TB2> INFO: run 1 of 1
[20:20:10.094] <TB2> INFO: Expecting 5025280 events.
[20:20:36.551] <TB2> INFO: 589896 events read in total (25865ms).
[20:21:02.694] <TB2> INFO: 1178824 events read in total (52008ms).
[20:21:29.141] <TB2> INFO: 1767936 events read in total (78455ms).
[20:21:55.288] <TB2> INFO: 2356568 events read in total (104602ms).
[20:22:21.348] <TB2> INFO: 2942752 events read in total (130662ms).
[20:22:47.379] <TB2> INFO: 3527952 events read in total (156693ms).
[20:23:13.132] <TB2> INFO: 4111928 events read in total (182446ms).
[20:23:38.469] <TB2> INFO: 4693928 events read in total (207783ms).
[20:23:53.859] <TB2> INFO: 5025280 events read in total (223173ms).
[20:23:53.941] <TB2> INFO: Test took 224124ms.
[20:24:18.437] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 56.1624 for pixel 18/75 mean/min/max = 44.6428/32.968/56.3176
[20:24:18.437] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 57.5037 for pixel 15/69 mean/min/max = 45.217/32.8478/57.5862
[20:24:18.438] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 55.8093 for pixel 7/79 mean/min/max = 43.8942/31.9257/55.8627
[20:24:18.438] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 57.3218 for pixel 31/3 mean/min/max = 46.9456/36.4667/57.4245
[20:24:18.438] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 63.8116 for pixel 0/21 mean/min/max = 48.6218/33.3617/63.8819
[20:24:18.439] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 57.8174 for pixel 8/10 mean/min/max = 44.8016/31.4605/58.1427
[20:24:18.439] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 60.6921 for pixel 3/76 mean/min/max = 46.1844/31.3714/60.9974
[20:24:18.439] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 64.4113 for pixel 0/78 mean/min/max = 47.2452/29.9922/64.4982
[20:24:18.440] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 63.5103 for pixel 0/3 mean/min/max = 50.5574/37.542/63.5727
[20:24:18.440] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 59.2618 for pixel 24/0 mean/min/max = 45.4627/31.6578/59.2677
[20:24:18.440] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 59.9272 for pixel 24/6 mean/min/max = 46.3708/32.5304/60.2112
[20:24:18.441] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 58.2165 for pixel 0/75 mean/min/max = 46.1616/33.8265/58.4967
[20:24:18.441] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 57.1841 for pixel 29/72 mean/min/max = 45.3544/33.1491/57.5598
[20:24:18.442] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 57.0617 for pixel 20/9 mean/min/max = 45.5369/33.6141/57.4596
[20:24:18.442] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 58.569 for pixel 7/17 mean/min/max = 45.8822/32.9278/58.8365
[20:24:18.442] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 59.0399 for pixel 17/2 mean/min/max = 46.1549/33.2409/59.0689
[20:24:18.443] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:24:18.531] <TB2> INFO: Expecting 411648 events.
[20:24:27.874] <TB2> INFO: 411648 events read in total (8751ms).
[20:24:27.882] <TB2> INFO: Expecting 411648 events.
[20:24:37.196] <TB2> INFO: 411648 events read in total (8911ms).
[20:24:37.207] <TB2> INFO: Expecting 411648 events.
[20:24:46.527] <TB2> INFO: 411648 events read in total (8917ms).
[20:24:46.541] <TB2> INFO: Expecting 411648 events.
[20:24:55.897] <TB2> INFO: 411648 events read in total (8953ms).
[20:24:55.915] <TB2> INFO: Expecting 411648 events.
[20:25:05.239] <TB2> INFO: 411648 events read in total (8921ms).
[20:25:05.258] <TB2> INFO: Expecting 411648 events.
[20:25:14.550] <TB2> INFO: 411648 events read in total (8888ms).
[20:25:14.579] <TB2> INFO: Expecting 411648 events.
[20:25:23.000] <TB2> INFO: 411648 events read in total (9018ms).
[20:25:24.032] <TB2> INFO: Expecting 411648 events.
[20:25:33.395] <TB2> INFO: 411648 events read in total (8960ms).
[20:25:33.433] <TB2> INFO: Expecting 411648 events.
[20:25:42.879] <TB2> INFO: 411648 events read in total (9043ms).
[20:25:42.920] <TB2> INFO: Expecting 411648 events.
[20:25:52.160] <TB2> INFO: 411648 events read in total (8837ms).
[20:25:52.199] <TB2> INFO: Expecting 411648 events.
[20:26:01.513] <TB2> INFO: 411648 events read in total (8911ms).
[20:26:01.557] <TB2> INFO: Expecting 411648 events.
[20:26:10.758] <TB2> INFO: 411648 events read in total (8798ms).
[20:26:10.796] <TB2> INFO: Expecting 411648 events.
[20:26:20.097] <TB2> INFO: 411648 events read in total (8898ms).
[20:26:20.139] <TB2> INFO: Expecting 411648 events.
[20:26:29.455] <TB2> INFO: 411648 events read in total (8913ms).
[20:26:29.513] <TB2> INFO: Expecting 411648 events.
[20:26:38.758] <TB2> INFO: 411648 events read in total (8842ms).
[20:26:38.806] <TB2> INFO: Expecting 411648 events.
[20:26:48.347] <TB2> INFO: 411648 events read in total (9137ms).
[20:26:48.397] <TB2> INFO: Test took 149954ms.
[20:26:49.193] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[20:26:49.206] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:26:49.206] <TB2> INFO: run 1 of 1
[20:26:49.443] <TB2> INFO: Expecting 5025280 events.
[20:27:16.297] <TB2> INFO: 585280 events read in total (26262ms).
[20:27:42.654] <TB2> INFO: 1169280 events read in total (52619ms).
[20:28:08.648] <TB2> INFO: 1753344 events read in total (78613ms).
[20:28:34.002] <TB2> INFO: 2336384 events read in total (104967ms).
[20:29:01.610] <TB2> INFO: 2918832 events read in total (131575ms).
[20:29:28.171] <TB2> INFO: 3500256 events read in total (158136ms).
[20:29:54.544] <TB2> INFO: 4081536 events read in total (184509ms).
[20:30:20.784] <TB2> INFO: 4662464 events read in total (210749ms).
[20:30:37.719] <TB2> INFO: 5025280 events read in total (227684ms).
[20:30:37.838] <TB2> INFO: Test took 228633ms.
[20:31:02.920] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 5.915576 .. 132.642819
[20:31:03.158] <TB2> INFO: Expecting 208000 events.
[20:31:12.630] <TB2> INFO: 208000 events read in total (8881ms).
[20:31:12.632] <TB2> INFO: Test took 9711ms.
[20:31:12.689] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 5 .. 142 (-1/-1) hits flags = 528 (plus default)
[20:31:12.703] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:31:12.703] <TB2> INFO: run 1 of 1
[20:31:12.981] <TB2> INFO: Expecting 4592640 events.
[20:31:39.529] <TB2> INFO: 582840 events read in total (25954ms).
[20:32:05.200] <TB2> INFO: 1167040 events read in total (51626ms).
[20:32:31.045] <TB2> INFO: 1751448 events read in total (77470ms).
[20:32:57.199] <TB2> INFO: 2335792 events read in total (103625ms).
[20:33:23.395] <TB2> INFO: 2919920 events read in total (129820ms).
[20:33:49.551] <TB2> INFO: 3502608 events read in total (155976ms).
[20:34:16.100] <TB2> INFO: 4082976 events read in total (182525ms).
[20:34:38.734] <TB2> INFO: 4592640 events read in total (205159ms).
[20:34:38.839] <TB2> INFO: Test took 206136ms.
[20:35:03.269] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.713286 .. 45.499867
[20:35:03.595] <TB2> INFO: Expecting 208000 events.
[20:35:13.482] <TB2> INFO: 208000 events read in total (9295ms).
[20:35:13.483] <TB2> INFO: Test took 10212ms.
[20:35:13.530] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 55 (-1/-1) hits flags = 528 (plus default)
[20:35:13.544] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:35:13.544] <TB2> INFO: run 1 of 1
[20:35:13.822] <TB2> INFO: Expecting 1297920 events.
[20:35:41.786] <TB2> INFO: 659944 events read in total (27373ms).
[20:36:09.240] <TB2> INFO: 1297920 events read in total (54828ms).
[20:36:09.278] <TB2> INFO: Test took 55735ms.
[20:36:22.217] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 25.141334 .. 46.839444
[20:36:22.457] <TB2> INFO: Expecting 208000 events.
[20:36:32.376] <TB2> INFO: 208000 events read in total (9328ms).
[20:36:32.377] <TB2> INFO: Test took 10158ms.
[20:36:32.426] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 56 (-1/-1) hits flags = 528 (plus default)
[20:36:32.439] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:36:32.439] <TB2> INFO: run 1 of 1
[20:36:32.718] <TB2> INFO: Expecting 1397760 events.
[20:37:00.988] <TB2> INFO: 664080 events read in total (27679ms).
[20:37:29.130] <TB2> INFO: 1328088 events read in total (55821ms).
[20:37:32.617] <TB2> INFO: 1397760 events read in total (59308ms).
[20:37:32.644] <TB2> INFO: Test took 60206ms.
[20:37:46.551] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 24.159763 .. 44.635973
[20:37:46.810] <TB2> INFO: Expecting 208000 events.
[20:37:57.061] <TB2> INFO: 208000 events read in total (9659ms).
[20:37:57.062] <TB2> INFO: Test took 10508ms.
[20:37:57.131] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 54 (-1/-1) hits flags = 528 (plus default)
[20:37:57.145] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:37:57.145] <TB2> INFO: run 1 of 1
[20:37:57.423] <TB2> INFO: Expecting 1364480 events.
[20:38:25.143] <TB2> INFO: 676888 events read in total (27128ms).
[20:38:52.906] <TB2> INFO: 1353544 events read in total (54892ms).
[20:38:53.794] <TB2> INFO: 1364480 events read in total (55780ms).
[20:38:53.822] <TB2> INFO: Test took 56676ms.
[20:39:05.908] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[20:39:05.908] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[20:39:05.921] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:39:05.921] <TB2> INFO: run 1 of 1
[20:39:06.158] <TB2> INFO: Expecting 1364480 events.
[20:39:34.984] <TB2> INFO: 668664 events read in total (28234ms).
[20:40:02.168] <TB2> INFO: 1336232 events read in total (55418ms).
[20:40:03.722] <TB2> INFO: 1364480 events read in total (56972ms).
[20:40:03.747] <TB2> INFO: Test took 57826ms.
[20:40:16.813] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C0.dat
[20:40:16.813] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C1.dat
[20:40:16.813] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C2.dat
[20:40:16.813] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C3.dat
[20:40:16.813] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C4.dat
[20:40:16.814] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C5.dat
[20:40:16.814] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C6.dat
[20:40:16.814] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C7.dat
[20:40:16.814] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C8.dat
[20:40:16.814] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C9.dat
[20:40:16.814] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C10.dat
[20:40:16.814] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C11.dat
[20:40:16.814] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C12.dat
[20:40:16.814] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C13.dat
[20:40:16.814] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C14.dat
[20:40:16.815] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C15.dat
[20:40:16.815] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C0.dat
[20:40:16.821] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C1.dat
[20:40:16.826] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C2.dat
[20:40:16.831] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C3.dat
[20:40:16.836] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C4.dat
[20:40:16.841] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C5.dat
[20:40:16.845] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C6.dat
[20:40:16.850] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C7.dat
[20:40:16.855] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C8.dat
[20:40:16.860] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C9.dat
[20:40:16.864] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C10.dat
[20:40:16.869] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C11.dat
[20:40:16.874] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C12.dat
[20:40:16.879] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C13.dat
[20:40:16.883] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C14.dat
[20:40:16.888] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters35_C15.dat
[20:40:16.893] <TB2> INFO: PixTestTrim::trimTest() done
[20:40:16.893] <TB2> INFO: vtrim: 121 124 121 132 153 128 130 149 159 129 140 112 117 115 114 128
[20:40:16.893] <TB2> INFO: vthrcomp: 117 123 131 136 131 131 117 117 139 128 124 122 122 124 115 123
[20:40:16.893] <TB2> INFO: vcal mean: 35.00 34.96 34.96 35.00 35.12 34.97 34.92 34.95 35.02 35.06 34.96 35.01 34.93 35.01 35.00 35.00
[20:40:16.893] <TB2> INFO: vcal RMS: 0.92 1.01 1.09 1.05 1.19 1.12 0.96 1.17 1.07 1.30 1.00 0.95 0.96 0.96 1.01 1.00
[20:40:16.893] <TB2> INFO: bits mean: 9.60 9.47 9.66 8.14 8.73 9.95 9.51 9.33 7.24 10.07 9.31 8.74 9.80 9.36 9.48 9.42
[20:40:16.893] <TB2> INFO: bits RMS: 2.61 2.70 2.75 2.49 2.73 2.65 2.78 2.95 2.42 2.57 2.68 2.80 2.49 2.61 2.63 2.59
[20:40:16.900] <TB2> INFO: ----------------------------------------------------------------------
[20:40:16.900] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[20:40:16.901] <TB2> INFO: ----------------------------------------------------------------------
[20:40:16.904] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[20:40:16.918] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:40:16.918] <TB2> INFO: run 1 of 1
[20:40:17.161] <TB2> INFO: Expecting 4160000 events.
[20:40:49.395] <TB2> INFO: 753275 events read in total (31642ms).
[20:41:21.199] <TB2> INFO: 1502630 events read in total (63446ms).
[20:41:52.826] <TB2> INFO: 2245935 events read in total (95074ms).
[20:42:24.340] <TB2> INFO: 2982285 events read in total (126587ms).
[20:42:56.014] <TB2> INFO: 3718050 events read in total (158261ms).
[20:43:15.174] <TB2> INFO: 4160000 events read in total (177421ms).
[20:43:15.242] <TB2> INFO: Test took 178324ms.
[20:43:41.328] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[20:43:41.342] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:43:41.342] <TB2> INFO: run 1 of 1
[20:43:41.668] <TB2> INFO: Expecting 4284800 events.
[20:44:13.532] <TB2> INFO: 723530 events read in total (31273ms).
[20:44:45.013] <TB2> INFO: 1443665 events read in total (62754ms).
[20:45:15.962] <TB2> INFO: 2159090 events read in total (93703ms).
[20:45:46.947] <TB2> INFO: 2868450 events read in total (124688ms).
[20:46:18.114] <TB2> INFO: 3575300 events read in total (155855ms).
[20:46:49.207] <TB2> INFO: 4283070 events read in total (186948ms).
[20:46:49.706] <TB2> INFO: 4284800 events read in total (187447ms).
[20:46:49.767] <TB2> INFO: Test took 188425ms.
[20:47:14.729] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 195 (-1/-1) hits flags = 528 (plus default)
[20:47:14.743] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:47:14.743] <TB2> INFO: run 1 of 1
[20:47:14.979] <TB2> INFO: Expecting 4076800 events.
[20:47:47.349] <TB2> INFO: 737245 events read in total (31778ms).
[20:48:18.731] <TB2> INFO: 1470760 events read in total (63160ms).
[20:48:50.155] <TB2> INFO: 2198100 events read in total (94584ms).
[20:49:21.493] <TB2> INFO: 2919365 events read in total (125922ms).
[20:49:52.770] <TB2> INFO: 3637840 events read in total (157199ms).
[20:50:11.814] <TB2> INFO: 4076800 events read in total (176243ms).
[20:50:11.873] <TB2> INFO: Test took 177130ms.
[20:50:36.866] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 197 (-1/-1) hits flags = 528 (plus default)
[20:50:36.879] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:50:36.879] <TB2> INFO: run 1 of 1
[20:50:37.115] <TB2> INFO: Expecting 4118400 events.
[20:51:09.376] <TB2> INFO: 734580 events read in total (31669ms).
[20:51:41.819] <TB2> INFO: 1465865 events read in total (64112ms).
[20:52:14.444] <TB2> INFO: 2191265 events read in total (96737ms).
[20:52:46.397] <TB2> INFO: 2910360 events read in total (128690ms).
[20:53:18.320] <TB2> INFO: 3626805 events read in total (160613ms).
[20:53:40.042] <TB2> INFO: 4118400 events read in total (182335ms).
[20:53:40.106] <TB2> INFO: Test took 183227ms.
[20:54:03.884] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[20:54:03.897] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:54:03.897] <TB2> INFO: run 1 of 1
[20:54:04.132] <TB2> INFO: Expecting 4097600 events.
[20:54:37.204] <TB2> INFO: 736355 events read in total (32480ms).
[20:55:09.072] <TB2> INFO: 1469220 events read in total (64348ms).
[20:55:40.666] <TB2> INFO: 2196075 events read in total (95942ms).
[20:56:11.987] <TB2> INFO: 2916520 events read in total (127263ms).
[20:56:43.558] <TB2> INFO: 3634505 events read in total (158834ms).
[20:57:03.694] <TB2> INFO: 4097600 events read in total (178970ms).
[20:57:03.753] <TB2> INFO: Test took 179856ms.
[20:57:30.161] <TB2> INFO: PixTestTrim::trimBitTest() done
[20:57:30.162] <TB2> INFO: PixTestTrim::doTest() done, duration: 2447 seconds
[20:57:30.162] <TB2> INFO: Decoding statistics:
[20:57:30.162] <TB2> INFO: General information:
[20:57:30.162] <TB2> INFO: 16bit words read: 0
[20:57:30.162] <TB2> INFO: valid events total: 0
[20:57:30.162] <TB2> INFO: empty events: 0
[20:57:30.162] <TB2> INFO: valid events with pixels: 0
[20:57:30.162] <TB2> INFO: valid pixel hits: 0
[20:57:30.162] <TB2> INFO: Event errors: 0
[20:57:30.162] <TB2> INFO: start marker: 0
[20:57:30.162] <TB2> INFO: stop marker: 0
[20:57:30.162] <TB2> INFO: overflow: 0
[20:57:30.162] <TB2> INFO: invalid 5bit words: 0
[20:57:30.162] <TB2> INFO: invalid XOR eye diagram: 0
[20:57:30.162] <TB2> INFO: frame (failed synchr.): 0
[20:57:30.162] <TB2> INFO: idle data (no TBM trl): 0
[20:57:30.162] <TB2> INFO: no data (only TBM hdr): 0
[20:57:30.162] <TB2> INFO: TBM errors: 0
[20:57:30.162] <TB2> INFO: flawed TBM headers: 0
[20:57:30.162] <TB2> INFO: flawed TBM trailers: 0
[20:57:30.162] <TB2> INFO: event ID mismatches: 0
[20:57:30.162] <TB2> INFO: ROC errors: 0
[20:57:30.162] <TB2> INFO: missing ROC header(s): 0
[20:57:30.162] <TB2> INFO: misplaced readback start: 0
[20:57:30.162] <TB2> INFO: Pixel decoding errors: 0
[20:57:30.162] <TB2> INFO: pixel data incomplete: 0
[20:57:30.162] <TB2> INFO: pixel address: 0
[20:57:30.162] <TB2> INFO: pulse height fill bit: 0
[20:57:30.162] <TB2> INFO: buffer corruption: 0
[20:57:30.757] <TB2> INFO: ######################################################################
[20:57:30.757] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[20:57:30.757] <TB2> INFO: ######################################################################
[20:57:30.997] <TB2> INFO: Expecting 41600 events.
[20:57:34.438] <TB2> INFO: 41600 events read in total (2850ms).
[20:57:34.439] <TB2> INFO: Test took 3680ms.
[20:57:34.895] <TB2> INFO: Expecting 41600 events.
[20:57:38.376] <TB2> INFO: 41600 events read in total (2889ms).
[20:57:38.376] <TB2> INFO: Test took 3732ms.
[20:57:38.666] <TB2> INFO: Expecting 41600 events.
[20:57:42.163] <TB2> INFO: 41600 events read in total (2906ms).
[20:57:42.164] <TB2> INFO: Test took 3764ms.
[20:57:42.453] <TB2> INFO: Expecting 41600 events.
[20:57:46.048] <TB2> INFO: 41600 events read in total (3003ms).
[20:57:46.049] <TB2> INFO: Test took 3861ms.
[20:57:46.338] <TB2> INFO: Expecting 41600 events.
[20:57:49.875] <TB2> INFO: 41600 events read in total (2945ms).
[20:57:49.876] <TB2> INFO: Test took 3803ms.
[20:57:50.166] <TB2> INFO: Expecting 41600 events.
[20:57:53.667] <TB2> INFO: 41600 events read in total (2909ms).
[20:57:53.668] <TB2> INFO: Test took 3767ms.
[20:57:53.957] <TB2> INFO: Expecting 41600 events.
[20:57:57.495] <TB2> INFO: 41600 events read in total (2947ms).
[20:57:57.496] <TB2> INFO: Test took 3804ms.
[20:57:57.785] <TB2> INFO: Expecting 41600 events.
[20:58:01.294] <TB2> INFO: 41600 events read in total (2917ms).
[20:58:01.295] <TB2> INFO: Test took 3775ms.
[20:58:01.585] <TB2> INFO: Expecting 41600 events.
[20:58:05.116] <TB2> INFO: 41600 events read in total (2939ms).
[20:58:05.117] <TB2> INFO: Test took 3797ms.
[20:58:05.409] <TB2> INFO: Expecting 41600 events.
[20:58:08.899] <TB2> INFO: 41600 events read in total (2899ms).
[20:58:08.900] <TB2> INFO: Test took 3756ms.
[20:58:09.190] <TB2> INFO: Expecting 41600 events.
[20:58:12.852] <TB2> INFO: 41600 events read in total (3071ms).
[20:58:12.854] <TB2> INFO: Test took 3929ms.
[20:58:13.143] <TB2> INFO: Expecting 41600 events.
[20:58:16.672] <TB2> INFO: 41600 events read in total (2938ms).
[20:58:16.673] <TB2> INFO: Test took 3795ms.
[20:58:16.962] <TB2> INFO: Expecting 41600 events.
[20:58:20.507] <TB2> INFO: 41600 events read in total (2954ms).
[20:58:20.508] <TB2> INFO: Test took 3812ms.
[20:58:20.797] <TB2> INFO: Expecting 41600 events.
[20:58:24.484] <TB2> INFO: 41600 events read in total (3095ms).
[20:58:24.485] <TB2> INFO: Test took 3952ms.
[20:58:24.774] <TB2> INFO: Expecting 41600 events.
[20:58:28.347] <TB2> INFO: 41600 events read in total (2982ms).
[20:58:28.348] <TB2> INFO: Test took 3839ms.
[20:58:28.638] <TB2> INFO: Expecting 41600 events.
[20:58:32.257] <TB2> INFO: 41600 events read in total (3027ms).
[20:58:32.257] <TB2> INFO: Test took 3885ms.
[20:58:32.547] <TB2> INFO: Expecting 41600 events.
[20:58:36.184] <TB2> INFO: 41600 events read in total (3045ms).
[20:58:36.185] <TB2> INFO: Test took 3903ms.
[20:58:36.474] <TB2> INFO: Expecting 41600 events.
[20:58:40.017] <TB2> INFO: 41600 events read in total (2952ms).
[20:58:40.018] <TB2> INFO: Test took 3809ms.
[20:58:40.328] <TB2> INFO: Expecting 41600 events.
[20:58:43.795] <TB2> INFO: 41600 events read in total (2875ms).
[20:58:43.796] <TB2> INFO: Test took 3753ms.
[20:58:44.085] <TB2> INFO: Expecting 41600 events.
[20:58:47.585] <TB2> INFO: 41600 events read in total (2908ms).
[20:58:47.586] <TB2> INFO: Test took 3766ms.
[20:58:47.876] <TB2> INFO: Expecting 41600 events.
[20:58:51.502] <TB2> INFO: 41600 events read in total (3034ms).
[20:58:51.502] <TB2> INFO: Test took 3892ms.
[20:58:51.793] <TB2> INFO: Expecting 41600 events.
[20:58:55.378] <TB2> INFO: 41600 events read in total (2993ms).
[20:58:55.378] <TB2> INFO: Test took 3851ms.
[20:58:55.669] <TB2> INFO: Expecting 41600 events.
[20:58:59.156] <TB2> INFO: 41600 events read in total (2896ms).
[20:58:59.157] <TB2> INFO: Test took 3754ms.
[20:58:59.447] <TB2> INFO: Expecting 41600 events.
[20:59:02.910] <TB2> INFO: 41600 events read in total (2871ms).
[20:59:02.911] <TB2> INFO: Test took 3730ms.
[20:59:03.200] <TB2> INFO: Expecting 41600 events.
[20:59:06.729] <TB2> INFO: 41600 events read in total (2937ms).
[20:59:06.730] <TB2> INFO: Test took 3795ms.
[20:59:07.019] <TB2> INFO: Expecting 41600 events.
[20:59:10.519] <TB2> INFO: 41600 events read in total (2908ms).
[20:59:10.520] <TB2> INFO: Test took 3766ms.
[20:59:10.809] <TB2> INFO: Expecting 41600 events.
[20:59:14.410] <TB2> INFO: 41600 events read in total (3009ms).
[20:59:14.411] <TB2> INFO: Test took 3866ms.
[20:59:14.731] <TB2> INFO: Expecting 41600 events.
[20:59:18.300] <TB2> INFO: 41600 events read in total (2977ms).
[20:59:18.301] <TB2> INFO: Test took 3866ms.
[20:59:18.591] <TB2> INFO: Expecting 41600 events.
[20:59:22.091] <TB2> INFO: 41600 events read in total (2908ms).
[20:59:22.092] <TB2> INFO: Test took 3767ms.
[20:59:22.401] <TB2> INFO: Expecting 41600 events.
[20:59:25.914] <TB2> INFO: 41600 events read in total (2921ms).
[20:59:25.915] <TB2> INFO: Test took 3796ms.
[20:59:26.208] <TB2> INFO: Expecting 2560 events.
[20:59:27.102] <TB2> INFO: 2560 events read in total (302ms).
[20:59:27.102] <TB2> INFO: Test took 1171ms.
[20:59:27.410] <TB2> INFO: Expecting 2560 events.
[20:59:28.300] <TB2> INFO: 2560 events read in total (299ms).
[20:59:28.301] <TB2> INFO: Test took 1199ms.
[20:59:28.608] <TB2> INFO: Expecting 2560 events.
[20:59:29.495] <TB2> INFO: 2560 events read in total (295ms).
[20:59:29.495] <TB2> INFO: Test took 1194ms.
[20:59:29.803] <TB2> INFO: Expecting 2560 events.
[20:59:30.699] <TB2> INFO: 2560 events read in total (303ms).
[20:59:30.699] <TB2> INFO: Test took 1203ms.
[20:59:31.007] <TB2> INFO: Expecting 2560 events.
[20:59:31.895] <TB2> INFO: 2560 events read in total (296ms).
[20:59:31.895] <TB2> INFO: Test took 1195ms.
[20:59:32.202] <TB2> INFO: Expecting 2560 events.
[20:59:33.088] <TB2> INFO: 2560 events read in total (295ms).
[20:59:33.088] <TB2> INFO: Test took 1192ms.
[20:59:33.397] <TB2> INFO: Expecting 2560 events.
[20:59:34.288] <TB2> INFO: 2560 events read in total (299ms).
[20:59:34.289] <TB2> INFO: Test took 1200ms.
[20:59:34.597] <TB2> INFO: Expecting 2560 events.
[20:59:35.488] <TB2> INFO: 2560 events read in total (300ms).
[20:59:35.488] <TB2> INFO: Test took 1199ms.
[20:59:35.795] <TB2> INFO: Expecting 2560 events.
[20:59:36.674] <TB2> INFO: 2560 events read in total (286ms).
[20:59:36.674] <TB2> INFO: Test took 1185ms.
[20:59:36.982] <TB2> INFO: Expecting 2560 events.
[20:59:37.867] <TB2> INFO: 2560 events read in total (293ms).
[20:59:37.868] <TB2> INFO: Test took 1194ms.
[20:59:38.175] <TB2> INFO: Expecting 2560 events.
[20:59:39.062] <TB2> INFO: 2560 events read in total (296ms).
[20:59:39.063] <TB2> INFO: Test took 1195ms.
[20:59:39.370] <TB2> INFO: Expecting 2560 events.
[20:59:40.249] <TB2> INFO: 2560 events read in total (288ms).
[20:59:40.249] <TB2> INFO: Test took 1185ms.
[20:59:40.557] <TB2> INFO: Expecting 2560 events.
[20:59:41.443] <TB2> INFO: 2560 events read in total (295ms).
[20:59:41.444] <TB2> INFO: Test took 1194ms.
[20:59:41.752] <TB2> INFO: Expecting 2560 events.
[20:59:42.642] <TB2> INFO: 2560 events read in total (298ms).
[20:59:42.642] <TB2> INFO: Test took 1198ms.
[20:59:42.950] <TB2> INFO: Expecting 2560 events.
[20:59:43.834] <TB2> INFO: 2560 events read in total (292ms).
[20:59:43.835] <TB2> INFO: Test took 1192ms.
[20:59:44.142] <TB2> INFO: Expecting 2560 events.
[20:59:45.030] <TB2> INFO: 2560 events read in total (296ms).
[20:59:45.030] <TB2> INFO: Test took 1195ms.
[20:59:45.037] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:59:45.338] <TB2> INFO: Expecting 655360 events.
[21:00:00.134] <TB2> INFO: 655360 events read in total (14204ms).
[21:00:00.150] <TB2> INFO: Expecting 655360 events.
[21:00:14.925] <TB2> INFO: 655360 events read in total (14372ms).
[21:00:14.942] <TB2> INFO: Expecting 655360 events.
[21:00:29.569] <TB2> INFO: 655360 events read in total (14224ms).
[21:00:29.590] <TB2> INFO: Expecting 655360 events.
[21:00:44.203] <TB2> INFO: 655360 events read in total (14210ms).
[21:00:44.229] <TB2> INFO: Expecting 655360 events.
[21:00:58.746] <TB2> INFO: 655360 events read in total (14114ms).
[21:00:58.775] <TB2> INFO: Expecting 655360 events.
[21:01:13.235] <TB2> INFO: 655360 events read in total (14057ms).
[21:01:13.271] <TB2> INFO: Expecting 655360 events.
[21:01:27.848] <TB2> INFO: 655360 events read in total (14174ms).
[21:01:27.906] <TB2> INFO: Expecting 655360 events.
[21:01:42.300] <TB2> INFO: 655360 events read in total (13991ms).
[21:01:42.342] <TB2> INFO: Expecting 655360 events.
[21:01:57.083] <TB2> INFO: 655360 events read in total (14338ms).
[21:01:57.171] <TB2> INFO: Expecting 655360 events.
[21:02:11.727] <TB2> INFO: 655360 events read in total (14153ms).
[21:02:11.788] <TB2> INFO: Expecting 655360 events.
[21:02:26.276] <TB2> INFO: 655360 events read in total (14085ms).
[21:02:26.345] <TB2> INFO: Expecting 655360 events.
[21:02:40.901] <TB2> INFO: 655360 events read in total (14153ms).
[21:02:40.966] <TB2> INFO: Expecting 655360 events.
[21:02:55.340] <TB2> INFO: 655360 events read in total (13971ms).
[21:02:55.418] <TB2> INFO: Expecting 655360 events.
[21:03:09.854] <TB2> INFO: 655360 events read in total (14033ms).
[21:03:10.097] <TB2> INFO: Expecting 655360 events.
[21:03:24.612] <TB2> INFO: 655360 events read in total (14112ms).
[21:03:24.731] <TB2> INFO: Expecting 655360 events.
[21:03:39.082] <TB2> INFO: 655360 events read in total (13948ms).
[21:03:39.192] <TB2> INFO: Test took 234155ms.
[21:03:39.558] <TB2> INFO: Expecting 655360 events.
[21:04:00.181] <TB2> INFO: 552550 events read in total (20032ms).
[21:04:04.263] <TB2> INFO: 655360 events read in total (24114ms).
[21:04:04.285] <TB2> INFO: Test took 24978ms.
[21:04:04.400] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.406] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[21:04:04.412] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.418] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.425] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[21:04:04.431] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[21:04:04.437] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[21:04:04.443] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[21:04:04.449] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[21:04:04.455] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[21:04:04.462] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[21:04:04.468] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[21:04:04.477] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.484] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.490] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[21:04:04.496] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.502] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.508] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.514] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.521] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[21:04:04.527] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[21:04:04.533] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[21:04:04.540] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[21:04:04.549] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[21:04:04.557] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.565] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[21:04:04.572] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[21:04:04.581] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[21:04:04.588] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[21:04:04.597] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[21:04:04.604] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[21:04:04.613] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[21:04:04.620] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.629] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.636] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[21:04:04.645] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[21:04:04.652] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[21:04:04.661] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.668] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[21:04:04.676] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[21:04:04.684] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[21:04:04.692] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[21:04:04.698] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[21:04:04.704] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.710] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[21:04:04.715] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[21:04:04.721] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[21:04:04.728] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.734] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[21:04:04.766] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C0.dat
[21:04:04.767] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C1.dat
[21:04:04.767] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C2.dat
[21:04:04.767] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C3.dat
[21:04:04.767] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C4.dat
[21:04:04.767] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C5.dat
[21:04:04.767] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C6.dat
[21:04:04.767] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C7.dat
[21:04:04.768] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C8.dat
[21:04:04.768] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C9.dat
[21:04:04.768] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C10.dat
[21:04:04.768] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C11.dat
[21:04:04.768] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C12.dat
[21:04:04.769] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C13.dat
[21:04:04.769] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C14.dat
[21:04:04.769] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters35_C15.dat
[21:04:05.047] <TB2> INFO: Expecting 41600 events.
[21:04:08.211] <TB2> INFO: 41600 events read in total (2572ms).
[21:04:08.212] <TB2> INFO: Test took 3441ms.
[21:04:08.667] <TB2> INFO: Expecting 41600 events.
[21:04:11.796] <TB2> INFO: 41600 events read in total (2537ms).
[21:04:11.797] <TB2> INFO: Test took 3370ms.
[21:04:12.250] <TB2> INFO: Expecting 41600 events.
[21:04:15.425] <TB2> INFO: 41600 events read in total (2583ms).
[21:04:15.427] <TB2> INFO: Test took 3416ms.
[21:04:15.646] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:15.736] <TB2> INFO: Expecting 2560 events.
[21:04:16.628] <TB2> INFO: 2560 events read in total (301ms).
[21:04:16.628] <TB2> INFO: Test took 982ms.
[21:04:16.631] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:16.935] <TB2> INFO: Expecting 2560 events.
[21:04:17.828] <TB2> INFO: 2560 events read in total (302ms).
[21:04:17.828] <TB2> INFO: Test took 1197ms.
[21:04:17.831] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:18.135] <TB2> INFO: Expecting 2560 events.
[21:04:19.029] <TB2> INFO: 2560 events read in total (302ms).
[21:04:19.029] <TB2> INFO: Test took 1198ms.
[21:04:19.032] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:19.335] <TB2> INFO: Expecting 2560 events.
[21:04:20.228] <TB2> INFO: 2560 events read in total (301ms).
[21:04:20.228] <TB2> INFO: Test took 1196ms.
[21:04:20.231] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:20.534] <TB2> INFO: Expecting 2560 events.
[21:04:21.420] <TB2> INFO: 2560 events read in total (294ms).
[21:04:21.420] <TB2> INFO: Test took 1189ms.
[21:04:21.422] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:21.728] <TB2> INFO: Expecting 2560 events.
[21:04:22.628] <TB2> INFO: 2560 events read in total (308ms).
[21:04:22.628] <TB2> INFO: Test took 1206ms.
[21:04:22.631] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:22.934] <TB2> INFO: Expecting 2560 events.
[21:04:23.828] <TB2> INFO: 2560 events read in total (302ms).
[21:04:23.829] <TB2> INFO: Test took 1199ms.
[21:04:23.831] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:24.135] <TB2> INFO: Expecting 2560 events.
[21:04:25.031] <TB2> INFO: 2560 events read in total (304ms).
[21:04:25.032] <TB2> INFO: Test took 1201ms.
[21:04:25.035] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:25.338] <TB2> INFO: Expecting 2560 events.
[21:04:26.225] <TB2> INFO: 2560 events read in total (295ms).
[21:04:26.225] <TB2> INFO: Test took 1190ms.
[21:04:26.229] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:26.533] <TB2> INFO: Expecting 2560 events.
[21:04:27.419] <TB2> INFO: 2560 events read in total (295ms).
[21:04:27.420] <TB2> INFO: Test took 1191ms.
[21:04:27.423] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:27.726] <TB2> INFO: Expecting 2560 events.
[21:04:28.615] <TB2> INFO: 2560 events read in total (298ms).
[21:04:28.615] <TB2> INFO: Test took 1192ms.
[21:04:28.618] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:28.923] <TB2> INFO: Expecting 2560 events.
[21:04:29.807] <TB2> INFO: 2560 events read in total (293ms).
[21:04:29.808] <TB2> INFO: Test took 1190ms.
[21:04:29.812] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:30.114] <TB2> INFO: Expecting 2560 events.
[21:04:30.996] <TB2> INFO: 2560 events read in total (290ms).
[21:04:30.997] <TB2> INFO: Test took 1185ms.
[21:04:30.999] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:31.305] <TB2> INFO: Expecting 2560 events.
[21:04:32.186] <TB2> INFO: 2560 events read in total (290ms).
[21:04:32.187] <TB2> INFO: Test took 1188ms.
[21:04:32.191] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:32.495] <TB2> INFO: Expecting 2560 events.
[21:04:33.377] <TB2> INFO: 2560 events read in total (291ms).
[21:04:33.377] <TB2> INFO: Test took 1186ms.
[21:04:33.381] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:33.685] <TB2> INFO: Expecting 2560 events.
[21:04:34.569] <TB2> INFO: 2560 events read in total (292ms).
[21:04:34.569] <TB2> INFO: Test took 1189ms.
[21:04:34.572] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:34.876] <TB2> INFO: Expecting 2560 events.
[21:04:35.767] <TB2> INFO: 2560 events read in total (300ms).
[21:04:35.767] <TB2> INFO: Test took 1195ms.
[21:04:35.769] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:36.075] <TB2> INFO: Expecting 2560 events.
[21:04:36.960] <TB2> INFO: 2560 events read in total (294ms).
[21:04:36.960] <TB2> INFO: Test took 1191ms.
[21:04:36.963] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:37.268] <TB2> INFO: Expecting 2560 events.
[21:04:38.155] <TB2> INFO: 2560 events read in total (295ms).
[21:04:38.155] <TB2> INFO: Test took 1192ms.
[21:04:38.158] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:38.461] <TB2> INFO: Expecting 2560 events.
[21:04:39.351] <TB2> INFO: 2560 events read in total (298ms).
[21:04:39.352] <TB2> INFO: Test took 1194ms.
[21:04:39.355] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:39.659] <TB2> INFO: Expecting 2560 events.
[21:04:40.544] <TB2> INFO: 2560 events read in total (293ms).
[21:04:40.544] <TB2> INFO: Test took 1189ms.
[21:04:40.546] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:40.852] <TB2> INFO: Expecting 2560 events.
[21:04:41.738] <TB2> INFO: 2560 events read in total (295ms).
[21:04:41.739] <TB2> INFO: Test took 1193ms.
[21:04:41.742] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:42.047] <TB2> INFO: Expecting 2560 events.
[21:04:42.929] <TB2> INFO: 2560 events read in total (291ms).
[21:04:42.929] <TB2> INFO: Test took 1187ms.
[21:04:42.932] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:43.237] <TB2> INFO: Expecting 2560 events.
[21:04:44.121] <TB2> INFO: 2560 events read in total (292ms).
[21:04:44.121] <TB2> INFO: Test took 1189ms.
[21:04:44.125] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:44.428] <TB2> INFO: Expecting 2560 events.
[21:04:45.318] <TB2> INFO: 2560 events read in total (298ms).
[21:04:45.319] <TB2> INFO: Test took 1194ms.
[21:04:45.321] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:45.625] <TB2> INFO: Expecting 2560 events.
[21:04:46.512] <TB2> INFO: 2560 events read in total (295ms).
[21:04:46.512] <TB2> INFO: Test took 1191ms.
[21:04:46.515] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:46.820] <TB2> INFO: Expecting 2560 events.
[21:04:47.706] <TB2> INFO: 2560 events read in total (294ms).
[21:04:47.706] <TB2> INFO: Test took 1191ms.
[21:04:47.711] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:48.014] <TB2> INFO: Expecting 2560 events.
[21:04:48.905] <TB2> INFO: 2560 events read in total (299ms).
[21:04:48.906] <TB2> INFO: Test took 1196ms.
[21:04:48.913] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:49.214] <TB2> INFO: Expecting 2560 events.
[21:04:50.101] <TB2> INFO: 2560 events read in total (296ms).
[21:04:50.101] <TB2> INFO: Test took 1188ms.
[21:04:50.106] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:50.407] <TB2> INFO: Expecting 2560 events.
[21:04:51.301] <TB2> INFO: 2560 events read in total (302ms).
[21:04:51.301] <TB2> INFO: Test took 1195ms.
[21:04:51.304] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:51.608] <TB2> INFO: Expecting 2560 events.
[21:04:52.503] <TB2> INFO: 2560 events read in total (303ms).
[21:04:52.504] <TB2> INFO: Test took 1200ms.
[21:04:52.506] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:04:52.811] <TB2> INFO: Expecting 2560 events.
[21:04:53.706] <TB2> INFO: 2560 events read in total (303ms).
[21:04:53.707] <TB2> INFO: Test took 1201ms.
[21:04:54.183] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 443 seconds
[21:04:54.183] <TB2> INFO: PH scale (per ROC): 42 42 50 43 44 32 48 37 38 48 44 36 48 35 36 40
[21:04:54.183] <TB2> INFO: PH offset (per ROC): 110 111 112 101 109 96 109 95 96 105 107 97 104 106 84 96
[21:04:54.193] <TB2> INFO: Decoding statistics:
[21:04:54.193] <TB2> INFO: General information:
[21:04:54.193] <TB2> INFO: 16bit words read: 127882
[21:04:54.193] <TB2> INFO: valid events total: 20480
[21:04:54.193] <TB2> INFO: empty events: 17979
[21:04:54.193] <TB2> INFO: valid events with pixels: 2501
[21:04:54.193] <TB2> INFO: valid pixel hits: 2501
[21:04:54.193] <TB2> INFO: Event errors: 0
[21:04:54.193] <TB2> INFO: start marker: 0
[21:04:54.193] <TB2> INFO: stop marker: 0
[21:04:54.193] <TB2> INFO: overflow: 0
[21:04:54.193] <TB2> INFO: invalid 5bit words: 0
[21:04:54.193] <TB2> INFO: invalid XOR eye diagram: 0
[21:04:54.193] <TB2> INFO: frame (failed synchr.): 0
[21:04:54.193] <TB2> INFO: idle data (no TBM trl): 0
[21:04:54.193] <TB2> INFO: no data (only TBM hdr): 0
[21:04:54.193] <TB2> INFO: TBM errors: 0
[21:04:54.193] <TB2> INFO: flawed TBM headers: 0
[21:04:54.193] <TB2> INFO: flawed TBM trailers: 0
[21:04:54.193] <TB2> INFO: event ID mismatches: 0
[21:04:54.193] <TB2> INFO: ROC errors: 0
[21:04:54.193] <TB2> INFO: missing ROC header(s): 0
[21:04:54.193] <TB2> INFO: misplaced readback start: 0
[21:04:54.193] <TB2> INFO: Pixel decoding errors: 0
[21:04:54.193] <TB2> INFO: pixel data incomplete: 0
[21:04:54.193] <TB2> INFO: pixel address: 0
[21:04:54.193] <TB2> INFO: pulse height fill bit: 0
[21:04:54.193] <TB2> INFO: buffer corruption: 0
[21:04:54.354] <TB2> INFO: ######################################################################
[21:04:54.354] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[21:04:54.354] <TB2> INFO: ######################################################################
[21:04:54.369] <TB2> INFO: scanning low vcal = 10
[21:04:54.613] <TB2> INFO: Expecting 41600 events.
[21:04:58.231] <TB2> INFO: 41600 events read in total (3026ms).
[21:04:58.231] <TB2> INFO: Test took 3862ms.
[21:04:58.233] <TB2> INFO: scanning low vcal = 20
[21:04:58.527] <TB2> INFO: Expecting 41600 events.
[21:05:02.109] <TB2> INFO: 41600 events read in total (2991ms).
[21:05:02.110] <TB2> INFO: Test took 3877ms.
[21:05:02.112] <TB2> INFO: scanning low vcal = 30
[21:05:02.400] <TB2> INFO: Expecting 41600 events.
[21:05:06.055] <TB2> INFO: 41600 events read in total (3063ms).
[21:05:06.056] <TB2> INFO: Test took 3944ms.
[21:05:06.058] <TB2> INFO: scanning low vcal = 40
[21:05:06.336] <TB2> INFO: Expecting 41600 events.
[21:05:10.343] <TB2> INFO: 41600 events read in total (3414ms).
[21:05:10.344] <TB2> INFO: Test took 4285ms.
[21:05:10.347] <TB2> INFO: scanning low vcal = 50
[21:05:10.625] <TB2> INFO: Expecting 41600 events.
[21:05:14.589] <TB2> INFO: 41600 events read in total (3373ms).
[21:05:14.590] <TB2> INFO: Test took 4243ms.
[21:05:14.593] <TB2> INFO: scanning low vcal = 60
[21:05:14.869] <TB2> INFO: Expecting 41600 events.
[21:05:18.830] <TB2> INFO: 41600 events read in total (3369ms).
[21:05:18.830] <TB2> INFO: Test took 4237ms.
[21:05:18.834] <TB2> INFO: scanning low vcal = 70
[21:05:19.110] <TB2> INFO: Expecting 41600 events.
[21:05:23.129] <TB2> INFO: 41600 events read in total (3427ms).
[21:05:23.130] <TB2> INFO: Test took 4296ms.
[21:05:23.133] <TB2> INFO: scanning low vcal = 80
[21:05:23.410] <TB2> INFO: Expecting 41600 events.
[21:05:27.434] <TB2> INFO: 41600 events read in total (3432ms).
[21:05:27.434] <TB2> INFO: Test took 4301ms.
[21:05:27.438] <TB2> INFO: scanning low vcal = 90
[21:05:27.715] <TB2> INFO: Expecting 41600 events.
[21:05:31.686] <TB2> INFO: 41600 events read in total (3379ms).
[21:05:31.687] <TB2> INFO: Test took 4249ms.
[21:05:31.691] <TB2> INFO: scanning low vcal = 100
[21:05:31.967] <TB2> INFO: Expecting 41600 events.
[21:05:35.972] <TB2> INFO: 41600 events read in total (3414ms).
[21:05:35.972] <TB2> INFO: Test took 4281ms.
[21:05:35.976] <TB2> INFO: scanning low vcal = 110
[21:05:36.253] <TB2> INFO: Expecting 41600 events.
[21:05:40.245] <TB2> INFO: 41600 events read in total (3401ms).
[21:05:40.246] <TB2> INFO: Test took 4270ms.
[21:05:40.250] <TB2> INFO: scanning low vcal = 120
[21:05:40.527] <TB2> INFO: Expecting 41600 events.
[21:05:44.491] <TB2> INFO: 41600 events read in total (3372ms).
[21:05:44.492] <TB2> INFO: Test took 4242ms.
[21:05:44.495] <TB2> INFO: scanning low vcal = 130
[21:05:44.772] <TB2> INFO: Expecting 41600 events.
[21:05:48.742] <TB2> INFO: 41600 events read in total (3379ms).
[21:05:48.743] <TB2> INFO: Test took 4248ms.
[21:05:48.746] <TB2> INFO: scanning low vcal = 140
[21:05:49.023] <TB2> INFO: Expecting 41600 events.
[21:05:52.000] <TB2> INFO: 41600 events read in total (3386ms).
[21:05:52.001] <TB2> INFO: Test took 4255ms.
[21:05:53.004] <TB2> INFO: scanning low vcal = 150
[21:05:53.282] <TB2> INFO: Expecting 41600 events.
[21:05:57.286] <TB2> INFO: 41600 events read in total (3413ms).
[21:05:57.287] <TB2> INFO: Test took 4282ms.
[21:05:57.291] <TB2> INFO: scanning low vcal = 160
[21:05:57.567] <TB2> INFO: Expecting 41600 events.
[21:06:01.517] <TB2> INFO: 41600 events read in total (3358ms).
[21:06:01.518] <TB2> INFO: Test took 4227ms.
[21:06:01.521] <TB2> INFO: scanning low vcal = 170
[21:06:01.798] <TB2> INFO: Expecting 41600 events.
[21:06:05.772] <TB2> INFO: 41600 events read in total (3382ms).
[21:06:05.773] <TB2> INFO: Test took 4252ms.
[21:06:05.779] <TB2> INFO: scanning low vcal = 180
[21:06:06.053] <TB2> INFO: Expecting 41600 events.
[21:06:10.111] <TB2> INFO: 41600 events read in total (3466ms).
[21:06:10.112] <TB2> INFO: Test took 4333ms.
[21:06:10.115] <TB2> INFO: scanning low vcal = 190
[21:06:10.392] <TB2> INFO: Expecting 41600 events.
[21:06:14.351] <TB2> INFO: 41600 events read in total (3367ms).
[21:06:14.352] <TB2> INFO: Test took 4237ms.
[21:06:14.355] <TB2> INFO: scanning low vcal = 200
[21:06:14.631] <TB2> INFO: Expecting 41600 events.
[21:06:18.585] <TB2> INFO: 41600 events read in total (3362ms).
[21:06:18.587] <TB2> INFO: Test took 4232ms.
[21:06:18.591] <TB2> INFO: scanning low vcal = 210
[21:06:18.870] <TB2> INFO: Expecting 41600 events.
[21:06:22.870] <TB2> INFO: 41600 events read in total (3408ms).
[21:06:22.871] <TB2> INFO: Test took 4280ms.
[21:06:22.874] <TB2> INFO: scanning low vcal = 220
[21:06:23.152] <TB2> INFO: Expecting 41600 events.
[21:06:27.126] <TB2> INFO: 41600 events read in total (3383ms).
[21:06:27.127] <TB2> INFO: Test took 4253ms.
[21:06:27.130] <TB2> INFO: scanning low vcal = 230
[21:06:27.408] <TB2> INFO: Expecting 41600 events.
[21:06:31.431] <TB2> INFO: 41600 events read in total (3432ms).
[21:06:31.432] <TB2> INFO: Test took 4301ms.
[21:06:31.436] <TB2> INFO: scanning low vcal = 240
[21:06:31.718] <TB2> INFO: Expecting 41600 events.
[21:06:35.719] <TB2> INFO: 41600 events read in total (3409ms).
[21:06:35.720] <TB2> INFO: Test took 4284ms.
[21:06:35.723] <TB2> INFO: scanning low vcal = 250
[21:06:35.000] <TB2> INFO: Expecting 41600 events.
[21:06:39.984] <TB2> INFO: 41600 events read in total (3392ms).
[21:06:39.985] <TB2> INFO: Test took 4262ms.
[21:06:39.989] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[21:06:40.265] <TB2> INFO: Expecting 41600 events.
[21:06:44.236] <TB2> INFO: 41600 events read in total (3379ms).
[21:06:44.237] <TB2> INFO: Test took 4248ms.
[21:06:44.240] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[21:06:44.517] <TB2> INFO: Expecting 41600 events.
[21:06:48.510] <TB2> INFO: 41600 events read in total (3401ms).
[21:06:48.511] <TB2> INFO: Test took 4270ms.
[21:06:48.515] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[21:06:48.791] <TB2> INFO: Expecting 41600 events.
[21:06:52.808] <TB2> INFO: 41600 events read in total (3425ms).
[21:06:52.809] <TB2> INFO: Test took 4294ms.
[21:06:52.813] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[21:06:53.090] <TB2> INFO: Expecting 41600 events.
[21:06:57.115] <TB2> INFO: 41600 events read in total (3433ms).
[21:06:57.116] <TB2> INFO: Test took 4303ms.
[21:06:57.119] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[21:06:57.395] <TB2> INFO: Expecting 41600 events.
[21:07:01.343] <TB2> INFO: 41600 events read in total (3356ms).
[21:07:01.344] <TB2> INFO: Test took 4225ms.
[21:07:01.755] <TB2> INFO: PixTestGainPedestal::measure() done
[21:07:34.173] <TB2> INFO: PixTestGainPedestal::fit() done
[21:07:34.173] <TB2> INFO: non-linearity mean: 0.942 0.896 0.967 0.909 0.944 0.884 0.958 0.946 0.891 0.961 0.962 0.920 0.969 0.924 0.936 0.930
[21:07:34.173] <TB2> INFO: non-linearity RMS: 0.061 0.136 0.018 0.122 0.055 0.167 0.025 0.171 0.135 0.048 0.031 0.107 0.011 0.122 0.162 0.119
[21:07:34.173] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[21:07:34.186] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[21:07:34.199] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[21:07:34.212] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[21:07:34.225] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[21:07:34.238] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[21:07:34.251] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[21:07:34.264] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[21:07:34.277] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[21:07:34.290] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[21:07:34.303] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[21:07:34.316] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[21:07:34.329] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[21:07:34.342] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[21:07:34.355] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[21:07:34.369] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[21:07:34.382] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 160 seconds
[21:07:34.382] <TB2> INFO: Decoding statistics:
[21:07:34.382] <TB2> INFO: General information:
[21:07:34.382] <TB2> INFO: 16bit words read: 3317232
[21:07:34.382] <TB2> INFO: valid events total: 332800
[21:07:34.382] <TB2> INFO: empty events: 264
[21:07:34.382] <TB2> INFO: valid events with pixels: 332536
[21:07:34.382] <TB2> INFO: valid pixel hits: 660216
[21:07:34.382] <TB2> INFO: Event errors: 0
[21:07:34.382] <TB2> INFO: start marker: 0
[21:07:34.382] <TB2> INFO: stop marker: 0
[21:07:34.382] <TB2> INFO: overflow: 0
[21:07:34.382] <TB2> INFO: invalid 5bit words: 0
[21:07:34.382] <TB2> INFO: invalid XOR eye diagram: 0
[21:07:34.382] <TB2> INFO: frame (failed synchr.): 0
[21:07:34.382] <TB2> INFO: idle data (no TBM trl): 0
[21:07:34.382] <TB2> INFO: no data (only TBM hdr): 0
[21:07:34.382] <TB2> INFO: TBM errors: 0
[21:07:34.382] <TB2> INFO: flawed TBM headers: 0
[21:07:34.382] <TB2> INFO: flawed TBM trailers: 0
[21:07:34.382] <TB2> INFO: event ID mismatches: 0
[21:07:34.382] <TB2> INFO: ROC errors: 0
[21:07:34.382] <TB2> INFO: missing ROC header(s): 0
[21:07:34.382] <TB2> INFO: misplaced readback start: 0
[21:07:34.382] <TB2> INFO: Pixel decoding errors: 0
[21:07:34.382] <TB2> INFO: pixel data incomplete: 0
[21:07:34.382] <TB2> INFO: pixel address: 0
[21:07:34.382] <TB2> INFO: pulse height fill bit: 0
[21:07:34.382] <TB2> INFO: buffer corruption: 0
[21:07:34.399] <TB2> INFO: Decoding statistics:
[21:07:34.399] <TB2> INFO: General information:
[21:07:34.399] <TB2> INFO: 16bit words read: 3446650
[21:07:34.399] <TB2> INFO: valid events total: 353536
[21:07:34.399] <TB2> INFO: empty events: 18499
[21:07:34.399] <TB2> INFO: valid events with pixels: 335037
[21:07:34.399] <TB2> INFO: valid pixel hits: 662717
[21:07:34.399] <TB2> INFO: Event errors: 0
[21:07:34.399] <TB2> INFO: start marker: 0
[21:07:34.399] <TB2> INFO: stop marker: 0
[21:07:34.399] <TB2> INFO: overflow: 0
[21:07:34.399] <TB2> INFO: invalid 5bit words: 0
[21:07:34.399] <TB2> INFO: invalid XOR eye diagram: 0
[21:07:34.399] <TB2> INFO: frame (failed synchr.): 0
[21:07:34.399] <TB2> INFO: idle data (no TBM trl): 0
[21:07:34.399] <TB2> INFO: no data (only TBM hdr): 0
[21:07:34.399] <TB2> INFO: TBM errors: 0
[21:07:34.399] <TB2> INFO: flawed TBM headers: 0
[21:07:34.399] <TB2> INFO: flawed TBM trailers: 0
[21:07:34.399] <TB2> INFO: event ID mismatches: 0
[21:07:34.399] <TB2> INFO: ROC errors: 0
[21:07:34.399] <TB2> INFO: missing ROC header(s): 0
[21:07:34.399] <TB2> INFO: misplaced readback start: 0
[21:07:34.399] <TB2> INFO: Pixel decoding errors: 0
[21:07:34.399] <TB2> INFO: pixel data incomplete: 0
[21:07:34.399] <TB2> INFO: pixel address: 0
[21:07:34.399] <TB2> INFO: pulse height fill bit: 0
[21:07:34.399] <TB2> INFO: buffer corruption: 0
[21:07:34.399] <TB2> INFO: enter test to run
[21:07:34.399] <TB2> INFO: test: trim80 no parameter change
[21:07:34.399] <TB2> INFO: running: trim80
[21:07:34.401] <TB2> INFO: ######################################################################
[21:07:34.401] <TB2> INFO: PixTestTrim80::doTest()
[21:07:34.401] <TB2> INFO: ######################################################################
[21:07:34.402] <TB2> INFO: ----------------------------------------------------------------------
[21:07:34.402] <TB2> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[21:07:34.402] <TB2> INFO: ----------------------------------------------------------------------
[21:07:34.453] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[21:07:34.453] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[21:07:34.466] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[21:07:34.466] <TB2> INFO: run 1 of 1
[21:07:34.705] <TB2> INFO: Expecting 5025280 events.
[21:08:02.646] <TB2> INFO: 670408 events read in total (27349ms).
[21:08:30.436] <TB2> INFO: 1335992 events read in total (55139ms).
[21:08:58.585] <TB2> INFO: 1999840 events read in total (83288ms).
[21:09:26.620] <TB2> INFO: 2663216 events read in total (111323ms).
[21:09:54.776] <TB2> INFO: 3328064 events read in total (139479ms).
[21:10:22.470] <TB2> INFO: 3992288 events read in total (167173ms).
[21:10:49.629] <TB2> INFO: 4656016 events read in total (194332ms).
[21:11:04.538] <TB2> INFO: 5025280 events read in total (209241ms).
[21:11:04.605] <TB2> INFO: Test took 210139ms.
[21:11:27.987] <TB2> INFO: ROC 0 VthrComp = 67
[21:11:27.987] <TB2> INFO: ROC 1 VthrComp = 73
[21:11:27.988] <TB2> INFO: ROC 2 VthrComp = 73
[21:11:27.988] <TB2> INFO: ROC 3 VthrComp = 78
[21:11:27.988] <TB2> INFO: ROC 4 VthrComp = 81
[21:11:27.988] <TB2> INFO: ROC 5 VthrComp = 77
[21:11:27.989] <TB2> INFO: ROC 6 VthrComp = 68
[21:11:27.989] <TB2> INFO: ROC 7 VthrComp = 68
[21:11:27.989] <TB2> INFO: ROC 8 VthrComp = 90
[21:11:27.989] <TB2> INFO: ROC 9 VthrComp = 78
[21:11:27.989] <TB2> INFO: ROC 10 VthrComp = 72
[21:11:27.989] <TB2> INFO: ROC 11 VthrComp = 73
[21:11:27.989] <TB2> INFO: ROC 12 VthrComp = 73
[21:11:27.989] <TB2> INFO: ROC 13 VthrComp = 75
[21:11:27.989] <TB2> INFO: ROC 14 VthrComp = 70
[21:11:27.989] <TB2> INFO: ROC 15 VthrComp = 74
[21:11:28.265] <TB2> INFO: Expecting 41600 events.
[21:11:31.904] <TB2> INFO: 41600 events read in total (3048ms).
[21:11:31.905] <TB2> INFO: Test took 3914ms.
[21:11:31.914] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[21:11:31.914] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[21:11:31.928] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[21:11:31.928] <TB2> INFO: run 1 of 1
[21:11:32.206] <TB2> INFO: Expecting 5025280 events.
[21:12:00.017] <TB2> INFO: 685792 events read in total (27220ms).
[21:12:27.508] <TB2> INFO: 1368448 events read in total (54711ms).
[21:12:54.970] <TB2> INFO: 2049992 events read in total (82173ms).
[21:13:22.625] <TB2> INFO: 2728456 events read in total (109828ms).
[21:13:49.642] <TB2> INFO: 3401456 events read in total (136845ms).
[21:14:16.884] <TB2> INFO: 4074376 events read in total (164087ms).
[21:14:44.292] <TB2> INFO: 4745296 events read in total (191495ms).
[21:14:55.833] <TB2> INFO: 5025280 events read in total (203036ms).
[21:14:55.896] <TB2> INFO: Test took 203968ms.
[21:15:20.893] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 105.231 for pixel 51/27 mean/min/max = 89.8896/74.5464/105.233
[21:15:20.894] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 105.778 for pixel 11/66 mean/min/max = 91.5562/77.3093/105.803
[21:15:20.894] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 105.582 for pixel 2/54 mean/min/max = 92/78.2839/105.716
[21:15:20.895] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 104.521 for pixel 51/56 mean/min/max = 91.4832/78.166/104.8
[21:15:20.896] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 109.97 for pixel 0/47 mean/min/max = 92.5977/75.1259/110.07
[21:15:20.896] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 110.231 for pixel 13/71 mean/min/max = 94.2906/78.2715/110.31
[21:15:20.897] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 107.5 for pixel 6/11 mean/min/max = 91.3205/75.0604/107.581
[21:15:20.897] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 112.986 for pixel 0/62 mean/min/max = 93.4475/73.857/113.038
[21:15:20.898] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 105.763 for pixel 19/14 mean/min/max = 91.2117/76.568/105.855
[21:15:20.898] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 109.086 for pixel 11/73 mean/min/max = 93.4449/77.7958/109.094
[21:15:20.899] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 110.002 for pixel 28/79 mean/min/max = 94.1407/78.1502/110.131
[21:15:20.899] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 109.09 for pixel 7/1 mean/min/max = 93.7756/78.2158/109.335
[21:15:20.900] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 108.024 for pixel 0/12 mean/min/max = 92.3618/76.6525/108.071
[21:15:20.900] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 105.825 for pixel 41/71 mean/min/max = 91.8379/77.8457/105.83
[21:15:20.901] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 106.57 for pixel 0/31 mean/min/max = 90.3961/74.1544/106.638
[21:15:20.902] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 108.939 for pixel 0/17 mean/min/max = 93.0063/77.0091/109.003
[21:15:20.902] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[21:15:20.992] <TB2> INFO: Expecting 411648 events.
[21:15:30.496] <TB2> INFO: 411648 events read in total (8912ms).
[21:15:30.503] <TB2> INFO: Expecting 411648 events.
[21:15:39.834] <TB2> INFO: 411648 events read in total (8928ms).
[21:15:39.848] <TB2> INFO: Expecting 411648 events.
[21:15:49.129] <TB2> INFO: 411648 events read in total (8878ms).
[21:15:49.146] <TB2> INFO: Expecting 411648 events.
[21:15:58.472] <TB2> INFO: 411648 events read in total (8923ms).
[21:15:58.489] <TB2> INFO: Expecting 411648 events.
[21:16:07.599] <TB2> INFO: 411648 events read in total (8707ms).
[21:16:07.622] <TB2> INFO: Expecting 411648 events.
[21:16:16.816] <TB2> INFO: 411648 events read in total (8791ms).
[21:16:16.839] <TB2> INFO: Expecting 411648 events.
[21:16:25.972] <TB2> INFO: 411648 events read in total (8730ms).
[21:16:25.997] <TB2> INFO: Expecting 411648 events.
[21:16:35.209] <TB2> INFO: 411648 events read in total (8809ms).
[21:16:35.237] <TB2> INFO: Expecting 411648 events.
[21:16:44.432] <TB2> INFO: 411648 events read in total (8792ms).
[21:16:44.463] <TB2> INFO: Expecting 411648 events.
[21:16:53.684] <TB2> INFO: 411648 events read in total (8818ms).
[21:16:53.720] <TB2> INFO: Expecting 411648 events.
[21:17:02.905] <TB2> INFO: 411648 events read in total (8783ms).
[21:17:02.973] <TB2> INFO: Expecting 411648 events.
[21:17:12.227] <TB2> INFO: 411648 events read in total (8851ms).
[21:17:12.269] <TB2> INFO: Expecting 411648 events.
[21:17:21.563] <TB2> INFO: 411648 events read in total (8891ms).
[21:17:21.735] <TB2> INFO: Expecting 411648 events.
[21:17:30.935] <TB2> INFO: 411648 events read in total (8797ms).
[21:17:31.008] <TB2> INFO: Expecting 411648 events.
[21:17:40.341] <TB2> INFO: 411648 events read in total (8930ms).
[21:17:40.399] <TB2> INFO: Expecting 411648 events.
[21:17:49.703] <TB2> INFO: 411648 events read in total (8900ms).
[21:17:49.765] <TB2> INFO: Test took 148863ms.
[21:17:51.273] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[21:17:51.286] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[21:17:51.286] <TB2> INFO: run 1 of 1
[21:17:51.522] <TB2> INFO: Expecting 5025280 events.
[21:18:19.371] <TB2> INFO: 671104 events read in total (27258ms).
[21:18:46.428] <TB2> INFO: 1339896 events read in total (54314ms).
[21:19:13.639] <TB2> INFO: 2006480 events read in total (81525ms).
[21:19:40.726] <TB2> INFO: 2668608 events read in total (108612ms).
[21:20:07.965] <TB2> INFO: 3326224 events read in total (135851ms).
[21:20:34.952] <TB2> INFO: 3980960 events read in total (162838ms).
[21:21:02.148] <TB2> INFO: 4632816 events read in total (190034ms).
[21:21:18.312] <TB2> INFO: 5025280 events read in total (206198ms).
[21:21:18.387] <TB2> INFO: Test took 207101ms.
[21:21:39.417] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 52.411578 .. 100.554117
[21:21:39.658] <TB2> INFO: Expecting 208000 events.
[21:21:49.235] <TB2> INFO: 208000 events read in total (8986ms).
[21:21:49.235] <TB2> INFO: Test took 9816ms.
[21:21:49.287] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 42 .. 110 (-1/-1) hits flags = 528 (plus default)
[21:21:49.303] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[21:21:49.303] <TB2> INFO: run 1 of 1
[21:21:49.582] <TB2> INFO: Expecting 2296320 events.
[21:22:18.294] <TB2> INFO: 693752 events read in total (28120ms).
[21:22:46.039] <TB2> INFO: 1384336 events read in total (55865ms).
[21:23:13.594] <TB2> INFO: 2062640 events read in total (83420ms).
[21:23:23.530] <TB2> INFO: 2296320 events read in total (93356ms).
[21:23:23.565] <TB2> INFO: Test took 94262ms.
[21:23:40.416] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 60.999315 .. 92.186888
[21:23:40.656] <TB2> INFO: Expecting 208000 events.
[21:23:50.243] <TB2> INFO: 208000 events read in total (8996ms).
[21:23:50.244] <TB2> INFO: Test took 9827ms.
[21:23:50.293] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 50 .. 102 (-1/-1) hits flags = 528 (plus default)
[21:23:50.307] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[21:23:50.307] <TB2> INFO: run 1 of 1
[21:23:50.585] <TB2> INFO: Expecting 1763840 events.
[21:24:19.475] <TB2> INFO: 695016 events read in total (28298ms).
[21:24:47.764] <TB2> INFO: 1389560 events read in total (56587ms).
[21:25:02.998] <TB2> INFO: 1763840 events read in total (71821ms).
[21:25:03.030] <TB2> INFO: Test took 72723ms.
[21:25:20.926] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 65.557594 .. 87.083566
[21:25:21.199] <TB2> INFO: Expecting 208000 events.
[21:25:30.964] <TB2> INFO: 208000 events read in total (9173ms).
[21:25:30.965] <TB2> INFO: Test took 10038ms.
[21:25:31.016] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 55 .. 97 (-1/-1) hits flags = 528 (plus default)
[21:25:31.029] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[21:25:31.029] <TB2> INFO: run 1 of 1
[21:25:31.308] <TB2> INFO: Expecting 1431040 events.
[21:26:00.996] <TB2> INFO: 701704 events read in total (29096ms).
[21:26:29.430] <TB2> INFO: 1403088 events read in total (57531ms).
[21:26:30.954] <TB2> INFO: 1431040 events read in total (59054ms).
[21:26:30.977] <TB2> INFO: Test took 59948ms.
[21:26:47.109] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 66.225643 .. 85.043784
[21:26:47.347] <TB2> INFO: Expecting 208000 events.
[21:26:57.157] <TB2> INFO: 208000 events read in total (9218ms).
[21:26:57.158] <TB2> INFO: Test took 10047ms.
[21:26:57.239] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 56 .. 95 (-1/-1) hits flags = 528 (plus default)
[21:26:57.254] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[21:26:57.254] <TB2> INFO: run 1 of 1
[21:26:57.561] <TB2> INFO: Expecting 1331200 events.
[21:27:26.428] <TB2> INFO: 710472 events read in total (28275ms).
[21:27:50.829] <TB2> INFO: 1331200 events read in total (52676ms).
[21:27:50.856] <TB2> INFO: Test took 53603ms.
[21:28:08.155] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[21:28:08.155] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[21:28:08.169] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[21:28:08.169] <TB2> INFO: run 1 of 1
[21:28:08.448] <TB2> INFO: Expecting 1364480 events.
[21:28:36.824] <TB2> INFO: 669152 events read in total (27784ms).
[21:29:03.946] <TB2> INFO: 1337864 events read in total (54906ms).
[21:29:05.474] <TB2> INFO: 1364480 events read in total (56434ms).
[21:29:05.496] <TB2> INFO: Test took 57327ms.
[21:29:20.980] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C0.dat
[21:29:20.980] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C1.dat
[21:29:20.980] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C2.dat
[21:29:20.981] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C3.dat
[21:29:20.981] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C4.dat
[21:29:20.981] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C5.dat
[21:29:20.981] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C6.dat
[21:29:20.981] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C7.dat
[21:29:20.981] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C8.dat
[21:29:20.981] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C9.dat
[21:29:20.981] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C10.dat
[21:29:20.981] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C11.dat
[21:29:20.981] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C12.dat
[21:29:20.982] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C13.dat
[21:29:20.982] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C14.dat
[21:29:20.982] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//dacParameters80_C15.dat
[21:29:20.982] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C0.dat
[21:29:20.990] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C1.dat
[21:29:20.998] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C2.dat
[21:29:21.006] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C3.dat
[21:29:21.014] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C4.dat
[21:29:21.022] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C5.dat
[21:29:21.030] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C6.dat
[21:29:21.037] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C7.dat
[21:29:21.045] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C8.dat
[21:29:21.053] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C9.dat
[21:29:21.061] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C10.dat
[21:29:21.068] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C11.dat
[21:29:21.076] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C12.dat
[21:29:21.084] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C13.dat
[21:29:21.091] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C14.dat
[21:29:21.099] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1095_FullQualification_2016-10-26_17h20m_1477495221//003_FulltestTrim80_p17//trimParameters80_C15.dat
[21:29:21.107] <TB2> INFO: PixTestTrim80::trimTest() done
[21:29:21.107] <TB2> INFO: vtrim: 93 106 101 97 112 110 100 118 115 100 112 98 89 90 88 106
[21:29:21.107] <TB2> INFO: vthrcomp: 67 73 73 78 81 77 68 68 90 78 72 73 73 75 70 74
[21:29:21.107] <TB2> INFO: vcal mean: 79.96 80.04 79.96 80.02 80.00 80.01 80.00 80.02 80.04 80.02 79.96 80.00 80.04 80.02 80.03 80.04
[21:29:21.107] <TB2> INFO: vcal RMS: 0.86 0.73 1.42 1.42 0.75 0.74 0.76 1.47 0.69 0.71 1.44 0.71 0.69 0.67 0.72 0.77
[21:29:21.107] <TB2> INFO: bits mean: 10.23 10.08 9.63 9.60 9.73 9.03 10.42 9.93 9.87 9.21 9.32 9.18 9.62 9.53 10.33 9.71
[21:29:21.107] <TB2> INFO: bits RMS: 2.45 2.12 2.14 2.18 2.47 2.31 2.30 2.53 2.30 2.36 2.27 2.30 2.30 2.28 2.43 2.24
[21:29:21.115] <TB2> INFO: ----------------------------------------------------------------------
[21:29:21.115] <TB2> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[21:29:21.115] <TB2> INFO: ----------------------------------------------------------------------
[21:29:21.117] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[21:29:21.132] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[21:29:21.133] <TB2> INFO: run 1 of 1
[21:29:21.410] <TB2> INFO: Expecting 4160000 events.
[21:29:53.738] <TB2> INFO: 752830 events read in total (31736ms).
[21:30:26.555] <TB2> INFO: 1502020 events read in total (64553ms).
[21:30:58.294] <TB2> INFO: 2245400 events read in total (96292ms).
[21:31:29.899] <TB2> INFO: 2981170 events read in total (127897ms).
[21:32:01.664] <TB2> INFO: 3716790 events read in total (159662ms).
[21:32:21.017] <TB2> INFO: 4160000 events read in total (179015ms).
[21:32:21.270] <TB2> INFO: Test took 180137ms.
[21:32:48.295] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[21:32:48.308] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[21:32:48.308] <TB2> INFO: run 1 of 1
[21:32:48.547] <TB2> INFO: Expecting 4264000 events.
[21:33:20.118] <TB2> INFO: 724605 events read in total (30980ms).
[21:33:51.149] <TB2> INFO: 1446015 events read in total (62011ms).
[21:34:22.518] <TB2> INFO: 2162710 events read in total (93381ms).
[21:34:53.360] <TB2> INFO: 2873020 events read in total (124222ms).
[21:35:24.015] <TB2> INFO: 3581230 events read in total (154877ms).
[21:35:53.758] <TB2> INFO: 4264000 events read in total (184620ms).
[21:35:53.833] <TB2> INFO: Test took 185524ms.
[21:36:18.671] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[21:36:18.685] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[21:36:18.685] <TB2> INFO: run 1 of 1
[21:36:18.950] <TB2> INFO: Expecting 4097600 events.
[21:36:50.928] <TB2> INFO: 735715 events read in total (31386ms).
[21:37:22.504] <TB2> INFO: 1467525 events read in total (62962ms).
[21:37:53.708] <TB2> INFO: 2193840 events read in total (94166ms).
[21:38:24.905] <TB2> INFO: 2913880 events read in total (125363ms).
[21:38:56.075] <TB2> INFO: 3631425 events read in total (156533ms).
[21:39:16.535] <TB2> INFO: 4097600 events read in total (176993ms).
[21:39:16.754] <TB2> INFO: Test took 178068ms.
[21:39:40.506] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 197 (-1/-1) hits flags = 528 (plus default)
[21:39:40.520] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[21:39:40.520] <TB2> INFO: run 1 of 1
[21:39:40.758] <TB2> INFO: Expecting 4118400 events.
[21:40:12.428] <TB2> INFO: 734560 events read in total (31079ms).
[21:40:43.792] <TB2> INFO: 1465270 events read in total (62443ms).
[21:41:15.273] <TB2> INFO: 2190805 events read in total (93924ms).
[21:41:46.621] <TB2> INFO: 2909750 events read in total (125272ms).
[21:42:17.666] <TB2> INFO: 3626320 events read in total (156317ms).
[21:42:39.265] <TB2> INFO: 4118400 events read in total (177916ms).
[21:42:39.345] <TB2> INFO: Test took 178824ms.
[21:43:04.506] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[21:43:04.520] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[21:43:04.521] <TB2> INFO: run 1 of 1
[21:43:04.767] <TB2> INFO: Expecting 4097600 events.
[21:43:37.189] <TB2> INFO: 736010 events read in total (31831ms).
[21:44:08.490] <TB2> INFO: 1468230 events read in total (63132ms).
[21:44:39.831] <TB2> INFO: 2195235 events read in total (94473ms).
[21:45:11.009] <TB2> INFO: 2915510 events read in total (125651ms).
[21:45:42.490] <TB2> INFO: 3633545 events read in total (157132ms).
[21:46:03.525] <TB2> INFO: 4097600 events read in total (178167ms).
[21:46:03.772] <TB2> INFO: Test took 179251ms.
[21:46:28.504] <TB2> INFO: PixTestTrim80::trimBitTest() done
[21:46:28.505] <TB2> INFO: PixTestTrim80::doTest() done, duration: 2334 seconds
[21:46:29.232] <TB2> INFO: enter test to run
[21:46:29.232] <TB2> INFO: test: exit no parameter change
[21:46:29.426] <TB2> QUIET: Connection to board 149 closed.
[21:46:29.427] <TB2> INFO: pXar: this is the end, my friend