[19:02:06.815] <TB1> INFO: *** Welcome to pxar ***
[19:02:06.815] <TB1> INFO: *** Today: 2016/10/26
[19:02:06.821] <TB1> INFO: *** Version: c8ba-dirty
[19:02:06.821] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C15.dat
[19:02:06.821] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[19:02:06.821] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//defaultMaskFile.dat
[19:02:06.821] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters_C15.dat
[19:02:06.876] <TB1> INFO: clk: 4
[19:02:06.876] <TB1> INFO: ctr: 4
[19:02:06.876] <TB1> INFO: sda: 19
[19:02:06.876] <TB1> INFO: tin: 9
[19:02:06.876] <TB1> INFO: level: 15
[19:02:06.876] <TB1> INFO: triggerdelay: 0
[19:02:06.876] <TB1> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[19:02:06.876] <TB1> INFO: Log level: INFO
[19:02:06.884] <TB1> INFO: Found DTB DTB_WXBYFL
[19:02:06.895] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[19:02:06.897] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
------------------------------------------------------
[19:02:06.898] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[19:02:08.453] <TB1> INFO: DUT info:
[19:02:08.453] <TB1> INFO: The DUT currently contains the following objects:
[19:02:08.453] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[19:02:08.453] <TB1> INFO: TBM Core alpha (0): 7 registers set
[19:02:08.453] <TB1> INFO: TBM Core beta (1): 7 registers set
[19:02:08.453] <TB1> INFO: TBM Core alpha (2): 7 registers set
[19:02:08.453] <TB1> INFO: TBM Core beta (3): 7 registers set
[19:02:08.453] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[19:02:08.453] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.453] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:08.854] <TB1> INFO: enter 'restricted' command line mode
[19:02:08.854] <TB1> INFO: enter test to run
[19:02:08.854] <TB1> INFO: test: pretest no parameter change
[19:02:08.854] <TB1> INFO: running: pretest
[19:02:09.414] <TB1> INFO: ######################################################################
[19:02:09.414] <TB1> INFO: PixTestPretest::doTest()
[19:02:09.414] <TB1> INFO: ######################################################################
[19:02:09.415] <TB1> INFO: ----------------------------------------------------------------------
[19:02:09.415] <TB1> INFO: PixTestPretest::programROC()
[19:02:09.415] <TB1> INFO: ----------------------------------------------------------------------
[19:02:27.428] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[19:02:27.428] <TB1> INFO: IA differences per ROC: 19.3 20.9 18.5 19.3 19.3 18.5 20.1 20.1 19.3 20.9 20.1 20.1 19.3 18.5 18.5 19.3
[19:02:27.462] <TB1> INFO: ----------------------------------------------------------------------
[19:02:27.462] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[19:02:27.462] <TB1> INFO: ----------------------------------------------------------------------
[19:02:48.705] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 380.2 mA = 23.7625 mA/ROC
[19:02:48.705] <TB1> INFO: i(loss) [mA/ROC]: 18.4 20.1 18.4 20.1 20.1 19.3 19.3 18.4 18.4 18.4 18.4 19.3 18.4 19.3 19.3 19.3
[19:02:48.733] <TB1> INFO: ----------------------------------------------------------------------
[19:02:48.733] <TB1> INFO: PixTestPretest::findTiming()
[19:02:48.733] <TB1> INFO: ----------------------------------------------------------------------
[19:02:48.733] <TB1> INFO: PixTestCmd::init()

[19:03:19.900] <TB1> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[19:03:19.900] <TB1> INFO: (success/tries = 100/100), width = 4
[19:03:21.399] <TB1> INFO: ----------------------------------------------------------------------
[19:03:21.399] <TB1> INFO: PixTestPretest::findWorkingPixel()
[19:03:21.399] <TB1> INFO: ----------------------------------------------------------------------
[19:03:21.490] <TB1> INFO: Expecting 231680 events.
[19:03:31.106] <TB1> INFO: 231680 events read in total (9024ms).
[19:03:31.113] <TB1> INFO: Test took 9712ms.
[19:03:31.358] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[19:03:31.387] <TB1> INFO: ----------------------------------------------------------------------
[19:03:31.387] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[19:03:31.387] <TB1> INFO: ----------------------------------------------------------------------
[19:03:31.479] <TB1> INFO: Expecting 231680 events.
[19:03:41.088] <TB1> INFO: 231680 events read in total (9018ms).
[19:03:41.097] <TB1> INFO: Test took 9707ms.
[19:03:41.356] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[19:03:41.356] <TB1> INFO: CalDel: 92 97 90 111 81 91 95 86 91 118 78 83 79 65 90 95
[19:03:41.356] <TB1> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 53 51 51
[19:03:41.358] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C0.dat
[19:03:41.358] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C1.dat
[19:03:41.359] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C2.dat
[19:03:41.359] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C3.dat
[19:03:41.359] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C4.dat
[19:03:41.359] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C5.dat
[19:03:41.359] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C6.dat
[19:03:41.359] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C7.dat
[19:03:41.359] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C8.dat
[19:03:41.359] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C9.dat
[19:03:41.359] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C10.dat
[19:03:41.360] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C11.dat
[19:03:41.360] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C12.dat
[19:03:41.360] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C13.dat
[19:03:41.360] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C14.dat
[19:03:41.360] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C15.dat
[19:03:41.360] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[19:03:41.360] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[19:03:41.360] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[19:03:41.360] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[19:03:41.360] <TB1> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[19:03:41.491] <TB1> INFO: enter test to run
[19:03:41.491] <TB1> INFO: test: fulltest no parameter change
[19:03:41.492] <TB1> INFO: running: fulltest
[19:03:41.492] <TB1> INFO: ######################################################################
[19:03:41.492] <TB1> INFO: PixTestFullTest::doTest()
[19:03:41.492] <TB1> INFO: ######################################################################
[19:03:41.493] <TB1> INFO: ######################################################################
[19:03:41.493] <TB1> INFO: PixTestAlive::doTest()
[19:03:41.493] <TB1> INFO: ######################################################################
[19:03:41.494] <TB1> INFO: ----------------------------------------------------------------------
[19:03:41.494] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[19:03:41.494] <TB1> INFO: ----------------------------------------------------------------------
[19:03:41.730] <TB1> INFO: Expecting 41600 events.
[19:03:45.193] <TB1> INFO: 41600 events read in total (2871ms).
[19:03:45.193] <TB1> INFO: Test took 3696ms.
[19:03:45.421] <TB1> INFO: PixTestAlive::aliveTest() done
[19:03:45.421] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[19:03:45.422] <TB1> INFO: ----------------------------------------------------------------------
[19:03:45.422] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[19:03:45.422] <TB1> INFO: ----------------------------------------------------------------------
[19:03:45.655] <TB1> INFO: Expecting 41600 events.
[19:03:48.587] <TB1> INFO: 41600 events read in total (2338ms).
[19:03:48.587] <TB1> INFO: Test took 3163ms.
[19:03:48.588] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[19:03:48.828] <TB1> INFO: PixTestAlive::maskTest() done
[19:03:48.828] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[19:03:48.829] <TB1> INFO: ----------------------------------------------------------------------
[19:03:48.829] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[19:03:48.829] <TB1> INFO: ----------------------------------------------------------------------
[19:03:49.066] <TB1> INFO: Expecting 41600 events.
[19:03:52.514] <TB1> INFO: 41600 events read in total (2857ms).
[19:03:52.514] <TB1> INFO: Test took 3683ms.
[19:03:52.741] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[19:03:52.741] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[19:03:52.741] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[19:03:52.741] <TB1> INFO: Decoding statistics:
[19:03:52.741] <TB1> INFO: General information:
[19:03:52.741] <TB1> INFO: 16bit words read: 0
[19:03:52.741] <TB1> INFO: valid events total: 0
[19:03:52.741] <TB1> INFO: empty events: 0
[19:03:52.741] <TB1> INFO: valid events with pixels: 0
[19:03:52.741] <TB1> INFO: valid pixel hits: 0
[19:03:52.741] <TB1> INFO: Event errors: 0
[19:03:52.741] <TB1> INFO: start marker: 0
[19:03:52.741] <TB1> INFO: stop marker: 0
[19:03:52.741] <TB1> INFO: overflow: 0
[19:03:52.741] <TB1> INFO: invalid 5bit words: 0
[19:03:52.741] <TB1> INFO: invalid XOR eye diagram: 0
[19:03:52.741] <TB1> INFO: frame (failed synchr.): 0
[19:03:52.741] <TB1> INFO: idle data (no TBM trl): 0
[19:03:52.741] <TB1> INFO: no data (only TBM hdr): 0
[19:03:52.741] <TB1> INFO: TBM errors: 0
[19:03:52.741] <TB1> INFO: flawed TBM headers: 0
[19:03:52.741] <TB1> INFO: flawed TBM trailers: 0
[19:03:52.741] <TB1> INFO: event ID mismatches: 0
[19:03:52.741] <TB1> INFO: ROC errors: 0
[19:03:52.741] <TB1> INFO: missing ROC header(s): 0
[19:03:52.741] <TB1> INFO: misplaced readback start: 0
[19:03:52.741] <TB1> INFO: Pixel decoding errors: 0
[19:03:52.741] <TB1> INFO: pixel data incomplete: 0
[19:03:52.741] <TB1> INFO: pixel address: 0
[19:03:52.741] <TB1> INFO: pulse height fill bit: 0
[19:03:52.741] <TB1> INFO: buffer corruption: 0
[19:03:52.748] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C15.dat
[19:03:52.748] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[19:03:52.748] <TB1> INFO: ######################################################################
[19:03:52.748] <TB1> INFO: PixTestReadback::doTest()
[19:03:52.748] <TB1> INFO: ######################################################################
[19:03:52.748] <TB1> INFO: ----------------------------------------------------------------------
[19:03:52.748] <TB1> INFO: PixTestReadback::CalibrateVd()
[19:03:52.748] <TB1> INFO: ----------------------------------------------------------------------
[19:04:02.708] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C0.dat
[19:04:02.708] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C1.dat
[19:04:02.708] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C2.dat
[19:04:02.708] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C3.dat
[19:04:02.708] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C4.dat
[19:04:02.708] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C5.dat
[19:04:02.708] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C6.dat
[19:04:02.708] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C7.dat
[19:04:02.708] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C8.dat
[19:04:02.708] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C9.dat
[19:04:02.708] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C10.dat
[19:04:02.708] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C11.dat
[19:04:02.709] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C12.dat
[19:04:02.709] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C13.dat
[19:04:02.709] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C14.dat
[19:04:02.709] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C15.dat
[19:04:02.737] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[19:04:02.737] <TB1> INFO: ----------------------------------------------------------------------
[19:04:02.737] <TB1> INFO: PixTestReadback::CalibrateVa()
[19:04:02.737] <TB1> INFO: ----------------------------------------------------------------------
[19:04:12.626] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C0.dat
[19:04:12.627] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C1.dat
[19:04:12.627] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C2.dat
[19:04:12.627] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C3.dat
[19:04:12.627] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C4.dat
[19:04:12.627] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C5.dat
[19:04:12.627] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C6.dat
[19:04:12.627] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C7.dat
[19:04:12.627] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C8.dat
[19:04:12.627] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C9.dat
[19:04:12.627] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C10.dat
[19:04:12.627] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C11.dat
[19:04:12.627] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C12.dat
[19:04:12.627] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C13.dat
[19:04:12.628] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C14.dat
[19:04:12.628] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C15.dat
[19:04:12.655] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[19:04:12.655] <TB1> INFO: ----------------------------------------------------------------------
[19:04:12.655] <TB1> INFO: PixTestReadback::readbackVbg()
[19:04:12.655] <TB1> INFO: ----------------------------------------------------------------------
[19:04:20.293] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[19:04:20.293] <TB1> INFO: ----------------------------------------------------------------------
[19:04:20.293] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[19:04:20.293] <TB1> INFO: ----------------------------------------------------------------------
[19:04:20.293] <TB1> INFO: Vbg will be calibrated using Vd calibration
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 154.9calibrated Vbg = 1.16559 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 150.7calibrated Vbg = 1.16228 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 148.1calibrated Vbg = 1.15043 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 146.1calibrated Vbg = 1.15386 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 143.3calibrated Vbg = 1.16189 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 150.2calibrated Vbg = 1.16732 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 148calibrated Vbg = 1.16681 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 155.2calibrated Vbg = 1.16383 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 154.1calibrated Vbg = 1.15871 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 158.6calibrated Vbg = 1.16143 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 153.4calibrated Vbg = 1.14952 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 159.1calibrated Vbg = 1.15353 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 155.5calibrated Vbg = 1.15564 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152.5calibrated Vbg = 1.16246 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 158.8calibrated Vbg = 1.16522 :::*/*/*/*/
[19:04:20.293] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 159.9calibrated Vbg = 1.16128 :::*/*/*/*/
[19:04:20.295] <TB1> INFO: ----------------------------------------------------------------------
[19:04:20.295] <TB1> INFO: PixTestReadback::CalibrateIa()
[19:04:20.295] <TB1> INFO: ----------------------------------------------------------------------
[19:07:00.615] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C0.dat
[19:07:00.615] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C1.dat
[19:07:00.615] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C2.dat
[19:07:00.615] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C3.dat
[19:07:00.615] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C4.dat
[19:07:00.615] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C5.dat
[19:07:00.615] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C6.dat
[19:07:00.615] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C7.dat
[19:07:00.615] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C8.dat
[19:07:00.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C9.dat
[19:07:00.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C10.dat
[19:07:00.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C11.dat
[19:07:00.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C12.dat
[19:07:00.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C13.dat
[19:07:00.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C14.dat
[19:07:00.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C15.dat
[19:07:00.644] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[19:07:00.645] <TB1> INFO: PixTestReadback::doTest() done
[19:07:00.645] <TB1> INFO: Decoding statistics:
[19:07:00.645] <TB1> INFO: General information:
[19:07:00.645] <TB1> INFO: 16bit words read: 1536
[19:07:00.645] <TB1> INFO: valid events total: 256
[19:07:00.645] <TB1> INFO: empty events: 256
[19:07:00.645] <TB1> INFO: valid events with pixels: 0
[19:07:00.645] <TB1> INFO: valid pixel hits: 0
[19:07:00.645] <TB1> INFO: Event errors: 0
[19:07:00.645] <TB1> INFO: start marker: 0
[19:07:00.645] <TB1> INFO: stop marker: 0
[19:07:00.645] <TB1> INFO: overflow: 0
[19:07:00.645] <TB1> INFO: invalid 5bit words: 0
[19:07:00.645] <TB1> INFO: invalid XOR eye diagram: 0
[19:07:00.645] <TB1> INFO: frame (failed synchr.): 0
[19:07:00.645] <TB1> INFO: idle data (no TBM trl): 0
[19:07:00.645] <TB1> INFO: no data (only TBM hdr): 0
[19:07:00.645] <TB1> INFO: TBM errors: 0
[19:07:00.645] <TB1> INFO: flawed TBM headers: 0
[19:07:00.645] <TB1> INFO: flawed TBM trailers: 0
[19:07:00.645] <TB1> INFO: event ID mismatches: 0
[19:07:00.645] <TB1> INFO: ROC errors: 0
[19:07:00.645] <TB1> INFO: missing ROC header(s): 0
[19:07:00.645] <TB1> INFO: misplaced readback start: 0
[19:07:00.645] <TB1> INFO: Pixel decoding errors: 0
[19:07:00.645] <TB1> INFO: pixel data incomplete: 0
[19:07:00.645] <TB1> INFO: pixel address: 0
[19:07:00.645] <TB1> INFO: pulse height fill bit: 0
[19:07:00.645] <TB1> INFO: buffer corruption: 0
[19:07:00.678] <TB1> INFO: ######################################################################
[19:07:00.678] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[19:07:00.678] <TB1> INFO: ######################################################################
[19:07:00.681] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[19:07:00.691] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:07:00.691] <TB1> INFO: run 1 of 1
[19:07:00.923] <TB1> INFO: Expecting 3120000 events.
[19:07:31.508] <TB1> INFO: 670280 events read in total (29993ms).











[19:08:00.628] <TB1> INFO: 1332525 events read in total (59113ms).











[19:08:29.871] <TB1> INFO: 1991640 events read in total (88356ms).











[19:08:59.324] <TB1> INFO: 2652050 events read in total (117809ms).











[19:09:20.061] <TB1> INFO: 3120000 events read in total (138546ms).
[19:09:20.132] <TB1> INFO: Test took 139441ms.
[19:09:47.126] <TB1> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 166 seconds
[19:09:47.126] <TB1> INFO: number of dead bumps (per ROC): 0 3 1 0 0 1 1 0 0 0 0 0 0 0 1 0
[19:09:47.126] <TB1> INFO: separation cut (per ROC): 102 114 101 103 102 103 101 107 101 99 106 109 107 113 102 103
[19:09:47.126] <TB1> INFO: Decoding statistics:
[19:09:47.126] <TB1> INFO: General information:
[19:09:47.126] <TB1> INFO: 16bit words read: 0
[19:09:47.126] <TB1> INFO: valid events total: 0
[19:09:47.126] <TB1> INFO: empty events: 0
[19:09:47.126] <TB1> INFO: valid events with pixels: 0
[19:09:47.126] <TB1> INFO: valid pixel hits: 0
[19:09:47.126] <TB1> INFO: Event errors: 0
[19:09:47.126] <TB1> INFO: start marker: 0
[19:09:47.126] <TB1> INFO: stop marker: 0
[19:09:47.126] <TB1> INFO: overflow: 0
[19:09:47.126] <TB1> INFO: invalid 5bit words: 0
[19:09:47.126] <TB1> INFO: invalid XOR eye diagram: 0
[19:09:47.126] <TB1> INFO: frame (failed synchr.): 0
[19:09:47.126] <TB1> INFO: idle data (no TBM trl): 0
[19:09:47.126] <TB1> INFO: no data (only TBM hdr): 0
[19:09:47.126] <TB1> INFO: TBM errors: 0
[19:09:47.126] <TB1> INFO: flawed TBM headers: 0
[19:09:47.126] <TB1> INFO: flawed TBM trailers: 0
[19:09:47.126] <TB1> INFO: event ID mismatches: 0
[19:09:47.127] <TB1> INFO: ROC errors: 0
[19:09:47.127] <TB1> INFO: missing ROC header(s): 0
[19:09:47.127] <TB1> INFO: misplaced readback start: 0
[19:09:47.127] <TB1> INFO: Pixel decoding errors: 0
[19:09:47.127] <TB1> INFO: pixel data incomplete: 0
[19:09:47.127] <TB1> INFO: pixel address: 0
[19:09:47.127] <TB1> INFO: pulse height fill bit: 0
[19:09:47.127] <TB1> INFO: buffer corruption: 0
[19:09:47.169] <TB1> INFO: ######################################################################
[19:09:47.169] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[19:09:47.169] <TB1> INFO: ######################################################################
[19:09:47.169] <TB1> INFO: ----------------------------------------------------------------------
[19:09:47.169] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[19:09:47.169] <TB1> INFO: ----------------------------------------------------------------------
[19:09:47.169] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[19:09:47.178] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[19:09:47.179] <TB1> INFO: run 1 of 1
[19:09:47.419] <TB1> INFO: Expecting 36608000 events.
[19:10:10.667] <TB1> INFO: 685300 events read in total (22657ms).
[19:10:33.287] <TB1> INFO: 1355850 events read in total (45277ms).
[19:10:55.918] <TB1> INFO: 2027150 events read in total (67908ms).
[19:11:18.386] <TB1> INFO: 2697650 events read in total (90376ms).
[19:11:40.955] <TB1> INFO: 3367050 events read in total (112945ms).
[19:12:03.401] <TB1> INFO: 4037600 events read in total (135391ms).
[19:12:25.845] <TB1> INFO: 4706700 events read in total (157835ms).
[19:12:48.547] <TB1> INFO: 5375500 events read in total (180537ms).
[19:13:11.166] <TB1> INFO: 6043000 events read in total (203156ms).
[19:13:34.074] <TB1> INFO: 6711000 events read in total (226064ms).
[19:13:56.450] <TB1> INFO: 7379150 events read in total (248440ms).
[19:14:18.885] <TB1> INFO: 8047050 events read in total (270875ms).
[19:14:41.347] <TB1> INFO: 8715500 events read in total (293337ms).
[19:15:03.947] <TB1> INFO: 9382900 events read in total (315937ms).
[19:15:26.401] <TB1> INFO: 10049750 events read in total (338392ms).
[19:15:48.860] <TB1> INFO: 10718200 events read in total (360850ms).
[19:16:11.353] <TB1> INFO: 11385200 events read in total (383344ms).
[19:16:34.051] <TB1> INFO: 12051400 events read in total (406041ms).
[19:16:56.496] <TB1> INFO: 12717450 events read in total (428486ms).
[19:17:19.207] <TB1> INFO: 13383350 events read in total (451197ms).
[19:17:41.833] <TB1> INFO: 14050200 events read in total (473823ms).
[19:18:04.617] <TB1> INFO: 14717200 events read in total (496607ms).
[19:18:27.275] <TB1> INFO: 15383550 events read in total (519265ms).
[19:18:49.994] <TB1> INFO: 16050150 events read in total (541984ms).
[19:19:12.576] <TB1> INFO: 16716750 events read in total (564566ms).
[19:19:35.110] <TB1> INFO: 17380150 events read in total (587100ms).
[19:19:57.715] <TB1> INFO: 18045900 events read in total (609705ms).
[19:20:20.300] <TB1> INFO: 18708450 events read in total (632290ms).
[19:20:42.732] <TB1> INFO: 19373000 events read in total (654722ms).
[19:21:05.215] <TB1> INFO: 20035500 events read in total (677205ms).
[19:21:27.986] <TB1> INFO: 20699700 events read in total (699976ms).
[19:21:50.495] <TB1> INFO: 21362400 events read in total (722485ms).
[19:22:13.340] <TB1> INFO: 22023600 events read in total (745330ms).
[19:22:35.815] <TB1> INFO: 22685450 events read in total (767805ms).
[19:22:58.280] <TB1> INFO: 23347100 events read in total (790270ms).
[19:23:20.935] <TB1> INFO: 24008600 events read in total (812925ms).
[19:23:43.388] <TB1> INFO: 24671050 events read in total (835378ms).
[19:24:06.298] <TB1> INFO: 25333750 events read in total (858288ms).
[19:24:28.816] <TB1> INFO: 25994050 events read in total (880806ms).
[19:24:51.422] <TB1> INFO: 26654400 events read in total (903412ms).
[19:25:13.000] <TB1> INFO: 27316150 events read in total (925990ms).
[19:25:36.680] <TB1> INFO: 27978300 events read in total (948670ms).
[19:25:59.328] <TB1> INFO: 28637500 events read in total (971318ms).
[19:26:21.684] <TB1> INFO: 29297200 events read in total (993674ms).
[19:26:44.514] <TB1> INFO: 29958400 events read in total (1016504ms).
[19:27:06.818] <TB1> INFO: 30618850 events read in total (1038808ms).
[19:27:29.328] <TB1> INFO: 31279600 events read in total (1061318ms).
[19:27:51.944] <TB1> INFO: 31940050 events read in total (1083934ms).
[19:28:14.527] <TB1> INFO: 32599900 events read in total (1106517ms).
[19:28:37.339] <TB1> INFO: 33260000 events read in total (1129329ms).
[19:28:59.942] <TB1> INFO: 33920950 events read in total (1151932ms).
[19:29:22.308] <TB1> INFO: 34582500 events read in total (1174298ms).
[19:29:44.938] <TB1> INFO: 35244400 events read in total (1196928ms).
[19:30:07.614] <TB1> INFO: 35906400 events read in total (1219604ms).
[19:30:30.734] <TB1> INFO: 36582050 events read in total (1242724ms).
[19:30:32.007] <TB1> INFO: 36608000 events read in total (1243997ms).
[19:30:32.068] <TB1> INFO: Test took 1244889ms.
[19:30:32.590] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:30:34.612] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:30:36.644] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:30:38.543] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:30:40.569] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:30:42.611] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:30:44.450] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:30:46.262] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:30:48.318] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:30:49.912] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:30:51.870] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:30:53.795] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:30:55.755] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:30:57.622] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:30:59.433] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:31:01.242] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[19:31:03.098] <TB1> INFO: PixTestScurves::scurves() done
[19:31:03.098] <TB1> INFO: Vcal mean: 116.99 119.26 116.06 117.69 113.99 111.18 114.73 114.74 120.53 111.97 117.46 119.83 125.12 119.22 110.18 116.80
[19:31:03.098] <TB1> INFO: Vcal RMS: 5.10 5.60 5.27 5.52 4.62 4.65 4.92 4.65 8.69 5.28 5.99 5.47 5.33 5.55 4.77 5.17
[19:31:03.098] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1275 seconds
[19:31:03.098] <TB1> INFO: Decoding statistics:
[19:31:03.098] <TB1> INFO: General information:
[19:31:03.098] <TB1> INFO: 16bit words read: 0
[19:31:03.098] <TB1> INFO: valid events total: 0
[19:31:03.098] <TB1> INFO: empty events: 0
[19:31:03.098] <TB1> INFO: valid events with pixels: 0
[19:31:03.098] <TB1> INFO: valid pixel hits: 0
[19:31:03.098] <TB1> INFO: Event errors: 0
[19:31:03.098] <TB1> INFO: start marker: 0
[19:31:03.098] <TB1> INFO: stop marker: 0
[19:31:03.098] <TB1> INFO: overflow: 0
[19:31:03.098] <TB1> INFO: invalid 5bit words: 0
[19:31:03.098] <TB1> INFO: invalid XOR eye diagram: 0
[19:31:03.098] <TB1> INFO: frame (failed synchr.): 0
[19:31:03.098] <TB1> INFO: idle data (no TBM trl): 0
[19:31:03.098] <TB1> INFO: no data (only TBM hdr): 0
[19:31:03.098] <TB1> INFO: TBM errors: 0
[19:31:03.098] <TB1> INFO: flawed TBM headers: 0
[19:31:03.098] <TB1> INFO: flawed TBM trailers: 0
[19:31:03.098] <TB1> INFO: event ID mismatches: 0
[19:31:03.098] <TB1> INFO: ROC errors: 0
[19:31:03.098] <TB1> INFO: missing ROC header(s): 0
[19:31:03.098] <TB1> INFO: misplaced readback start: 0
[19:31:03.098] <TB1> INFO: Pixel decoding errors: 0
[19:31:03.098] <TB1> INFO: pixel data incomplete: 0
[19:31:03.098] <TB1> INFO: pixel address: 0
[19:31:03.098] <TB1> INFO: pulse height fill bit: 0
[19:31:03.098] <TB1> INFO: buffer corruption: 0
[19:31:03.164] <TB1> INFO: ######################################################################
[19:31:03.164] <TB1> INFO: PixTestTrim::doTest()
[19:31:03.164] <TB1> INFO: ######################################################################
[19:31:03.165] <TB1> INFO: ----------------------------------------------------------------------
[19:31:03.165] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[19:31:03.165] <TB1> INFO: ----------------------------------------------------------------------
[19:31:03.206] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[19:31:03.206] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[19:31:03.215] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:31:03.215] <TB1> INFO: run 1 of 1
[19:31:03.470] <TB1> INFO: Expecting 5025280 events.
[19:31:33.853] <TB1> INFO: 822576 events read in total (29788ms).
[19:32:03.430] <TB1> INFO: 1642208 events read in total (59365ms).
[19:32:33.166] <TB1> INFO: 2460552 events read in total (89102ms).
[19:33:02.994] <TB1> INFO: 3274944 events read in total (118929ms).
[19:33:32.602] <TB1> INFO: 4085928 events read in total (148537ms).
[19:34:02.595] <TB1> INFO: 4895136 events read in total (178530ms).
[19:34:07.763] <TB1> INFO: 5025280 events read in total (183698ms).
[19:34:07.814] <TB1> INFO: Test took 184599ms.
[19:34:26.813] <TB1> INFO: ROC 0 VthrComp = 123
[19:34:26.813] <TB1> INFO: ROC 1 VthrComp = 129
[19:34:26.813] <TB1> INFO: ROC 2 VthrComp = 113
[19:34:26.813] <TB1> INFO: ROC 3 VthrComp = 124
[19:34:26.813] <TB1> INFO: ROC 4 VthrComp = 116
[19:34:26.813] <TB1> INFO: ROC 5 VthrComp = 117
[19:34:26.814] <TB1> INFO: ROC 6 VthrComp = 122
[19:34:26.815] <TB1> INFO: ROC 7 VthrComp = 120
[19:34:26.815] <TB1> INFO: ROC 8 VthrComp = 117
[19:34:26.815] <TB1> INFO: ROC 9 VthrComp = 112
[19:34:26.816] <TB1> INFO: ROC 10 VthrComp = 121
[19:34:26.816] <TB1> INFO: ROC 11 VthrComp = 129
[19:34:26.816] <TB1> INFO: ROC 12 VthrComp = 128
[19:34:26.816] <TB1> INFO: ROC 13 VthrComp = 129
[19:34:26.816] <TB1> INFO: ROC 14 VthrComp = 112
[19:34:26.816] <TB1> INFO: ROC 15 VthrComp = 122
[19:34:27.052] <TB1> INFO: Expecting 41600 events.
[19:34:30.522] <TB1> INFO: 41600 events read in total (2879ms).
[19:34:30.523] <TB1> INFO: Test took 3705ms.
[19:34:30.532] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[19:34:30.532] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[19:34:30.540] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:34:30.540] <TB1> INFO: run 1 of 1
[19:34:30.818] <TB1> INFO: Expecting 5025280 events.
[19:34:57.071] <TB1> INFO: 590824 events read in total (25661ms).
[19:35:22.623] <TB1> INFO: 1180624 events read in total (51213ms).
[19:35:48.454] <TB1> INFO: 1770128 events read in total (77044ms).
[19:36:14.108] <TB1> INFO: 2358176 events read in total (102698ms).
[19:36:39.812] <TB1> INFO: 2944368 events read in total (128402ms).
[19:37:05.125] <TB1> INFO: 3529704 events read in total (153715ms).
[19:37:30.935] <TB1> INFO: 4113728 events read in total (179525ms).
[19:37:56.414] <TB1> INFO: 4696672 events read in total (205004ms).
[19:38:11.634] <TB1> INFO: 5025280 events read in total (220224ms).
[19:38:11.704] <TB1> INFO: Test took 221163ms.
[19:38:38.322] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 57.691 for pixel 9/56 mean/min/max = 45.0061/32.2155/57.7967
[19:38:38.323] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 57.8598 for pixel 3/2 mean/min/max = 45.0338/32.1381/57.9294
[19:38:38.323] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 59.6969 for pixel 2/0 mean/min/max = 46.7204/33.6983/59.7425
[19:38:38.323] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 58.2124 for pixel 0/79 mean/min/max = 45.3522/32.1149/58.5896
[19:38:38.324] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 57.974 for pixel 16/0 mean/min/max = 45.9415/33.8522/58.0308
[19:38:38.324] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 57.5441 for pixel 51/2 mean/min/max = 44.8565/32.1443/57.5687
[19:38:38.324] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 58.2608 for pixel 16/4 mean/min/max = 45.4494/32.6259/58.2729
[19:38:38.325] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 57.2915 for pixel 7/79 mean/min/max = 45.4268/33.5593/57.2943
[19:38:38.325] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 67.2481 for pixel 18/58 mean/min/max = 48.6367/29.7638/67.5095
[19:38:38.325] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 58.2644 for pixel 7/65 mean/min/max = 45.625/32.9416/58.3084
[19:38:38.326] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 59.1957 for pixel 35/44 mean/min/max = 46.5084/33.4218/59.595
[19:38:38.326] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 56.7492 for pixel 33/2 mean/min/max = 44.4642/32.0866/56.8418
[19:38:38.327] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 59.3831 for pixel 33/10 mean/min/max = 45.8258/32.1622/59.4893
[19:38:38.327] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 58.2378 for pixel 0/28 mean/min/max = 45.4408/32.6271/58.2545
[19:38:38.327] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 58.2666 for pixel 34/7 mean/min/max = 46.1187/33.6859/58.5514
[19:38:38.328] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 58.7369 for pixel 12/14 mean/min/max = 45.8544/32.9333/58.7755
[19:38:38.328] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:38:38.417] <TB1> INFO: Expecting 411648 events.
[19:38:47.766] <TB1> INFO: 411648 events read in total (8758ms).
[19:38:47.774] <TB1> INFO: Expecting 411648 events.
[19:38:56.907] <TB1> INFO: 411648 events read in total (8730ms).
[19:38:56.917] <TB1> INFO: Expecting 411648 events.
[19:39:06.024] <TB1> INFO: 411648 events read in total (8704ms).
[19:39:06.036] <TB1> INFO: Expecting 411648 events.
[19:39:15.128] <TB1> INFO: 411648 events read in total (8689ms).
[19:39:15.146] <TB1> INFO: Expecting 411648 events.
[19:39:24.237] <TB1> INFO: 411648 events read in total (8688ms).
[19:39:24.261] <TB1> INFO: Expecting 411648 events.
[19:39:33.365] <TB1> INFO: 411648 events read in total (8701ms).
[19:39:33.390] <TB1> INFO: Expecting 411648 events.
[19:39:42.496] <TB1> INFO: 411648 events read in total (8703ms).
[19:39:42.525] <TB1> INFO: Expecting 411648 events.
[19:39:51.645] <TB1> INFO: 411648 events read in total (8718ms).
[19:39:51.670] <TB1> INFO: Expecting 411648 events.
[19:40:00.832] <TB1> INFO: 411648 events read in total (8759ms).
[19:40:00.861] <TB1> INFO: Expecting 411648 events.
[19:40:09.926] <TB1> INFO: 411648 events read in total (8662ms).
[19:40:09.957] <TB1> INFO: Expecting 411648 events.
[19:40:19.121] <TB1> INFO: 411648 events read in total (8761ms).
[19:40:19.156] <TB1> INFO: Expecting 411648 events.
[19:40:28.261] <TB1> INFO: 411648 events read in total (8702ms).
[19:40:28.308] <TB1> INFO: Expecting 411648 events.
[19:40:37.550] <TB1> INFO: 411648 events read in total (8826ms).
[19:40:37.602] <TB1> INFO: Expecting 411648 events.
[19:40:46.675] <TB1> INFO: 411648 events read in total (8669ms).
[19:40:46.717] <TB1> INFO: Expecting 411648 events.
[19:40:55.841] <TB1> INFO: 411648 events read in total (8721ms).
[19:40:55.903] <TB1> INFO: Expecting 411648 events.
[19:41:04.995] <TB1> INFO: 411648 events read in total (8688ms).
[19:41:05.048] <TB1> INFO: Test took 146720ms.
[19:41:05.795] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[19:41:05.805] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:41:05.805] <TB1> INFO: run 1 of 1
[19:41:06.037] <TB1> INFO: Expecting 5025280 events.
[19:41:32.341] <TB1> INFO: 587584 events read in total (25712ms).
[19:41:58.177] <TB1> INFO: 1172248 events read in total (51548ms).
[19:42:23.837] <TB1> INFO: 1756144 events read in total (77208ms).
[19:42:49.697] <TB1> INFO: 2340136 events read in total (103068ms).
[19:43:15.327] <TB1> INFO: 2924160 events read in total (128699ms).
[19:43:41.161] <TB1> INFO: 3507672 events read in total (154532ms).
[19:44:06.994] <TB1> INFO: 4092200 events read in total (180365ms).
[19:44:32.793] <TB1> INFO: 4676232 events read in total (206164ms).
[19:44:48.625] <TB1> INFO: 5025280 events read in total (221996ms).
[19:44:48.737] <TB1> INFO: Test took 222933ms.
[19:45:13.153] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 2.651909 .. 144.937924
[19:45:13.390] <TB1> INFO: Expecting 208000 events.
[19:45:22.954] <TB1> INFO: 208000 events read in total (8972ms).
[19:45:22.955] <TB1> INFO: Test took 9801ms.
[19:45:23.013] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 154 (-1/-1) hits flags = 528 (plus default)
[19:45:23.025] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:45:23.025] <TB1> INFO: run 1 of 1
[19:45:23.302] <TB1> INFO: Expecting 5091840 events.
[19:45:49.593] <TB1> INFO: 584088 events read in total (25699ms).
[19:46:14.898] <TB1> INFO: 1168288 events read in total (51004ms).
[19:46:40.947] <TB1> INFO: 1752192 events read in total (77053ms).
[19:47:06.182] <TB1> INFO: 2336224 events read in total (102288ms).
[19:47:31.393] <TB1> INFO: 2919904 events read in total (127499ms).
[19:47:56.840] <TB1> INFO: 3502704 events read in total (152946ms).
[19:48:22.323] <TB1> INFO: 4085232 events read in total (178429ms).
[19:48:47.956] <TB1> INFO: 4666560 events read in total (204062ms).
[19:49:06.780] <TB1> INFO: 5091840 events read in total (222886ms).
[19:49:06.848] <TB1> INFO: Test took 223823ms.
[19:49:34.420] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.412583 .. 43.638436
[19:49:34.693] <TB1> INFO: Expecting 208000 events.
[19:49:44.273] <TB1> INFO: 208000 events read in total (8989ms).
[19:49:44.274] <TB1> INFO: Test took 9853ms.
[19:49:44.323] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 53 (-1/-1) hits flags = 528 (plus default)
[19:49:44.331] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:49:44.331] <TB1> INFO: run 1 of 1
[19:49:44.610] <TB1> INFO: Expecting 1231360 events.
[19:50:12.525] <TB1> INFO: 668984 events read in total (27324ms).
[19:50:36.383] <TB1> INFO: 1231360 events read in total (51183ms).
[19:50:36.421] <TB1> INFO: Test took 52090ms.
[19:50:49.868] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 26.680814 .. 48.045450
[19:50:50.138] <TB1> INFO: Expecting 208000 events.
[19:50:59.699] <TB1> INFO: 208000 events read in total (8970ms).
[19:50:59.699] <TB1> INFO: Test took 9830ms.
[19:50:59.755] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 58 (-1/-1) hits flags = 528 (plus default)
[19:50:59.765] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:50:59.765] <TB1> INFO: run 1 of 1
[19:51:00.043] <TB1> INFO: Expecting 1431040 events.
[19:51:27.737] <TB1> INFO: 653160 events read in total (27102ms).
[19:51:54.921] <TB1> INFO: 1305104 events read in total (54286ms).
[19:52:00.720] <TB1> INFO: 1431040 events read in total (60085ms).
[19:52:00.748] <TB1> INFO: Test took 60984ms.
[19:52:15.276] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 26.543148 .. 51.229204
[19:52:15.510] <TB1> INFO: Expecting 208000 events.
[19:52:25.399] <TB1> INFO: 208000 events read in total (9297ms).
[19:52:25.400] <TB1> INFO: Test took 10123ms.
[19:52:25.451] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 61 (-1/-1) hits flags = 528 (plus default)
[19:52:25.462] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:52:25.462] <TB1> INFO: run 1 of 1
[19:52:25.740] <TB1> INFO: Expecting 1530880 events.
[19:52:53.136] <TB1> INFO: 643208 events read in total (26804ms).
[19:53:20.084] <TB1> INFO: 1286200 events read in total (53753ms).
[19:53:31.199] <TB1> INFO: 1530880 events read in total (64867ms).
[19:53:31.228] <TB1> INFO: Test took 65767ms.
[19:53:45.887] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[19:53:45.887] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[19:53:45.896] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[19:53:45.896] <TB1> INFO: run 1 of 1
[19:53:46.134] <TB1> INFO: Expecting 1364480 events.
[19:54:14.280] <TB1> INFO: 668632 events read in total (27554ms).
[19:54:42.037] <TB1> INFO: 1336088 events read in total (55311ms).
[19:54:43.715] <TB1> INFO: 1364480 events read in total (56990ms).
[19:54:43.738] <TB1> INFO: Test took 57842ms.
[19:54:57.621] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C0.dat
[19:54:57.621] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C1.dat
[19:54:57.621] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C2.dat
[19:54:57.621] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C3.dat
[19:54:57.621] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C4.dat
[19:54:57.621] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C5.dat
[19:54:57.621] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C6.dat
[19:54:57.622] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C7.dat
[19:54:57.622] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C8.dat
[19:54:57.622] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C9.dat
[19:54:57.622] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C10.dat
[19:54:57.622] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C11.dat
[19:54:57.622] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C12.dat
[19:54:57.622] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C13.dat
[19:54:57.622] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C14.dat
[19:54:57.622] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C15.dat
[19:54:57.622] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C0.dat
[19:54:57.629] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C1.dat
[19:54:57.634] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C2.dat
[19:54:57.640] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C3.dat
[19:54:57.646] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C4.dat
[19:54:57.652] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C5.dat
[19:54:57.659] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C6.dat
[19:54:57.666] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C7.dat
[19:54:57.671] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C8.dat
[19:54:57.676] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C9.dat
[19:54:57.682] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C10.dat
[19:54:57.688] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C11.dat
[19:54:57.693] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C12.dat
[19:54:57.699] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C13.dat
[19:54:57.704] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C14.dat
[19:54:57.710] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C15.dat
[19:54:57.715] <TB1> INFO: PixTestTrim::trimTest() done
[19:54:57.715] <TB1> INFO: vtrim: 142 125 135 118 137 115 137 133 162 118 148 133 133 115 137 123
[19:54:57.715] <TB1> INFO: vthrcomp: 123 129 113 124 116 117 122 120 117 112 121 129 128 129 112 122
[19:54:57.715] <TB1> INFO: vcal mean: 34.98 34.93 35.16 35.00 35.01 34.97 34.98 34.96 35.64 35.08 35.24 34.98 34.98 34.92 35.15 35.04
[19:54:57.715] <TB1> INFO: vcal RMS: 1.06 0.98 1.31 1.01 1.16 0.98 1.00 0.94 2.02 1.07 1.31 1.14 1.09 0.97 1.27 1.14
[19:54:57.715] <TB1> INFO: bits mean: 10.25 9.88 9.85 9.52 9.99 9.66 10.23 9.84 10.47 9.72 10.11 10.28 9.69 9.46 10.21 9.65
[19:54:57.715] <TB1> INFO: bits RMS: 2.40 2.62 2.36 2.74 2.31 2.67 2.36 2.39 2.43 2.52 2.25 2.41 2.65 2.67 2.23 2.61
[19:54:57.722] <TB1> INFO: ----------------------------------------------------------------------
[19:54:57.722] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[19:54:57.722] <TB1> INFO: ----------------------------------------------------------------------
[19:54:57.725] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[19:54:57.734] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:54:57.734] <TB1> INFO: run 1 of 1
[19:54:57.999] <TB1> INFO: Expecting 4160000 events.
[19:55:29.806] <TB1> INFO: 756970 events read in total (31216ms).
[19:56:01.162] <TB1> INFO: 1508615 events read in total (62572ms).
[19:56:32.645] <TB1> INFO: 2256990 events read in total (94055ms).
[19:57:04.168] <TB1> INFO: 3001065 events read in total (125578ms).
[19:57:35.619] <TB1> INFO: 3742750 events read in total (157029ms).
[19:57:53.384] <TB1> INFO: 4160000 events read in total (174794ms).
[19:57:53.439] <TB1> INFO: Test took 175705ms.
[19:58:23.964] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[19:58:23.973] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:58:23.973] <TB1> INFO: run 1 of 1
[19:58:24.206] <TB1> INFO: Expecting 4243200 events.
[19:58:55.793] <TB1> INFO: 727730 events read in total (30996ms).
[19:59:26.265] <TB1> INFO: 1450750 events read in total (61468ms).
[19:59:57.057] <TB1> INFO: 2171320 events read in total (92260ms).
[20:00:27.625] <TB1> INFO: 2887380 events read in total (122828ms).
[20:00:57.927] <TB1> INFO: 3601515 events read in total (153130ms).
[20:01:25.624] <TB1> INFO: 4243200 events read in total (180827ms).
[20:01:25.678] <TB1> INFO: Test took 181705ms.
[20:01:54.790] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 190 (-1/-1) hits flags = 528 (plus default)
[20:01:54.799] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[20:01:54.799] <TB1> INFO: run 1 of 1
[20:01:55.033] <TB1> INFO: Expecting 3972800 events.
[20:02:26.962] <TB1> INFO: 746680 events read in total (31337ms).
[20:02:57.915] <TB1> INFO: 1488035 events read in total (62290ms).
[20:03:29.237] <TB1> INFO: 2225750 events read in total (93612ms).
[20:04:00.370] <TB1> INFO: 2958820 events read in total (124745ms).
[20:04:31.397] <TB1> INFO: 3689985 events read in total (155772ms).
[20:04:43.737] <TB1> INFO: 3972800 events read in total (168112ms).
[20:04:43.784] <TB1> INFO: Test took 168984ms.
[20:05:11.865] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 189 (-1/-1) hits flags = 528 (plus default)
[20:05:11.876] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[20:05:11.876] <TB1> INFO: run 1 of 1
[20:05:12.152] <TB1> INFO: Expecting 3952000 events.
[20:05:43.885] <TB1> INFO: 748485 events read in total (31142ms).
[20:06:15.083] <TB1> INFO: 1491670 events read in total (62340ms).
[20:06:46.382] <TB1> INFO: 2230615 events read in total (93639ms).
[20:07:17.733] <TB1> INFO: 2965505 events read in total (124990ms).
[20:07:48.683] <TB1> INFO: 3698340 events read in total (155940ms).
[20:07:59.580] <TB1> INFO: 3952000 events read in total (166837ms).
[20:07:59.626] <TB1> INFO: Test took 167750ms.
[20:08:27.786] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 189 (-1/-1) hits flags = 528 (plus default)
[20:08:27.799] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[20:08:27.799] <TB1> INFO: run 1 of 1
[20:08:28.092] <TB1> INFO: Expecting 3952000 events.
[20:09:00.056] <TB1> INFO: 748575 events read in total (31372ms).
[20:09:31.301] <TB1> INFO: 1491980 events read in total (62617ms).
[20:10:02.451] <TB1> INFO: 2230850 events read in total (93767ms).
[20:10:33.226] <TB1> INFO: 2965720 events read in total (124542ms).
[20:11:04.114] <TB1> INFO: 3698685 events read in total (155430ms).
[20:11:15.257] <TB1> INFO: 3952000 events read in total (166573ms).
[20:11:15.302] <TB1> INFO: Test took 167502ms.
[20:11:41.974] <TB1> INFO: PixTestTrim::trimBitTest() done
[20:11:41.975] <TB1> INFO: PixTestTrim::doTest() done, duration: 2438 seconds
[20:11:41.975] <TB1> INFO: Decoding statistics:
[20:11:41.975] <TB1> INFO: General information:
[20:11:41.975] <TB1> INFO: 16bit words read: 0
[20:11:41.975] <TB1> INFO: valid events total: 0
[20:11:41.975] <TB1> INFO: empty events: 0
[20:11:41.975] <TB1> INFO: valid events with pixels: 0
[20:11:41.975] <TB1> INFO: valid pixel hits: 0
[20:11:41.976] <TB1> INFO: Event errors: 0
[20:11:41.976] <TB1> INFO: start marker: 0
[20:11:41.976] <TB1> INFO: stop marker: 0
[20:11:41.976] <TB1> INFO: overflow: 0
[20:11:41.976] <TB1> INFO: invalid 5bit words: 0
[20:11:41.976] <TB1> INFO: invalid XOR eye diagram: 0
[20:11:41.976] <TB1> INFO: frame (failed synchr.): 0
[20:11:41.976] <TB1> INFO: idle data (no TBM trl): 0
[20:11:41.976] <TB1> INFO: no data (only TBM hdr): 0
[20:11:41.976] <TB1> INFO: TBM errors: 0
[20:11:41.976] <TB1> INFO: flawed TBM headers: 0
[20:11:41.976] <TB1> INFO: flawed TBM trailers: 0
[20:11:41.976] <TB1> INFO: event ID mismatches: 0
[20:11:41.976] <TB1> INFO: ROC errors: 0
[20:11:41.976] <TB1> INFO: missing ROC header(s): 0
[20:11:41.976] <TB1> INFO: misplaced readback start: 0
[20:11:41.976] <TB1> INFO: Pixel decoding errors: 0
[20:11:41.976] <TB1> INFO: pixel data incomplete: 0
[20:11:41.976] <TB1> INFO: pixel address: 0
[20:11:41.976] <TB1> INFO: pulse height fill bit: 0
[20:11:41.976] <TB1> INFO: buffer corruption: 0
[20:11:42.691] <TB1> INFO: ######################################################################
[20:11:42.691] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[20:11:42.691] <TB1> INFO: ######################################################################
[20:11:42.977] <TB1> INFO: Expecting 41600 events.
[20:11:46.513] <TB1> INFO: 41600 events read in total (2944ms).
[20:11:46.514] <TB1> INFO: Test took 3822ms.
[20:11:46.999] <TB1> INFO: Expecting 41600 events.
[20:11:50.516] <TB1> INFO: 41600 events read in total (2926ms).
[20:11:50.517] <TB1> INFO: Test took 3800ms.
[20:11:50.805] <TB1> INFO: Expecting 41600 events.
[20:11:54.444] <TB1> INFO: 41600 events read in total (3047ms).
[20:11:54.445] <TB1> INFO: Test took 3904ms.
[20:11:54.735] <TB1> INFO: Expecting 41600 events.
[20:11:58.331] <TB1> INFO: 41600 events read in total (3005ms).
[20:11:58.331] <TB1> INFO: Test took 3861ms.
[20:11:58.619] <TB1> INFO: Expecting 41600 events.
[20:12:02.180] <TB1> INFO: 41600 events read in total (2969ms).
[20:12:02.181] <TB1> INFO: Test took 3826ms.
[20:12:02.469] <TB1> INFO: Expecting 41600 events.
[20:12:06.076] <TB1> INFO: 41600 events read in total (3015ms).
[20:12:06.077] <TB1> INFO: Test took 3872ms.
[20:12:06.365] <TB1> INFO: Expecting 41600 events.
[20:12:09.889] <TB1> INFO: 41600 events read in total (2932ms).
[20:12:09.890] <TB1> INFO: Test took 3789ms.
[20:12:10.178] <TB1> INFO: Expecting 41600 events.
[20:12:13.770] <TB1> INFO: 41600 events read in total (3000ms).
[20:12:13.771] <TB1> INFO: Test took 3857ms.
[20:12:14.061] <TB1> INFO: Expecting 41600 events.
[20:12:17.557] <TB1> INFO: 41600 events read in total (2904ms).
[20:12:17.558] <TB1> INFO: Test took 3761ms.
[20:12:17.848] <TB1> INFO: Expecting 41600 events.
[20:12:21.382] <TB1> INFO: 41600 events read in total (2942ms).
[20:12:21.383] <TB1> INFO: Test took 3799ms.
[20:12:21.671] <TB1> INFO: Expecting 41600 events.
[20:12:25.201] <TB1> INFO: 41600 events read in total (2938ms).
[20:12:25.201] <TB1> INFO: Test took 3794ms.
[20:12:25.489] <TB1> INFO: Expecting 41600 events.
[20:12:28.970] <TB1> INFO: 41600 events read in total (2889ms).
[20:12:28.971] <TB1> INFO: Test took 3746ms.
[20:12:29.259] <TB1> INFO: Expecting 41600 events.
[20:12:32.801] <TB1> INFO: 41600 events read in total (2950ms).
[20:12:32.802] <TB1> INFO: Test took 3808ms.
[20:12:33.103] <TB1> INFO: Expecting 41600 events.
[20:12:36.639] <TB1> INFO: 41600 events read in total (2945ms).
[20:12:36.639] <TB1> INFO: Test took 3814ms.
[20:12:36.939] <TB1> INFO: Expecting 41600 events.
[20:12:40.403] <TB1> INFO: 41600 events read in total (2873ms).
[20:12:40.404] <TB1> INFO: Test took 3741ms.
[20:12:40.708] <TB1> INFO: Expecting 41600 events.
[20:12:44.279] <TB1> INFO: 41600 events read in total (2979ms).
[20:12:44.280] <TB1> INFO: Test took 3850ms.
[20:12:44.571] <TB1> INFO: Expecting 41600 events.
[20:12:48.072] <TB1> INFO: 41600 events read in total (2909ms).
[20:12:48.073] <TB1> INFO: Test took 3767ms.
[20:12:48.361] <TB1> INFO: Expecting 41600 events.
[20:12:51.919] <TB1> INFO: 41600 events read in total (2967ms).
[20:12:51.920] <TB1> INFO: Test took 3824ms.
[20:12:52.224] <TB1> INFO: Expecting 41600 events.
[20:12:55.772] <TB1> INFO: 41600 events read in total (2956ms).
[20:12:55.772] <TB1> INFO: Test took 3826ms.
[20:12:56.067] <TB1> INFO: Expecting 41600 events.
[20:12:59.655] <TB1> INFO: 41600 events read in total (2996ms).
[20:12:59.656] <TB1> INFO: Test took 3860ms.
[20:12:59.945] <TB1> INFO: Expecting 41600 events.
[20:13:03.430] <TB1> INFO: 41600 events read in total (2893ms).
[20:13:03.431] <TB1> INFO: Test took 3752ms.
[20:13:03.719] <TB1> INFO: Expecting 41600 events.
[20:13:07.238] <TB1> INFO: 41600 events read in total (2927ms).
[20:13:07.239] <TB1> INFO: Test took 3785ms.
[20:13:07.533] <TB1> INFO: Expecting 41600 events.
[20:13:11.013] <TB1> INFO: 41600 events read in total (2889ms).
[20:13:11.014] <TB1> INFO: Test took 3752ms.
[20:13:11.302] <TB1> INFO: Expecting 41600 events.
[20:13:14.766] <TB1> INFO: 41600 events read in total (2872ms).
[20:13:14.766] <TB1> INFO: Test took 3729ms.
[20:13:15.054] <TB1> INFO: Expecting 41600 events.
[20:13:18.676] <TB1> INFO: 41600 events read in total (3030ms).
[20:13:18.676] <TB1> INFO: Test took 3886ms.
[20:13:18.965] <TB1> INFO: Expecting 41600 events.
[20:13:22.542] <TB1> INFO: 41600 events read in total (2986ms).
[20:13:22.543] <TB1> INFO: Test took 3843ms.
[20:13:22.834] <TB1> INFO: Expecting 41600 events.
[20:13:26.449] <TB1> INFO: 41600 events read in total (3023ms).
[20:13:26.449] <TB1> INFO: Test took 3880ms.
[20:13:26.750] <TB1> INFO: Expecting 41600 events.
[20:13:30.279] <TB1> INFO: 41600 events read in total (2937ms).
[20:13:30.279] <TB1> INFO: Test took 3805ms.
[20:13:30.568] <TB1> INFO: Expecting 2560 events.
[20:13:31.452] <TB1> INFO: 2560 events read in total (292ms).
[20:13:31.452] <TB1> INFO: Test took 1161ms.
[20:13:31.764] <TB1> INFO: Expecting 2560 events.
[20:13:32.652] <TB1> INFO: 2560 events read in total (296ms).
[20:13:32.652] <TB1> INFO: Test took 1200ms.
[20:13:32.960] <TB1> INFO: Expecting 2560 events.
[20:13:33.841] <TB1> INFO: 2560 events read in total (290ms).
[20:13:33.841] <TB1> INFO: Test took 1189ms.
[20:13:34.149] <TB1> INFO: Expecting 2560 events.
[20:13:35.032] <TB1> INFO: 2560 events read in total (291ms).
[20:13:35.032] <TB1> INFO: Test took 1190ms.
[20:13:35.340] <TB1> INFO: Expecting 2560 events.
[20:13:36.220] <TB1> INFO: 2560 events read in total (288ms).
[20:13:36.221] <TB1> INFO: Test took 1188ms.
[20:13:36.528] <TB1> INFO: Expecting 2560 events.
[20:13:37.408] <TB1> INFO: 2560 events read in total (288ms).
[20:13:37.408] <TB1> INFO: Test took 1187ms.
[20:13:37.716] <TB1> INFO: Expecting 2560 events.
[20:13:38.597] <TB1> INFO: 2560 events read in total (290ms).
[20:13:38.597] <TB1> INFO: Test took 1189ms.
[20:13:38.905] <TB1> INFO: Expecting 2560 events.
[20:13:39.785] <TB1> INFO: 2560 events read in total (289ms).
[20:13:39.786] <TB1> INFO: Test took 1189ms.
[20:13:40.093] <TB1> INFO: Expecting 2560 events.
[20:13:40.972] <TB1> INFO: 2560 events read in total (287ms).
[20:13:40.973] <TB1> INFO: Test took 1187ms.
[20:13:41.281] <TB1> INFO: Expecting 2560 events.
[20:13:42.160] <TB1> INFO: 2560 events read in total (288ms).
[20:13:42.160] <TB1> INFO: Test took 1187ms.
[20:13:42.468] <TB1> INFO: Expecting 2560 events.
[20:13:43.350] <TB1> INFO: 2560 events read in total (290ms).
[20:13:43.350] <TB1> INFO: Test took 1189ms.
[20:13:43.659] <TB1> INFO: Expecting 2560 events.
[20:13:44.540] <TB1> INFO: 2560 events read in total (290ms).
[20:13:44.540] <TB1> INFO: Test took 1189ms.
[20:13:44.849] <TB1> INFO: Expecting 2560 events.
[20:13:45.735] <TB1> INFO: 2560 events read in total (295ms).
[20:13:45.735] <TB1> INFO: Test took 1194ms.
[20:13:46.043] <TB1> INFO: Expecting 2560 events.
[20:13:46.926] <TB1> INFO: 2560 events read in total (291ms).
[20:13:46.926] <TB1> INFO: Test took 1190ms.
[20:13:47.234] <TB1> INFO: Expecting 2560 events.
[20:13:48.117] <TB1> INFO: 2560 events read in total (292ms).
[20:13:48.118] <TB1> INFO: Test took 1192ms.
[20:13:48.426] <TB1> INFO: Expecting 2560 events.
[20:13:49.309] <TB1> INFO: 2560 events read in total (292ms).
[20:13:49.309] <TB1> INFO: Test took 1190ms.
[20:13:49.312] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:13:49.618] <TB1> INFO: Expecting 655360 events.
[20:14:04.076] <TB1> INFO: 655360 events read in total (13867ms).
[20:14:04.087] <TB1> INFO: Expecting 655360 events.
[20:14:18.278] <TB1> INFO: 655360 events read in total (13788ms).
[20:14:18.298] <TB1> INFO: Expecting 655360 events.
[20:14:32.380] <TB1> INFO: 655360 events read in total (13679ms).
[20:14:32.408] <TB1> INFO: Expecting 655360 events.
[20:14:46.577] <TB1> INFO: 655360 events read in total (13767ms).
[20:14:46.600] <TB1> INFO: Expecting 655360 events.
[20:15:00.786] <TB1> INFO: 655360 events read in total (13783ms).
[20:15:00.824] <TB1> INFO: Expecting 655360 events.
[20:15:15.015] <TB1> INFO: 655360 events read in total (13788ms).
[20:15:15.046] <TB1> INFO: Expecting 655360 events.
[20:15:29.164] <TB1> INFO: 655360 events read in total (13715ms).
[20:15:29.208] <TB1> INFO: Expecting 655360 events.
[20:15:43.372] <TB1> INFO: 655360 events read in total (13761ms).
[20:15:43.424] <TB1> INFO: Expecting 655360 events.
[20:15:57.557] <TB1> INFO: 655360 events read in total (13731ms).
[20:15:57.601] <TB1> INFO: Expecting 655360 events.
[20:16:11.652] <TB1> INFO: 655360 events read in total (13648ms).
[20:16:11.699] <TB1> INFO: Expecting 655360 events.
[20:16:25.835] <TB1> INFO: 655360 events read in total (13733ms).
[20:16:25.891] <TB1> INFO: Expecting 655360 events.
[20:16:40.051] <TB1> INFO: 655360 events read in total (13757ms).
[20:16:40.110] <TB1> INFO: Expecting 655360 events.
[20:16:54.282] <TB1> INFO: 655360 events read in total (13769ms).
[20:16:54.344] <TB1> INFO: Expecting 655360 events.
[20:17:08.491] <TB1> INFO: 655360 events read in total (13744ms).
[20:17:08.579] <TB1> INFO: Expecting 655360 events.
[20:17:22.693] <TB1> INFO: 655360 events read in total (13711ms).
[20:17:22.779] <TB1> INFO: Expecting 655360 events.
[20:17:36.969] <TB1> INFO: 655360 events read in total (13787ms).
[20:17:37.046] <TB1> INFO: Test took 227735ms.
[20:17:37.125] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:17:37.390] <TB1> INFO: Expecting 655360 events.
[20:17:51.585] <TB1> INFO: 655360 events read in total (13604ms).
[20:17:51.596] <TB1> INFO: Expecting 655360 events.
[20:18:05.682] <TB1> INFO: 655360 events read in total (13684ms).
[20:18:05.701] <TB1> INFO: Expecting 655360 events.
[20:18:19.513] <TB1> INFO: 655360 events read in total (13410ms).
[20:18:19.538] <TB1> INFO: Expecting 655360 events.
[20:18:33.780] <TB1> INFO: 655360 events read in total (13839ms).
[20:18:33.810] <TB1> INFO: Expecting 655360 events.
[20:18:47.738] <TB1> INFO: 655360 events read in total (13525ms).
[20:18:47.767] <TB1> INFO: Expecting 655360 events.
[20:19:01.920] <TB1> INFO: 655360 events read in total (13750ms).
[20:19:01.951] <TB1> INFO: Expecting 655360 events.
[20:19:16.069] <TB1> INFO: 655360 events read in total (13712ms).
[20:19:16.114] <TB1> INFO: Expecting 655360 events.
[20:19:30.106] <TB1> INFO: 655360 events read in total (13589ms).
[20:19:30.160] <TB1> INFO: Expecting 655360 events.
[20:19:44.216] <TB1> INFO: 655360 events read in total (13653ms).
[20:19:44.258] <TB1> INFO: Expecting 655360 events.
[20:19:58.313] <TB1> INFO: 655360 events read in total (13652ms).
[20:19:58.375] <TB1> INFO: Expecting 655360 events.
[20:20:12.508] <TB1> INFO: 655360 events read in total (13729ms).
[20:20:12.559] <TB1> INFO: Expecting 655360 events.
[20:20:26.569] <TB1> INFO: 655360 events read in total (13607ms).
[20:20:26.637] <TB1> INFO: Expecting 655360 events.
[20:20:40.737] <TB1> INFO: 655360 events read in total (13697ms).
[20:20:40.798] <TB1> INFO: Expecting 655360 events.
[20:20:54.965] <TB1> INFO: 655360 events read in total (13764ms).
[20:20:55.031] <TB1> INFO: Expecting 655360 events.
[20:21:09.102] <TB1> INFO: 655360 events read in total (13668ms).
[20:21:09.200] <TB1> INFO: Expecting 655360 events.
[20:21:23.314] <TB1> INFO: 655360 events read in total (13711ms).
[20:21:23.389] <TB1> INFO: Test took 226264ms.
[20:21:23.555] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.560] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.565] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[20:21:23.570] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[20:21:23.574] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.579] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.583] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[20:21:23.588] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[20:21:23.592] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[20:21:23.597] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[20:21:23.602] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[20:21:23.607] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[20:21:23.611] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[20:21:23.616] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[20:21:23.620] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.625] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[20:21:23.629] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[20:21:23.634] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.639] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.644] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[20:21:23.649] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[20:21:23.655] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[20:21:23.660] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[20:21:23.666] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.671] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.676] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.681] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.687] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[20:21:23.692] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[20:21:23.697] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.702] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.708] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.713] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.718] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:23.752] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C0.dat
[20:21:23.753] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C1.dat
[20:21:23.753] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C2.dat
[20:21:23.753] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C3.dat
[20:21:23.753] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C4.dat
[20:21:23.754] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C5.dat
[20:21:23.754] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C6.dat
[20:21:23.754] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C7.dat
[20:21:23.754] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C8.dat
[20:21:23.754] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C9.dat
[20:21:23.754] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C10.dat
[20:21:23.754] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C11.dat
[20:21:23.754] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C12.dat
[20:21:23.754] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C13.dat
[20:21:23.755] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C14.dat
[20:21:23.755] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C15.dat
[20:21:24.009] <TB1> INFO: Expecting 41600 events.
[20:21:27.093] <TB1> INFO: 41600 events read in total (2493ms).
[20:21:27.093] <TB1> INFO: Test took 3335ms.
[20:21:27.537] <TB1> INFO: Expecting 41600 events.
[20:21:30.571] <TB1> INFO: 41600 events read in total (2442ms).
[20:21:30.572] <TB1> INFO: Test took 3269ms.
[20:21:31.015] <TB1> INFO: Expecting 41600 events.
[20:21:34.093] <TB1> INFO: 41600 events read in total (2487ms).
[20:21:34.093] <TB1> INFO: Test took 3310ms.
[20:21:34.307] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:34.396] <TB1> INFO: Expecting 2560 events.
[20:21:35.284] <TB1> INFO: 2560 events read in total (297ms).
[20:21:35.285] <TB1> INFO: Test took 978ms.
[20:21:35.286] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:35.593] <TB1> INFO: Expecting 2560 events.
[20:21:36.477] <TB1> INFO: 2560 events read in total (293ms).
[20:21:36.478] <TB1> INFO: Test took 1192ms.
[20:21:36.479] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:36.786] <TB1> INFO: Expecting 2560 events.
[20:21:37.669] <TB1> INFO: 2560 events read in total (292ms).
[20:21:37.669] <TB1> INFO: Test took 1190ms.
[20:21:37.671] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:37.978] <TB1> INFO: Expecting 2560 events.
[20:21:38.860] <TB1> INFO: 2560 events read in total (291ms).
[20:21:38.860] <TB1> INFO: Test took 1189ms.
[20:21:38.862] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:39.169] <TB1> INFO: Expecting 2560 events.
[20:21:40.054] <TB1> INFO: 2560 events read in total (294ms).
[20:21:40.054] <TB1> INFO: Test took 1192ms.
[20:21:40.056] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:40.364] <TB1> INFO: Expecting 2560 events.
[20:21:41.254] <TB1> INFO: 2560 events read in total (298ms).
[20:21:41.254] <TB1> INFO: Test took 1198ms.
[20:21:41.256] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:41.563] <TB1> INFO: Expecting 2560 events.
[20:21:42.447] <TB1> INFO: 2560 events read in total (293ms).
[20:21:42.447] <TB1> INFO: Test took 1191ms.
[20:21:42.450] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:42.756] <TB1> INFO: Expecting 2560 events.
[20:21:43.638] <TB1> INFO: 2560 events read in total (291ms).
[20:21:43.638] <TB1> INFO: Test took 1188ms.
[20:21:43.640] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:43.946] <TB1> INFO: Expecting 2560 events.
[20:21:44.824] <TB1> INFO: 2560 events read in total (286ms).
[20:21:44.824] <TB1> INFO: Test took 1184ms.
[20:21:44.826] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:45.133] <TB1> INFO: Expecting 2560 events.
[20:21:46.011] <TB1> INFO: 2560 events read in total (287ms).
[20:21:46.011] <TB1> INFO: Test took 1185ms.
[20:21:46.013] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:46.320] <TB1> INFO: Expecting 2560 events.
[20:21:47.200] <TB1> INFO: 2560 events read in total (288ms).
[20:21:47.200] <TB1> INFO: Test took 1187ms.
[20:21:47.202] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:47.508] <TB1> INFO: Expecting 2560 events.
[20:21:48.387] <TB1> INFO: 2560 events read in total (287ms).
[20:21:48.388] <TB1> INFO: Test took 1186ms.
[20:21:48.389] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:48.696] <TB1> INFO: Expecting 2560 events.
[20:21:49.575] <TB1> INFO: 2560 events read in total (287ms).
[20:21:49.575] <TB1> INFO: Test took 1186ms.
[20:21:49.577] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:49.883] <TB1> INFO: Expecting 2560 events.
[20:21:50.764] <TB1> INFO: 2560 events read in total (289ms).
[20:21:50.765] <TB1> INFO: Test took 1188ms.
[20:21:50.766] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:51.073] <TB1> INFO: Expecting 2560 events.
[20:21:51.951] <TB1> INFO: 2560 events read in total (286ms).
[20:21:51.952] <TB1> INFO: Test took 1186ms.
[20:21:51.954] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:52.260] <TB1> INFO: Expecting 2560 events.
[20:21:53.148] <TB1> INFO: 2560 events read in total (296ms).
[20:21:53.149] <TB1> INFO: Test took 1196ms.
[20:21:53.151] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:53.457] <TB1> INFO: Expecting 2560 events.
[20:21:54.337] <TB1> INFO: 2560 events read in total (288ms).
[20:21:54.337] <TB1> INFO: Test took 1187ms.
[20:21:54.339] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:54.645] <TB1> INFO: Expecting 2560 events.
[20:21:55.524] <TB1> INFO: 2560 events read in total (287ms).
[20:21:55.525] <TB1> INFO: Test took 1186ms.
[20:21:55.527] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:55.833] <TB1> INFO: Expecting 2560 events.
[20:21:56.713] <TB1> INFO: 2560 events read in total (288ms).
[20:21:56.713] <TB1> INFO: Test took 1187ms.
[20:21:56.715] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:57.021] <TB1> INFO: Expecting 2560 events.
[20:21:57.900] <TB1> INFO: 2560 events read in total (287ms).
[20:21:57.900] <TB1> INFO: Test took 1186ms.
[20:21:57.902] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:58.208] <TB1> INFO: Expecting 2560 events.
[20:21:59.086] <TB1> INFO: 2560 events read in total (286ms).
[20:21:59.086] <TB1> INFO: Test took 1184ms.
[20:21:59.088] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:59.395] <TB1> INFO: Expecting 2560 events.
[20:22:00.274] <TB1> INFO: 2560 events read in total (288ms).
[20:22:00.275] <TB1> INFO: Test took 1187ms.
[20:22:00.277] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:00.583] <TB1> INFO: Expecting 2560 events.
[20:22:01.461] <TB1> INFO: 2560 events read in total (286ms).
[20:22:01.462] <TB1> INFO: Test took 1186ms.
[20:22:01.464] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:01.770] <TB1> INFO: Expecting 2560 events.
[20:22:02.651] <TB1> INFO: 2560 events read in total (289ms).
[20:22:02.651] <TB1> INFO: Test took 1187ms.
[20:22:02.653] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:02.960] <TB1> INFO: Expecting 2560 events.
[20:22:03.843] <TB1> INFO: 2560 events read in total (292ms).
[20:22:03.843] <TB1> INFO: Test took 1190ms.
[20:22:03.845] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:04.151] <TB1> INFO: Expecting 2560 events.
[20:22:05.035] <TB1> INFO: 2560 events read in total (292ms).
[20:22:05.035] <TB1> INFO: Test took 1190ms.
[20:22:05.037] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:05.343] <TB1> INFO: Expecting 2560 events.
[20:22:06.226] <TB1> INFO: 2560 events read in total (291ms).
[20:22:06.227] <TB1> INFO: Test took 1190ms.
[20:22:06.229] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:06.535] <TB1> INFO: Expecting 2560 events.
[20:22:07.418] <TB1> INFO: 2560 events read in total (291ms).
[20:22:07.419] <TB1> INFO: Test took 1190ms.
[20:22:07.420] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:07.727] <TB1> INFO: Expecting 2560 events.
[20:22:08.610] <TB1> INFO: 2560 events read in total (291ms).
[20:22:08.611] <TB1> INFO: Test took 1191ms.
[20:22:08.612] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:08.919] <TB1> INFO: Expecting 2560 events.
[20:22:09.802] <TB1> INFO: 2560 events read in total (291ms).
[20:22:09.802] <TB1> INFO: Test took 1190ms.
[20:22:09.804] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:10.110] <TB1> INFO: Expecting 2560 events.
[20:22:10.994] <TB1> INFO: 2560 events read in total (293ms).
[20:22:10.994] <TB1> INFO: Test took 1190ms.
[20:22:10.996] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:11.302] <TB1> INFO: Expecting 2560 events.
[20:22:12.186] <TB1> INFO: 2560 events read in total (292ms).
[20:22:12.186] <TB1> INFO: Test took 1190ms.
[20:22:12.649] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 629 seconds
[20:22:12.649] <TB1> INFO: PH scale (per ROC): 60 42 49 48 34 39 43 30 32 60 33 52 38 40 42 45
[20:22:12.649] <TB1> INFO: PH offset (per ROC): 127 91 109 112 95 109 97 102 102 125 109 104 98 85 95 107
[20:22:12.654] <TB1> INFO: Decoding statistics:
[20:22:12.654] <TB1> INFO: General information:
[20:22:12.654] <TB1> INFO: 16bit words read: 127886
[20:22:12.654] <TB1> INFO: valid events total: 20480
[20:22:12.654] <TB1> INFO: empty events: 17977
[20:22:12.654] <TB1> INFO: valid events with pixels: 2503
[20:22:12.654] <TB1> INFO: valid pixel hits: 2503
[20:22:12.654] <TB1> INFO: Event errors: 0
[20:22:12.654] <TB1> INFO: start marker: 0
[20:22:12.654] <TB1> INFO: stop marker: 0
[20:22:12.654] <TB1> INFO: overflow: 0
[20:22:12.654] <TB1> INFO: invalid 5bit words: 0
[20:22:12.654] <TB1> INFO: invalid XOR eye diagram: 0
[20:22:12.654] <TB1> INFO: frame (failed synchr.): 0
[20:22:12.654] <TB1> INFO: idle data (no TBM trl): 0
[20:22:12.654] <TB1> INFO: no data (only TBM hdr): 0
[20:22:12.654] <TB1> INFO: TBM errors: 0
[20:22:12.654] <TB1> INFO: flawed TBM headers: 0
[20:22:12.654] <TB1> INFO: flawed TBM trailers: 0
[20:22:12.654] <TB1> INFO: event ID mismatches: 0
[20:22:12.654] <TB1> INFO: ROC errors: 0
[20:22:12.654] <TB1> INFO: missing ROC header(s): 0
[20:22:12.654] <TB1> INFO: misplaced readback start: 0
[20:22:12.654] <TB1> INFO: Pixel decoding errors: 0
[20:22:12.654] <TB1> INFO: pixel data incomplete: 0
[20:22:12.654] <TB1> INFO: pixel address: 0
[20:22:12.654] <TB1> INFO: pulse height fill bit: 0
[20:22:12.654] <TB1> INFO: buffer corruption: 0
[20:22:12.921] <TB1> INFO: ######################################################################
[20:22:12.921] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[20:22:12.921] <TB1> INFO: ######################################################################
[20:22:12.931] <TB1> INFO: scanning low vcal = 10
[20:22:13.163] <TB1> INFO: Expecting 41600 events.
[20:22:16.719] <TB1> INFO: 41600 events read in total (2965ms).
[20:22:16.719] <TB1> INFO: Test took 3788ms.
[20:22:16.721] <TB1> INFO: scanning low vcal = 20
[20:22:17.021] <TB1> INFO: Expecting 41600 events.
[20:22:20.583] <TB1> INFO: 41600 events read in total (2971ms).
[20:22:20.584] <TB1> INFO: Test took 3863ms.
[20:22:20.585] <TB1> INFO: scanning low vcal = 30
[20:22:20.882] <TB1> INFO: Expecting 41600 events.
[20:22:24.526] <TB1> INFO: 41600 events read in total (3052ms).
[20:22:24.527] <TB1> INFO: Test took 3942ms.
[20:22:24.529] <TB1> INFO: scanning low vcal = 40
[20:22:24.810] <TB1> INFO: Expecting 41600 events.
[20:22:28.724] <TB1> INFO: 41600 events read in total (3323ms).
[20:22:28.725] <TB1> INFO: Test took 4196ms.
[20:22:28.728] <TB1> INFO: scanning low vcal = 50
[20:22:29.004] <TB1> INFO: Expecting 41600 events.
[20:22:32.967] <TB1> INFO: 41600 events read in total (3371ms).
[20:22:32.968] <TB1> INFO: Test took 4240ms.
[20:22:32.970] <TB1> INFO: scanning low vcal = 60
[20:22:33.247] <TB1> INFO: Expecting 41600 events.
[20:22:37.207] <TB1> INFO: 41600 events read in total (3369ms).
[20:22:37.207] <TB1> INFO: Test took 4237ms.
[20:22:37.210] <TB1> INFO: scanning low vcal = 70
[20:22:37.487] <TB1> INFO: Expecting 41600 events.
[20:22:41.425] <TB1> INFO: 41600 events read in total (3347ms).
[20:22:41.425] <TB1> INFO: Test took 4215ms.
[20:22:41.428] <TB1> INFO: scanning low vcal = 80
[20:22:41.704] <TB1> INFO: Expecting 41600 events.
[20:22:45.694] <TB1> INFO: 41600 events read in total (3398ms).
[20:22:45.695] <TB1> INFO: Test took 4267ms.
[20:22:45.698] <TB1> INFO: scanning low vcal = 90
[20:22:45.975] <TB1> INFO: Expecting 41600 events.
[20:22:49.952] <TB1> INFO: 41600 events read in total (3386ms).
[20:22:49.952] <TB1> INFO: Test took 4254ms.
[20:22:49.955] <TB1> INFO: scanning low vcal = 100
[20:22:50.231] <TB1> INFO: Expecting 41600 events.
[20:22:54.182] <TB1> INFO: 41600 events read in total (3359ms).
[20:22:54.183] <TB1> INFO: Test took 4228ms.
[20:22:54.185] <TB1> INFO: scanning low vcal = 110
[20:22:54.462] <TB1> INFO: Expecting 41600 events.
[20:22:58.433] <TB1> INFO: 41600 events read in total (3379ms).
[20:22:58.433] <TB1> INFO: Test took 4248ms.
[20:22:58.436] <TB1> INFO: scanning low vcal = 120
[20:22:58.713] <TB1> INFO: Expecting 41600 events.
[20:23:02.668] <TB1> INFO: 41600 events read in total (3364ms).
[20:23:02.668] <TB1> INFO: Test took 4233ms.
[20:23:02.671] <TB1> INFO: scanning low vcal = 130
[20:23:02.948] <TB1> INFO: Expecting 41600 events.
[20:23:06.905] <TB1> INFO: 41600 events read in total (3366ms).
[20:23:06.906] <TB1> INFO: Test took 4235ms.
[20:23:06.909] <TB1> INFO: scanning low vcal = 140
[20:23:07.185] <TB1> INFO: Expecting 41600 events.
[20:23:11.138] <TB1> INFO: 41600 events read in total (3361ms).
[20:23:11.139] <TB1> INFO: Test took 4230ms.
[20:23:11.141] <TB1> INFO: scanning low vcal = 150
[20:23:11.460] <TB1> INFO: Expecting 41600 events.
[20:23:15.428] <TB1> INFO: 41600 events read in total (3376ms).
[20:23:15.429] <TB1> INFO: Test took 4288ms.
[20:23:15.431] <TB1> INFO: scanning low vcal = 160
[20:23:15.708] <TB1> INFO: Expecting 41600 events.
[20:23:19.659] <TB1> INFO: 41600 events read in total (3360ms).
[20:23:19.660] <TB1> INFO: Test took 4229ms.
[20:23:19.662] <TB1> INFO: scanning low vcal = 170
[20:23:19.940] <TB1> INFO: Expecting 41600 events.
[20:23:23.861] <TB1> INFO: 41600 events read in total (3330ms).
[20:23:23.862] <TB1> INFO: Test took 4200ms.
[20:23:23.865] <TB1> INFO: scanning low vcal = 180
[20:23:24.141] <TB1> INFO: Expecting 41600 events.
[20:23:28.113] <TB1> INFO: 41600 events read in total (3380ms).
[20:23:28.114] <TB1> INFO: Test took 4249ms.
[20:23:28.116] <TB1> INFO: scanning low vcal = 190
[20:23:28.393] <TB1> INFO: Expecting 41600 events.
[20:23:32.369] <TB1> INFO: 41600 events read in total (3384ms).
[20:23:32.370] <TB1> INFO: Test took 4253ms.
[20:23:32.373] <TB1> INFO: scanning low vcal = 200
[20:23:32.678] <TB1> INFO: Expecting 41600 events.
[20:23:36.632] <TB1> INFO: 41600 events read in total (3363ms).
[20:23:36.632] <TB1> INFO: Test took 4259ms.
[20:23:36.635] <TB1> INFO: scanning low vcal = 210
[20:23:36.912] <TB1> INFO: Expecting 41600 events.
[20:23:40.870] <TB1> INFO: 41600 events read in total (3367ms).
[20:23:40.870] <TB1> INFO: Test took 4235ms.
[20:23:40.873] <TB1> INFO: scanning low vcal = 220
[20:23:41.161] <TB1> INFO: Expecting 41600 events.
[20:23:45.159] <TB1> INFO: 41600 events read in total (3407ms).
[20:23:45.160] <TB1> INFO: Test took 4287ms.
[20:23:45.162] <TB1> INFO: scanning low vcal = 230
[20:23:45.439] <TB1> INFO: Expecting 41600 events.
[20:23:49.423] <TB1> INFO: 41600 events read in total (3392ms).
[20:23:49.424] <TB1> INFO: Test took 4262ms.
[20:23:49.426] <TB1> INFO: scanning low vcal = 240
[20:23:49.707] <TB1> INFO: Expecting 41600 events.
[20:23:53.665] <TB1> INFO: 41600 events read in total (3367ms).
[20:23:53.665] <TB1> INFO: Test took 4239ms.
[20:23:53.668] <TB1> INFO: scanning low vcal = 250
[20:23:53.945] <TB1> INFO: Expecting 41600 events.
[20:23:57.875] <TB1> INFO: 41600 events read in total (3338ms).
[20:23:57.876] <TB1> INFO: Test took 4208ms.
[20:23:57.880] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[20:23:58.156] <TB1> INFO: Expecting 41600 events.
[20:24:02.094] <TB1> INFO: 41600 events read in total (3346ms).
[20:24:02.095] <TB1> INFO: Test took 4215ms.
[20:24:02.097] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[20:24:02.374] <TB1> INFO: Expecting 41600 events.
[20:24:06.308] <TB1> INFO: 41600 events read in total (3342ms).
[20:24:06.308] <TB1> INFO: Test took 4211ms.
[20:24:06.311] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[20:24:06.588] <TB1> INFO: Expecting 41600 events.
[20:24:10.522] <TB1> INFO: 41600 events read in total (3341ms).
[20:24:10.522] <TB1> INFO: Test took 4212ms.
[20:24:10.525] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[20:24:10.801] <TB1> INFO: Expecting 41600 events.
[20:24:14.730] <TB1> INFO: 41600 events read in total (3337ms).
[20:24:14.731] <TB1> INFO: Test took 4206ms.
[20:24:14.733] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[20:24:15.010] <TB1> INFO: Expecting 41600 events.
[20:24:18.989] <TB1> INFO: 41600 events read in total (3387ms).
[20:24:18.989] <TB1> INFO: Test took 4256ms.
[20:24:19.500] <TB1> INFO: PixTestGainPedestal::measure() done
[20:24:59.022] <TB1> INFO: PixTestGainPedestal::fit() done
[20:24:59.022] <TB1> INFO: non-linearity mean: 0.983 0.928 0.970 0.973 0.927 0.918 0.927 0.944 0.972 0.986 0.918 0.970 0.927 0.905 0.919 0.956
[20:24:59.022] <TB1> INFO: non-linearity RMS: 0.003 0.072 0.010 0.009 0.135 0.097 0.083 0.207 0.204 0.003 0.168 0.027 0.109 0.153 0.080 0.034
[20:24:59.022] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[20:24:59.040] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[20:24:59.063] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[20:24:59.085] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[20:24:59.108] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[20:24:59.129] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[20:24:59.151] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[20:24:59.174] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[20:24:59.196] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[20:24:59.219] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[20:24:59.241] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[20:24:59.265] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[20:24:59.289] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[20:24:59.313] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[20:24:59.336] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[20:24:59.358] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[20:24:59.382] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 166 seconds
[20:24:59.382] <TB1> INFO: Decoding statistics:
[20:24:59.382] <TB1> INFO: General information:
[20:24:59.382] <TB1> INFO: 16bit words read: 3305514
[20:24:59.382] <TB1> INFO: valid events total: 332800
[20:24:59.382] <TB1> INFO: empty events: 1825
[20:24:59.382] <TB1> INFO: valid events with pixels: 330975
[20:24:59.382] <TB1> INFO: valid pixel hits: 654357
[20:24:59.382] <TB1> INFO: Event errors: 0
[20:24:59.382] <TB1> INFO: start marker: 0
[20:24:59.382] <TB1> INFO: stop marker: 0
[20:24:59.382] <TB1> INFO: overflow: 0
[20:24:59.382] <TB1> INFO: invalid 5bit words: 0
[20:24:59.382] <TB1> INFO: invalid XOR eye diagram: 0
[20:24:59.382] <TB1> INFO: frame (failed synchr.): 0
[20:24:59.382] <TB1> INFO: idle data (no TBM trl): 0
[20:24:59.382] <TB1> INFO: no data (only TBM hdr): 0
[20:24:59.382] <TB1> INFO: TBM errors: 0
[20:24:59.382] <TB1> INFO: flawed TBM headers: 0
[20:24:59.382] <TB1> INFO: flawed TBM trailers: 0
[20:24:59.382] <TB1> INFO: event ID mismatches: 0
[20:24:59.382] <TB1> INFO: ROC errors: 0
[20:24:59.382] <TB1> INFO: missing ROC header(s): 0
[20:24:59.382] <TB1> INFO: misplaced readback start: 0
[20:24:59.382] <TB1> INFO: Pixel decoding errors: 0
[20:24:59.382] <TB1> INFO: pixel data incomplete: 0
[20:24:59.382] <TB1> INFO: pixel address: 0
[20:24:59.382] <TB1> INFO: pulse height fill bit: 0
[20:24:59.382] <TB1> INFO: buffer corruption: 0
[20:24:59.402] <TB1> INFO: Decoding statistics:
[20:24:59.402] <TB1> INFO: General information:
[20:24:59.402] <TB1> INFO: 16bit words read: 3434936
[20:24:59.402] <TB1> INFO: valid events total: 353536
[20:24:59.402] <TB1> INFO: empty events: 20058
[20:24:59.402] <TB1> INFO: valid events with pixels: 333478
[20:24:59.402] <TB1> INFO: valid pixel hits: 656860
[20:24:59.402] <TB1> INFO: Event errors: 0
[20:24:59.402] <TB1> INFO: start marker: 0
[20:24:59.402] <TB1> INFO: stop marker: 0
[20:24:59.402] <TB1> INFO: overflow: 0
[20:24:59.402] <TB1> INFO: invalid 5bit words: 0
[20:24:59.402] <TB1> INFO: invalid XOR eye diagram: 0
[20:24:59.402] <TB1> INFO: frame (failed synchr.): 0
[20:24:59.402] <TB1> INFO: idle data (no TBM trl): 0
[20:24:59.402] <TB1> INFO: no data (only TBM hdr): 0
[20:24:59.402] <TB1> INFO: TBM errors: 0
[20:24:59.402] <TB1> INFO: flawed TBM headers: 0
[20:24:59.402] <TB1> INFO: flawed TBM trailers: 0
[20:24:59.402] <TB1> INFO: event ID mismatches: 0
[20:24:59.402] <TB1> INFO: ROC errors: 0
[20:24:59.402] <TB1> INFO: missing ROC header(s): 0
[20:24:59.402] <TB1> INFO: misplaced readback start: 0
[20:24:59.402] <TB1> INFO: Pixel decoding errors: 0
[20:24:59.402] <TB1> INFO: pixel data incomplete: 0
[20:24:59.402] <TB1> INFO: pixel address: 0
[20:24:59.402] <TB1> INFO: pulse height fill bit: 0
[20:24:59.402] <TB1> INFO: buffer corruption: 0
[20:24:59.402] <TB1> INFO: enter test to run
[20:24:59.402] <TB1> INFO: test: Trim80 no parameter change
[20:24:59.402] <TB1> INFO: running: trim80
[20:24:59.426] <TB1> INFO: ######################################################################
[20:24:59.426] <TB1> INFO: PixTestTrim80::doTest()
[20:24:59.426] <TB1> INFO: ######################################################################
[20:24:59.427] <TB1> INFO: ----------------------------------------------------------------------
[20:24:59.427] <TB1> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[20:24:59.427] <TB1> INFO: ----------------------------------------------------------------------
[20:24:59.468] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[20:24:59.468] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[20:24:59.479] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:24:59.479] <TB1> INFO: run 1 of 1
[20:24:59.717] <TB1> INFO: Expecting 5025280 events.
[20:25:27.514] <TB1> INFO: 673688 events read in total (27206ms).
[20:25:54.244] <TB1> INFO: 1343528 events read in total (53936ms).
[20:26:20.987] <TB1> INFO: 2011688 events read in total (80679ms).
[20:26:47.920] <TB1> INFO: 2679320 events read in total (107612ms).
[20:27:14.647] <TB1> INFO: 3347368 events read in total (134339ms).
[20:27:41.465] <TB1> INFO: 4014040 events read in total (161157ms).
[20:28:08.416] <TB1> INFO: 4680704 events read in total (188108ms).
[20:28:22.415] <TB1> INFO: 5025280 events read in total (202107ms).
[20:28:22.474] <TB1> INFO: Test took 202995ms.
[20:28:46.738] <TB1> INFO: ROC 0 VthrComp = 73
[20:28:46.738] <TB1> INFO: ROC 1 VthrComp = 75
[20:28:46.738] <TB1> INFO: ROC 2 VthrComp = 72
[20:28:46.738] <TB1> INFO: ROC 3 VthrComp = 73
[20:28:46.738] <TB1> INFO: ROC 4 VthrComp = 71
[20:28:46.738] <TB1> INFO: ROC 5 VthrComp = 69
[20:28:46.739] <TB1> INFO: ROC 6 VthrComp = 72
[20:28:46.739] <TB1> INFO: ROC 7 VthrComp = 72
[20:28:46.739] <TB1> INFO: ROC 8 VthrComp = 70
[20:28:46.739] <TB1> INFO: ROC 9 VthrComp = 68
[20:28:46.739] <TB1> INFO: ROC 10 VthrComp = 72
[20:28:46.739] <TB1> INFO: ROC 11 VthrComp = 75
[20:28:46.740] <TB1> INFO: ROC 12 VthrComp = 77
[20:28:46.740] <TB1> INFO: ROC 13 VthrComp = 75
[20:28:46.740] <TB1> INFO: ROC 14 VthrComp = 67
[20:28:46.740] <TB1> INFO: ROC 15 VthrComp = 73
[20:28:46.975] <TB1> INFO: Expecting 41600 events.
[20:28:50.444] <TB1> INFO: 41600 events read in total (2877ms).
[20:28:50.445] <TB1> INFO: Test took 3704ms.
[20:28:50.453] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[20:28:50.453] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[20:28:50.462] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:28:50.462] <TB1> INFO: run 1 of 1
[20:28:50.740] <TB1> INFO: Expecting 5025280 events.
[20:29:18.639] <TB1> INFO: 681840 events read in total (27307ms).
[20:29:45.626] <TB1> INFO: 1359296 events read in total (54294ms).
[20:30:12.541] <TB1> INFO: 2035704 events read in total (81209ms).
[20:30:39.602] <TB1> INFO: 2709712 events read in total (108270ms).
[20:31:06.075] <TB1> INFO: 3380336 events read in total (134743ms).
[20:31:32.886] <TB1> INFO: 4049664 events read in total (161554ms).
[20:31:59.581] <TB1> INFO: 4718696 events read in total (188249ms).
[20:32:11.773] <TB1> INFO: 5025280 events read in total (200441ms).
[20:32:11.822] <TB1> INFO: Test took 201360ms.
[20:32:37.982] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 106.851 for pixel 0/3 mean/min/max = 91.7282/76.5981/106.858
[20:32:37.982] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 108.014 for pixel 6/5 mean/min/max = 92.6794/77.2388/108.12
[20:32:37.983] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 105.586 for pixel 3/31 mean/min/max = 91.0553/76.2113/105.899
[20:32:37.984] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 108.688 for pixel 0/20 mean/min/max = 92.9713/77.1514/108.791
[20:32:37.984] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 103.281 for pixel 0/33 mean/min/max = 88.8956/74.45/103.341
[20:32:37.985] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 103.741 for pixel 0/79 mean/min/max = 88.9997/74.212/103.788
[20:32:37.985] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 106.954 for pixel 20/9 mean/min/max = 92.4546/77.9204/106.989
[20:32:37.986] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 105.498 for pixel 20/27 mean/min/max = 91.1483/76.7791/105.518
[20:32:37.986] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 119.641 for pixel 0/60 mean/min/max = 95.795/71.8746/119.715
[20:32:37.987] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 105.494 for pixel 0/51 mean/min/max = 89.7145/73.868/105.561
[20:32:37.987] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 109.839 for pixel 6/76 mean/min/max = 93.3239/76.6738/109.974
[20:32:37.988] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 106.057 for pixel 51/69 mean/min/max = 92.3809/78.6107/106.151
[20:32:37.988] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 109.544 for pixel 0/8 mean/min/max = 94.5878/79.1196/110.056
[20:32:37.989] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 108.546 for pixel 13/12 mean/min/max = 93.1339/77.6654/108.602
[20:32:37.989] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 104.661 for pixel 0/77 mean/min/max = 89.6273/74.3565/104.898
[20:32:37.990] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 106.637 for pixel 4/53 mean/min/max = 91.7395/76.7834/106.696
[20:32:37.990] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:32:38.079] <TB1> INFO: Expecting 411648 events.
[20:32:47.510] <TB1> INFO: 411648 events read in total (8839ms).
[20:32:47.517] <TB1> INFO: Expecting 411648 events.
[20:32:56.754] <TB1> INFO: 411648 events read in total (8834ms).
[20:32:56.763] <TB1> INFO: Expecting 411648 events.
[20:33:05.893] <TB1> INFO: 411648 events read in total (8727ms).
[20:33:05.905] <TB1> INFO: Expecting 411648 events.
[20:33:14.947] <TB1> INFO: 411648 events read in total (8639ms).
[20:33:14.967] <TB1> INFO: Expecting 411648 events.
[20:33:24.009] <TB1> INFO: 411648 events read in total (8640ms).
[20:33:24.026] <TB1> INFO: Expecting 411648 events.
[20:33:33.127] <TB1> INFO: 411648 events read in total (8698ms).
[20:33:33.154] <TB1> INFO: Expecting 411648 events.
[20:33:42.176] <TB1> INFO: 411648 events read in total (8619ms).
[20:33:42.200] <TB1> INFO: Expecting 411648 events.
[20:33:51.262] <TB1> INFO: 411648 events read in total (8659ms).
[20:33:51.287] <TB1> INFO: Expecting 411648 events.
[20:34:00.380] <TB1> INFO: 411648 events read in total (8690ms).
[20:34:00.417] <TB1> INFO: Expecting 411648 events.
[20:34:09.518] <TB1> INFO: 411648 events read in total (8698ms).
[20:34:09.551] <TB1> INFO: Expecting 411648 events.
[20:34:18.626] <TB1> INFO: 411648 events read in total (8672ms).
[20:34:18.659] <TB1> INFO: Expecting 411648 events.
[20:34:27.741] <TB1> INFO: 411648 events read in total (8679ms).
[20:34:27.780] <TB1> INFO: Expecting 411648 events.
[20:34:36.923] <TB1> INFO: 411648 events read in total (8740ms).
[20:34:36.974] <TB1> INFO: Expecting 411648 events.
[20:34:45.985] <TB1> INFO: 411648 events read in total (8608ms).
[20:34:46.027] <TB1> INFO: Expecting 411648 events.
[20:34:55.144] <TB1> INFO: 411648 events read in total (8714ms).
[20:34:55.204] <TB1> INFO: Expecting 411648 events.
[20:35:04.329] <TB1> INFO: 411648 events read in total (8722ms).
[20:35:04.392] <TB1> INFO: Test took 146402ms.
[20:35:06.024] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[20:35:06.034] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:35:06.034] <TB1> INFO: run 1 of 1
[20:35:06.267] <TB1> INFO: Expecting 5025280 events.
[20:35:33.216] <TB1> INFO: 667624 events read in total (26357ms).
[20:35:59.804] <TB1> INFO: 1332056 events read in total (52945ms).
[20:36:26.609] <TB1> INFO: 1996224 events read in total (79750ms).
[20:36:53.881] <TB1> INFO: 2657112 events read in total (107022ms).
[20:37:20.322] <TB1> INFO: 3313416 events read in total (133463ms).
[20:37:46.858] <TB1> INFO: 3968360 events read in total (159999ms).
[20:38:13.807] <TB1> INFO: 4621072 events read in total (186948ms).
[20:38:30.485] <TB1> INFO: 5025280 events read in total (203626ms).
[20:38:30.547] <TB1> INFO: Test took 204513ms.
[20:38:55.473] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 50.607538 .. 98.836386
[20:38:55.744] <TB1> INFO: Expecting 208000 events.
[20:39:05.861] <TB1> INFO: 208000 events read in total (9526ms).
[20:39:05.862] <TB1> INFO: Test took 10387ms.
[20:39:05.921] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 40 .. 108 (-1/-1) hits flags = 528 (plus default)
[20:39:05.931] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:39:05.931] <TB1> INFO: run 1 of 1
[20:39:06.209] <TB1> INFO: Expecting 2296320 events.
[20:39:34.515] <TB1> INFO: 702024 events read in total (27714ms).
[20:40:02.223] <TB1> INFO: 1398680 events read in total (55422ms).
[20:40:29.887] <TB1> INFO: 2088136 events read in total (83086ms).
[20:40:38.320] <TB1> INFO: 2296320 events read in total (91519ms).
[20:40:38.350] <TB1> INFO: Test took 92420ms.
[20:40:57.464] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 62.503914 .. 87.477116
[20:40:57.706] <TB1> INFO: Expecting 208000 events.
[20:41:07.503] <TB1> INFO: 208000 events read in total (9206ms).
[20:41:07.504] <TB1> INFO: Test took 10038ms.
[20:41:07.557] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 52 .. 97 (-1/-1) hits flags = 528 (plus default)
[20:41:07.565] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:41:07.565] <TB1> INFO: run 1 of 1
[20:41:07.843] <TB1> INFO: Expecting 1530880 events.
[20:41:36.523] <TB1> INFO: 712800 events read in total (28088ms).
[20:42:04.788] <TB1> INFO: 1423520 events read in total (56354ms).
[20:42:09.499] <TB1> INFO: 1530880 events read in total (61064ms).
[20:42:09.522] <TB1> INFO: Test took 61957ms.
[20:42:26.925] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 66.942171 .. 83.375554
[20:42:27.178] <TB1> INFO: Expecting 208000 events.
[20:42:37.122] <TB1> INFO: 208000 events read in total (9352ms).
[20:42:37.123] <TB1> INFO: Test took 10196ms.
[20:42:37.189] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 56 .. 93 (-1/-1) hits flags = 528 (plus default)
[20:42:37.202] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:42:37.202] <TB1> INFO: run 1 of 1
[20:42:37.480] <TB1> INFO: Expecting 1264640 events.
[20:43:06.474] <TB1> INFO: 722936 events read in total (28387ms).
[20:43:28.055] <TB1> INFO: 1264640 events read in total (49969ms).
[20:43:28.077] <TB1> INFO: Test took 50875ms.
[20:43:44.423] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 69.901603 .. 83.375554
[20:43:44.668] <TB1> INFO: Expecting 208000 events.
[20:43:54.609] <TB1> INFO: 208000 events read in total (9349ms).
[20:43:54.610] <TB1> INFO: Test took 10186ms.
[20:43:54.686] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 59 .. 93 (-1/-1) hits flags = 528 (plus default)
[20:43:54.698] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:43:54.698] <TB1> INFO: run 1 of 1
[20:43:55.021] <TB1> INFO: Expecting 1164800 events.
[20:44:24.215] <TB1> INFO: 713064 events read in total (28602ms).
[20:44:42.269] <TB1> INFO: 1164800 events read in total (46656ms).
[20:44:42.289] <TB1> INFO: Test took 47590ms.
[20:44:58.900] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[20:44:58.900] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[20:44:58.909] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[20:44:58.909] <TB1> INFO: run 1 of 1
[20:44:59.159] <TB1> INFO: Expecting 1364480 events.
[20:45:27.513] <TB1> INFO: 668920 events read in total (27762ms).
[20:45:54.558] <TB1> INFO: 1337488 events read in total (54807ms).
[20:45:56.094] <TB1> INFO: 1364480 events read in total (56343ms).
[20:45:56.118] <TB1> INFO: Test took 57209ms.
[20:46:14.548] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C0.dat
[20:46:14.549] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C1.dat
[20:46:14.549] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C2.dat
[20:46:14.549] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C3.dat
[20:46:14.549] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C4.dat
[20:46:14.549] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C5.dat
[20:46:14.549] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C6.dat
[20:46:14.549] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C7.dat
[20:46:14.549] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C8.dat
[20:46:14.549] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C9.dat
[20:46:14.550] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C10.dat
[20:46:14.550] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C11.dat
[20:46:14.550] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C12.dat
[20:46:14.550] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C13.dat
[20:46:14.550] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C14.dat
[20:46:14.550] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C15.dat
[20:46:14.550] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C0.dat
[20:46:14.557] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C1.dat
[20:46:14.565] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C2.dat
[20:46:14.573] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C3.dat
[20:46:14.581] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C4.dat
[20:46:14.589] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C5.dat
[20:46:14.598] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C6.dat
[20:46:14.607] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C7.dat
[20:46:14.616] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C8.dat
[20:46:14.624] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C9.dat
[20:46:14.633] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C10.dat
[20:46:14.642] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C11.dat
[20:46:14.650] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C12.dat
[20:46:14.659] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C13.dat
[20:46:14.668] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C14.dat
[20:46:14.676] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1094_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C15.dat
[20:46:14.685] <TB1> INFO: PixTestTrim80::trimTest() done
[20:46:14.685] <TB1> INFO: vtrim: 104 102 101 102 94 93 112 96 119 89 109 109 120 89 82 94
[20:46:14.685] <TB1> INFO: vthrcomp: 73 75 72 73 71 69 72 72 70 68 72 75 77 75 67 73
[20:46:14.685] <TB1> INFO: vcal mean: 79.94 79.97 79.94 79.95 79.96 79.94 79.97 79.97 79.95 80.02 79.97 79.98 79.96 79.97 79.97 79.97
[20:46:14.685] <TB1> INFO: vcal RMS: 0.70 0.70 0.77 0.72 0.72 0.74 0.76 0.68 0.94 0.78 0.73 0.72 0.83 0.70 0.73 0.70
[20:46:14.685] <TB1> INFO: bits mean: 9.95 9.90 10.39 9.65 10.92 10.92 10.55 10.04 10.09 10.52 9.81 9.95 9.68 9.31 10.48 9.90
[20:46:14.685] <TB1> INFO: bits RMS: 2.22 2.15 2.14 2.26 2.16 2.22 1.85 2.17 2.55 2.41 2.20 1.98 1.96 2.28 2.35 2.23
[20:46:14.692] <TB1> INFO: ----------------------------------------------------------------------
[20:46:14.692] <TB1> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[20:46:14.692] <TB1> INFO: ----------------------------------------------------------------------
[20:46:14.694] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[20:46:14.707] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[20:46:14.707] <TB1> INFO: run 1 of 1
[20:46:14.947] <TB1> INFO: Expecting 4160000 events.
[20:46:47.625] <TB1> INFO: 756785 events read in total (32087ms).
[20:47:19.461] <TB1> INFO: 1508145 events read in total (63923ms).
[20:47:51.103] <TB1> INFO: 2256770 events read in total (95565ms).
[20:48:22.700] <TB1> INFO: 3000920 events read in total (127162ms).
[20:48:53.855] <TB1> INFO: 3742730 events read in total (158318ms).
[20:49:11.302] <TB1> INFO: 4160000 events read in total (175764ms).
[20:49:11.362] <TB1> INFO: Test took 176655ms.
[20:49:38.336] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[20:49:38.348] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[20:49:38.348] <TB1> INFO: run 1 of 1
[20:49:38.581] <TB1> INFO: Expecting 4264000 events.
[20:50:10.733] <TB1> INFO: 726495 events read in total (31561ms).
[20:50:41.708] <TB1> INFO: 1448285 events read in total (62536ms).
[20:51:12.908] <TB1> INFO: 2167700 events read in total (93736ms).
[20:51:43.728] <TB1> INFO: 2882960 events read in total (124556ms).
[20:52:14.546] <TB1> INFO: 3595690 events read in total (155374ms).
[20:52:43.522] <TB1> INFO: 4264000 events read in total (184350ms).
[20:52:43.579] <TB1> INFO: Test took 185231ms.
[20:53:11.679] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 190 (-1/-1) hits flags = 528 (plus default)
[20:53:11.692] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[20:53:11.692] <TB1> INFO: run 1 of 1
[20:53:11.965] <TB1> INFO: Expecting 3972800 events.
[20:53:44.481] <TB1> INFO: 746690 events read in total (31925ms).
[20:54:15.939] <TB1> INFO: 1488205 events read in total (63383ms).
[20:54:47.318] <TB1> INFO: 2225855 events read in total (94762ms).
[20:55:18.509] <TB1> INFO: 2959095 events read in total (125953ms).
[20:55:49.704] <TB1> INFO: 3690420 events read in total (157148ms).
[20:56:01.851] <TB1> INFO: 3972800 events read in total (169295ms).
[20:56:01.898] <TB1> INFO: Test took 170206ms.
[20:56:29.647] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 189 (-1/-1) hits flags = 528 (plus default)
[20:56:29.656] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[20:56:29.656] <TB1> INFO: run 1 of 1
[20:56:29.888] <TB1> INFO: Expecting 3952000 events.
[20:57:02.470] <TB1> INFO: 748500 events read in total (31990ms).
[20:57:33.542] <TB1> INFO: 1491765 events read in total (63062ms).
[20:58:04.587] <TB1> INFO: 2230770 events read in total (94107ms).
[20:58:35.599] <TB1> INFO: 2965625 events read in total (125120ms).
[20:59:07.235] <TB1> INFO: 3698400 events read in total (156755ms).
[20:59:18.238] <TB1> INFO: 3952000 events read in total (167758ms).
[20:59:18.283] <TB1> INFO: Test took 168627ms.
[20:59:44.364] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 188 (-1/-1) hits flags = 528 (plus default)
[20:59:44.375] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[20:59:44.375] <TB1> INFO: run 1 of 1
[20:59:44.627] <TB1> INFO: Expecting 3931200 events.
[21:00:16.922] <TB1> INFO: 749900 events read in total (31703ms).
[21:00:48.376] <TB1> INFO: 1494630 events read in total (63157ms).
[21:01:19.574] <TB1> INFO: 2234805 events read in total (94356ms).
[21:01:50.507] <TB1> INFO: 2971265 events read in total (125288ms).
[21:02:21.536] <TB1> INFO: 3706005 events read in total (156317ms).
[21:02:31.545] <TB1> INFO: 3931200 events read in total (166326ms).
[21:02:31.589] <TB1> INFO: Test took 167214ms.
[21:02:57.791] <TB1> INFO: PixTestTrim80::trimBitTest() done
[21:02:57.793] <TB1> INFO: PixTestTrim80::doTest() done, duration: 2278 seconds
[21:02:58.428] <TB1> INFO: enter test to run
[21:02:58.428] <TB1> INFO: test: exit no parameter change
[21:02:58.555] <TB1> QUIET: Connection to board 153 closed.
[21:02:58.556] <TB1> INFO: pXar: this is the end, my friend