[11:34:34.499] <TB2> INFO: *** Welcome to pxar ***
[11:34:34.499] <TB2> INFO: *** Today: 2016/10/31
[11:34:34.505] <TB2> INFO: *** Version: c8ba-dirty
[11:34:34.505] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C15.dat
[11:34:34.505] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//tbmParameters_C1b.dat
[11:34:34.505] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//defaultMaskFile.dat
[11:34:34.505] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters_C15.dat
[11:34:34.560] <TB2> INFO: clk: 4
[11:34:34.560] <TB2> INFO: ctr: 4
[11:34:34.560] <TB2> INFO: sda: 19
[11:34:34.560] <TB2> INFO: tin: 9
[11:34:34.560] <TB2> INFO: level: 15
[11:34:34.560] <TB2> INFO: triggerdelay: 0
[11:34:34.560] <TB2> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[11:34:34.560] <TB2> INFO: Log level: INFO
[11:34:34.568] <TB2> INFO: Found DTB DTB_WXC55Z
[11:34:34.579] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[11:34:34.581] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[11:34:34.583] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[11:34:36.124] <TB2> INFO: DUT info:
[11:34:36.124] <TB2> INFO: The DUT currently contains the following objects:
[11:34:36.124] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[11:34:36.124] <TB2> INFO: TBM Core alpha (0): 7 registers set
[11:34:36.124] <TB2> INFO: TBM Core beta (1): 7 registers set
[11:34:36.124] <TB2> INFO: TBM Core alpha (2): 7 registers set
[11:34:36.124] <TB2> INFO: TBM Core beta (3): 7 registers set
[11:34:36.124] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:34:36.124] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.124] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:34:36.525] <TB2> INFO: enter 'restricted' command line mode
[11:34:36.525] <TB2> INFO: enter test to run
[11:34:36.525] <TB2> INFO: test: pretest no parameter change
[11:34:36.525] <TB2> INFO: running: pretest
[11:34:37.094] <TB2> INFO: ######################################################################
[11:34:37.094] <TB2> INFO: PixTestPretest::doTest()
[11:34:37.094] <TB2> INFO: ######################################################################
[11:34:37.095] <TB2> INFO: ----------------------------------------------------------------------
[11:34:37.095] <TB2> INFO: PixTestPretest::programROC()
[11:34:37.095] <TB2> INFO: ----------------------------------------------------------------------
[11:34:55.108] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:34:55.108] <TB2> INFO: IA differences per ROC: 16.9 20.1 20.1 19.3 17.7 17.7 21.7 18.5 19.3 17.7 18.5 19.3 16.9 20.1 19.3 19.3
[11:34:55.145] <TB2> INFO: ----------------------------------------------------------------------
[11:34:55.145] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:34:55.145] <TB2> INFO: ----------------------------------------------------------------------
[11:35:03.332] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 396.3 mA = 24.7688 mA/ROC
[11:35:03.332] <TB2> INFO: i(loss) [mA/ROC]: 20.1 20.1 20.1 20.1 20.1 20.1 20.1 20.1 20.9 20.1 20.1 20.1 20.1 20.1 20.9 20.1
[11:35:03.360] <TB2> INFO: ----------------------------------------------------------------------
[11:35:03.360] <TB2> INFO: PixTestPretest::findTiming()
[11:35:03.360] <TB2> INFO: ----------------------------------------------------------------------
[11:35:03.361] <TB2> INFO: PixTestCmd::init()

[11:35:34.324] <TB2> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:35:34.324] <TB2> INFO: (success/tries = 100/100), width = 4
[11:35:35.833] <TB2> INFO: ----------------------------------------------------------------------
[11:35:35.833] <TB2> INFO: PixTestPretest::findWorkingPixel()
[11:35:35.833] <TB2> INFO: ----------------------------------------------------------------------
[11:35:35.925] <TB2> INFO: Expecting 231680 events.
[11:35:45.556] <TB2> INFO: 231680 events read in total (9039ms).
[11:35:45.564] <TB2> INFO: Test took 9728ms.
[11:35:45.808] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:35:45.838] <TB2> INFO: ----------------------------------------------------------------------
[11:35:45.838] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[11:35:45.838] <TB2> INFO: ----------------------------------------------------------------------
[11:35:45.929] <TB2> INFO: Expecting 231680 events.
[11:35:55.632] <TB2> INFO: 231680 events read in total (9111ms).
[11:35:55.641] <TB2> INFO: Test took 9800ms.
[11:35:55.898] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[11:35:55.898] <TB2> INFO: CalDel: 106 88 87 81 86 92 112 87 89 87 93 111 106 100 108 89
[11:35:55.898] <TB2> INFO: VthrComp: 51 51 51 51 57 51 51 51 51 51 51 51 51 51 51 51
[11:35:55.900] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C0.dat
[11:35:55.901] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C1.dat
[11:35:55.901] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C2.dat
[11:35:55.901] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C3.dat
[11:35:55.901] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C4.dat
[11:35:55.901] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C5.dat
[11:35:55.901] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C6.dat
[11:35:55.901] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C7.dat
[11:35:55.901] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C8.dat
[11:35:55.901] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C9.dat
[11:35:55.901] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C10.dat
[11:35:55.902] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C11.dat
[11:35:55.902] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C12.dat
[11:35:55.902] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C13.dat
[11:35:55.902] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C14.dat
[11:35:55.902] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters_C15.dat
[11:35:55.902] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//tbmParameters_C0a.dat
[11:35:55.902] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//tbmParameters_C0b.dat
[11:35:55.902] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//tbmParameters_C1a.dat
[11:35:55.902] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//tbmParameters_C1b.dat
[11:35:55.902] <TB2> INFO: PixTestPretest::doTest() done, duration: 79 seconds
[11:35:55.000] <TB2> INFO: enter test to run
[11:35:55.000] <TB2> INFO: test: FullTest no parameter change
[11:35:55.000] <TB2> INFO: running: fulltest
[11:35:55.000] <TB2> INFO: ######################################################################
[11:35:55.000] <TB2> INFO: PixTestFullTest::doTest()
[11:35:55.000] <TB2> INFO: ######################################################################
[11:35:55.001] <TB2> INFO: ######################################################################
[11:35:55.001] <TB2> INFO: PixTestAlive::doTest()
[11:35:55.001] <TB2> INFO: ######################################################################
[11:35:55.002] <TB2> INFO: ----------------------------------------------------------------------
[11:35:55.002] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:35:55.002] <TB2> INFO: ----------------------------------------------------------------------
[11:35:56.237] <TB2> INFO: Expecting 41600 events.
[11:35:59.688] <TB2> INFO: 41600 events read in total (2859ms).
[11:35:59.689] <TB2> INFO: Test took 3684ms.
[11:35:59.915] <TB2> INFO: PixTestAlive::aliveTest() done
[11:35:59.915] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:35:59.916] <TB2> INFO: ----------------------------------------------------------------------
[11:35:59.916] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:35:59.916] <TB2> INFO: ----------------------------------------------------------------------
[11:36:00.150] <TB2> INFO: Expecting 41600 events.
[11:36:03.085] <TB2> INFO: 41600 events read in total (2343ms).
[11:36:03.086] <TB2> INFO: Test took 3168ms.
[11:36:03.086] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:36:03.325] <TB2> INFO: PixTestAlive::maskTest() done
[11:36:03.325] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:36:03.327] <TB2> INFO: ----------------------------------------------------------------------
[11:36:03.327] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:36:03.327] <TB2> INFO: ----------------------------------------------------------------------
[11:36:03.605] <TB2> INFO: Expecting 41600 events.
[11:36:07.025] <TB2> INFO: 41600 events read in total (2829ms).
[11:36:07.026] <TB2> INFO: Test took 3698ms.
[11:36:07.251] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[11:36:07.251] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:36:07.251] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:36:07.251] <TB2> INFO: Decoding statistics:
[11:36:07.251] <TB2> INFO: General information:
[11:36:07.251] <TB2> INFO: 16bit words read: 0
[11:36:07.251] <TB2> INFO: valid events total: 0
[11:36:07.251] <TB2> INFO: empty events: 0
[11:36:07.251] <TB2> INFO: valid events with pixels: 0
[11:36:07.251] <TB2> INFO: valid pixel hits: 0
[11:36:07.251] <TB2> INFO: Event errors: 0
[11:36:07.251] <TB2> INFO: start marker: 0
[11:36:07.251] <TB2> INFO: stop marker: 0
[11:36:07.251] <TB2> INFO: overflow: 0
[11:36:07.251] <TB2> INFO: invalid 5bit words: 0
[11:36:07.251] <TB2> INFO: invalid XOR eye diagram: 0
[11:36:07.251] <TB2> INFO: frame (failed synchr.): 0
[11:36:07.251] <TB2> INFO: idle data (no TBM trl): 0
[11:36:07.251] <TB2> INFO: no data (only TBM hdr): 0
[11:36:07.251] <TB2> INFO: TBM errors: 0
[11:36:07.251] <TB2> INFO: flawed TBM headers: 0
[11:36:07.251] <TB2> INFO: flawed TBM trailers: 0
[11:36:07.251] <TB2> INFO: event ID mismatches: 0
[11:36:07.251] <TB2> INFO: ROC errors: 0
[11:36:07.251] <TB2> INFO: missing ROC header(s): 0
[11:36:07.251] <TB2> INFO: misplaced readback start: 0
[11:36:07.251] <TB2> INFO: Pixel decoding errors: 0
[11:36:07.251] <TB2> INFO: pixel data incomplete: 0
[11:36:07.251] <TB2> INFO: pixel address: 0
[11:36:07.251] <TB2> INFO: pulse height fill bit: 0
[11:36:07.251] <TB2> INFO: buffer corruption: 0
[11:36:07.258] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C15.dat
[11:36:07.258] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[11:36:07.258] <TB2> INFO: ######################################################################
[11:36:07.258] <TB2> INFO: PixTestReadback::doTest()
[11:36:07.258] <TB2> INFO: ######################################################################
[11:36:07.258] <TB2> INFO: ----------------------------------------------------------------------
[11:36:07.258] <TB2> INFO: PixTestReadback::CalibrateVd()
[11:36:07.258] <TB2> INFO: ----------------------------------------------------------------------
[11:36:17.229] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C0.dat
[11:36:17.229] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C1.dat
[11:36:17.229] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C2.dat
[11:36:17.229] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C3.dat
[11:36:17.229] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C4.dat
[11:36:17.229] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C5.dat
[11:36:17.230] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C6.dat
[11:36:17.230] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C7.dat
[11:36:17.230] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C8.dat
[11:36:17.230] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C9.dat
[11:36:17.230] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C10.dat
[11:36:17.230] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C11.dat
[11:36:17.230] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C12.dat
[11:36:17.230] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C13.dat
[11:36:17.230] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C14.dat
[11:36:17.230] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C15.dat
[11:36:17.259] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:36:17.259] <TB2> INFO: ----------------------------------------------------------------------
[11:36:17.259] <TB2> INFO: PixTestReadback::CalibrateVa()
[11:36:17.259] <TB2> INFO: ----------------------------------------------------------------------
[11:36:27.151] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C0.dat
[11:36:27.151] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C1.dat
[11:36:27.151] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C2.dat
[11:36:27.151] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C3.dat
[11:36:27.151] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C4.dat
[11:36:27.151] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C5.dat
[11:36:27.151] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C6.dat
[11:36:27.151] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C7.dat
[11:36:27.151] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C8.dat
[11:36:27.151] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C9.dat
[11:36:27.152] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C10.dat
[11:36:27.152] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C11.dat
[11:36:27.152] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C12.dat
[11:36:27.152] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C13.dat
[11:36:27.152] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C14.dat
[11:36:27.152] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C15.dat
[11:36:27.182] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:36:27.182] <TB2> INFO: ----------------------------------------------------------------------
[11:36:27.182] <TB2> INFO: PixTestReadback::readbackVbg()
[11:36:27.182] <TB2> INFO: ----------------------------------------------------------------------
[11:36:34.827] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:36:34.827] <TB2> INFO: ----------------------------------------------------------------------
[11:36:34.827] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[11:36:34.827] <TB2> INFO: ----------------------------------------------------------------------
[11:36:34.827] <TB2> INFO: Vbg will be calibrated using Vd calibration
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 158.8calibrated Vbg = 1.16684 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 161.2calibrated Vbg = 1.1594 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 156.5calibrated Vbg = 1.15147 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 147.4calibrated Vbg = 1.16102 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 161.8calibrated Vbg = 1.15852 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 152.9calibrated Vbg = 1.164 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 151.9calibrated Vbg = 1.1554 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 160calibrated Vbg = 1.16099 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 151.3calibrated Vbg = 1.16945 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 147.4calibrated Vbg = 1.15715 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 142calibrated Vbg = 1.15732 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 145.2calibrated Vbg = 1.14471 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 152.3calibrated Vbg = 1.15616 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 141.8calibrated Vbg = 1.16089 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 152.1calibrated Vbg = 1.15047 :::*/*/*/*/
[11:36:34.827] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 154.4calibrated Vbg = 1.15297 :::*/*/*/*/
[11:36:34.829] <TB2> INFO: ----------------------------------------------------------------------
[11:36:34.829] <TB2> INFO: PixTestReadback::CalibrateIa()
[11:36:34.829] <TB2> INFO: ----------------------------------------------------------------------
[11:39:15.113] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C0.dat
[11:39:15.114] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C1.dat
[11:39:15.114] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C2.dat
[11:39:15.114] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C3.dat
[11:39:15.114] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C4.dat
[11:39:15.114] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C5.dat
[11:39:15.114] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C6.dat
[11:39:15.114] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C7.dat
[11:39:15.114] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C8.dat
[11:39:15.114] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C9.dat
[11:39:15.114] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C10.dat
[11:39:15.114] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C11.dat
[11:39:15.114] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C12.dat
[11:39:15.115] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C13.dat
[11:39:15.115] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C14.dat
[11:39:15.115] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//readbackCal_C15.dat
[11:39:15.142] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:39:15.143] <TB2> INFO: PixTestReadback::doTest() done
[11:39:15.143] <TB2> INFO: Decoding statistics:
[11:39:15.143] <TB2> INFO: General information:
[11:39:15.143] <TB2> INFO: 16bit words read: 1536
[11:39:15.143] <TB2> INFO: valid events total: 256
[11:39:15.143] <TB2> INFO: empty events: 256
[11:39:15.143] <TB2> INFO: valid events with pixels: 0
[11:39:15.143] <TB2> INFO: valid pixel hits: 0
[11:39:15.143] <TB2> INFO: Event errors: 0
[11:39:15.143] <TB2> INFO: start marker: 0
[11:39:15.143] <TB2> INFO: stop marker: 0
[11:39:15.143] <TB2> INFO: overflow: 0
[11:39:15.143] <TB2> INFO: invalid 5bit words: 0
[11:39:15.143] <TB2> INFO: invalid XOR eye diagram: 0
[11:39:15.143] <TB2> INFO: frame (failed synchr.): 0
[11:39:15.143] <TB2> INFO: idle data (no TBM trl): 0
[11:39:15.143] <TB2> INFO: no data (only TBM hdr): 0
[11:39:15.143] <TB2> INFO: TBM errors: 0
[11:39:15.143] <TB2> INFO: flawed TBM headers: 0
[11:39:15.143] <TB2> INFO: flawed TBM trailers: 0
[11:39:15.143] <TB2> INFO: event ID mismatches: 0
[11:39:15.143] <TB2> INFO: ROC errors: 0
[11:39:15.143] <TB2> INFO: missing ROC header(s): 0
[11:39:15.143] <TB2> INFO: misplaced readback start: 0
[11:39:15.143] <TB2> INFO: Pixel decoding errors: 0
[11:39:15.143] <TB2> INFO: pixel data incomplete: 0
[11:39:15.143] <TB2> INFO: pixel address: 0
[11:39:15.143] <TB2> INFO: pulse height fill bit: 0
[11:39:15.143] <TB2> INFO: buffer corruption: 0
[11:39:15.177] <TB2> INFO: ######################################################################
[11:39:15.177] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:39:15.177] <TB2> INFO: ######################################################################
[11:39:15.180] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:39:15.190] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:39:15.190] <TB2> INFO: run 1 of 1
[11:39:15.422] <TB2> INFO: Expecting 3120000 events.
[11:39:46.737] <TB2> INFO: 653395 events read in total (30723ms).











[11:40:16.688] <TB2> INFO: 1299370 events read in total (60674ms).











[11:40:46.984] <TB2> INFO: 1940190 events read in total (90970ms).





















[11:41:16.812] <TB2> INFO: 2579025 events read in total (120798ms).











[11:41:41.896] <TB2> INFO: 3120000 events read in total (145882ms).
[11:41:41.950] <TB2> INFO: Test took 146761ms.
[11:42:03.218] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 168 seconds
[11:42:03.218] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 0 1 1 0 0 0 0 0 2 2 0 13 33
[11:42:03.218] <TB2> INFO: separation cut (per ROC): 95 104 102 103 112 107 103 106 103 110 105 97 92 96 110 96
[11:42:03.218] <TB2> INFO: Decoding statistics:
[11:42:03.218] <TB2> INFO: General information:
[11:42:03.218] <TB2> INFO: 16bit words read: 0
[11:42:03.218] <TB2> INFO: valid events total: 0
[11:42:03.218] <TB2> INFO: empty events: 0
[11:42:03.218] <TB2> INFO: valid events with pixels: 0
[11:42:03.218] <TB2> INFO: valid pixel hits: 0
[11:42:03.218] <TB2> INFO: Event errors: 0
[11:42:03.218] <TB2> INFO: start marker: 0
[11:42:03.218] <TB2> INFO: stop marker: 0
[11:42:03.218] <TB2> INFO: overflow: 0
[11:42:03.218] <TB2> INFO: invalid 5bit words: 0
[11:42:03.218] <TB2> INFO: invalid XOR eye diagram: 0
[11:42:03.218] <TB2> INFO: frame (failed synchr.): 0
[11:42:03.218] <TB2> INFO: idle data (no TBM trl): 0
[11:42:03.218] <TB2> INFO: no data (only TBM hdr): 0
[11:42:03.218] <TB2> INFO: TBM errors: 0
[11:42:03.218] <TB2> INFO: flawed TBM headers: 0
[11:42:03.218] <TB2> INFO: flawed TBM trailers: 0
[11:42:03.218] <TB2> INFO: event ID mismatches: 0
[11:42:03.218] <TB2> INFO: ROC errors: 0
[11:42:03.218] <TB2> INFO: missing ROC header(s): 0
[11:42:03.218] <TB2> INFO: misplaced readback start: 0
[11:42:03.218] <TB2> INFO: Pixel decoding errors: 0
[11:42:03.218] <TB2> INFO: pixel data incomplete: 0
[11:42:03.218] <TB2> INFO: pixel address: 0
[11:42:03.218] <TB2> INFO: pulse height fill bit: 0
[11:42:03.219] <TB2> INFO: buffer corruption: 0
[11:42:03.255] <TB2> INFO: ######################################################################
[11:42:03.255] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:42:03.255] <TB2> INFO: ######################################################################
[11:42:03.255] <TB2> INFO: ----------------------------------------------------------------------
[11:42:03.255] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:42:03.255] <TB2> INFO: ----------------------------------------------------------------------
[11:42:03.255] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[11:42:03.266] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[11:42:03.266] <TB2> INFO: run 1 of 1
[11:42:03.497] <TB2> INFO: Expecting 36608000 events.
[11:42:27.006] <TB2> INFO: 661650 events read in total (22917ms).
[11:42:49.784] <TB2> INFO: 1314750 events read in total (45695ms).
[11:43:12.435] <TB2> INFO: 1966300 events read in total (68346ms).
[11:43:35.587] <TB2> INFO: 2618700 events read in total (91498ms).
[11:43:58.845] <TB2> INFO: 3269850 events read in total (114756ms).
[11:44:21.219] <TB2> INFO: 3921500 events read in total (137130ms).
[11:44:43.869] <TB2> INFO: 4572200 events read in total (159780ms).
[11:45:06.810] <TB2> INFO: 5221300 events read in total (182721ms).
[11:45:29.582] <TB2> INFO: 5870500 events read in total (205493ms).
[11:45:52.537] <TB2> INFO: 6518850 events read in total (228448ms).
[11:46:15.551] <TB2> INFO: 7168300 events read in total (251462ms).
[11:46:38.425] <TB2> INFO: 7816500 events read in total (274336ms).
[11:47:01.592] <TB2> INFO: 8465150 events read in total (297503ms).
[11:47:24.435] <TB2> INFO: 9113400 events read in total (320346ms).
[11:47:47.290] <TB2> INFO: 9763200 events read in total (343201ms).
[11:48:10.151] <TB2> INFO: 10410150 events read in total (366062ms).
[11:48:32.944] <TB2> INFO: 11059900 events read in total (388855ms).
[11:48:55.978] <TB2> INFO: 11709050 events read in total (411889ms).
[11:49:18.902] <TB2> INFO: 12355250 events read in total (434813ms).
[11:49:41.966] <TB2> INFO: 13004550 events read in total (457877ms).
[11:50:04.833] <TB2> INFO: 13652800 events read in total (480744ms).
[11:50:27.777] <TB2> INFO: 14299550 events read in total (503688ms).
[11:50:50.132] <TB2> INFO: 14946850 events read in total (526043ms).
[11:51:12.842] <TB2> INFO: 15593750 events read in total (548753ms).
[11:51:35.990] <TB2> INFO: 16242650 events read in total (571901ms).
[11:51:59.030] <TB2> INFO: 16891500 events read in total (594941ms).
[11:52:22.128] <TB2> INFO: 17535950 events read in total (618039ms).
[11:52:45.031] <TB2> INFO: 18181650 events read in total (640942ms).
[11:53:08.079] <TB2> INFO: 18827850 events read in total (663990ms).
[11:53:30.405] <TB2> INFO: 19473400 events read in total (686316ms).
[11:53:53.044] <TB2> INFO: 20119700 events read in total (708955ms).
[11:54:16.154] <TB2> INFO: 20764500 events read in total (732065ms).
[11:54:39.283] <TB2> INFO: 21409150 events read in total (755194ms).
[11:55:02.223] <TB2> INFO: 22052300 events read in total (778134ms).
[11:55:25.041] <TB2> INFO: 22697600 events read in total (800952ms).
[11:55:47.927] <TB2> INFO: 23344650 events read in total (823838ms).
[11:56:10.856] <TB2> INFO: 23991250 events read in total (846767ms).
[11:56:33.943] <TB2> INFO: 24636700 events read in total (869854ms).
[11:56:56.692] <TB2> INFO: 25280650 events read in total (892603ms).
[11:57:19.475] <TB2> INFO: 25924150 events read in total (915386ms).
[11:57:42.284] <TB2> INFO: 26567450 events read in total (938195ms).
[11:58:04.538] <TB2> INFO: 27211700 events read in total (960449ms).
[11:58:27.125] <TB2> INFO: 27856350 events read in total (983036ms).
[11:58:49.936] <TB2> INFO: 28500500 events read in total (1005847ms).
[11:59:12.784] <TB2> INFO: 29144350 events read in total (1028695ms).
[11:59:35.306] <TB2> INFO: 29791100 events read in total (1051217ms).
[11:59:58.136] <TB2> INFO: 30435250 events read in total (1074047ms).
[12:00:21.112] <TB2> INFO: 31080700 events read in total (1097023ms).
[12:00:43.714] <TB2> INFO: 31724500 events read in total (1119625ms).
[12:01:06.825] <TB2> INFO: 32370650 events read in total (1142736ms).
[12:01:29.707] <TB2> INFO: 33015350 events read in total (1165618ms).
[12:01:52.864] <TB2> INFO: 33664200 events read in total (1188775ms).
[12:02:15.754] <TB2> INFO: 34309450 events read in total (1211665ms).
[12:02:38.888] <TB2> INFO: 34956850 events read in total (1234799ms).
[12:03:01.899] <TB2> INFO: 35605300 events read in total (1257810ms).
[12:03:24.731] <TB2> INFO: 36261500 events read in total (1280642ms).
[12:03:36.427] <TB2> INFO: 36608000 events read in total (1292338ms).
[12:03:36.481] <TB2> INFO: Test took 1293215ms.
[12:03:37.007] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:03:39.103] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:03:41.203] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:03:42.838] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:03:44.569] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:03:46.316] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:03:47.888] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:03:49.518] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:03:51.316] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:03:53.079] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:03:54.711] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:03:56.444] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:03:58.742] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:04:00.519] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:04:01.989] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:04:03.524] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:04:05.021] <TB2> INFO: PixTestScurves::scurves() done
[12:04:05.021] <TB2> INFO: Vcal mean: 103.22 112.30 110.45 113.02 127.86 116.17 119.80 118.57 116.48 122.76 103.37 102.88 103.73 108.02 113.47 111.54
[12:04:05.021] <TB2> INFO: Vcal RMS: 5.08 4.22 4.48 4.91 6.23 5.69 5.19 5.66 5.81 5.59 5.09 5.61 4.94 4.83 4.69 4.77
[12:04:05.021] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1321 seconds
[12:04:05.022] <TB2> INFO: Decoding statistics:
[12:04:05.022] <TB2> INFO: General information:
[12:04:05.022] <TB2> INFO: 16bit words read: 0
[12:04:05.022] <TB2> INFO: valid events total: 0
[12:04:05.022] <TB2> INFO: empty events: 0
[12:04:05.022] <TB2> INFO: valid events with pixels: 0
[12:04:05.022] <TB2> INFO: valid pixel hits: 0
[12:04:05.022] <TB2> INFO: Event errors: 0
[12:04:05.022] <TB2> INFO: start marker: 0
[12:04:05.022] <TB2> INFO: stop marker: 0
[12:04:05.022] <TB2> INFO: overflow: 0
[12:04:05.022] <TB2> INFO: invalid 5bit words: 0
[12:04:05.022] <TB2> INFO: invalid XOR eye diagram: 0
[12:04:05.022] <TB2> INFO: frame (failed synchr.): 0
[12:04:05.022] <TB2> INFO: idle data (no TBM trl): 0
[12:04:05.022] <TB2> INFO: no data (only TBM hdr): 0
[12:04:05.022] <TB2> INFO: TBM errors: 0
[12:04:05.022] <TB2> INFO: flawed TBM headers: 0
[12:04:05.022] <TB2> INFO: flawed TBM trailers: 0
[12:04:05.022] <TB2> INFO: event ID mismatches: 0
[12:04:05.022] <TB2> INFO: ROC errors: 0
[12:04:05.022] <TB2> INFO: missing ROC header(s): 0
[12:04:05.022] <TB2> INFO: misplaced readback start: 0
[12:04:05.022] <TB2> INFO: Pixel decoding errors: 0
[12:04:05.022] <TB2> INFO: pixel data incomplete: 0
[12:04:05.022] <TB2> INFO: pixel address: 0
[12:04:05.022] <TB2> INFO: pulse height fill bit: 0
[12:04:05.022] <TB2> INFO: buffer corruption: 0
[12:04:05.112] <TB2> INFO: ######################################################################
[12:04:05.112] <TB2> INFO: PixTestTrim::doTest()
[12:04:05.112] <TB2> INFO: ######################################################################
[12:04:05.113] <TB2> INFO: ----------------------------------------------------------------------
[12:04:05.113] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:04:05.113] <TB2> INFO: ----------------------------------------------------------------------
[12:04:05.160] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:04:05.160] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:04:05.171] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:04:05.171] <TB2> INFO: run 1 of 1
[12:04:05.404] <TB2> INFO: Expecting 5025280 events.
[12:04:36.132] <TB2> INFO: 809832 events read in total (30132ms).
[12:05:06.342] <TB2> INFO: 1616104 events read in total (60342ms).
[12:05:36.688] <TB2> INFO: 2419920 events read in total (90688ms).
[12:06:06.170] <TB2> INFO: 3219736 events read in total (120170ms).
[12:06:36.397] <TB2> INFO: 4015800 events read in total (150398ms).
[12:07:06.506] <TB2> INFO: 4811448 events read in total (180506ms).
[12:07:14.765] <TB2> INFO: 5025280 events read in total (188765ms).
[12:07:14.821] <TB2> INFO: Test took 189650ms.
[12:07:30.278] <TB2> INFO: ROC 0 VthrComp = 111
[12:07:30.278] <TB2> INFO: ROC 1 VthrComp = 128
[12:07:30.278] <TB2> INFO: ROC 2 VthrComp = 120
[12:07:30.278] <TB2> INFO: ROC 3 VthrComp = 127
[12:07:30.278] <TB2> INFO: ROC 4 VthrComp = 135
[12:07:30.279] <TB2> INFO: ROC 5 VthrComp = 125
[12:07:30.279] <TB2> INFO: ROC 6 VthrComp = 131
[12:07:30.279] <TB2> INFO: ROC 7 VthrComp = 128
[12:07:30.279] <TB2> INFO: ROC 8 VthrComp = 128
[12:07:30.279] <TB2> INFO: ROC 9 VthrComp = 129
[12:07:30.279] <TB2> INFO: ROC 10 VthrComp = 117
[12:07:30.279] <TB2> INFO: ROC 11 VthrComp = 115
[12:07:30.279] <TB2> INFO: ROC 12 VthrComp = 108
[12:07:30.279] <TB2> INFO: ROC 13 VthrComp = 116
[12:07:30.279] <TB2> INFO: ROC 14 VthrComp = 130
[12:07:30.280] <TB2> INFO: ROC 15 VthrComp = 124
[12:07:30.512] <TB2> INFO: Expecting 41600 events.
[12:07:34.188] <TB2> INFO: 41600 events read in total (3084ms).
[12:07:34.188] <TB2> INFO: Test took 3907ms.
[12:07:34.197] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:07:34.197] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:07:34.206] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:07:34.206] <TB2> INFO: run 1 of 1
[12:07:34.484] <TB2> INFO: Expecting 5025280 events.
[12:08:01.090] <TB2> INFO: 586768 events read in total (26015ms).
[12:08:27.030] <TB2> INFO: 1171528 events read in total (51955ms).
[12:08:52.833] <TB2> INFO: 1757152 events read in total (77758ms).
[12:09:18.407] <TB2> INFO: 2342728 events read in total (103332ms).
[12:09:44.769] <TB2> INFO: 2927584 events read in total (129694ms).
[12:10:10.599] <TB2> INFO: 3512248 events read in total (155524ms).
[12:10:36.200] <TB2> INFO: 4095504 events read in total (181125ms).
[12:11:01.933] <TB2> INFO: 4678240 events read in total (206858ms).
[12:11:17.401] <TB2> INFO: 5025280 events read in total (222326ms).
[12:11:17.458] <TB2> INFO: Test took 223252ms.
[12:11:39.663] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 58.3424 for pixel 3/11 mean/min/max = 46.3857/34.4241/58.3473
[12:11:39.663] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 56.422 for pixel 48/10 mean/min/max = 44.4357/32.4311/56.4403
[12:11:39.663] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 58.3332 for pixel 2/79 mean/min/max = 46.0117/33.3842/58.6393
[12:11:39.664] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 58.027 for pixel 4/7 mean/min/max = 44.7942/31.4007/58.1877
[12:11:39.664] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 64.1922 for pixel 11/0 mean/min/max = 49.7775/35.3385/64.2165
[12:11:39.665] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 58.436 for pixel 28/74 mean/min/max = 45.0006/31.4765/58.5247
[12:11:39.665] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 57.8743 for pixel 31/5 mean/min/max = 45.3186/32.6936/57.9437
[12:11:39.665] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 58.5664 for pixel 5/79 mean/min/max = 45.3218/31.8717/58.7719
[12:11:39.666] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 60.5894 for pixel 0/4 mean/min/max = 46.0358/31.3434/60.7281
[12:11:39.666] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 61.732 for pixel 36/4 mean/min/max = 47.1047/32.2601/61.9494
[12:11:39.666] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 55.0121 for pixel 0/9 mean/min/max = 43.7648/32.0711/55.4584
[12:11:39.667] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 57.7493 for pixel 13/78 mean/min/max = 44.6349/31.4976/57.7721
[12:11:39.667] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 59.4982 for pixel 2/39 mean/min/max = 47.3393/34.9455/59.7331
[12:11:39.668] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 58.5228 for pixel 0/21 mean/min/max = 45.4245/32.3173/58.5316
[12:11:39.668] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 55.3784 for pixel 11/8 mean/min/max = 43.9733/31.8585/56.0882
[12:11:39.668] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 57.3801 for pixel 7/76 mean/min/max = 44.7517/31.8156/57.6877
[12:11:39.669] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:11:39.757] <TB2> INFO: Expecting 411648 events.
[12:11:49.291] <TB2> INFO: 411648 events read in total (8942ms).
[12:11:49.298] <TB2> INFO: Expecting 411648 events.
[12:11:58.624] <TB2> INFO: 411648 events read in total (8924ms).
[12:11:58.638] <TB2> INFO: Expecting 411648 events.
[12:12:08.008] <TB2> INFO: 411648 events read in total (8967ms).
[12:12:08.019] <TB2> INFO: Expecting 411648 events.
[12:12:17.425] <TB2> INFO: 411648 events read in total (9003ms).
[12:12:17.439] <TB2> INFO: Expecting 411648 events.
[12:12:26.768] <TB2> INFO: 411648 events read in total (8926ms).
[12:12:26.785] <TB2> INFO: Expecting 411648 events.
[12:12:36.070] <TB2> INFO: 411648 events read in total (8882ms).
[12:12:36.099] <TB2> INFO: Expecting 411648 events.
[12:12:45.510] <TB2> INFO: 411648 events read in total (9008ms).
[12:12:45.533] <TB2> INFO: Expecting 411648 events.
[12:12:54.944] <TB2> INFO: 411648 events read in total (9008ms).
[12:12:54.969] <TB2> INFO: Expecting 411648 events.
[12:13:04.322] <TB2> INFO: 411648 events read in total (8950ms).
[12:13:04.363] <TB2> INFO: Expecting 411648 events.
[12:13:13.772] <TB2> INFO: 411648 events read in total (9006ms).
[12:13:13.817] <TB2> INFO: Expecting 411648 events.
[12:13:23.204] <TB2> INFO: 411648 events read in total (8984ms).
[12:13:23.253] <TB2> INFO: Expecting 411648 events.
[12:13:32.665] <TB2> INFO: 411648 events read in total (9009ms).
[12:13:32.702] <TB2> INFO: Expecting 411648 events.
[12:13:42.121] <TB2> INFO: 411648 events read in total (9016ms).
[12:13:42.162] <TB2> INFO: Expecting 411648 events.
[12:13:51.503] <TB2> INFO: 411648 events read in total (8939ms).
[12:13:51.546] <TB2> INFO: Expecting 411648 events.
[12:14:00.974] <TB2> INFO: 411648 events read in total (9025ms).
[12:14:01.044] <TB2> INFO: Expecting 411648 events.
[12:14:10.487] <TB2> INFO: 411648 events read in total (9040ms).
[12:14:10.536] <TB2> INFO: Test took 150867ms.
[12:14:11.326] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:14:11.336] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:14:11.336] <TB2> INFO: run 1 of 1
[12:14:11.567] <TB2> INFO: Expecting 5025280 events.
[12:14:38.268] <TB2> INFO: 583304 events read in total (26109ms).
[12:15:04.627] <TB2> INFO: 1166080 events read in total (52468ms).
[12:15:30.792] <TB2> INFO: 1748456 events read in total (78633ms).
[12:15:56.618] <TB2> INFO: 2329768 events read in total (104459ms).
[12:16:23.087] <TB2> INFO: 2908856 events read in total (130928ms).
[12:16:49.209] <TB2> INFO: 3489040 events read in total (157050ms).
[12:17:15.150] <TB2> INFO: 4067904 events read in total (182991ms).
[12:17:40.871] <TB2> INFO: 4647480 events read in total (208712ms).
[12:17:57.919] <TB2> INFO: 5025280 events read in total (225760ms).
[12:17:58.040] <TB2> INFO: Test took 226705ms.
[12:18:18.470] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 1.611782 .. 146.664768
[12:18:18.704] <TB2> INFO: Expecting 208000 events.
[12:18:28.589] <TB2> INFO: 208000 events read in total (9293ms).
[12:18:28.589] <TB2> INFO: Test took 10118ms.
[12:18:28.634] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 156 (-1/-1) hits flags = 528 (plus default)
[12:18:28.644] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:18:28.644] <TB2> INFO: run 1 of 1
[12:18:28.922] <TB2> INFO: Expecting 5191680 events.
[12:18:55.161] <TB2> INFO: 584088 events read in total (25647ms).
[12:19:21.495] <TB2> INFO: 1167376 events read in total (51981ms).
[12:19:47.800] <TB2> INFO: 1750912 events read in total (78286ms).
[12:20:13.721] <TB2> INFO: 2334480 events read in total (104207ms).
[12:20:40.215] <TB2> INFO: 2917656 events read in total (130701ms).
[12:21:06.191] <TB2> INFO: 3500464 events read in total (156677ms).
[12:21:32.206] <TB2> INFO: 4083104 events read in total (182692ms).
[12:21:58.026] <TB2> INFO: 4665008 events read in total (208512ms).
[12:22:21.553] <TB2> INFO: 5191680 events read in total (232039ms).
[12:22:21.641] <TB2> INFO: Test took 232996ms.
[12:22:44.472] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.750051 .. 45.145673
[12:22:44.704] <TB2> INFO: Expecting 208000 events.
[12:22:54.675] <TB2> INFO: 208000 events read in total (9379ms).
[12:22:54.676] <TB2> INFO: Test took 10203ms.
[12:22:54.721] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:22:54.731] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:22:54.731] <TB2> INFO: run 1 of 1
[12:22:55.022] <TB2> INFO: Expecting 1297920 events.
[12:23:23.604] <TB2> INFO: 658424 events read in total (27990ms).
[12:23:51.584] <TB2> INFO: 1297920 events read in total (55970ms).
[12:23:51.621] <TB2> INFO: Test took 56891ms.
[12:24:03.033] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 25.112345 .. 44.322352
[12:24:03.321] <TB2> INFO: Expecting 208000 events.
[12:24:13.109] <TB2> INFO: 208000 events read in total (9196ms).
[12:24:13.110] <TB2> INFO: Test took 10076ms.
[12:24:13.156] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 54 (-1/-1) hits flags = 528 (plus default)
[12:24:13.166] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:24:13.166] <TB2> INFO: run 1 of 1
[12:24:13.444] <TB2> INFO: Expecting 1331200 events.
[12:24:41.791] <TB2> INFO: 671688 events read in total (27756ms).
[12:25:09.446] <TB2> INFO: 1331200 events read in total (55411ms).
[12:25:09.476] <TB2> INFO: Test took 56311ms.
[12:25:20.707] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 22.763135 .. 41.505520
[12:25:20.940] <TB2> INFO: Expecting 208000 events.
[12:25:30.971] <TB2> INFO: 208000 events read in total (9439ms).
[12:25:30.972] <TB2> INFO: Test took 10263ms.
[12:25:31.052] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 12 .. 51 (-1/-1) hits flags = 528 (plus default)
[12:25:31.064] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:25:31.064] <TB2> INFO: run 1 of 1
[12:25:31.356] <TB2> INFO: Expecting 1331200 events.
[12:26:00.682] <TB2> INFO: 698048 events read in total (28735ms).
[12:26:26.575] <TB2> INFO: 1331200 events read in total (54628ms).
[12:26:26.599] <TB2> INFO: Test took 55536ms.
[12:26:36.002] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:26:36.002] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:26:37.013] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:26:37.013] <TB2> INFO: run 1 of 1
[12:26:37.243] <TB2> INFO: Expecting 1364480 events.
[12:27:05.899] <TB2> INFO: 667480 events read in total (28064ms).
[12:27:34.151] <TB2> INFO: 1334088 events read in total (56316ms).
[12:27:35.792] <TB2> INFO: 1364480 events read in total (57957ms).
[12:27:35.814] <TB2> INFO: Test took 58802ms.
[12:27:46.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C0.dat
[12:27:46.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C1.dat
[12:27:46.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C2.dat
[12:27:46.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C3.dat
[12:27:46.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C4.dat
[12:27:46.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C5.dat
[12:27:46.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C6.dat
[12:27:46.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C7.dat
[12:27:46.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C8.dat
[12:27:46.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C9.dat
[12:27:46.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C10.dat
[12:27:46.673] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C11.dat
[12:27:46.673] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C12.dat
[12:27:46.673] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C13.dat
[12:27:46.673] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C14.dat
[12:27:46.673] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C15.dat
[12:27:46.673] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C0.dat
[12:27:46.678] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C1.dat
[12:27:46.684] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C2.dat
[12:27:46.689] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C3.dat
[12:27:46.694] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C4.dat
[12:27:46.699] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C5.dat
[12:27:46.705] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C6.dat
[12:27:46.710] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C7.dat
[12:27:46.715] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C8.dat
[12:27:46.721] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C9.dat
[12:27:46.726] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C10.dat
[12:27:46.731] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C11.dat
[12:27:46.737] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C12.dat
[12:27:46.742] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C13.dat
[12:27:46.750] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C14.dat
[12:27:46.757] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//trimParameters35_C15.dat
[12:27:46.765] <TB2> INFO: PixTestTrim::trimTest() done
[12:27:46.765] <TB2> INFO: vtrim: 131 138 142 138 163 147 145 151 154 162 145 134 135 130 134 133
[12:27:46.765] <TB2> INFO: vthrcomp: 111 128 120 127 135 125 131 128 128 129 117 115 108 116 130 124
[12:27:46.765] <TB2> INFO: vcal mean: 34.98 34.95 34.96 34.99 35.03 34.95 34.96 34.94 34.97 35.00 35.00 35.00 34.99 34.91 34.95 34.96
[12:27:46.765] <TB2> INFO: vcal RMS: 0.92 1.00 0.94 1.09 1.14 1.08 0.99 1.08 1.11 1.07 0.95 0.94 0.96 1.00 1.01 0.98
[12:27:46.765] <TB2> INFO: bits mean: 9.31 10.47 9.19 10.00 8.89 10.32 9.84 10.35 9.51 9.87 10.35 9.86 8.83 9.48 10.42 9.53
[12:27:46.765] <TB2> INFO: bits RMS: 2.40 2.25 2.64 2.62 2.26 2.45 2.48 2.35 2.78 2.45 2.37 2.69 2.50 2.70 2.35 2.78
[12:27:46.772] <TB2> INFO: ----------------------------------------------------------------------
[12:27:46.772] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:27:46.772] <TB2> INFO: ----------------------------------------------------------------------
[12:27:46.775] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:27:46.784] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:27:46.784] <TB2> INFO: run 1 of 1
[12:27:47.016] <TB2> INFO: Expecting 4160000 events.
[12:28:18.919] <TB2> INFO: 728330 events read in total (31312ms).
[12:28:50.219] <TB2> INFO: 1450890 events read in total (62612ms).
[12:29:22.018] <TB2> INFO: 2170755 events read in total (94411ms).
[12:29:53.571] <TB2> INFO: 2887490 events read in total (125964ms).
[12:30:25.381] <TB2> INFO: 3601785 events read in total (157774ms).
[12:30:49.804] <TB2> INFO: 4160000 events read in total (182197ms).
[12:30:49.856] <TB2> INFO: Test took 183072ms.
[12:31:13.293] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[12:31:13.303] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:31:13.303] <TB2> INFO: run 1 of 1
[12:31:13.555] <TB2> INFO: Expecting 4264000 events.
[12:31:45.070] <TB2> INFO: 700420 events read in total (30923ms).
[12:32:16.607] <TB2> INFO: 1396545 events read in total (62460ms).
[12:32:47.475] <TB2> INFO: 2090405 events read in total (93328ms).
[12:33:18.413] <TB2> INFO: 2782300 events read in total (124266ms).
[12:33:48.954] <TB2> INFO: 3472575 events read in total (154807ms).
[12:34:20.026] <TB2> INFO: 4164730 events read in total (185879ms).
[12:34:24.755] <TB2> INFO: 4264000 events read in total (190608ms).
[12:34:24.812] <TB2> INFO: Test took 191508ms.
[12:34:50.192] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[12:34:50.202] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:34:50.202] <TB2> INFO: run 1 of 1
[12:34:50.439] <TB2> INFO: Expecting 4139200 events.
[12:35:22.033] <TB2> INFO: 707185 events read in total (31002ms).
[12:35:53.210] <TB2> INFO: 1409755 events read in total (62179ms).
[12:36:24.529] <TB2> INFO: 2110475 events read in total (93498ms).
[12:36:55.434] <TB2> INFO: 2808915 events read in total (124403ms).
[12:37:26.270] <TB2> INFO: 3506075 events read in total (155239ms).
[12:37:54.690] <TB2> INFO: 4139200 events read in total (183659ms).
[12:37:54.765] <TB2> INFO: Test took 184563ms.
[12:38:21.283] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[12:38:21.295] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:38:21.295] <TB2> INFO: run 1 of 1
[12:38:21.548] <TB2> INFO: Expecting 4139200 events.
[12:38:53.028] <TB2> INFO: 707485 events read in total (30888ms).
[12:39:23.963] <TB2> INFO: 1410335 events read in total (61823ms).
[12:39:54.862] <TB2> INFO: 2111200 events read in total (92722ms).
[12:40:25.946] <TB2> INFO: 2809885 events read in total (123806ms).
[12:40:57.324] <TB2> INFO: 3507325 events read in total (155184ms).
[12:41:24.864] <TB2> INFO: 4139200 events read in total (182724ms).
[12:41:24.943] <TB2> INFO: Test took 183648ms.
[12:41:48.827] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[12:41:48.839] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:41:48.839] <TB2> INFO: run 1 of 1
[12:41:49.071] <TB2> INFO: Expecting 4139200 events.
[12:42:20.572] <TB2> INFO: 707735 events read in total (30910ms).
[12:42:51.895] <TB2> INFO: 1410705 events read in total (62233ms).
[12:43:23.200] <TB2> INFO: 2112015 events read in total (93538ms).
[12:43:53.892] <TB2> INFO: 2810795 events read in total (124230ms).
[12:44:24.849] <TB2> INFO: 3508455 events read in total (155187ms).
[12:44:52.896] <TB2> INFO: 4139200 events read in total (183234ms).
[12:44:52.971] <TB2> INFO: Test took 184132ms.
[12:45:17.020] <TB2> INFO: PixTestTrim::trimBitTest() done
[12:45:17.022] <TB2> INFO: PixTestTrim::doTest() done, duration: 2471 seconds
[12:45:17.022] <TB2> INFO: Decoding statistics:
[12:45:17.022] <TB2> INFO: General information:
[12:45:17.022] <TB2> INFO: 16bit words read: 0
[12:45:17.022] <TB2> INFO: valid events total: 0
[12:45:17.022] <TB2> INFO: empty events: 0
[12:45:17.022] <TB2> INFO: valid events with pixels: 0
[12:45:17.022] <TB2> INFO: valid pixel hits: 0
[12:45:17.022] <TB2> INFO: Event errors: 0
[12:45:17.022] <TB2> INFO: start marker: 0
[12:45:17.022] <TB2> INFO: stop marker: 0
[12:45:17.022] <TB2> INFO: overflow: 0
[12:45:17.022] <TB2> INFO: invalid 5bit words: 0
[12:45:17.022] <TB2> INFO: invalid XOR eye diagram: 0
[12:45:17.022] <TB2> INFO: frame (failed synchr.): 0
[12:45:17.022] <TB2> INFO: idle data (no TBM trl): 0
[12:45:17.022] <TB2> INFO: no data (only TBM hdr): 0
[12:45:17.022] <TB2> INFO: TBM errors: 0
[12:45:17.022] <TB2> INFO: flawed TBM headers: 0
[12:45:17.022] <TB2> INFO: flawed TBM trailers: 0
[12:45:17.022] <TB2> INFO: event ID mismatches: 0
[12:45:17.022] <TB2> INFO: ROC errors: 0
[12:45:17.022] <TB2> INFO: missing ROC header(s): 0
[12:45:17.022] <TB2> INFO: misplaced readback start: 0
[12:45:17.022] <TB2> INFO: Pixel decoding errors: 0
[12:45:17.022] <TB2> INFO: pixel data incomplete: 0
[12:45:17.022] <TB2> INFO: pixel address: 0
[12:45:17.022] <TB2> INFO: pulse height fill bit: 0
[12:45:17.022] <TB2> INFO: buffer corruption: 0
[12:45:17.743] <TB2> INFO: ######################################################################
[12:45:17.743] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:45:17.743] <TB2> INFO: ######################################################################
[12:45:17.981] <TB2> INFO: Expecting 41600 events.
[12:45:21.509] <TB2> INFO: 41600 events read in total (2937ms).
[12:45:21.510] <TB2> INFO: Test took 3766ms.
[12:45:21.946] <TB2> INFO: Expecting 41600 events.
[12:45:25.430] <TB2> INFO: 41600 events read in total (2892ms).
[12:45:25.430] <TB2> INFO: Test took 3717ms.
[12:45:25.719] <TB2> INFO: Expecting 41600 events.
[12:45:29.203] <TB2> INFO: 41600 events read in total (2893ms).
[12:45:29.204] <TB2> INFO: Test took 3750ms.
[12:45:29.492] <TB2> INFO: Expecting 41600 events.
[12:45:32.995] <TB2> INFO: 41600 events read in total (2912ms).
[12:45:32.995] <TB2> INFO: Test took 3768ms.
[12:45:33.305] <TB2> INFO: Expecting 41600 events.
[12:45:36.893] <TB2> INFO: 41600 events read in total (2997ms).
[12:45:36.894] <TB2> INFO: Test took 3875ms.
[12:45:37.185] <TB2> INFO: Expecting 41600 events.
[12:45:40.768] <TB2> INFO: 41600 events read in total (2991ms).
[12:45:40.769] <TB2> INFO: Test took 3849ms.
[12:45:41.057] <TB2> INFO: Expecting 41600 events.
[12:45:44.522] <TB2> INFO: 41600 events read in total (2873ms).
[12:45:44.523] <TB2> INFO: Test took 3730ms.
[12:45:44.814] <TB2> INFO: Expecting 41600 events.
[12:45:48.365] <TB2> INFO: 41600 events read in total (2959ms).
[12:45:48.366] <TB2> INFO: Test took 3816ms.
[12:45:48.657] <TB2> INFO: Expecting 41600 events.
[12:45:52.262] <TB2> INFO: 41600 events read in total (3013ms).
[12:45:52.263] <TB2> INFO: Test took 3870ms.
[12:45:52.551] <TB2> INFO: Expecting 41600 events.
[12:45:56.251] <TB2> INFO: 41600 events read in total (3108ms).
[12:45:56.252] <TB2> INFO: Test took 3966ms.
[12:45:56.540] <TB2> INFO: Expecting 41600 events.
[12:46:00.008] <TB2> INFO: 41600 events read in total (2877ms).
[12:46:00.009] <TB2> INFO: Test took 3734ms.
[12:46:00.297] <TB2> INFO: Expecting 41600 events.
[12:46:03.797] <TB2> INFO: 41600 events read in total (2909ms).
[12:46:03.798] <TB2> INFO: Test took 3766ms.
[12:46:04.089] <TB2> INFO: Expecting 41600 events.
[12:46:07.562] <TB2> INFO: 41600 events read in total (2881ms).
[12:46:07.563] <TB2> INFO: Test took 3738ms.
[12:46:07.884] <TB2> INFO: Expecting 41600 events.
[12:46:11.489] <TB2> INFO: 41600 events read in total (3013ms).
[12:46:11.490] <TB2> INFO: Test took 3900ms.
[12:46:11.812] <TB2> INFO: Expecting 41600 events.
[12:46:15.406] <TB2> INFO: 41600 events read in total (3002ms).
[12:46:15.406] <TB2> INFO: Test took 3889ms.
[12:46:15.694] <TB2> INFO: Expecting 41600 events.
[12:46:19.432] <TB2> INFO: 41600 events read in total (3146ms).
[12:46:19.433] <TB2> INFO: Test took 4003ms.
[12:46:19.721] <TB2> INFO: Expecting 41600 events.
[12:46:23.279] <TB2> INFO: 41600 events read in total (2967ms).
[12:46:23.280] <TB2> INFO: Test took 3824ms.
[12:46:23.567] <TB2> INFO: Expecting 41600 events.
[12:46:27.176] <TB2> INFO: 41600 events read in total (3017ms).
[12:46:27.176] <TB2> INFO: Test took 3873ms.
[12:46:27.465] <TB2> INFO: Expecting 41600 events.
[12:46:30.972] <TB2> INFO: 41600 events read in total (2916ms).
[12:46:30.973] <TB2> INFO: Test took 3773ms.
[12:46:31.289] <TB2> INFO: Expecting 41600 events.
[12:46:35.021] <TB2> INFO: 41600 events read in total (3140ms).
[12:46:35.022] <TB2> INFO: Test took 4026ms.
[12:46:35.313] <TB2> INFO: Expecting 41600 events.
[12:46:38.898] <TB2> INFO: 41600 events read in total (2993ms).
[12:46:38.898] <TB2> INFO: Test took 3849ms.
[12:46:39.212] <TB2> INFO: Expecting 41600 events.
[12:46:42.815] <TB2> INFO: 41600 events read in total (3011ms).
[12:46:42.815] <TB2> INFO: Test took 3893ms.
[12:46:43.133] <TB2> INFO: Expecting 41600 events.
[12:46:46.696] <TB2> INFO: 41600 events read in total (2971ms).
[12:46:46.697] <TB2> INFO: Test took 3858ms.
[12:46:46.989] <TB2> INFO: Expecting 41600 events.
[12:46:50.710] <TB2> INFO: 41600 events read in total (3130ms).
[12:46:50.711] <TB2> INFO: Test took 3987ms.
[12:46:50.999] <TB2> INFO: Expecting 41600 events.
[12:46:54.622] <TB2> INFO: 41600 events read in total (3031ms).
[12:46:54.623] <TB2> INFO: Test took 3888ms.
[12:46:54.914] <TB2> INFO: Expecting 41600 events.
[12:46:58.600] <TB2> INFO: 41600 events read in total (3094ms).
[12:46:58.601] <TB2> INFO: Test took 3951ms.
[12:46:58.889] <TB2> INFO: Expecting 41600 events.
[12:47:02.416] <TB2> INFO: 41600 events read in total (2935ms).
[12:47:02.416] <TB2> INFO: Test took 3792ms.
[12:47:02.704] <TB2> INFO: Expecting 41600 events.
[12:47:06.200] <TB2> INFO: 41600 events read in total (2904ms).
[12:47:06.201] <TB2> INFO: Test took 3761ms.
[12:47:06.489] <TB2> INFO: Expecting 41600 events.
[12:47:10.011] <TB2> INFO: 41600 events read in total (2931ms).
[12:47:10.011] <TB2> INFO: Test took 3787ms.
[12:47:10.299] <TB2> INFO: Expecting 41600 events.
[12:47:13.879] <TB2> INFO: 41600 events read in total (2988ms).
[12:47:13.879] <TB2> INFO: Test took 3844ms.
[12:47:14.167] <TB2> INFO: Expecting 41600 events.
[12:47:17.796] <TB2> INFO: 41600 events read in total (3037ms).
[12:47:17.797] <TB2> INFO: Test took 3894ms.
[12:47:18.088] <TB2> INFO: Expecting 41600 events.
[12:47:21.718] <TB2> INFO: 41600 events read in total (3038ms).
[12:47:21.719] <TB2> INFO: Test took 3895ms.
[12:47:22.038] <TB2> INFO: Expecting 41600 events.
[12:47:25.614] <TB2> INFO: 41600 events read in total (2985ms).
[12:47:25.615] <TB2> INFO: Test took 3869ms.
[12:47:25.907] <TB2> INFO: Expecting 41600 events.
[12:47:29.456] <TB2> INFO: 41600 events read in total (2958ms).
[12:47:29.457] <TB2> INFO: Test took 3815ms.
[12:47:29.745] <TB2> INFO: Expecting 41600 events.
[12:47:33.450] <TB2> INFO: 41600 events read in total (3114ms).
[12:47:33.450] <TB2> INFO: Test took 3970ms.
[12:47:33.738] <TB2> INFO: Expecting 41600 events.
[12:47:37.246] <TB2> INFO: 41600 events read in total (2916ms).
[12:47:37.247] <TB2> INFO: Test took 3774ms.
[12:47:37.538] <TB2> INFO: Expecting 41600 events.
[12:47:41.225] <TB2> INFO: 41600 events read in total (3096ms).
[12:47:41.226] <TB2> INFO: Test took 3952ms.
[12:47:41.546] <TB2> INFO: Expecting 41600 events.
[12:47:45.303] <TB2> INFO: 41600 events read in total (3165ms).
[12:47:45.304] <TB2> INFO: Test took 4050ms.
[12:47:45.625] <TB2> INFO: Expecting 41600 events.
[12:47:49.094] <TB2> INFO: 41600 events read in total (2877ms).
[12:47:49.095] <TB2> INFO: Test took 3764ms.
[12:47:49.416] <TB2> INFO: Expecting 41600 events.
[12:47:52.925] <TB2> INFO: 41600 events read in total (2917ms).
[12:47:52.926] <TB2> INFO: Test took 3804ms.
[12:47:53.216] <TB2> INFO: Expecting 41600 events.
[12:47:56.747] <TB2> INFO: 41600 events read in total (2939ms).
[12:47:56.747] <TB2> INFO: Test took 3796ms.
[12:47:57.070] <TB2> INFO: Expecting 41600 events.
[12:48:00.582] <TB2> INFO: 41600 events read in total (2921ms).
[12:48:00.583] <TB2> INFO: Test took 3808ms.
[12:48:00.874] <TB2> INFO: Expecting 41600 events.
[12:48:04.549] <TB2> INFO: 41600 events read in total (3083ms).
[12:48:04.550] <TB2> INFO: Test took 3940ms.
[12:48:04.838] <TB2> INFO: Expecting 41600 events.
[12:48:08.426] <TB2> INFO: 41600 events read in total (2996ms).
[12:48:08.426] <TB2> INFO: Test took 3853ms.
[12:48:08.741] <TB2> INFO: Expecting 41600 events.
[12:48:12.190] <TB2> INFO: 41600 events read in total (2857ms).
[12:48:12.191] <TB2> INFO: Test took 3741ms.
[12:48:12.482] <TB2> INFO: Expecting 41600 events.
[12:48:15.951] <TB2> INFO: 41600 events read in total (2877ms).
[12:48:15.952] <TB2> INFO: Test took 3734ms.
[12:48:16.240] <TB2> INFO: Expecting 41600 events.
[12:48:19.790] <TB2> INFO: 41600 events read in total (2958ms).
[12:48:19.791] <TB2> INFO: Test took 3815ms.
[12:48:20.079] <TB2> INFO: Expecting 41600 events.
[12:48:23.708] <TB2> INFO: 41600 events read in total (3038ms).
[12:48:23.709] <TB2> INFO: Test took 3895ms.
[12:48:23.000] <TB2> INFO: Expecting 41600 events.
[12:48:27.453] <TB2> INFO: 41600 events read in total (2861ms).
[12:48:27.454] <TB2> INFO: Test took 3719ms.
[12:48:27.742] <TB2> INFO: Expecting 41600 events.
[12:48:31.523] <TB2> INFO: 41600 events read in total (3189ms).
[12:48:31.524] <TB2> INFO: Test took 4046ms.
[12:48:31.812] <TB2> INFO: Expecting 41600 events.
[12:48:35.333] <TB2> INFO: 41600 events read in total (2930ms).
[12:48:35.334] <TB2> INFO: Test took 3787ms.
[12:48:35.626] <TB2> INFO: Expecting 41600 events.
[12:48:39.095] <TB2> INFO: 41600 events read in total (2877ms).
[12:48:39.095] <TB2> INFO: Test took 3734ms.
[12:48:39.383] <TB2> INFO: Expecting 41600 events.
[12:48:42.981] <TB2> INFO: 41600 events read in total (3006ms).
[12:48:42.981] <TB2> INFO: Test took 3862ms.
[12:48:43.276] <TB2> INFO: Expecting 41600 events.
[12:48:46.941] <TB2> INFO: 41600 events read in total (3074ms).
[12:48:46.942] <TB2> INFO: Test took 3931ms.
[12:48:47.235] <TB2> INFO: Expecting 2560 events.
[12:48:48.119] <TB2> INFO: 2560 events read in total (292ms).
[12:48:48.119] <TB2> INFO: Test took 1161ms.
[12:48:48.427] <TB2> INFO: Expecting 2560 events.
[12:48:49.309] <TB2> INFO: 2560 events read in total (291ms).
[12:48:49.310] <TB2> INFO: Test took 1190ms.
[12:48:49.618] <TB2> INFO: Expecting 2560 events.
[12:48:50.503] <TB2> INFO: 2560 events read in total (294ms).
[12:48:50.504] <TB2> INFO: Test took 1194ms.
[12:48:50.811] <TB2> INFO: Expecting 2560 events.
[12:48:51.699] <TB2> INFO: 2560 events read in total (296ms).
[12:48:51.699] <TB2> INFO: Test took 1195ms.
[12:48:52.007] <TB2> INFO: Expecting 2560 events.
[12:48:52.888] <TB2> INFO: 2560 events read in total (289ms).
[12:48:52.889] <TB2> INFO: Test took 1190ms.
[12:48:53.197] <TB2> INFO: Expecting 2560 events.
[12:48:54.080] <TB2> INFO: 2560 events read in total (292ms).
[12:48:54.080] <TB2> INFO: Test took 1191ms.
[12:48:54.388] <TB2> INFO: Expecting 2560 events.
[12:48:55.271] <TB2> INFO: 2560 events read in total (291ms).
[12:48:55.271] <TB2> INFO: Test took 1190ms.
[12:48:55.579] <TB2> INFO: Expecting 2560 events.
[12:48:56.458] <TB2> INFO: 2560 events read in total (287ms).
[12:48:56.458] <TB2> INFO: Test took 1186ms.
[12:48:56.766] <TB2> INFO: Expecting 2560 events.
[12:48:57.648] <TB2> INFO: 2560 events read in total (290ms).
[12:48:57.649] <TB2> INFO: Test took 1190ms.
[12:48:57.957] <TB2> INFO: Expecting 2560 events.
[12:48:58.836] <TB2> INFO: 2560 events read in total (288ms).
[12:48:58.837] <TB2> INFO: Test took 1188ms.
[12:48:59.144] <TB2> INFO: Expecting 2560 events.
[12:49:00.024] <TB2> INFO: 2560 events read in total (288ms).
[12:49:00.024] <TB2> INFO: Test took 1187ms.
[12:49:00.332] <TB2> INFO: Expecting 2560 events.
[12:49:01.215] <TB2> INFO: 2560 events read in total (291ms).
[12:49:01.216] <TB2> INFO: Test took 1192ms.
[12:49:01.523] <TB2> INFO: Expecting 2560 events.
[12:49:02.407] <TB2> INFO: 2560 events read in total (292ms).
[12:49:02.407] <TB2> INFO: Test took 1191ms.
[12:49:02.715] <TB2> INFO: Expecting 2560 events.
[12:49:03.603] <TB2> INFO: 2560 events read in total (296ms).
[12:49:03.603] <TB2> INFO: Test took 1196ms.
[12:49:03.911] <TB2> INFO: Expecting 2560 events.
[12:49:04.800] <TB2> INFO: 2560 events read in total (297ms).
[12:49:04.800] <TB2> INFO: Test took 1197ms.
[12:49:05.108] <TB2> INFO: Expecting 2560 events.
[12:49:05.995] <TB2> INFO: 2560 events read in total (295ms).
[12:49:05.996] <TB2> INFO: Test took 1195ms.
[12:49:06.305] <TB2> INFO: Expecting 655360 events.
[12:49:27.312] <TB2> INFO: 531260 events read in total (20416ms).
[12:49:32.448] <TB2> INFO: 655360 events read in total (25552ms).
[12:49:32.466] <TB2> INFO: Test took 26468ms.
[12:49:32.489] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:32.754] <TB2> INFO: Expecting 655360 events.
[12:49:47.290] <TB2> INFO: 655360 events read in total (13944ms).
[12:49:47.300] <TB2> INFO: Expecting 655360 events.
[12:50:01.763] <TB2> INFO: 655360 events read in total (14060ms).
[12:50:01.783] <TB2> INFO: Expecting 655360 events.
[12:50:16.234] <TB2> INFO: 655360 events read in total (14048ms).
[12:50:16.253] <TB2> INFO: Expecting 655360 events.
[12:50:30.769] <TB2> INFO: 655360 events read in total (14113ms).
[12:50:30.801] <TB2> INFO: Expecting 655360 events.
[12:50:45.008] <TB2> INFO: 655360 events read in total (13804ms).
[12:50:45.034] <TB2> INFO: Expecting 655360 events.
[12:50:59.231] <TB2> INFO: 655360 events read in total (13794ms).
[12:50:59.275] <TB2> INFO: Expecting 655360 events.
[12:51:13.844] <TB2> INFO: 655360 events read in total (14166ms).
[12:51:13.892] <TB2> INFO: Expecting 655360 events.
[12:51:28.275] <TB2> INFO: 655360 events read in total (13980ms).
[12:51:28.314] <TB2> INFO: Expecting 655360 events.
[12:51:42.694] <TB2> INFO: 655360 events read in total (13977ms).
[12:51:42.761] <TB2> INFO: Expecting 655360 events.
[12:51:57.125] <TB2> INFO: 655360 events read in total (13961ms).
[12:51:57.171] <TB2> INFO: Expecting 655360 events.
[12:52:11.837] <TB2> INFO: 655360 events read in total (14263ms).
[12:52:11.898] <TB2> INFO: Expecting 655360 events.
[12:52:26.353] <TB2> INFO: 655360 events read in total (14052ms).
[12:52:26.408] <TB2> INFO: Expecting 655360 events.
[12:52:40.825] <TB2> INFO: 655360 events read in total (14014ms).
[12:52:40.886] <TB2> INFO: Expecting 655360 events.
[12:52:55.150] <TB2> INFO: 655360 events read in total (13861ms).
[12:52:55.214] <TB2> INFO: Expecting 655360 events.
[12:53:09.639] <TB2> INFO: 655360 events read in total (14022ms).
[12:53:09.707] <TB2> INFO: Expecting 655360 events.
[12:53:23.877] <TB2> INFO: 655360 events read in total (13767ms).
[12:53:23.952] <TB2> INFO: Test took 231463ms.
[12:53:24.106] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.110] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.115] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.119] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.124] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.128] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.133] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.137] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:53:24.141] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:53:24.146] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.150] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:53:24.155] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.159] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:53:24.164] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:53:24.168] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:53:24.173] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.177] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.182] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.186] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.191] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.195] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:53:24.199] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.204] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:53:24.208] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:53:24.213] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:53:24.217] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:53:24.222] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:24.226] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:53:24.231] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:53:24.235] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:53:24.240] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:53:24.273] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C0.dat
[12:53:24.273] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C1.dat
[12:53:24.273] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C2.dat
[12:53:24.274] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C3.dat
[12:53:24.274] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C4.dat
[12:53:24.274] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C5.dat
[12:53:24.274] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C6.dat
[12:53:24.274] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C7.dat
[12:53:24.274] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C8.dat
[12:53:24.274] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C9.dat
[12:53:24.274] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C10.dat
[12:53:24.274] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C11.dat
[12:53:24.275] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C12.dat
[12:53:24.275] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C13.dat
[12:53:24.275] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C14.dat
[12:53:24.275] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//dacParameters35_C15.dat
[12:53:24.568] <TB2> INFO: Expecting 41600 events.
[12:53:27.673] <TB2> INFO: 41600 events read in total (2513ms).
[12:53:27.674] <TB2> INFO: Test took 3397ms.
[12:53:28.178] <TB2> INFO: Expecting 41600 events.
[12:53:31.309] <TB2> INFO: 41600 events read in total (2540ms).
[12:53:31.310] <TB2> INFO: Test took 3422ms.
[12:53:31.754] <TB2> INFO: Expecting 41600 events.
[12:53:34.848] <TB2> INFO: 41600 events read in total (2502ms).
[12:53:34.848] <TB2> INFO: Test took 3327ms.
[12:53:35.062] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:35.151] <TB2> INFO: Expecting 2560 events.
[12:53:36.033] <TB2> INFO: 2560 events read in total (291ms).
[12:53:36.034] <TB2> INFO: Test took 972ms.
[12:53:36.036] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:36.342] <TB2> INFO: Expecting 2560 events.
[12:53:37.229] <TB2> INFO: 2560 events read in total (295ms).
[12:53:37.230] <TB2> INFO: Test took 1194ms.
[12:53:37.232] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:37.538] <TB2> INFO: Expecting 2560 events.
[12:53:38.422] <TB2> INFO: 2560 events read in total (292ms).
[12:53:38.422] <TB2> INFO: Test took 1190ms.
[12:53:38.424] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:38.731] <TB2> INFO: Expecting 2560 events.
[12:53:39.617] <TB2> INFO: 2560 events read in total (295ms).
[12:53:39.618] <TB2> INFO: Test took 1194ms.
[12:53:39.620] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:39.926] <TB2> INFO: Expecting 2560 events.
[12:53:40.813] <TB2> INFO: 2560 events read in total (295ms).
[12:53:40.813] <TB2> INFO: Test took 1194ms.
[12:53:40.815] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:41.122] <TB2> INFO: Expecting 2560 events.
[12:53:42.004] <TB2> INFO: 2560 events read in total (291ms).
[12:53:42.004] <TB2> INFO: Test took 1189ms.
[12:53:42.006] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:42.313] <TB2> INFO: Expecting 2560 events.
[12:53:43.196] <TB2> INFO: 2560 events read in total (292ms).
[12:53:43.197] <TB2> INFO: Test took 1191ms.
[12:53:43.199] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:43.505] <TB2> INFO: Expecting 2560 events.
[12:53:44.389] <TB2> INFO: 2560 events read in total (292ms).
[12:53:44.389] <TB2> INFO: Test took 1190ms.
[12:53:44.391] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:44.697] <TB2> INFO: Expecting 2560 events.
[12:53:45.577] <TB2> INFO: 2560 events read in total (288ms).
[12:53:45.577] <TB2> INFO: Test took 1186ms.
[12:53:45.579] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:45.885] <TB2> INFO: Expecting 2560 events.
[12:53:46.768] <TB2> INFO: 2560 events read in total (291ms).
[12:53:46.769] <TB2> INFO: Test took 1190ms.
[12:53:46.771] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:47.077] <TB2> INFO: Expecting 2560 events.
[12:53:47.955] <TB2> INFO: 2560 events read in total (287ms).
[12:53:47.955] <TB2> INFO: Test took 1184ms.
[12:53:47.957] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:48.264] <TB2> INFO: Expecting 2560 events.
[12:53:49.144] <TB2> INFO: 2560 events read in total (289ms).
[12:53:49.144] <TB2> INFO: Test took 1187ms.
[12:53:49.146] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:49.452] <TB2> INFO: Expecting 2560 events.
[12:53:50.332] <TB2> INFO: 2560 events read in total (288ms).
[12:53:50.332] <TB2> INFO: Test took 1186ms.
[12:53:50.335] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:50.640] <TB2> INFO: Expecting 2560 events.
[12:53:51.519] <TB2> INFO: 2560 events read in total (287ms).
[12:53:51.519] <TB2> INFO: Test took 1184ms.
[12:53:51.521] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:51.827] <TB2> INFO: Expecting 2560 events.
[12:53:52.711] <TB2> INFO: 2560 events read in total (292ms).
[12:53:52.711] <TB2> INFO: Test took 1190ms.
[12:53:52.713] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:53.019] <TB2> INFO: Expecting 2560 events.
[12:53:53.899] <TB2> INFO: 2560 events read in total (288ms).
[12:53:53.899] <TB2> INFO: Test took 1186ms.
[12:53:53.901] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:54.207] <TB2> INFO: Expecting 2560 events.
[12:53:55.087] <TB2> INFO: 2560 events read in total (288ms).
[12:53:55.087] <TB2> INFO: Test took 1186ms.
[12:53:55.089] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:55.395] <TB2> INFO: Expecting 2560 events.
[12:53:56.275] <TB2> INFO: 2560 events read in total (288ms).
[12:53:56.275] <TB2> INFO: Test took 1187ms.
[12:53:56.277] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:56.583] <TB2> INFO: Expecting 2560 events.
[12:53:57.463] <TB2> INFO: 2560 events read in total (289ms).
[12:53:57.463] <TB2> INFO: Test took 1186ms.
[12:53:57.465] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:57.772] <TB2> INFO: Expecting 2560 events.
[12:53:58.655] <TB2> INFO: 2560 events read in total (292ms).
[12:53:58.655] <TB2> INFO: Test took 1190ms.
[12:53:58.657] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:58.963] <TB2> INFO: Expecting 2560 events.
[12:53:59.843] <TB2> INFO: 2560 events read in total (288ms).
[12:53:59.843] <TB2> INFO: Test took 1186ms.
[12:53:59.845] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:00.155] <TB2> INFO: Expecting 2560 events.
[12:54:01.035] <TB2> INFO: 2560 events read in total (288ms).
[12:54:01.035] <TB2> INFO: Test took 1190ms.
[12:54:01.037] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:01.344] <TB2> INFO: Expecting 2560 events.
[12:54:02.227] <TB2> INFO: 2560 events read in total (292ms).
[12:54:02.227] <TB2> INFO: Test took 1190ms.
[12:54:02.229] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:02.535] <TB2> INFO: Expecting 2560 events.
[12:54:03.418] <TB2> INFO: 2560 events read in total (291ms).
[12:54:03.418] <TB2> INFO: Test took 1189ms.
[12:54:03.420] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:03.726] <TB2> INFO: Expecting 2560 events.
[12:54:04.610] <TB2> INFO: 2560 events read in total (292ms).
[12:54:04.610] <TB2> INFO: Test took 1190ms.
[12:54:04.613] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:04.919] <TB2> INFO: Expecting 2560 events.
[12:54:05.803] <TB2> INFO: 2560 events read in total (292ms).
[12:54:05.804] <TB2> INFO: Test took 1192ms.
[12:54:05.806] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:06.112] <TB2> INFO: Expecting 2560 events.
[12:54:06.996] <TB2> INFO: 2560 events read in total (292ms).
[12:54:06.996] <TB2> INFO: Test took 1191ms.
[12:54:06.998] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:07.305] <TB2> INFO: Expecting 2560 events.
[12:54:08.188] <TB2> INFO: 2560 events read in total (292ms).
[12:54:08.188] <TB2> INFO: Test took 1190ms.
[12:54:08.190] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:08.496] <TB2> INFO: Expecting 2560 events.
[12:54:09.380] <TB2> INFO: 2560 events read in total (292ms).
[12:54:09.380] <TB2> INFO: Test took 1190ms.
[12:54:09.382] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:09.688] <TB2> INFO: Expecting 2560 events.
[12:54:10.571] <TB2> INFO: 2560 events read in total (291ms).
[12:54:10.571] <TB2> INFO: Test took 1189ms.
[12:54:10.573] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:10.879] <TB2> INFO: Expecting 2560 events.
[12:54:11.763] <TB2> INFO: 2560 events read in total (292ms).
[12:54:11.763] <TB2> INFO: Test took 1190ms.
[12:54:11.765] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:12.071] <TB2> INFO: Expecting 2560 events.
[12:54:12.955] <TB2> INFO: 2560 events read in total (292ms).
[12:54:12.955] <TB2> INFO: Test took 1190ms.
[12:54:13.417] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 535 seconds
[12:54:13.417] <TB2> INFO: PH scale (per ROC): 50 39 42 72 53 52 47 38 48 37 48 36 41 46 48 47
[12:54:13.417] <TB2> INFO: PH offset (per ROC): 128 111 97 121 139 132 114 110 139 107 134 153 109 129 112 133
[12:54:13.422] <TB2> INFO: Decoding statistics:
[12:54:13.422] <TB2> INFO: General information:
[12:54:13.422] <TB2> INFO: 16bit words read: 127884
[12:54:13.422] <TB2> INFO: valid events total: 20480
[12:54:13.422] <TB2> INFO: empty events: 17978
[12:54:13.422] <TB2> INFO: valid events with pixels: 2502
[12:54:13.422] <TB2> INFO: valid pixel hits: 2502
[12:54:13.422] <TB2> INFO: Event errors: 0
[12:54:13.422] <TB2> INFO: start marker: 0
[12:54:13.422] <TB2> INFO: stop marker: 0
[12:54:13.422] <TB2> INFO: overflow: 0
[12:54:13.422] <TB2> INFO: invalid 5bit words: 0
[12:54:13.422] <TB2> INFO: invalid XOR eye diagram: 0
[12:54:13.422] <TB2> INFO: frame (failed synchr.): 0
[12:54:13.422] <TB2> INFO: idle data (no TBM trl): 0
[12:54:13.422] <TB2> INFO: no data (only TBM hdr): 0
[12:54:13.422] <TB2> INFO: TBM errors: 0
[12:54:13.422] <TB2> INFO: flawed TBM headers: 0
[12:54:13.422] <TB2> INFO: flawed TBM trailers: 0
[12:54:13.422] <TB2> INFO: event ID mismatches: 0
[12:54:13.422] <TB2> INFO: ROC errors: 0
[12:54:13.422] <TB2> INFO: missing ROC header(s): 0
[12:54:13.422] <TB2> INFO: misplaced readback start: 0
[12:54:13.422] <TB2> INFO: Pixel decoding errors: 0
[12:54:13.422] <TB2> INFO: pixel data incomplete: 0
[12:54:13.422] <TB2> INFO: pixel address: 0
[12:54:13.422] <TB2> INFO: pulse height fill bit: 0
[12:54:13.422] <TB2> INFO: buffer corruption: 0
[12:54:13.680] <TB2> INFO: ######################################################################
[12:54:13.680] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[12:54:13.680] <TB2> INFO: ######################################################################
[12:54:13.692] <TB2> INFO: scanning low vcal = 10
[12:54:13.925] <TB2> INFO: Expecting 41600 events.
[12:54:17.518] <TB2> INFO: 41600 events read in total (3002ms).
[12:54:17.518] <TB2> INFO: Test took 3826ms.
[12:54:17.520] <TB2> INFO: scanning low vcal = 20
[12:54:17.820] <TB2> INFO: Expecting 41600 events.
[12:54:21.402] <TB2> INFO: 41600 events read in total (2991ms).
[12:54:21.403] <TB2> INFO: Test took 3883ms.
[12:54:21.405] <TB2> INFO: scanning low vcal = 30
[12:54:21.701] <TB2> INFO: Expecting 41600 events.
[12:54:25.368] <TB2> INFO: 41600 events read in total (3076ms).
[12:54:25.369] <TB2> INFO: Test took 3964ms.
[12:54:25.371] <TB2> INFO: scanning low vcal = 40
[12:54:25.651] <TB2> INFO: Expecting 41600 events.
[12:54:29.645] <TB2> INFO: 41600 events read in total (3403ms).
[12:54:29.646] <TB2> INFO: Test took 4275ms.
[12:54:29.649] <TB2> INFO: scanning low vcal = 50
[12:54:29.946] <TB2> INFO: Expecting 41600 events.
[12:54:33.898] <TB2> INFO: 41600 events read in total (3361ms).
[12:54:33.898] <TB2> INFO: Test took 4249ms.
[12:54:33.901] <TB2> INFO: scanning low vcal = 60
[12:54:34.193] <TB2> INFO: Expecting 41600 events.
[12:54:38.242] <TB2> INFO: 41600 events read in total (3457ms).
[12:54:38.242] <TB2> INFO: Test took 4341ms.
[12:54:38.245] <TB2> INFO: scanning low vcal = 70
[12:54:38.538] <TB2> INFO: Expecting 41600 events.
[12:54:42.564] <TB2> INFO: 41600 events read in total (3434ms).
[12:54:42.565] <TB2> INFO: Test took 4320ms.
[12:54:42.568] <TB2> INFO: scanning low vcal = 80
[12:54:42.845] <TB2> INFO: Expecting 41600 events.
[12:54:46.816] <TB2> INFO: 41600 events read in total (3380ms).
[12:54:46.816] <TB2> INFO: Test took 4248ms.
[12:54:46.819] <TB2> INFO: scanning low vcal = 90
[12:54:47.111] <TB2> INFO: Expecting 41600 events.
[12:54:51.091] <TB2> INFO: 41600 events read in total (3388ms).
[12:54:51.091] <TB2> INFO: Test took 4272ms.
[12:54:51.094] <TB2> INFO: scanning low vcal = 100
[12:54:51.370] <TB2> INFO: Expecting 41600 events.
[12:54:55.417] <TB2> INFO: 41600 events read in total (3455ms).
[12:54:55.418] <TB2> INFO: Test took 4324ms.
[12:54:55.421] <TB2> INFO: scanning low vcal = 110
[12:54:55.698] <TB2> INFO: Expecting 41600 events.
[12:54:59.690] <TB2> INFO: 41600 events read in total (3401ms).
[12:54:59.691] <TB2> INFO: Test took 4270ms.
[12:54:59.693] <TB2> INFO: scanning low vcal = 120
[12:54:59.970] <TB2> INFO: Expecting 41600 events.
[12:55:03.976] <TB2> INFO: 41600 events read in total (3415ms).
[12:55:03.977] <TB2> INFO: Test took 4284ms.
[12:55:03.980] <TB2> INFO: scanning low vcal = 130
[12:55:04.256] <TB2> INFO: Expecting 41600 events.
[12:55:08.272] <TB2> INFO: 41600 events read in total (3424ms).
[12:55:08.273] <TB2> INFO: Test took 4293ms.
[12:55:08.276] <TB2> INFO: scanning low vcal = 140
[12:55:08.572] <TB2> INFO: Expecting 41600 events.
[12:55:12.612] <TB2> INFO: 41600 events read in total (3448ms).
[12:55:12.612] <TB2> INFO: Test took 4336ms.
[12:55:12.615] <TB2> INFO: scanning low vcal = 150
[12:55:12.892] <TB2> INFO: Expecting 41600 events.
[12:55:16.866] <TB2> INFO: 41600 events read in total (3383ms).
[12:55:16.866] <TB2> INFO: Test took 4251ms.
[12:55:16.869] <TB2> INFO: scanning low vcal = 160
[12:55:17.146] <TB2> INFO: Expecting 41600 events.
[12:55:21.158] <TB2> INFO: 41600 events read in total (3421ms).
[12:55:21.159] <TB2> INFO: Test took 4290ms.
[12:55:21.162] <TB2> INFO: scanning low vcal = 170
[12:55:21.455] <TB2> INFO: Expecting 41600 events.
[12:55:25.460] <TB2> INFO: 41600 events read in total (3413ms).
[12:55:25.461] <TB2> INFO: Test took 4299ms.
[12:55:25.464] <TB2> INFO: scanning low vcal = 180
[12:55:25.761] <TB2> INFO: Expecting 41600 events.
[12:55:29.751] <TB2> INFO: 41600 events read in total (3399ms).
[12:55:29.752] <TB2> INFO: Test took 4288ms.
[12:55:29.754] <TB2> INFO: scanning low vcal = 190
[12:55:30.047] <TB2> INFO: Expecting 41600 events.
[12:55:34.028] <TB2> INFO: 41600 events read in total (3390ms).
[12:55:34.029] <TB2> INFO: Test took 4274ms.
[12:55:34.031] <TB2> INFO: scanning low vcal = 200
[12:55:34.308] <TB2> INFO: Expecting 41600 events.
[12:55:38.325] <TB2> INFO: 41600 events read in total (3425ms).
[12:55:38.326] <TB2> INFO: Test took 4295ms.
[12:55:38.329] <TB2> INFO: scanning low vcal = 210
[12:55:38.606] <TB2> INFO: Expecting 41600 events.
[12:55:42.601] <TB2> INFO: 41600 events read in total (3404ms).
[12:55:42.602] <TB2> INFO: Test took 4273ms.
[12:55:42.605] <TB2> INFO: scanning low vcal = 220
[12:55:42.881] <TB2> INFO: Expecting 41600 events.
[12:55:46.900] <TB2> INFO: 41600 events read in total (3427ms).
[12:55:46.901] <TB2> INFO: Test took 4296ms.
[12:55:46.903] <TB2> INFO: scanning low vcal = 230
[12:55:47.199] <TB2> INFO: Expecting 41600 events.
[12:55:51.240] <TB2> INFO: 41600 events read in total (3449ms).
[12:55:51.241] <TB2> INFO: Test took 4338ms.
[12:55:51.244] <TB2> INFO: scanning low vcal = 240
[12:55:51.535] <TB2> INFO: Expecting 41600 events.
[12:55:55.519] <TB2> INFO: 41600 events read in total (3392ms).
[12:55:55.519] <TB2> INFO: Test took 4275ms.
[12:55:55.522] <TB2> INFO: scanning low vcal = 250
[12:55:55.798] <TB2> INFO: Expecting 41600 events.
[12:55:59.811] <TB2> INFO: 41600 events read in total (3420ms).
[12:55:59.812] <TB2> INFO: Test took 4290ms.
[12:55:59.816] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[12:56:00.092] <TB2> INFO: Expecting 41600 events.
[12:56:04.051] <TB2> INFO: 41600 events read in total (3368ms).
[12:56:04.052] <TB2> INFO: Test took 4236ms.
[12:56:04.054] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[12:56:04.331] <TB2> INFO: Expecting 41600 events.
[12:56:08.379] <TB2> INFO: 41600 events read in total (3456ms).
[12:56:08.380] <TB2> INFO: Test took 4325ms.
[12:56:08.382] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[12:56:08.659] <TB2> INFO: Expecting 41600 events.
[12:56:12.681] <TB2> INFO: 41600 events read in total (3430ms).
[12:56:12.681] <TB2> INFO: Test took 4298ms.
[12:56:12.684] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[12:56:12.960] <TB2> INFO: Expecting 41600 events.
[12:56:16.971] <TB2> INFO: 41600 events read in total (3419ms).
[12:56:16.971] <TB2> INFO: Test took 4287ms.
[12:56:16.974] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:56:17.250] <TB2> INFO: Expecting 41600 events.
[12:56:21.251] <TB2> INFO: 41600 events read in total (3409ms).
[12:56:21.251] <TB2> INFO: Test took 4277ms.
[12:56:21.652] <TB2> INFO: PixTestGainPedestal::measure() done
[12:56:55.251] <TB2> INFO: PixTestGainPedestal::fit() done
[12:56:55.251] <TB2> INFO: non-linearity mean: 0.972 0.920 0.892 0.983 0.967 0.976 0.973 0.949 0.973 0.917 0.966 0.944 0.894 0.965 0.949 0.961
[12:56:55.251] <TB2> INFO: non-linearity RMS: 0.006 0.067 0.114 0.003 0.005 0.004 0.005 0.020 0.006 0.070 0.005 0.020 0.124 0.006 0.021 0.007
[12:56:55.251] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[12:56:55.272] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[12:56:55.294] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[12:56:55.315] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[12:56:55.334] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[12:56:55.347] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[12:56:55.368] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[12:56:55.388] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[12:56:55.408] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[12:56:55.430] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[12:56:55.453] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[12:56:55.472] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[12:56:55.485] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[12:56:55.499] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[12:56:55.513] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[12:56:55.527] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[12:56:55.541] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 161 seconds
[12:56:55.541] <TB2> INFO: Decoding statistics:
[12:56:55.541] <TB2> INFO: General information:
[12:56:55.541] <TB2> INFO: 16bit words read: 3327976
[12:56:55.541] <TB2> INFO: valid events total: 332800
[12:56:55.541] <TB2> INFO: empty events: 0
[12:56:55.541] <TB2> INFO: valid events with pixels: 332800
[12:56:55.541] <TB2> INFO: valid pixel hits: 665588
[12:56:55.541] <TB2> INFO: Event errors: 0
[12:56:55.541] <TB2> INFO: start marker: 0
[12:56:55.541] <TB2> INFO: stop marker: 0
[12:56:55.541] <TB2> INFO: overflow: 0
[12:56:55.541] <TB2> INFO: invalid 5bit words: 0
[12:56:55.541] <TB2> INFO: invalid XOR eye diagram: 0
[12:56:55.541] <TB2> INFO: frame (failed synchr.): 0
[12:56:55.541] <TB2> INFO: idle data (no TBM trl): 0
[12:56:55.541] <TB2> INFO: no data (only TBM hdr): 0
[12:56:55.541] <TB2> INFO: TBM errors: 0
[12:56:55.541] <TB2> INFO: flawed TBM headers: 0
[12:56:55.541] <TB2> INFO: flawed TBM trailers: 0
[12:56:55.541] <TB2> INFO: event ID mismatches: 0
[12:56:55.541] <TB2> INFO: ROC errors: 0
[12:56:55.541] <TB2> INFO: missing ROC header(s): 0
[12:56:55.541] <TB2> INFO: misplaced readback start: 0
[12:56:55.541] <TB2> INFO: Pixel decoding errors: 0
[12:56:55.541] <TB2> INFO: pixel data incomplete: 0
[12:56:55.541] <TB2> INFO: pixel address: 0
[12:56:55.541] <TB2> INFO: pulse height fill bit: 0
[12:56:55.541] <TB2> INFO: buffer corruption: 0
[12:56:55.563] <TB2> INFO: Decoding statistics:
[12:56:55.563] <TB2> INFO: General information:
[12:56:55.563] <TB2> INFO: 16bit words read: 3457396
[12:56:55.563] <TB2> INFO: valid events total: 353536
[12:56:55.563] <TB2> INFO: empty events: 18234
[12:56:55.563] <TB2> INFO: valid events with pixels: 335302
[12:56:55.563] <TB2> INFO: valid pixel hits: 668090
[12:56:55.563] <TB2> INFO: Event errors: 0
[12:56:55.563] <TB2> INFO: start marker: 0
[12:56:55.563] <TB2> INFO: stop marker: 0
[12:56:55.563] <TB2> INFO: overflow: 0
[12:56:55.563] <TB2> INFO: invalid 5bit words: 0
[12:56:55.563] <TB2> INFO: invalid XOR eye diagram: 0
[12:56:55.563] <TB2> INFO: frame (failed synchr.): 0
[12:56:55.564] <TB2> INFO: idle data (no TBM trl): 0
[12:56:55.564] <TB2> INFO: no data (only TBM hdr): 0
[12:56:55.564] <TB2> INFO: TBM errors: 0
[12:56:55.564] <TB2> INFO: flawed TBM headers: 0
[12:56:55.564] <TB2> INFO: flawed TBM trailers: 0
[12:56:55.564] <TB2> INFO: event ID mismatches: 0
[12:56:55.564] <TB2> INFO: ROC errors: 0
[12:56:55.564] <TB2> INFO: missing ROC header(s): 0
[12:56:55.564] <TB2> INFO: misplaced readback start: 0
[12:56:55.564] <TB2> INFO: Pixel decoding errors: 0
[12:56:55.564] <TB2> INFO: pixel data incomplete: 0
[12:56:55.564] <TB2> INFO: pixel address: 0
[12:56:55.564] <TB2> INFO: pulse height fill bit: 0
[12:56:55.564] <TB2> INFO: buffer corruption: 0
[12:56:55.564] <TB2> INFO: enter test to run
[12:56:55.564] <TB2> INFO: test: exit no parameter change
[12:56:55.626] <TB2> QUIET: Connection to board 156 closed.
[12:56:55.626] <TB2> INFO: pXar: this is the end, my friend