[13:15:58.065] <TB2> INFO: *** Welcome to pxar ***
[13:15:58.065] <TB2> INFO: *** Today: 2016/10/31
[13:15:58.072] <TB2> INFO: *** Version: c8ba-dirty
[13:15:58.072] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C15.dat
[13:15:58.072] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[13:15:58.073] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//defaultMaskFile.dat
[13:15:58.073] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters_C15.dat
[13:15:58.165] <TB2> INFO: clk: 4
[13:15:58.165] <TB2> INFO: ctr: 4
[13:15:58.165] <TB2> INFO: sda: 19
[13:15:58.165] <TB2> INFO: tin: 9
[13:15:58.165] <TB2> INFO: level: 15
[13:15:58.165] <TB2> INFO: triggerdelay: 0
[13:15:58.165] <TB2> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[13:15:58.165] <TB2> INFO: Log level: INFO
[13:15:58.174] <TB2> INFO: Found DTB DTB_WXC55Z
[13:15:58.185] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[13:15:58.187] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[13:15:58.189] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[13:15:59.729] <TB2> INFO: DUT info:
[13:15:59.729] <TB2> INFO: The DUT currently contains the following objects:
[13:15:59.729] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[13:15:59.729] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:15:59.729] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:15:59.729] <TB2> INFO: TBM Core alpha (2): 7 registers set
[13:15:59.729] <TB2> INFO: TBM Core beta (3): 7 registers set
[13:15:59.729] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[13:15:59.729] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:59.729] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:16:00.130] <TB2> INFO: enter 'restricted' command line mode
[13:16:00.130] <TB2> INFO: enter test to run
[13:16:00.130] <TB2> INFO: test: pretest no parameter change
[13:16:00.130] <TB2> INFO: running: pretest
[13:16:00.000] <TB2> INFO: ######################################################################
[13:16:00.000] <TB2> INFO: PixTestPretest::doTest()
[13:16:00.000] <TB2> INFO: ######################################################################
[13:16:00.001] <TB2> INFO: ----------------------------------------------------------------------
[13:16:00.001] <TB2> INFO: PixTestPretest::programROC()
[13:16:00.001] <TB2> INFO: ----------------------------------------------------------------------
[13:16:19.014] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:16:19.014] <TB2> INFO: IA differences per ROC: 16.9 19.3 20.1 19.3 17.7 18.5 21.7 18.5 19.3 18.5 18.5 20.1 17.7 20.1 19.3 20.1
[13:16:19.049] <TB2> INFO: ----------------------------------------------------------------------
[13:16:19.049] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:16:19.049] <TB2> INFO: ----------------------------------------------------------------------
[13:16:40.292] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 387.5 mA = 24.2188 mA/ROC
[13:16:40.292] <TB2> INFO: i(loss) [mA/ROC]: 20.9 20.1 19.3 19.3 20.1 20.9 20.1 20.1 18.5 20.1 20.1 19.3 20.1 20.1 19.3 19.3
[13:16:40.320] <TB2> INFO: ----------------------------------------------------------------------
[13:16:40.320] <TB2> INFO: PixTestPretest::findTiming()
[13:16:40.320] <TB2> INFO: ----------------------------------------------------------------------
[13:16:40.320] <TB2> INFO: PixTestCmd::init()

[13:17:11.578] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[13:17:11.578] <TB2> INFO: (success/tries = 100/100), width = 4
[13:17:13.080] <TB2> INFO: ----------------------------------------------------------------------
[13:17:13.080] <TB2> INFO: PixTestPretest::findWorkingPixel()
[13:17:13.080] <TB2> INFO: ----------------------------------------------------------------------
[13:17:13.171] <TB2> INFO: Expecting 231680 events.
[13:17:22.855] <TB2> INFO: 231680 events read in total (9092ms).
[13:17:22.862] <TB2> INFO: Test took 9780ms.
[13:17:23.107] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[13:17:23.137] <TB2> INFO: ----------------------------------------------------------------------
[13:17:23.137] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[13:17:23.137] <TB2> INFO: ----------------------------------------------------------------------
[13:17:23.229] <TB2> INFO: Expecting 231680 events.
[13:17:32.888] <TB2> INFO: 231680 events read in total (9068ms).
[13:17:32.897] <TB2> INFO: Test took 9757ms.
[13:17:33.156] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[13:17:33.156] <TB2> INFO: CalDel: 94 80 79 74 77 81 100 80 80 78 82 99 94 90 95 79
[13:17:33.156] <TB2> INFO: VthrComp: 51 51 51 51 57 51 51 52 51 51 51 51 51 51 51 51
[13:17:33.159] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C0.dat
[13:17:33.159] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C1.dat
[13:17:33.159] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C2.dat
[13:17:33.159] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C3.dat
[13:17:33.160] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C4.dat
[13:17:33.160] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C5.dat
[13:17:33.160] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C6.dat
[13:17:33.160] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C7.dat
[13:17:33.160] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C8.dat
[13:17:33.160] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C9.dat
[13:17:33.160] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C10.dat
[13:17:33.160] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C11.dat
[13:17:33.160] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C12.dat
[13:17:33.161] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C13.dat
[13:17:33.161] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C14.dat
[13:17:33.161] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C15.dat
[13:17:33.161] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[13:17:33.161] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[13:17:33.161] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[13:17:33.161] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[13:17:33.161] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[13:17:33.257] <TB2> INFO: enter test to run
[13:17:33.257] <TB2> INFO: test: fulltest no parameter change
[13:17:33.257] <TB2> INFO: running: fulltest
[13:17:33.257] <TB2> INFO: ######################################################################
[13:17:33.257] <TB2> INFO: PixTestFullTest::doTest()
[13:17:33.257] <TB2> INFO: ######################################################################
[13:17:33.258] <TB2> INFO: ######################################################################
[13:17:33.258] <TB2> INFO: PixTestAlive::doTest()
[13:17:33.258] <TB2> INFO: ######################################################################
[13:17:33.259] <TB2> INFO: ----------------------------------------------------------------------
[13:17:33.259] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:17:33.259] <TB2> INFO: ----------------------------------------------------------------------
[13:17:33.497] <TB2> INFO: Expecting 41600 events.
[13:17:37.145] <TB2> INFO: 41600 events read in total (3056ms).
[13:17:37.146] <TB2> INFO: Test took 3885ms.
[13:17:37.374] <TB2> INFO: PixTestAlive::aliveTest() done
[13:17:37.374] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
[13:17:37.375] <TB2> INFO: ----------------------------------------------------------------------
[13:17:37.375] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:17:37.375] <TB2> INFO: ----------------------------------------------------------------------
[13:17:37.608] <TB2> INFO: Expecting 41600 events.
[13:17:40.520] <TB2> INFO: 41600 events read in total (2320ms).
[13:17:40.520] <TB2> INFO: Test took 3143ms.
[13:17:40.521] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[13:17:40.757] <TB2> INFO: PixTestAlive::maskTest() done
[13:17:40.758] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:17:40.759] <TB2> INFO: ----------------------------------------------------------------------
[13:17:40.759] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:17:40.759] <TB2> INFO: ----------------------------------------------------------------------
[13:17:41.036] <TB2> INFO: Expecting 41600 events.
[13:17:44.470] <TB2> INFO: 41600 events read in total (2843ms).
[13:17:44.471] <TB2> INFO: Test took 3711ms.
[13:17:44.698] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[13:17:44.698] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:17:44.698] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[13:17:44.698] <TB2> INFO: Decoding statistics:
[13:17:44.698] <TB2> INFO: General information:
[13:17:44.698] <TB2> INFO: 16bit words read: 0
[13:17:44.698] <TB2> INFO: valid events total: 0
[13:17:44.698] <TB2> INFO: empty events: 0
[13:17:44.698] <TB2> INFO: valid events with pixels: 0
[13:17:44.698] <TB2> INFO: valid pixel hits: 0
[13:17:44.698] <TB2> INFO: Event errors: 0
[13:17:44.698] <TB2> INFO: start marker: 0
[13:17:44.698] <TB2> INFO: stop marker: 0
[13:17:44.698] <TB2> INFO: overflow: 0
[13:17:44.698] <TB2> INFO: invalid 5bit words: 0
[13:17:44.698] <TB2> INFO: invalid XOR eye diagram: 0
[13:17:44.699] <TB2> INFO: frame (failed synchr.): 0
[13:17:44.699] <TB2> INFO: idle data (no TBM trl): 0
[13:17:44.699] <TB2> INFO: no data (only TBM hdr): 0
[13:17:44.699] <TB2> INFO: TBM errors: 0
[13:17:44.699] <TB2> INFO: flawed TBM headers: 0
[13:17:44.699] <TB2> INFO: flawed TBM trailers: 0
[13:17:44.699] <TB2> INFO: event ID mismatches: 0
[13:17:44.699] <TB2> INFO: ROC errors: 0
[13:17:44.699] <TB2> INFO: missing ROC header(s): 0
[13:17:44.699] <TB2> INFO: misplaced readback start: 0
[13:17:44.699] <TB2> INFO: Pixel decoding errors: 0
[13:17:44.699] <TB2> INFO: pixel data incomplete: 0
[13:17:44.699] <TB2> INFO: pixel address: 0
[13:17:44.699] <TB2> INFO: pulse height fill bit: 0
[13:17:44.699] <TB2> INFO: buffer corruption: 0
[13:17:44.706] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:17:44.706] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[13:17:44.706] <TB2> INFO: ######################################################################
[13:17:44.706] <TB2> INFO: PixTestReadback::doTest()
[13:17:44.706] <TB2> INFO: ######################################################################
[13:17:44.706] <TB2> INFO: ----------------------------------------------------------------------
[13:17:44.706] <TB2> INFO: PixTestReadback::CalibrateVd()
[13:17:44.706] <TB2> INFO: ----------------------------------------------------------------------
[13:17:54.661] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:17:54.662] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:17:54.691] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:17:54.691] <TB2> INFO: ----------------------------------------------------------------------
[13:17:54.691] <TB2> INFO: PixTestReadback::CalibrateVa()
[13:17:54.691] <TB2> INFO: ----------------------------------------------------------------------
[13:18:04.582] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:18:04.582] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:18:04.582] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:18:04.582] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:18:04.582] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:18:04.582] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:18:04.582] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:18:04.582] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:18:04.583] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:18:04.583] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:18:04.583] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:18:04.583] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:18:04.583] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:18:04.583] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:18:04.583] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:18:04.583] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:18:04.612] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:18:04.612] <TB2> INFO: ----------------------------------------------------------------------
[13:18:04.612] <TB2> INFO: PixTestReadback::readbackVbg()
[13:18:04.612] <TB2> INFO: ----------------------------------------------------------------------
[13:18:12.252] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:18:12.252] <TB2> INFO: ----------------------------------------------------------------------
[13:18:12.252] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[13:18:12.252] <TB2> INFO: ----------------------------------------------------------------------
[13:18:12.252] <TB2> INFO: Vbg will be calibrated using Vd calibration
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 158.6calibrated Vbg = 1.17717 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 160.7calibrated Vbg = 1.17735 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 156.7calibrated Vbg = 1.16671 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 148.6calibrated Vbg = 1.1736 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 161.8calibrated Vbg = 1.17392 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 153.2calibrated Vbg = 1.18204 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 152.7calibrated Vbg = 1.17203 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 160.4calibrated Vbg = 1.17531 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 152.3calibrated Vbg = 1.17626 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 148.2calibrated Vbg = 1.17059 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 143calibrated Vbg = 1.16695 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 146.3calibrated Vbg = 1.15816 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 153.4calibrated Vbg = 1.16853 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 143.2calibrated Vbg = 1.17322 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 153.1calibrated Vbg = 1.16768 :::*/*/*/*/
[13:18:12.252] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 155calibrated Vbg = 1.1646 :::*/*/*/*/
[13:18:12.254] <TB2> INFO: ----------------------------------------------------------------------
[13:18:12.254] <TB2> INFO: PixTestReadback::CalibrateIa()
[13:18:12.254] <TB2> INFO: ----------------------------------------------------------------------
[13:20:52.574] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:20:52.574] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:20:52.574] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:20:52.574] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:20:52.575] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:20:52.575] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:20:52.575] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:20:52.575] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:20:52.575] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:20:52.575] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:20:52.575] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:20:52.575] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:20:52.575] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:20:52.575] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:20:52.575] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:20:52.575] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:20:52.601] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:20:52.603] <TB2> INFO: PixTestReadback::doTest() done
[13:20:52.603] <TB2> INFO: Decoding statistics:
[13:20:52.603] <TB2> INFO: General information:
[13:20:52.603] <TB2> INFO: 16bit words read: 1536
[13:20:52.603] <TB2> INFO: valid events total: 256
[13:20:52.603] <TB2> INFO: empty events: 256
[13:20:52.603] <TB2> INFO: valid events with pixels: 0
[13:20:52.603] <TB2> INFO: valid pixel hits: 0
[13:20:52.603] <TB2> INFO: Event errors: 0
[13:20:52.603] <TB2> INFO: start marker: 0
[13:20:52.603] <TB2> INFO: stop marker: 0
[13:20:52.603] <TB2> INFO: overflow: 0
[13:20:52.603] <TB2> INFO: invalid 5bit words: 0
[13:20:52.603] <TB2> INFO: invalid XOR eye diagram: 0
[13:20:52.603] <TB2> INFO: frame (failed synchr.): 0
[13:20:52.603] <TB2> INFO: idle data (no TBM trl): 0
[13:20:52.603] <TB2> INFO: no data (only TBM hdr): 0
[13:20:52.603] <TB2> INFO: TBM errors: 0
[13:20:52.603] <TB2> INFO: flawed TBM headers: 0
[13:20:52.603] <TB2> INFO: flawed TBM trailers: 0
[13:20:52.603] <TB2> INFO: event ID mismatches: 0
[13:20:52.603] <TB2> INFO: ROC errors: 0
[13:20:52.603] <TB2> INFO: missing ROC header(s): 0
[13:20:52.603] <TB2> INFO: misplaced readback start: 0
[13:20:52.603] <TB2> INFO: Pixel decoding errors: 0
[13:20:52.603] <TB2> INFO: pixel data incomplete: 0
[13:20:52.603] <TB2> INFO: pixel address: 0
[13:20:52.603] <TB2> INFO: pulse height fill bit: 0
[13:20:52.603] <TB2> INFO: buffer corruption: 0
[13:20:52.647] <TB2> INFO: ######################################################################
[13:20:52.647] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[13:20:52.647] <TB2> INFO: ######################################################################
[13:20:52.650] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[13:20:52.662] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:20:52.662] <TB2> INFO: run 1 of 1
[13:20:52.897] <TB2> INFO: Expecting 3120000 events.
[13:21:23.045] <TB2> INFO: 664830 events read in total (29556ms).





















[13:21:52.615] <TB2> INFO: 1323350 events read in total (59126ms).











[13:22:21.971] <TB2> INFO: 1975405 events read in total (88482ms).











[13:22:51.289] <TB2> INFO: 2625955 events read in total (117800ms).











[13:23:13.792] <TB2> INFO: 3120000 events read in total (140303ms).
[13:23:13.850] <TB2> INFO: Test took 141189ms.
[13:23:38.561] <TB2> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 165 seconds
[13:23:38.561] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 0 2 0 0 0 0 0 0 2 2 0 19 21
[13:23:38.561] <TB2> INFO: separation cut (per ROC): 101 104 102 103 111 111 108 115 101 111 109 98 99 102 108 130
[13:23:38.561] <TB2> INFO: Decoding statistics:
[13:23:38.561] <TB2> INFO: General information:
[13:23:38.561] <TB2> INFO: 16bit words read: 0
[13:23:38.561] <TB2> INFO: valid events total: 0
[13:23:38.561] <TB2> INFO: empty events: 0
[13:23:38.561] <TB2> INFO: valid events with pixels: 0
[13:23:38.561] <TB2> INFO: valid pixel hits: 0
[13:23:38.561] <TB2> INFO: Event errors: 0
[13:23:38.561] <TB2> INFO: start marker: 0
[13:23:38.562] <TB2> INFO: stop marker: 0
[13:23:38.562] <TB2> INFO: overflow: 0
[13:23:38.562] <TB2> INFO: invalid 5bit words: 0
[13:23:38.562] <TB2> INFO: invalid XOR eye diagram: 0
[13:23:38.562] <TB2> INFO: frame (failed synchr.): 0
[13:23:38.562] <TB2> INFO: idle data (no TBM trl): 0
[13:23:38.562] <TB2> INFO: no data (only TBM hdr): 0
[13:23:38.562] <TB2> INFO: TBM errors: 0
[13:23:38.562] <TB2> INFO: flawed TBM headers: 0
[13:23:38.562] <TB2> INFO: flawed TBM trailers: 0
[13:23:38.562] <TB2> INFO: event ID mismatches: 0
[13:23:38.562] <TB2> INFO: ROC errors: 0
[13:23:38.562] <TB2> INFO: missing ROC header(s): 0
[13:23:38.562] <TB2> INFO: misplaced readback start: 0
[13:23:38.562] <TB2> INFO: Pixel decoding errors: 0
[13:23:38.562] <TB2> INFO: pixel data incomplete: 0
[13:23:38.562] <TB2> INFO: pixel address: 0
[13:23:38.562] <TB2> INFO: pulse height fill bit: 0
[13:23:38.562] <TB2> INFO: buffer corruption: 0
[13:23:38.598] <TB2> INFO: ######################################################################
[13:23:38.598] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:23:38.598] <TB2> INFO: ######################################################################
[13:23:38.598] <TB2> INFO: ----------------------------------------------------------------------
[13:23:38.598] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:23:38.598] <TB2> INFO: ----------------------------------------------------------------------
[13:23:38.598] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[13:23:38.612] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[13:23:38.612] <TB2> INFO: run 1 of 1
[13:23:38.869] <TB2> INFO: Expecting 36608000 events.
[13:24:02.216] <TB2> INFO: 683500 events read in total (22756ms).
[13:24:24.971] <TB2> INFO: 1353600 events read in total (45511ms).
[13:24:47.463] <TB2> INFO: 2023200 events read in total (68003ms).
[13:25:10.139] <TB2> INFO: 2693750 events read in total (90679ms).
[13:25:32.647] <TB2> INFO: 3363350 events read in total (113187ms).
[13:25:55.079] <TB2> INFO: 4033900 events read in total (135619ms).
[13:26:17.442] <TB2> INFO: 4701150 events read in total (157982ms).
[13:26:40.076] <TB2> INFO: 5367850 events read in total (180616ms).
[13:27:02.724] <TB2> INFO: 6035300 events read in total (203264ms).
[13:27:25.236] <TB2> INFO: 6701650 events read in total (225776ms).
[13:27:47.921] <TB2> INFO: 7368300 events read in total (248461ms).
[13:28:10.713] <TB2> INFO: 8033700 events read in total (271253ms).
[13:28:33.738] <TB2> INFO: 8700600 events read in total (294278ms).
[13:28:56.735] <TB2> INFO: 9367700 events read in total (317275ms).
[13:29:19.597] <TB2> INFO: 10035400 events read in total (340137ms).
[13:29:42.570] <TB2> INFO: 10701350 events read in total (363110ms).
[13:30:05.336] <TB2> INFO: 11369350 events read in total (385876ms).
[13:30:28.004] <TB2> INFO: 12035000 events read in total (408544ms).
[13:30:50.788] <TB2> INFO: 12700950 events read in total (431328ms).
[13:31:13.623] <TB2> INFO: 13365350 events read in total (454163ms).
[13:31:36.476] <TB2> INFO: 14031400 events read in total (477016ms).
[13:31:59.771] <TB2> INFO: 14693950 events read in total (500311ms).
[13:32:22.490] <TB2> INFO: 15358000 events read in total (523030ms).
[13:32:45.733] <TB2> INFO: 16023100 events read in total (546273ms).
[13:33:08.694] <TB2> INFO: 16688650 events read in total (569234ms).
[13:33:31.799] <TB2> INFO: 17352600 events read in total (592339ms).
[13:33:54.800] <TB2> INFO: 18016750 events read in total (615340ms).
[13:34:18.084] <TB2> INFO: 18680050 events read in total (638624ms).
[13:34:41.311] <TB2> INFO: 19342600 events read in total (661851ms).
[13:35:04.362] <TB2> INFO: 20007150 events read in total (684902ms).
[13:35:27.546] <TB2> INFO: 20668900 events read in total (708086ms).
[13:35:50.463] <TB2> INFO: 21330850 events read in total (731003ms).
[13:36:13.576] <TB2> INFO: 21990950 events read in total (754116ms).
[13:36:36.726] <TB2> INFO: 22652400 events read in total (777266ms).
[13:36:59.700] <TB2> INFO: 23316900 events read in total (800240ms).
[13:37:22.389] <TB2> INFO: 23979600 events read in total (822929ms).
[13:37:45.133] <TB2> INFO: 24642200 events read in total (845673ms).
[13:38:08.741] <TB2> INFO: 25304450 events read in total (869281ms).
[13:38:31.840] <TB2> INFO: 25964900 events read in total (892380ms).
[13:38:54.671] <TB2> INFO: 26624700 events read in total (915211ms).
[13:39:17.498] <TB2> INFO: 27285250 events read in total (938038ms).
[13:39:40.616] <TB2> INFO: 27945800 events read in total (961156ms).
[13:40:03.700] <TB2> INFO: 28606250 events read in total (984240ms).
[13:40:26.733] <TB2> INFO: 29266800 events read in total (1007273ms).
[13:40:50.093] <TB2> INFO: 29928400 events read in total (1030633ms).
[13:41:12.955] <TB2> INFO: 30588750 events read in total (1053495ms).
[13:41:36.079] <TB2> INFO: 31251250 events read in total (1076619ms).
[13:41:59.284] <TB2> INFO: 31911750 events read in total (1099824ms).
[13:42:22.556] <TB2> INFO: 32574000 events read in total (1123096ms).
[13:42:45.659] <TB2> INFO: 33237000 events read in total (1146199ms).
[13:43:08.863] <TB2> INFO: 33902600 events read in total (1169403ms).
[13:43:31.814] <TB2> INFO: 34564900 events read in total (1192354ms).
[13:43:54.676] <TB2> INFO: 35231050 events read in total (1215216ms).
[13:44:17.931] <TB2> INFO: 35895300 events read in total (1238471ms).
[13:44:41.159] <TB2> INFO: 36578650 events read in total (1261699ms).
[13:44:42.484] <TB2> INFO: 36608000 events read in total (1263024ms).
[13:44:42.555] <TB2> INFO: Test took 1263943ms.
[13:44:42.981] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:44:44.479] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:44:45.877] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:44:47.461] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:44:48.895] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:44:50.624] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:44:52.246] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:44:53.951] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:44:56.061] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:44:57.918] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:44:59.989] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:45:01.777] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:45:03.244] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:45:04.641] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:45:06.051] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:45:07.452] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:45:08.917] <TB2> INFO: PixTestScurves::scurves() done
[13:45:08.917] <TB2> INFO: Vcal mean: 114.92 126.23 119.80 119.34 134.39 128.46 128.45 131.16 122.63 131.93 114.09 110.94 116.18 117.31 117.87 118.23
[13:45:08.917] <TB2> INFO: Vcal RMS: 5.21 5.27 5.33 5.86 6.15 6.26 5.21 6.40 6.81 5.62 4.98 5.45 5.15 5.53 5.29 5.57
[13:45:08.917] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1290 seconds
[13:45:08.917] <TB2> INFO: Decoding statistics:
[13:45:08.917] <TB2> INFO: General information:
[13:45:08.917] <TB2> INFO: 16bit words read: 0
[13:45:08.917] <TB2> INFO: valid events total: 0
[13:45:08.917] <TB2> INFO: empty events: 0
[13:45:08.917] <TB2> INFO: valid events with pixels: 0
[13:45:08.917] <TB2> INFO: valid pixel hits: 0
[13:45:08.917] <TB2> INFO: Event errors: 0
[13:45:08.917] <TB2> INFO: start marker: 0
[13:45:08.917] <TB2> INFO: stop marker: 0
[13:45:08.917] <TB2> INFO: overflow: 0
[13:45:08.917] <TB2> INFO: invalid 5bit words: 0
[13:45:08.917] <TB2> INFO: invalid XOR eye diagram: 0
[13:45:08.917] <TB2> INFO: frame (failed synchr.): 0
[13:45:08.917] <TB2> INFO: idle data (no TBM trl): 0
[13:45:08.917] <TB2> INFO: no data (only TBM hdr): 0
[13:45:08.917] <TB2> INFO: TBM errors: 0
[13:45:08.917] <TB2> INFO: flawed TBM headers: 0
[13:45:08.917] <TB2> INFO: flawed TBM trailers: 0
[13:45:08.917] <TB2> INFO: event ID mismatches: 0
[13:45:08.917] <TB2> INFO: ROC errors: 0
[13:45:08.917] <TB2> INFO: missing ROC header(s): 0
[13:45:08.917] <TB2> INFO: misplaced readback start: 0
[13:45:08.917] <TB2> INFO: Pixel decoding errors: 0
[13:45:08.917] <TB2> INFO: pixel data incomplete: 0
[13:45:08.917] <TB2> INFO: pixel address: 0
[13:45:08.917] <TB2> INFO: pulse height fill bit: 0
[13:45:08.917] <TB2> INFO: buffer corruption: 0
[13:45:08.983] <TB2> INFO: ######################################################################
[13:45:08.983] <TB2> INFO: PixTestTrim::doTest()
[13:45:08.983] <TB2> INFO: ######################################################################
[13:45:08.984] <TB2> INFO: ----------------------------------------------------------------------
[13:45:08.984] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[13:45:08.984] <TB2> INFO: ----------------------------------------------------------------------
[13:45:09.025] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:45:09.025] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:45:09.033] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:45:09.033] <TB2> INFO: run 1 of 1
[13:45:09.266] <TB2> INFO: Expecting 5025280 events.
[13:45:40.342] <TB2> INFO: 824304 events read in total (30481ms).
[13:46:10.647] <TB2> INFO: 1645136 events read in total (60787ms).
[13:46:41.039] <TB2> INFO: 2463592 events read in total (91179ms).
[13:47:11.167] <TB2> INFO: 3277712 events read in total (121306ms).
[13:47:41.845] <TB2> INFO: 4087448 events read in total (151985ms).
[13:48:12.279] <TB2> INFO: 4895888 events read in total (182418ms).
[13:48:17.355] <TB2> INFO: 5025280 events read in total (187494ms).
[13:48:17.392] <TB2> INFO: Test took 188359ms.
[13:48:33.215] <TB2> INFO: ROC 0 VthrComp = 120
[13:48:33.215] <TB2> INFO: ROC 1 VthrComp = 133
[13:48:33.215] <TB2> INFO: ROC 2 VthrComp = 126
[13:48:33.215] <TB2> INFO: ROC 3 VthrComp = 126
[13:48:33.216] <TB2> INFO: ROC 4 VthrComp = 135
[13:48:33.217] <TB2> INFO: ROC 5 VthrComp = 133
[13:48:33.218] <TB2> INFO: ROC 6 VthrComp = 133
[13:48:33.218] <TB2> INFO: ROC 7 VthrComp = 133
[13:48:33.218] <TB2> INFO: ROC 8 VthrComp = 120
[13:48:33.218] <TB2> INFO: ROC 9 VthrComp = 131
[13:48:33.218] <TB2> INFO: ROC 10 VthrComp = 126
[13:48:33.218] <TB2> INFO: ROC 11 VthrComp = 116
[13:48:33.219] <TB2> INFO: ROC 12 VthrComp = 117
[13:48:33.219] <TB2> INFO: ROC 13 VthrComp = 119
[13:48:33.219] <TB2> INFO: ROC 14 VthrComp = 126
[13:48:33.219] <TB2> INFO: ROC 15 VthrComp = 123
[13:48:33.504] <TB2> INFO: Expecting 41600 events.
[13:48:37.035] <TB2> INFO: 41600 events read in total (2939ms).
[13:48:37.035] <TB2> INFO: Test took 3814ms.
[13:48:37.044] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:48:37.044] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:48:37.053] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:48:37.053] <TB2> INFO: run 1 of 1
[13:48:37.331] <TB2> INFO: Expecting 5025280 events.
[13:49:03.879] <TB2> INFO: 587200 events read in total (25957ms).
[13:49:29.999] <TB2> INFO: 1172440 events read in total (52077ms).
[13:49:56.428] <TB2> INFO: 1758608 events read in total (78506ms).
[13:50:22.833] <TB2> INFO: 2344920 events read in total (104911ms).
[13:50:48.704] <TB2> INFO: 2930400 events read in total (130782ms).
[13:51:14.974] <TB2> INFO: 3515768 events read in total (157052ms).
[13:51:40.480] <TB2> INFO: 4099984 events read in total (182558ms).
[13:52:06.412] <TB2> INFO: 4683848 events read in total (208490ms).
[13:52:21.518] <TB2> INFO: 5025280 events read in total (223596ms).
[13:52:21.578] <TB2> INFO: Test took 224525ms.
[13:52:47.166] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 58.0569 for pixel 6/77 mean/min/max = 46.0081/33.7787/58.2374
[13:52:47.166] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 58.1706 for pixel 0/29 mean/min/max = 46.7037/35.1805/58.2269
[13:52:47.167] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 58.5851 for pixel 10/74 mean/min/max = 45.929/33.2318/58.6261
[13:52:47.167] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 58.9081 for pixel 4/7 mean/min/max = 45.8499/32.5956/59.1041
[13:52:47.167] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 64.7661 for pixel 11/78 mean/min/max = 50.1613/35.4187/64.904
[13:52:47.168] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 59.6035 for pixel 0/11 mean/min/max = 46.5023/33.3066/59.698
[13:52:47.168] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 58.9438 for pixel 15/12 mean/min/max = 46.9098/34.7686/59.0511
[13:52:47.168] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 61.1096 for pixel 12/3 mean/min/max = 47.6885/34.0852/61.2919
[13:52:47.169] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 63.8387 for pixel 0/15 mean/min/max = 48.3852/32.6418/64.1286
[13:52:47.169] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 63.4068 for pixel 23/6 mean/min/max = 48.3711/33.3335/63.4087
[13:52:47.169] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 54.7093 for pixel 23/79 mean/min/max = 43.4629/31.5271/55.3987
[13:52:47.170] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 58.4544 for pixel 51/29 mean/min/max = 45.5716/32.5904/58.5529
[13:52:47.170] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 58.6662 for pixel 5/33 mean/min/max = 45.6302/32.497/58.7634
[13:52:47.171] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 59.6083 for pixel 0/21 mean/min/max = 46.0244/32.3242/59.7246
[13:52:47.171] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 56.8729 for pixel 14/73 mean/min/max = 44.4422/31.9608/56.9236
[13:52:47.171] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 58.9061 for pixel 20/8 mean/min/max = 45.9625/32.8411/59.084
[13:52:47.172] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:52:47.260] <TB2> INFO: Expecting 411648 events.
[13:52:56.562] <TB2> INFO: 411648 events read in total (8710ms).
[13:52:56.568] <TB2> INFO: Expecting 411648 events.
[13:53:05.792] <TB2> INFO: 411648 events read in total (8821ms).
[13:53:05.801] <TB2> INFO: Expecting 411648 events.
[13:53:15.102] <TB2> INFO: 411648 events read in total (8898ms).
[13:53:15.114] <TB2> INFO: Expecting 411648 events.
[13:53:24.445] <TB2> INFO: 411648 events read in total (8928ms).
[13:53:24.459] <TB2> INFO: Expecting 411648 events.
[13:53:33.675] <TB2> INFO: 411648 events read in total (8813ms).
[13:53:33.699] <TB2> INFO: Expecting 411648 events.
[13:53:42.935] <TB2> INFO: 411648 events read in total (8833ms).
[13:53:42.954] <TB2> INFO: Expecting 411648 events.
[13:53:52.215] <TB2> INFO: 411648 events read in total (8858ms).
[13:53:52.239] <TB2> INFO: Expecting 411648 events.
[13:54:01.469] <TB2> INFO: 411648 events read in total (8827ms).
[13:54:01.494] <TB2> INFO: Expecting 411648 events.
[13:54:10.654] <TB2> INFO: 411648 events read in total (8757ms).
[13:54:10.682] <TB2> INFO: Expecting 411648 events.
[13:54:19.937] <TB2> INFO: 411648 events read in total (8852ms).
[13:54:19.986] <TB2> INFO: Expecting 411648 events.
[13:54:29.272] <TB2> INFO: 411648 events read in total (8883ms).
[13:54:29.307] <TB2> INFO: Expecting 411648 events.
[13:54:38.775] <TB2> INFO: 411648 events read in total (9065ms).
[13:54:38.812] <TB2> INFO: Expecting 411648 events.
[13:54:48.024] <TB2> INFO: 411648 events read in total (8809ms).
[13:54:48.065] <TB2> INFO: Expecting 411648 events.
[13:54:57.268] <TB2> INFO: 411648 events read in total (8800ms).
[13:54:57.311] <TB2> INFO: Expecting 411648 events.
[13:55:06.600] <TB2> INFO: 411648 events read in total (8886ms).
[13:55:06.645] <TB2> INFO: Expecting 411648 events.
[13:55:15.898] <TB2> INFO: 411648 events read in total (8850ms).
[13:55:15.968] <TB2> INFO: Test took 148796ms.
[13:55:16.851] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:55:16.862] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:55:16.862] <TB2> INFO: run 1 of 1
[13:55:17.093] <TB2> INFO: Expecting 5025280 events.
[13:55:44.040] <TB2> INFO: 585656 events read in total (26355ms).
[13:56:10.616] <TB2> INFO: 1170520 events read in total (52931ms).
[13:56:37.239] <TB2> INFO: 1754800 events read in total (79554ms).
[13:57:03.833] <TB2> INFO: 2339256 events read in total (106148ms).
[13:57:30.318] <TB2> INFO: 2921792 events read in total (132633ms).
[13:57:56.212] <TB2> INFO: 3505088 events read in total (158527ms).
[13:58:22.677] <TB2> INFO: 4086352 events read in total (184992ms).
[13:58:48.824] <TB2> INFO: 4667936 events read in total (211140ms).
[13:59:04.968] <TB2> INFO: 5025280 events read in total (227283ms).
[13:59:05.085] <TB2> INFO: Test took 228223ms.
[13:59:33.083] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 7.208914 .. 146.265081
[13:59:33.316] <TB2> INFO: Expecting 208000 events.
[13:59:43.120] <TB2> INFO: 208000 events read in total (9213ms).
[13:59:43.121] <TB2> INFO: Test took 10036ms.
[13:59:43.168] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 7 .. 156 (-1/-1) hits flags = 528 (plus default)
[13:59:43.178] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:59:43.178] <TB2> INFO: run 1 of 1
[13:59:43.470] <TB2> INFO: Expecting 4992000 events.
[14:00:10.102] <TB2> INFO: 576568 events read in total (26040ms).
[14:00:35.815] <TB2> INFO: 1152192 events read in total (51754ms).
[14:01:01.906] <TB2> INFO: 1728280 events read in total (77844ms).
[14:01:28.143] <TB2> INFO: 2304120 events read in total (104081ms).
[14:01:54.287] <TB2> INFO: 2880016 events read in total (130225ms).
[14:02:20.105] <TB2> INFO: 3455968 events read in total (156043ms).
[14:02:45.756] <TB2> INFO: 4031424 events read in total (181694ms).
[14:03:11.654] <TB2> INFO: 4605904 events read in total (207592ms).
[14:03:28.654] <TB2> INFO: 4992000 events read in total (224592ms).
[14:03:28.747] <TB2> INFO: Test took 225569ms.
[14:03:53.694] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.557808 .. 43.073120
[14:03:53.986] <TB2> INFO: Expecting 208000 events.
[14:04:04.257] <TB2> INFO: 208000 events read in total (9680ms).
[14:04:04.258] <TB2> INFO: Test took 10562ms.
[14:04:04.305] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 53 (-1/-1) hits flags = 528 (plus default)
[14:04:04.315] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:04:04.315] <TB2> INFO: run 1 of 1
[14:04:04.593] <TB2> INFO: Expecting 1231360 events.
[14:04:33.396] <TB2> INFO: 668112 events read in total (28212ms).
[14:04:57.102] <TB2> INFO: 1231360 events read in total (51919ms).
[14:04:57.145] <TB2> INFO: Test took 52831ms.
[14:05:08.729] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 25.715913 .. 48.316566
[14:05:08.962] <TB2> INFO: Expecting 208000 events.
[14:05:19.144] <TB2> INFO: 208000 events read in total (9590ms).
[14:05:19.145] <TB2> INFO: Test took 10415ms.
[14:05:19.220] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 58 (-1/-1) hits flags = 528 (plus default)
[14:05:19.232] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:05:19.232] <TB2> INFO: run 1 of 1
[14:05:19.525] <TB2> INFO: Expecting 1464320 events.
[14:05:47.935] <TB2> INFO: 656696 events read in total (27818ms).
[14:06:16.170] <TB2> INFO: 1313568 events read in total (56053ms).
[14:06:22.941] <TB2> INFO: 1464320 events read in total (62825ms).
[14:06:22.968] <TB2> INFO: Test took 63736ms.
[14:06:35.083] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 25.355635 .. 50.543669
[14:06:35.316] <TB2> INFO: Expecting 208000 events.
[14:06:44.995] <TB2> INFO: 208000 events read in total (9087ms).
[14:06:44.996] <TB2> INFO: Test took 9911ms.
[14:06:45.073] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 60 (-1/-1) hits flags = 528 (plus default)
[14:06:45.086] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:06:45.086] <TB2> INFO: run 1 of 1
[14:06:45.378] <TB2> INFO: Expecting 1530880 events.
[14:07:13.868] <TB2> INFO: 650072 events read in total (27898ms).
[14:07:41.467] <TB2> INFO: 1300352 events read in total (55497ms).
[14:07:51.977] <TB2> INFO: 1530880 events read in total (66007ms).
[14:07:52.014] <TB2> INFO: Test took 66928ms.
[14:08:04.757] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:08:04.757] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:08:04.769] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:08:04.769] <TB2> INFO: run 1 of 1
[14:08:05.055] <TB2> INFO: Expecting 1364480 events.
[14:08:33.408] <TB2> INFO: 668728 events read in total (27762ms).
[14:09:01.672] <TB2> INFO: 1337224 events read in total (56026ms).
[14:09:03.178] <TB2> INFO: 1364480 events read in total (57532ms).
[14:09:03.200] <TB2> INFO: Test took 58431ms.
[14:09:15.732] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C0.dat
[14:09:15.732] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C1.dat
[14:09:15.732] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C2.dat
[14:09:15.732] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C3.dat
[14:09:15.732] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C4.dat
[14:09:15.732] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C5.dat
[14:09:15.732] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C6.dat
[14:09:15.732] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C7.dat
[14:09:15.733] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C8.dat
[14:09:15.733] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C9.dat
[14:09:15.733] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C10.dat
[14:09:15.733] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C11.dat
[14:09:15.733] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C12.dat
[14:09:15.733] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C13.dat
[14:09:15.733] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C14.dat
[14:09:15.733] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C15.dat
[14:09:15.733] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C0.dat
[14:09:15.741] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C1.dat
[14:09:15.749] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C2.dat
[14:09:15.755] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C3.dat
[14:09:15.761] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C4.dat
[14:09:15.769] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C5.dat
[14:09:15.777] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C6.dat
[14:09:15.785] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C7.dat
[14:09:15.792] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C8.dat
[14:09:15.800] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C9.dat
[14:09:15.808] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C10.dat
[14:09:15.816] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C11.dat
[14:09:15.823] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C12.dat
[14:09:15.831] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C13.dat
[14:09:15.839] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C14.dat
[14:09:15.847] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C15.dat
[14:09:15.855] <TB2> INFO: PixTestTrim::trimTest() done
[14:09:15.855] <TB2> INFO: vtrim: 121 131 151 137 165 142 149 151 165 163 139 128 143 134 123 138
[14:09:15.855] <TB2> INFO: vthrcomp: 120 133 126 126 135 133 133 133 120 131 126 116 117 119 126 123
[14:09:15.855] <TB2> INFO: vcal mean: 35.03 35.00 34.99 35.30 35.66 34.98 35.07 35.02 35.79 35.56 34.98 35.01 35.02 34.94 34.94 35.01
[14:09:15.855] <TB2> INFO: vcal RMS: 0.95 0.96 1.08 1.35 1.80 1.03 1.14 1.22 2.00 1.65 1.00 0.98 1.07 1.14 1.04 1.01
[14:09:15.855] <TB2> INFO: bits mean: 9.15 9.21 10.00 10.02 9.32 9.23 9.48 9.40 9.98 9.80 10.45 9.51 10.17 9.61 10.29 9.47
[14:09:15.855] <TB2> INFO: bits RMS: 2.62 2.37 2.37 2.53 2.25 2.62 2.35 2.38 2.43 2.42 2.44 2.69 2.39 2.61 2.42 2.63
[14:09:15.862] <TB2> INFO: ----------------------------------------------------------------------
[14:09:15.862] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:09:15.862] <TB2> INFO: ----------------------------------------------------------------------
[14:09:15.865] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:09:15.877] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:09:15.877] <TB2> INFO: run 1 of 1
[14:09:16.156] <TB2> INFO: Expecting 4160000 events.
[14:09:49.067] <TB2> INFO: 754510 events read in total (32319ms).
[14:10:21.290] <TB2> INFO: 1503190 events read in total (64542ms).
[14:10:53.323] <TB2> INFO: 2248750 events read in total (96575ms).
[14:11:25.185] <TB2> INFO: 2989835 events read in total (128437ms).
[14:11:57.133] <TB2> INFO: 3729110 events read in total (160385ms).
[14:12:15.769] <TB2> INFO: 4160000 events read in total (179021ms).
[14:12:15.815] <TB2> INFO: Test took 179938ms.
[14:12:40.356] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[14:12:40.366] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:12:40.367] <TB2> INFO: run 1 of 1
[14:12:40.598] <TB2> INFO: Expecting 4347200 events.
[14:13:13.046] <TB2> INFO: 720865 events read in total (31857ms).
[14:13:44.466] <TB2> INFO: 1436640 events read in total (63277ms).
[14:14:15.883] <TB2> INFO: 2149615 events read in total (94694ms).
[14:14:47.225] <TB2> INFO: 2859900 events read in total (126036ms).
[14:15:18.551] <TB2> INFO: 3567600 events read in total (157362ms).
[14:15:50.037] <TB2> INFO: 4277915 events read in total (188848ms).
[14:15:53.526] <TB2> INFO: 4347200 events read in total (192337ms).
[14:15:53.600] <TB2> INFO: Test took 193233ms.
[14:16:18.270] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[14:16:18.282] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:16:18.282] <TB2> INFO: run 1 of 1
[14:16:18.571] <TB2> INFO: Expecting 4347200 events.
[14:16:50.222] <TB2> INFO: 721110 events read in total (31060ms).
[14:17:21.502] <TB2> INFO: 1437225 events read in total (62340ms).
[14:17:53.078] <TB2> INFO: 2150555 events read in total (93916ms).
[14:18:24.411] <TB2> INFO: 2861000 events read in total (125249ms).
[14:18:55.607] <TB2> INFO: 3569010 events read in total (156445ms).
[14:19:27.052] <TB2> INFO: 4279515 events read in total (187890ms).
[14:19:30.429] <TB2> INFO: 4347200 events read in total (191267ms).
[14:19:30.482] <TB2> INFO: Test took 192200ms.
[14:19:54.675] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[14:19:54.687] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:19:54.687] <TB2> INFO: run 1 of 1
[14:19:54.929] <TB2> INFO: Expecting 4347200 events.
[14:20:26.957] <TB2> INFO: 721075 events read in total (31437ms).
[14:20:58.169] <TB2> INFO: 1437495 events read in total (62649ms).
[14:21:29.534] <TB2> INFO: 2150875 events read in total (94014ms).
[14:22:00.705] <TB2> INFO: 2861540 events read in total (125185ms).
[14:22:31.941] <TB2> INFO: 3569715 events read in total (156421ms).
[14:23:03.149] <TB2> INFO: 4280540 events read in total (187629ms).
[14:23:06.415] <TB2> INFO: 4347200 events read in total (190895ms).
[14:23:06.469] <TB2> INFO: Test took 191782ms.
[14:23:33.445] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[14:23:33.457] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:23:33.457] <TB2> INFO: run 1 of 1
[14:23:33.746] <TB2> INFO: Expecting 4326400 events.
[14:24:05.701] <TB2> INFO: 722585 events read in total (31364ms).
[14:24:37.349] <TB2> INFO: 1440320 events read in total (63012ms).
[14:25:08.593] <TB2> INFO: 2155570 events read in total (94256ms).
[14:25:39.591] <TB2> INFO: 2867370 events read in total (125254ms).
[14:26:10.658] <TB2> INFO: 3577345 events read in total (156321ms).
[14:26:42.059] <TB2> INFO: 4290210 events read in total (187722ms).
[14:26:44.081] <TB2> INFO: 4326400 events read in total (189744ms).
[14:26:44.134] <TB2> INFO: Test took 190677ms.
[14:27:09.480] <TB2> INFO: PixTestTrim::trimBitTest() done
[14:27:09.481] <TB2> INFO: PixTestTrim::doTest() done, duration: 2520 seconds
[14:27:09.481] <TB2> INFO: Decoding statistics:
[14:27:09.481] <TB2> INFO: General information:
[14:27:09.481] <TB2> INFO: 16bit words read: 0
[14:27:09.481] <TB2> INFO: valid events total: 0
[14:27:09.481] <TB2> INFO: empty events: 0
[14:27:09.481] <TB2> INFO: valid events with pixels: 0
[14:27:09.481] <TB2> INFO: valid pixel hits: 0
[14:27:09.481] <TB2> INFO: Event errors: 0
[14:27:09.481] <TB2> INFO: start marker: 0
[14:27:09.481] <TB2> INFO: stop marker: 0
[14:27:09.481] <TB2> INFO: overflow: 0
[14:27:09.481] <TB2> INFO: invalid 5bit words: 0
[14:27:09.481] <TB2> INFO: invalid XOR eye diagram: 0
[14:27:09.481] <TB2> INFO: frame (failed synchr.): 0
[14:27:09.481] <TB2> INFO: idle data (no TBM trl): 0
[14:27:09.481] <TB2> INFO: no data (only TBM hdr): 0
[14:27:09.481] <TB2> INFO: TBM errors: 0
[14:27:09.481] <TB2> INFO: flawed TBM headers: 0
[14:27:09.481] <TB2> INFO: flawed TBM trailers: 0
[14:27:09.481] <TB2> INFO: event ID mismatches: 0
[14:27:09.481] <TB2> INFO: ROC errors: 0
[14:27:09.481] <TB2> INFO: missing ROC header(s): 0
[14:27:09.481] <TB2> INFO: misplaced readback start: 0
[14:27:09.481] <TB2> INFO: Pixel decoding errors: 0
[14:27:09.481] <TB2> INFO: pixel data incomplete: 0
[14:27:09.481] <TB2> INFO: pixel address: 0
[14:27:09.481] <TB2> INFO: pulse height fill bit: 0
[14:27:09.481] <TB2> INFO: buffer corruption: 0
[14:27:10.341] <TB2> INFO: ######################################################################
[14:27:10.341] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[14:27:10.341] <TB2> INFO: ######################################################################
[14:27:10.574] <TB2> INFO: Expecting 41600 events.
[14:27:14.043] <TB2> INFO: 41600 events read in total (2877ms).
[14:27:14.044] <TB2> INFO: Test took 3701ms.
[14:27:14.482] <TB2> INFO: Expecting 41600 events.
[14:27:18.036] <TB2> INFO: 41600 events read in total (2962ms).
[14:27:18.036] <TB2> INFO: Test took 3785ms.
[14:27:18.324] <TB2> INFO: Expecting 41600 events.
[14:27:21.964] <TB2> INFO: 41600 events read in total (3048ms).
[14:27:21.965] <TB2> INFO: Test took 3906ms.
[14:27:22.288] <TB2> INFO: Expecting 41600 events.
[14:27:25.792] <TB2> INFO: 41600 events read in total (2912ms).
[14:27:25.793] <TB2> INFO: Test took 3803ms.
[14:27:26.111] <TB2> INFO: Expecting 41600 events.
[14:27:29.562] <TB2> INFO: 41600 events read in total (2859ms).
[14:27:29.562] <TB2> INFO: Test took 3742ms.
[14:27:29.851] <TB2> INFO: Expecting 41600 events.
[14:27:33.303] <TB2> INFO: 41600 events read in total (2861ms).
[14:27:33.304] <TB2> INFO: Test took 3718ms.
[14:27:33.595] <TB2> INFO: Expecting 41600 events.
[14:27:37.289] <TB2> INFO: 41600 events read in total (3102ms).
[14:27:37.290] <TB2> INFO: Test took 3960ms.
[14:27:37.583] <TB2> INFO: Expecting 41600 events.
[14:27:41.139] <TB2> INFO: 41600 events read in total (2965ms).
[14:27:41.140] <TB2> INFO: Test took 3822ms.
[14:27:41.428] <TB2> INFO: Expecting 41600 events.
[14:27:45.086] <TB2> INFO: 41600 events read in total (3067ms).
[14:27:45.087] <TB2> INFO: Test took 3924ms.
[14:27:45.378] <TB2> INFO: Expecting 41600 events.
[14:27:49.062] <TB2> INFO: 41600 events read in total (3092ms).
[14:27:49.062] <TB2> INFO: Test took 3948ms.
[14:27:49.350] <TB2> INFO: Expecting 41600 events.
[14:27:53.050] <TB2> INFO: 41600 events read in total (3108ms).
[14:27:53.051] <TB2> INFO: Test took 3965ms.
[14:27:53.368] <TB2> INFO: Expecting 41600 events.
[14:27:57.094] <TB2> INFO: 41600 events read in total (3134ms).
[14:27:57.095] <TB2> INFO: Test took 4021ms.
[14:27:57.408] <TB2> INFO: Expecting 41600 events.
[14:28:00.977] <TB2> INFO: 41600 events read in total (2977ms).
[14:28:00.977] <TB2> INFO: Test took 3859ms.
[14:28:01.279] <TB2> INFO: Expecting 41600 events.
[14:28:04.823] <TB2> INFO: 41600 events read in total (2952ms).
[14:28:04.823] <TB2> INFO: Test took 3822ms.
[14:28:05.111] <TB2> INFO: Expecting 41600 events.
[14:28:08.728] <TB2> INFO: 41600 events read in total (3025ms).
[14:28:08.729] <TB2> INFO: Test took 3882ms.
[14:28:09.017] <TB2> INFO: Expecting 41600 events.
[14:28:12.641] <TB2> INFO: 41600 events read in total (3032ms).
[14:28:12.642] <TB2> INFO: Test took 3890ms.
[14:28:12.930] <TB2> INFO: Expecting 41600 events.
[14:28:16.488] <TB2> INFO: 41600 events read in total (2966ms).
[14:28:16.489] <TB2> INFO: Test took 3823ms.
[14:28:16.777] <TB2> INFO: Expecting 41600 events.
[14:28:20.259] <TB2> INFO: 41600 events read in total (2891ms).
[14:28:20.260] <TB2> INFO: Test took 3748ms.
[14:28:20.575] <TB2> INFO: Expecting 41600 events.
[14:28:24.108] <TB2> INFO: 41600 events read in total (2941ms).
[14:28:24.109] <TB2> INFO: Test took 3826ms.
[14:28:24.397] <TB2> INFO: Expecting 41600 events.
[14:28:27.844] <TB2> INFO: 41600 events read in total (2857ms).
[14:28:27.845] <TB2> INFO: Test took 3713ms.
[14:28:28.159] <TB2> INFO: Expecting 41600 events.
[14:28:31.828] <TB2> INFO: 41600 events read in total (3078ms).
[14:28:31.828] <TB2> INFO: Test took 3959ms.
[14:28:32.120] <TB2> INFO: Expecting 41600 events.
[14:28:35.837] <TB2> INFO: 41600 events read in total (3125ms).
[14:28:35.838] <TB2> INFO: Test took 3983ms.
[14:28:36.125] <TB2> INFO: Expecting 41600 events.
[14:28:39.595] <TB2> INFO: 41600 events read in total (2878ms).
[14:28:39.595] <TB2> INFO: Test took 3734ms.
[14:28:39.911] <TB2> INFO: Expecting 41600 events.
[14:28:43.501] <TB2> INFO: 41600 events read in total (2998ms).
[14:28:43.502] <TB2> INFO: Test took 3883ms.
[14:28:43.810] <TB2> INFO: Expecting 41600 events.
[14:28:47.337] <TB2> INFO: 41600 events read in total (2935ms).
[14:28:47.338] <TB2> INFO: Test took 3813ms.
[14:28:47.629] <TB2> INFO: Expecting 41600 events.
[14:28:51.149] <TB2> INFO: 41600 events read in total (2928ms).
[14:28:51.150] <TB2> INFO: Test took 3785ms.
[14:28:51.438] <TB2> INFO: Expecting 41600 events.
[14:28:55.064] <TB2> INFO: 41600 events read in total (3034ms).
[14:28:55.065] <TB2> INFO: Test took 3891ms.
[14:28:55.353] <TB2> INFO: Expecting 41600 events.
[14:28:58.862] <TB2> INFO: 41600 events read in total (2917ms).
[14:28:58.863] <TB2> INFO: Test took 3775ms.
[14:28:59.152] <TB2> INFO: Expecting 41600 events.
[14:29:02.899] <TB2> INFO: 41600 events read in total (3156ms).
[14:29:02.899] <TB2> INFO: Test took 4012ms.
[14:29:03.189] <TB2> INFO: Expecting 41600 events.
[14:29:06.917] <TB2> INFO: 41600 events read in total (3137ms).
[14:29:06.918] <TB2> INFO: Test took 3994ms.
[14:29:07.207] <TB2> INFO: Expecting 2560 events.
[14:29:08.094] <TB2> INFO: 2560 events read in total (296ms).
[14:29:08.094] <TB2> INFO: Test took 1164ms.
[14:29:08.402] <TB2> INFO: Expecting 2560 events.
[14:29:09.286] <TB2> INFO: 2560 events read in total (293ms).
[14:29:09.286] <TB2> INFO: Test took 1192ms.
[14:29:09.593] <TB2> INFO: Expecting 2560 events.
[14:29:10.477] <TB2> INFO: 2560 events read in total (292ms).
[14:29:10.477] <TB2> INFO: Test took 1191ms.
[14:29:10.784] <TB2> INFO: Expecting 2560 events.
[14:29:11.672] <TB2> INFO: 2560 events read in total (296ms).
[14:29:11.672] <TB2> INFO: Test took 1195ms.
[14:29:11.980] <TB2> INFO: Expecting 2560 events.
[14:29:12.859] <TB2> INFO: 2560 events read in total (287ms).
[14:29:12.859] <TB2> INFO: Test took 1186ms.
[14:29:13.167] <TB2> INFO: Expecting 2560 events.
[14:29:14.045] <TB2> INFO: 2560 events read in total (287ms).
[14:29:14.045] <TB2> INFO: Test took 1186ms.
[14:29:14.353] <TB2> INFO: Expecting 2560 events.
[14:29:15.234] <TB2> INFO: 2560 events read in total (290ms).
[14:29:15.235] <TB2> INFO: Test took 1190ms.
[14:29:15.543] <TB2> INFO: Expecting 2560 events.
[14:29:16.421] <TB2> INFO: 2560 events read in total (287ms).
[14:29:16.421] <TB2> INFO: Test took 1186ms.
[14:29:16.730] <TB2> INFO: Expecting 2560 events.
[14:29:17.609] <TB2> INFO: 2560 events read in total (288ms).
[14:29:17.609] <TB2> INFO: Test took 1187ms.
[14:29:17.917] <TB2> INFO: Expecting 2560 events.
[14:29:18.796] <TB2> INFO: 2560 events read in total (288ms).
[14:29:18.796] <TB2> INFO: Test took 1186ms.
[14:29:19.104] <TB2> INFO: Expecting 2560 events.
[14:29:19.983] <TB2> INFO: 2560 events read in total (287ms).
[14:29:19.984] <TB2> INFO: Test took 1187ms.
[14:29:20.291] <TB2> INFO: Expecting 2560 events.
[14:29:21.171] <TB2> INFO: 2560 events read in total (288ms).
[14:29:21.171] <TB2> INFO: Test took 1187ms.
[14:29:21.479] <TB2> INFO: Expecting 2560 events.
[14:29:22.367] <TB2> INFO: 2560 events read in total (296ms).
[14:29:22.367] <TB2> INFO: Test took 1195ms.
[14:29:22.675] <TB2> INFO: Expecting 2560 events.
[14:29:23.559] <TB2> INFO: 2560 events read in total (292ms).
[14:29:23.559] <TB2> INFO: Test took 1192ms.
[14:29:23.866] <TB2> INFO: Expecting 2560 events.
[14:29:24.750] <TB2> INFO: 2560 events read in total (292ms).
[14:29:24.750] <TB2> INFO: Test took 1191ms.
[14:29:25.058] <TB2> INFO: Expecting 2560 events.
[14:29:25.942] <TB2> INFO: 2560 events read in total (292ms).
[14:29:25.942] <TB2> INFO: Test took 1191ms.
[14:29:25.945] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:26.251] <TB2> INFO: Expecting 655360 events.
[14:29:40.780] <TB2> INFO: 655360 events read in total (13938ms).
[14:29:40.791] <TB2> INFO: Expecting 655360 events.
[14:29:55.260] <TB2> INFO: 655360 events read in total (14066ms).
[14:29:55.274] <TB2> INFO: Expecting 655360 events.
[14:30:09.761] <TB2> INFO: 655360 events read in total (14084ms).
[14:30:09.780] <TB2> INFO: Expecting 655360 events.
[14:30:24.215] <TB2> INFO: 655360 events read in total (14032ms).
[14:30:24.238] <TB2> INFO: Expecting 655360 events.
[14:30:38.646] <TB2> INFO: 655360 events read in total (14005ms).
[14:30:38.685] <TB2> INFO: Expecting 655360 events.
[14:30:53.196] <TB2> INFO: 655360 events read in total (14108ms).
[14:30:53.227] <TB2> INFO: Expecting 655360 events.
[14:31:07.782] <TB2> INFO: 655360 events read in total (14152ms).
[14:31:07.818] <TB2> INFO: Expecting 655360 events.
[14:31:22.368] <TB2> INFO: 655360 events read in total (14147ms).
[14:31:22.407] <TB2> INFO: Expecting 655360 events.
[14:31:36.980] <TB2> INFO: 655360 events read in total (14170ms).
[14:31:37.044] <TB2> INFO: Expecting 655360 events.
[14:31:51.563] <TB2> INFO: 655360 events read in total (14116ms).
[14:31:51.636] <TB2> INFO: Expecting 655360 events.
[14:32:06.219] <TB2> INFO: 655360 events read in total (14180ms).
[14:32:06.273] <TB2> INFO: Expecting 655360 events.
[14:32:20.737] <TB2> INFO: 655360 events read in total (14061ms).
[14:32:20.794] <TB2> INFO: Expecting 655360 events.
[14:32:35.309] <TB2> INFO: 655360 events read in total (14112ms).
[14:32:35.370] <TB2> INFO: Expecting 655360 events.
[14:32:49.886] <TB2> INFO: 655360 events read in total (14112ms).
[14:32:49.952] <TB2> INFO: Expecting 655360 events.
[14:33:04.514] <TB2> INFO: 655360 events read in total (14159ms).
[14:33:04.616] <TB2> INFO: Expecting 655360 events.
[14:33:19.217] <TB2> INFO: 655360 events read in total (14198ms).
[14:33:19.292] <TB2> INFO: Test took 233347ms.
[14:33:19.370] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:33:19.635] <TB2> INFO: Expecting 655360 events.
[14:33:34.348] <TB2> INFO: 655360 events read in total (14122ms).
[14:33:34.359] <TB2> INFO: Expecting 655360 events.
[14:33:48.679] <TB2> INFO: 655360 events read in total (13917ms).
[14:33:48.700] <TB2> INFO: Expecting 655360 events.
[14:34:03.268] <TB2> INFO: 655360 events read in total (14165ms).
[14:34:03.292] <TB2> INFO: Expecting 655360 events.
[14:34:17.705] <TB2> INFO: 655360 events read in total (14010ms).
[14:34:17.728] <TB2> INFO: Expecting 655360 events.
[14:34:32.116] <TB2> INFO: 655360 events read in total (13985ms).
[14:34:32.143] <TB2> INFO: Expecting 655360 events.
[14:34:46.561] <TB2> INFO: 655360 events read in total (14015ms).
[14:34:46.606] <TB2> INFO: Expecting 655360 events.
[14:35:01.154] <TB2> INFO: 655360 events read in total (14145ms).
[14:35:01.189] <TB2> INFO: Expecting 655360 events.
[14:35:15.621] <TB2> INFO: 655360 events read in total (14029ms).
[14:35:15.671] <TB2> INFO: Expecting 655360 events.
[14:35:29.913] <TB2> INFO: 655360 events read in total (13839ms).
[14:35:29.955] <TB2> INFO: Expecting 655360 events.
[14:35:44.718] <TB2> INFO: 655360 events read in total (14360ms).
[14:35:44.791] <TB2> INFO: Expecting 655360 events.
[14:35:59.305] <TB2> INFO: 655360 events read in total (14111ms).
[14:35:59.358] <TB2> INFO: Expecting 655360 events.
[14:36:13.001] <TB2> INFO: 655360 events read in total (14240ms).
[14:36:14.088] <TB2> INFO: Expecting 655360 events.
[14:36:28.510] <TB2> INFO: 655360 events read in total (14019ms).
[14:36:28.570] <TB2> INFO: Expecting 655360 events.
[14:36:43.215] <TB2> INFO: 655360 events read in total (14242ms).
[14:36:43.311] <TB2> INFO: Expecting 655360 events.
[14:36:57.810] <TB2> INFO: 655360 events read in total (14096ms).
[14:36:57.880] <TB2> INFO: Expecting 655360 events.
[14:37:12.229] <TB2> INFO: 655360 events read in total (13946ms).
[14:37:12.302] <TB2> INFO: Test took 232932ms.
[14:37:12.459] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.464] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.468] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:37:12.475] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:37:12.482] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:37:12.488] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:37:12.495] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:37:12.502] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.509] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.515] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:37:12.522] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:37:12.529] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.536] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:37:12.543] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:37:12.550] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.557] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.564] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.570] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:37:12.577] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:37:12.584] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:37:12.591] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:37:12.598] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:37:12.605] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.612] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.619] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.626] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:37:12.633] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.640] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.647] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:37:12.654] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:37:12.661] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:37:12.667] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:37:12.674] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:37:12.681] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.688] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.695] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:12.730] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C0.dat
[14:37:12.730] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C1.dat
[14:37:12.730] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C2.dat
[14:37:12.730] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C3.dat
[14:37:12.730] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C4.dat
[14:37:12.731] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C5.dat
[14:37:12.731] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C6.dat
[14:37:12.731] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C7.dat
[14:37:12.731] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C8.dat
[14:37:12.731] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C9.dat
[14:37:12.731] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C10.dat
[14:37:12.731] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C11.dat
[14:37:12.731] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C12.dat
[14:37:12.731] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C13.dat
[14:37:12.731] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C14.dat
[14:37:12.731] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C15.dat
[14:37:12.965] <TB2> INFO: Expecting 41600 events.
[14:37:16.166] <TB2> INFO: 41600 events read in total (2610ms).
[14:37:16.167] <TB2> INFO: Test took 3433ms.
[14:37:16.675] <TB2> INFO: Expecting 41600 events.
[14:37:19.734] <TB2> INFO: 41600 events read in total (2468ms).
[14:37:19.735] <TB2> INFO: Test took 3354ms.
[14:37:20.204] <TB2> INFO: Expecting 41600 events.
[14:37:23.366] <TB2> INFO: 41600 events read in total (2570ms).
[14:37:23.366] <TB2> INFO: Test took 3420ms.
[14:37:23.581] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:23.669] <TB2> INFO: Expecting 2560 events.
[14:37:24.553] <TB2> INFO: 2560 events read in total (292ms).
[14:37:24.553] <TB2> INFO: Test took 972ms.
[14:37:24.555] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:24.862] <TB2> INFO: Expecting 2560 events.
[14:37:25.746] <TB2> INFO: 2560 events read in total (293ms).
[14:37:25.746] <TB2> INFO: Test took 1191ms.
[14:37:25.748] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:26.054] <TB2> INFO: Expecting 2560 events.
[14:37:26.938] <TB2> INFO: 2560 events read in total (292ms).
[14:37:26.939] <TB2> INFO: Test took 1191ms.
[14:37:26.940] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:27.247] <TB2> INFO: Expecting 2560 events.
[14:37:28.131] <TB2> INFO: 2560 events read in total (293ms).
[14:37:28.131] <TB2> INFO: Test took 1191ms.
[14:37:28.133] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:28.440] <TB2> INFO: Expecting 2560 events.
[14:37:29.324] <TB2> INFO: 2560 events read in total (293ms).
[14:37:29.325] <TB2> INFO: Test took 1192ms.
[14:37:29.326] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:29.633] <TB2> INFO: Expecting 2560 events.
[14:37:30.517] <TB2> INFO: 2560 events read in total (293ms).
[14:37:30.517] <TB2> INFO: Test took 1191ms.
[14:37:30.519] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:30.826] <TB2> INFO: Expecting 2560 events.
[14:37:31.710] <TB2> INFO: 2560 events read in total (293ms).
[14:37:31.710] <TB2> INFO: Test took 1191ms.
[14:37:31.712] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:32.018] <TB2> INFO: Expecting 2560 events.
[14:37:32.903] <TB2> INFO: 2560 events read in total (293ms).
[14:37:32.903] <TB2> INFO: Test took 1191ms.
[14:37:32.905] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:33.211] <TB2> INFO: Expecting 2560 events.
[14:37:34.090] <TB2> INFO: 2560 events read in total (288ms).
[14:37:34.091] <TB2> INFO: Test took 1186ms.
[14:37:34.093] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:34.399] <TB2> INFO: Expecting 2560 events.
[14:37:35.279] <TB2> INFO: 2560 events read in total (288ms).
[14:37:35.279] <TB2> INFO: Test took 1186ms.
[14:37:35.281] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:35.588] <TB2> INFO: Expecting 2560 events.
[14:37:36.472] <TB2> INFO: 2560 events read in total (294ms).
[14:37:36.473] <TB2> INFO: Test took 1192ms.
[14:37:36.475] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:36.781] <TB2> INFO: Expecting 2560 events.
[14:37:37.661] <TB2> INFO: 2560 events read in total (289ms).
[14:37:37.661] <TB2> INFO: Test took 1186ms.
[14:37:37.663] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:37.969] <TB2> INFO: Expecting 2560 events.
[14:37:38.849] <TB2> INFO: 2560 events read in total (288ms).
[14:37:38.850] <TB2> INFO: Test took 1187ms.
[14:37:38.852] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:39.158] <TB2> INFO: Expecting 2560 events.
[14:37:40.038] <TB2> INFO: 2560 events read in total (288ms).
[14:37:40.039] <TB2> INFO: Test took 1188ms.
[14:37:40.040] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:40.347] <TB2> INFO: Expecting 2560 events.
[14:37:41.230] <TB2> INFO: 2560 events read in total (292ms).
[14:37:41.230] <TB2> INFO: Test took 1190ms.
[14:37:41.232] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:41.538] <TB2> INFO: Expecting 2560 events.
[14:37:42.417] <TB2> INFO: 2560 events read in total (287ms).
[14:37:42.417] <TB2> INFO: Test took 1185ms.
[14:37:42.419] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:42.725] <TB2> INFO: Expecting 2560 events.
[14:37:43.606] <TB2> INFO: 2560 events read in total (289ms).
[14:37:43.606] <TB2> INFO: Test took 1187ms.
[14:37:43.608] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:43.914] <TB2> INFO: Expecting 2560 events.
[14:37:44.797] <TB2> INFO: 2560 events read in total (291ms).
[14:37:44.798] <TB2> INFO: Test took 1190ms.
[14:37:44.799] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:45.106] <TB2> INFO: Expecting 2560 events.
[14:37:45.986] <TB2> INFO: 2560 events read in total (288ms).
[14:37:45.986] <TB2> INFO: Test took 1187ms.
[14:37:45.988] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:46.295] <TB2> INFO: Expecting 2560 events.
[14:37:47.179] <TB2> INFO: 2560 events read in total (292ms).
[14:37:47.179] <TB2> INFO: Test took 1191ms.
[14:37:47.181] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:47.487] <TB2> INFO: Expecting 2560 events.
[14:37:48.366] <TB2> INFO: 2560 events read in total (288ms).
[14:37:48.367] <TB2> INFO: Test took 1186ms.
[14:37:48.369] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:48.675] <TB2> INFO: Expecting 2560 events.
[14:37:49.559] <TB2> INFO: 2560 events read in total (292ms).
[14:37:49.559] <TB2> INFO: Test took 1191ms.
[14:37:49.561] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:49.867] <TB2> INFO: Expecting 2560 events.
[14:37:50.746] <TB2> INFO: 2560 events read in total (288ms).
[14:37:50.746] <TB2> INFO: Test took 1185ms.
[14:37:50.748] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:51.055] <TB2> INFO: Expecting 2560 events.
[14:37:51.934] <TB2> INFO: 2560 events read in total (287ms).
[14:37:51.935] <TB2> INFO: Test took 1187ms.
[14:37:51.936] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:52.243] <TB2> INFO: Expecting 2560 events.
[14:37:53.132] <TB2> INFO: 2560 events read in total (297ms).
[14:37:53.132] <TB2> INFO: Test took 1196ms.
[14:37:53.134] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:53.440] <TB2> INFO: Expecting 2560 events.
[14:37:54.327] <TB2> INFO: 2560 events read in total (295ms).
[14:37:54.328] <TB2> INFO: Test took 1194ms.
[14:37:54.329] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:54.636] <TB2> INFO: Expecting 2560 events.
[14:37:55.520] <TB2> INFO: 2560 events read in total (292ms).
[14:37:55.520] <TB2> INFO: Test took 1191ms.
[14:37:55.522] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:55.828] <TB2> INFO: Expecting 2560 events.
[14:37:56.717] <TB2> INFO: 2560 events read in total (297ms).
[14:37:56.717] <TB2> INFO: Test took 1195ms.
[14:37:56.719] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:57.025] <TB2> INFO: Expecting 2560 events.
[14:37:57.912] <TB2> INFO: 2560 events read in total (296ms).
[14:37:57.913] <TB2> INFO: Test took 1194ms.
[14:37:57.914] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:58.221] <TB2> INFO: Expecting 2560 events.
[14:37:59.103] <TB2> INFO: 2560 events read in total (290ms).
[14:37:59.103] <TB2> INFO: Test took 1189ms.
[14:37:59.105] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:59.412] <TB2> INFO: Expecting 2560 events.
[14:38:00.297] <TB2> INFO: 2560 events read in total (293ms).
[14:38:00.297] <TB2> INFO: Test took 1192ms.
[14:38:00.300] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:38:00.605] <TB2> INFO: Expecting 2560 events.
[14:38:01.493] <TB2> INFO: 2560 events read in total (296ms).
[14:38:01.493] <TB2> INFO: Test took 1194ms.
[14:38:01.954] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 651 seconds
[14:38:01.954] <TB2> INFO: PH scale (per ROC): 49 47 44 34 50 48 37 48 43 37 48 48 44 40 49 47
[14:38:01.954] <TB2> INFO: PH offset (per ROC): 114 97 87 100 123 123 95 94 129 95 114 133 97 110 100 122
[14:38:01.960] <TB2> INFO: Decoding statistics:
[14:38:01.960] <TB2> INFO: General information:
[14:38:01.960] <TB2> INFO: 16bit words read: 127868
[14:38:01.961] <TB2> INFO: valid events total: 20480
[14:38:01.961] <TB2> INFO: empty events: 17986
[14:38:01.961] <TB2> INFO: valid events with pixels: 2494
[14:38:01.961] <TB2> INFO: valid pixel hits: 2494
[14:38:01.961] <TB2> INFO: Event errors: 0
[14:38:01.961] <TB2> INFO: start marker: 0
[14:38:01.961] <TB2> INFO: stop marker: 0
[14:38:01.961] <TB2> INFO: overflow: 0
[14:38:01.961] <TB2> INFO: invalid 5bit words: 0
[14:38:01.961] <TB2> INFO: invalid XOR eye diagram: 0
[14:38:01.961] <TB2> INFO: frame (failed synchr.): 0
[14:38:01.961] <TB2> INFO: idle data (no TBM trl): 0
[14:38:01.961] <TB2> INFO: no data (only TBM hdr): 0
[14:38:01.961] <TB2> INFO: TBM errors: 0
[14:38:01.961] <TB2> INFO: flawed TBM headers: 0
[14:38:01.961] <TB2> INFO: flawed TBM trailers: 0
[14:38:01.961] <TB2> INFO: event ID mismatches: 0
[14:38:01.961] <TB2> INFO: ROC errors: 0
[14:38:01.961] <TB2> INFO: missing ROC header(s): 0
[14:38:01.961] <TB2> INFO: misplaced readback start: 0
[14:38:01.961] <TB2> INFO: Pixel decoding errors: 0
[14:38:01.961] <TB2> INFO: pixel data incomplete: 0
[14:38:01.961] <TB2> INFO: pixel address: 0
[14:38:01.961] <TB2> INFO: pulse height fill bit: 0
[14:38:01.961] <TB2> INFO: buffer corruption: 0
[14:38:02.343] <TB2> INFO: ######################################################################
[14:38:02.343] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[14:38:02.343] <TB2> INFO: ######################################################################
[14:38:02.356] <TB2> INFO: scanning low vcal = 10
[14:38:02.650] <TB2> INFO: Expecting 41600 events.
[14:38:06.251] <TB2> INFO: 41600 events read in total (3009ms).
[14:38:06.251] <TB2> INFO: Test took 3895ms.
[14:38:06.253] <TB2> INFO: scanning low vcal = 20
[14:38:06.553] <TB2> INFO: Expecting 41600 events.
[14:38:10.150] <TB2> INFO: 41600 events read in total (3006ms).
[14:38:10.150] <TB2> INFO: Test took 3896ms.
[14:38:10.153] <TB2> INFO: scanning low vcal = 30
[14:38:10.451] <TB2> INFO: Expecting 41600 events.
[14:38:14.100] <TB2> INFO: 41600 events read in total (3058ms).
[14:38:14.101] <TB2> INFO: Test took 3948ms.
[14:38:14.103] <TB2> INFO: scanning low vcal = 40
[14:38:14.380] <TB2> INFO: Expecting 41600 events.
[14:38:18.361] <TB2> INFO: 41600 events read in total (3389ms).
[14:38:18.362] <TB2> INFO: Test took 4259ms.
[14:38:18.365] <TB2> INFO: scanning low vcal = 50
[14:38:18.641] <TB2> INFO: Expecting 41600 events.
[14:38:22.620] <TB2> INFO: 41600 events read in total (3387ms).
[14:38:22.621] <TB2> INFO: Test took 4256ms.
[14:38:22.624] <TB2> INFO: scanning low vcal = 60
[14:38:22.900] <TB2> INFO: Expecting 41600 events.
[14:38:26.925] <TB2> INFO: 41600 events read in total (3433ms).
[14:38:26.926] <TB2> INFO: Test took 4302ms.
[14:38:26.928] <TB2> INFO: scanning low vcal = 70
[14:38:27.205] <TB2> INFO: Expecting 41600 events.
[14:38:31.255] <TB2> INFO: 41600 events read in total (3458ms).
[14:38:31.256] <TB2> INFO: Test took 4328ms.
[14:38:31.259] <TB2> INFO: scanning low vcal = 80
[14:38:31.536] <TB2> INFO: Expecting 41600 events.
[14:38:35.517] <TB2> INFO: 41600 events read in total (3390ms).
[14:38:35.518] <TB2> INFO: Test took 4259ms.
[14:38:35.521] <TB2> INFO: scanning low vcal = 90
[14:38:35.798] <TB2> INFO: Expecting 41600 events.
[14:38:39.781] <TB2> INFO: 41600 events read in total (3392ms).
[14:38:39.782] <TB2> INFO: Test took 4261ms.
[14:38:39.784] <TB2> INFO: scanning low vcal = 100
[14:38:40.061] <TB2> INFO: Expecting 41600 events.
[14:38:44.064] <TB2> INFO: 41600 events read in total (3411ms).
[14:38:44.065] <TB2> INFO: Test took 4280ms.
[14:38:44.068] <TB2> INFO: scanning low vcal = 110
[14:38:44.345] <TB2> INFO: Expecting 41600 events.
[14:38:48.360] <TB2> INFO: 41600 events read in total (3424ms).
[14:38:48.361] <TB2> INFO: Test took 4293ms.
[14:38:48.364] <TB2> INFO: scanning low vcal = 120
[14:38:48.640] <TB2> INFO: Expecting 41600 events.
[14:38:52.643] <TB2> INFO: 41600 events read in total (3411ms).
[14:38:52.644] <TB2> INFO: Test took 4280ms.
[14:38:52.647] <TB2> INFO: scanning low vcal = 130
[14:38:52.933] <TB2> INFO: Expecting 41600 events.
[14:38:56.932] <TB2> INFO: 41600 events read in total (3407ms).
[14:38:56.933] <TB2> INFO: Test took 4286ms.
[14:38:56.935] <TB2> INFO: scanning low vcal = 140
[14:38:57.212] <TB2> INFO: Expecting 41600 events.
[14:39:01.207] <TB2> INFO: 41600 events read in total (3404ms).
[14:39:01.208] <TB2> INFO: Test took 4273ms.
[14:39:01.210] <TB2> INFO: scanning low vcal = 150
[14:39:01.509] <TB2> INFO: Expecting 41600 events.
[14:39:05.477] <TB2> INFO: 41600 events read in total (3376ms).
[14:39:05.478] <TB2> INFO: Test took 4267ms.
[14:39:05.480] <TB2> INFO: scanning low vcal = 160
[14:39:05.757] <TB2> INFO: Expecting 41600 events.
[14:39:09.729] <TB2> INFO: 41600 events read in total (3380ms).
[14:39:09.730] <TB2> INFO: Test took 4249ms.
[14:39:09.732] <TB2> INFO: scanning low vcal = 170
[14:39:10.009] <TB2> INFO: Expecting 41600 events.
[14:39:14.021] <TB2> INFO: 41600 events read in total (3420ms).
[14:39:14.021] <TB2> INFO: Test took 4288ms.
[14:39:14.024] <TB2> INFO: scanning low vcal = 180
[14:39:14.301] <TB2> INFO: Expecting 41600 events.
[14:39:18.276] <TB2> INFO: 41600 events read in total (3384ms).
[14:39:18.276] <TB2> INFO: Test took 4252ms.
[14:39:18.279] <TB2> INFO: scanning low vcal = 190
[14:39:18.555] <TB2> INFO: Expecting 41600 events.
[14:39:22.539] <TB2> INFO: 41600 events read in total (3392ms).
[14:39:22.540] <TB2> INFO: Test took 4261ms.
[14:39:22.543] <TB2> INFO: scanning low vcal = 200
[14:39:22.820] <TB2> INFO: Expecting 41600 events.
[14:39:26.824] <TB2> INFO: 41600 events read in total (3413ms).
[14:39:26.825] <TB2> INFO: Test took 4282ms.
[14:39:26.828] <TB2> INFO: scanning low vcal = 210
[14:39:27.105] <TB2> INFO: Expecting 41600 events.
[14:39:31.093] <TB2> INFO: 41600 events read in total (3397ms).
[14:39:31.094] <TB2> INFO: Test took 4266ms.
[14:39:31.096] <TB2> INFO: scanning low vcal = 220
[14:39:31.386] <TB2> INFO: Expecting 41600 events.
[14:39:35.393] <TB2> INFO: 41600 events read in total (3415ms).
[14:39:35.394] <TB2> INFO: Test took 4297ms.
[14:39:35.396] <TB2> INFO: scanning low vcal = 230
[14:39:35.673] <TB2> INFO: Expecting 41600 events.
[14:39:39.693] <TB2> INFO: 41600 events read in total (3429ms).
[14:39:39.693] <TB2> INFO: Test took 4297ms.
[14:39:39.696] <TB2> INFO: scanning low vcal = 240
[14:39:39.973] <TB2> INFO: Expecting 41600 events.
[14:39:43.952] <TB2> INFO: 41600 events read in total (3388ms).
[14:39:43.953] <TB2> INFO: Test took 4257ms.
[14:39:43.955] <TB2> INFO: scanning low vcal = 250
[14:39:44.252] <TB2> INFO: Expecting 41600 events.
[14:39:48.253] <TB2> INFO: 41600 events read in total (3409ms).
[14:39:48.254] <TB2> INFO: Test took 4299ms.
[14:39:48.257] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[14:39:48.533] <TB2> INFO: Expecting 41600 events.
[14:39:52.563] <TB2> INFO: 41600 events read in total (3438ms).
[14:39:52.563] <TB2> INFO: Test took 4306ms.
[14:39:52.566] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[14:39:52.843] <TB2> INFO: Expecting 41600 events.
[14:39:56.792] <TB2> INFO: 41600 events read in total (3358ms).
[14:39:56.793] <TB2> INFO: Test took 4227ms.
[14:39:56.795] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[14:39:57.072] <TB2> INFO: Expecting 41600 events.
[14:40:01.085] <TB2> INFO: 41600 events read in total (3421ms).
[14:40:01.086] <TB2> INFO: Test took 4291ms.
[14:40:01.089] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[14:40:01.366] <TB2> INFO: Expecting 41600 events.
[14:40:05.348] <TB2> INFO: 41600 events read in total (3391ms).
[14:40:05.349] <TB2> INFO: Test took 4260ms.
[14:40:05.352] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[14:40:05.629] <TB2> INFO: Expecting 41600 events.
[14:40:09.573] <TB2> INFO: 41600 events read in total (3353ms).
[14:40:09.574] <TB2> INFO: Test took 4221ms.
[14:40:10.159] <TB2> INFO: PixTestGainPedestal::measure() done
[14:40:44.166] <TB2> INFO: PixTestGainPedestal::fit() done
[14:40:44.166] <TB2> INFO: non-linearity mean: 0.976 0.952 0.925 0.979 0.970 0.980 0.932 0.974 0.972 0.930 0.963 0.975 0.918 0.936 0.963 0.974
[14:40:44.166] <TB2> INFO: non-linearity RMS: 0.006 0.052 0.089 0.183 0.012 0.004 0.105 0.009 0.007 0.074 0.019 0.007 0.110 0.067 0.023 0.006
[14:40:44.166] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[14:40:44.180] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[14:40:44.193] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[14:40:44.207] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[14:40:44.221] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[14:40:44.234] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[14:40:44.255] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[14:40:44.276] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[14:40:44.297] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[14:40:44.318] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[14:40:44.340] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[14:40:44.362] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[14:40:44.383] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[14:40:44.405] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[14:40:44.427] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[14:40:44.449] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[14:40:44.470] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 162 seconds
[14:40:44.470] <TB2> INFO: Decoding statistics:
[14:40:44.470] <TB2> INFO: General information:
[14:40:44.470] <TB2> INFO: 16bit words read: 3287716
[14:40:44.470] <TB2> INFO: valid events total: 332800
[14:40:44.470] <TB2> INFO: empty events: 341
[14:40:44.470] <TB2> INFO: valid events with pixels: 332459
[14:40:44.470] <TB2> INFO: valid pixel hits: 645458
[14:40:44.471] <TB2> INFO: Event errors: 0
[14:40:44.471] <TB2> INFO: start marker: 0
[14:40:44.471] <TB2> INFO: stop marker: 0
[14:40:44.471] <TB2> INFO: overflow: 0
[14:40:44.471] <TB2> INFO: invalid 5bit words: 0
[14:40:44.471] <TB2> INFO: invalid XOR eye diagram: 0
[14:40:44.471] <TB2> INFO: frame (failed synchr.): 0
[14:40:44.471] <TB2> INFO: idle data (no TBM trl): 0
[14:40:44.471] <TB2> INFO: no data (only TBM hdr): 0
[14:40:44.471] <TB2> INFO: TBM errors: 0
[14:40:44.471] <TB2> INFO: flawed TBM headers: 0
[14:40:44.471] <TB2> INFO: flawed TBM trailers: 0
[14:40:44.471] <TB2> INFO: event ID mismatches: 0
[14:40:44.471] <TB2> INFO: ROC errors: 0
[14:40:44.471] <TB2> INFO: missing ROC header(s): 0
[14:40:44.471] <TB2> INFO: misplaced readback start: 0
[14:40:44.471] <TB2> INFO: Pixel decoding errors: 0
[14:40:44.471] <TB2> INFO: pixel data incomplete: 0
[14:40:44.471] <TB2> INFO: pixel address: 0
[14:40:44.471] <TB2> INFO: pulse height fill bit: 0
[14:40:44.471] <TB2> INFO: buffer corruption: 0
[14:40:44.493] <TB2> INFO: Decoding statistics:
[14:40:44.493] <TB2> INFO: General information:
[14:40:44.493] <TB2> INFO: 16bit words read: 3417120
[14:40:44.493] <TB2> INFO: valid events total: 353536
[14:40:44.493] <TB2> INFO: empty events: 18583
[14:40:44.493] <TB2> INFO: valid events with pixels: 334953
[14:40:44.493] <TB2> INFO: valid pixel hits: 647952
[14:40:44.493] <TB2> INFO: Event errors: 0
[14:40:44.493] <TB2> INFO: start marker: 0
[14:40:44.493] <TB2> INFO: stop marker: 0
[14:40:44.493] <TB2> INFO: overflow: 0
[14:40:44.493] <TB2> INFO: invalid 5bit words: 0
[14:40:44.493] <TB2> INFO: invalid XOR eye diagram: 0
[14:40:44.493] <TB2> INFO: frame (failed synchr.): 0
[14:40:44.493] <TB2> INFO: idle data (no TBM trl): 0
[14:40:44.493] <TB2> INFO: no data (only TBM hdr): 0
[14:40:44.493] <TB2> INFO: TBM errors: 0
[14:40:44.493] <TB2> INFO: flawed TBM headers: 0
[14:40:44.493] <TB2> INFO: flawed TBM trailers: 0
[14:40:44.493] <TB2> INFO: event ID mismatches: 0
[14:40:44.493] <TB2> INFO: ROC errors: 0
[14:40:44.493] <TB2> INFO: missing ROC header(s): 0
[14:40:44.493] <TB2> INFO: misplaced readback start: 0
[14:40:44.493] <TB2> INFO: Pixel decoding errors: 0
[14:40:44.493] <TB2> INFO: pixel data incomplete: 0
[14:40:44.493] <TB2> INFO: pixel address: 0
[14:40:44.493] <TB2> INFO: pulse height fill bit: 0
[14:40:44.494] <TB2> INFO: buffer corruption: 0
[14:40:44.494] <TB2> INFO: enter test to run
[14:40:44.494] <TB2> INFO: test: Trim80 no parameter change
[14:40:44.494] <TB2> INFO: running: trim80
[14:40:44.515] <TB2> INFO: ######################################################################
[14:40:44.515] <TB2> INFO: PixTestTrim80::doTest()
[14:40:44.515] <TB2> INFO: ######################################################################
[14:40:44.516] <TB2> INFO: ----------------------------------------------------------------------
[14:40:44.516] <TB2> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[14:40:44.516] <TB2> INFO: ----------------------------------------------------------------------
[14:40:44.557] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:40:44.557] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:40:44.565] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:40:44.565] <TB2> INFO: run 1 of 1
[14:40:44.797] <TB2> INFO: Expecting 5025280 events.
[14:41:13.028] <TB2> INFO: 674952 events read in total (27640ms).
[14:41:40.725] <TB2> INFO: 1347152 events read in total (55337ms).
[14:42:08.013] <TB2> INFO: 2016568 events read in total (82626ms).
[14:42:35.966] <TB2> INFO: 2683000 events read in total (110578ms).
[14:43:03.866] <TB2> INFO: 3347024 events read in total (138478ms).
[14:43:30.835] <TB2> INFO: 4008312 events read in total (165447ms).
[14:43:58.145] <TB2> INFO: 4667104 events read in total (192757ms).
[14:44:13.340] <TB2> INFO: 5025280 events read in total (207952ms).
[14:44:13.396] <TB2> INFO: Test took 208830ms.
[14:44:37.132] <TB2> INFO: ROC 0 VthrComp = 71
[14:44:37.132] <TB2> INFO: ROC 1 VthrComp = 81
[14:44:37.132] <TB2> INFO: ROC 2 VthrComp = 74
[14:44:37.132] <TB2> INFO: ROC 3 VthrComp = 73
[14:44:37.132] <TB2> INFO: ROC 4 VthrComp = 89
[14:44:37.133] <TB2> INFO: ROC 5 VthrComp = 80
[14:44:37.133] <TB2> INFO: ROC 6 VthrComp = 82
[14:44:37.133] <TB2> INFO: ROC 7 VthrComp = 83
[14:44:37.133] <TB2> INFO: ROC 8 VthrComp = 73
[14:44:37.133] <TB2> INFO: ROC 9 VthrComp = 82
[14:44:37.133] <TB2> INFO: ROC 10 VthrComp = 72
[14:44:37.134] <TB2> INFO: ROC 11 VthrComp = 68
[14:44:37.134] <TB2> INFO: ROC 12 VthrComp = 72
[14:44:37.135] <TB2> INFO: ROC 13 VthrComp = 72
[14:44:37.135] <TB2> INFO: ROC 14 VthrComp = 74
[14:44:37.135] <TB2> INFO: ROC 15 VthrComp = 74
[14:44:37.371] <TB2> INFO: Expecting 41600 events.
[14:44:40.890] <TB2> INFO: 41600 events read in total (2927ms).
[14:44:40.891] <TB2> INFO: Test took 3755ms.
[14:44:40.899] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:44:40.899] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:44:40.909] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:44:40.909] <TB2> INFO: run 1 of 1
[14:44:41.187] <TB2> INFO: Expecting 5025280 events.
[14:45:09.351] <TB2> INFO: 683344 events read in total (27573ms).
[14:45:37.331] <TB2> INFO: 1362080 events read in total (55553ms).
[14:46:05.423] <TB2> INFO: 2040016 events read in total (83645ms).
[14:46:32.886] <TB2> INFO: 2716832 events read in total (111108ms).
[14:47:00.458] <TB2> INFO: 3389536 events read in total (138680ms).
[14:47:28.143] <TB2> INFO: 4061520 events read in total (166365ms).
[14:47:55.504] <TB2> INFO: 4731840 events read in total (193726ms).
[14:48:07.650] <TB2> INFO: 5025280 events read in total (205872ms).
[14:48:07.700] <TB2> INFO: Test took 206791ms.
[14:48:28.868] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 105.166 for pixel 3/79 mean/min/max = 90.1811/75.0802/105.282
[14:48:28.869] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 103.306 for pixel 8/61 mean/min/max = 89.5306/75.5186/103.543
[14:48:28.869] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 109.093 for pixel 2/79 mean/min/max = 93.8649/78.6301/109.1
[14:48:28.870] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 110.604 for pixel 0/46 mean/min/max = 93.9008/77.1462/110.655
[14:48:28.870] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 108.732 for pixel 0/15 mean/min/max = 92.6478/76.4983/108.797
[14:48:28.871] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 108.986 for pixel 0/71 mean/min/max = 91.8224/74.6383/109.006
[14:48:28.871] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 103.66 for pixel 17/79 mean/min/max = 89.5659/75.1895/103.942
[14:48:28.871] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 106.787 for pixel 29/79 mean/min/max = 90.8551/74.8924/106.818
[14:48:28.872] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 113.177 for pixel 0/40 mean/min/max = 95.2282/77.1552/113.301
[14:48:28.872] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 107.239 for pixel 0/19 mean/min/max = 91.5444/75.8169/107.272
[14:48:28.873] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 106.033 for pixel 0/59 mean/min/max = 91.2327/76.3791/106.086
[14:48:28.873] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 105.889 for pixel 0/77 mean/min/max = 89.7302/73.5212/105.939
[14:48:28.873] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 105.622 for pixel 0/42 mean/min/max = 91.067/76.03/106.104
[14:48:28.874] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 108.208 for pixel 0/44 mean/min/max = 92.3237/76.3166/108.331
[14:48:28.874] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 105.847 for pixel 31/79 mean/min/max = 91.9321/77.8868/105.977
[14:48:28.875] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 107.311 for pixel 14/1 mean/min/max = 92.3186/77.3143/107.323
[14:48:28.875] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:28.963] <TB2> INFO: Expecting 411648 events.
[14:48:38.314] <TB2> INFO: 411648 events read in total (8759ms).
[14:48:38.325] <TB2> INFO: Expecting 411648 events.
[14:48:47.585] <TB2> INFO: 411648 events read in total (8858ms).
[14:48:47.594] <TB2> INFO: Expecting 411648 events.
[14:48:57.028] <TB2> INFO: 411648 events read in total (9031ms).
[14:48:57.045] <TB2> INFO: Expecting 411648 events.
[14:49:06.264] <TB2> INFO: 411648 events read in total (8816ms).
[14:49:06.278] <TB2> INFO: Expecting 411648 events.
[14:49:15.526] <TB2> INFO: 411648 events read in total (8845ms).
[14:49:15.543] <TB2> INFO: Expecting 411648 events.
[14:49:24.905] <TB2> INFO: 411648 events read in total (8959ms).
[14:49:24.933] <TB2> INFO: Expecting 411648 events.
[14:49:34.206] <TB2> INFO: 411648 events read in total (8870ms).
[14:49:34.239] <TB2> INFO: Expecting 411648 events.
[14:49:43.554] <TB2> INFO: 411648 events read in total (8912ms).
[14:49:43.579] <TB2> INFO: Expecting 411648 events.
[14:49:52.892] <TB2> INFO: 411648 events read in total (8910ms).
[14:49:52.933] <TB2> INFO: Expecting 411648 events.
[14:50:02.239] <TB2> INFO: 411648 events read in total (8903ms).
[14:50:02.285] <TB2> INFO: Expecting 411648 events.
[14:50:11.487] <TB2> INFO: 411648 events read in total (8799ms).
[14:50:11.521] <TB2> INFO: Expecting 411648 events.
[14:50:20.994] <TB2> INFO: 411648 events read in total (9070ms).
[14:50:21.047] <TB2> INFO: Expecting 411648 events.
[14:50:30.269] <TB2> INFO: 411648 events read in total (8819ms).
[14:50:30.308] <TB2> INFO: Expecting 411648 events.
[14:50:39.516] <TB2> INFO: 411648 events read in total (8805ms).
[14:50:39.569] <TB2> INFO: Expecting 411648 events.
[14:50:48.972] <TB2> INFO: 411648 events read in total (9000ms).
[14:50:49.018] <TB2> INFO: Expecting 411648 events.
[14:50:58.233] <TB2> INFO: 411648 events read in total (8812ms).
[14:50:58.301] <TB2> INFO: Test took 149426ms.
[14:50:59.848] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:50:59.859] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:50:59.859] <TB2> INFO: run 1 of 1
[14:51:00.090] <TB2> INFO: Expecting 5025280 events.
[14:51:28.359] <TB2> INFO: 666304 events read in total (27677ms).
[14:51:55.373] <TB2> INFO: 1329944 events read in total (54691ms).
[14:52:22.444] <TB2> INFO: 1992920 events read in total (81762ms).
[14:52:49.613] <TB2> INFO: 2654952 events read in total (108931ms).
[14:53:16.506] <TB2> INFO: 3313152 events read in total (135824ms).
[14:53:43.751] <TB2> INFO: 3969904 events read in total (163069ms).
[14:54:11.048] <TB2> INFO: 4624920 events read in total (190366ms).
[14:54:28.015] <TB2> INFO: 5025280 events read in total (207333ms).
[14:54:28.064] <TB2> INFO: Test took 208205ms.
[14:54:49.554] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 54.368406 .. 109.341220
[14:54:49.787] <TB2> INFO: Expecting 208000 events.
[14:54:59.431] <TB2> INFO: 208000 events read in total (9052ms).
[14:54:59.432] <TB2> INFO: Test took 9876ms.
[14:54:59.478] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 44 .. 119 (-1/-1) hits flags = 528 (plus default)
[14:54:59.488] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:54:59.488] <TB2> INFO: run 1 of 1
[14:54:59.766] <TB2> INFO: Expecting 2529280 events.
[14:55:28.034] <TB2> INFO: 663912 events read in total (27677ms).
[14:55:55.431] <TB2> INFO: 1325784 events read in total (55074ms).
[14:56:23.338] <TB2> INFO: 1981672 events read in total (82981ms).
[14:56:46.054] <TB2> INFO: 2529280 events read in total (105697ms).
[14:56:46.090] <TB2> INFO: Test took 106602ms.
[14:57:02.574] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 64.123371 .. 97.132602
[14:57:02.806] <TB2> INFO: Expecting 208000 events.
[14:57:13.047] <TB2> INFO: 208000 events read in total (9649ms).
[14:57:13.047] <TB2> INFO: Test took 10472ms.
[14:57:13.093] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 54 .. 107 (-1/-1) hits flags = 528 (plus default)
[14:57:13.101] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:57:13.101] <TB2> INFO: run 1 of 1
[14:57:13.379] <TB2> INFO: Expecting 1797120 events.
[14:57:41.699] <TB2> INFO: 664760 events read in total (27728ms).
[14:58:09.860] <TB2> INFO: 1329920 events read in total (55889ms).
[14:58:29.312] <TB2> INFO: 1797120 events read in total (75341ms).
[14:58:29.341] <TB2> INFO: Test took 76241ms.
[14:58:44.559] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 67.834407 .. 91.669345
[14:58:44.813] <TB2> INFO: Expecting 208000 events.
[14:58:54.583] <TB2> INFO: 208000 events read in total (9178ms).
[14:58:54.583] <TB2> INFO: Test took 10022ms.
[14:58:54.630] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 57 .. 101 (-1/-1) hits flags = 528 (plus default)
[14:58:54.640] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:58:54.640] <TB2> INFO: run 1 of 1
[14:58:54.917] <TB2> INFO: Expecting 1497600 events.
[14:59:23.297] <TB2> INFO: 676464 events read in total (27788ms).
[14:59:51.877] <TB2> INFO: 1352208 events read in total (56369ms).
[14:59:58.450] <TB2> INFO: 1497600 events read in total (62941ms).
[14:59:58.473] <TB2> INFO: Test took 63834ms.
[15:00:14.468] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 69.847826 .. 91.669345
[15:00:14.762] <TB2> INFO: Expecting 208000 events.
[15:00:24.536] <TB2> INFO: 208000 events read in total (9182ms).
[15:00:24.537] <TB2> INFO: Test took 10068ms.
[15:00:24.583] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 59 .. 101 (-1/-1) hits flags = 528 (plus default)
[15:00:24.593] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:00:24.593] <TB2> INFO: run 1 of 1
[15:00:24.871] <TB2> INFO: Expecting 1431040 events.
[15:00:53.678] <TB2> INFO: 669536 events read in total (28216ms).
[15:01:21.938] <TB2> INFO: 1338944 events read in total (56476ms).
[15:01:26.162] <TB2> INFO: 1431040 events read in total (60700ms).
[15:01:26.193] <TB2> INFO: Test took 61601ms.
[15:01:41.405] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[15:01:41.405] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[15:01:41.415] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:01:41.415] <TB2> INFO: run 1 of 1
[15:01:41.651] <TB2> INFO: Expecting 1364480 events.
[15:02:09.792] <TB2> INFO: 668304 events read in total (27550ms).
[15:02:37.867] <TB2> INFO: 1336136 events read in total (55626ms).
[15:02:39.515] <TB2> INFO: 1364480 events read in total (57273ms).
[15:02:39.533] <TB2> INFO: Test took 58119ms.
[15:02:56.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C0.dat
[15:02:56.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C1.dat
[15:02:56.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C2.dat
[15:02:56.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C3.dat
[15:02:56.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C4.dat
[15:02:56.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C5.dat
[15:02:56.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C6.dat
[15:02:56.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C7.dat
[15:02:56.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C8.dat
[15:02:56.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C9.dat
[15:02:56.101] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C10.dat
[15:02:56.101] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C11.dat
[15:02:56.101] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C12.dat
[15:02:56.101] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C13.dat
[15:02:56.101] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C14.dat
[15:02:56.101] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C15.dat
[15:02:56.101] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C0.dat
[15:02:56.106] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C1.dat
[15:02:56.112] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C2.dat
[15:02:56.117] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C3.dat
[15:02:56.123] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C4.dat
[15:02:56.128] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C5.dat
[15:02:56.134] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C6.dat
[15:02:56.140] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C7.dat
[15:02:56.145] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C8.dat
[15:02:56.151] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C9.dat
[15:02:56.156] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C10.dat
[15:02:56.162] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C11.dat
[15:02:56.167] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C12.dat
[15:02:56.172] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C13.dat
[15:02:56.178] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C14.dat
[15:02:56.183] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1092_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C15.dat
[15:02:56.188] <TB2> INFO: PixTestTrim80::trimTest() done
[15:02:56.188] <TB2> INFO: vtrim: 100 106 124 111 114 108 101 114 127 113 112 95 102 106 93 114
[15:02:56.188] <TB2> INFO: vthrcomp: 71 81 74 73 89 80 82 83 73 82 72 68 72 72 74 74
[15:02:56.188] <TB2> INFO: vcal mean: 80.01 79.94 79.96 79.92 79.93 79.96 79.93 79.97 79.92 80.00 79.97 79.97 80.03 79.93 79.98 79.92
[15:02:56.189] <TB2> INFO: vcal RMS: 0.73 0.71 0.70 0.70 0.81 0.74 0.70 1.45 0.76 0.77 0.70 0.75 0.72 0.70 0.75 0.75
[15:02:56.189] <TB2> INFO: bits mean: 10.64 11.04 9.80 9.87 10.18 9.72 10.26 10.72 9.76 10.27 10.18 10.51 10.25 9.80 9.67 10.16
[15:02:56.189] <TB2> INFO: bits RMS: 2.16 1.96 1.97 2.08 2.14 2.56 2.37 2.16 2.10 2.24 2.14 2.54 2.19 2.30 2.18 2.06
[15:02:56.194] <TB2> INFO: ----------------------------------------------------------------------
[15:02:56.194] <TB2> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[15:02:56.194] <TB2> INFO: ----------------------------------------------------------------------
[15:02:56.197] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[15:02:56.206] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:02:56.206] <TB2> INFO: run 1 of 1
[15:02:56.440] <TB2> INFO: Expecting 4160000 events.
[15:03:29.421] <TB2> INFO: 754190 events read in total (32390ms).
[15:04:01.490] <TB2> INFO: 1502670 events read in total (64459ms).
[15:04:33.800] <TB2> INFO: 2247835 events read in total (96770ms).
[15:05:05.804] <TB2> INFO: 2988720 events read in total (128773ms).
[15:05:37.461] <TB2> INFO: 3727725 events read in total (160430ms).
[15:05:55.939] <TB2> INFO: 4160000 events read in total (178908ms).
[15:05:55.986] <TB2> INFO: Test took 179780ms.
[15:06:18.774] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[15:06:18.788] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:06:18.788] <TB2> INFO: run 1 of 1
[15:06:19.078] <TB2> INFO: Expecting 4430400 events.
[15:06:51.446] <TB2> INFO: 715830 events read in total (31776ms).
[15:07:22.376] <TB2> INFO: 1426745 events read in total (62706ms).
[15:07:53.785] <TB2> INFO: 2135260 events read in total (94115ms).
[15:08:24.473] <TB2> INFO: 2840555 events read in total (124803ms).
[15:08:55.452] <TB2> INFO: 3544095 events read in total (155782ms).
[15:09:26.836] <TB2> INFO: 4248475 events read in total (187166ms).
[15:09:35.341] <TB2> INFO: 4430400 events read in total (195671ms).
[15:09:35.418] <TB2> INFO: Test took 196629ms.
[15:09:59.440] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[15:09:59.450] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:09:59.450] <TB2> INFO: run 1 of 1
[15:09:59.682] <TB2> INFO: Expecting 4472000 events.
[15:10:31.428] <TB2> INFO: 714020 events read in total (31154ms).
[15:11:02.828] <TB2> INFO: 1423135 events read in total (62554ms).
[15:11:34.362] <TB2> INFO: 2129965 events read in total (94088ms).
[15:12:05.622] <TB2> INFO: 2833735 events read in total (125348ms).
[15:12:36.459] <TB2> INFO: 3535675 events read in total (156185ms).
[15:13:07.883] <TB2> INFO: 4237985 events read in total (187609ms).
[15:13:17.962] <TB2> INFO: 4472000 events read in total (197688ms).
[15:13:18.020] <TB2> INFO: Test took 198569ms.
[15:13:46.906] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[15:13:46.916] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:13:46.916] <TB2> INFO: run 1 of 1
[15:13:47.148] <TB2> INFO: Expecting 4472000 events.
[15:14:19.056] <TB2> INFO: 714155 events read in total (31316ms).
[15:14:50.270] <TB2> INFO: 1423305 events read in total (62530ms).
[15:15:21.247] <TB2> INFO: 2130235 events read in total (93507ms).
[15:15:52.193] <TB2> INFO: 2834205 events read in total (124453ms).
[15:16:23.273] <TB2> INFO: 3536270 events read in total (155533ms).
[15:16:54.089] <TB2> INFO: 4238545 events read in total (186349ms).
[15:17:04.582] <TB2> INFO: 4472000 events read in total (196842ms).
[15:17:04.636] <TB2> INFO: Test took 197720ms.
[15:17:31.221] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[15:17:31.231] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:17:31.231] <TB2> INFO: run 1 of 1
[15:17:31.463] <TB2> INFO: Expecting 4472000 events.
[15:18:02.994] <TB2> INFO: 714360 events read in total (30939ms).
[15:18:33.935] <TB2> INFO: 1423740 events read in total (61880ms).
[15:19:05.135] <TB2> INFO: 2130700 events read in total (93080ms).
[15:19:36.013] <TB2> INFO: 2834995 events read in total (123958ms).
[15:20:07.037] <TB2> INFO: 3537385 events read in total (154982ms).
[15:20:36.301] <TB2> INFO: 4239875 events read in total (184246ms).
[15:20:46.150] <TB2> INFO: 4472000 events read in total (194095ms).
[15:20:46.205] <TB2> INFO: Test took 194974ms.
[15:21:10.510] <TB2> INFO: PixTestTrim80::trimBitTest() done
[15:21:10.511] <TB2> INFO: PixTestTrim80::doTest() done, duration: 2426 seconds
[15:21:11.147] <TB2> INFO: enter test to run
[15:21:11.147] <TB2> INFO: test: exit no parameter change
[15:21:11.246] <TB2> QUIET: Connection to board 156 closed.
[15:21:11.247] <TB2> INFO: pXar: this is the end, my friend