[13:15:48.139] <TB1> INFO: *** Welcome to pxar ***
[13:15:48.139] <TB1> INFO: *** Today: 2016/10/31
[13:15:48.146] <TB1> INFO: *** Version: c8ba-dirty
[13:15:48.146] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C15.dat
[13:15:48.146] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[13:15:48.146] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//defaultMaskFile.dat
[13:15:48.146] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters_C15.dat
[13:15:48.200] <TB1> INFO: clk: 4
[13:15:48.200] <TB1> INFO: ctr: 4
[13:15:48.200] <TB1> INFO: sda: 19
[13:15:48.200] <TB1> INFO: tin: 9
[13:15:48.200] <TB1> INFO: level: 15
[13:15:48.200] <TB1> INFO: triggerdelay: 0
[13:15:48.200] <TB1> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[13:15:48.200] <TB1> INFO: Log level: INFO
[13:15:48.208] <TB1> INFO: Found DTB DTB_WXBYFL
[13:15:48.218] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[13:15:48.220] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
------------------------------------------------------
[13:15:48.222] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[13:15:49.708] <TB1> INFO: DUT info:
[13:15:49.708] <TB1> INFO: The DUT currently contains the following objects:
[13:15:49.708] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[13:15:49.708] <TB1> INFO: TBM Core alpha (0): 7 registers set
[13:15:49.708] <TB1> INFO: TBM Core beta (1): 7 registers set
[13:15:49.708] <TB1> INFO: TBM Core alpha (2): 7 registers set
[13:15:49.708] <TB1> INFO: TBM Core beta (3): 7 registers set
[13:15:49.708] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[13:15:49.708] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:49.708] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:15:50.109] <TB1> INFO: enter 'restricted' command line mode
[13:15:50.109] <TB1> INFO: enter test to run
[13:15:50.109] <TB1> INFO: test: pretest no parameter change
[13:15:50.109] <TB1> INFO: running: pretest
[13:15:50.650] <TB1> INFO: ######################################################################
[13:15:50.650] <TB1> INFO: PixTestPretest::doTest()
[13:15:50.650] <TB1> INFO: ######################################################################
[13:15:50.651] <TB1> INFO: ----------------------------------------------------------------------
[13:15:50.651] <TB1> INFO: PixTestPretest::programROC()
[13:15:50.651] <TB1> INFO: ----------------------------------------------------------------------
[13:16:08.664] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:16:08.664] <TB1> INFO: IA differences per ROC: 18.5 19.3 20.1 17.7 20.9 17.7 18.5 19.3 20.1 20.1 19.3 18.5 20.1 19.3 19.3 19.3
[13:16:08.699] <TB1> INFO: ----------------------------------------------------------------------
[13:16:08.699] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:16:08.699] <TB1> INFO: ----------------------------------------------------------------------
[13:16:17.485] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 387.5 mA = 24.2188 mA/ROC
[13:16:17.485] <TB1> INFO: i(loss) [mA/ROC]: 18.5 18.5 19.3 19.3 19.3 19.3 18.5 19.3 18.5 18.5 19.3 20.1 19.3 19.3 19.3 19.3
[13:16:17.513] <TB1> INFO: ----------------------------------------------------------------------
[13:16:17.513] <TB1> INFO: PixTestPretest::findTiming()
[13:16:17.513] <TB1> INFO: ----------------------------------------------------------------------
[13:16:17.513] <TB1> INFO: PixTestCmd::init()

[13:16:48.968] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[13:16:48.968] <TB1> INFO: (success/tries = 100/100), width = 4
[13:16:50.472] <TB1> INFO: ----------------------------------------------------------------------
[13:16:50.472] <TB1> INFO: PixTestPretest::findWorkingPixel()
[13:16:50.472] <TB1> INFO: ----------------------------------------------------------------------
[13:16:50.563] <TB1> INFO: Expecting 231680 events.
[13:17:00.229] <TB1> INFO: 231680 events read in total (9074ms).
[13:17:00.236] <TB1> INFO: Test took 9762ms.
[13:17:00.482] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[13:17:00.511] <TB1> INFO: ----------------------------------------------------------------------
[13:17:00.511] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[13:17:00.511] <TB1> INFO: ----------------------------------------------------------------------
[13:17:00.603] <TB1> INFO: Expecting 231680 events.
[13:17:10.299] <TB1> INFO: 231680 events read in total (9105ms).
[13:17:10.307] <TB1> INFO: Test took 9793ms.
[13:17:10.564] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[13:17:10.564] <TB1> INFO: CalDel: 102 83 89 97 93 80 87 82 97 105 81 82 78 93 100 92
[13:17:10.564] <TB1> INFO: VthrComp: 51 53 52 51 51 51 51 54 51 51 53 51 55 55 58 53
[13:17:10.567] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C0.dat
[13:17:10.567] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C1.dat
[13:17:10.567] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C2.dat
[13:17:10.567] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C3.dat
[13:17:10.567] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C4.dat
[13:17:10.567] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C5.dat
[13:17:10.567] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C6.dat
[13:17:10.567] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C7.dat
[13:17:10.568] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C8.dat
[13:17:10.568] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C9.dat
[13:17:10.568] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C10.dat
[13:17:10.568] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C11.dat
[13:17:10.568] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C12.dat
[13:17:10.568] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C13.dat
[13:17:10.568] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C14.dat
[13:17:10.568] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters_C15.dat
[13:17:10.568] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[13:17:10.568] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[13:17:10.568] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[13:17:10.569] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[13:17:10.569] <TB1> INFO: PixTestPretest::doTest() done, duration: 80 seconds
[13:17:10.664] <TB1> INFO: enter test to run
[13:17:10.664] <TB1> INFO: test: fulltest no parameter change
[13:17:10.664] <TB1> INFO: running: fulltest
[13:17:10.664] <TB1> INFO: ######################################################################
[13:17:10.664] <TB1> INFO: PixTestFullTest::doTest()
[13:17:10.664] <TB1> INFO: ######################################################################
[13:17:10.665] <TB1> INFO: ######################################################################
[13:17:10.665] <TB1> INFO: PixTestAlive::doTest()
[13:17:10.665] <TB1> INFO: ######################################################################
[13:17:10.666] <TB1> INFO: ----------------------------------------------------------------------
[13:17:10.666] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:17:10.666] <TB1> INFO: ----------------------------------------------------------------------
[13:17:10.902] <TB1> INFO: Expecting 41600 events.
[13:17:14.430] <TB1> INFO: 41600 events read in total (2936ms).
[13:17:14.431] <TB1> INFO: Test took 3763ms.
[13:17:14.659] <TB1> INFO: PixTestAlive::aliveTest() done
[13:17:14.659] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:17:14.660] <TB1> INFO: ----------------------------------------------------------------------
[13:17:14.660] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:17:14.660] <TB1> INFO: ----------------------------------------------------------------------
[13:17:14.937] <TB1> INFO: Expecting 41600 events.
[13:17:17.881] <TB1> INFO: 41600 events read in total (2353ms).
[13:17:17.881] <TB1> INFO: Test took 3220ms.
[13:17:17.881] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[13:17:18.119] <TB1> INFO: PixTestAlive::maskTest() done
[13:17:18.119] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:17:18.120] <TB1> INFO: ----------------------------------------------------------------------
[13:17:18.120] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:17:18.120] <TB1> INFO: ----------------------------------------------------------------------
[13:17:18.355] <TB1> INFO: Expecting 41600 events.
[13:17:21.779] <TB1> INFO: 41600 events read in total (2832ms).
[13:17:21.780] <TB1> INFO: Test took 3658ms.
[13:17:22.006] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[13:17:22.006] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:17:22.007] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[13:17:22.007] <TB1> INFO: Decoding statistics:
[13:17:22.007] <TB1> INFO: General information:
[13:17:22.007] <TB1> INFO: 16bit words read: 0
[13:17:22.007] <TB1> INFO: valid events total: 0
[13:17:22.007] <TB1> INFO: empty events: 0
[13:17:22.007] <TB1> INFO: valid events with pixels: 0
[13:17:22.007] <TB1> INFO: valid pixel hits: 0
[13:17:22.007] <TB1> INFO: Event errors: 0
[13:17:22.007] <TB1> INFO: start marker: 0
[13:17:22.007] <TB1> INFO: stop marker: 0
[13:17:22.007] <TB1> INFO: overflow: 0
[13:17:22.007] <TB1> INFO: invalid 5bit words: 0
[13:17:22.007] <TB1> INFO: invalid XOR eye diagram: 0
[13:17:22.007] <TB1> INFO: frame (failed synchr.): 0
[13:17:22.007] <TB1> INFO: idle data (no TBM trl): 0
[13:17:22.007] <TB1> INFO: no data (only TBM hdr): 0
[13:17:22.007] <TB1> INFO: TBM errors: 0
[13:17:22.007] <TB1> INFO: flawed TBM headers: 0
[13:17:22.007] <TB1> INFO: flawed TBM trailers: 0
[13:17:22.007] <TB1> INFO: event ID mismatches: 0
[13:17:22.007] <TB1> INFO: ROC errors: 0
[13:17:22.007] <TB1> INFO: missing ROC header(s): 0
[13:17:22.007] <TB1> INFO: misplaced readback start: 0
[13:17:22.007] <TB1> INFO: Pixel decoding errors: 0
[13:17:22.007] <TB1> INFO: pixel data incomplete: 0
[13:17:22.007] <TB1> INFO: pixel address: 0
[13:17:22.007] <TB1> INFO: pulse height fill bit: 0
[13:17:22.007] <TB1> INFO: buffer corruption: 0
[13:17:22.014] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:17:22.015] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[13:17:22.015] <TB1> INFO: ######################################################################
[13:17:22.015] <TB1> INFO: PixTestReadback::doTest()
[13:17:22.015] <TB1> INFO: ######################################################################
[13:17:22.015] <TB1> INFO: ----------------------------------------------------------------------
[13:17:22.015] <TB1> INFO: PixTestReadback::CalibrateVd()
[13:17:22.015] <TB1> INFO: ----------------------------------------------------------------------
[13:17:31.971] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:17:31.971] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:17:31.972] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:17:31.972] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:17:31.972] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:17:31.972] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:17:31.972] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:17:31.972] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:17:31.972] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:17:31.972] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:17:31.972] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:17:31.972] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:17:31.972] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:17:31.972] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:17:31.972] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:17:31.972] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:17:31.999] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:17:31.999] <TB1> INFO: ----------------------------------------------------------------------
[13:17:31.999] <TB1> INFO: PixTestReadback::CalibrateVa()
[13:17:31.999] <TB1> INFO: ----------------------------------------------------------------------
[13:17:41.892] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:17:41.892] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:17:41.892] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:17:41.892] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:17:41.892] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:17:41.892] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:17:41.892] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:17:41.892] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:17:41.893] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:17:41.893] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:17:41.893] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:17:41.893] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:17:41.893] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:17:41.893] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:17:41.893] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:17:41.893] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:17:41.920] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:17:41.920] <TB1> INFO: ----------------------------------------------------------------------
[13:17:41.920] <TB1> INFO: PixTestReadback::readbackVbg()
[13:17:41.920] <TB1> INFO: ----------------------------------------------------------------------
[13:17:49.561] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:17:49.561] <TB1> INFO: ----------------------------------------------------------------------
[13:17:49.561] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[13:17:49.561] <TB1> INFO: ----------------------------------------------------------------------
[13:17:49.561] <TB1> INFO: Vbg will be calibrated using Vd calibration
[13:17:49.561] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 159.6calibrated Vbg = 1.16126 :::*/*/*/*/
[13:17:49.561] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 157.2calibrated Vbg = 1.16255 :::*/*/*/*/
[13:17:49.562] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 154.1calibrated Vbg = 1.15456 :::*/*/*/*/
[13:17:49.562] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 160calibrated Vbg = 1.15281 :::*/*/*/*/
[13:17:49.562] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 156.5calibrated Vbg = 1.1635 :::*/*/*/*/
[13:17:49.562] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 158.8calibrated Vbg = 1.16829 :::*/*/*/*/
[13:17:49.562] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 153calibrated Vbg = 1.16019 :::*/*/*/*/
[13:17:49.562] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 148.1calibrated Vbg = 1.1596 :::*/*/*/*/
[13:17:49.562] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 156.2calibrated Vbg = 1.16163 :::*/*/*/*/
[13:17:49.562] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 150calibrated Vbg = 1.15624 :::*/*/*/*/
[13:17:49.562] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 155.1calibrated Vbg = 1.15741 :::*/*/*/*/
[13:17:49.562] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 156.5calibrated Vbg = 1.14602 :::*/*/*/*/
[13:17:49.562] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 165.9calibrated Vbg = 1.15193 :::*/*/*/*/
[13:17:49.562] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152calibrated Vbg = 1.15136 :::*/*/*/*/
[13:17:49.562] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 161.2calibrated Vbg = 1.15973 :::*/*/*/*/
[13:17:49.562] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 153.8calibrated Vbg = 1.16229 :::*/*/*/*/
[13:17:49.564] <TB1> INFO: ----------------------------------------------------------------------
[13:17:49.564] <TB1> INFO: PixTestReadback::CalibrateIa()
[13:17:49.564] <TB1> INFO: ----------------------------------------------------------------------
[13:20:29.882] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:20:29.882] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:20:29.882] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:20:29.882] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:20:29.883] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:20:29.883] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:20:29.883] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:20:29.883] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:20:29.883] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:20:29.883] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:20:29.883] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:20:29.883] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:20:29.883] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:20:29.883] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:20:29.883] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:20:29.883] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:20:29.910] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:20:29.912] <TB1> INFO: PixTestReadback::doTest() done
[13:20:29.912] <TB1> INFO: Decoding statistics:
[13:20:29.912] <TB1> INFO: General information:
[13:20:29.912] <TB1> INFO: 16bit words read: 1536
[13:20:29.912] <TB1> INFO: valid events total: 256
[13:20:29.912] <TB1> INFO: empty events: 256
[13:20:29.912] <TB1> INFO: valid events with pixels: 0
[13:20:29.912] <TB1> INFO: valid pixel hits: 0
[13:20:29.912] <TB1> INFO: Event errors: 0
[13:20:29.912] <TB1> INFO: start marker: 0
[13:20:29.912] <TB1> INFO: stop marker: 0
[13:20:29.912] <TB1> INFO: overflow: 0
[13:20:29.912] <TB1> INFO: invalid 5bit words: 0
[13:20:29.912] <TB1> INFO: invalid XOR eye diagram: 0
[13:20:29.912] <TB1> INFO: frame (failed synchr.): 0
[13:20:29.912] <TB1> INFO: idle data (no TBM trl): 0
[13:20:29.912] <TB1> INFO: no data (only TBM hdr): 0
[13:20:29.912] <TB1> INFO: TBM errors: 0
[13:20:29.912] <TB1> INFO: flawed TBM headers: 0
[13:20:29.912] <TB1> INFO: flawed TBM trailers: 0
[13:20:29.912] <TB1> INFO: event ID mismatches: 0
[13:20:29.912] <TB1> INFO: ROC errors: 0
[13:20:29.912] <TB1> INFO: missing ROC header(s): 0
[13:20:29.912] <TB1> INFO: misplaced readback start: 0
[13:20:29.912] <TB1> INFO: Pixel decoding errors: 0
[13:20:29.912] <TB1> INFO: pixel data incomplete: 0
[13:20:29.912] <TB1> INFO: pixel address: 0
[13:20:29.912] <TB1> INFO: pulse height fill bit: 0
[13:20:29.912] <TB1> INFO: buffer corruption: 0
[13:20:29.945] <TB1> INFO: ######################################################################
[13:20:29.945] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[13:20:29.945] <TB1> INFO: ######################################################################
[13:20:29.948] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[13:20:29.958] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:20:29.958] <TB1> INFO: run 1 of 1
[13:20:30.189] <TB1> INFO: Expecting 3120000 events.
[13:21:00.723] <TB1> INFO: 674450 events read in total (29942ms).











[13:21:30.493] <TB1> INFO: 1343665 events read in total (59713ms).











[13:22:00.582] <TB1> INFO: 2010930 events read in total (89802ms).











[13:22:30.907] <TB1> INFO: 2680155 events read in total (120126ms).











[13:22:51.162] <TB1> INFO: 3120000 events read in total (140381ms).
[13:22:51.239] <TB1> INFO: Test took 141281ms.
[13:23:14.386] <TB1> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 164 seconds
[13:23:14.386] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0
[13:23:14.386] <TB1> INFO: separation cut (per ROC): 103 107 107 104 105 106 105 117 105 110 108 112 110 119 108 107
[13:23:14.386] <TB1> INFO: Decoding statistics:
[13:23:14.386] <TB1> INFO: General information:
[13:23:14.386] <TB1> INFO: 16bit words read: 0
[13:23:14.386] <TB1> INFO: valid events total: 0
[13:23:14.386] <TB1> INFO: empty events: 0
[13:23:14.386] <TB1> INFO: valid events with pixels: 0
[13:23:14.386] <TB1> INFO: valid pixel hits: 0
[13:23:14.386] <TB1> INFO: Event errors: 0
[13:23:14.386] <TB1> INFO: start marker: 0
[13:23:14.386] <TB1> INFO: stop marker: 0
[13:23:14.386] <TB1> INFO: overflow: 0
[13:23:14.386] <TB1> INFO: invalid 5bit words: 0
[13:23:14.386] <TB1> INFO: invalid XOR eye diagram: 0
[13:23:14.386] <TB1> INFO: frame (failed synchr.): 0
[13:23:14.386] <TB1> INFO: idle data (no TBM trl): 0
[13:23:14.386] <TB1> INFO: no data (only TBM hdr): 0
[13:23:14.386] <TB1> INFO: TBM errors: 0
[13:23:14.386] <TB1> INFO: flawed TBM headers: 0
[13:23:14.386] <TB1> INFO: flawed TBM trailers: 0
[13:23:14.386] <TB1> INFO: event ID mismatches: 0
[13:23:14.386] <TB1> INFO: ROC errors: 0
[13:23:14.386] <TB1> INFO: missing ROC header(s): 0
[13:23:14.386] <TB1> INFO: misplaced readback start: 0
[13:23:14.386] <TB1> INFO: Pixel decoding errors: 0
[13:23:14.386] <TB1> INFO: pixel data incomplete: 0
[13:23:14.386] <TB1> INFO: pixel address: 0
[13:23:14.386] <TB1> INFO: pulse height fill bit: 0
[13:23:14.386] <TB1> INFO: buffer corruption: 0
[13:23:14.437] <TB1> INFO: ######################################################################
[13:23:14.437] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:23:14.437] <TB1> INFO: ######################################################################
[13:23:14.437] <TB1> INFO: ----------------------------------------------------------------------
[13:23:14.437] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:23:14.437] <TB1> INFO: ----------------------------------------------------------------------
[13:23:14.437] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[13:23:14.449] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[13:23:14.450] <TB1> INFO: run 1 of 1
[13:23:14.730] <TB1> INFO: Expecting 36608000 events.
[13:23:38.795] <TB1> INFO: 711200 events read in total (23473ms).
[13:24:02.024] <TB1> INFO: 1407750 events read in total (46702ms).
[13:24:25.404] <TB1> INFO: 2099500 events read in total (70082ms).
[13:24:48.751] <TB1> INFO: 2793150 events read in total (93429ms).
[13:25:11.967] <TB1> INFO: 3483450 events read in total (116645ms).
[13:25:35.175] <TB1> INFO: 4177000 events read in total (139853ms).
[13:25:58.348] <TB1> INFO: 4868000 events read in total (163026ms).
[13:26:21.029] <TB1> INFO: 5560900 events read in total (185707ms).
[13:26:44.303] <TB1> INFO: 6250300 events read in total (208981ms).
[13:27:07.613] <TB1> INFO: 6942050 events read in total (232291ms).
[13:27:30.962] <TB1> INFO: 7631000 events read in total (255641ms).
[13:27:54.329] <TB1> INFO: 8323000 events read in total (279007ms).
[13:28:17.799] <TB1> INFO: 9012000 events read in total (302477ms).
[13:28:41.417] <TB1> INFO: 9700900 events read in total (326095ms).
[13:29:04.814] <TB1> INFO: 10390950 events read in total (349492ms).
[13:29:28.045] <TB1> INFO: 11079450 events read in total (372723ms).
[13:29:51.177] <TB1> INFO: 11768200 events read in total (395855ms).
[13:30:14.677] <TB1> INFO: 12456150 events read in total (419355ms).
[13:30:37.790] <TB1> INFO: 13142850 events read in total (442468ms).
[13:31:00.786] <TB1> INFO: 13829800 events read in total (465464ms).
[13:31:24.006] <TB1> INFO: 14516100 events read in total (488684ms).
[13:31:47.173] <TB1> INFO: 15201600 events read in total (511851ms).
[13:32:10.528] <TB1> INFO: 15889100 events read in total (535206ms).
[13:32:33.976] <TB1> INFO: 16574050 events read in total (558654ms).
[13:32:57.624] <TB1> INFO: 17259100 events read in total (582302ms).
[13:33:20.912] <TB1> INFO: 17942950 events read in total (605590ms).
[13:33:44.508] <TB1> INFO: 18627950 events read in total (629186ms).
[13:34:08.268] <TB1> INFO: 19309900 events read in total (652946ms).
[13:34:31.196] <TB1> INFO: 19992350 events read in total (675874ms).
[13:34:54.834] <TB1> INFO: 20674850 events read in total (699512ms).
[13:35:17.841] <TB1> INFO: 21356150 events read in total (722519ms).
[13:35:41.516] <TB1> INFO: 22038050 events read in total (746194ms).
[13:36:05.111] <TB1> INFO: 22720100 events read in total (769789ms).
[13:36:28.984] <TB1> INFO: 23401250 events read in total (793662ms).
[13:36:52.151] <TB1> INFO: 24083550 events read in total (816829ms).
[13:37:15.685] <TB1> INFO: 24761900 events read in total (840363ms).
[13:37:39.612] <TB1> INFO: 25442850 events read in total (864290ms).
[13:38:03.218] <TB1> INFO: 26124850 events read in total (887896ms).
[13:38:26.463] <TB1> INFO: 26807100 events read in total (911141ms).
[13:38:49.823] <TB1> INFO: 27486950 events read in total (934501ms).
[13:39:12.930] <TB1> INFO: 28167400 events read in total (957608ms).
[13:39:35.965] <TB1> INFO: 28846200 events read in total (980643ms).
[13:39:59.600] <TB1> INFO: 29525250 events read in total (1004278ms).
[13:40:22.720] <TB1> INFO: 30203100 events read in total (1027398ms).
[13:40:45.975] <TB1> INFO: 30883250 events read in total (1050653ms).
[13:41:09.447] <TB1> INFO: 31561550 events read in total (1074125ms).
[13:41:32.851] <TB1> INFO: 32241400 events read in total (1097529ms).
[13:41:56.283] <TB1> INFO: 32920450 events read in total (1120961ms).
[13:42:19.997] <TB1> INFO: 33601150 events read in total (1144675ms).
[13:42:43.307] <TB1> INFO: 34281100 events read in total (1167985ms).
[13:43:07.183] <TB1> INFO: 34961950 events read in total (1191861ms).
[13:43:30.711] <TB1> INFO: 35643050 events read in total (1215389ms).
[13:43:54.646] <TB1> INFO: 36335350 events read in total (1239324ms).
[13:44:04.064] <TB1> INFO: 36608000 events read in total (1248742ms).
[13:44:04.112] <TB1> INFO: Test took 1249662ms.
[13:44:04.484] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:05.944] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:07.843] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:09.535] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:11.246] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:13.239] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:15.126] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:16.662] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:18.210] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:19.631] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:21.065] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:22.524] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:23.996] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:25.480] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:27.070] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:28.546] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:44:30.033] <TB1> INFO: PixTestScurves::scurves() done
[13:44:30.033] <TB1> INFO: Vcal mean: 124.59 122.91 125.56 124.34 122.44 124.89 119.64 127.78 122.29 127.67 128.09 129.90 124.72 132.28 129.90 125.50
[13:44:30.033] <TB1> INFO: Vcal RMS: 6.97 6.18 5.78 5.91 6.92 6.04 5.52 6.31 6.35 6.79 7.47 6.62 6.76 6.47 7.88 6.61
[13:44:30.033] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1275 seconds
[13:44:30.033] <TB1> INFO: Decoding statistics:
[13:44:30.033] <TB1> INFO: General information:
[13:44:30.033] <TB1> INFO: 16bit words read: 0
[13:44:30.033] <TB1> INFO: valid events total: 0
[13:44:30.033] <TB1> INFO: empty events: 0
[13:44:30.033] <TB1> INFO: valid events with pixels: 0
[13:44:30.033] <TB1> INFO: valid pixel hits: 0
[13:44:30.033] <TB1> INFO: Event errors: 0
[13:44:30.033] <TB1> INFO: start marker: 0
[13:44:30.033] <TB1> INFO: stop marker: 0
[13:44:30.033] <TB1> INFO: overflow: 0
[13:44:30.033] <TB1> INFO: invalid 5bit words: 0
[13:44:30.033] <TB1> INFO: invalid XOR eye diagram: 0
[13:44:30.033] <TB1> INFO: frame (failed synchr.): 0
[13:44:30.033] <TB1> INFO: idle data (no TBM trl): 0
[13:44:30.033] <TB1> INFO: no data (only TBM hdr): 0
[13:44:30.033] <TB1> INFO: TBM errors: 0
[13:44:30.033] <TB1> INFO: flawed TBM headers: 0
[13:44:30.033] <TB1> INFO: flawed TBM trailers: 0
[13:44:30.033] <TB1> INFO: event ID mismatches: 0
[13:44:30.033] <TB1> INFO: ROC errors: 0
[13:44:30.033] <TB1> INFO: missing ROC header(s): 0
[13:44:30.033] <TB1> INFO: misplaced readback start: 0
[13:44:30.033] <TB1> INFO: Pixel decoding errors: 0
[13:44:30.034] <TB1> INFO: pixel data incomplete: 0
[13:44:30.034] <TB1> INFO: pixel address: 0
[13:44:30.034] <TB1> INFO: pulse height fill bit: 0
[13:44:30.034] <TB1> INFO: buffer corruption: 0
[13:44:30.123] <TB1> INFO: ######################################################################
[13:44:30.123] <TB1> INFO: PixTestTrim::doTest()
[13:44:30.123] <TB1> INFO: ######################################################################
[13:44:30.124] <TB1> INFO: ----------------------------------------------------------------------
[13:44:30.124] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[13:44:30.124] <TB1> INFO: ----------------------------------------------------------------------
[13:44:30.166] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:44:30.166] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:44:30.177] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:44:30.177] <TB1> INFO: run 1 of 1
[13:44:30.408] <TB1> INFO: Expecting 5025280 events.
[13:45:01.250] <TB1> INFO: 837592 events read in total (30248ms).
[13:45:31.656] <TB1> INFO: 1672512 events read in total (60654ms).
[13:46:02.250] <TB1> INFO: 2504096 events read in total (91248ms).
[13:46:32.760] <TB1> INFO: 3332648 events read in total (121758ms).
[13:47:03.620] <TB1> INFO: 4158072 events read in total (152619ms).
[13:47:34.016] <TB1> INFO: 4982864 events read in total (183014ms).
[13:47:36.115] <TB1> INFO: 5025280 events read in total (185113ms).
[13:47:36.167] <TB1> INFO: Test took 185990ms.
[13:47:50.075] <TB1> INFO: ROC 0 VthrComp = 120
[13:47:50.075] <TB1> INFO: ROC 1 VthrComp = 123
[13:47:50.075] <TB1> INFO: ROC 2 VthrComp = 123
[13:47:50.075] <TB1> INFO: ROC 3 VthrComp = 118
[13:47:50.076] <TB1> INFO: ROC 4 VthrComp = 121
[13:47:50.076] <TB1> INFO: ROC 5 VthrComp = 123
[13:47:50.076] <TB1> INFO: ROC 6 VthrComp = 117
[13:47:50.076] <TB1> INFO: ROC 7 VthrComp = 132
[13:47:50.076] <TB1> INFO: ROC 8 VthrComp = 122
[13:47:50.076] <TB1> INFO: ROC 9 VthrComp = 126
[13:47:50.076] <TB1> INFO: ROC 10 VthrComp = 128
[13:47:50.076] <TB1> INFO: ROC 11 VthrComp = 130
[13:47:50.076] <TB1> INFO: ROC 12 VthrComp = 131
[13:47:50.077] <TB1> INFO: ROC 13 VthrComp = 134
[13:47:50.077] <TB1> INFO: ROC 14 VthrComp = 129
[13:47:50.077] <TB1> INFO: ROC 15 VthrComp = 125
[13:47:50.309] <TB1> INFO: Expecting 41600 events.
[13:47:53.869] <TB1> INFO: 41600 events read in total (2968ms).
[13:47:53.870] <TB1> INFO: Test took 3792ms.
[13:47:53.878] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:47:53.878] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:47:53.887] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:47:53.887] <TB1> INFO: run 1 of 1
[13:47:54.165] <TB1> INFO: Expecting 5025280 events.
[13:48:21.007] <TB1> INFO: 593008 events read in total (26251ms).
[13:48:47.415] <TB1> INFO: 1183904 events read in total (52659ms).
[13:49:13.591] <TB1> INFO: 1775024 events read in total (78835ms).
[13:49:40.082] <TB1> INFO: 2365192 events read in total (105326ms).
[13:50:06.796] <TB1> INFO: 2952744 events read in total (132040ms).
[13:50:32.518] <TB1> INFO: 3539496 events read in total (157762ms).
[13:50:58.245] <TB1> INFO: 4125800 events read in total (183489ms).
[13:51:23.692] <TB1> INFO: 4711560 events read in total (208936ms).
[13:51:37.371] <TB1> INFO: 5025280 events read in total (222615ms).
[13:51:37.426] <TB1> INFO: Test took 223539ms.
[13:51:59.597] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 61.7332 for pixel 1/19 mean/min/max = 47.3035/32.8607/61.7463
[13:51:59.597] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 61.3352 for pixel 25/6 mean/min/max = 46.5395/31.4425/61.6364
[13:51:59.598] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 61.3517 for pixel 12/74 mean/min/max = 47.386/33.3219/61.45
[13:51:59.598] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 63.1877 for pixel 15/0 mean/min/max = 47.7126/32.1286/63.2966
[13:51:59.598] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 60.764 for pixel 7/78 mean/min/max = 46.7237/32.484/60.9634
[13:51:59.599] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 60.8028 for pixel 0/20 mean/min/max = 46.457/32.071/60.8431
[13:51:59.599] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 60.7263 for pixel 7/7 mean/min/max = 46.3389/31.8873/60.7904
[13:51:59.600] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 60.8509 for pixel 1/0 mean/min/max = 46.5288/32.0898/60.9678
[13:51:59.600] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 59.7521 for pixel 3/37 mean/min/max = 46.0864/32.4047/59.7681
[13:51:59.600] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 61.5085 for pixel 19/9 mean/min/max = 46.6312/31.5877/61.6747
[13:51:59.601] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 61.8198 for pixel 14/70 mean/min/max = 46.9617/32.0895/61.8339
[13:51:59.601] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 61.5222 for pixel 2/17 mean/min/max = 46.583/31.6116/61.5544
[13:51:59.602] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 59.0593 for pixel 23/19 mean/min/max = 45.3655/31.525/59.206
[13:51:59.602] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 61.4583 for pixel 6/13 mean/min/max = 47.1228/32.7175/61.5281
[13:51:59.602] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 63.9606 for pixel 8/0 mean/min/max = 47.7415/31.3496/64.1335
[13:51:59.603] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 61.2746 for pixel 1/9 mean/min/max = 46.6809/32.0472/61.3146
[13:51:59.603] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:51:59.692] <TB1> INFO: Expecting 411648 events.
[13:52:09.120] <TB1> INFO: 411648 events read in total (8837ms).
[13:52:09.126] <TB1> INFO: Expecting 411648 events.
[13:52:18.540] <TB1> INFO: 411648 events read in total (9011ms).
[13:52:18.552] <TB1> INFO: Expecting 411648 events.
[13:52:27.964] <TB1> INFO: 411648 events read in total (9009ms).
[13:52:27.979] <TB1> INFO: Expecting 411648 events.
[13:52:37.388] <TB1> INFO: 411648 events read in total (9006ms).
[13:52:37.406] <TB1> INFO: Expecting 411648 events.
[13:52:46.783] <TB1> INFO: 411648 events read in total (8973ms).
[13:52:46.800] <TB1> INFO: Expecting 411648 events.
[13:52:56.028] <TB1> INFO: 411648 events read in total (8825ms).
[13:52:56.046] <TB1> INFO: Expecting 411648 events.
[13:53:05.417] <TB1> INFO: 411648 events read in total (8968ms).
[13:53:05.441] <TB1> INFO: Expecting 411648 events.
[13:53:14.733] <TB1> INFO: 411648 events read in total (8889ms).
[13:53:14.757] <TB1> INFO: Expecting 411648 events.
[13:53:23.905] <TB1> INFO: 411648 events read in total (8745ms).
[13:53:23.941] <TB1> INFO: Expecting 411648 events.
[13:53:33.122] <TB1> INFO: 411648 events read in total (8778ms).
[13:53:33.152] <TB1> INFO: Expecting 411648 events.
[13:53:42.448] <TB1> INFO: 411648 events read in total (8893ms).
[13:53:42.492] <TB1> INFO: Expecting 411648 events.
[13:53:51.741] <TB1> INFO: 411648 events read in total (8846ms).
[13:53:51.776] <TB1> INFO: Expecting 411648 events.
[13:54:01.093] <TB1> INFO: 411648 events read in total (8914ms).
[13:54:01.147] <TB1> INFO: Expecting 411648 events.
[13:54:10.351] <TB1> INFO: 411648 events read in total (8801ms).
[13:54:10.391] <TB1> INFO: Expecting 411648 events.
[13:54:19.602] <TB1> INFO: 411648 events read in total (8808ms).
[13:54:19.664] <TB1> INFO: Expecting 411648 events.
[13:54:28.920] <TB1> INFO: 411648 events read in total (8853ms).
[13:54:28.965] <TB1> INFO: Test took 149362ms.
[13:54:29.516] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:54:29.526] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:54:29.526] <TB1> INFO: run 1 of 1
[13:54:29.757] <TB1> INFO: Expecting 5025280 events.
[13:54:56.721] <TB1> INFO: 594120 events read in total (26372ms).
[13:55:22.942] <TB1> INFO: 1191192 events read in total (52593ms).
[13:55:49.254] <TB1> INFO: 1785688 events read in total (78905ms).
[13:56:15.832] <TB1> INFO: 2381200 events read in total (105483ms).
[13:56:42.334] <TB1> INFO: 2981328 events read in total (131985ms).
[13:57:08.710] <TB1> INFO: 3580016 events read in total (158361ms).
[13:57:34.988] <TB1> INFO: 4178424 events read in total (184639ms).
[13:58:01.590] <TB1> INFO: 4776904 events read in total (211241ms).
[13:58:12.798] <TB1> INFO: 5025280 events read in total (222449ms).
[13:58:12.895] <TB1> INFO: Test took 223369ms.
[13:58:31.930] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 2.375271 .. 147.429953
[13:58:32.162] <TB1> INFO: Expecting 208000 events.
[13:58:41.738] <TB1> INFO: 208000 events read in total (8984ms).
[13:58:41.739] <TB1> INFO: Test took 9808ms.
[13:58:41.785] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 157 (-1/-1) hits flags = 528 (plus default)
[13:58:41.793] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:58:41.793] <TB1> INFO: run 1 of 1
[13:58:42.071] <TB1> INFO: Expecting 5191680 events.
[13:59:09.012] <TB1> INFO: 584096 events read in total (26349ms).
[13:59:35.259] <TB1> INFO: 1167744 events read in total (52596ms).
[14:00:00.630] <TB1> INFO: 1751736 events read in total (77967ms).
[14:00:26.151] <TB1> INFO: 2334832 events read in total (103488ms).
[14:00:51.778] <TB1> INFO: 2918104 events read in total (129115ms).
[14:01:18.277] <TB1> INFO: 3500712 events read in total (155614ms).
[14:01:43.784] <TB1> INFO: 4082840 events read in total (181121ms).
[14:02:09.263] <TB1> INFO: 4664664 events read in total (206600ms).
[14:02:33.291] <TB1> INFO: 5191680 events read in total (230628ms).
[14:02:33.371] <TB1> INFO: Test took 231579ms.
[14:02:56.623] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.142859 .. 43.823592
[14:02:56.916] <TB1> INFO: Expecting 208000 events.
[14:03:06.559] <TB1> INFO: 208000 events read in total (9051ms).
[14:03:06.561] <TB1> INFO: Test took 9936ms.
[14:03:06.634] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 53 (-1/-1) hits flags = 528 (plus default)
[14:03:06.646] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:03:06.646] <TB1> INFO: run 1 of 1
[14:03:06.935] <TB1> INFO: Expecting 1231360 events.
[14:03:36.108] <TB1> INFO: 678000 events read in total (28582ms).
[14:03:59.415] <TB1> INFO: 1231360 events read in total (51890ms).
[14:03:59.457] <TB1> INFO: Test took 52812ms.
[14:04:10.009] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 30.015608 .. 48.259366
[14:04:10.242] <TB1> INFO: Expecting 208000 events.
[14:04:20.371] <TB1> INFO: 208000 events read in total (9538ms).
[14:04:20.372] <TB1> INFO: Test took 10362ms.
[14:04:20.444] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 20 .. 58 (-1/-1) hits flags = 528 (plus default)
[14:04:20.456] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:04:20.456] <TB1> INFO: run 1 of 1
[14:04:20.745] <TB1> INFO: Expecting 1297920 events.
[14:04:49.051] <TB1> INFO: 639864 events read in total (27714ms).
[14:05:16.973] <TB1> INFO: 1277688 events read in total (55636ms).
[14:05:18.260] <TB1> INFO: 1297920 events read in total (56923ms).
[14:05:18.295] <TB1> INFO: Test took 57839ms.
[14:05:29.308] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 26.783813 .. 50.658555
[14:05:29.540] <TB1> INFO: Expecting 208000 events.
[14:05:39.328] <TB1> INFO: 208000 events read in total (9196ms).
[14:05:39.329] <TB1> INFO: Test took 10019ms.
[14:05:39.374] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 60 (-1/-1) hits flags = 528 (plus default)
[14:05:39.384] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:05:39.384] <TB1> INFO: run 1 of 1
[14:05:39.662] <TB1> INFO: Expecting 1497600 events.
[14:06:08.006] <TB1> INFO: 646872 events read in total (27752ms).
[14:06:35.719] <TB1> INFO: 1292784 events read in total (55466ms).
[14:06:45.081] <TB1> INFO: 1497600 events read in total (64827ms).
[14:06:45.122] <TB1> INFO: Test took 65738ms.
[14:06:57.266] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:06:57.266] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:06:57.276] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:06:57.276] <TB1> INFO: run 1 of 1
[14:06:57.507] <TB1> INFO: Expecting 1364480 events.
[14:07:26.711] <TB1> INFO: 669448 events read in total (28612ms).
[14:07:54.466] <TB1> INFO: 1338016 events read in total (56367ms).
[14:07:55.961] <TB1> INFO: 1364480 events read in total (57862ms).
[14:07:55.991] <TB1> INFO: Test took 58716ms.
[14:08:08.199] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C0.dat
[14:08:08.199] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C1.dat
[14:08:08.199] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C2.dat
[14:08:08.199] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C3.dat
[14:08:08.199] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C4.dat
[14:08:08.199] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C5.dat
[14:08:08.199] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C6.dat
[14:08:08.199] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C7.dat
[14:08:08.199] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C8.dat
[14:08:08.199] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C9.dat
[14:08:08.199] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C10.dat
[14:08:08.200] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C11.dat
[14:08:08.200] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C12.dat
[14:08:08.200] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C13.dat
[14:08:08.200] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C14.dat
[14:08:08.200] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C15.dat
[14:08:08.200] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C0.dat
[14:08:08.205] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C1.dat
[14:08:08.211] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C2.dat
[14:08:08.216] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C3.dat
[14:08:08.222] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C4.dat
[14:08:08.227] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C5.dat
[14:08:08.233] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C6.dat
[14:08:08.238] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C7.dat
[14:08:08.244] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C8.dat
[14:08:08.249] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C9.dat
[14:08:08.254] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C10.dat
[14:08:08.260] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C11.dat
[14:08:08.265] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C12.dat
[14:08:08.271] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C13.dat
[14:08:08.276] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C14.dat
[14:08:08.282] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters35_C15.dat
[14:08:08.287] <TB1> INFO: PixTestTrim::trimTest() done
[14:08:08.287] <TB1> INFO: vtrim: 137 146 133 143 127 126 130 149 116 154 146 156 139 141 142 139
[14:08:08.287] <TB1> INFO: vthrcomp: 120 123 123 118 121 123 117 132 122 126 128 130 131 134 129 125
[14:08:08.287] <TB1> INFO: vcal mean: 35.06 35.18 35.12 35.71 35.07 35.26 35.11 35.09 35.11 35.39 35.29 35.25 34.95 35.27 35.95 35.09
[14:08:08.287] <TB1> INFO: vcal RMS: 1.18 1.42 1.23 2.01 1.10 1.41 1.25 1.19 1.18 1.68 1.46 1.45 1.17 1.38 2.24 1.18
[14:08:08.288] <TB1> INFO: bits mean: 9.77 10.15 9.53 10.22 9.46 9.89 9.91 9.76 9.93 10.40 10.12 10.26 10.27 9.73 10.29 9.80
[14:08:08.288] <TB1> INFO: bits RMS: 2.39 2.53 2.47 2.45 2.61 2.64 2.56 2.62 2.49 2.38 2.41 2.43 2.45 2.49 2.47 2.54
[14:08:08.294] <TB1> INFO: ----------------------------------------------------------------------
[14:08:08.294] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:08:08.294] <TB1> INFO: ----------------------------------------------------------------------
[14:08:08.296] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:08:08.307] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:08:08.307] <TB1> INFO: run 1 of 1
[14:08:08.573] <TB1> INFO: Expecting 4160000 events.
[14:08:42.674] <TB1> INFO: 786945 events read in total (33509ms).
[14:09:15.001] <TB1> INFO: 1565815 events read in total (66836ms).
[14:09:48.560] <TB1> INFO: 2337840 events read in total (99396ms).
[14:10:21.111] <TB1> INFO: 3104950 events read in total (131946ms).
[14:10:53.856] <TB1> INFO: 3870755 events read in total (164691ms).
[14:11:06.574] <TB1> INFO: 4160000 events read in total (177409ms).
[14:11:06.617] <TB1> INFO: Test took 178309ms.
[14:11:29.475] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 242 (-1/-1) hits flags = 528 (plus default)
[14:11:29.486] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:11:29.486] <TB1> INFO: run 1 of 1
[14:11:29.717] <TB1> INFO: Expecting 5054400 events.
[14:12:01.557] <TB1> INFO: 705655 events read in total (31248ms).
[14:12:32.962] <TB1> INFO: 1407635 events read in total (62653ms).
[14:13:04.180] <TB1> INFO: 2105640 events read in total (93871ms).
[14:13:35.247] <TB1> INFO: 2802055 events read in total (124938ms).
[14:14:06.356] <TB1> INFO: 3495775 events read in total (156047ms).
[14:14:37.072] <TB1> INFO: 4189085 events read in total (186763ms).
[14:15:08.369] <TB1> INFO: 4882660 events read in total (218060ms).
[14:15:16.195] <TB1> INFO: 5054400 events read in total (225886ms).
[14:15:16.260] <TB1> INFO: Test took 226774ms.
[14:15:44.698] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 215 (-1/-1) hits flags = 528 (plus default)
[14:15:44.711] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:15:44.711] <TB1> INFO: run 1 of 1
[14:15:44.971] <TB1> INFO: Expecting 4492800 events.
[14:16:17.635] <TB1> INFO: 735570 events read in total (32073ms).
[14:16:49.586] <TB1> INFO: 1466075 events read in total (64024ms).
[14:17:21.335] <TB1> INFO: 2191915 events read in total (95773ms).
[14:17:52.846] <TB1> INFO: 2914320 events read in total (127284ms).
[14:18:24.408] <TB1> INFO: 3635215 events read in total (158846ms).
[14:18:55.928] <TB1> INFO: 4356305 events read in total (190366ms).
[14:19:02.189] <TB1> INFO: 4492800 events read in total (196627ms).
[14:19:02.240] <TB1> INFO: Test took 197529ms.
[14:19:28.883] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 217 (-1/-1) hits flags = 528 (plus default)
[14:19:28.895] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:19:28.895] <TB1> INFO: run 1 of 1
[14:19:29.188] <TB1> INFO: Expecting 4534400 events.
[14:20:01.670] <TB1> INFO: 733135 events read in total (31890ms).
[14:20:33.583] <TB1> INFO: 1460850 events read in total (63803ms).
[14:21:05.679] <TB1> INFO: 2184705 events read in total (95899ms).
[14:21:37.243] <TB1> INFO: 2904820 events read in total (127463ms).
[14:22:08.881] <TB1> INFO: 3623675 events read in total (159101ms).
[14:22:40.681] <TB1> INFO: 4342415 events read in total (190901ms).
[14:22:49.451] <TB1> INFO: 4534400 events read in total (199671ms).
[14:22:49.503] <TB1> INFO: Test took 200608ms.
[14:23:15.747] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 216 (-1/-1) hits flags = 528 (plus default)
[14:23:15.757] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:23:15.757] <TB1> INFO: run 1 of 1
[14:23:15.988] <TB1> INFO: Expecting 4513600 events.
[14:23:48.553] <TB1> INFO: 734240 events read in total (31973ms).
[14:24:20.327] <TB1> INFO: 1463340 events read in total (63747ms).
[14:24:52.249] <TB1> INFO: 2188215 events read in total (95669ms).
[14:25:24.677] <TB1> INFO: 2909585 events read in total (128097ms).
[14:25:56.210] <TB1> INFO: 3629405 events read in total (159631ms).
[14:26:28.346] <TB1> INFO: 4349630 events read in total (191766ms).
[14:26:35.806] <TB1> INFO: 4513600 events read in total (199226ms).
[14:26:35.880] <TB1> INFO: Test took 200122ms.
[14:27:01.761] <TB1> INFO: PixTestTrim::trimBitTest() done
[14:27:01.762] <TB1> INFO: PixTestTrim::doTest() done, duration: 2551 seconds
[14:27:01.762] <TB1> INFO: Decoding statistics:
[14:27:01.762] <TB1> INFO: General information:
[14:27:01.762] <TB1> INFO: 16bit words read: 0
[14:27:01.762] <TB1> INFO: valid events total: 0
[14:27:01.762] <TB1> INFO: empty events: 0
[14:27:01.762] <TB1> INFO: valid events with pixels: 0
[14:27:01.762] <TB1> INFO: valid pixel hits: 0
[14:27:01.762] <TB1> INFO: Event errors: 0
[14:27:01.763] <TB1> INFO: start marker: 0
[14:27:01.763] <TB1> INFO: stop marker: 0
[14:27:01.763] <TB1> INFO: overflow: 0
[14:27:01.763] <TB1> INFO: invalid 5bit words: 0
[14:27:01.763] <TB1> INFO: invalid XOR eye diagram: 0
[14:27:01.763] <TB1> INFO: frame (failed synchr.): 0
[14:27:01.763] <TB1> INFO: idle data (no TBM trl): 0
[14:27:01.763] <TB1> INFO: no data (only TBM hdr): 0
[14:27:01.763] <TB1> INFO: TBM errors: 0
[14:27:01.763] <TB1> INFO: flawed TBM headers: 0
[14:27:01.763] <TB1> INFO: flawed TBM trailers: 0
[14:27:01.763] <TB1> INFO: event ID mismatches: 0
[14:27:01.763] <TB1> INFO: ROC errors: 0
[14:27:01.763] <TB1> INFO: missing ROC header(s): 0
[14:27:01.763] <TB1> INFO: misplaced readback start: 0
[14:27:01.763] <TB1> INFO: Pixel decoding errors: 0
[14:27:01.763] <TB1> INFO: pixel data incomplete: 0
[14:27:01.763] <TB1> INFO: pixel address: 0
[14:27:01.763] <TB1> INFO: pulse height fill bit: 0
[14:27:01.763] <TB1> INFO: buffer corruption: 0
[14:27:02.419] <TB1> INFO: ######################################################################
[14:27:02.419] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[14:27:02.419] <TB1> INFO: ######################################################################
[14:27:02.654] <TB1> INFO: Expecting 41600 events.
[14:27:06.095] <TB1> INFO: 41600 events read in total (2850ms).
[14:27:06.096] <TB1> INFO: Test took 3675ms.
[14:27:06.530] <TB1> INFO: Expecting 41600 events.
[14:27:10.092] <TB1> INFO: 41600 events read in total (2970ms).
[14:27:10.092] <TB1> INFO: Test took 3794ms.
[14:27:10.380] <TB1> INFO: Expecting 41600 events.
[14:27:14.089] <TB1> INFO: 41600 events read in total (3117ms).
[14:27:14.090] <TB1> INFO: Test took 3974ms.
[14:27:14.410] <TB1> INFO: Expecting 41600 events.
[14:27:18.111] <TB1> INFO: 41600 events read in total (3109ms).
[14:27:18.112] <TB1> INFO: Test took 3999ms.
[14:27:18.400] <TB1> INFO: Expecting 41600 events.
[14:27:21.910] <TB1> INFO: 41600 events read in total (2918ms).
[14:27:21.911] <TB1> INFO: Test took 3775ms.
[14:27:22.202] <TB1> INFO: Expecting 41600 events.
[14:27:25.960] <TB1> INFO: 41600 events read in total (3166ms).
[14:27:25.961] <TB1> INFO: Test took 4023ms.
[14:27:26.249] <TB1> INFO: Expecting 41600 events.
[14:27:29.697] <TB1> INFO: 41600 events read in total (2856ms).
[14:27:29.697] <TB1> INFO: Test took 3712ms.
[14:27:29.986] <TB1> INFO: Expecting 41600 events.
[14:27:33.477] <TB1> INFO: 41600 events read in total (2900ms).
[14:27:33.478] <TB1> INFO: Test took 3757ms.
[14:27:33.769] <TB1> INFO: Expecting 41600 events.
[14:27:37.414] <TB1> INFO: 41600 events read in total (3054ms).
[14:27:37.415] <TB1> INFO: Test took 3911ms.
[14:27:37.706] <TB1> INFO: Expecting 41600 events.
[14:27:41.275] <TB1> INFO: 41600 events read in total (2977ms).
[14:27:41.275] <TB1> INFO: Test took 3833ms.
[14:27:41.563] <TB1> INFO: Expecting 41600 events.
[14:27:44.996] <TB1> INFO: 41600 events read in total (2841ms).
[14:27:44.997] <TB1> INFO: Test took 3698ms.
[14:27:45.285] <TB1> INFO: Expecting 41600 events.
[14:27:48.777] <TB1> INFO: 41600 events read in total (2901ms).
[14:27:48.778] <TB1> INFO: Test took 3758ms.
[14:27:49.069] <TB1> INFO: Expecting 41600 events.
[14:27:52.643] <TB1> INFO: 41600 events read in total (2982ms).
[14:27:52.643] <TB1> INFO: Test took 3838ms.
[14:27:52.931] <TB1> INFO: Expecting 41600 events.
[14:27:56.514] <TB1> INFO: 41600 events read in total (2991ms).
[14:27:56.515] <TB1> INFO: Test took 3849ms.
[14:27:56.824] <TB1> INFO: Expecting 41600 events.
[14:28:00.442] <TB1> INFO: 41600 events read in total (3026ms).
[14:28:00.443] <TB1> INFO: Test took 3905ms.
[14:28:00.731] <TB1> INFO: Expecting 41600 events.
[14:28:04.181] <TB1> INFO: 41600 events read in total (2859ms).
[14:28:04.181] <TB1> INFO: Test took 3715ms.
[14:28:04.500] <TB1> INFO: Expecting 41600 events.
[14:28:07.999] <TB1> INFO: 41600 events read in total (2907ms).
[14:28:07.000] <TB1> INFO: Test took 3795ms.
[14:28:08.311] <TB1> INFO: Expecting 41600 events.
[14:28:11.813] <TB1> INFO: 41600 events read in total (2910ms).
[14:28:11.814] <TB1> INFO: Test took 3791ms.
[14:28:12.102] <TB1> INFO: Expecting 41600 events.
[14:28:15.694] <TB1> INFO: 41600 events read in total (3001ms).
[14:28:15.695] <TB1> INFO: Test took 3858ms.
[14:28:15.983] <TB1> INFO: Expecting 41600 events.
[14:28:19.628] <TB1> INFO: 41600 events read in total (3053ms).
[14:28:19.629] <TB1> INFO: Test took 3910ms.
[14:28:19.921] <TB1> INFO: Expecting 41600 events.
[14:28:23.547] <TB1> INFO: 41600 events read in total (3035ms).
[14:28:23.548] <TB1> INFO: Test took 3892ms.
[14:28:23.862] <TB1> INFO: Expecting 41600 events.
[14:28:27.579] <TB1> INFO: 41600 events read in total (3126ms).
[14:28:27.580] <TB1> INFO: Test took 4006ms.
[14:28:27.872] <TB1> INFO: Expecting 41600 events.
[14:28:31.569] <TB1> INFO: 41600 events read in total (3105ms).
[14:28:31.570] <TB1> INFO: Test took 3963ms.
[14:28:31.862] <TB1> INFO: Expecting 41600 events.
[14:28:35.319] <TB1> INFO: 41600 events read in total (2865ms).
[14:28:35.321] <TB1> INFO: Test took 3724ms.
[14:28:35.610] <TB1> INFO: Expecting 41600 events.
[14:28:39.232] <TB1> INFO: 41600 events read in total (3031ms).
[14:28:39.233] <TB1> INFO: Test took 3888ms.
[14:28:39.524] <TB1> INFO: Expecting 41600 events.
[14:28:42.003] <TB1> INFO: 41600 events read in total (2887ms).
[14:28:43.003] <TB1> INFO: Test took 3743ms.
[14:28:43.294] <TB1> INFO: Expecting 41600 events.
[14:28:46.805] <TB1> INFO: 41600 events read in total (2919ms).
[14:28:46.806] <TB1> INFO: Test took 3776ms.
[14:28:47.118] <TB1> INFO: Expecting 41600 events.
[14:28:50.590] <TB1> INFO: 41600 events read in total (2881ms).
[14:28:50.591] <TB1> INFO: Test took 3761ms.
[14:28:50.879] <TB1> INFO: Expecting 41600 events.
[14:28:54.494] <TB1> INFO: 41600 events read in total (3024ms).
[14:28:54.495] <TB1> INFO: Test took 3881ms.
[14:28:54.785] <TB1> INFO: Expecting 41600 events.
[14:28:58.423] <TB1> INFO: 41600 events read in total (3047ms).
[14:28:58.423] <TB1> INFO: Test took 3903ms.
[14:28:58.718] <TB1> INFO: Expecting 2560 events.
[14:28:59.606] <TB1> INFO: 2560 events read in total (296ms).
[14:28:59.606] <TB1> INFO: Test took 1165ms.
[14:28:59.914] <TB1> INFO: Expecting 2560 events.
[14:29:00.800] <TB1> INFO: 2560 events read in total (295ms).
[14:29:00.801] <TB1> INFO: Test took 1194ms.
[14:29:01.109] <TB1> INFO: Expecting 2560 events.
[14:29:01.994] <TB1> INFO: 2560 events read in total (294ms).
[14:29:01.995] <TB1> INFO: Test took 1194ms.
[14:29:02.302] <TB1> INFO: Expecting 2560 events.
[14:29:03.190] <TB1> INFO: 2560 events read in total (296ms).
[14:29:03.190] <TB1> INFO: Test took 1194ms.
[14:29:03.498] <TB1> INFO: Expecting 2560 events.
[14:29:04.377] <TB1> INFO: 2560 events read in total (288ms).
[14:29:04.377] <TB1> INFO: Test took 1187ms.
[14:29:04.685] <TB1> INFO: Expecting 2560 events.
[14:29:05.569] <TB1> INFO: 2560 events read in total (292ms).
[14:29:05.569] <TB1> INFO: Test took 1191ms.
[14:29:05.876] <TB1> INFO: Expecting 2560 events.
[14:29:06.760] <TB1> INFO: 2560 events read in total (292ms).
[14:29:06.760] <TB1> INFO: Test took 1191ms.
[14:29:07.068] <TB1> INFO: Expecting 2560 events.
[14:29:07.952] <TB1> INFO: 2560 events read in total (293ms).
[14:29:07.952] <TB1> INFO: Test took 1192ms.
[14:29:08.260] <TB1> INFO: Expecting 2560 events.
[14:29:09.143] <TB1> INFO: 2560 events read in total (291ms).
[14:29:09.143] <TB1> INFO: Test took 1190ms.
[14:29:09.452] <TB1> INFO: Expecting 2560 events.
[14:29:10.335] <TB1> INFO: 2560 events read in total (292ms).
[14:29:10.335] <TB1> INFO: Test took 1191ms.
[14:29:10.643] <TB1> INFO: Expecting 2560 events.
[14:29:11.524] <TB1> INFO: 2560 events read in total (289ms).
[14:29:11.524] <TB1> INFO: Test took 1189ms.
[14:29:11.832] <TB1> INFO: Expecting 2560 events.
[14:29:12.712] <TB1> INFO: 2560 events read in total (288ms).
[14:29:12.712] <TB1> INFO: Test took 1187ms.
[14:29:13.020] <TB1> INFO: Expecting 2560 events.
[14:29:13.907] <TB1> INFO: 2560 events read in total (296ms).
[14:29:13.907] <TB1> INFO: Test took 1195ms.
[14:29:14.215] <TB1> INFO: Expecting 2560 events.
[14:29:15.099] <TB1> INFO: 2560 events read in total (292ms).
[14:29:15.100] <TB1> INFO: Test took 1193ms.
[14:29:15.407] <TB1> INFO: Expecting 2560 events.
[14:29:16.296] <TB1> INFO: 2560 events read in total (297ms).
[14:29:16.296] <TB1> INFO: Test took 1196ms.
[14:29:16.603] <TB1> INFO: Expecting 2560 events.
[14:29:17.487] <TB1> INFO: 2560 events read in total (292ms).
[14:29:17.487] <TB1> INFO: Test took 1191ms.
[14:29:17.490] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:17.796] <TB1> INFO: Expecting 655360 events.
[14:29:32.645] <TB1> INFO: 655360 events read in total (14258ms).
[14:29:32.660] <TB1> INFO: Expecting 655360 events.
[14:29:47.205] <TB1> INFO: 655360 events read in total (14142ms).
[14:29:47.226] <TB1> INFO: Expecting 655360 events.
[14:30:01.787] <TB1> INFO: 655360 events read in total (14158ms).
[14:30:01.814] <TB1> INFO: Expecting 655360 events.
[14:30:16.302] <TB1> INFO: 655360 events read in total (14085ms).
[14:30:16.336] <TB1> INFO: Expecting 655360 events.
[14:30:30.898] <TB1> INFO: 655360 events read in total (14159ms).
[14:30:30.925] <TB1> INFO: Expecting 655360 events.
[14:30:45.419] <TB1> INFO: 655360 events read in total (14091ms).
[14:30:45.451] <TB1> INFO: Expecting 655360 events.
[14:31:00.132] <TB1> INFO: 655360 events read in total (14278ms).
[14:31:00.168] <TB1> INFO: Expecting 655360 events.
[14:31:14.676] <TB1> INFO: 655360 events read in total (14105ms).
[14:31:14.716] <TB1> INFO: Expecting 655360 events.
[14:31:29.325] <TB1> INFO: 655360 events read in total (14206ms).
[14:31:29.391] <TB1> INFO: Expecting 655360 events.
[14:31:43.971] <TB1> INFO: 655360 events read in total (14177ms).
[14:31:44.020] <TB1> INFO: Expecting 655360 events.
[14:31:58.410] <TB1> INFO: 655360 events read in total (13987ms).
[14:31:58.489] <TB1> INFO: Expecting 655360 events.
[14:32:12.902] <TB1> INFO: 655360 events read in total (14010ms).
[14:32:12.959] <TB1> INFO: Expecting 655360 events.
[14:32:27.458] <TB1> INFO: 655360 events read in total (14096ms).
[14:32:27.519] <TB1> INFO: Expecting 655360 events.
[14:32:42.153] <TB1> INFO: 655360 events read in total (14231ms).
[14:32:42.220] <TB1> INFO: Expecting 655360 events.
[14:32:56.738] <TB1> INFO: 655360 events read in total (14115ms).
[14:32:56.808] <TB1> INFO: Expecting 655360 events.
[14:33:11.424] <TB1> INFO: 655360 events read in total (14213ms).
[14:33:11.534] <TB1> INFO: Test took 234044ms.
[14:33:11.634] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:33:11.899] <TB1> INFO: Expecting 655360 events.
[14:33:26.454] <TB1> INFO: 655360 events read in total (13964ms).
[14:33:26.467] <TB1> INFO: Expecting 655360 events.
[14:33:40.774] <TB1> INFO: 655360 events read in total (13904ms).
[14:33:40.789] <TB1> INFO: Expecting 655360 events.
[14:33:55.139] <TB1> INFO: 655360 events read in total (13947ms).
[14:33:55.158] <TB1> INFO: Expecting 655360 events.
[14:34:09.377] <TB1> INFO: 655360 events read in total (13816ms).
[14:34:09.401] <TB1> INFO: Expecting 655360 events.
[14:34:23.578] <TB1> INFO: 655360 events read in total (13774ms).
[14:34:23.618] <TB1> INFO: Expecting 655360 events.
[14:34:38.124] <TB1> INFO: 655360 events read in total (14103ms).
[14:34:38.157] <TB1> INFO: Expecting 655360 events.
[14:34:52.371] <TB1> INFO: 655360 events read in total (13811ms).
[14:34:52.407] <TB1> INFO: Expecting 655360 events.
[14:35:06.912] <TB1> INFO: 655360 events read in total (14102ms).
[14:35:06.968] <TB1> INFO: Expecting 655360 events.
[14:35:21.337] <TB1> INFO: 655360 events read in total (13966ms).
[14:35:21.382] <TB1> INFO: Expecting 655360 events.
[14:35:35.741] <TB1> INFO: 655360 events read in total (13955ms).
[14:35:35.788] <TB1> INFO: Expecting 655360 events.
[14:35:50.189] <TB1> INFO: 655360 events read in total (13998ms).
[14:35:50.241] <TB1> INFO: Expecting 655360 events.
[14:36:04.724] <TB1> INFO: 655360 events read in total (14080ms).
[14:36:04.784] <TB1> INFO: Expecting 655360 events.
[14:36:19.281] <TB1> INFO: 655360 events read in total (14094ms).
[14:36:19.341] <TB1> INFO: Expecting 655360 events.
[14:36:33.544] <TB1> INFO: 655360 events read in total (13800ms).
[14:36:33.610] <TB1> INFO: Expecting 655360 events.
[14:36:47.943] <TB1> INFO: 655360 events read in total (13930ms).
[14:36:48.014] <TB1> INFO: Expecting 655360 events.
[14:37:02.467] <TB1> INFO: 655360 events read in total (14049ms).
[14:37:02.578] <TB1> INFO: Test took 230944ms.
[14:37:02.830] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.837] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[14:37:02.844] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[14:37:02.851] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[14:37:02.858] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[14:37:02.864] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.871] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[14:37:02.878] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[14:37:02.885] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.892] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[14:37:02.899] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[14:37:02.905] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[14:37:02.913] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[14:37:02.920] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.926] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.933] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.940] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.947] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.953] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.957] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[14:37:02.961] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.966] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.970] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.975] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.979] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.984] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:02.988] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[14:37:02.992] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[14:37:02.997] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[14:37:02.001] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[14:37:03.006] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:37:03.040] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C0.dat
[14:37:03.040] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C1.dat
[14:37:03.040] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C2.dat
[14:37:03.041] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C3.dat
[14:37:03.041] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C4.dat
[14:37:03.041] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C5.dat
[14:37:03.041] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C6.dat
[14:37:03.041] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C7.dat
[14:37:03.041] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C8.dat
[14:37:03.041] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C9.dat
[14:37:03.041] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C10.dat
[14:37:03.041] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C11.dat
[14:37:03.041] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C12.dat
[14:37:03.042] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C13.dat
[14:37:03.042] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C14.dat
[14:37:03.042] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters35_C15.dat
[14:37:03.337] <TB1> INFO: Expecting 41600 events.
[14:37:06.507] <TB1> INFO: 41600 events read in total (2578ms).
[14:37:06.508] <TB1> INFO: Test took 3463ms.
[14:37:06.951] <TB1> INFO: Expecting 41600 events.
[14:37:10.013] <TB1> INFO: 41600 events read in total (2470ms).
[14:37:10.014] <TB1> INFO: Test took 3294ms.
[14:37:10.460] <TB1> INFO: Expecting 41600 events.
[14:37:13.615] <TB1> INFO: 41600 events read in total (2564ms).
[14:37:13.616] <TB1> INFO: Test took 3388ms.
[14:37:13.830] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:13.919] <TB1> INFO: Expecting 2560 events.
[14:37:14.803] <TB1> INFO: 2560 events read in total (293ms).
[14:37:14.803] <TB1> INFO: Test took 973ms.
[14:37:14.805] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:15.111] <TB1> INFO: Expecting 2560 events.
[14:37:15.998] <TB1> INFO: 2560 events read in total (296ms).
[14:37:15.998] <TB1> INFO: Test took 1193ms.
[14:37:15.000] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:16.306] <TB1> INFO: Expecting 2560 events.
[14:37:17.190] <TB1> INFO: 2560 events read in total (292ms).
[14:37:17.191] <TB1> INFO: Test took 1191ms.
[14:37:17.192] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:17.499] <TB1> INFO: Expecting 2560 events.
[14:37:18.385] <TB1> INFO: 2560 events read in total (295ms).
[14:37:18.385] <TB1> INFO: Test took 1193ms.
[14:37:18.387] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:18.693] <TB1> INFO: Expecting 2560 events.
[14:37:19.576] <TB1> INFO: 2560 events read in total (291ms).
[14:37:19.576] <TB1> INFO: Test took 1189ms.
[14:37:19.578] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:19.884] <TB1> INFO: Expecting 2560 events.
[14:37:20.768] <TB1> INFO: 2560 events read in total (292ms).
[14:37:20.768] <TB1> INFO: Test took 1190ms.
[14:37:20.770] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:21.077] <TB1> INFO: Expecting 2560 events.
[14:37:21.960] <TB1> INFO: 2560 events read in total (292ms).
[14:37:21.960] <TB1> INFO: Test took 1190ms.
[14:37:21.962] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:22.269] <TB1> INFO: Expecting 2560 events.
[14:37:23.153] <TB1> INFO: 2560 events read in total (292ms).
[14:37:23.153] <TB1> INFO: Test took 1191ms.
[14:37:23.155] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:23.462] <TB1> INFO: Expecting 2560 events.
[14:37:24.342] <TB1> INFO: 2560 events read in total (289ms).
[14:37:24.342] <TB1> INFO: Test took 1187ms.
[14:37:24.344] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:24.650] <TB1> INFO: Expecting 2560 events.
[14:37:25.529] <TB1> INFO: 2560 events read in total (287ms).
[14:37:25.530] <TB1> INFO: Test took 1186ms.
[14:37:25.532] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:25.838] <TB1> INFO: Expecting 2560 events.
[14:37:26.719] <TB1> INFO: 2560 events read in total (289ms).
[14:37:26.719] <TB1> INFO: Test took 1187ms.
[14:37:26.722] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:27.027] <TB1> INFO: Expecting 2560 events.
[14:37:27.907] <TB1> INFO: 2560 events read in total (288ms).
[14:37:27.907] <TB1> INFO: Test took 1185ms.
[14:37:27.909] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:28.215] <TB1> INFO: Expecting 2560 events.
[14:37:29.100] <TB1> INFO: 2560 events read in total (293ms).
[14:37:29.100] <TB1> INFO: Test took 1191ms.
[14:37:29.102] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:29.408] <TB1> INFO: Expecting 2560 events.
[14:37:30.287] <TB1> INFO: 2560 events read in total (288ms).
[14:37:30.287] <TB1> INFO: Test took 1185ms.
[14:37:30.289] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:30.596] <TB1> INFO: Expecting 2560 events.
[14:37:31.479] <TB1> INFO: 2560 events read in total (292ms).
[14:37:31.480] <TB1> INFO: Test took 1191ms.
[14:37:31.481] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:31.788] <TB1> INFO: Expecting 2560 events.
[14:37:32.668] <TB1> INFO: 2560 events read in total (288ms).
[14:37:32.668] <TB1> INFO: Test took 1187ms.
[14:37:32.670] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:32.976] <TB1> INFO: Expecting 2560 events.
[14:37:33.856] <TB1> INFO: 2560 events read in total (288ms).
[14:37:33.856] <TB1> INFO: Test took 1186ms.
[14:37:33.858] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:34.165] <TB1> INFO: Expecting 2560 events.
[14:37:35.044] <TB1> INFO: 2560 events read in total (288ms).
[14:37:35.044] <TB1> INFO: Test took 1186ms.
[14:37:35.046] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:35.353] <TB1> INFO: Expecting 2560 events.
[14:37:36.233] <TB1> INFO: 2560 events read in total (288ms).
[14:37:36.233] <TB1> INFO: Test took 1187ms.
[14:37:36.235] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:36.541] <TB1> INFO: Expecting 2560 events.
[14:37:37.425] <TB1> INFO: 2560 events read in total (292ms).
[14:37:37.425] <TB1> INFO: Test took 1190ms.
[14:37:37.427] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:37.733] <TB1> INFO: Expecting 2560 events.
[14:37:38.613] <TB1> INFO: 2560 events read in total (288ms).
[14:37:38.613] <TB1> INFO: Test took 1186ms.
[14:37:38.615] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:38.921] <TB1> INFO: Expecting 2560 events.
[14:37:39.800] <TB1> INFO: 2560 events read in total (287ms).
[14:37:39.800] <TB1> INFO: Test took 1185ms.
[14:37:39.802] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:40.109] <TB1> INFO: Expecting 2560 events.
[14:37:40.988] <TB1> INFO: 2560 events read in total (288ms).
[14:37:40.988] <TB1> INFO: Test took 1186ms.
[14:37:40.990] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:41.297] <TB1> INFO: Expecting 2560 events.
[14:37:42.176] <TB1> INFO: 2560 events read in total (288ms).
[14:37:42.176] <TB1> INFO: Test took 1186ms.
[14:37:42.178] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:42.484] <TB1> INFO: Expecting 2560 events.
[14:37:43.368] <TB1> INFO: 2560 events read in total (292ms).
[14:37:43.368] <TB1> INFO: Test took 1190ms.
[14:37:43.370] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:43.676] <TB1> INFO: Expecting 2560 events.
[14:37:44.564] <TB1> INFO: 2560 events read in total (296ms).
[14:37:44.564] <TB1> INFO: Test took 1194ms.
[14:37:44.566] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:44.873] <TB1> INFO: Expecting 2560 events.
[14:37:45.756] <TB1> INFO: 2560 events read in total (292ms).
[14:37:45.757] <TB1> INFO: Test took 1191ms.
[14:37:45.759] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:46.065] <TB1> INFO: Expecting 2560 events.
[14:37:46.953] <TB1> INFO: 2560 events read in total (297ms).
[14:37:46.953] <TB1> INFO: Test took 1194ms.
[14:37:46.956] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:47.262] <TB1> INFO: Expecting 2560 events.
[14:37:48.150] <TB1> INFO: 2560 events read in total (297ms).
[14:37:48.150] <TB1> INFO: Test took 1194ms.
[14:37:48.152] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:48.459] <TB1> INFO: Expecting 2560 events.
[14:37:49.342] <TB1> INFO: 2560 events read in total (292ms).
[14:37:49.342] <TB1> INFO: Test took 1191ms.
[14:37:49.344] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:49.651] <TB1> INFO: Expecting 2560 events.
[14:37:50.539] <TB1> INFO: 2560 events read in total (296ms).
[14:37:50.540] <TB1> INFO: Test took 1196ms.
[14:37:50.541] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:37:50.848] <TB1> INFO: Expecting 2560 events.
[14:37:51.733] <TB1> INFO: 2560 events read in total (294ms).
[14:37:51.733] <TB1> INFO: Test took 1192ms.
[14:37:52.194] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 649 seconds
[14:37:52.194] <TB1> INFO: PH scale (per ROC): 31 34 48 37 31 35 48 46 48 31 35 39 47 49 31 33
[14:37:52.194] <TB1> INFO: PH offset (per ROC): 92 81 112 113 104 106 130 120 112 102 102 110 126 128 91 98
[14:37:52.199] <TB1> INFO: Decoding statistics:
[14:37:52.200] <TB1> INFO: General information:
[14:37:52.200] <TB1> INFO: 16bit words read: 127876
[14:37:52.200] <TB1> INFO: valid events total: 20480
[14:37:52.200] <TB1> INFO: empty events: 17982
[14:37:52.200] <TB1> INFO: valid events with pixels: 2498
[14:37:52.200] <TB1> INFO: valid pixel hits: 2498
[14:37:52.200] <TB1> INFO: Event errors: 0
[14:37:52.200] <TB1> INFO: start marker: 0
[14:37:52.200] <TB1> INFO: stop marker: 0
[14:37:52.200] <TB1> INFO: overflow: 0
[14:37:52.200] <TB1> INFO: invalid 5bit words: 0
[14:37:52.200] <TB1> INFO: invalid XOR eye diagram: 0
[14:37:52.200] <TB1> INFO: frame (failed synchr.): 0
[14:37:52.200] <TB1> INFO: idle data (no TBM trl): 0
[14:37:52.200] <TB1> INFO: no data (only TBM hdr): 0
[14:37:52.200] <TB1> INFO: TBM errors: 0
[14:37:52.200] <TB1> INFO: flawed TBM headers: 0
[14:37:52.200] <TB1> INFO: flawed TBM trailers: 0
[14:37:52.200] <TB1> INFO: event ID mismatches: 0
[14:37:52.200] <TB1> INFO: ROC errors: 0
[14:37:52.200] <TB1> INFO: missing ROC header(s): 0
[14:37:52.200] <TB1> INFO: misplaced readback start: 0
[14:37:52.200] <TB1> INFO: Pixel decoding errors: 0
[14:37:52.200] <TB1> INFO: pixel data incomplete: 0
[14:37:52.200] <TB1> INFO: pixel address: 0
[14:37:52.200] <TB1> INFO: pulse height fill bit: 0
[14:37:52.200] <TB1> INFO: buffer corruption: 0
[14:37:52.468] <TB1> INFO: ######################################################################
[14:37:52.468] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[14:37:52.468] <TB1> INFO: ######################################################################
[14:37:52.481] <TB1> INFO: scanning low vcal = 10
[14:37:52.774] <TB1> INFO: Expecting 41600 events.
[14:37:56.373] <TB1> INFO: 41600 events read in total (3008ms).
[14:37:56.373] <TB1> INFO: Test took 3892ms.
[14:37:56.375] <TB1> INFO: scanning low vcal = 20
[14:37:56.674] <TB1> INFO: Expecting 41600 events.
[14:38:00.303] <TB1> INFO: 41600 events read in total (3037ms).
[14:38:00.304] <TB1> INFO: Test took 3929ms.
[14:38:00.305] <TB1> INFO: scanning low vcal = 30
[14:38:00.603] <TB1> INFO: Expecting 41600 events.
[14:38:04.262] <TB1> INFO: 41600 events read in total (3067ms).
[14:38:04.263] <TB1> INFO: Test took 3958ms.
[14:38:04.265] <TB1> INFO: scanning low vcal = 40
[14:38:04.542] <TB1> INFO: Expecting 41600 events.
[14:38:08.462] <TB1> INFO: 41600 events read in total (3328ms).
[14:38:08.463] <TB1> INFO: Test took 4197ms.
[14:38:08.466] <TB1> INFO: scanning low vcal = 50
[14:38:08.742] <TB1> INFO: Expecting 41600 events.
[14:38:12.747] <TB1> INFO: 41600 events read in total (3413ms).
[14:38:12.748] <TB1> INFO: Test took 4282ms.
[14:38:12.751] <TB1> INFO: scanning low vcal = 60
[14:38:13.027] <TB1> INFO: Expecting 41600 events.
[14:38:17.010] <TB1> INFO: 41600 events read in total (3391ms).
[14:38:17.010] <TB1> INFO: Test took 4259ms.
[14:38:17.013] <TB1> INFO: scanning low vcal = 70
[14:38:17.290] <TB1> INFO: Expecting 41600 events.
[14:38:21.298] <TB1> INFO: 41600 events read in total (3417ms).
[14:38:21.299] <TB1> INFO: Test took 4286ms.
[14:38:21.302] <TB1> INFO: scanning low vcal = 80
[14:38:21.578] <TB1> INFO: Expecting 41600 events.
[14:38:25.536] <TB1> INFO: 41600 events read in total (3366ms).
[14:38:25.537] <TB1> INFO: Test took 4235ms.
[14:38:25.539] <TB1> INFO: scanning low vcal = 90
[14:38:25.816] <TB1> INFO: Expecting 41600 events.
[14:38:29.823] <TB1> INFO: 41600 events read in total (3416ms).
[14:38:29.823] <TB1> INFO: Test took 4284ms.
[14:38:29.826] <TB1> INFO: scanning low vcal = 100
[14:38:30.103] <TB1> INFO: Expecting 41600 events.
[14:38:34.107] <TB1> INFO: 41600 events read in total (3413ms).
[14:38:34.108] <TB1> INFO: Test took 4282ms.
[14:38:34.111] <TB1> INFO: scanning low vcal = 110
[14:38:34.404] <TB1> INFO: Expecting 41600 events.
[14:38:38.357] <TB1> INFO: 41600 events read in total (3362ms).
[14:38:38.358] <TB1> INFO: Test took 4247ms.
[14:38:38.360] <TB1> INFO: scanning low vcal = 120
[14:38:38.637] <TB1> INFO: Expecting 41600 events.
[14:38:42.612] <TB1> INFO: 41600 events read in total (3383ms).
[14:38:42.613] <TB1> INFO: Test took 4252ms.
[14:38:42.615] <TB1> INFO: scanning low vcal = 130
[14:38:42.904] <TB1> INFO: Expecting 41600 events.
[14:38:46.877] <TB1> INFO: 41600 events read in total (3381ms).
[14:38:46.878] <TB1> INFO: Test took 4263ms.
[14:38:46.881] <TB1> INFO: scanning low vcal = 140
[14:38:47.157] <TB1> INFO: Expecting 41600 events.
[14:38:51.152] <TB1> INFO: 41600 events read in total (3404ms).
[14:38:51.153] <TB1> INFO: Test took 4272ms.
[14:38:51.155] <TB1> INFO: scanning low vcal = 150
[14:38:51.432] <TB1> INFO: Expecting 41600 events.
[14:38:55.442] <TB1> INFO: 41600 events read in total (3418ms).
[14:38:55.443] <TB1> INFO: Test took 4287ms.
[14:38:55.446] <TB1> INFO: scanning low vcal = 160
[14:38:55.722] <TB1> INFO: Expecting 41600 events.
[14:38:59.717] <TB1> INFO: 41600 events read in total (3403ms).
[14:38:59.718] <TB1> INFO: Test took 4272ms.
[14:38:59.721] <TB1> INFO: scanning low vcal = 170
[14:38:59.997] <TB1> INFO: Expecting 41600 events.
[14:39:03.971] <TB1> INFO: 41600 events read in total (3382ms).
[14:39:03.972] <TB1> INFO: Test took 4251ms.
[14:39:03.975] <TB1> INFO: scanning low vcal = 180
[14:39:04.251] <TB1> INFO: Expecting 41600 events.
[14:39:08.262] <TB1> INFO: 41600 events read in total (3419ms).
[14:39:08.263] <TB1> INFO: Test took 4288ms.
[14:39:08.265] <TB1> INFO: scanning low vcal = 190
[14:39:08.560] <TB1> INFO: Expecting 41600 events.
[14:39:12.610] <TB1> INFO: 41600 events read in total (3458ms).
[14:39:12.611] <TB1> INFO: Test took 4345ms.
[14:39:12.613] <TB1> INFO: scanning low vcal = 200
[14:39:12.908] <TB1> INFO: Expecting 41600 events.
[14:39:16.864] <TB1> INFO: 41600 events read in total (3364ms).
[14:39:16.865] <TB1> INFO: Test took 4252ms.
[14:39:16.868] <TB1> INFO: scanning low vcal = 210
[14:39:17.144] <TB1> INFO: Expecting 41600 events.
[14:39:21.110] <TB1> INFO: 41600 events read in total (3374ms).
[14:39:21.111] <TB1> INFO: Test took 4243ms.
[14:39:21.114] <TB1> INFO: scanning low vcal = 220
[14:39:21.405] <TB1> INFO: Expecting 41600 events.
[14:39:25.352] <TB1> INFO: 41600 events read in total (3356ms).
[14:39:25.353] <TB1> INFO: Test took 4239ms.
[14:39:25.355] <TB1> INFO: scanning low vcal = 230
[14:39:25.632] <TB1> INFO: Expecting 41600 events.
[14:39:29.609] <TB1> INFO: 41600 events read in total (3386ms).
[14:39:29.609] <TB1> INFO: Test took 4254ms.
[14:39:29.612] <TB1> INFO: scanning low vcal = 240
[14:39:29.889] <TB1> INFO: Expecting 41600 events.
[14:39:33.905] <TB1> INFO: 41600 events read in total (3425ms).
[14:39:33.906] <TB1> INFO: Test took 4294ms.
[14:39:33.909] <TB1> INFO: scanning low vcal = 250
[14:39:34.185] <TB1> INFO: Expecting 41600 events.
[14:39:38.162] <TB1> INFO: 41600 events read in total (3385ms).
[14:39:38.162] <TB1> INFO: Test took 4253ms.
[14:39:38.166] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[14:39:38.442] <TB1> INFO: Expecting 41600 events.
[14:39:42.405] <TB1> INFO: 41600 events read in total (3372ms).
[14:39:42.405] <TB1> INFO: Test took 4239ms.
[14:39:42.408] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[14:39:42.701] <TB1> INFO: Expecting 41600 events.
[14:39:46.650] <TB1> INFO: 41600 events read in total (3357ms).
[14:39:46.651] <TB1> INFO: Test took 4243ms.
[14:39:46.653] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[14:39:46.930] <TB1> INFO: Expecting 41600 events.
[14:39:50.925] <TB1> INFO: 41600 events read in total (3404ms).
[14:39:50.926] <TB1> INFO: Test took 4273ms.
[14:39:50.928] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[14:39:51.206] <TB1> INFO: Expecting 41600 events.
[14:39:55.154] <TB1> INFO: 41600 events read in total (3357ms).
[14:39:55.154] <TB1> INFO: Test took 4225ms.
[14:39:55.157] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[14:39:55.433] <TB1> INFO: Expecting 41600 events.
[14:39:59.457] <TB1> INFO: 41600 events read in total (3432ms).
[14:39:59.458] <TB1> INFO: Test took 4301ms.
[14:39:59.976] <TB1> INFO: PixTestGainPedestal::measure() done
[14:40:35.073] <TB1> INFO: PixTestGainPedestal::fit() done
[14:40:35.073] <TB1> INFO: non-linearity mean: 1.050 1.005 0.960 0.956 1.032 0.945 0.981 0.975 0.987 0.930 0.946 0.943 0.979 0.982 0.930 0.941
[14:40:35.073] <TB1> INFO: non-linearity RMS: 0.157 0.202 0.035 0.086 0.153 0.124 0.004 0.005 0.002 0.106 0.174 0.075 0.005 0.004 0.144 0.159
[14:40:35.073] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[14:40:35.096] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[14:40:35.118] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[14:40:35.141] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[14:40:35.163] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[14:40:35.186] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[14:40:35.208] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[14:40:35.228] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[14:40:35.242] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[14:40:35.256] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[14:40:35.275] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[14:40:35.289] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[14:40:35.302] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[14:40:35.316] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[14:40:35.330] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[14:40:35.344] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[14:40:35.358] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 162 seconds
[14:40:35.358] <TB1> INFO: Decoding statistics:
[14:40:35.358] <TB1> INFO: General information:
[14:40:35.358] <TB1> INFO: 16bit words read: 3284170
[14:40:35.358] <TB1> INFO: valid events total: 332800
[14:40:35.358] <TB1> INFO: empty events: 2534
[14:40:35.358] <TB1> INFO: valid events with pixels: 330266
[14:40:35.358] <TB1> INFO: valid pixel hits: 643685
[14:40:35.358] <TB1> INFO: Event errors: 0
[14:40:35.358] <TB1> INFO: start marker: 0
[14:40:35.358] <TB1> INFO: stop marker: 0
[14:40:35.358] <TB1> INFO: overflow: 0
[14:40:35.358] <TB1> INFO: invalid 5bit words: 0
[14:40:35.358] <TB1> INFO: invalid XOR eye diagram: 0
[14:40:35.358] <TB1> INFO: frame (failed synchr.): 0
[14:40:35.358] <TB1> INFO: idle data (no TBM trl): 0
[14:40:35.358] <TB1> INFO: no data (only TBM hdr): 0
[14:40:35.358] <TB1> INFO: TBM errors: 0
[14:40:35.358] <TB1> INFO: flawed TBM headers: 0
[14:40:35.358] <TB1> INFO: flawed TBM trailers: 0
[14:40:35.358] <TB1> INFO: event ID mismatches: 0
[14:40:35.358] <TB1> INFO: ROC errors: 0
[14:40:35.358] <TB1> INFO: missing ROC header(s): 0
[14:40:35.358] <TB1> INFO: misplaced readback start: 0
[14:40:35.358] <TB1> INFO: Pixel decoding errors: 0
[14:40:35.358] <TB1> INFO: pixel data incomplete: 0
[14:40:35.358] <TB1> INFO: pixel address: 0
[14:40:35.358] <TB1> INFO: pulse height fill bit: 0
[14:40:35.358] <TB1> INFO: buffer corruption: 0
[14:40:35.373] <TB1> INFO: Decoding statistics:
[14:40:35.373] <TB1> INFO: General information:
[14:40:35.373] <TB1> INFO: 16bit words read: 3413582
[14:40:35.373] <TB1> INFO: valid events total: 353536
[14:40:35.373] <TB1> INFO: empty events: 20772
[14:40:35.373] <TB1> INFO: valid events with pixels: 332764
[14:40:35.373] <TB1> INFO: valid pixel hits: 646183
[14:40:35.373] <TB1> INFO: Event errors: 0
[14:40:35.373] <TB1> INFO: start marker: 0
[14:40:35.373] <TB1> INFO: stop marker: 0
[14:40:35.373] <TB1> INFO: overflow: 0
[14:40:35.373] <TB1> INFO: invalid 5bit words: 0
[14:40:35.373] <TB1> INFO: invalid XOR eye diagram: 0
[14:40:35.373] <TB1> INFO: frame (failed synchr.): 0
[14:40:35.373] <TB1> INFO: idle data (no TBM trl): 0
[14:40:35.373] <TB1> INFO: no data (only TBM hdr): 0
[14:40:35.373] <TB1> INFO: TBM errors: 0
[14:40:35.373] <TB1> INFO: flawed TBM headers: 0
[14:40:35.373] <TB1> INFO: flawed TBM trailers: 0
[14:40:35.373] <TB1> INFO: event ID mismatches: 0
[14:40:35.373] <TB1> INFO: ROC errors: 0
[14:40:35.373] <TB1> INFO: missing ROC header(s): 0
[14:40:35.373] <TB1> INFO: misplaced readback start: 0
[14:40:35.373] <TB1> INFO: Pixel decoding errors: 0
[14:40:35.373] <TB1> INFO: pixel data incomplete: 0
[14:40:35.373] <TB1> INFO: pixel address: 0
[14:40:35.373] <TB1> INFO: pulse height fill bit: 0
[14:40:35.373] <TB1> INFO: buffer corruption: 0
[14:40:35.373] <TB1> INFO: enter test to run
[14:40:35.373] <TB1> INFO: test: Trim80 no parameter change
[14:40:35.373] <TB1> INFO: running: trim80
[14:40:35.389] <TB1> INFO: ######################################################################
[14:40:35.389] <TB1> INFO: PixTestTrim80::doTest()
[14:40:35.389] <TB1> INFO: ######################################################################
[14:40:35.390] <TB1> INFO: ----------------------------------------------------------------------
[14:40:35.390] <TB1> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[14:40:35.390] <TB1> INFO: ----------------------------------------------------------------------
[14:40:35.456] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:40:35.456] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:40:35.468] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:40:35.468] <TB1> INFO: run 1 of 1
[14:40:35.765] <TB1> INFO: Expecting 5025280 events.
[14:41:04.451] <TB1> INFO: 692104 events read in total (28095ms).
[14:41:32.541] <TB1> INFO: 1379408 events read in total (56185ms).
[14:42:00.837] <TB1> INFO: 2062920 events read in total (84481ms).
[14:42:28.407] <TB1> INFO: 2744968 events read in total (112051ms).
[14:42:56.891] <TB1> INFO: 3426920 events read in total (140535ms).
[14:43:24.681] <TB1> INFO: 4108520 events read in total (168325ms).
[14:43:52.496] <TB1> INFO: 4789888 events read in total (196140ms).
[14:44:02.295] <TB1> INFO: 5025280 events read in total (205939ms).
[14:44:02.346] <TB1> INFO: Test took 206878ms.
[14:44:21.166] <TB1> INFO: ROC 0 VthrComp = 74
[14:44:21.167] <TB1> INFO: ROC 1 VthrComp = 76
[14:44:21.167] <TB1> INFO: ROC 2 VthrComp = 77
[14:44:21.167] <TB1> INFO: ROC 3 VthrComp = 75
[14:44:21.167] <TB1> INFO: ROC 4 VthrComp = 73
[14:44:21.167] <TB1> INFO: ROC 5 VthrComp = 75
[14:44:21.167] <TB1> INFO: ROC 6 VthrComp = 73
[14:44:21.167] <TB1> INFO: ROC 7 VthrComp = 82
[14:44:21.168] <TB1> INFO: ROC 8 VthrComp = 74
[14:44:21.168] <TB1> INFO: ROC 9 VthrComp = 77
[14:44:21.168] <TB1> INFO: ROC 10 VthrComp = 79
[14:44:21.168] <TB1> INFO: ROC 11 VthrComp = 79
[14:44:21.168] <TB1> INFO: ROC 12 VthrComp = 81
[14:44:21.168] <TB1> INFO: ROC 13 VthrComp = 85
[14:44:21.168] <TB1> INFO: ROC 14 VthrComp = 82
[14:44:21.168] <TB1> INFO: ROC 15 VthrComp = 78
[14:44:21.402] <TB1> INFO: Expecting 41600 events.
[14:44:25.055] <TB1> INFO: 41600 events read in total (3061ms).
[14:44:25.056] <TB1> INFO: Test took 3886ms.
[14:44:25.064] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:44:25.064] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:44:25.073] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:44:25.073] <TB1> INFO: run 1 of 1
[14:44:25.351] <TB1> INFO: Expecting 5025280 events.
[14:44:54.108] <TB1> INFO: 688288 events read in total (28165ms).
[14:45:22.085] <TB1> INFO: 1371328 events read in total (56142ms).
[14:45:49.951] <TB1> INFO: 2053728 events read in total (84008ms).
[14:46:17.806] <TB1> INFO: 2732320 events read in total (111863ms).
[14:46:44.897] <TB1> INFO: 3407632 events read in total (138954ms).
[14:47:13.050] <TB1> INFO: 4082584 events read in total (167107ms).
[14:47:40.569] <TB1> INFO: 4758416 events read in total (194626ms).
[14:47:51.856] <TB1> INFO: 5025280 events read in total (205913ms).
[14:47:51.922] <TB1> INFO: Test took 206849ms.
[14:48:12.244] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 112.969 for pixel 9/72 mean/min/max = 95.2507/77.4315/113.07
[14:48:12.245] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 111.592 for pixel 4/79 mean/min/max = 94.6833/77.7625/111.604
[14:48:12.245] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 110.637 for pixel 30/9 mean/min/max = 94.4389/78.1122/110.766
[14:48:12.245] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 111.604 for pixel 49/5 mean/min/max = 94.3978/77.173/111.623
[14:48:12.246] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 113.779 for pixel 4/78 mean/min/max = 95.2534/76.6894/113.817
[14:48:12.246] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 111.694 for pixel 2/31 mean/min/max = 95.069/78.4405/111.697
[14:48:12.246] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 109.346 for pixel 51/8 mean/min/max = 93.2953/77.2187/109.372
[14:48:12.246] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 107.271 for pixel 1/79 mean/min/max = 91.1621/74.9373/107.387
[14:48:12.247] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 110.854 for pixel 1/36 mean/min/max = 94.3075/77.5449/111.07
[14:48:12.247] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 112.187 for pixel 0/56 mean/min/max = 95.0192/77.7125/112.326
[14:48:12.247] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 114.543 for pixel 7/75 mean/min/max = 94.9951/75.4259/114.564
[14:48:12.248] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 111.513 for pixel 0/74 mean/min/max = 95.0442/78.4107/111.678
[14:48:12.248] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 107.257 for pixel 38/73 mean/min/max = 91.1196/74.9328/107.306
[14:48:12.248] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 109.469 for pixel 17/1 mean/min/max = 92.0269/74.5158/109.538
[14:48:12.249] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 113.443 for pixel 6/79 mean/min/max = 93.6158/73.3871/113.844
[14:48:12.249] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 111.408 for pixel 8/79 mean/min/max = 94.2604/77.0681/111.453
[14:48:12.249] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:12.338] <TB1> INFO: Expecting 411648 events.
[14:48:21.845] <TB1> INFO: 411648 events read in total (8916ms).
[14:48:21.852] <TB1> INFO: Expecting 411648 events.
[14:48:31.099] <TB1> INFO: 411648 events read in total (8844ms).
[14:48:31.111] <TB1> INFO: Expecting 411648 events.
[14:48:40.310] <TB1> INFO: 411648 events read in total (8796ms).
[14:48:40.327] <TB1> INFO: Expecting 411648 events.
[14:48:49.439] <TB1> INFO: 411648 events read in total (8709ms).
[14:48:49.453] <TB1> INFO: Expecting 411648 events.
[14:48:58.809] <TB1> INFO: 411648 events read in total (8953ms).
[14:48:58.826] <TB1> INFO: Expecting 411648 events.
[14:49:08.053] <TB1> INFO: 411648 events read in total (8824ms).
[14:49:08.080] <TB1> INFO: Expecting 411648 events.
[14:49:17.409] <TB1> INFO: 411648 events read in total (8926ms).
[14:49:17.432] <TB1> INFO: Expecting 411648 events.
[14:49:26.868] <TB1> INFO: 411648 events read in total (9033ms).
[14:49:26.903] <TB1> INFO: Expecting 411648 events.
[14:49:36.059] <TB1> INFO: 411648 events read in total (8753ms).
[14:49:36.099] <TB1> INFO: Expecting 411648 events.
[14:49:45.230] <TB1> INFO: 411648 events read in total (8728ms).
[14:49:45.259] <TB1> INFO: Expecting 411648 events.
[14:49:54.662] <TB1> INFO: 411648 events read in total (9000ms).
[14:49:54.713] <TB1> INFO: Expecting 411648 events.
[14:50:03.995] <TB1> INFO: 411648 events read in total (8879ms).
[14:50:04.029] <TB1> INFO: Expecting 411648 events.
[14:50:13.272] <TB1> INFO: 411648 events read in total (8840ms).
[14:50:13.315] <TB1> INFO: Expecting 411648 events.
[14:50:22.737] <TB1> INFO: 411648 events read in total (9019ms).
[14:50:22.776] <TB1> INFO: Expecting 411648 events.
[14:50:31.958] <TB1> INFO: 411648 events read in total (8779ms).
[14:50:31.002] <TB1> INFO: Expecting 411648 events.
[14:50:41.233] <TB1> INFO: 411648 events read in total (8829ms).
[14:50:41.279] <TB1> INFO: Test took 149030ms.
[14:50:42.630] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:50:42.640] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:50:42.640] <TB1> INFO: run 1 of 1
[14:50:42.871] <TB1> INFO: Expecting 5025280 events.
[14:51:10.818] <TB1> INFO: 665336 events read in total (27355ms).
[14:51:38.381] <TB1> INFO: 1327728 events read in total (54918ms).
[14:52:06.192] <TB1> INFO: 1989584 events read in total (82729ms).
[14:52:33.363] <TB1> INFO: 2647912 events read in total (109900ms).
[14:53:00.520] <TB1> INFO: 3301216 events read in total (137057ms).
[14:53:27.733] <TB1> INFO: 3953664 events read in total (164270ms).
[14:53:54.623] <TB1> INFO: 4604032 events read in total (191160ms).
[14:54:12.331] <TB1> INFO: 5025280 events read in total (208868ms).
[14:54:12.380] <TB1> INFO: Test took 209740ms.
[14:54:32.531] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 48.626577 .. 99.878472
[14:54:32.812] <TB1> INFO: Expecting 208000 events.
[14:54:43.113] <TB1> INFO: 208000 events read in total (9709ms).
[14:54:43.113] <TB1> INFO: Test took 10580ms.
[14:54:43.173] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 38 .. 109 (-1/-1) hits flags = 528 (plus default)
[14:54:43.185] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:54:43.185] <TB1> INFO: run 1 of 1
[14:54:43.481] <TB1> INFO: Expecting 2396160 events.
[14:55:12.161] <TB1> INFO: 705424 events read in total (28089ms).
[14:55:40.416] <TB1> INFO: 1404920 events read in total (56344ms).
[14:56:08.839] <TB1> INFO: 2097200 events read in total (84767ms).
[14:56:21.376] <TB1> INFO: 2396160 events read in total (97304ms).
[14:56:21.411] <TB1> INFO: Test took 98225ms.
[14:56:37.433] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 59.560393 .. 88.320647
[14:56:37.729] <TB1> INFO: Expecting 208000 events.
[14:56:47.979] <TB1> INFO: 208000 events read in total (9659ms).
[14:56:47.980] <TB1> INFO: Test took 10545ms.
[14:56:48.052] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 49 .. 98 (-1/-1) hits flags = 528 (plus default)
[14:56:48.063] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:56:48.063] <TB1> INFO: run 1 of 1
[14:56:48.341] <TB1> INFO: Expecting 1664000 events.
[14:57:17.267] <TB1> INFO: 715512 events read in total (28334ms).
[14:57:46.345] <TB1> INFO: 1430040 events read in total (57412ms).
[14:57:56.105] <TB1> INFO: 1664000 events read in total (67173ms).
[14:57:56.134] <TB1> INFO: Test took 68071ms.
[14:58:11.137] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 63.668125 .. 83.354971
[14:58:11.370] <TB1> INFO: Expecting 208000 events.
[14:58:21.349] <TB1> INFO: 208000 events read in total (9388ms).
[14:58:21.350] <TB1> INFO: Test took 10211ms.
[14:58:21.423] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 53 .. 93 (-1/-1) hits flags = 528 (plus default)
[14:58:21.435] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:58:21.435] <TB1> INFO: run 1 of 1
[14:58:21.713] <TB1> INFO: Expecting 1364480 events.
[14:58:51.929] <TB1> INFO: 732256 events read in total (29625ms).
[14:59:17.674] <TB1> INFO: 1364480 events read in total (55370ms).
[14:59:17.697] <TB1> INFO: Test took 56263ms.
[14:59:31.356] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 67.871504 .. 82.173416
[14:59:31.590] <TB1> INFO: Expecting 208000 events.
[14:59:41.126] <TB1> INFO: 208000 events read in total (8944ms).
[14:59:41.127] <TB1> INFO: Test took 9769ms.
[14:59:41.183] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 57 .. 92 (-1/-1) hits flags = 528 (plus default)
[14:59:41.195] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:59:41.195] <TB1> INFO: run 1 of 1
[14:59:41.473] <TB1> INFO: Expecting 1198080 events.
[15:00:11.072] <TB1> INFO: 726624 events read in total (29007ms).
[15:00:30.132] <TB1> INFO: 1198080 events read in total (48068ms).
[15:00:30.156] <TB1> INFO: Test took 48961ms.
[15:00:44.286] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[15:00:44.286] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[15:00:44.296] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[15:00:44.296] <TB1> INFO: run 1 of 1
[15:00:44.528] <TB1> INFO: Expecting 1364480 events.
[15:01:13.243] <TB1> INFO: 668760 events read in total (28124ms).
[15:01:40.745] <TB1> INFO: 1336864 events read in total (55626ms).
[15:01:42.371] <TB1> INFO: 1364480 events read in total (57252ms).
[15:01:42.394] <TB1> INFO: Test took 58098ms.
[15:01:57.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C0.dat
[15:01:57.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C1.dat
[15:01:57.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C2.dat
[15:01:57.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C3.dat
[15:01:57.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C4.dat
[15:01:57.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C5.dat
[15:01:57.802] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C6.dat
[15:01:57.803] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C7.dat
[15:01:57.803] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C8.dat
[15:01:57.803] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C9.dat
[15:01:57.803] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C10.dat
[15:01:57.803] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C11.dat
[15:01:57.803] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C12.dat
[15:01:57.803] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C13.dat
[15:01:57.803] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C14.dat
[15:01:57.803] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//dacParameters80_C15.dat
[15:01:57.803] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C0.dat
[15:01:57.808] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C1.dat
[15:01:57.814] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C2.dat
[15:01:57.819] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C3.dat
[15:01:57.825] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C4.dat
[15:01:57.830] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C5.dat
[15:01:57.835] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C6.dat
[15:01:57.841] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C7.dat
[15:01:57.846] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C8.dat
[15:01:57.852] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C9.dat
[15:01:57.857] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C10.dat
[15:01:57.863] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C11.dat
[15:01:57.868] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C12.dat
[15:01:57.873] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C13.dat
[15:01:57.879] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C14.dat
[15:01:57.884] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1091_FullQualification_2016-10-31_10h37m_1477906653//003_FulltestTrim80_p17//trimParameters80_C15.dat
[15:01:57.889] <TB1> INFO: PixTestTrim80::trimTest() done
[15:01:57.889] <TB1> INFO: vtrim: 120 106 112 123 123 118 102 110 95 121 129 121 111 114 117 134
[15:01:57.889] <TB1> INFO: vthrcomp: 74 76 77 75 73 75 73 82 74 77 79 79 81 85 82 78
[15:01:57.889] <TB1> INFO: vcal mean: 80.03 80.01 80.02 80.06 79.97 80.02 79.99 80.02 80.03 80.01 80.00 79.97 80.03 80.02 80.04 80.02
[15:01:57.889] <TB1> INFO: vcal RMS: 0.95 0.78 0.90 1.02 0.90 0.90 0.84 0.82 0.77 0.87 0.91 0.86 0.83 0.86 1.05 0.91
[15:01:57.889] <TB1> INFO: bits mean: 9.92 9.10 9.90 10.38 10.00 10.11 9.70 10.09 9.51 9.64 9.99 9.34 10.54 10.53 10.46 10.51
[15:01:57.889] <TB1> INFO: bits RMS: 2.04 2.34 1.99 1.88 2.06 1.86 2.18 2.43 2.20 2.14 2.20 2.18 2.21 2.18 2.24 1.87
[15:01:57.895] <TB1> INFO: ----------------------------------------------------------------------
[15:01:57.895] <TB1> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[15:01:57.895] <TB1> INFO: ----------------------------------------------------------------------
[15:01:57.898] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[15:01:57.908] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:01:57.908] <TB1> INFO: run 1 of 1
[15:01:58.204] <TB1> INFO: Expecting 4160000 events.
[15:02:32.028] <TB1> INFO: 787130 events read in total (33232ms).
[15:03:04.760] <TB1> INFO: 1565725 events read in total (65964ms).
[15:03:37.283] <TB1> INFO: 2337705 events read in total (98488ms).
[15:04:09.991] <TB1> INFO: 3104715 events read in total (131195ms).
[15:04:43.102] <TB1> INFO: 3870520 events read in total (164306ms).
[15:04:56.112] <TB1> INFO: 4160000 events read in total (177316ms).
[15:04:56.154] <TB1> INFO: Test took 178246ms.
[15:05:19.151] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[15:05:19.163] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:05:19.163] <TB1> INFO: run 1 of 1
[15:05:19.451] <TB1> INFO: Expecting 4472000 events.
[15:05:52.243] <TB1> INFO: 736550 events read in total (32200ms).
[15:06:24.575] <TB1> INFO: 1468080 events read in total (64532ms).
[15:06:56.558] <TB1> INFO: 2194685 events read in total (96515ms).
[15:07:28.314] <TB1> INFO: 2918250 events read in total (128271ms).
[15:08:00.086] <TB1> INFO: 3639740 events read in total (160043ms).
[15:08:32.321] <TB1> INFO: 4361830 events read in total (192278ms).
[15:08:37.259] <TB1> INFO: 4472000 events read in total (197216ms).
[15:08:37.310] <TB1> INFO: Test took 198146ms.
[15:09:02.513] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[15:09:02.525] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:09:02.525] <TB1> INFO: run 1 of 1
[15:09:02.780] <TB1> INFO: Expecting 4472000 events.
[15:09:35.230] <TB1> INFO: 736850 events read in total (31858ms).
[15:10:06.866] <TB1> INFO: 1468410 events read in total (63494ms).
[15:10:39.047] <TB1> INFO: 2195320 events read in total (95675ms).
[15:11:10.801] <TB1> INFO: 2919255 events read in total (127429ms).
[15:11:42.355] <TB1> INFO: 3641050 events read in total (158983ms).
[15:12:14.385] <TB1> INFO: 4363355 events read in total (191013ms).
[15:12:19.496] <TB1> INFO: 4472000 events read in total (196124ms).
[15:12:19.548] <TB1> INFO: Test took 197023ms.
[15:12:45.539] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[15:12:45.549] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:12:45.549] <TB1> INFO: run 1 of 1
[15:12:45.780] <TB1> INFO: Expecting 4472000 events.
[15:13:18.167] <TB1> INFO: 736920 events read in total (31795ms).
[15:13:50.085] <TB1> INFO: 1468535 events read in total (63713ms).
[15:14:21.768] <TB1> INFO: 2195425 events read in total (95396ms).
[15:14:53.325] <TB1> INFO: 2919380 events read in total (126953ms).
[15:15:24.990] <TB1> INFO: 3641240 events read in total (158618ms).
[15:15:56.759] <TB1> INFO: 4363660 events read in total (190387ms).
[15:16:01.822] <TB1> INFO: 4472000 events read in total (195450ms).
[15:16:01.894] <TB1> INFO: Test took 196345ms.
[15:16:26.037] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[15:16:26.050] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:16:26.051] <TB1> INFO: run 1 of 1
[15:16:26.295] <TB1> INFO: Expecting 4472000 events.
[15:16:59.020] <TB1> INFO: 736930 events read in total (32134ms).
[15:17:30.602] <TB1> INFO: 1468905 events read in total (63716ms).
[15:18:02.262] <TB1> INFO: 2195980 events read in total (95377ms).
[15:18:33.838] <TB1> INFO: 2919810 events read in total (126952ms).
[15:19:05.394] <TB1> INFO: 3641935 events read in total (158508ms).
[15:19:36.863] <TB1> INFO: 4364475 events read in total (189977ms).
[15:19:41.636] <TB1> INFO: 4472000 events read in total (194750ms).
[15:19:41.689] <TB1> INFO: Test took 195638ms.
[15:20:08.247] <TB1> INFO: PixTestTrim80::trimBitTest() done
[15:20:08.248] <TB1> INFO: PixTestTrim80::doTest() done, duration: 2372 seconds
[15:20:09.191] <TB1> INFO: enter test to run
[15:20:09.191] <TB1> INFO: test: exit no parameter change
[15:20:09.315] <TB1> QUIET: Connection to board 153 closed.
[15:20:09.316] <TB1> INFO: pXar: this is the end, my friend