[12:54:07.308] <TB2> INFO: *** Welcome to pxar ***
[12:54:07.308] <TB2> INFO: *** Today: 2016/10/26
[12:54:07.314] <TB2> INFO: *** Version: c8ba-dirty
[12:54:07.314] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C15.dat
[12:54:07.314] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//tbmParameters_C1b.dat
[12:54:07.314] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//defaultMaskFile.dat
[12:54:07.314] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters_C15.dat
[12:54:07.376] <TB2> INFO: clk: 4
[12:54:07.376] <TB2> INFO: ctr: 4
[12:54:07.376] <TB2> INFO: sda: 19
[12:54:07.376] <TB2> INFO: tin: 9
[12:54:07.376] <TB2> INFO: level: 15
[12:54:07.376] <TB2> INFO: triggerdelay: 0
[12:54:07.376] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[12:54:07.376] <TB2> INFO: Log level: INFO
[12:54:07.384] <TB2> INFO: Found DTB DTB_WWXUD2
[12:54:07.392] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[12:54:07.393] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[12:54:07.395] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[12:54:08.887] <TB2> INFO: DUT info:
[12:54:08.887] <TB2> INFO: The DUT currently contains the following objects:
[12:54:08.887] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[12:54:08.887] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:54:08.887] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:54:08.887] <TB2> INFO: TBM Core alpha (2): 7 registers set
[12:54:08.888] <TB2> INFO: TBM Core beta (3): 7 registers set
[12:54:08.888] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[12:54:08.888] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:08.888] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:54:09.289] <TB2> INFO: enter 'restricted' command line mode
[12:54:09.289] <TB2> INFO: enter test to run
[12:54:09.289] <TB2> INFO: test: pretest no parameter change
[12:54:09.289] <TB2> INFO: running: pretest
[12:54:09.294] <TB2> INFO: ######################################################################
[12:54:09.294] <TB2> INFO: PixTestPretest::doTest()
[12:54:09.294] <TB2> INFO: ######################################################################
[12:54:09.295] <TB2> INFO: ----------------------------------------------------------------------
[12:54:09.295] <TB2> INFO: PixTestPretest::programROC()
[12:54:09.295] <TB2> INFO: ----------------------------------------------------------------------
[12:54:27.309] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:54:27.309] <TB2> INFO: IA differences per ROC: 17.7 16.9 16.9 19.3 19.3 19.3 20.1 17.7 17.7 19.3 20.9 20.1 17.7 20.1 19.3 17.7
[12:54:27.368] <TB2> INFO: ----------------------------------------------------------------------
[12:54:27.368] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:54:27.368] <TB2> INFO: ----------------------------------------------------------------------
[12:54:34.871] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 390.7 mA = 24.4187 mA/ROC
[12:54:34.871] <TB2> INFO: i(loss) [mA/ROC]: 20.1 20.1 20.1 20.1 20.1 20.1 20.1 20.1 20.1 20.9 20.1 20.9 20.1 20.9 20.1 20.1
[12:54:34.907] <TB2> INFO: ----------------------------------------------------------------------
[12:54:34.907] <TB2> INFO: PixTestPretest::findTiming()
[12:54:34.907] <TB2> INFO: ----------------------------------------------------------------------
[12:54:34.907] <TB2> INFO: PixTestCmd::init()

[12:55:07.080] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:55:07.080] <TB2> INFO: (success/tries = 100/100), width = 3
[12:55:08.583] <TB2> INFO: ----------------------------------------------------------------------
[12:55:08.583] <TB2> INFO: PixTestPretest::findWorkingPixel()
[12:55:08.583] <TB2> INFO: ----------------------------------------------------------------------
[12:55:08.678] <TB2> INFO: Expecting 231680 events.
[12:55:18.629] <TB2> INFO: 231680 events read in total (9360ms).
[12:55:18.638] <TB2> INFO: Test took 10050ms.
[12:55:18.887] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:55:18.918] <TB2> INFO: ----------------------------------------------------------------------
[12:55:18.918] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[12:55:18.918] <TB2> INFO: ----------------------------------------------------------------------
[12:55:19.012] <TB2> INFO: Expecting 231680 events.
[12:55:28.983] <TB2> INFO: 231680 events read in total (9378ms).
[12:55:28.993] <TB2> INFO: Test took 10071ms.
[12:55:29.259] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[12:55:29.259] <TB2> INFO: CalDel: 107 91 114 106 92 96 106 91 112 106 101 110 109 95 99 108
[12:55:29.259] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 58 51 51 53 51 52
[12:55:29.263] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C0.dat
[12:55:29.263] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C1.dat
[12:55:29.263] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C2.dat
[12:55:29.263] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C3.dat
[12:55:29.263] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C4.dat
[12:55:29.264] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C5.dat
[12:55:29.264] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C6.dat
[12:55:29.264] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C7.dat
[12:55:29.264] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C8.dat
[12:55:29.264] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C9.dat
[12:55:29.264] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C10.dat
[12:55:29.264] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C11.dat
[12:55:29.265] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C12.dat
[12:55:29.265] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C13.dat
[12:55:29.265] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C14.dat
[12:55:29.265] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters_C15.dat
[12:55:29.265] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//tbmParameters_C0a.dat
[12:55:29.265] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//tbmParameters_C0b.dat
[12:55:29.265] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//tbmParameters_C1a.dat
[12:55:29.265] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//tbmParameters_C1b.dat
[12:55:29.266] <TB2> INFO: PixTestPretest::doTest() done, duration: 79 seconds
[12:55:29.321] <TB2> INFO: enter test to run
[12:55:29.321] <TB2> INFO: test: FullTest no parameter change
[12:55:29.321] <TB2> INFO: running: fulltest
[12:55:29.321] <TB2> INFO: ######################################################################
[12:55:29.321] <TB2> INFO: PixTestFullTest::doTest()
[12:55:29.321] <TB2> INFO: ######################################################################
[12:55:29.323] <TB2> INFO: ######################################################################
[12:55:29.323] <TB2> INFO: PixTestAlive::doTest()
[12:55:29.323] <TB2> INFO: ######################################################################
[12:55:29.324] <TB2> INFO: ----------------------------------------------------------------------
[12:55:29.324] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:55:29.324] <TB2> INFO: ----------------------------------------------------------------------
[12:55:29.570] <TB2> INFO: Expecting 41600 events.
[12:55:33.101] <TB2> INFO: 41600 events read in total (2940ms).
[12:55:33.101] <TB2> INFO: Test took 3775ms.
[12:55:33.334] <TB2> INFO: PixTestAlive::aliveTest() done
[12:55:33.334] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:55:33.336] <TB2> INFO: ----------------------------------------------------------------------
[12:55:33.336] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:55:33.336] <TB2> INFO: ----------------------------------------------------------------------
[12:55:33.595] <TB2> INFO: Expecting 41600 events.
[12:55:36.581] <TB2> INFO: 41600 events read in total (2395ms).
[12:55:36.581] <TB2> INFO: Test took 3242ms.
[12:55:36.582] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:55:36.823] <TB2> INFO: PixTestAlive::maskTest() done
[12:55:36.823] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:55:36.825] <TB2> INFO: ----------------------------------------------------------------------
[12:55:36.825] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:55:36.825] <TB2> INFO: ----------------------------------------------------------------------
[12:55:37.066] <TB2> INFO: Expecting 41600 events.
[12:55:40.563] <TB2> INFO: 41600 events read in total (2905ms).
[12:55:40.564] <TB2> INFO: Test took 3737ms.
[12:55:40.796] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[12:55:40.796] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:55:40.797] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:55:40.797] <TB2> INFO: Decoding statistics:
[12:55:40.797] <TB2> INFO: General information:
[12:55:40.797] <TB2> INFO: 16bit words read: 0
[12:55:40.797] <TB2> INFO: valid events total: 0
[12:55:40.797] <TB2> INFO: empty events: 0
[12:55:40.797] <TB2> INFO: valid events with pixels: 0
[12:55:40.797] <TB2> INFO: valid pixel hits: 0
[12:55:40.797] <TB2> INFO: Event errors: 0
[12:55:40.797] <TB2> INFO: start marker: 0
[12:55:40.797] <TB2> INFO: stop marker: 0
[12:55:40.797] <TB2> INFO: overflow: 0
[12:55:40.797] <TB2> INFO: invalid 5bit words: 0
[12:55:40.797] <TB2> INFO: invalid XOR eye diagram: 0
[12:55:40.797] <TB2> INFO: frame (failed synchr.): 0
[12:55:40.797] <TB2> INFO: idle data (no TBM trl): 0
[12:55:40.797] <TB2> INFO: no data (only TBM hdr): 0
[12:55:40.797] <TB2> INFO: TBM errors: 0
[12:55:40.797] <TB2> INFO: flawed TBM headers: 0
[12:55:40.797] <TB2> INFO: flawed TBM trailers: 0
[12:55:40.797] <TB2> INFO: event ID mismatches: 0
[12:55:40.797] <TB2> INFO: ROC errors: 0
[12:55:40.797] <TB2> INFO: missing ROC header(s): 0
[12:55:40.797] <TB2> INFO: misplaced readback start: 0
[12:55:40.797] <TB2> INFO: Pixel decoding errors: 0
[12:55:40.797] <TB2> INFO: pixel data incomplete: 0
[12:55:40.797] <TB2> INFO: pixel address: 0
[12:55:40.797] <TB2> INFO: pulse height fill bit: 0
[12:55:40.797] <TB2> INFO: buffer corruption: 0
[12:55:40.808] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C15.dat
[12:55:40.808] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[12:55:40.808] <TB2> INFO: ######################################################################
[12:55:40.808] <TB2> INFO: PixTestReadback::doTest()
[12:55:40.808] <TB2> INFO: ######################################################################
[12:55:40.808] <TB2> INFO: ----------------------------------------------------------------------
[12:55:40.808] <TB2> INFO: PixTestReadback::CalibrateVd()
[12:55:40.808] <TB2> INFO: ----------------------------------------------------------------------
[12:55:50.784] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C0.dat
[12:55:50.784] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C1.dat
[12:55:50.785] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C2.dat
[12:55:50.785] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C3.dat
[12:55:50.785] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C4.dat
[12:55:50.785] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C5.dat
[12:55:50.785] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C6.dat
[12:55:50.785] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C7.dat
[12:55:50.785] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C8.dat
[12:55:50.785] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C9.dat
[12:55:50.785] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C10.dat
[12:55:50.786] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C11.dat
[12:55:50.786] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C12.dat
[12:55:50.786] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C13.dat
[12:55:50.786] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C14.dat
[12:55:50.786] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C15.dat
[12:55:50.816] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:55:50.816] <TB2> INFO: ----------------------------------------------------------------------
[12:55:50.816] <TB2> INFO: PixTestReadback::CalibrateVa()
[12:55:50.816] <TB2> INFO: ----------------------------------------------------------------------
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C0.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C1.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C2.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C3.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C4.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C5.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C6.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C7.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C8.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C9.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C10.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C11.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C12.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C13.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C14.dat
[12:56:00.746] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C15.dat
[12:56:00.775] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:56:00.775] <TB2> INFO: ----------------------------------------------------------------------
[12:56:00.775] <TB2> INFO: PixTestReadback::readbackVbg()
[12:56:00.775] <TB2> INFO: ----------------------------------------------------------------------
[12:56:08.439] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:56:08.440] <TB2> INFO: ----------------------------------------------------------------------
[12:56:08.440] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[12:56:08.440] <TB2> INFO: ----------------------------------------------------------------------
[12:56:08.440] <TB2> INFO: Vbg will be calibrated using Vd calibration
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 148.6calibrated Vbg = 1.17766 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 156.5calibrated Vbg = 1.18455 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 153.5calibrated Vbg = 1.18057 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 161.4calibrated Vbg = 1.17059 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 164.2calibrated Vbg = 1.17724 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 151.7calibrated Vbg = 1.18761 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 148.6calibrated Vbg = 1.18512 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 155.9calibrated Vbg = 1.17971 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 154.6calibrated Vbg = 1.17819 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 148.8calibrated Vbg = 1.17799 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 170.2calibrated Vbg = 1.16873 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 155.5calibrated Vbg = 1.1736 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 158.8calibrated Vbg = 1.17753 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 146.1calibrated Vbg = 1.17932 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 145.3calibrated Vbg = 1.18372 :::*/*/*/*/
[12:56:08.440] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 156.6calibrated Vbg = 1.17408 :::*/*/*/*/
[12:56:08.443] <TB2> INFO: ----------------------------------------------------------------------
[12:56:08.443] <TB2> INFO: PixTestReadback::CalibrateIa()
[12:56:08.443] <TB2> INFO: ----------------------------------------------------------------------
[12:58:49.271] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C0.dat
[12:58:49.272] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C1.dat
[12:58:49.272] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C2.dat
[12:58:49.272] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C3.dat
[12:58:49.272] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C4.dat
[12:58:49.272] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C5.dat
[12:58:49.272] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C6.dat
[12:58:49.272] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C7.dat
[12:58:49.272] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C8.dat
[12:58:49.272] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C9.dat
[12:58:49.272] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C10.dat
[12:58:49.272] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C11.dat
[12:58:49.272] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C12.dat
[12:58:49.272] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C13.dat
[12:58:49.272] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C14.dat
[12:58:49.273] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//readbackCal_C15.dat
[12:58:49.301] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:58:49.302] <TB2> INFO: PixTestReadback::doTest() done
[12:58:49.302] <TB2> INFO: Decoding statistics:
[12:58:49.302] <TB2> INFO: General information:
[12:58:49.302] <TB2> INFO: 16bit words read: 1536
[12:58:49.302] <TB2> INFO: valid events total: 256
[12:58:49.302] <TB2> INFO: empty events: 256
[12:58:49.302] <TB2> INFO: valid events with pixels: 0
[12:58:49.302] <TB2> INFO: valid pixel hits: 0
[12:58:49.302] <TB2> INFO: Event errors: 0
[12:58:49.302] <TB2> INFO: start marker: 0
[12:58:49.302] <TB2> INFO: stop marker: 0
[12:58:49.302] <TB2> INFO: overflow: 0
[12:58:49.302] <TB2> INFO: invalid 5bit words: 0
[12:58:49.302] <TB2> INFO: invalid XOR eye diagram: 0
[12:58:49.302] <TB2> INFO: frame (failed synchr.): 0
[12:58:49.302] <TB2> INFO: idle data (no TBM trl): 0
[12:58:49.302] <TB2> INFO: no data (only TBM hdr): 0
[12:58:49.302] <TB2> INFO: TBM errors: 0
[12:58:49.302] <TB2> INFO: flawed TBM headers: 0
[12:58:49.302] <TB2> INFO: flawed TBM trailers: 0
[12:58:49.302] <TB2> INFO: event ID mismatches: 0
[12:58:49.302] <TB2> INFO: ROC errors: 0
[12:58:49.302] <TB2> INFO: missing ROC header(s): 0
[12:58:49.302] <TB2> INFO: misplaced readback start: 0
[12:58:49.302] <TB2> INFO: Pixel decoding errors: 0
[12:58:49.302] <TB2> INFO: pixel data incomplete: 0
[12:58:49.302] <TB2> INFO: pixel address: 0
[12:58:49.302] <TB2> INFO: pulse height fill bit: 0
[12:58:49.302] <TB2> INFO: buffer corruption: 0
[12:58:49.353] <TB2> INFO: ######################################################################
[12:58:49.353] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:58:49.353] <TB2> INFO: ######################################################################
[12:58:49.356] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:58:49.379] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:58:49.379] <TB2> INFO: run 1 of 1
[12:58:49.615] <TB2> INFO: Expecting 3120000 events.
[12:59:20.795] <TB2> INFO: 669485 events read in total (30588ms).











[12:59:51.249] <TB2> INFO: 1333795 events read in total (61042ms).











[13:00:22.138] <TB2> INFO: 1995680 events read in total (91931ms).











[13:00:52.720] <TB2> INFO: 2658555 events read in total (122513ms).
[13:01:14.584] <TB2> INFO: 3120000 events read in total (144377ms).
[13:01:14.676] <TB2> INFO: Test took 145298ms.
[13:01:39.206] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 169 seconds
[13:01:39.206] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:01:39.206] <TB2> INFO: separation cut (per ROC): 106 106 100 111 113 103 108 106 102 112 119 110 111 114 104 117
[13:01:39.206] <TB2> INFO: Decoding statistics:
[13:01:39.206] <TB2> INFO: General information:
[13:01:39.206] <TB2> INFO: 16bit words read: 0
[13:01:39.206] <TB2> INFO: valid events total: 0
[13:01:39.206] <TB2> INFO: empty events: 0
[13:01:39.206] <TB2> INFO: valid events with pixels: 0
[13:01:39.206] <TB2> INFO: valid pixel hits: 0
[13:01:39.206] <TB2> INFO: Event errors: 0
[13:01:39.206] <TB2> INFO: start marker: 0
[13:01:39.206] <TB2> INFO: stop marker: 0
[13:01:39.206] <TB2> INFO: overflow: 0
[13:01:39.206] <TB2> INFO: invalid 5bit words: 0
[13:01:39.206] <TB2> INFO: invalid XOR eye diagram: 0
[13:01:39.206] <TB2> INFO: frame (failed synchr.): 0
[13:01:39.206] <TB2> INFO: idle data (no TBM trl): 0
[13:01:39.206] <TB2> INFO: no data (only TBM hdr): 0
[13:01:39.206] <TB2> INFO: TBM errors: 0
[13:01:39.206] <TB2> INFO: flawed TBM headers: 0
[13:01:39.206] <TB2> INFO: flawed TBM trailers: 0
[13:01:39.206] <TB2> INFO: event ID mismatches: 0
[13:01:39.206] <TB2> INFO: ROC errors: 0
[13:01:39.206] <TB2> INFO: missing ROC header(s): 0
[13:01:39.206] <TB2> INFO: misplaced readback start: 0
[13:01:39.206] <TB2> INFO: Pixel decoding errors: 0
[13:01:39.206] <TB2> INFO: pixel data incomplete: 0
[13:01:39.206] <TB2> INFO: pixel address: 0
[13:01:39.206] <TB2> INFO: pulse height fill bit: 0
[13:01:39.206] <TB2> INFO: buffer corruption: 0
[13:01:39.243] <TB2> INFO: ######################################################################
[13:01:39.243] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:01:39.243] <TB2> INFO: ######################################################################
[13:01:39.243] <TB2> INFO: ----------------------------------------------------------------------
[13:01:39.243] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:01:39.243] <TB2> INFO: ----------------------------------------------------------------------
[13:01:39.243] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[13:01:39.259] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[13:01:39.259] <TB2> INFO: run 1 of 1
[13:01:39.523] <TB2> INFO: Expecting 36608000 events.
[13:02:02.943] <TB2> INFO: 678800 events read in total (22828ms).
[13:02:25.698] <TB2> INFO: 1344900 events read in total (45583ms).
[13:02:48.827] <TB2> INFO: 2010800 events read in total (68712ms).
[13:03:11.707] <TB2> INFO: 2674400 events read in total (91592ms).
[13:03:34.529] <TB2> INFO: 3340850 events read in total (114414ms).
[13:03:57.328] <TB2> INFO: 4007350 events read in total (137213ms).
[13:04:20.161] <TB2> INFO: 4673150 events read in total (160046ms).
[13:04:43.048] <TB2> INFO: 5340300 events read in total (182933ms).
[13:05:06.082] <TB2> INFO: 6007250 events read in total (205967ms).
[13:05:29.256] <TB2> INFO: 6672650 events read in total (229141ms).
[13:05:52.268] <TB2> INFO: 7337400 events read in total (252153ms).
[13:06:14.966] <TB2> INFO: 8001550 events read in total (274852ms).
[13:06:37.729] <TB2> INFO: 8666000 events read in total (297614ms).
[13:07:00.684] <TB2> INFO: 9331650 events read in total (320569ms).
[13:07:23.749] <TB2> INFO: 9996450 events read in total (343634ms).
[13:07:46.304] <TB2> INFO: 10661350 events read in total (366189ms).
[13:08:09.390] <TB2> INFO: 11324350 events read in total (389275ms).
[13:08:32.616] <TB2> INFO: 11989550 events read in total (412501ms).
[13:08:55.462] <TB2> INFO: 12652800 events read in total (435347ms).
[13:09:18.513] <TB2> INFO: 13316400 events read in total (458398ms).
[13:09:41.516] <TB2> INFO: 13980250 events read in total (481401ms).
[13:10:04.518] <TB2> INFO: 14644650 events read in total (504403ms).
[13:10:27.583] <TB2> INFO: 15308300 events read in total (527468ms).
[13:10:50.607] <TB2> INFO: 15970500 events read in total (550492ms).
[13:11:13.314] <TB2> INFO: 16632400 events read in total (573199ms).
[13:11:36.229] <TB2> INFO: 17296400 events read in total (596114ms).
[13:11:58.973] <TB2> INFO: 17958600 events read in total (618858ms).
[13:12:21.931] <TB2> INFO: 18620050 events read in total (641816ms).
[13:12:45.118] <TB2> INFO: 19280400 events read in total (665003ms).
[13:13:07.843] <TB2> INFO: 19941000 events read in total (687728ms).
[13:13:31.026] <TB2> INFO: 20600450 events read in total (710911ms).
[13:13:54.249] <TB2> INFO: 21260800 events read in total (734134ms).
[13:14:17.457] <TB2> INFO: 21920550 events read in total (757343ms).
[13:14:40.157] <TB2> INFO: 22579000 events read in total (780042ms).
[13:15:03.299] <TB2> INFO: 23238900 events read in total (803184ms).
[13:15:26.456] <TB2> INFO: 23897350 events read in total (826341ms).
[13:15:49.410] <TB2> INFO: 24556950 events read in total (849295ms).
[13:16:12.064] <TB2> INFO: 25215100 events read in total (871949ms).
[13:16:34.924] <TB2> INFO: 25873800 events read in total (894809ms).
[13:16:57.620] <TB2> INFO: 26531250 events read in total (917505ms).
[13:17:20.391] <TB2> INFO: 27191350 events read in total (940276ms).
[13:17:43.536] <TB2> INFO: 27851400 events read in total (963421ms).
[13:18:06.341] <TB2> INFO: 28511000 events read in total (986226ms).
[13:18:29.413] <TB2> INFO: 29170950 events read in total (1009298ms).
[13:18:52.143] <TB2> INFO: 29830100 events read in total (1032028ms).
[13:19:14.947] <TB2> INFO: 30488000 events read in total (1054832ms).
[13:19:37.786] <TB2> INFO: 31147000 events read in total (1077671ms).
[13:20:00.468] <TB2> INFO: 31805400 events read in total (1100353ms).
[13:20:23.057] <TB2> INFO: 32462250 events read in total (1122942ms).
[13:20:46.038] <TB2> INFO: 33122600 events read in total (1145923ms).
[13:21:08.884] <TB2> INFO: 33783250 events read in total (1168769ms).
[13:21:31.889] <TB2> INFO: 34443900 events read in total (1191774ms).
[13:21:54.999] <TB2> INFO: 35104000 events read in total (1214884ms).
[13:22:17.673] <TB2> INFO: 35765700 events read in total (1237558ms).
[13:22:40.791] <TB2> INFO: 36438500 events read in total (1260676ms).
[13:22:46.604] <TB2> INFO: 36608000 events read in total (1266489ms).
[13:22:46.695] <TB2> INFO: Test took 1267437ms.
[13:22:47.083] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:22:48.549] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:22:50.123] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:22:51.704] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:22:53.263] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:22:54.882] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:22:56.474] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:22:58.044] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:22:59.587] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:23:01.153] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:23:03.260] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:23:05.247] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:23:07.306] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:23:09.266] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:23:10.954] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:23:12.567] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:23:14.072] <TB2> INFO: PixTestScurves::scurves() done
[13:23:14.072] <TB2> INFO: Vcal mean: 115.72 113.72 106.51 116.89 116.87 106.40 122.75 123.55 109.57 117.33 131.56 119.07 119.64 118.25 104.24 128.14
[13:23:14.072] <TB2> INFO: Vcal RMS: 5.49 5.25 5.10 5.96 5.43 4.81 6.05 6.14 5.05 5.45 6.72 5.68 5.68 5.53 5.34 6.25
[13:23:14.072] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1294 seconds
[13:23:14.072] <TB2> INFO: Decoding statistics:
[13:23:14.072] <TB2> INFO: General information:
[13:23:14.072] <TB2> INFO: 16bit words read: 0
[13:23:14.072] <TB2> INFO: valid events total: 0
[13:23:14.072] <TB2> INFO: empty events: 0
[13:23:14.072] <TB2> INFO: valid events with pixels: 0
[13:23:14.072] <TB2> INFO: valid pixel hits: 0
[13:23:14.072] <TB2> INFO: Event errors: 0
[13:23:14.072] <TB2> INFO: start marker: 0
[13:23:14.072] <TB2> INFO: stop marker: 0
[13:23:14.072] <TB2> INFO: overflow: 0
[13:23:14.072] <TB2> INFO: invalid 5bit words: 0
[13:23:14.072] <TB2> INFO: invalid XOR eye diagram: 0
[13:23:14.072] <TB2> INFO: frame (failed synchr.): 0
[13:23:14.072] <TB2> INFO: idle data (no TBM trl): 0
[13:23:14.072] <TB2> INFO: no data (only TBM hdr): 0
[13:23:14.072] <TB2> INFO: TBM errors: 0
[13:23:14.072] <TB2> INFO: flawed TBM headers: 0
[13:23:14.072] <TB2> INFO: flawed TBM trailers: 0
[13:23:14.073] <TB2> INFO: event ID mismatches: 0
[13:23:14.073] <TB2> INFO: ROC errors: 0
[13:23:14.073] <TB2> INFO: missing ROC header(s): 0
[13:23:14.073] <TB2> INFO: misplaced readback start: 0
[13:23:14.073] <TB2> INFO: Pixel decoding errors: 0
[13:23:14.073] <TB2> INFO: pixel data incomplete: 0
[13:23:14.073] <TB2> INFO: pixel address: 0
[13:23:14.073] <TB2> INFO: pulse height fill bit: 0
[13:23:14.073] <TB2> INFO: buffer corruption: 0
[13:23:14.151] <TB2> INFO: ######################################################################
[13:23:14.151] <TB2> INFO: PixTestTrim::doTest()
[13:23:14.151] <TB2> INFO: ######################################################################
[13:23:14.152] <TB2> INFO: ----------------------------------------------------------------------
[13:23:14.152] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[13:23:14.152] <TB2> INFO: ----------------------------------------------------------------------
[13:23:14.202] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:23:14.202] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:23:14.215] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:23:14.215] <TB2> INFO: run 1 of 1
[13:23:14.452] <TB2> INFO: Expecting 5025280 events.
[13:23:46.331] <TB2> INFO: 824768 events read in total (31276ms).
[13:24:17.017] <TB2> INFO: 1648032 events read in total (61962ms).
[13:24:47.266] <TB2> INFO: 2469424 events read in total (92212ms).
[13:25:17.900] <TB2> INFO: 3286088 events read in total (122845ms).
[13:25:48.234] <TB2> INFO: 4100608 events read in total (153180ms).
[13:26:18.271] <TB2> INFO: 4912344 events read in total (183216ms).
[13:26:23.291] <TB2> INFO: 5025280 events read in total (188236ms).
[13:26:23.359] <TB2> INFO: Test took 189144ms.
[13:26:44.043] <TB2> INFO: ROC 0 VthrComp = 122
[13:26:44.043] <TB2> INFO: ROC 1 VthrComp = 117
[13:26:44.043] <TB2> INFO: ROC 2 VthrComp = 106
[13:26:44.044] <TB2> INFO: ROC 3 VthrComp = 122
[13:26:44.044] <TB2> INFO: ROC 4 VthrComp = 130
[13:26:44.044] <TB2> INFO: ROC 5 VthrComp = 113
[13:26:44.044] <TB2> INFO: ROC 6 VthrComp = 125
[13:26:44.044] <TB2> INFO: ROC 7 VthrComp = 130
[13:26:44.044] <TB2> INFO: ROC 8 VthrComp = 112
[13:26:44.044] <TB2> INFO: ROC 9 VthrComp = 121
[13:26:44.044] <TB2> INFO: ROC 10 VthrComp = 133
[13:26:44.044] <TB2> INFO: ROC 11 VthrComp = 123
[13:26:44.044] <TB2> INFO: ROC 12 VthrComp = 126
[13:26:44.044] <TB2> INFO: ROC 13 VthrComp = 128
[13:26:44.044] <TB2> INFO: ROC 14 VthrComp = 107
[13:26:44.045] <TB2> INFO: ROC 15 VthrComp = 130
[13:26:44.285] <TB2> INFO: Expecting 41600 events.
[13:26:47.762] <TB2> INFO: 41600 events read in total (2885ms).
[13:26:47.762] <TB2> INFO: Test took 3716ms.
[13:26:47.771] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:26:47.771] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:26:47.783] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:26:47.783] <TB2> INFO: run 1 of 1
[13:26:48.062] <TB2> INFO: Expecting 5025280 events.
[13:27:15.094] <TB2> INFO: 588008 events read in total (26441ms).
[13:27:40.727] <TB2> INFO: 1175520 events read in total (52074ms).
[13:28:06.500] <TB2> INFO: 1763296 events read in total (77847ms).
[13:28:32.485] <TB2> INFO: 2351128 events read in total (103832ms).
[13:28:58.052] <TB2> INFO: 2937304 events read in total (129399ms).
[13:29:23.687] <TB2> INFO: 3522256 events read in total (155034ms).
[13:29:49.637] <TB2> INFO: 4106904 events read in total (180984ms).
[13:30:15.360] <TB2> INFO: 4691376 events read in total (206707ms).
[13:30:29.649] <TB2> INFO: 5025280 events read in total (220996ms).
[13:30:29.729] <TB2> INFO: Test took 221946ms.
[13:30:55.319] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 59.3331 for pixel 2/16 mean/min/max = 45.4948/31.2928/59.6968
[13:30:55.320] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 61.0547 for pixel 9/8 mean/min/max = 46.2445/31.4341/61.0549
[13:30:55.320] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 62.4139 for pixel 20/46 mean/min/max = 48.2333/34.0112/62.4554
[13:30:55.321] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.8418 for pixel 16/1 mean/min/max = 45.3396/29.7574/60.9219
[13:30:55.321] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 57.4825 for pixel 51/39 mean/min/max = 44.7742/31.728/57.8204
[13:30:55.322] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 57.2975 for pixel 0/21 mean/min/max = 44.8909/32.4218/57.36
[13:30:55.322] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 60.3077 for pixel 14/4 mean/min/max = 45.8191/31.3303/60.3078
[13:30:55.323] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 59.7082 for pixel 17/3 mean/min/max = 45.4798/30.9277/60.032
[13:30:55.323] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 59.8385 for pixel 30/16 mean/min/max = 46.3338/32.6243/60.0433
[13:30:55.323] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 60.4729 for pixel 8/69 mean/min/max = 46.2632/31.9952/60.5312
[13:30:55.324] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 69.3496 for pixel 0/41 mean/min/max = 53.0576/36.5411/69.5742
[13:30:55.324] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 60.8819 for pixel 16/14 mean/min/max = 46.5445/32.0565/61.0326
[13:30:55.324] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 59.1511 for pixel 22/9 mean/min/max = 45.0346/30.6894/59.3799
[13:30:55.325] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 58.7361 for pixel 8/18 mean/min/max = 44.7764/30.6735/58.8794
[13:30:55.325] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 61.9026 for pixel 32/40 mean/min/max = 48.5792/35.0564/62.1019
[13:30:55.325] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 61.201 for pixel 10/27 mean/min/max = 46.3846/31.3342/61.435
[13:30:55.326] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:30:55.415] <TB2> INFO: Expecting 411648 events.
[13:31:04.748] <TB2> INFO: 411648 events read in total (8741ms).
[13:31:04.756] <TB2> INFO: Expecting 411648 events.
[13:31:13.872] <TB2> INFO: 411648 events read in total (8713ms).
[13:31:13.883] <TB2> INFO: Expecting 411648 events.
[13:31:23.003] <TB2> INFO: 411648 events read in total (8717ms).
[13:31:23.018] <TB2> INFO: Expecting 411648 events.
[13:31:32.339] <TB2> INFO: 411648 events read in total (8918ms).
[13:31:32.355] <TB2> INFO: Expecting 411648 events.
[13:31:41.653] <TB2> INFO: 411648 events read in total (8895ms).
[13:31:41.672] <TB2> INFO: Expecting 411648 events.
[13:31:50.970] <TB2> INFO: 411648 events read in total (8895ms).
[13:31:50.997] <TB2> INFO: Expecting 411648 events.
[13:32:00.236] <TB2> INFO: 411648 events read in total (8836ms).
[13:32:00.261] <TB2> INFO: Expecting 411648 events.
[13:32:09.484] <TB2> INFO: 411648 events read in total (8820ms).
[13:32:09.511] <TB2> INFO: Expecting 411648 events.
[13:32:18.828] <TB2> INFO: 411648 events read in total (8914ms).
[13:32:18.860] <TB2> INFO: Expecting 411648 events.
[13:32:27.988] <TB2> INFO: 411648 events read in total (8725ms).
[13:32:28.020] <TB2> INFO: Expecting 411648 events.
[13:32:37.211] <TB2> INFO: 411648 events read in total (8788ms).
[13:32:37.252] <TB2> INFO: Expecting 411648 events.
[13:32:46.560] <TB2> INFO: 411648 events read in total (8905ms).
[13:32:46.599] <TB2> INFO: Expecting 411648 events.
[13:32:55.869] <TB2> INFO: 411648 events read in total (8867ms).
[13:32:55.917] <TB2> INFO: Expecting 411648 events.
[13:33:05.196] <TB2> INFO: 411648 events read in total (8876ms).
[13:33:05.238] <TB2> INFO: Expecting 411648 events.
[13:33:14.566] <TB2> INFO: 411648 events read in total (8924ms).
[13:33:14.613] <TB2> INFO: Expecting 411648 events.
[13:33:23.879] <TB2> INFO: 411648 events read in total (8863ms).
[13:33:23.935] <TB2> INFO: Test took 148609ms.
[13:33:24.693] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:33:24.707] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:33:24.707] <TB2> INFO: run 1 of 1
[13:33:24.985] <TB2> INFO: Expecting 5025280 events.
[13:33:51.514] <TB2> INFO: 585480 events read in total (25937ms).
[13:34:17.554] <TB2> INFO: 1169472 events read in total (51977ms).
[13:34:43.857] <TB2> INFO: 1753600 events read in total (78280ms).
[13:35:10.314] <TB2> INFO: 2337656 events read in total (104737ms).
[13:35:36.747] <TB2> INFO: 2919648 events read in total (131171ms).
[13:36:02.936] <TB2> INFO: 3501712 events read in total (157359ms).
[13:36:29.101] <TB2> INFO: 4084544 events read in total (183524ms).
[13:36:55.080] <TB2> INFO: 4667032 events read in total (209503ms).
[13:37:11.407] <TB2> INFO: 5025280 events read in total (225830ms).
[13:37:11.555] <TB2> INFO: Test took 226849ms.
[13:37:37.106] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 1.988773 .. 140.322461
[13:37:37.349] <TB2> INFO: Expecting 208000 events.
[13:37:47.081] <TB2> INFO: 208000 events read in total (9140ms).
[13:37:47.082] <TB2> INFO: Test took 9974ms.
[13:37:47.132] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:37:47.146] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:37:47.146] <TB2> INFO: run 1 of 1
[13:37:47.425] <TB2> INFO: Expecting 4992000 events.
[13:38:14.513] <TB2> INFO: 585432 events read in total (26496ms).
[13:38:40.172] <TB2> INFO: 1171584 events read in total (52155ms).
[13:39:05.851] <TB2> INFO: 1757376 events read in total (77834ms).
[13:39:31.820] <TB2> INFO: 2343152 events read in total (103803ms).
[13:39:57.907] <TB2> INFO: 2928984 events read in total (129890ms).
[13:40:23.865] <TB2> INFO: 3514352 events read in total (155848ms).
[13:40:49.261] <TB2> INFO: 4099200 events read in total (181244ms).
[13:41:14.976] <TB2> INFO: 4683952 events read in total (206959ms).
[13:41:28.471] <TB2> INFO: 4992000 events read in total (220454ms).
[13:41:28.585] <TB2> INFO: Test took 221439ms.
[13:41:53.012] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.739600 .. 45.723106
[13:41:53.249] <TB2> INFO: Expecting 208000 events.
[13:42:02.921] <TB2> INFO: 208000 events read in total (9080ms).
[13:42:02.922] <TB2> INFO: Test took 9909ms.
[13:42:02.974] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 55 (-1/-1) hits flags = 528 (plus default)
[13:42:02.987] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:42:02.987] <TB2> INFO: run 1 of 1
[13:42:03.282] <TB2> INFO: Expecting 1297920 events.
[13:42:31.607] <TB2> INFO: 657624 events read in total (27729ms).
[13:42:59.113] <TB2> INFO: 1297920 events read in total (55235ms).
[13:42:59.155] <TB2> INFO: Test took 56168ms.
[13:43:14.743] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 26.117608 .. 47.348030
[13:43:14.980] <TB2> INFO: Expecting 208000 events.
[13:43:24.644] <TB2> INFO: 208000 events read in total (9072ms).
[13:43:24.645] <TB2> INFO: Test took 9901ms.
[13:43:24.714] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[13:43:24.728] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:43:24.728] <TB2> INFO: run 1 of 1
[13:43:25.009] <TB2> INFO: Expecting 1397760 events.
[13:43:53.665] <TB2> INFO: 655488 events read in total (28064ms).
[13:44:21.052] <TB2> INFO: 1309992 events read in total (55451ms).
[13:44:25.264] <TB2> INFO: 1397760 events read in total (59663ms).
[13:44:25.301] <TB2> INFO: Test took 60574ms.
[13:44:41.225] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 25.232785 .. 44.585840
[13:44:41.481] <TB2> INFO: Expecting 208000 events.
[13:44:51.307] <TB2> INFO: 208000 events read in total (9234ms).
[13:44:51.308] <TB2> INFO: Test took 10082ms.
[13:44:51.356] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 54 (-1/-1) hits flags = 528 (plus default)
[13:44:51.368] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:44:51.369] <TB2> INFO: run 1 of 1
[13:44:51.647] <TB2> INFO: Expecting 1331200 events.
[13:45:20.337] <TB2> INFO: 671504 events read in total (28099ms).
[13:45:47.707] <TB2> INFO: 1331200 events read in total (55469ms).
[13:45:47.738] <TB2> INFO: Test took 56370ms.
[13:46:02.297] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[13:46:02.297] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[13:46:02.310] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:46:02.310] <TB2> INFO: run 1 of 1
[13:46:02.547] <TB2> INFO: Expecting 1364480 events.
[13:46:30.919] <TB2> INFO: 667480 events read in total (27780ms).
[13:46:58.183] <TB2> INFO: 1334432 events read in total (55044ms).
[13:46:59.863] <TB2> INFO: 1364480 events read in total (56725ms).
[13:46:59.890] <TB2> INFO: Test took 57580ms.
[13:47:13.750] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C0.dat
[13:47:13.750] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C1.dat
[13:47:13.750] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C2.dat
[13:47:13.750] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C3.dat
[13:47:13.750] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C4.dat
[13:47:13.750] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C5.dat
[13:47:13.751] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C6.dat
[13:47:13.751] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C7.dat
[13:47:13.751] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C8.dat
[13:47:13.751] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C9.dat
[13:47:13.751] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C10.dat
[13:47:13.751] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C11.dat
[13:47:13.751] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C12.dat
[13:47:13.751] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C13.dat
[13:47:13.751] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C14.dat
[13:47:13.751] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C15.dat
[13:47:13.751] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C0.dat
[13:47:13.756] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C1.dat
[13:47:13.761] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C2.dat
[13:47:13.765] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C3.dat
[13:47:13.770] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C4.dat
[13:47:13.775] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C5.dat
[13:47:13.780] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C6.dat
[13:47:13.784] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C7.dat
[13:47:13.789] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C8.dat
[13:47:13.794] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C9.dat
[13:47:13.798] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C10.dat
[13:47:13.803] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C11.dat
[13:47:13.808] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C12.dat
[13:47:13.814] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C13.dat
[13:47:13.820] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C14.dat
[13:47:13.826] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//trimParameters35_C15.dat
[13:47:13.833] <TB2> INFO: PixTestTrim::trimTest() done
[13:47:13.833] <TB2> INFO: vtrim: 127 126 142 125 111 109 140 135 115 129 146 134 111 123 138 130
[13:47:13.833] <TB2> INFO: vthrcomp: 122 117 106 122 130 113 125 130 112 121 133 123 126 128 107 130
[13:47:13.833] <TB2> INFO: vcal mean: 34.92 34.94 35.04 34.89 34.98 34.97 34.99 34.90 34.98 34.93 35.27 34.94 34.97 34.91 35.00 35.13
[13:47:13.833] <TB2> INFO: vcal RMS: 1.06 1.05 1.04 1.15 1.05 0.97 1.11 1.17 1.01 1.07 1.44 1.08 1.08 1.13 0.96 1.25
[13:47:13.833] <TB2> INFO: bits mean: 9.72 9.70 9.05 10.17 9.41 8.84 9.73 9.78 9.74 9.15 7.58 9.53 9.75 10.12 8.63 9.79
[13:47:13.833] <TB2> INFO: bits RMS: 2.70 2.65 2.52 2.66 2.86 2.99 2.69 2.75 2.48 2.82 2.54 2.61 2.83 2.63 2.45 2.70
[13:47:13.840] <TB2> INFO: ----------------------------------------------------------------------
[13:47:13.840] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:47:13.840] <TB2> INFO: ----------------------------------------------------------------------
[13:47:13.843] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:47:13.857] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:47:13.857] <TB2> INFO: run 1 of 1
[13:47:14.101] <TB2> INFO: Expecting 4160000 events.
[13:47:45.803] <TB2> INFO: 748890 events read in total (31103ms).
[13:48:17.625] <TB2> INFO: 1494055 events read in total (62925ms).
[13:48:49.618] <TB2> INFO: 2236095 events read in total (94918ms).
[13:49:21.799] <TB2> INFO: 2974230 events read in total (127099ms).
[13:49:53.575] <TB2> INFO: 3711525 events read in total (158875ms).
[13:50:12.916] <TB2> INFO: 4160000 events read in total (178216ms).
[13:50:13.019] <TB2> INFO: Test took 179162ms.
[13:50:42.551] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 211 (-1/-1) hits flags = 528 (plus default)
[13:50:42.565] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:50:42.565] <TB2> INFO: run 1 of 1
[13:50:42.835] <TB2> INFO: Expecting 4409600 events.
[13:51:14.073] <TB2> INFO: 710975 events read in total (30647ms).
[13:51:45.133] <TB2> INFO: 1418605 events read in total (61707ms).
[13:52:15.712] <TB2> INFO: 2125015 events read in total (92286ms).
[13:52:46.273] <TB2> INFO: 2826940 events read in total (122847ms).
[13:53:17.123] <TB2> INFO: 3528360 events read in total (153697ms).
[13:53:48.061] <TB2> INFO: 4229965 events read in total (184635ms).
[13:53:56.255] <TB2> INFO: 4409600 events read in total (192829ms).
[13:53:56.384] <TB2> INFO: Test took 193818ms.
[13:54:25.390] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[13:54:25.404] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:54:25.404] <TB2> INFO: run 1 of 1
[13:54:25.647] <TB2> INFO: Expecting 4243200 events.
[13:54:57.734] <TB2> INFO: 719850 events read in total (31496ms).
[13:55:28.613] <TB2> INFO: 1437015 events read in total (62375ms).
[13:55:59.834] <TB2> INFO: 2151930 events read in total (93596ms).
[13:56:30.767] <TB2> INFO: 2862750 events read in total (124529ms).
[13:57:01.657] <TB2> INFO: 3572720 events read in total (155419ms).
[13:57:30.901] <TB2> INFO: 4243200 events read in total (184663ms).
[13:57:31.018] <TB2> INFO: Test took 185614ms.
[13:58:02.626] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[13:58:02.639] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:58:02.639] <TB2> INFO: run 1 of 1
[13:58:02.880] <TB2> INFO: Expecting 4264000 events.
[13:58:34.994] <TB2> INFO: 718750 events read in total (31522ms).
[13:59:06.439] <TB2> INFO: 1434695 events read in total (62967ms).
[13:59:37.829] <TB2> INFO: 2148260 events read in total (94357ms).
[14:00:09.260] <TB2> INFO: 2857490 events read in total (125788ms).
[14:00:40.736] <TB2> INFO: 3566420 events read in total (157264ms).
[14:01:11.180] <TB2> INFO: 4264000 events read in total (187708ms).
[14:01:11.291] <TB2> INFO: Test took 188652ms.
[14:01:39.740] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[14:01:39.753] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:01:39.753] <TB2> INFO: run 1 of 1
[14:01:39.991] <TB2> INFO: Expecting 4243200 events.
[14:02:11.900] <TB2> INFO: 719875 events read in total (31318ms).
[14:02:42.771] <TB2> INFO: 1436910 events read in total (62189ms).
[14:03:14.277] <TB2> INFO: 2151595 events read in total (93695ms).
[14:03:45.675] <TB2> INFO: 2861965 events read in total (125093ms).
[14:04:16.844] <TB2> INFO: 3572030 events read in total (156262ms).
[14:04:45.686] <TB2> INFO: 4243200 events read in total (185104ms).
[14:04:45.826] <TB2> INFO: Test took 186073ms.
[14:05:11.295] <TB2> INFO: PixTestTrim::trimBitTest() done
[14:05:11.297] <TB2> INFO: PixTestTrim::doTest() done, duration: 2517 seconds
[14:05:11.297] <TB2> INFO: Decoding statistics:
[14:05:11.297] <TB2> INFO: General information:
[14:05:11.297] <TB2> INFO: 16bit words read: 0
[14:05:11.297] <TB2> INFO: valid events total: 0
[14:05:11.297] <TB2> INFO: empty events: 0
[14:05:11.297] <TB2> INFO: valid events with pixels: 0
[14:05:11.297] <TB2> INFO: valid pixel hits: 0
[14:05:11.297] <TB2> INFO: Event errors: 0
[14:05:11.297] <TB2> INFO: start marker: 0
[14:05:11.297] <TB2> INFO: stop marker: 0
[14:05:11.297] <TB2> INFO: overflow: 0
[14:05:11.297] <TB2> INFO: invalid 5bit words: 0
[14:05:11.297] <TB2> INFO: invalid XOR eye diagram: 0
[14:05:11.297] <TB2> INFO: frame (failed synchr.): 0
[14:05:11.297] <TB2> INFO: idle data (no TBM trl): 0
[14:05:11.297] <TB2> INFO: no data (only TBM hdr): 0
[14:05:11.297] <TB2> INFO: TBM errors: 0
[14:05:11.297] <TB2> INFO: flawed TBM headers: 0
[14:05:11.297] <TB2> INFO: flawed TBM trailers: 0
[14:05:11.297] <TB2> INFO: event ID mismatches: 0
[14:05:11.297] <TB2> INFO: ROC errors: 0
[14:05:11.297] <TB2> INFO: missing ROC header(s): 0
[14:05:11.297] <TB2> INFO: misplaced readback start: 0
[14:05:11.297] <TB2> INFO: Pixel decoding errors: 0
[14:05:11.297] <TB2> INFO: pixel data incomplete: 0
[14:05:11.297] <TB2> INFO: pixel address: 0
[14:05:11.297] <TB2> INFO: pulse height fill bit: 0
[14:05:11.297] <TB2> INFO: buffer corruption: 0
[14:05:12.025] <TB2> INFO: ######################################################################
[14:05:12.025] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[14:05:12.025] <TB2> INFO: ######################################################################
[14:05:12.262] <TB2> INFO: Expecting 41600 events.
[14:05:15.720] <TB2> INFO: 41600 events read in total (2866ms).
[14:05:15.721] <TB2> INFO: Test took 3695ms.
[14:05:16.170] <TB2> INFO: Expecting 41600 events.
[14:05:19.650] <TB2> INFO: 41600 events read in total (2888ms).
[14:05:19.651] <TB2> INFO: Test took 3726ms.
[14:05:19.943] <TB2> INFO: Expecting 41600 events.
[14:05:23.569] <TB2> INFO: 41600 events read in total (3035ms).
[14:05:23.569] <TB2> INFO: Test took 3893ms.
[14:05:23.859] <TB2> INFO: Expecting 41600 events.
[14:05:27.463] <TB2> INFO: 41600 events read in total (3013ms).
[14:05:27.464] <TB2> INFO: Test took 3870ms.
[14:05:27.758] <TB2> INFO: Expecting 41600 events.
[14:05:31.370] <TB2> INFO: 41600 events read in total (3021ms).
[14:05:31.371] <TB2> INFO: Test took 3878ms.
[14:05:31.661] <TB2> INFO: Expecting 41600 events.
[14:05:35.198] <TB2> INFO: 41600 events read in total (2945ms).
[14:05:35.199] <TB2> INFO: Test took 3803ms.
[14:05:35.497] <TB2> INFO: Expecting 41600 events.
[14:05:39.018] <TB2> INFO: 41600 events read in total (2929ms).
[14:05:39.019] <TB2> INFO: Test took 3796ms.
[14:05:39.308] <TB2> INFO: Expecting 41600 events.
[14:05:42.782] <TB2> INFO: 41600 events read in total (2882ms).
[14:05:42.783] <TB2> INFO: Test took 3739ms.
[14:05:43.073] <TB2> INFO: Expecting 41600 events.
[14:05:46.715] <TB2> INFO: 41600 events read in total (3050ms).
[14:05:46.715] <TB2> INFO: Test took 3906ms.
[14:05:47.005] <TB2> INFO: Expecting 41600 events.
[14:05:50.494] <TB2> INFO: 41600 events read in total (2897ms).
[14:05:50.495] <TB2> INFO: Test took 3755ms.
[14:05:50.784] <TB2> INFO: Expecting 41600 events.
[14:05:54.335] <TB2> INFO: 41600 events read in total (2960ms).
[14:05:54.336] <TB2> INFO: Test took 3817ms.
[14:05:54.626] <TB2> INFO: Expecting 41600 events.
[14:05:58.252] <TB2> INFO: 41600 events read in total (3034ms).
[14:05:58.253] <TB2> INFO: Test took 3892ms.
[14:05:58.546] <TB2> INFO: Expecting 41600 events.
[14:06:02.073] <TB2> INFO: 41600 events read in total (2935ms).
[14:06:02.074] <TB2> INFO: Test took 3793ms.
[14:06:02.364] <TB2> INFO: Expecting 41600 events.
[14:06:05.916] <TB2> INFO: 41600 events read in total (2961ms).
[14:06:05.917] <TB2> INFO: Test took 3818ms.
[14:06:06.209] <TB2> INFO: Expecting 41600 events.
[14:06:09.785] <TB2> INFO: 41600 events read in total (2984ms).
[14:06:09.786] <TB2> INFO: Test took 3841ms.
[14:06:10.087] <TB2> INFO: Expecting 41600 events.
[14:06:13.669] <TB2> INFO: 41600 events read in total (2990ms).
[14:06:13.670] <TB2> INFO: Test took 3859ms.
[14:06:13.962] <TB2> INFO: Expecting 41600 events.
[14:06:17.454] <TB2> INFO: 41600 events read in total (2900ms).
[14:06:17.455] <TB2> INFO: Test took 3761ms.
[14:06:17.761] <TB2> INFO: Expecting 41600 events.
[14:06:21.273] <TB2> INFO: 41600 events read in total (2920ms).
[14:06:21.273] <TB2> INFO: Test took 3791ms.
[14:06:21.564] <TB2> INFO: Expecting 41600 events.
[14:06:25.043] <TB2> INFO: 41600 events read in total (2887ms).
[14:06:25.044] <TB2> INFO: Test took 3745ms.
[14:06:25.333] <TB2> INFO: Expecting 41600 events.
[14:06:28.878] <TB2> INFO: 41600 events read in total (2953ms).
[14:06:28.878] <TB2> INFO: Test took 3810ms.
[14:06:29.168] <TB2> INFO: Expecting 41600 events.
[14:06:32.781] <TB2> INFO: 41600 events read in total (3022ms).
[14:06:32.782] <TB2> INFO: Test took 3879ms.
[14:06:33.072] <TB2> INFO: Expecting 41600 events.
[14:06:36.634] <TB2> INFO: 41600 events read in total (2971ms).
[14:06:36.635] <TB2> INFO: Test took 3828ms.
[14:06:36.927] <TB2> INFO: Expecting 41600 events.
[14:06:40.562] <TB2> INFO: 41600 events read in total (3044ms).
[14:06:40.562] <TB2> INFO: Test took 3900ms.
[14:06:40.853] <TB2> INFO: Expecting 41600 events.
[14:06:44.352] <TB2> INFO: 41600 events read in total (2908ms).
[14:06:44.352] <TB2> INFO: Test took 3765ms.
[14:06:44.642] <TB2> INFO: Expecting 41600 events.
[14:06:48.124] <TB2> INFO: 41600 events read in total (2890ms).
[14:06:48.124] <TB2> INFO: Test took 3747ms.
[14:06:48.414] <TB2> INFO: Expecting 41600 events.
[14:06:51.977] <TB2> INFO: 41600 events read in total (2972ms).
[14:06:51.978] <TB2> INFO: Test took 3829ms.
[14:06:52.267] <TB2> INFO: Expecting 41600 events.
[14:06:55.760] <TB2> INFO: 41600 events read in total (2902ms).
[14:06:55.761] <TB2> INFO: Test took 3759ms.
[14:06:56.050] <TB2> INFO: Expecting 41600 events.
[14:06:59.560] <TB2> INFO: 41600 events read in total (2918ms).
[14:06:59.561] <TB2> INFO: Test took 3776ms.
[14:06:59.853] <TB2> INFO: Expecting 41600 events.
[14:07:03.382] <TB2> INFO: 41600 events read in total (2937ms).
[14:07:03.382] <TB2> INFO: Test took 3794ms.
[14:07:03.672] <TB2> INFO: Expecting 2560 events.
[14:07:04.563] <TB2> INFO: 2560 events read in total (299ms).
[14:07:04.564] <TB2> INFO: Test took 1169ms.
[14:07:04.871] <TB2> INFO: Expecting 2560 events.
[14:07:05.758] <TB2> INFO: 2560 events read in total (295ms).
[14:07:05.759] <TB2> INFO: Test took 1194ms.
[14:07:06.067] <TB2> INFO: Expecting 2560 events.
[14:07:06.960] <TB2> INFO: 2560 events read in total (302ms).
[14:07:06.961] <TB2> INFO: Test took 1202ms.
[14:07:07.270] <TB2> INFO: Expecting 2560 events.
[14:07:08.155] <TB2> INFO: 2560 events read in total (294ms).
[14:07:08.155] <TB2> INFO: Test took 1194ms.
[14:07:08.462] <TB2> INFO: Expecting 2560 events.
[14:07:09.354] <TB2> INFO: 2560 events read in total (300ms).
[14:07:09.355] <TB2> INFO: Test took 1199ms.
[14:07:09.662] <TB2> INFO: Expecting 2560 events.
[14:07:10.544] <TB2> INFO: 2560 events read in total (290ms).
[14:07:10.544] <TB2> INFO: Test took 1189ms.
[14:07:10.852] <TB2> INFO: Expecting 2560 events.
[14:07:11.731] <TB2> INFO: 2560 events read in total (288ms).
[14:07:11.731] <TB2> INFO: Test took 1186ms.
[14:07:12.040] <TB2> INFO: Expecting 2560 events.
[14:07:12.929] <TB2> INFO: 2560 events read in total (297ms).
[14:07:12.929] <TB2> INFO: Test took 1198ms.
[14:07:13.237] <TB2> INFO: Expecting 2560 events.
[14:07:14.127] <TB2> INFO: 2560 events read in total (298ms).
[14:07:14.127] <TB2> INFO: Test took 1197ms.
[14:07:14.435] <TB2> INFO: Expecting 2560 events.
[14:07:15.314] <TB2> INFO: 2560 events read in total (288ms).
[14:07:15.314] <TB2> INFO: Test took 1186ms.
[14:07:15.622] <TB2> INFO: Expecting 2560 events.
[14:07:16.502] <TB2> INFO: 2560 events read in total (288ms).
[14:07:16.502] <TB2> INFO: Test took 1187ms.
[14:07:16.810] <TB2> INFO: Expecting 2560 events.
[14:07:17.691] <TB2> INFO: 2560 events read in total (289ms).
[14:07:17.692] <TB2> INFO: Test took 1190ms.
[14:07:17.999] <TB2> INFO: Expecting 2560 events.
[14:07:18.883] <TB2> INFO: 2560 events read in total (292ms).
[14:07:18.883] <TB2> INFO: Test took 1191ms.
[14:07:19.192] <TB2> INFO: Expecting 2560 events.
[14:07:20.076] <TB2> INFO: 2560 events read in total (293ms).
[14:07:20.077] <TB2> INFO: Test took 1193ms.
[14:07:20.385] <TB2> INFO: Expecting 2560 events.
[14:07:21.269] <TB2> INFO: 2560 events read in total (293ms).
[14:07:21.269] <TB2> INFO: Test took 1192ms.
[14:07:21.577] <TB2> INFO: Expecting 2560 events.
[14:07:22.463] <TB2> INFO: 2560 events read in total (294ms).
[14:07:22.463] <TB2> INFO: Test took 1193ms.
[14:07:22.466] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:07:22.772] <TB2> INFO: Expecting 655360 events.
[14:07:37.519] <TB2> INFO: 655360 events read in total (14155ms).
[14:07:37.531] <TB2> INFO: Expecting 655360 events.
[14:07:52.332] <TB2> INFO: 655360 events read in total (14398ms).
[14:07:52.352] <TB2> INFO: Expecting 655360 events.
[14:08:06.935] <TB2> INFO: 655360 events read in total (14180ms).
[14:08:06.955] <TB2> INFO: Expecting 655360 events.
[14:08:21.722] <TB2> INFO: 655360 events read in total (14363ms).
[14:08:21.748] <TB2> INFO: Expecting 655360 events.
[14:08:36.080] <TB2> INFO: 655360 events read in total (13929ms).
[14:08:36.122] <TB2> INFO: Expecting 655360 events.
[14:08:50.870] <TB2> INFO: 655360 events read in total (14345ms).
[14:08:50.904] <TB2> INFO: Expecting 655360 events.
[14:09:05.255] <TB2> INFO: 655360 events read in total (13948ms).
[14:09:05.302] <TB2> INFO: Expecting 655360 events.
[14:09:19.838] <TB2> INFO: 655360 events read in total (14133ms).
[14:09:19.882] <TB2> INFO: Expecting 655360 events.
[14:09:34.368] <TB2> INFO: 655360 events read in total (14083ms).
[14:09:34.416] <TB2> INFO: Expecting 655360 events.
[14:09:48.866] <TB2> INFO: 655360 events read in total (14047ms).
[14:09:48.917] <TB2> INFO: Expecting 655360 events.
[14:10:03.361] <TB2> INFO: 655360 events read in total (14041ms).
[14:10:03.415] <TB2> INFO: Expecting 655360 events.
[14:10:17.697] <TB2> INFO: 655360 events read in total (13879ms).
[14:10:17.771] <TB2> INFO: Expecting 655360 events.
[14:10:32.373] <TB2> INFO: 655360 events read in total (14199ms).
[14:10:32.439] <TB2> INFO: Expecting 655360 events.
[14:10:47.042] <TB2> INFO: 655360 events read in total (14200ms).
[14:10:47.150] <TB2> INFO: Expecting 655360 events.
[14:11:01.794] <TB2> INFO: 655360 events read in total (14241ms).
[14:11:01.889] <TB2> INFO: Expecting 655360 events.
[14:11:16.468] <TB2> INFO: 655360 events read in total (14176ms).
[14:11:16.572] <TB2> INFO: Test took 234106ms.
[14:11:16.674] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:11:16.928] <TB2> INFO: Expecting 655360 events.
[14:11:31.629] <TB2> INFO: 655360 events read in total (14109ms).
[14:11:31.641] <TB2> INFO: Expecting 655360 events.
[14:11:46.233] <TB2> INFO: 655360 events read in total (14189ms).
[14:11:46.253] <TB2> INFO: Expecting 655360 events.
[14:12:00.675] <TB2> INFO: 655360 events read in total (14019ms).
[14:12:00.696] <TB2> INFO: Expecting 655360 events.
[14:12:15.179] <TB2> INFO: 655360 events read in total (14080ms).
[14:12:15.203] <TB2> INFO: Expecting 655360 events.
[14:12:29.774] <TB2> INFO: 655360 events read in total (14168ms).
[14:12:29.805] <TB2> INFO: Expecting 655360 events.
[14:12:44.277] <TB2> INFO: 655360 events read in total (14069ms).
[14:12:44.311] <TB2> INFO: Expecting 655360 events.
[14:12:58.560] <TB2> INFO: 655360 events read in total (13845ms).
[14:12:58.603] <TB2> INFO: Expecting 655360 events.
[14:13:13.021] <TB2> INFO: 655360 events read in total (14014ms).
[14:13:13.063] <TB2> INFO: Expecting 655360 events.
[14:13:27.529] <TB2> INFO: 655360 events read in total (14063ms).
[14:13:27.578] <TB2> INFO: Expecting 655360 events.
[14:13:41.983] <TB2> INFO: 655360 events read in total (14002ms).
[14:13:42.039] <TB2> INFO: Expecting 655360 events.
[14:13:56.329] <TB2> INFO: 655360 events read in total (13887ms).
[14:13:56.386] <TB2> INFO: Expecting 655360 events.
[14:14:10.832] <TB2> INFO: 655360 events read in total (14043ms).
[14:14:10.908] <TB2> INFO: Expecting 655360 events.
[14:14:25.367] <TB2> INFO: 655360 events read in total (14056ms).
[14:14:25.433] <TB2> INFO: Expecting 655360 events.
[14:14:39.926] <TB2> INFO: 655360 events read in total (14090ms).
[14:14:40.044] <TB2> INFO: Expecting 655360 events.
[14:14:54.300] <TB2> INFO: 655360 events read in total (13852ms).
[14:14:54.414] <TB2> INFO: Expecting 655360 events.
[14:15:08.926] <TB2> INFO: 655360 events read in total (14109ms).
[14:15:09.025] <TB2> INFO: Test took 232351ms.
[14:15:09.190] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.196] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.202] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:15:09.208] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:15:09.214] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:15:09.220] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:15:09.225] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.231] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.237] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.243] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.249] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.254] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:15:09.260] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:15:09.266] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:15:09.272] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:15:09.277] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:15:09.283] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[14:15:09.288] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[14:15:09.294] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[14:15:09.300] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[14:15:09.305] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[14:15:09.311] <TB2> INFO: safety margin for low PH: adding 11, margin is now 31
[14:15:09.316] <TB2> INFO: safety margin for low PH: adding 12, margin is now 32
[14:15:09.322] <TB2> INFO: safety margin for low PH: adding 13, margin is now 33
[14:15:09.327] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.333] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.338] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:15:09.344] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.349] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:15:09.355] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:15:09.360] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:15:09.366] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:15:09.372] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:15:09.377] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[14:15:09.383] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.388] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.394] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.399] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.405] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.410] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:15:09.416] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:15:09.422] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:15:09.461] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C0.dat
[14:15:09.461] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C1.dat
[14:15:09.461] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C2.dat
[14:15:09.462] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C3.dat
[14:15:09.462] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C4.dat
[14:15:09.462] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C5.dat
[14:15:09.462] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C6.dat
[14:15:09.462] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C7.dat
[14:15:09.463] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C8.dat
[14:15:09.463] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C9.dat
[14:15:09.463] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C10.dat
[14:15:09.463] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C11.dat
[14:15:09.463] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C12.dat
[14:15:09.463] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C13.dat
[14:15:09.464] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C14.dat
[14:15:09.464] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//dacParameters35_C15.dat
[14:15:09.706] <TB2> INFO: Expecting 41600 events.
[14:15:12.883] <TB2> INFO: 41600 events read in total (2586ms).
[14:15:12.884] <TB2> INFO: Test took 3417ms.
[14:15:13.338] <TB2> INFO: Expecting 41600 events.
[14:15:16.415] <TB2> INFO: 41600 events read in total (2485ms).
[14:15:16.416] <TB2> INFO: Test took 3320ms.
[14:15:16.874] <TB2> INFO: Expecting 41600 events.
[14:15:19.998] <TB2> INFO: 41600 events read in total (2533ms).
[14:15:19.998] <TB2> INFO: Test took 3370ms.
[14:15:20.213] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:20.302] <TB2> INFO: Expecting 2560 events.
[14:15:21.191] <TB2> INFO: 2560 events read in total (297ms).
[14:15:21.191] <TB2> INFO: Test took 978ms.
[14:15:21.194] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:21.500] <TB2> INFO: Expecting 2560 events.
[14:15:22.384] <TB2> INFO: 2560 events read in total (292ms).
[14:15:22.385] <TB2> INFO: Test took 1191ms.
[14:15:22.387] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:22.693] <TB2> INFO: Expecting 2560 events.
[14:15:23.585] <TB2> INFO: 2560 events read in total (300ms).
[14:15:23.585] <TB2> INFO: Test took 1198ms.
[14:15:23.588] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:23.892] <TB2> INFO: Expecting 2560 events.
[14:15:24.785] <TB2> INFO: 2560 events read in total (301ms).
[14:15:24.786] <TB2> INFO: Test took 1198ms.
[14:15:24.789] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:25.094] <TB2> INFO: Expecting 2560 events.
[14:15:25.985] <TB2> INFO: 2560 events read in total (299ms).
[14:15:25.986] <TB2> INFO: Test took 1197ms.
[14:15:25.989] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:26.295] <TB2> INFO: Expecting 2560 events.
[14:15:27.188] <TB2> INFO: 2560 events read in total (301ms).
[14:15:27.189] <TB2> INFO: Test took 1200ms.
[14:15:27.191] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:27.497] <TB2> INFO: Expecting 2560 events.
[14:15:28.384] <TB2> INFO: 2560 events read in total (295ms).
[14:15:28.385] <TB2> INFO: Test took 1194ms.
[14:15:28.388] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:28.692] <TB2> INFO: Expecting 2560 events.
[14:15:29.585] <TB2> INFO: 2560 events read in total (301ms).
[14:15:29.585] <TB2> INFO: Test took 1197ms.
[14:15:29.588] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:29.893] <TB2> INFO: Expecting 2560 events.
[14:15:30.774] <TB2> INFO: 2560 events read in total (289ms).
[14:15:30.775] <TB2> INFO: Test took 1187ms.
[14:15:30.777] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:31.084] <TB2> INFO: Expecting 2560 events.
[14:15:31.972] <TB2> INFO: 2560 events read in total (295ms).
[14:15:31.972] <TB2> INFO: Test took 1195ms.
[14:15:31.976] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:32.281] <TB2> INFO: Expecting 2560 events.
[14:15:33.168] <TB2> INFO: 2560 events read in total (296ms).
[14:15:33.169] <TB2> INFO: Test took 1193ms.
[14:15:33.174] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:33.477] <TB2> INFO: Expecting 2560 events.
[14:15:34.359] <TB2> INFO: 2560 events read in total (290ms).
[14:15:34.359] <TB2> INFO: Test took 1185ms.
[14:15:34.362] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:34.668] <TB2> INFO: Expecting 2560 events.
[14:15:35.556] <TB2> INFO: 2560 events read in total (297ms).
[14:15:35.556] <TB2> INFO: Test took 1194ms.
[14:15:35.560] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:35.865] <TB2> INFO: Expecting 2560 events.
[14:15:36.743] <TB2> INFO: 2560 events read in total (286ms).
[14:15:36.744] <TB2> INFO: Test took 1185ms.
[14:15:36.745] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:37.052] <TB2> INFO: Expecting 2560 events.
[14:15:37.944] <TB2> INFO: 2560 events read in total (300ms).
[14:15:37.944] <TB2> INFO: Test took 1199ms.
[14:15:37.947] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:38.254] <TB2> INFO: Expecting 2560 events.
[14:15:39.139] <TB2> INFO: 2560 events read in total (294ms).
[14:15:39.139] <TB2> INFO: Test took 1192ms.
[14:15:39.142] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:39.447] <TB2> INFO: Expecting 2560 events.
[14:15:40.327] <TB2> INFO: 2560 events read in total (288ms).
[14:15:40.327] <TB2> INFO: Test took 1185ms.
[14:15:40.329] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:40.635] <TB2> INFO: Expecting 2560 events.
[14:15:41.527] <TB2> INFO: 2560 events read in total (300ms).
[14:15:41.527] <TB2> INFO: Test took 1198ms.
[14:15:41.532] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:41.836] <TB2> INFO: Expecting 2560 events.
[14:15:42.725] <TB2> INFO: 2560 events read in total (298ms).
[14:15:42.725] <TB2> INFO: Test took 1193ms.
[14:15:42.728] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:43.033] <TB2> INFO: Expecting 2560 events.
[14:15:43.917] <TB2> INFO: 2560 events read in total (292ms).
[14:15:43.918] <TB2> INFO: Test took 1190ms.
[14:15:43.922] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:44.226] <TB2> INFO: Expecting 2560 events.
[14:15:45.115] <TB2> INFO: 2560 events read in total (297ms).
[14:15:45.116] <TB2> INFO: Test took 1194ms.
[14:15:45.119] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:45.424] <TB2> INFO: Expecting 2560 events.
[14:15:46.314] <TB2> INFO: 2560 events read in total (298ms).
[14:15:46.314] <TB2> INFO: Test took 1195ms.
[14:15:46.317] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:46.623] <TB2> INFO: Expecting 2560 events.
[14:15:47.511] <TB2> INFO: 2560 events read in total (296ms).
[14:15:47.512] <TB2> INFO: Test took 1195ms.
[14:15:47.515] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:47.820] <TB2> INFO: Expecting 2560 events.
[14:15:48.704] <TB2> INFO: 2560 events read in total (293ms).
[14:15:48.705] <TB2> INFO: Test took 1190ms.
[14:15:48.708] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:49.013] <TB2> INFO: Expecting 2560 events.
[14:15:49.899] <TB2> INFO: 2560 events read in total (294ms).
[14:15:49.899] <TB2> INFO: Test took 1191ms.
[14:15:49.903] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:50.207] <TB2> INFO: Expecting 2560 events.
[14:15:51.101] <TB2> INFO: 2560 events read in total (302ms).
[14:15:51.102] <TB2> INFO: Test took 1200ms.
[14:15:51.104] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:51.409] <TB2> INFO: Expecting 2560 events.
[14:15:52.296] <TB2> INFO: 2560 events read in total (294ms).
[14:15:52.297] <TB2> INFO: Test took 1193ms.
[14:15:52.299] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:52.605] <TB2> INFO: Expecting 2560 events.
[14:15:53.492] <TB2> INFO: 2560 events read in total (296ms).
[14:15:53.492] <TB2> INFO: Test took 1193ms.
[14:15:53.494] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:53.801] <TB2> INFO: Expecting 2560 events.
[14:15:54.691] <TB2> INFO: 2560 events read in total (298ms).
[14:15:54.691] <TB2> INFO: Test took 1197ms.
[14:15:54.694] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:54.998] <TB2> INFO: Expecting 2560 events.
[14:15:55.890] <TB2> INFO: 2560 events read in total (300ms).
[14:15:55.891] <TB2> INFO: Test took 1198ms.
[14:15:55.893] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:56.199] <TB2> INFO: Expecting 2560 events.
[14:15:57.084] <TB2> INFO: 2560 events read in total (294ms).
[14:15:57.085] <TB2> INFO: Test took 1192ms.
[14:15:57.090] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:57.393] <TB2> INFO: Expecting 2560 events.
[14:15:58.289] <TB2> INFO: 2560 events read in total (304ms).
[14:15:58.289] <TB2> INFO: Test took 1199ms.
[14:15:58.763] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 646 seconds
[14:15:58.763] <TB2> INFO: PH scale (per ROC): 52 36 48 50 48 63 36 61 53 36 45 63 62 59 53 52
[14:15:58.763] <TB2> INFO: PH offset (per ROC): 132 105 111 108 95 127 112 107 95 96 92 119 98 131 125 131
[14:15:58.771] <TB2> INFO: Decoding statistics:
[14:15:58.771] <TB2> INFO: General information:
[14:15:58.771] <TB2> INFO: 16bit words read: 127874
[14:15:58.771] <TB2> INFO: valid events total: 20480
[14:15:58.771] <TB2> INFO: empty events: 17983
[14:15:58.771] <TB2> INFO: valid events with pixels: 2497
[14:15:58.771] <TB2> INFO: valid pixel hits: 2497
[14:15:58.771] <TB2> INFO: Event errors: 0
[14:15:58.771] <TB2> INFO: start marker: 0
[14:15:58.771] <TB2> INFO: stop marker: 0
[14:15:58.771] <TB2> INFO: overflow: 0
[14:15:58.771] <TB2> INFO: invalid 5bit words: 0
[14:15:58.771] <TB2> INFO: invalid XOR eye diagram: 0
[14:15:58.771] <TB2> INFO: frame (failed synchr.): 0
[14:15:58.771] <TB2> INFO: idle data (no TBM trl): 0
[14:15:58.771] <TB2> INFO: no data (only TBM hdr): 0
[14:15:58.771] <TB2> INFO: TBM errors: 0
[14:15:58.771] <TB2> INFO: flawed TBM headers: 0
[14:15:58.771] <TB2> INFO: flawed TBM trailers: 0
[14:15:58.771] <TB2> INFO: event ID mismatches: 0
[14:15:58.771] <TB2> INFO: ROC errors: 0
[14:15:58.771] <TB2> INFO: missing ROC header(s): 0
[14:15:58.771] <TB2> INFO: misplaced readback start: 0
[14:15:58.771] <TB2> INFO: Pixel decoding errors: 0
[14:15:58.771] <TB2> INFO: pixel data incomplete: 0
[14:15:58.771] <TB2> INFO: pixel address: 0
[14:15:58.771] <TB2> INFO: pulse height fill bit: 0
[14:15:58.771] <TB2> INFO: buffer corruption: 0
[14:15:58.932] <TB2> INFO: ######################################################################
[14:15:58.932] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[14:15:58.932] <TB2> INFO: ######################################################################
[14:15:58.947] <TB2> INFO: scanning low vcal = 10
[14:15:59.228] <TB2> INFO: Expecting 41600 events.
[14:16:02.819] <TB2> INFO: 41600 events read in total (2998ms).
[14:16:02.820] <TB2> INFO: Test took 3873ms.
[14:16:02.822] <TB2> INFO: scanning low vcal = 20
[14:16:03.112] <TB2> INFO: Expecting 41600 events.
[14:16:06.753] <TB2> INFO: 41600 events read in total (3049ms).
[14:16:06.753] <TB2> INFO: Test took 3931ms.
[14:16:06.756] <TB2> INFO: scanning low vcal = 30
[14:16:07.047] <TB2> INFO: Expecting 41600 events.
[14:16:10.735] <TB2> INFO: 41600 events read in total (3096ms).
[14:16:10.736] <TB2> INFO: Test took 3980ms.
[14:16:10.740] <TB2> INFO: scanning low vcal = 40
[14:16:11.016] <TB2> INFO: Expecting 41600 events.
[14:16:15.009] <TB2> INFO: 41600 events read in total (3401ms).
[14:16:15.011] <TB2> INFO: Test took 4271ms.
[14:16:15.014] <TB2> INFO: scanning low vcal = 50
[14:16:15.292] <TB2> INFO: Expecting 41600 events.
[14:16:19.281] <TB2> INFO: 41600 events read in total (3397ms).
[14:16:19.281] <TB2> INFO: Test took 4267ms.
[14:16:19.284] <TB2> INFO: scanning low vcal = 60
[14:16:19.561] <TB2> INFO: Expecting 41600 events.
[14:16:23.561] <TB2> INFO: 41600 events read in total (3408ms).
[14:16:23.562] <TB2> INFO: Test took 4277ms.
[14:16:23.565] <TB2> INFO: scanning low vcal = 70
[14:16:23.844] <TB2> INFO: Expecting 41600 events.
[14:16:27.861] <TB2> INFO: 41600 events read in total (3425ms).
[14:16:27.861] <TB2> INFO: Test took 4295ms.
[14:16:27.864] <TB2> INFO: scanning low vcal = 80
[14:16:28.142] <TB2> INFO: Expecting 41600 events.
[14:16:32.139] <TB2> INFO: 41600 events read in total (3405ms).
[14:16:32.140] <TB2> INFO: Test took 4276ms.
[14:16:32.143] <TB2> INFO: scanning low vcal = 90
[14:16:32.420] <TB2> INFO: Expecting 41600 events.
[14:16:36.406] <TB2> INFO: 41600 events read in total (3395ms).
[14:16:36.407] <TB2> INFO: Test took 4264ms.
[14:16:36.412] <TB2> INFO: scanning low vcal = 100
[14:16:36.695] <TB2> INFO: Expecting 41600 events.
[14:16:40.759] <TB2> INFO: 41600 events read in total (3473ms).
[14:16:40.760] <TB2> INFO: Test took 4348ms.
[14:16:40.762] <TB2> INFO: scanning low vcal = 110
[14:16:41.042] <TB2> INFO: Expecting 41600 events.
[14:16:45.075] <TB2> INFO: 41600 events read in total (3441ms).
[14:16:45.076] <TB2> INFO: Test took 4313ms.
[14:16:45.079] <TB2> INFO: scanning low vcal = 120
[14:16:45.355] <TB2> INFO: Expecting 41600 events.
[14:16:49.340] <TB2> INFO: 41600 events read in total (3393ms).
[14:16:49.341] <TB2> INFO: Test took 4262ms.
[14:16:49.344] <TB2> INFO: scanning low vcal = 130
[14:16:49.621] <TB2> INFO: Expecting 41600 events.
[14:16:53.606] <TB2> INFO: 41600 events read in total (3393ms).
[14:16:53.607] <TB2> INFO: Test took 4263ms.
[14:16:53.610] <TB2> INFO: scanning low vcal = 140
[14:16:53.887] <TB2> INFO: Expecting 41600 events.
[14:16:57.894] <TB2> INFO: 41600 events read in total (3414ms).
[14:16:57.895] <TB2> INFO: Test took 4285ms.
[14:16:57.898] <TB2> INFO: scanning low vcal = 150
[14:16:58.175] <TB2> INFO: Expecting 41600 events.
[14:17:02.141] <TB2> INFO: 41600 events read in total (3374ms).
[14:17:02.141] <TB2> INFO: Test took 4243ms.
[14:17:02.144] <TB2> INFO: scanning low vcal = 160
[14:17:02.422] <TB2> INFO: Expecting 41600 events.
[14:17:06.387] <TB2> INFO: 41600 events read in total (3374ms).
[14:17:06.388] <TB2> INFO: Test took 4244ms.
[14:17:06.391] <TB2> INFO: scanning low vcal = 170
[14:17:06.669] <TB2> INFO: Expecting 41600 events.
[14:17:10.675] <TB2> INFO: 41600 events read in total (3414ms).
[14:17:10.676] <TB2> INFO: Test took 4285ms.
[14:17:10.681] <TB2> INFO: scanning low vcal = 180
[14:17:10.957] <TB2> INFO: Expecting 41600 events.
[14:17:14.962] <TB2> INFO: 41600 events read in total (3414ms).
[14:17:14.962] <TB2> INFO: Test took 4281ms.
[14:17:14.966] <TB2> INFO: scanning low vcal = 190
[14:17:15.243] <TB2> INFO: Expecting 41600 events.
[14:17:19.203] <TB2> INFO: 41600 events read in total (3368ms).
[14:17:19.204] <TB2> INFO: Test took 4238ms.
[14:17:19.207] <TB2> INFO: scanning low vcal = 200
[14:17:19.485] <TB2> INFO: Expecting 41600 events.
[14:17:23.457] <TB2> INFO: 41600 events read in total (3381ms).
[14:17:23.458] <TB2> INFO: Test took 4251ms.
[14:17:23.461] <TB2> INFO: scanning low vcal = 210
[14:17:23.740] <TB2> INFO: Expecting 41600 events.
[14:17:27.747] <TB2> INFO: 41600 events read in total (3415ms).
[14:17:27.747] <TB2> INFO: Test took 4286ms.
[14:17:27.750] <TB2> INFO: scanning low vcal = 220
[14:17:28.028] <TB2> INFO: Expecting 41600 events.
[14:17:31.999] <TB2> INFO: 41600 events read in total (3379ms).
[14:17:31.000] <TB2> INFO: Test took 4249ms.
[14:17:32.003] <TB2> INFO: scanning low vcal = 230
[14:17:32.280] <TB2> INFO: Expecting 41600 events.
[14:17:36.240] <TB2> INFO: 41600 events read in total (3368ms).
[14:17:36.241] <TB2> INFO: Test took 4238ms.
[14:17:36.244] <TB2> INFO: scanning low vcal = 240
[14:17:36.521] <TB2> INFO: Expecting 41600 events.
[14:17:40.522] <TB2> INFO: 41600 events read in total (3409ms).
[14:17:40.523] <TB2> INFO: Test took 4279ms.
[14:17:40.526] <TB2> INFO: scanning low vcal = 250
[14:17:40.803] <TB2> INFO: Expecting 41600 events.
[14:17:44.772] <TB2> INFO: 41600 events read in total (3377ms).
[14:17:44.773] <TB2> INFO: Test took 4247ms.
[14:17:44.779] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[14:17:45.053] <TB2> INFO: Expecting 41600 events.
[14:17:49.051] <TB2> INFO: 41600 events read in total (3407ms).
[14:17:49.052] <TB2> INFO: Test took 4273ms.
[14:17:49.055] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[14:17:49.331] <TB2> INFO: Expecting 41600 events.
[14:17:53.301] <TB2> INFO: 41600 events read in total (3378ms).
[14:17:53.302] <TB2> INFO: Test took 4247ms.
[14:17:53.305] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[14:17:53.582] <TB2> INFO: Expecting 41600 events.
[14:17:57.527] <TB2> INFO: 41600 events read in total (3354ms).
[14:17:57.528] <TB2> INFO: Test took 4224ms.
[14:17:57.532] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[14:17:57.808] <TB2> INFO: Expecting 41600 events.
[14:18:01.752] <TB2> INFO: 41600 events read in total (3351ms).
[14:18:01.752] <TB2> INFO: Test took 4220ms.
[14:18:01.757] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[14:18:02.032] <TB2> INFO: Expecting 41600 events.
[14:18:05.986] <TB2> INFO: 41600 events read in total (3364ms).
[14:18:05.987] <TB2> INFO: Test took 4230ms.
[14:18:06.680] <TB2> INFO: PixTestGainPedestal::measure() done
[14:18:41.547] <TB2> INFO: PixTestGainPedestal::fit() done
[14:18:41.547] <TB2> INFO: non-linearity mean: 0.978 0.930 0.941 0.956 0.893 0.984 0.956 0.984 0.973 1.001 0.940 0.981 0.984 0.984 0.982 0.982
[14:18:41.547] <TB2> INFO: non-linearity RMS: 0.005 0.155 0.083 0.030 0.124 0.003 0.151 0.005 0.008 0.161 0.148 0.004 0.005 0.004 0.004 0.003
[14:18:41.547] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[14:18:41.560] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[14:18:41.574] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[14:18:41.587] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[14:18:41.600] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[14:18:41.613] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[14:18:41.625] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[14:18:41.638] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[14:18:41.652] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[14:18:41.665] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[14:18:41.678] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[14:18:41.691] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[14:18:41.704] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[14:18:41.717] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[14:18:41.730] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[14:18:41.744] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[14:18:41.757] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 162 seconds
[14:18:41.757] <TB2> INFO: Decoding statistics:
[14:18:41.757] <TB2> INFO: General information:
[14:18:41.757] <TB2> INFO: 16bit words read: 3327880
[14:18:41.757] <TB2> INFO: valid events total: 332800
[14:18:41.757] <TB2> INFO: empty events: 0
[14:18:41.757] <TB2> INFO: valid events with pixels: 332800
[14:18:41.757] <TB2> INFO: valid pixel hits: 665540
[14:18:41.757] <TB2> INFO: Event errors: 0
[14:18:41.757] <TB2> INFO: start marker: 0
[14:18:41.757] <TB2> INFO: stop marker: 0
[14:18:41.757] <TB2> INFO: overflow: 0
[14:18:41.757] <TB2> INFO: invalid 5bit words: 0
[14:18:41.757] <TB2> INFO: invalid XOR eye diagram: 0
[14:18:41.757] <TB2> INFO: frame (failed synchr.): 0
[14:18:41.757] <TB2> INFO: idle data (no TBM trl): 0
[14:18:41.757] <TB2> INFO: no data (only TBM hdr): 0
[14:18:41.757] <TB2> INFO: TBM errors: 0
[14:18:41.757] <TB2> INFO: flawed TBM headers: 0
[14:18:41.757] <TB2> INFO: flawed TBM trailers: 0
[14:18:41.757] <TB2> INFO: event ID mismatches: 0
[14:18:41.757] <TB2> INFO: ROC errors: 0
[14:18:41.757] <TB2> INFO: missing ROC header(s): 0
[14:18:41.757] <TB2> INFO: misplaced readback start: 0
[14:18:41.757] <TB2> INFO: Pixel decoding errors: 0
[14:18:41.757] <TB2> INFO: pixel data incomplete: 0
[14:18:41.757] <TB2> INFO: pixel address: 0
[14:18:41.757] <TB2> INFO: pulse height fill bit: 0
[14:18:41.757] <TB2> INFO: buffer corruption: 0
[14:18:41.773] <TB2> INFO: Decoding statistics:
[14:18:41.773] <TB2> INFO: General information:
[14:18:41.773] <TB2> INFO: 16bit words read: 3457290
[14:18:41.773] <TB2> INFO: valid events total: 353536
[14:18:41.773] <TB2> INFO: empty events: 18239
[14:18:41.773] <TB2> INFO: valid events with pixels: 335297
[14:18:41.773] <TB2> INFO: valid pixel hits: 668037
[14:18:41.773] <TB2> INFO: Event errors: 0
[14:18:41.773] <TB2> INFO: start marker: 0
[14:18:41.773] <TB2> INFO: stop marker: 0
[14:18:41.773] <TB2> INFO: overflow: 0
[14:18:41.773] <TB2> INFO: invalid 5bit words: 0
[14:18:41.773] <TB2> INFO: invalid XOR eye diagram: 0
[14:18:41.773] <TB2> INFO: frame (failed synchr.): 0
[14:18:41.773] <TB2> INFO: idle data (no TBM trl): 0
[14:18:41.773] <TB2> INFO: no data (only TBM hdr): 0
[14:18:41.773] <TB2> INFO: TBM errors: 0
[14:18:41.773] <TB2> INFO: flawed TBM headers: 0
[14:18:41.773] <TB2> INFO: flawed TBM trailers: 0
[14:18:41.773] <TB2> INFO: event ID mismatches: 0
[14:18:41.773] <TB2> INFO: ROC errors: 0
[14:18:41.773] <TB2> INFO: missing ROC header(s): 0
[14:18:41.773] <TB2> INFO: misplaced readback start: 0
[14:18:41.773] <TB2> INFO: Pixel decoding errors: 0
[14:18:41.773] <TB2> INFO: pixel data incomplete: 0
[14:18:41.773] <TB2> INFO: pixel address: 0
[14:18:41.773] <TB2> INFO: pulse height fill bit: 0
[14:18:41.773] <TB2> INFO: buffer corruption: 0
[14:18:41.773] <TB2> INFO: enter test to run
[14:18:41.773] <TB2> INFO: test: exit no parameter change
[14:18:41.890] <TB2> QUIET: Connection to board 149 closed.
[14:18:41.891] <TB2> INFO: pXar: this is the end, my friend