[14:34:38.280] <TB2> INFO: *** Welcome to pxar ***
[14:34:38.280] <TB2> INFO: *** Today: 2016/10/26
[14:34:38.287] <TB2> INFO: *** Version: c8ba-dirty
[14:34:38.287] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C15.dat
[14:34:38.288] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[14:34:38.288] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//defaultMaskFile.dat
[14:34:38.288] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters_C15.dat
[14:34:38.350] <TB2> INFO: clk: 4
[14:34:38.350] <TB2> INFO: ctr: 4
[14:34:38.350] <TB2> INFO: sda: 19
[14:34:38.350] <TB2> INFO: tin: 9
[14:34:38.350] <TB2> INFO: level: 15
[14:34:38.350] <TB2> INFO: triggerdelay: 0
[14:34:38.350] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[14:34:38.350] <TB2> INFO: Log level: INFO
[14:34:38.358] <TB2> INFO: Found DTB DTB_WWXUD2
[14:34:38.366] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[14:34:38.368] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[14:34:38.370] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[14:34:39.916] <TB2> INFO: DUT info:
[14:34:39.916] <TB2> INFO: The DUT currently contains the following objects:
[14:34:39.916] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[14:34:39.916] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:34:39.916] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:34:39.916] <TB2> INFO: TBM Core alpha (2): 7 registers set
[14:34:39.916] <TB2> INFO: TBM Core beta (3): 7 registers set
[14:34:39.916] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[14:34:39.916] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:39.916] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[14:34:40.317] <TB2> INFO: enter 'restricted' command line mode
[14:34:40.317] <TB2> INFO: enter test to run
[14:34:40.317] <TB2> INFO: test: pretest no parameter change
[14:34:40.317] <TB2> INFO: running: pretest
[14:34:40.323] <TB2> INFO: ######################################################################
[14:34:40.323] <TB2> INFO: PixTestPretest::doTest()
[14:34:40.323] <TB2> INFO: ######################################################################
[14:34:40.325] <TB2> INFO: ----------------------------------------------------------------------
[14:34:40.325] <TB2> INFO: PixTestPretest::programROC()
[14:34:40.325] <TB2> INFO: ----------------------------------------------------------------------
[14:34:58.339] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[14:34:58.339] <TB2> INFO: IA differences per ROC: 18.5 17.7 17.7 19.3 20.1 20.1 20.1 18.5 17.7 20.1 20.9 20.1 18.5 20.1 20.1 19.3
[14:34:58.403] <TB2> INFO: ----------------------------------------------------------------------
[14:34:58.403] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[14:34:58.403] <TB2> INFO: ----------------------------------------------------------------------
[14:35:05.809] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 381 mA = 23.8125 mA/ROC
[14:35:05.809] <TB2> INFO: i(loss) [mA/ROC]: 19.2 19.2 19.2 19.2 20.1 19.2 19.2 20.1 19.2 19.2 19.2 19.2 19.2 19.2 20.1 19.2
[14:35:05.841] <TB2> INFO: ----------------------------------------------------------------------
[14:35:05.841] <TB2> INFO: PixTestPretest::findTiming()
[14:35:05.841] <TB2> INFO: ----------------------------------------------------------------------
[14:35:05.841] <TB2> INFO: PixTestCmd::init()

[14:35:37.814] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[14:35:37.814] <TB2> INFO: (success/tries = 100/100), width = 3
[14:35:39.321] <TB2> INFO: ----------------------------------------------------------------------
[14:35:39.321] <TB2> INFO: PixTestPretest::findWorkingPixel()
[14:35:39.321] <TB2> INFO: ----------------------------------------------------------------------
[14:35:39.416] <TB2> INFO: Expecting 231680 events.
[14:35:49.160] <TB2> INFO: 231680 events read in total (9152ms).
[14:35:49.169] <TB2> INFO: Test took 9843ms.
[14:35:49.405] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[14:35:49.434] <TB2> INFO: ----------------------------------------------------------------------
[14:35:49.434] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[14:35:49.434] <TB2> INFO: ----------------------------------------------------------------------
[14:35:49.529] <TB2> INFO: Expecting 231680 events.
[14:35:59.405] <TB2> INFO: 231680 events read in total (9284ms).
[14:35:59.418] <TB2> INFO: Test took 9978ms.
[14:35:59.684] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[14:35:59.684] <TB2> INFO: CalDel: 94 81 105 93 81 86 93 81 102 94 91 98 97 85 89 97
[14:35:59.684] <TB2> INFO: VthrComp: 51 51 51 52 51 51 51 52 51 51 57 52 51 53 51 52
[14:35:59.687] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C0.dat
[14:35:59.688] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C1.dat
[14:35:59.688] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C2.dat
[14:35:59.688] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C3.dat
[14:35:59.688] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C4.dat
[14:35:59.688] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C5.dat
[14:35:59.688] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C6.dat
[14:35:59.688] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C7.dat
[14:35:59.688] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C8.dat
[14:35:59.689] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C9.dat
[14:35:59.689] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C10.dat
[14:35:59.689] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C11.dat
[14:35:59.689] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C12.dat
[14:35:59.689] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C13.dat
[14:35:59.689] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C14.dat
[14:35:59.689] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters_C15.dat
[14:35:59.690] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[14:35:59.690] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[14:35:59.690] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[14:35:59.690] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[14:35:59.690] <TB2> INFO: PixTestPretest::doTest() done, duration: 79 seconds
[14:35:59.743] <TB2> INFO: enter test to run
[14:35:59.743] <TB2> INFO: test: fulltest no parameter change
[14:35:59.743] <TB2> INFO: running: fulltest
[14:35:59.743] <TB2> INFO: ######################################################################
[14:35:59.744] <TB2> INFO: PixTestFullTest::doTest()
[14:35:59.744] <TB2> INFO: ######################################################################
[14:35:59.745] <TB2> INFO: ######################################################################
[14:35:59.745] <TB2> INFO: PixTestAlive::doTest()
[14:35:59.745] <TB2> INFO: ######################################################################
[14:35:59.747] <TB2> INFO: ----------------------------------------------------------------------
[14:35:59.747] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:35:59.747] <TB2> INFO: ----------------------------------------------------------------------
[14:35:59.985] <TB2> INFO: Expecting 41600 events.
[14:36:03.616] <TB2> INFO: 41600 events read in total (3039ms).
[14:36:03.616] <TB2> INFO: Test took 3868ms.
[14:36:03.853] <TB2> INFO: PixTestAlive::aliveTest() done
[14:36:03.853] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:36:03.855] <TB2> INFO: ----------------------------------------------------------------------
[14:36:03.855] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:36:03.855] <TB2> INFO: ----------------------------------------------------------------------
[14:36:04.098] <TB2> INFO: Expecting 41600 events.
[14:36:07.054] <TB2> INFO: 41600 events read in total (2364ms).
[14:36:07.054] <TB2> INFO: Test took 3197ms.
[14:36:07.055] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[14:36:07.297] <TB2> INFO: PixTestAlive::maskTest() done
[14:36:07.297] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:36:07.298] <TB2> INFO: ----------------------------------------------------------------------
[14:36:07.298] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:36:07.298] <TB2> INFO: ----------------------------------------------------------------------
[14:36:07.545] <TB2> INFO: Expecting 41600 events.
[14:36:11.044] <TB2> INFO: 41600 events read in total (2908ms).
[14:36:11.045] <TB2> INFO: Test took 3744ms.
[14:36:11.285] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[14:36:11.285] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:36:11.285] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[14:36:11.285] <TB2> INFO: Decoding statistics:
[14:36:11.285] <TB2> INFO: General information:
[14:36:11.285] <TB2> INFO: 16bit words read: 0
[14:36:11.285] <TB2> INFO: valid events total: 0
[14:36:11.285] <TB2> INFO: empty events: 0
[14:36:11.285] <TB2> INFO: valid events with pixels: 0
[14:36:11.286] <TB2> INFO: valid pixel hits: 0
[14:36:11.286] <TB2> INFO: Event errors: 0
[14:36:11.286] <TB2> INFO: start marker: 0
[14:36:11.286] <TB2> INFO: stop marker: 0
[14:36:11.286] <TB2> INFO: overflow: 0
[14:36:11.286] <TB2> INFO: invalid 5bit words: 0
[14:36:11.286] <TB2> INFO: invalid XOR eye diagram: 0
[14:36:11.286] <TB2> INFO: frame (failed synchr.): 0
[14:36:11.286] <TB2> INFO: idle data (no TBM trl): 0
[14:36:11.286] <TB2> INFO: no data (only TBM hdr): 0
[14:36:11.286] <TB2> INFO: TBM errors: 0
[14:36:11.286] <TB2> INFO: flawed TBM headers: 0
[14:36:11.286] <TB2> INFO: flawed TBM trailers: 0
[14:36:11.286] <TB2> INFO: event ID mismatches: 0
[14:36:11.286] <TB2> INFO: ROC errors: 0
[14:36:11.286] <TB2> INFO: missing ROC header(s): 0
[14:36:11.286] <TB2> INFO: misplaced readback start: 0
[14:36:11.286] <TB2> INFO: Pixel decoding errors: 0
[14:36:11.286] <TB2> INFO: pixel data incomplete: 0
[14:36:11.286] <TB2> INFO: pixel address: 0
[14:36:11.286] <TB2> INFO: pulse height fill bit: 0
[14:36:11.286] <TB2> INFO: buffer corruption: 0
[14:36:11.294] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C15.dat
[14:36:11.294] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[14:36:11.294] <TB2> INFO: ######################################################################
[14:36:11.294] <TB2> INFO: PixTestReadback::doTest()
[14:36:11.294] <TB2> INFO: ######################################################################
[14:36:11.294] <TB2> INFO: ----------------------------------------------------------------------
[14:36:11.294] <TB2> INFO: PixTestReadback::CalibrateVd()
[14:36:11.294] <TB2> INFO: ----------------------------------------------------------------------
[14:36:21.276] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C0.dat
[14:36:21.277] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C1.dat
[14:36:21.277] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C2.dat
[14:36:21.277] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C3.dat
[14:36:21.277] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C4.dat
[14:36:21.277] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C5.dat
[14:36:21.277] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C6.dat
[14:36:21.277] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C7.dat
[14:36:21.277] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C8.dat
[14:36:21.277] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C9.dat
[14:36:21.277] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C10.dat
[14:36:21.278] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C11.dat
[14:36:21.278] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C12.dat
[14:36:21.278] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C13.dat
[14:36:21.278] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C14.dat
[14:36:21.278] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C15.dat
[14:36:21.310] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:36:21.310] <TB2> INFO: ----------------------------------------------------------------------
[14:36:21.310] <TB2> INFO: PixTestReadback::CalibrateVa()
[14:36:21.310] <TB2> INFO: ----------------------------------------------------------------------
[14:36:31.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C0.dat
[14:36:31.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C1.dat
[14:36:31.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C2.dat
[14:36:31.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C3.dat
[14:36:31.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C4.dat
[14:36:31.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C5.dat
[14:36:31.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C6.dat
[14:36:31.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C7.dat
[14:36:31.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C8.dat
[14:36:31.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C9.dat
[14:36:31.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C10.dat
[14:36:31.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C11.dat
[14:36:31.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C12.dat
[14:36:31.249] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C13.dat
[14:36:31.249] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C14.dat
[14:36:31.249] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C15.dat
[14:36:31.281] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:36:31.281] <TB2> INFO: ----------------------------------------------------------------------
[14:36:31.281] <TB2> INFO: PixTestReadback::readbackVbg()
[14:36:31.281] <TB2> INFO: ----------------------------------------------------------------------
[14:36:38.949] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:36:38.949] <TB2> INFO: ----------------------------------------------------------------------
[14:36:38.949] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[14:36:38.949] <TB2> INFO: ----------------------------------------------------------------------
[14:36:38.949] <TB2> INFO: Vbg will be calibrated using Vd calibration
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 150.2calibrated Vbg = 1.19608 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 156.6calibrated Vbg = 1.20145 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 153.8calibrated Vbg = 1.19445 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 161.4calibrated Vbg = 1.1846 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 163.9calibrated Vbg = 1.19378 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 152.3calibrated Vbg = 1.20432 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 148.7calibrated Vbg = 1.19917 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 157calibrated Vbg = 1.19691 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 154.9calibrated Vbg = 1.1983 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 149.8calibrated Vbg = 1.19196 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 169.4calibrated Vbg = 1.18624 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 155.5calibrated Vbg = 1.18572 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 158.3calibrated Vbg = 1.19202 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 147.2calibrated Vbg = 1.19519 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 147calibrated Vbg = 1.19841 :::*/*/*/*/
[14:36:38.949] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 156.7calibrated Vbg = 1.19122 :::*/*/*/*/
[14:36:38.952] <TB2> INFO: ----------------------------------------------------------------------
[14:36:38.952] <TB2> INFO: PixTestReadback::CalibrateIa()
[14:36:38.952] <TB2> INFO: ----------------------------------------------------------------------
[14:39:19.753] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C0.dat
[14:39:19.753] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C1.dat
[14:39:19.753] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C2.dat
[14:39:19.753] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C3.dat
[14:39:19.753] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C4.dat
[14:39:19.753] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C5.dat
[14:39:19.753] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C6.dat
[14:39:19.753] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C7.dat
[14:39:19.754] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C8.dat
[14:39:19.754] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C9.dat
[14:39:19.754] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C10.dat
[14:39:19.754] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C11.dat
[14:39:19.754] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C12.dat
[14:39:19.754] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C13.dat
[14:39:19.754] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C14.dat
[14:39:19.754] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//readbackCal_C15.dat
[14:39:19.782] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:39:19.783] <TB2> INFO: PixTestReadback::doTest() done
[14:39:19.783] <TB2> INFO: Decoding statistics:
[14:39:19.783] <TB2> INFO: General information:
[14:39:19.783] <TB2> INFO: 16bit words read: 1536
[14:39:19.783] <TB2> INFO: valid events total: 256
[14:39:19.783] <TB2> INFO: empty events: 256
[14:39:19.783] <TB2> INFO: valid events with pixels: 0
[14:39:19.783] <TB2> INFO: valid pixel hits: 0
[14:39:19.783] <TB2> INFO: Event errors: 0
[14:39:19.783] <TB2> INFO: start marker: 0
[14:39:19.784] <TB2> INFO: stop marker: 0
[14:39:19.784] <TB2> INFO: overflow: 0
[14:39:19.784] <TB2> INFO: invalid 5bit words: 0
[14:39:19.784] <TB2> INFO: invalid XOR eye diagram: 0
[14:39:19.784] <TB2> INFO: frame (failed synchr.): 0
[14:39:19.784] <TB2> INFO: idle data (no TBM trl): 0
[14:39:19.784] <TB2> INFO: no data (only TBM hdr): 0
[14:39:19.784] <TB2> INFO: TBM errors: 0
[14:39:19.784] <TB2> INFO: flawed TBM headers: 0
[14:39:19.784] <TB2> INFO: flawed TBM trailers: 0
[14:39:19.784] <TB2> INFO: event ID mismatches: 0
[14:39:19.784] <TB2> INFO: ROC errors: 0
[14:39:19.784] <TB2> INFO: missing ROC header(s): 0
[14:39:19.784] <TB2> INFO: misplaced readback start: 0
[14:39:19.784] <TB2> INFO: Pixel decoding errors: 0
[14:39:19.784] <TB2> INFO: pixel data incomplete: 0
[14:39:19.784] <TB2> INFO: pixel address: 0
[14:39:19.784] <TB2> INFO: pulse height fill bit: 0
[14:39:19.784] <TB2> INFO: buffer corruption: 0
[14:39:19.837] <TB2> INFO: ######################################################################
[14:39:19.837] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[14:39:19.837] <TB2> INFO: ######################################################################
[14:39:19.839] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[14:39:19.869] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:39:19.870] <TB2> INFO: run 1 of 1
[14:39:20.106] <TB2> INFO: Expecting 3120000 events.
[14:39:51.401] <TB2> INFO: 677805 events read in total (30703ms).
[14:40:21.755] <TB2> INFO: 1351100 events read in total (61057ms).











[14:40:52.225] <TB2> INFO: 2022405 events read in total (91527ms).











[14:41:22.773] <TB2> INFO: 2694880 events read in total (122075ms).











[14:41:41.893] <TB2> INFO: 3120000 events read in total (141195ms).
[14:41:42.008] <TB2> INFO: Test took 142140ms.
[14:42:04.602] <TB2> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 164 seconds
[14:42:04.602] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:42:04.603] <TB2> INFO: separation cut (per ROC): 105 105 102 111 121 102 106 111 101 115 121 111 114 115 103 120
[14:42:04.603] <TB2> INFO: Decoding statistics:
[14:42:04.603] <TB2> INFO: General information:
[14:42:04.603] <TB2> INFO: 16bit words read: 0
[14:42:04.603] <TB2> INFO: valid events total: 0
[14:42:04.603] <TB2> INFO: empty events: 0
[14:42:04.603] <TB2> INFO: valid events with pixels: 0
[14:42:04.603] <TB2> INFO: valid pixel hits: 0
[14:42:04.603] <TB2> INFO: Event errors: 0
[14:42:04.603] <TB2> INFO: start marker: 0
[14:42:04.603] <TB2> INFO: stop marker: 0
[14:42:04.603] <TB2> INFO: overflow: 0
[14:42:04.603] <TB2> INFO: invalid 5bit words: 0
[14:42:04.603] <TB2> INFO: invalid XOR eye diagram: 0
[14:42:04.603] <TB2> INFO: frame (failed synchr.): 0
[14:42:04.603] <TB2> INFO: idle data (no TBM trl): 0
[14:42:04.603] <TB2> INFO: no data (only TBM hdr): 0
[14:42:04.603] <TB2> INFO: TBM errors: 0
[14:42:04.603] <TB2> INFO: flawed TBM headers: 0
[14:42:04.603] <TB2> INFO: flawed TBM trailers: 0
[14:42:04.603] <TB2> INFO: event ID mismatches: 0
[14:42:04.603] <TB2> INFO: ROC errors: 0
[14:42:04.603] <TB2> INFO: missing ROC header(s): 0
[14:42:04.603] <TB2> INFO: misplaced readback start: 0
[14:42:04.603] <TB2> INFO: Pixel decoding errors: 0
[14:42:04.603] <TB2> INFO: pixel data incomplete: 0
[14:42:04.603] <TB2> INFO: pixel address: 0
[14:42:04.603] <TB2> INFO: pulse height fill bit: 0
[14:42:04.603] <TB2> INFO: buffer corruption: 0
[14:42:04.652] <TB2> INFO: ######################################################################
[14:42:04.652] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:42:04.652] <TB2> INFO: ######################################################################
[14:42:04.652] <TB2> INFO: ----------------------------------------------------------------------
[14:42:04.652] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:42:04.652] <TB2> INFO: ----------------------------------------------------------------------
[14:42:04.652] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[14:42:04.666] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[14:42:04.666] <TB2> INFO: run 1 of 1
[14:42:04.918] <TB2> INFO: Expecting 36608000 events.
[14:42:28.960] <TB2> INFO: 704950 events read in total (23450ms).
[14:42:52.045] <TB2> INFO: 1391900 events read in total (46535ms).
[14:43:15.209] <TB2> INFO: 2079350 events read in total (69699ms).
[14:43:38.341] <TB2> INFO: 2765900 events read in total (92831ms).
[14:44:01.504] <TB2> INFO: 3453350 events read in total (115994ms).
[14:44:24.482] <TB2> INFO: 4138700 events read in total (138972ms).
[14:44:47.410] <TB2> INFO: 4826150 events read in total (161900ms).
[14:45:10.668] <TB2> INFO: 5512300 events read in total (185158ms).
[14:45:33.625] <TB2> INFO: 6200200 events read in total (208115ms).
[14:45:56.884] <TB2> INFO: 6887750 events read in total (231374ms).
[14:46:19.981] <TB2> INFO: 7572850 events read in total (254471ms).
[14:46:42.755] <TB2> INFO: 8254950 events read in total (277245ms).
[14:47:05.860] <TB2> INFO: 8940300 events read in total (300350ms).
[14:47:28.881] <TB2> INFO: 9625900 events read in total (323371ms).
[14:47:52.320] <TB2> INFO: 10311650 events read in total (346810ms).
[14:48:15.620] <TB2> INFO: 10996500 events read in total (370110ms).
[14:48:38.758] <TB2> INFO: 11681100 events read in total (393248ms).
[14:49:01.909] <TB2> INFO: 12363250 events read in total (416399ms).
[14:49:25.123] <TB2> INFO: 13047700 events read in total (439613ms).
[14:49:48.272] <TB2> INFO: 13729050 events read in total (462762ms).
[14:50:11.340] <TB2> INFO: 14411950 events read in total (485830ms).
[14:50:34.137] <TB2> INFO: 15095050 events read in total (508627ms).
[14:50:57.138] <TB2> INFO: 15776450 events read in total (531628ms).
[14:51:20.407] <TB2> INFO: 16455800 events read in total (554897ms).
[14:51:43.525] <TB2> INFO: 17139300 events read in total (578015ms).
[14:52:06.491] <TB2> INFO: 17820200 events read in total (600981ms).
[14:52:29.625] <TB2> INFO: 18500800 events read in total (624115ms).
[14:52:52.880] <TB2> INFO: 19180300 events read in total (647370ms).
[14:53:15.811] <TB2> INFO: 19858350 events read in total (670301ms).
[14:53:38.806] <TB2> INFO: 20535350 events read in total (693296ms).
[14:54:01.933] <TB2> INFO: 21212800 events read in total (716423ms).
[14:54:25.033] <TB2> INFO: 21890800 events read in total (739523ms).
[14:54:48.259] <TB2> INFO: 22568250 events read in total (762749ms).
[14:55:11.284] <TB2> INFO: 23246050 events read in total (785774ms).
[14:55:34.244] <TB2> INFO: 23921150 events read in total (808734ms).
[14:55:57.142] <TB2> INFO: 24598350 events read in total (831632ms).
[14:56:20.118] <TB2> INFO: 25273900 events read in total (854608ms).
[14:56:43.044] <TB2> INFO: 25949600 events read in total (877534ms).
[14:57:05.879] <TB2> INFO: 26623850 events read in total (900369ms).
[14:57:28.925] <TB2> INFO: 27302050 events read in total (923415ms).
[14:57:51.976] <TB2> INFO: 27978250 events read in total (946466ms).
[14:58:15.025] <TB2> INFO: 28653700 events read in total (969515ms).
[14:58:37.958] <TB2> INFO: 29330150 events read in total (992448ms).
[14:59:00.669] <TB2> INFO: 30005650 events read in total (1015159ms).
[14:59:23.630] <TB2> INFO: 30679800 events read in total (1038120ms).
[14:59:46.523] <TB2> INFO: 31355350 events read in total (1061013ms).
[15:00:09.564] <TB2> INFO: 32030350 events read in total (1084054ms).
[15:00:32.430] <TB2> INFO: 32706000 events read in total (1106920ms).
[15:00:55.490] <TB2> INFO: 33384000 events read in total (1129980ms).
[15:01:18.549] <TB2> INFO: 34061450 events read in total (1153039ms).
[15:01:41.737] <TB2> INFO: 34739600 events read in total (1176227ms).
[15:02:04.857] <TB2> INFO: 35417350 events read in total (1199347ms).
[15:02:27.797] <TB2> INFO: 36102100 events read in total (1222287ms).
[15:02:45.021] <TB2> INFO: 36608000 events read in total (1239511ms).
[15:02:45.186] <TB2> INFO: Test took 1240521ms.
[15:02:45.662] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:02:47.624] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:02:49.601] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:02:51.539] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:02:53.373] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:02:55.200] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:02:57.307] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:02:59.516] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:03:01.536] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:03:03.477] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:03:05.761] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:03:07.840] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:03:09.809] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:03:11.439] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:03:12.966] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:03:14.410] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:03:16.700] <TB2> INFO: PixTestScurves::scurves() done
[15:03:16.700] <TB2> INFO: Vcal mean: 124.58 122.66 115.72 126.22 129.00 115.50 129.66 134.88 118.90 126.49 140.76 127.34 128.71 126.64 113.94 136.60
[15:03:16.700] <TB2> INFO: Vcal RMS: 6.10 5.97 5.25 6.38 6.05 5.12 6.09 5.90 5.78 5.78 6.14 6.02 5.88 5.91 5.42 5.87
[15:03:16.700] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1272 seconds
[15:03:16.700] <TB2> INFO: Decoding statistics:
[15:03:16.700] <TB2> INFO: General information:
[15:03:16.700] <TB2> INFO: 16bit words read: 0
[15:03:16.700] <TB2> INFO: valid events total: 0
[15:03:16.700] <TB2> INFO: empty events: 0
[15:03:16.700] <TB2> INFO: valid events with pixels: 0
[15:03:16.700] <TB2> INFO: valid pixel hits: 0
[15:03:16.700] <TB2> INFO: Event errors: 0
[15:03:16.700] <TB2> INFO: start marker: 0
[15:03:16.700] <TB2> INFO: stop marker: 0
[15:03:16.700] <TB2> INFO: overflow: 0
[15:03:16.700] <TB2> INFO: invalid 5bit words: 0
[15:03:16.700] <TB2> INFO: invalid XOR eye diagram: 0
[15:03:16.700] <TB2> INFO: frame (failed synchr.): 0
[15:03:16.700] <TB2> INFO: idle data (no TBM trl): 0
[15:03:16.700] <TB2> INFO: no data (only TBM hdr): 0
[15:03:16.700] <TB2> INFO: TBM errors: 0
[15:03:16.700] <TB2> INFO: flawed TBM headers: 0
[15:03:16.700] <TB2> INFO: flawed TBM trailers: 0
[15:03:16.700] <TB2> INFO: event ID mismatches: 0
[15:03:16.700] <TB2> INFO: ROC errors: 0
[15:03:16.700] <TB2> INFO: missing ROC header(s): 0
[15:03:16.700] <TB2> INFO: misplaced readback start: 0
[15:03:16.700] <TB2> INFO: Pixel decoding errors: 0
[15:03:16.700] <TB2> INFO: pixel data incomplete: 0
[15:03:16.700] <TB2> INFO: pixel address: 0
[15:03:16.700] <TB2> INFO: pulse height fill bit: 0
[15:03:16.700] <TB2> INFO: buffer corruption: 0
[15:03:16.794] <TB2> INFO: ######################################################################
[15:03:16.794] <TB2> INFO: PixTestTrim::doTest()
[15:03:16.794] <TB2> INFO: ######################################################################
[15:03:16.795] <TB2> INFO: ----------------------------------------------------------------------
[15:03:16.795] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[15:03:16.795] <TB2> INFO: ----------------------------------------------------------------------
[15:03:16.863] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[15:03:16.863] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:03:16.877] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:03:16.877] <TB2> INFO: run 1 of 1
[15:03:17.202] <TB2> INFO: Expecting 5025280 events.
[15:03:48.296] <TB2> INFO: 835344 events read in total (30490ms).
[15:04:18.841] <TB2> INFO: 1667512 events read in total (61035ms).
[15:04:49.358] <TB2> INFO: 2498880 events read in total (91552ms).
[15:05:19.530] <TB2> INFO: 3325896 events read in total (121724ms).
[15:05:49.834] <TB2> INFO: 4149936 events read in total (152028ms).
[15:06:19.818] <TB2> INFO: 4973136 events read in total (182012ms).
[15:06:22.414] <TB2> INFO: 5025280 events read in total (184608ms).
[15:06:22.470] <TB2> INFO: Test took 185594ms.
[15:06:40.753] <TB2> INFO: ROC 0 VthrComp = 124
[15:06:40.754] <TB2> INFO: ROC 1 VthrComp = 119
[15:06:40.754] <TB2> INFO: ROC 2 VthrComp = 109
[15:06:40.754] <TB2> INFO: ROC 3 VthrComp = 127
[15:06:40.754] <TB2> INFO: ROC 4 VthrComp = 133
[15:06:40.754] <TB2> INFO: ROC 5 VthrComp = 118
[15:06:40.754] <TB2> INFO: ROC 6 VthrComp = 124
[15:06:40.754] <TB2> INFO: ROC 7 VthrComp = 132
[15:06:40.754] <TB2> INFO: ROC 8 VthrComp = 115
[15:06:40.755] <TB2> INFO: ROC 9 VthrComp = 124
[15:06:40.755] <TB2> INFO: ROC 10 VthrComp = 132
[15:06:40.755] <TB2> INFO: ROC 11 VthrComp = 124
[15:06:40.755] <TB2> INFO: ROC 12 VthrComp = 128
[15:06:40.755] <TB2> INFO: ROC 13 VthrComp = 128
[15:06:40.755] <TB2> INFO: ROC 14 VthrComp = 113
[15:06:40.755] <TB2> INFO: ROC 15 VthrComp = 130
[15:06:40.999] <TB2> INFO: Expecting 41600 events.
[15:06:44.511] <TB2> INFO: 41600 events read in total (2921ms).
[15:06:44.512] <TB2> INFO: Test took 3755ms.
[15:06:44.521] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[15:06:44.521] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:06:44.533] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:06:44.533] <TB2> INFO: run 1 of 1
[15:06:44.812] <TB2> INFO: Expecting 5025280 events.
[15:07:11.536] <TB2> INFO: 590376 events read in total (26133ms).
[15:07:37.549] <TB2> INFO: 1179944 events read in total (52146ms).
[15:08:03.574] <TB2> INFO: 1770136 events read in total (78171ms).
[15:08:29.635] <TB2> INFO: 2360016 events read in total (104232ms).
[15:08:55.615] <TB2> INFO: 2947696 events read in total (130212ms).
[15:09:21.130] <TB2> INFO: 3534152 events read in total (155727ms).
[15:09:46.947] <TB2> INFO: 4119704 events read in total (181544ms).
[15:10:12.804] <TB2> INFO: 4704928 events read in total (207401ms).
[15:10:27.293] <TB2> INFO: 5025280 events read in total (221890ms).
[15:10:27.470] <TB2> INFO: Test took 222936ms.
[15:10:55.081] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 60.825 for pixel 3/20 mean/min/max = 46.4551/32.0556/60.8546
[15:10:55.082] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 61.225 for pixel 14/16 mean/min/max = 46.2404/31.12/61.3608
[15:10:55.082] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 63.9093 for pixel 9/0 mean/min/max = 49.3733/34.7326/64.014
[15:10:55.083] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.7549 for pixel 16/1 mean/min/max = 45.3445/29.8399/60.8491
[15:10:55.083] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 59.3877 for pixel 21/55 mean/min/max = 46.7847/34.049/59.5204
[15:10:55.084] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 57.251 for pixel 10/33 mean/min/max = 44.8085/32.1666/57.4504
[15:10:55.084] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 61.4605 for pixel 50/6 mean/min/max = 47.2714/32.8817/61.6612
[15:10:55.085] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 62.3788 for pixel 1/18 mean/min/max = 48.1026/33.5403/62.665
[15:10:55.085] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 60.8635 for pixel 24/6 mean/min/max = 46.7691/32.6538/60.8845
[15:10:55.086] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 61.0254 for pixel 5/0 mean/min/max = 46.8033/32.4856/61.1211
[15:10:55.086] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 71.2456 for pixel 2/76 mean/min/max = 54.7892/38.1333/71.445
[15:10:55.087] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 62.0094 for pixel 36/2 mean/min/max = 47.6386/32.9482/62.329
[15:10:55.087] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 60.0588 for pixel 7/7 mean/min/max = 45.7144/31.3258/60.1031
[15:10:55.088] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 59.7192 for pixel 25/18 mean/min/max = 45.8601/31.7819/59.9383
[15:10:55.088] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 60.7645 for pixel 39/1 mean/min/max = 46.998/33.204/60.7921
[15:10:55.089] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 62.3378 for pixel 10/0 mean/min/max = 47.074/31.576/62.5721
[15:10:55.089] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:10:55.178] <TB2> INFO: Expecting 411648 events.
[15:11:04.751] <TB2> INFO: 411648 events read in total (8981ms).
[15:11:04.757] <TB2> INFO: Expecting 411648 events.
[15:11:14.169] <TB2> INFO: 411648 events read in total (9009ms).
[15:11:14.181] <TB2> INFO: Expecting 411648 events.
[15:11:23.647] <TB2> INFO: 411648 events read in total (9063ms).
[15:11:23.662] <TB2> INFO: Expecting 411648 events.
[15:11:33.038] <TB2> INFO: 411648 events read in total (8972ms).
[15:11:33.058] <TB2> INFO: Expecting 411648 events.
[15:11:42.583] <TB2> INFO: 411648 events read in total (9122ms).
[15:11:42.601] <TB2> INFO: Expecting 411648 events.
[15:11:52.031] <TB2> INFO: 411648 events read in total (9027ms).
[15:11:52.054] <TB2> INFO: Expecting 411648 events.
[15:12:01.462] <TB2> INFO: 411648 events read in total (9005ms).
[15:12:01.486] <TB2> INFO: Expecting 411648 events.
[15:12:10.879] <TB2> INFO: 411648 events read in total (8990ms).
[15:12:10.905] <TB2> INFO: Expecting 411648 events.
[15:12:20.268] <TB2> INFO: 411648 events read in total (8959ms).
[15:12:20.296] <TB2> INFO: Expecting 411648 events.
[15:12:29.649] <TB2> INFO: 411648 events read in total (8950ms).
[15:12:29.681] <TB2> INFO: Expecting 411648 events.
[15:12:39.080] <TB2> INFO: 411648 events read in total (8996ms).
[15:12:39.114] <TB2> INFO: Expecting 411648 events.
[15:12:48.481] <TB2> INFO: 411648 events read in total (8964ms).
[15:12:48.517] <TB2> INFO: Expecting 411648 events.
[15:12:57.848] <TB2> INFO: 411648 events read in total (8927ms).
[15:12:57.889] <TB2> INFO: Expecting 411648 events.
[15:13:07.342] <TB2> INFO: 411648 events read in total (9049ms).
[15:13:07.384] <TB2> INFO: Expecting 411648 events.
[15:13:16.701] <TB2> INFO: 411648 events read in total (8914ms).
[15:13:16.763] <TB2> INFO: Expecting 411648 events.
[15:13:26.123] <TB2> INFO: 411648 events read in total (8957ms).
[15:13:26.173] <TB2> INFO: Test took 151084ms.
[15:13:26.911] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[15:13:26.924] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:13:26.924] <TB2> INFO: run 1 of 1
[15:13:27.162] <TB2> INFO: Expecting 5025280 events.
[15:13:53.522] <TB2> INFO: 588544 events read in total (25768ms).
[15:14:19.498] <TB2> INFO: 1175248 events read in total (51744ms).
[15:14:45.999] <TB2> INFO: 1761936 events read in total (78245ms).
[15:15:12.609] <TB2> INFO: 2347520 events read in total (104855ms).
[15:15:39.161] <TB2> INFO: 2931776 events read in total (131407ms).
[15:16:06.131] <TB2> INFO: 3517992 events read in total (158377ms).
[15:16:32.718] <TB2> INFO: 4103840 events read in total (184964ms).
[15:16:58.880] <TB2> INFO: 4688240 events read in total (211126ms).
[15:17:14.493] <TB2> INFO: 5025280 events read in total (226739ms).
[15:17:14.649] <TB2> INFO: Test took 227727ms.
[15:17:40.657] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 5.422975 .. 143.567519
[15:17:40.896] <TB2> INFO: Expecting 208000 events.
[15:17:50.582] <TB2> INFO: 208000 events read in total (9095ms).
[15:17:50.583] <TB2> INFO: Test took 9925ms.
[15:17:50.633] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 5 .. 153 (-1/-1) hits flags = 528 (plus default)
[15:17:50.646] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:17:50.647] <TB2> INFO: run 1 of 1
[15:17:50.925] <TB2> INFO: Expecting 4958720 events.
[15:18:16.818] <TB2> INFO: 580168 events read in total (25302ms).
[15:18:42.801] <TB2> INFO: 1160608 events read in total (51286ms).
[15:19:08.865] <TB2> INFO: 1740712 events read in total (77349ms).
[15:19:35.092] <TB2> INFO: 2321272 events read in total (103577ms).
[15:20:01.107] <TB2> INFO: 2901712 events read in total (129591ms).
[15:20:26.822] <TB2> INFO: 3481344 events read in total (155306ms).
[15:20:53.374] <TB2> INFO: 4060920 events read in total (181858ms).
[15:21:19.250] <TB2> INFO: 4640912 events read in total (207734ms).
[15:21:34.075] <TB2> INFO: 4958720 events read in total (222559ms).
[15:21:34.267] <TB2> INFO: Test took 223620ms.
[15:22:05.336] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.158903 .. 47.452199
[15:22:05.592] <TB2> INFO: Expecting 208000 events.
[15:22:15.339] <TB2> INFO: 208000 events read in total (9156ms).
[15:22:15.340] <TB2> INFO: Test took 10002ms.
[15:22:15.386] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 57 (-1/-1) hits flags = 528 (plus default)
[15:22:15.400] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:22:15.400] <TB2> INFO: run 1 of 1
[15:22:15.678] <TB2> INFO: Expecting 1364480 events.
[15:22:44.150] <TB2> INFO: 652632 events read in total (27880ms).
[15:23:12.366] <TB2> INFO: 1304360 events read in total (56096ms).
[15:23:15.353] <TB2> INFO: 1364480 events read in total (59083ms).
[15:23:15.388] <TB2> INFO: Test took 59988ms.
[15:23:31.603] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 27.934324 .. 51.097787
[15:23:31.844] <TB2> INFO: Expecting 208000 events.
[15:23:41.778] <TB2> INFO: 208000 events read in total (9342ms).
[15:23:41.779] <TB2> INFO: Test took 10174ms.
[15:23:41.826] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 61 (-1/-1) hits flags = 528 (plus default)
[15:23:41.840] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:23:41.840] <TB2> INFO: run 1 of 1
[15:23:42.119] <TB2> INFO: Expecting 1497600 events.
[15:24:10.492] <TB2> INFO: 639856 events read in total (27782ms).
[15:24:38.114] <TB2> INFO: 1279168 events read in total (55404ms).
[15:24:48.383] <TB2> INFO: 1497600 events read in total (65673ms).
[15:24:48.429] <TB2> INFO: Test took 66590ms.
[15:25:04.820] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 27.545412 .. 56.774040
[15:25:05.100] <TB2> INFO: Expecting 208000 events.
[15:25:14.867] <TB2> INFO: 208000 events read in total (9175ms).
[15:25:14.867] <TB2> INFO: Test took 10045ms.
[15:25:14.916] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 17 .. 66 (-1/-1) hits flags = 528 (plus default)
[15:25:14.930] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:25:14.930] <TB2> INFO: run 1 of 1
[15:25:15.208] <TB2> INFO: Expecting 1664000 events.
[15:25:42.991] <TB2> INFO: 627056 events read in total (27191ms).
[15:26:10.173] <TB2> INFO: 1253872 events read in total (54373ms).
[15:26:28.193] <TB2> INFO: 1664000 events read in total (72393ms).
[15:26:28.244] <TB2> INFO: Test took 73315ms.
[15:26:42.271] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[15:26:42.271] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[15:26:42.285] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:26:42.285] <TB2> INFO: run 1 of 1
[15:26:42.524] <TB2> INFO: Expecting 1364480 events.
[15:27:10.912] <TB2> INFO: 667752 events read in total (27797ms).
[15:27:39.080] <TB2> INFO: 1336216 events read in total (55965ms).
[15:27:40.746] <TB2> INFO: 1364480 events read in total (57631ms).
[15:27:40.778] <TB2> INFO: Test took 58494ms.
[15:27:54.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C0.dat
[15:27:54.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C1.dat
[15:27:54.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C2.dat
[15:27:54.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C3.dat
[15:27:54.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C4.dat
[15:27:54.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C5.dat
[15:27:54.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C6.dat
[15:27:54.210] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C7.dat
[15:27:54.210] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C8.dat
[15:27:54.210] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C9.dat
[15:27:54.210] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C10.dat
[15:27:54.210] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C11.dat
[15:27:54.210] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C12.dat
[15:27:54.210] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C13.dat
[15:27:54.210] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C14.dat
[15:27:54.210] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C15.dat
[15:27:54.210] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C0.dat
[15:27:54.215] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C1.dat
[15:27:54.220] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C2.dat
[15:27:54.225] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C3.dat
[15:27:54.229] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C4.dat
[15:27:54.234] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C5.dat
[15:27:54.239] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C6.dat
[15:27:54.243] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C7.dat
[15:27:54.248] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C8.dat
[15:27:54.253] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C9.dat
[15:27:54.258] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C10.dat
[15:27:54.262] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C11.dat
[15:27:54.267] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C12.dat
[15:27:54.272] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C13.dat
[15:27:54.276] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C14.dat
[15:27:54.281] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters35_C15.dat
[15:27:54.286] <TB2> INFO: PixTestTrim::trimTest() done
[15:27:54.286] <TB2> INFO: vtrim: 122 122 135 121 119 113 133 135 118 128 152 133 116 119 129 119
[15:27:54.286] <TB2> INFO: vthrcomp: 124 119 109 127 133 118 124 132 115 124 132 124 128 128 113 130
[15:27:54.286] <TB2> INFO: vcal mean: 34.99 35.08 35.15 35.02 35.00 34.93 35.14 35.10 35.11 35.00 36.59 35.17 34.99 35.02 34.96 35.70
[15:27:54.286] <TB2> INFO: vcal RMS: 1.06 1.20 1.26 1.22 1.09 1.01 1.23 1.18 1.23 1.11 2.92 1.32 1.17 1.14 1.03 1.87
[15:27:54.286] <TB2> INFO: bits mean: 9.26 9.89 8.73 10.16 8.91 9.53 9.21 8.75 10.03 9.18 8.06 9.46 9.98 9.78 9.29 9.64
[15:27:54.286] <TB2> INFO: bits RMS: 2.74 2.66 2.55 2.72 2.63 2.76 2.71 2.75 2.40 2.76 2.68 2.57 2.63 2.65 2.57 2.89
[15:27:54.293] <TB2> INFO: ----------------------------------------------------------------------
[15:27:54.293] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[15:27:54.293] <TB2> INFO: ----------------------------------------------------------------------
[15:27:54.295] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[15:27:54.308] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:27:54.308] <TB2> INFO: run 1 of 1
[15:27:54.568] <TB2> INFO: Expecting 4160000 events.
[15:28:27.838] <TB2> INFO: 779020 events read in total (32679ms).
[15:29:00.503] <TB2> INFO: 1551850 events read in total (65344ms).
[15:29:33.099] <TB2> INFO: 2320820 events read in total (97940ms).
[15:30:05.439] <TB2> INFO: 3084140 events read in total (130280ms).
[15:30:37.908] <TB2> INFO: 3846565 events read in total (162749ms).
[15:30:51.846] <TB2> INFO: 4160000 events read in total (176687ms).
[15:30:51.916] <TB2> INFO: Test took 177607ms.
[15:31:18.498] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[15:31:18.511] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:31:18.511] <TB2> INFO: run 1 of 1
[15:31:18.748] <TB2> INFO: Expecting 4430400 events.
[15:31:51.133] <TB2> INFO: 733110 events read in total (31793ms).
[15:32:22.675] <TB2> INFO: 1463100 events read in total (63335ms).
[15:32:53.984] <TB2> INFO: 2189765 events read in total (94644ms).
[15:33:25.266] <TB2> INFO: 2912345 events read in total (125926ms).
[15:33:56.342] <TB2> INFO: 3633380 events read in total (157002ms).
[15:34:27.407] <TB2> INFO: 4355245 events read in total (188067ms).
[15:34:31.025] <TB2> INFO: 4430400 events read in total (191685ms).
[15:34:31.096] <TB2> INFO: Test took 192585ms.
[15:34:58.890] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[15:34:58.904] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:34:58.904] <TB2> INFO: run 1 of 1
[15:34:59.143] <TB2> INFO: Expecting 4472000 events.
[15:35:32.139] <TB2> INFO: 731035 events read in total (32404ms).
[15:36:04.018] <TB2> INFO: 1458530 events read in total (64283ms).
[15:36:35.301] <TB2> INFO: 2183115 events read in total (95566ms).
[15:37:07.290] <TB2> INFO: 2904020 events read in total (127555ms).
[15:37:39.005] <TB2> INFO: 3622925 events read in total (159270ms).
[15:38:09.890] <TB2> INFO: 4341565 events read in total (190155ms).
[15:38:15.833] <TB2> INFO: 4472000 events read in total (196098ms).
[15:38:15.906] <TB2> INFO: Test took 197001ms.
[15:38:42.050] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 215 (-1/-1) hits flags = 528 (plus default)
[15:38:42.063] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:38:42.063] <TB2> INFO: run 1 of 1
[15:38:42.302] <TB2> INFO: Expecting 4492800 events.
[15:39:14.276] <TB2> INFO: 729780 events read in total (31382ms).
[15:39:45.534] <TB2> INFO: 1455755 events read in total (62640ms).
[15:40:16.901] <TB2> INFO: 2179765 events read in total (94007ms).
[15:40:47.932] <TB2> INFO: 2899320 events read in total (125038ms).
[15:41:19.009] <TB2> INFO: 3617095 events read in total (156115ms).
[15:41:50.591] <TB2> INFO: 4335025 events read in total (187697ms).
[15:41:57.633] <TB2> INFO: 4492800 events read in total (194739ms).
[15:41:57.718] <TB2> INFO: Test took 195654ms.
[15:42:28.222] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 213 (-1/-1) hits flags = 528 (plus default)
[15:42:28.235] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:42:28.235] <TB2> INFO: run 1 of 1
[15:42:28.481] <TB2> INFO: Expecting 4451200 events.
[15:43:00.561] <TB2> INFO: 732455 events read in total (31489ms).
[15:43:32.059] <TB2> INFO: 1461435 events read in total (62987ms).
[15:44:03.298] <TB2> INFO: 2187160 events read in total (94226ms).
[15:44:34.729] <TB2> INFO: 2909310 events read in total (125657ms).
[15:45:06.015] <TB2> INFO: 3629765 events read in total (156943ms).
[15:45:37.478] <TB2> INFO: 4350095 events read in total (188406ms).
[15:45:42.139] <TB2> INFO: 4451200 events read in total (193067ms).
[15:45:42.210] <TB2> INFO: Test took 193975ms.
[15:46:13.128] <TB2> INFO: PixTestTrim::trimBitTest() done
[15:46:13.129] <TB2> INFO: PixTestTrim::doTest() done, duration: 2576 seconds
[15:46:13.129] <TB2> INFO: Decoding statistics:
[15:46:13.129] <TB2> INFO: General information:
[15:46:13.129] <TB2> INFO: 16bit words read: 0
[15:46:13.129] <TB2> INFO: valid events total: 0
[15:46:13.129] <TB2> INFO: empty events: 0
[15:46:13.129] <TB2> INFO: valid events with pixels: 0
[15:46:13.129] <TB2> INFO: valid pixel hits: 0
[15:46:13.129] <TB2> INFO: Event errors: 0
[15:46:13.129] <TB2> INFO: start marker: 0
[15:46:13.129] <TB2> INFO: stop marker: 0
[15:46:13.129] <TB2> INFO: overflow: 0
[15:46:13.129] <TB2> INFO: invalid 5bit words: 0
[15:46:13.129] <TB2> INFO: invalid XOR eye diagram: 0
[15:46:13.129] <TB2> INFO: frame (failed synchr.): 0
[15:46:13.129] <TB2> INFO: idle data (no TBM trl): 0
[15:46:13.129] <TB2> INFO: no data (only TBM hdr): 0
[15:46:13.129] <TB2> INFO: TBM errors: 0
[15:46:13.129] <TB2> INFO: flawed TBM headers: 0
[15:46:13.129] <TB2> INFO: flawed TBM trailers: 0
[15:46:13.129] <TB2> INFO: event ID mismatches: 0
[15:46:13.129] <TB2> INFO: ROC errors: 0
[15:46:13.129] <TB2> INFO: missing ROC header(s): 0
[15:46:13.129] <TB2> INFO: misplaced readback start: 0
[15:46:13.129] <TB2> INFO: Pixel decoding errors: 0
[15:46:13.129] <TB2> INFO: pixel data incomplete: 0
[15:46:13.129] <TB2> INFO: pixel address: 0
[15:46:13.129] <TB2> INFO: pulse height fill bit: 0
[15:46:13.129] <TB2> INFO: buffer corruption: 0
[15:46:13.829] <TB2> INFO: ######################################################################
[15:46:13.829] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[15:46:13.829] <TB2> INFO: ######################################################################
[15:46:14.068] <TB2> INFO: Expecting 41600 events.
[15:46:17.610] <TB2> INFO: 41600 events read in total (2951ms).
[15:46:17.611] <TB2> INFO: Test took 3780ms.
[15:46:18.074] <TB2> INFO: Expecting 41600 events.
[15:46:21.732] <TB2> INFO: 41600 events read in total (3066ms).
[15:46:21.733] <TB2> INFO: Test took 3917ms.
[15:46:22.033] <TB2> INFO: Expecting 41600 events.
[15:46:25.593] <TB2> INFO: 41600 events read in total (2969ms).
[15:46:25.594] <TB2> INFO: Test took 3836ms.
[15:46:25.883] <TB2> INFO: Expecting 41600 events.
[15:46:29.452] <TB2> INFO: 41600 events read in total (2978ms).
[15:46:29.453] <TB2> INFO: Test took 3835ms.
[15:46:29.742] <TB2> INFO: Expecting 41600 events.
[15:46:33.307] <TB2> INFO: 41600 events read in total (2974ms).
[15:46:33.308] <TB2> INFO: Test took 3831ms.
[15:46:33.598] <TB2> INFO: Expecting 41600 events.
[15:46:37.142] <TB2> INFO: 41600 events read in total (2952ms).
[15:46:37.143] <TB2> INFO: Test took 3810ms.
[15:46:37.432] <TB2> INFO: Expecting 41600 events.
[15:46:40.925] <TB2> INFO: 41600 events read in total (2901ms).
[15:46:40.926] <TB2> INFO: Test took 3759ms.
[15:46:41.216] <TB2> INFO: Expecting 41600 events.
[15:46:44.717] <TB2> INFO: 41600 events read in total (2910ms).
[15:46:44.718] <TB2> INFO: Test took 3768ms.
[15:46:45.007] <TB2> INFO: Expecting 41600 events.
[15:46:48.567] <TB2> INFO: 41600 events read in total (2968ms).
[15:46:48.568] <TB2> INFO: Test took 3825ms.
[15:46:48.856] <TB2> INFO: Expecting 41600 events.
[15:46:52.333] <TB2> INFO: 41600 events read in total (2881ms).
[15:46:52.334] <TB2> INFO: Test took 3742ms.
[15:46:52.623] <TB2> INFO: Expecting 41600 events.
[15:46:56.154] <TB2> INFO: 41600 events read in total (2939ms).
[15:46:56.155] <TB2> INFO: Test took 3797ms.
[15:46:56.510] <TB2> INFO: Expecting 41600 events.
[15:47:00.019] <TB2> INFO: 41600 events read in total (2917ms).
[15:47:00.021] <TB2> INFO: Test took 3837ms.
[15:47:00.310] <TB2> INFO: Expecting 41600 events.
[15:47:03.773] <TB2> INFO: 41600 events read in total (2871ms).
[15:47:03.774] <TB2> INFO: Test took 3729ms.
[15:47:04.075] <TB2> INFO: Expecting 41600 events.
[15:47:07.551] <TB2> INFO: 41600 events read in total (2885ms).
[15:47:07.552] <TB2> INFO: Test took 3753ms.
[15:47:07.841] <TB2> INFO: Expecting 41600 events.
[15:47:11.382] <TB2> INFO: 41600 events read in total (2950ms).
[15:47:11.383] <TB2> INFO: Test took 3808ms.
[15:47:11.673] <TB2> INFO: Expecting 41600 events.
[15:47:15.157] <TB2> INFO: 41600 events read in total (2893ms).
[15:47:15.158] <TB2> INFO: Test took 3750ms.
[15:47:15.447] <TB2> INFO: Expecting 41600 events.
[15:47:18.994] <TB2> INFO: 41600 events read in total (2955ms).
[15:47:18.995] <TB2> INFO: Test took 3813ms.
[15:47:19.287] <TB2> INFO: Expecting 41600 events.
[15:47:22.787] <TB2> INFO: 41600 events read in total (2908ms).
[15:47:22.788] <TB2> INFO: Test took 3767ms.
[15:47:23.137] <TB2> INFO: Expecting 41600 events.
[15:47:26.761] <TB2> INFO: 41600 events read in total (3032ms).
[15:47:26.762] <TB2> INFO: Test took 3950ms.
[15:47:27.114] <TB2> INFO: Expecting 41600 events.
[15:47:30.618] <TB2> INFO: 41600 events read in total (2912ms).
[15:47:30.619] <TB2> INFO: Test took 3830ms.
[15:47:30.908] <TB2> INFO: Expecting 41600 events.
[15:47:34.409] <TB2> INFO: 41600 events read in total (2909ms).
[15:47:34.410] <TB2> INFO: Test took 3767ms.
[15:47:34.701] <TB2> INFO: Expecting 41600 events.
[15:47:38.222] <TB2> INFO: 41600 events read in total (2929ms).
[15:47:38.222] <TB2> INFO: Test took 3786ms.
[15:47:38.512] <TB2> INFO: Expecting 41600 events.
[15:47:42.057] <TB2> INFO: 41600 events read in total (2953ms).
[15:47:42.058] <TB2> INFO: Test took 3811ms.
[15:47:42.349] <TB2> INFO: Expecting 41600 events.
[15:47:45.956] <TB2> INFO: 41600 events read in total (3016ms).
[15:47:45.957] <TB2> INFO: Test took 3874ms.
[15:47:46.247] <TB2> INFO: Expecting 41600 events.
[15:47:49.734] <TB2> INFO: 41600 events read in total (2896ms).
[15:47:49.735] <TB2> INFO: Test took 3754ms.
[15:47:50.024] <TB2> INFO: Expecting 41600 events.
[15:47:53.544] <TB2> INFO: 41600 events read in total (2928ms).
[15:47:53.545] <TB2> INFO: Test took 3786ms.
[15:47:53.883] <TB2> INFO: Expecting 41600 events.
[15:47:57.390] <TB2> INFO: 41600 events read in total (2916ms).
[15:47:57.391] <TB2> INFO: Test took 3822ms.
[15:47:57.695] <TB2> INFO: Expecting 41600 events.
[15:48:01.276] <TB2> INFO: 41600 events read in total (2990ms).
[15:48:01.277] <TB2> INFO: Test took 3860ms.
[15:48:01.566] <TB2> INFO: Expecting 2560 events.
[15:48:02.450] <TB2> INFO: 2560 events read in total (292ms).
[15:48:02.450] <TB2> INFO: Test took 1161ms.
[15:48:02.759] <TB2> INFO: Expecting 2560 events.
[15:48:03.643] <TB2> INFO: 2560 events read in total (293ms).
[15:48:03.643] <TB2> INFO: Test took 1192ms.
[15:48:03.951] <TB2> INFO: Expecting 2560 events.
[15:48:04.836] <TB2> INFO: 2560 events read in total (293ms).
[15:48:04.836] <TB2> INFO: Test took 1193ms.
[15:48:05.143] <TB2> INFO: Expecting 2560 events.
[15:48:06.027] <TB2> INFO: 2560 events read in total (292ms).
[15:48:06.027] <TB2> INFO: Test took 1190ms.
[15:48:06.335] <TB2> INFO: Expecting 2560 events.
[15:48:07.215] <TB2> INFO: 2560 events read in total (288ms).
[15:48:07.215] <TB2> INFO: Test took 1187ms.
[15:48:07.522] <TB2> INFO: Expecting 2560 events.
[15:48:08.412] <TB2> INFO: 2560 events read in total (298ms).
[15:48:08.412] <TB2> INFO: Test took 1196ms.
[15:48:08.720] <TB2> INFO: Expecting 2560 events.
[15:48:09.606] <TB2> INFO: 2560 events read in total (294ms).
[15:48:09.606] <TB2> INFO: Test took 1192ms.
[15:48:09.914] <TB2> INFO: Expecting 2560 events.
[15:48:10.800] <TB2> INFO: 2560 events read in total (294ms).
[15:48:10.801] <TB2> INFO: Test took 1195ms.
[15:48:11.110] <TB2> INFO: Expecting 2560 events.
[15:48:11.993] <TB2> INFO: 2560 events read in total (292ms).
[15:48:11.993] <TB2> INFO: Test took 1192ms.
[15:48:12.300] <TB2> INFO: Expecting 2560 events.
[15:48:13.191] <TB2> INFO: 2560 events read in total (299ms).
[15:48:13.191] <TB2> INFO: Test took 1197ms.
[15:48:13.498] <TB2> INFO: Expecting 2560 events.
[15:48:14.391] <TB2> INFO: 2560 events read in total (301ms).
[15:48:14.391] <TB2> INFO: Test took 1199ms.
[15:48:14.698] <TB2> INFO: Expecting 2560 events.
[15:48:15.588] <TB2> INFO: 2560 events read in total (297ms).
[15:48:15.589] <TB2> INFO: Test took 1197ms.
[15:48:15.896] <TB2> INFO: Expecting 2560 events.
[15:48:16.792] <TB2> INFO: 2560 events read in total (304ms).
[15:48:16.792] <TB2> INFO: Test took 1202ms.
[15:48:17.100] <TB2> INFO: Expecting 2560 events.
[15:48:17.992] <TB2> INFO: 2560 events read in total (301ms).
[15:48:17.992] <TB2> INFO: Test took 1199ms.
[15:48:18.300] <TB2> INFO: Expecting 2560 events.
[15:48:19.186] <TB2> INFO: 2560 events read in total (294ms).
[15:48:19.186] <TB2> INFO: Test took 1193ms.
[15:48:19.493] <TB2> INFO: Expecting 2560 events.
[15:48:20.377] <TB2> INFO: 2560 events read in total (292ms).
[15:48:20.377] <TB2> INFO: Test took 1190ms.
[15:48:20.381] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:48:20.688] <TB2> INFO: Expecting 655360 events.
[15:48:35.624] <TB2> INFO: 655360 events read in total (14344ms).
[15:48:35.639] <TB2> INFO: Expecting 655360 events.
[15:48:50.222] <TB2> INFO: 655360 events read in total (14180ms).
[15:48:50.241] <TB2> INFO: Expecting 655360 events.
[15:49:05.029] <TB2> INFO: 655360 events read in total (14386ms).
[15:49:05.051] <TB2> INFO: Expecting 655360 events.
[15:49:19.751] <TB2> INFO: 655360 events read in total (14297ms).
[15:49:19.776] <TB2> INFO: Expecting 655360 events.
[15:49:34.404] <TB2> INFO: 655360 events read in total (14225ms).
[15:49:34.433] <TB2> INFO: Expecting 655360 events.
[15:49:49.033] <TB2> INFO: 655360 events read in total (14197ms).
[15:49:49.067] <TB2> INFO: Expecting 655360 events.
[15:50:03.613] <TB2> INFO: 655360 events read in total (14143ms).
[15:50:03.650] <TB2> INFO: Expecting 655360 events.
[15:50:18.221] <TB2> INFO: 655360 events read in total (14168ms).
[15:50:18.266] <TB2> INFO: Expecting 655360 events.
[15:50:32.904] <TB2> INFO: 655360 events read in total (14235ms).
[15:50:32.950] <TB2> INFO: Expecting 655360 events.
[15:50:47.570] <TB2> INFO: 655360 events read in total (14217ms).
[15:50:47.620] <TB2> INFO: Expecting 655360 events.
[15:51:02.226] <TB2> INFO: 655360 events read in total (14202ms).
[15:51:02.282] <TB2> INFO: Expecting 655360 events.
[15:51:16.992] <TB2> INFO: 655360 events read in total (14307ms).
[15:51:17.061] <TB2> INFO: Expecting 655360 events.
[15:51:31.737] <TB2> INFO: 655360 events read in total (14273ms).
[15:51:31.806] <TB2> INFO: Expecting 655360 events.
[15:51:46.425] <TB2> INFO: 655360 events read in total (14216ms).
[15:51:46.515] <TB2> INFO: Expecting 655360 events.
[15:52:01.111] <TB2> INFO: 655360 events read in total (14193ms).
[15:52:01.188] <TB2> INFO: Expecting 655360 events.
[15:52:15.805] <TB2> INFO: 655360 events read in total (14213ms).
[15:52:15.942] <TB2> INFO: Test took 235562ms.
[15:52:16.038] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:52:16.296] <TB2> INFO: Expecting 655360 events.
[15:52:30.856] <TB2> INFO: 655360 events read in total (13969ms).
[15:52:30.871] <TB2> INFO: Expecting 655360 events.
[15:52:45.239] <TB2> INFO: 655360 events read in total (13965ms).
[15:52:45.255] <TB2> INFO: Expecting 655360 events.
[15:52:59.489] <TB2> INFO: 655360 events read in total (13831ms).
[15:52:59.509] <TB2> INFO: Expecting 655360 events.
[15:53:14.006] <TB2> INFO: 655360 events read in total (14094ms).
[15:53:14.032] <TB2> INFO: Expecting 655360 events.
[15:53:28.657] <TB2> INFO: 655360 events read in total (14222ms).
[15:53:28.695] <TB2> INFO: Expecting 655360 events.
[15:53:43.177] <TB2> INFO: 655360 events read in total (14079ms).
[15:53:43.210] <TB2> INFO: Expecting 655360 events.
[15:53:57.257] <TB2> INFO: 655360 events read in total (13644ms).
[15:53:57.292] <TB2> INFO: Expecting 655360 events.
[15:54:11.770] <TB2> INFO: 655360 events read in total (14075ms).
[15:54:11.817] <TB2> INFO: Expecting 655360 events.
[15:54:26.228] <TB2> INFO: 655360 events read in total (14008ms).
[15:54:26.275] <TB2> INFO: Expecting 655360 events.
[15:54:40.832] <TB2> INFO: 655360 events read in total (14154ms).
[15:54:40.884] <TB2> INFO: Expecting 655360 events.
[15:54:55.217] <TB2> INFO: 655360 events read in total (13931ms).
[15:54:55.287] <TB2> INFO: Expecting 655360 events.
[15:55:09.831] <TB2> INFO: 655360 events read in total (14141ms).
[15:55:09.899] <TB2> INFO: Expecting 655360 events.
[15:55:24.504] <TB2> INFO: 655360 events read in total (14202ms).
[15:55:24.576] <TB2> INFO: Expecting 655360 events.
[15:55:39.119] <TB2> INFO: 655360 events read in total (14140ms).
[15:55:39.229] <TB2> INFO: Expecting 655360 events.
[15:55:53.876] <TB2> INFO: 655360 events read in total (14244ms).
[15:55:53.960] <TB2> INFO: Expecting 655360 events.
[15:56:08.417] <TB2> INFO: 655360 events read in total (14053ms).
[15:56:08.506] <TB2> INFO: Test took 232468ms.
[15:56:08.680] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.686] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:56:08.691] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:56:08.697] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:56:08.702] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:56:08.708] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:56:08.714] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[15:56:08.721] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[15:56:08.727] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[15:56:08.733] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[15:56:08.738] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.744] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.749] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.755] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.760] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.766] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.771] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:56:08.777] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:56:08.783] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:56:08.788] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:56:08.794] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:56:08.800] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[15:56:08.806] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[15:56:08.812] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[15:56:08.818] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[15:56:08.823] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[15:56:08.829] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.835] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.841] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.847] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:56:08.853] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:56:08.859] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:56:08.866] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:56:08.872] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.878] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.885] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:56:08.891] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:56:08.897] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:56:08.903] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:56:08.909] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:56:08.915] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[15:56:08.921] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[15:56:08.927] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[15:56:08.933] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[15:56:08.939] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[15:56:08.945] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.951] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.957] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:56:08.965] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:56:08.974] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:56:08.983] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:56:08.993] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:08.002] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:56:09.012] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:56:09.020] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:56:09.028] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:56:09.036] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:56:09.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C0.dat
[15:56:09.078] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C1.dat
[15:56:09.078] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C2.dat
[15:56:09.078] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C3.dat
[15:56:09.078] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C4.dat
[15:56:09.078] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C5.dat
[15:56:09.078] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C6.dat
[15:56:09.078] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C7.dat
[15:56:09.079] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C8.dat
[15:56:09.079] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C9.dat
[15:56:09.079] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C10.dat
[15:56:09.079] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C11.dat
[15:56:09.079] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C12.dat
[15:56:09.079] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C13.dat
[15:56:09.079] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C14.dat
[15:56:09.079] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters35_C15.dat
[15:56:09.319] <TB2> INFO: Expecting 41600 events.
[15:56:12.471] <TB2> INFO: 41600 events read in total (2560ms).
[15:56:12.472] <TB2> INFO: Test took 3389ms.
[15:56:12.939] <TB2> INFO: Expecting 41600 events.
[15:56:15.993] <TB2> INFO: 41600 events read in total (2462ms).
[15:56:15.994] <TB2> INFO: Test took 3305ms.
[15:56:16.466] <TB2> INFO: Expecting 41600 events.
[15:56:19.666] <TB2> INFO: 41600 events read in total (2608ms).
[15:56:19.667] <TB2> INFO: Test took 3459ms.
[15:56:19.882] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:19.971] <TB2> INFO: Expecting 2560 events.
[15:56:20.858] <TB2> INFO: 2560 events read in total (294ms).
[15:56:20.858] <TB2> INFO: Test took 976ms.
[15:56:20.861] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:21.173] <TB2> INFO: Expecting 2560 events.
[15:56:22.059] <TB2> INFO: 2560 events read in total (295ms).
[15:56:22.060] <TB2> INFO: Test took 1199ms.
[15:56:22.064] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:22.367] <TB2> INFO: Expecting 2560 events.
[15:56:23.252] <TB2> INFO: 2560 events read in total (293ms).
[15:56:23.252] <TB2> INFO: Test took 1188ms.
[15:56:23.255] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:23.561] <TB2> INFO: Expecting 2560 events.
[15:56:24.451] <TB2> INFO: 2560 events read in total (298ms).
[15:56:24.452] <TB2> INFO: Test took 1197ms.
[15:56:24.454] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:24.761] <TB2> INFO: Expecting 2560 events.
[15:56:25.649] <TB2> INFO: 2560 events read in total (296ms).
[15:56:25.649] <TB2> INFO: Test took 1195ms.
[15:56:25.652] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:25.958] <TB2> INFO: Expecting 2560 events.
[15:56:26.843] <TB2> INFO: 2560 events read in total (294ms).
[15:56:26.844] <TB2> INFO: Test took 1192ms.
[15:56:26.848] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:27.152] <TB2> INFO: Expecting 2560 events.
[15:56:28.043] <TB2> INFO: 2560 events read in total (299ms).
[15:56:28.043] <TB2> INFO: Test took 1196ms.
[15:56:28.046] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:28.353] <TB2> INFO: Expecting 2560 events.
[15:56:29.239] <TB2> INFO: 2560 events read in total (295ms).
[15:56:29.240] <TB2> INFO: Test took 1194ms.
[15:56:29.243] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:29.548] <TB2> INFO: Expecting 2560 events.
[15:56:30.435] <TB2> INFO: 2560 events read in total (296ms).
[15:56:30.436] <TB2> INFO: Test took 1193ms.
[15:56:30.439] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:30.743] <TB2> INFO: Expecting 2560 events.
[15:56:31.634] <TB2> INFO: 2560 events read in total (299ms).
[15:56:31.634] <TB2> INFO: Test took 1196ms.
[15:56:31.637] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:31.943] <TB2> INFO: Expecting 2560 events.
[15:56:32.835] <TB2> INFO: 2560 events read in total (300ms).
[15:56:32.835] <TB2> INFO: Test took 1198ms.
[15:56:32.839] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:33.143] <TB2> INFO: Expecting 2560 events.
[15:56:34.033] <TB2> INFO: 2560 events read in total (298ms).
[15:56:34.033] <TB2> INFO: Test took 1194ms.
[15:56:34.035] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:34.343] <TB2> INFO: Expecting 2560 events.
[15:56:35.226] <TB2> INFO: 2560 events read in total (291ms).
[15:56:35.226] <TB2> INFO: Test took 1191ms.
[15:56:35.229] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:35.533] <TB2> INFO: Expecting 2560 events.
[15:56:36.422] <TB2> INFO: 2560 events read in total (298ms).
[15:56:36.423] <TB2> INFO: Test took 1194ms.
[15:56:36.426] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:36.732] <TB2> INFO: Expecting 2560 events.
[15:56:37.616] <TB2> INFO: 2560 events read in total (293ms).
[15:56:37.616] <TB2> INFO: Test took 1190ms.
[15:56:37.619] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:37.925] <TB2> INFO: Expecting 2560 events.
[15:56:38.817] <TB2> INFO: 2560 events read in total (300ms).
[15:56:38.817] <TB2> INFO: Test took 1198ms.
[15:56:38.820] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:39.126] <TB2> INFO: Expecting 2560 events.
[15:56:40.013] <TB2> INFO: 2560 events read in total (296ms).
[15:56:40.014] <TB2> INFO: Test took 1194ms.
[15:56:40.016] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:40.321] <TB2> INFO: Expecting 2560 events.
[15:56:41.208] <TB2> INFO: 2560 events read in total (296ms).
[15:56:41.208] <TB2> INFO: Test took 1192ms.
[15:56:41.211] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:41.516] <TB2> INFO: Expecting 2560 events.
[15:56:42.401] <TB2> INFO: 2560 events read in total (293ms).
[15:56:42.402] <TB2> INFO: Test took 1191ms.
[15:56:42.405] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:42.708] <TB2> INFO: Expecting 2560 events.
[15:56:43.597] <TB2> INFO: 2560 events read in total (293ms).
[15:56:43.598] <TB2> INFO: Test took 1193ms.
[15:56:43.600] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:43.907] <TB2> INFO: Expecting 2560 events.
[15:56:44.797] <TB2> INFO: 2560 events read in total (299ms).
[15:56:44.797] <TB2> INFO: Test took 1197ms.
[15:56:44.800] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:45.105] <TB2> INFO: Expecting 2560 events.
[15:56:45.991] <TB2> INFO: 2560 events read in total (294ms).
[15:56:45.991] <TB2> INFO: Test took 1191ms.
[15:56:45.993] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:46.301] <TB2> INFO: Expecting 2560 events.
[15:56:47.189] <TB2> INFO: 2560 events read in total (296ms).
[15:56:47.190] <TB2> INFO: Test took 1197ms.
[15:56:47.193] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:47.497] <TB2> INFO: Expecting 2560 events.
[15:56:48.386] <TB2> INFO: 2560 events read in total (297ms).
[15:56:48.387] <TB2> INFO: Test took 1194ms.
[15:56:48.390] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:48.695] <TB2> INFO: Expecting 2560 events.
[15:56:49.591] <TB2> INFO: 2560 events read in total (304ms).
[15:56:49.591] <TB2> INFO: Test took 1202ms.
[15:56:49.594] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:49.900] <TB2> INFO: Expecting 2560 events.
[15:56:50.793] <TB2> INFO: 2560 events read in total (302ms).
[15:56:50.793] <TB2> INFO: Test took 1199ms.
[15:56:50.797] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:51.102] <TB2> INFO: Expecting 2560 events.
[15:56:51.986] <TB2> INFO: 2560 events read in total (292ms).
[15:56:51.986] <TB2> INFO: Test took 1189ms.
[15:56:51.989] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:52.294] <TB2> INFO: Expecting 2560 events.
[15:56:53.187] <TB2> INFO: 2560 events read in total (301ms).
[15:56:53.187] <TB2> INFO: Test took 1199ms.
[15:56:53.192] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:53.495] <TB2> INFO: Expecting 2560 events.
[15:56:54.386] <TB2> INFO: 2560 events read in total (299ms).
[15:56:54.387] <TB2> INFO: Test took 1195ms.
[15:56:54.390] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:54.695] <TB2> INFO: Expecting 2560 events.
[15:56:55.584] <TB2> INFO: 2560 events read in total (297ms).
[15:56:55.584] <TB2> INFO: Test took 1195ms.
[15:56:55.587] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:55.893] <TB2> INFO: Expecting 2560 events.
[15:56:56.786] <TB2> INFO: 2560 events read in total (301ms).
[15:56:56.786] <TB2> INFO: Test took 1200ms.
[15:56:56.791] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:56:57.095] <TB2> INFO: Expecting 2560 events.
[15:56:57.980] <TB2> INFO: 2560 events read in total (293ms).
[15:56:57.980] <TB2> INFO: Test took 1190ms.
[15:56:58.451] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 644 seconds
[15:56:58.451] <TB2> INFO: PH scale (per ROC): 48 30 40 43 38 48 37 53 43 28 35 45 50 52 30 47
[15:56:58.451] <TB2> INFO: PH offset (per ROC): 126 100 107 101 92 117 113 99 93 91 89 112 96 125 106 123
[15:56:58.461] <TB2> INFO: Decoding statistics:
[15:56:58.461] <TB2> INFO: General information:
[15:56:58.461] <TB2> INFO: 16bit words read: 127838
[15:56:58.461] <TB2> INFO: valid events total: 20480
[15:56:58.461] <TB2> INFO: empty events: 18001
[15:56:58.461] <TB2> INFO: valid events with pixels: 2479
[15:56:58.461] <TB2> INFO: valid pixel hits: 2479
[15:56:58.461] <TB2> INFO: Event errors: 0
[15:56:58.461] <TB2> INFO: start marker: 0
[15:56:58.462] <TB2> INFO: stop marker: 0
[15:56:58.462] <TB2> INFO: overflow: 0
[15:56:58.462] <TB2> INFO: invalid 5bit words: 0
[15:56:58.462] <TB2> INFO: invalid XOR eye diagram: 0
[15:56:58.462] <TB2> INFO: frame (failed synchr.): 0
[15:56:58.462] <TB2> INFO: idle data (no TBM trl): 0
[15:56:58.462] <TB2> INFO: no data (only TBM hdr): 0
[15:56:58.462] <TB2> INFO: TBM errors: 0
[15:56:58.462] <TB2> INFO: flawed TBM headers: 0
[15:56:58.462] <TB2> INFO: flawed TBM trailers: 0
[15:56:58.462] <TB2> INFO: event ID mismatches: 0
[15:56:58.462] <TB2> INFO: ROC errors: 0
[15:56:58.462] <TB2> INFO: missing ROC header(s): 0
[15:56:58.462] <TB2> INFO: misplaced readback start: 0
[15:56:58.462] <TB2> INFO: Pixel decoding errors: 0
[15:56:58.462] <TB2> INFO: pixel data incomplete: 0
[15:56:58.462] <TB2> INFO: pixel address: 0
[15:56:58.462] <TB2> INFO: pulse height fill bit: 0
[15:56:58.462] <TB2> INFO: buffer corruption: 0
[15:56:58.632] <TB2> INFO: ######################################################################
[15:56:58.632] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:56:58.632] <TB2> INFO: ######################################################################
[15:56:58.649] <TB2> INFO: scanning low vcal = 10
[15:56:58.897] <TB2> INFO: Expecting 41600 events.
[15:57:02.512] <TB2> INFO: 41600 events read in total (3023ms).
[15:57:02.513] <TB2> INFO: Test took 3863ms.
[15:57:02.515] <TB2> INFO: scanning low vcal = 20
[15:57:02.808] <TB2> INFO: Expecting 41600 events.
[15:57:06.422] <TB2> INFO: 41600 events read in total (3022ms).
[15:57:06.422] <TB2> INFO: Test took 3907ms.
[15:57:06.424] <TB2> INFO: scanning low vcal = 30
[15:57:06.719] <TB2> INFO: Expecting 41600 events.
[15:57:10.410] <TB2> INFO: 41600 events read in total (3099ms).
[15:57:10.411] <TB2> INFO: Test took 3987ms.
[15:57:10.414] <TB2> INFO: scanning low vcal = 40
[15:57:10.693] <TB2> INFO: Expecting 41600 events.
[15:57:14.666] <TB2> INFO: 41600 events read in total (3381ms).
[15:57:14.667] <TB2> INFO: Test took 4253ms.
[15:57:14.670] <TB2> INFO: scanning low vcal = 50
[15:57:14.948] <TB2> INFO: Expecting 41600 events.
[15:57:19.016] <TB2> INFO: 41600 events read in total (3477ms).
[15:57:19.017] <TB2> INFO: Test took 4347ms.
[15:57:19.020] <TB2> INFO: scanning low vcal = 60
[15:57:19.297] <TB2> INFO: Expecting 41600 events.
[15:57:23.361] <TB2> INFO: 41600 events read in total (3471ms).
[15:57:23.361] <TB2> INFO: Test took 4340ms.
[15:57:23.364] <TB2> INFO: scanning low vcal = 70
[15:57:23.642] <TB2> INFO: Expecting 41600 events.
[15:57:27.690] <TB2> INFO: 41600 events read in total (3458ms).
[15:57:27.691] <TB2> INFO: Test took 4327ms.
[15:57:27.695] <TB2> INFO: scanning low vcal = 80
[15:57:27.972] <TB2> INFO: Expecting 41600 events.
[15:57:32.016] <TB2> INFO: 41600 events read in total (3452ms).
[15:57:32.017] <TB2> INFO: Test took 4322ms.
[15:57:32.020] <TB2> INFO: scanning low vcal = 90
[15:57:32.298] <TB2> INFO: Expecting 41600 events.
[15:57:36.324] <TB2> INFO: 41600 events read in total (3434ms).
[15:57:36.325] <TB2> INFO: Test took 4305ms.
[15:57:36.328] <TB2> INFO: scanning low vcal = 100
[15:57:36.605] <TB2> INFO: Expecting 41600 events.
[15:57:40.644] <TB2> INFO: 41600 events read in total (3447ms).
[15:57:40.644] <TB2> INFO: Test took 4315ms.
[15:57:40.648] <TB2> INFO: scanning low vcal = 110
[15:57:40.928] <TB2> INFO: Expecting 41600 events.
[15:57:44.965] <TB2> INFO: 41600 events read in total (3445ms).
[15:57:44.966] <TB2> INFO: Test took 4318ms.
[15:57:44.969] <TB2> INFO: scanning low vcal = 120
[15:57:45.246] <TB2> INFO: Expecting 41600 events.
[15:57:49.258] <TB2> INFO: 41600 events read in total (3420ms).
[15:57:49.259] <TB2> INFO: Test took 4289ms.
[15:57:49.262] <TB2> INFO: scanning low vcal = 130
[15:57:49.539] <TB2> INFO: Expecting 41600 events.
[15:57:53.579] <TB2> INFO: 41600 events read in total (3448ms).
[15:57:53.580] <TB2> INFO: Test took 4318ms.
[15:57:53.583] <TB2> INFO: scanning low vcal = 140
[15:57:53.860] <TB2> INFO: Expecting 41600 events.
[15:57:57.906] <TB2> INFO: 41600 events read in total (3454ms).
[15:57:57.907] <TB2> INFO: Test took 4323ms.
[15:57:57.910] <TB2> INFO: scanning low vcal = 150
[15:57:58.187] <TB2> INFO: Expecting 41600 events.
[15:58:02.217] <TB2> INFO: 41600 events read in total (3438ms).
[15:58:02.218] <TB2> INFO: Test took 4308ms.
[15:58:02.221] <TB2> INFO: scanning low vcal = 160
[15:58:02.498] <TB2> INFO: Expecting 41600 events.
[15:58:06.511] <TB2> INFO: 41600 events read in total (3422ms).
[15:58:06.512] <TB2> INFO: Test took 4291ms.
[15:58:06.515] <TB2> INFO: scanning low vcal = 170
[15:58:06.792] <TB2> INFO: Expecting 41600 events.
[15:58:10.827] <TB2> INFO: 41600 events read in total (3443ms).
[15:58:10.828] <TB2> INFO: Test took 4313ms.
[15:58:10.834] <TB2> INFO: scanning low vcal = 180
[15:58:11.108] <TB2> INFO: Expecting 41600 events.
[15:58:15.126] <TB2> INFO: 41600 events read in total (3427ms).
[15:58:15.127] <TB2> INFO: Test took 4292ms.
[15:58:15.130] <TB2> INFO: scanning low vcal = 190
[15:58:15.410] <TB2> INFO: Expecting 41600 events.
[15:58:19.404] <TB2> INFO: 41600 events read in total (3402ms).
[15:58:19.405] <TB2> INFO: Test took 4275ms.
[15:58:19.408] <TB2> INFO: scanning low vcal = 200
[15:58:19.684] <TB2> INFO: Expecting 41600 events.
[15:58:23.712] <TB2> INFO: 41600 events read in total (3436ms).
[15:58:23.712] <TB2> INFO: Test took 4304ms.
[15:58:23.716] <TB2> INFO: scanning low vcal = 210
[15:58:23.992] <TB2> INFO: Expecting 41600 events.
[15:58:27.991] <TB2> INFO: 41600 events read in total (3407ms).
[15:58:27.992] <TB2> INFO: Test took 4276ms.
[15:58:27.995] <TB2> INFO: scanning low vcal = 220
[15:58:28.272] <TB2> INFO: Expecting 41600 events.
[15:58:32.261] <TB2> INFO: 41600 events read in total (3397ms).
[15:58:32.262] <TB2> INFO: Test took 4267ms.
[15:58:32.266] <TB2> INFO: scanning low vcal = 230
[15:58:32.542] <TB2> INFO: Expecting 41600 events.
[15:58:36.589] <TB2> INFO: 41600 events read in total (3455ms).
[15:58:36.589] <TB2> INFO: Test took 4323ms.
[15:58:36.593] <TB2> INFO: scanning low vcal = 240
[15:58:36.869] <TB2> INFO: Expecting 41600 events.
[15:58:40.886] <TB2> INFO: 41600 events read in total (3425ms).
[15:58:40.887] <TB2> INFO: Test took 4294ms.
[15:58:40.890] <TB2> INFO: scanning low vcal = 250
[15:58:41.171] <TB2> INFO: Expecting 41600 events.
[15:58:45.136] <TB2> INFO: 41600 events read in total (3373ms).
[15:58:45.137] <TB2> INFO: Test took 4247ms.
[15:58:45.142] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[15:58:45.418] <TB2> INFO: Expecting 41600 events.
[15:58:49.409] <TB2> INFO: 41600 events read in total (3399ms).
[15:58:49.410] <TB2> INFO: Test took 4268ms.
[15:58:49.413] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[15:58:49.690] <TB2> INFO: Expecting 41600 events.
[15:58:53.644] <TB2> INFO: 41600 events read in total (3362ms).
[15:58:53.645] <TB2> INFO: Test took 4232ms.
[15:58:53.649] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[15:58:53.925] <TB2> INFO: Expecting 41600 events.
[15:58:57.911] <TB2> INFO: 41600 events read in total (3395ms).
[15:58:57.912] <TB2> INFO: Test took 4263ms.
[15:58:57.916] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[15:58:58.192] <TB2> INFO: Expecting 41600 events.
[15:59:02.142] <TB2> INFO: 41600 events read in total (3358ms).
[15:59:02.143] <TB2> INFO: Test took 4227ms.
[15:59:02.146] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:59:02.424] <TB2> INFO: Expecting 41600 events.
[15:59:06.364] <TB2> INFO: 41600 events read in total (3348ms).
[15:59:06.365] <TB2> INFO: Test took 4219ms.
[15:59:06.795] <TB2> INFO: PixTestGainPedestal::measure() done
[15:59:47.978] <TB2> INFO: PixTestGainPedestal::fit() done
[15:59:47.978] <TB2> INFO: non-linearity mean: 0.983 0.944 0.941 0.948 0.898 0.970 0.959 0.981 0.966 1.050 0.950 0.969 0.983 0.984 0.990 0.981
[15:59:47.978] <TB2> INFO: non-linearity RMS: 0.003 0.157 0.101 0.039 0.141 0.014 0.035 0.007 0.012 0.156 0.150 0.013 0.005 0.003 0.189 0.004
[15:59:47.978] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[15:59:47.998] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[15:59:48.016] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[15:59:48.036] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[15:59:48.055] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[15:59:48.074] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[15:59:48.092] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[15:59:48.110] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[15:59:48.131] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[15:59:48.149] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[15:59:48.168] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[15:59:48.186] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[15:59:48.205] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[15:59:48.224] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[15:59:48.243] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[15:59:48.261] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[15:59:48.279] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 169 seconds
[15:59:48.279] <TB2> INFO: Decoding statistics:
[15:59:48.280] <TB2> INFO: General information:
[15:59:48.280] <TB2> INFO: 16bit words read: 3287240
[15:59:48.280] <TB2> INFO: valid events total: 332800
[15:59:48.280] <TB2> INFO: empty events: 949
[15:59:48.280] <TB2> INFO: valid events with pixels: 331851
[15:59:48.280] <TB2> INFO: valid pixel hits: 645220
[15:59:48.280] <TB2> INFO: Event errors: 0
[15:59:48.280] <TB2> INFO: start marker: 0
[15:59:48.280] <TB2> INFO: stop marker: 0
[15:59:48.280] <TB2> INFO: overflow: 0
[15:59:48.280] <TB2> INFO: invalid 5bit words: 0
[15:59:48.280] <TB2> INFO: invalid XOR eye diagram: 0
[15:59:48.280] <TB2> INFO: frame (failed synchr.): 0
[15:59:48.280] <TB2> INFO: idle data (no TBM trl): 0
[15:59:48.280] <TB2> INFO: no data (only TBM hdr): 0
[15:59:48.280] <TB2> INFO: TBM errors: 0
[15:59:48.280] <TB2> INFO: flawed TBM headers: 0
[15:59:48.280] <TB2> INFO: flawed TBM trailers: 0
[15:59:48.280] <TB2> INFO: event ID mismatches: 0
[15:59:48.280] <TB2> INFO: ROC errors: 0
[15:59:48.280] <TB2> INFO: missing ROC header(s): 0
[15:59:48.280] <TB2> INFO: misplaced readback start: 0
[15:59:48.280] <TB2> INFO: Pixel decoding errors: 0
[15:59:48.280] <TB2> INFO: pixel data incomplete: 0
[15:59:48.280] <TB2> INFO: pixel address: 0
[15:59:48.280] <TB2> INFO: pulse height fill bit: 0
[15:59:48.280] <TB2> INFO: buffer corruption: 0
[15:59:48.303] <TB2> INFO: Decoding statistics:
[15:59:48.303] <TB2> INFO: General information:
[15:59:48.303] <TB2> INFO: 16bit words read: 3416614
[15:59:48.303] <TB2> INFO: valid events total: 353536
[15:59:48.304] <TB2> INFO: empty events: 19206
[15:59:48.304] <TB2> INFO: valid events with pixels: 334330
[15:59:48.304] <TB2> INFO: valid pixel hits: 647699
[15:59:48.304] <TB2> INFO: Event errors: 0
[15:59:48.304] <TB2> INFO: start marker: 0
[15:59:48.304] <TB2> INFO: stop marker: 0
[15:59:48.304] <TB2> INFO: overflow: 0
[15:59:48.304] <TB2> INFO: invalid 5bit words: 0
[15:59:48.304] <TB2> INFO: invalid XOR eye diagram: 0
[15:59:48.304] <TB2> INFO: frame (failed synchr.): 0
[15:59:48.304] <TB2> INFO: idle data (no TBM trl): 0
[15:59:48.304] <TB2> INFO: no data (only TBM hdr): 0
[15:59:48.304] <TB2> INFO: TBM errors: 0
[15:59:48.304] <TB2> INFO: flawed TBM headers: 0
[15:59:48.304] <TB2> INFO: flawed TBM trailers: 0
[15:59:48.304] <TB2> INFO: event ID mismatches: 0
[15:59:48.304] <TB2> INFO: ROC errors: 0
[15:59:48.304] <TB2> INFO: missing ROC header(s): 0
[15:59:48.304] <TB2> INFO: misplaced readback start: 0
[15:59:48.304] <TB2> INFO: Pixel decoding errors: 0
[15:59:48.304] <TB2> INFO: pixel data incomplete: 0
[15:59:48.304] <TB2> INFO: pixel address: 0
[15:59:48.304] <TB2> INFO: pulse height fill bit: 0
[15:59:48.304] <TB2> INFO: buffer corruption: 0
[15:59:48.304] <TB2> INFO: enter test to run
[15:59:48.304] <TB2> INFO: test: trim80 no parameter change
[15:59:48.304] <TB2> INFO: running: trim80
[15:59:48.305] <TB2> INFO: ######################################################################
[15:59:48.305] <TB2> INFO: PixTestTrim80::doTest()
[15:59:48.305] <TB2> INFO: ######################################################################
[15:59:48.307] <TB2> INFO: ----------------------------------------------------------------------
[15:59:48.307] <TB2> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[15:59:48.307] <TB2> INFO: ----------------------------------------------------------------------
[15:59:48.377] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[15:59:48.377] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:59:48.391] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:59:48.391] <TB2> INFO: run 1 of 1
[15:59:48.652] <TB2> INFO: Expecting 5025280 events.
[16:00:16.978] <TB2> INFO: 685232 events read in total (27735ms).
[16:00:44.157] <TB2> INFO: 1368728 events read in total (54914ms).
[16:01:11.900] <TB2> INFO: 2050768 events read in total (82657ms).
[16:01:39.382] <TB2> INFO: 2730016 events read in total (110139ms).
[16:02:06.712] <TB2> INFO: 3408304 events read in total (137469ms).
[16:02:33.883] <TB2> INFO: 4085240 events read in total (164640ms).
[16:03:00.989] <TB2> INFO: 4760664 events read in total (191746ms).
[16:03:11.912] <TB2> INFO: 5025280 events read in total (202669ms).
[16:03:12.024] <TB2> INFO: Test took 203633ms.
[16:03:34.797] <TB2> INFO: ROC 0 VthrComp = 75
[16:03:34.797] <TB2> INFO: ROC 1 VthrComp = 74
[16:03:34.797] <TB2> INFO: ROC 2 VthrComp = 70
[16:03:34.797] <TB2> INFO: ROC 3 VthrComp = 77
[16:03:34.797] <TB2> INFO: ROC 4 VthrComp = 81
[16:03:34.797] <TB2> INFO: ROC 5 VthrComp = 72
[16:03:34.797] <TB2> INFO: ROC 6 VthrComp = 79
[16:03:34.798] <TB2> INFO: ROC 7 VthrComp = 83
[16:03:34.798] <TB2> INFO: ROC 8 VthrComp = 72
[16:03:34.798] <TB2> INFO: ROC 9 VthrComp = 76
[16:03:34.798] <TB2> INFO: ROC 10 VthrComp = 92
[16:03:34.798] <TB2> INFO: ROC 11 VthrComp = 78
[16:03:34.798] <TB2> INFO: ROC 12 VthrComp = 78
[16:03:34.798] <TB2> INFO: ROC 13 VthrComp = 79
[16:03:34.798] <TB2> INFO: ROC 14 VthrComp = 70
[16:03:34.798] <TB2> INFO: ROC 15 VthrComp = 83
[16:03:35.074] <TB2> INFO: Expecting 41600 events.
[16:03:38.755] <TB2> INFO: 41600 events read in total (3090ms).
[16:03:38.756] <TB2> INFO: Test took 3955ms.
[16:03:38.769] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[16:03:38.769] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:03:38.783] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:03:38.783] <TB2> INFO: run 1 of 1
[16:03:39.088] <TB2> INFO: Expecting 5025280 events.
[16:04:07.545] <TB2> INFO: 685424 events read in total (27865ms).
[16:04:35.174] <TB2> INFO: 1368104 events read in total (55495ms).
[16:05:02.696] <TB2> INFO: 2049688 events read in total (83016ms).
[16:05:30.057] <TB2> INFO: 2728032 events read in total (110377ms).
[16:05:57.481] <TB2> INFO: 3403352 events read in total (137801ms).
[16:06:25.029] <TB2> INFO: 4078160 events read in total (165349ms).
[16:06:52.271] <TB2> INFO: 4752008 events read in total (192591ms).
[16:07:03.515] <TB2> INFO: 5025280 events read in total (203835ms).
[16:07:03.576] <TB2> INFO: Test took 204792ms.
[16:07:27.857] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 111.206 for pixel 0/79 mean/min/max = 95.045/78.8208/111.269
[16:07:27.857] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 110.313 for pixel 0/76 mean/min/max = 94.1365/77.8071/110.466
[16:07:27.857] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 107.101 for pixel 0/47 mean/min/max = 90.5938/74.0683/107.119
[16:07:27.858] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 111.18 for pixel 0/52 mean/min/max = 94.7186/78.1404/111.297
[16:07:27.858] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 106.634 for pixel 7/63 mean/min/max = 90.6111/74.5754/106.647
[16:07:27.859] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 106.752 for pixel 48/2 mean/min/max = 91.831/76.7838/106.878
[16:07:27.859] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 109.423 for pixel 45/79 mean/min/max = 93.1878/76.9277/109.448
[16:07:27.860] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 107.738 for pixel 12/75 mean/min/max = 91.4406/75.1284/107.753
[16:07:27.860] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 109.564 for pixel 0/79 mean/min/max = 93.1597/76.7129/109.607
[16:07:27.861] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 111.881 for pixel 5/16 mean/min/max = 95.524/79.1422/111.906
[16:07:27.861] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 110.893 for pixel 28/73 mean/min/max = 93.3833/75.7797/110.987
[16:07:27.862] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 111.224 for pixel 0/76 mean/min/max = 95.1434/79.0369/111.25
[16:07:27.862] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 111.52 for pixel 0/31 mean/min/max = 95.2335/78.8831/111.584
[16:07:27.863] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 110.046 for pixel 51/3 mean/min/max = 94.0171/77.9096/110.125
[16:07:27.863] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 107.66 for pixel 8/13 mean/min/max = 91.1699/74.5626/107.777
[16:07:27.863] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 108.781 for pixel 38/0 mean/min/max = 91.6344/74.3962/108.873
[16:07:27.867] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:07:27.956] <TB2> INFO: Expecting 411648 events.
[16:07:37.452] <TB2> INFO: 411648 events read in total (8904ms).
[16:07:37.460] <TB2> INFO: Expecting 411648 events.
[16:07:46.764] <TB2> INFO: 411648 events read in total (8900ms).
[16:07:46.776] <TB2> INFO: Expecting 411648 events.
[16:07:55.951] <TB2> INFO: 411648 events read in total (8772ms).
[16:07:55.965] <TB2> INFO: Expecting 411648 events.
[16:08:05.071] <TB2> INFO: 411648 events read in total (8703ms).
[16:08:05.088] <TB2> INFO: Expecting 411648 events.
[16:08:14.365] <TB2> INFO: 411648 events read in total (8874ms).
[16:08:14.385] <TB2> INFO: Expecting 411648 events.
[16:08:23.837] <TB2> INFO: 411648 events read in total (9049ms).
[16:08:23.859] <TB2> INFO: Expecting 411648 events.
[16:08:33.193] <TB2> INFO: 411648 events read in total (8931ms).
[16:08:33.225] <TB2> INFO: Expecting 411648 events.
[16:08:42.576] <TB2> INFO: 411648 events read in total (8947ms).
[16:08:42.605] <TB2> INFO: Expecting 411648 events.
[16:08:51.926] <TB2> INFO: 411648 events read in total (8918ms).
[16:08:51.957] <TB2> INFO: Expecting 411648 events.
[16:09:01.333] <TB2> INFO: 411648 events read in total (8973ms).
[16:09:01.400] <TB2> INFO: Expecting 411648 events.
[16:09:10.666] <TB2> INFO: 411648 events read in total (8863ms).
[16:09:10.704] <TB2> INFO: Expecting 411648 events.
[16:09:19.988] <TB2> INFO: 411648 events read in total (8881ms).
[16:09:20.037] <TB2> INFO: Expecting 411648 events.
[16:09:29.245] <TB2> INFO: 411648 events read in total (8805ms).
[16:09:29.304] <TB2> INFO: Expecting 411648 events.
[16:09:38.636] <TB2> INFO: 411648 events read in total (8929ms).
[16:09:38.715] <TB2> INFO: Expecting 411648 events.
[16:09:48.111] <TB2> INFO: 411648 events read in total (8993ms).
[16:09:48.185] <TB2> INFO: Expecting 411648 events.
[16:09:57.381] <TB2> INFO: 411648 events read in total (8793ms).
[16:09:57.459] <TB2> INFO: Test took 149592ms.
[16:09:58.976] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[16:09:58.989] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:09:58.989] <TB2> INFO: run 1 of 1
[16:09:59.228] <TB2> INFO: Expecting 5025280 events.
[16:10:27.110] <TB2> INFO: 668872 events read in total (27290ms).
[16:10:54.255] <TB2> INFO: 1336240 events read in total (54436ms).
[16:11:21.314] <TB2> INFO: 2003592 events read in total (81494ms).
[16:11:48.325] <TB2> INFO: 2667312 events read in total (108505ms).
[16:12:15.334] <TB2> INFO: 3327776 events read in total (135514ms).
[16:12:42.201] <TB2> INFO: 3988776 events read in total (162381ms).
[16:13:08.983] <TB2> INFO: 4648216 events read in total (189163ms).
[16:13:24.582] <TB2> INFO: 5025280 events read in total (204762ms).
[16:13:24.643] <TB2> INFO: Test took 205654ms.
[16:13:48.288] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 53.849101 .. 100.781777
[16:13:48.550] <TB2> INFO: Expecting 208000 events.
[16:13:58.798] <TB2> INFO: 208000 events read in total (9657ms).
[16:13:58.799] <TB2> INFO: Test took 10510ms.
[16:13:58.851] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 43 .. 110 (-1/-1) hits flags = 528 (plus default)
[16:13:58.865] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:13:58.865] <TB2> INFO: run 1 of 1
[16:13:59.145] <TB2> INFO: Expecting 2263040 events.
[16:14:27.954] <TB2> INFO: 690472 events read in total (28217ms).
[16:15:39.834] <TB2> INFO: 1377752 events read in total (100097ms).
[16:16:41.140] <TB2> INFO: 2060648 events read in total (161403ms).
[16:17:10.132] <TB2> INFO: 2263040 events read in total (190395ms).
[16:17:10.174] <TB2> INFO: Test took 191310ms.
[16:17:28.252] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 63.331161 .. 92.594453
[16:17:28.495] <TB2> INFO: Expecting 208000 events.
[16:18:14.902] <TB2> INFO: 208000 events read in total (45816ms).
[16:18:14.920] <TB2> INFO: Test took 46666ms.
[16:18:15.122] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 53 .. 102 (-1/-1) hits flags = 528 (plus default)
[16:18:15.160] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:18:15.163] <TB2> INFO: run 1 of 1
[16:18:16.071] <TB2> INFO: Expecting 1664000 events.
[16:18:47.085] <TB2> INFO: 686464 events read in total (30358ms).
[16:20:11.038] <TB2> INFO: 1372000 events read in total (114311ms).
[16:20:23.694] <TB2> INFO: 1664000 events read in total (126967ms).
[16:20:23.746] <TB2> INFO: Test took 128576ms.
[16:21:02.185] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 68.345195 .. 88.333737
[16:21:02.775] <TB2> INFO: Expecting 208000 events.
[16:21:36.783] <TB2> INFO: 208000 events read in total (33340ms).
[16:21:36.784] <TB2> INFO: Test took 34569ms.
[16:21:36.843] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 58 .. 98 (-1/-1) hits flags = 528 (plus default)
[16:21:36.857] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:21:36.857] <TB2> INFO: run 1 of 1
[16:21:37.135] <TB2> INFO: Expecting 1364480 events.
[16:22:10.208] <TB2> INFO: 686400 events read in total (32481ms).
[16:23:21.782] <TB2> INFO: 1364480 events read in total (104055ms).
[16:23:21.816] <TB2> INFO: Test took 104959ms.
[16:23:47.210] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 71.268690 .. 87.532524
[16:23:47.751] <TB2> INFO: Expecting 208000 events.
[16:24:18.047] <TB2> INFO: 208000 events read in total (29632ms).
[16:24:18.048] <TB2> INFO: Test took 30837ms.
[16:24:18.125] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 61 .. 97 (-1/-1) hits flags = 528 (plus default)
[16:24:18.139] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:24:18.139] <TB2> INFO: run 1 of 1
[16:24:18.417] <TB2> INFO: Expecting 1231360 events.
[16:24:57.302] <TB2> INFO: 679872 events read in total (38293ms).
[16:25:20.502] <TB2> INFO: 1231360 events read in total (61494ms).
[16:25:20.546] <TB2> INFO: Test took 62408ms.
[16:25:39.269] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[16:25:39.269] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[16:25:39.283] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:25:39.283] <TB2> INFO: run 1 of 1
[16:25:39.608] <TB2> INFO: Expecting 1364480 events.
[16:26:07.814] <TB2> INFO: 668528 events read in total (27615ms).
[16:26:35.196] <TB2> INFO: 1337752 events read in total (54998ms).
[16:26:36.703] <TB2> INFO: 1364480 events read in total (56504ms).
[16:26:36.731] <TB2> INFO: Test took 57449ms.
[16:26:56.005] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C0.dat
[16:26:56.006] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C1.dat
[16:26:56.006] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C2.dat
[16:26:56.006] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C3.dat
[16:26:56.006] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C4.dat
[16:26:56.006] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C5.dat
[16:26:56.006] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C6.dat
[16:26:56.006] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C7.dat
[16:26:56.006] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C8.dat
[16:26:56.007] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C9.dat
[16:26:56.007] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C10.dat
[16:26:56.007] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C11.dat
[16:26:56.007] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C12.dat
[16:26:56.007] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C13.dat
[16:26:56.007] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C14.dat
[16:26:56.007] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//dacParameters80_C15.dat
[16:26:56.007] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C0.dat
[16:26:56.014] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C1.dat
[16:26:56.020] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C2.dat
[16:26:56.026] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C3.dat
[16:26:56.033] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C4.dat
[16:26:56.039] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C5.dat
[16:26:56.043] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C6.dat
[16:26:56.048] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C7.dat
[16:26:56.053] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C8.dat
[16:26:56.057] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C9.dat
[16:26:56.062] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C10.dat
[16:26:56.069] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C11.dat
[16:26:56.074] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C12.dat
[16:26:56.079] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C13.dat
[16:26:56.085] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C14.dat
[16:26:56.091] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1088_FullQualification_2016-10-26_12h02m_1477476121//003_FulltestTrim80_p17//trimParameters80_C15.dat
[16:26:56.096] <TB2> INFO: PixTestTrim80::trimTest() done
[16:26:56.096] <TB2> INFO: vtrim: 95 91 93 95 90 100 100 108 84 114 111 99 101 94 97 97
[16:26:56.096] <TB2> INFO: vthrcomp: 75 74 70 77 81 72 79 83 72 76 92 78 78 79 70 83
[16:26:56.096] <TB2> INFO: vcal mean: 80.10 80.06 80.06 80.09 80.06 80.04 80.01 79.98 80.05 80.05 80.01 80.04 80.05 80.01 80.03 79.98
[16:26:56.096] <TB2> INFO: vcal RMS: 0.75 0.77 0.80 0.79 0.75 0.71 0.77 0.78 0.74 0.75 0.85 0.79 0.77 0.72 0.71 0.74
[16:26:56.096] <TB2> INFO: bits mean: 8.53 9.03 10.31 8.92 10.18 9.92 9.17 10.15 9.55 9.30 9.89 8.89 9.25 9.08 10.21 10.07
[16:26:56.096] <TB2> INFO: bits RMS: 2.42 2.38 2.40 2.40 2.39 2.20 2.44 2.29 2.29 2.09 2.25 2.30 2.14 2.33 2.37 2.40
[16:26:56.105] <TB2> INFO: ----------------------------------------------------------------------
[16:26:56.105] <TB2> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[16:26:56.105] <TB2> INFO: ----------------------------------------------------------------------
[16:26:56.108] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[16:26:56.119] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:26:56.120] <TB2> INFO: run 1 of 1
[16:26:56.404] <TB2> INFO: Expecting 4160000 events.
[16:27:29.439] <TB2> INFO: 779255 events read in total (32443ms).
[16:28:02.166] <TB2> INFO: 1552115 events read in total (65170ms).
[16:28:34.693] <TB2> INFO: 2320210 events read in total (97697ms).
[16:29:07.201] <TB2> INFO: 3082935 events read in total (130205ms).
[16:29:39.885] <TB2> INFO: 3844610 events read in total (162889ms).
[16:29:53.720] <TB2> INFO: 4160000 events read in total (176724ms).
[16:29:53.864] <TB2> INFO: Test took 177745ms.
[16:30:21.338] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[16:30:21.353] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:30:21.353] <TB2> INFO: run 1 of 1
[16:30:21.593] <TB2> INFO: Expecting 5324800 events.
[16:30:52.740] <TB2> INFO: 689605 events read in total (30555ms).
[16:31:23.171] <TB2> INFO: 1377150 events read in total (60986ms).
[16:31:53.667] <TB2> INFO: 2062960 events read in total (91482ms).
[16:32:24.060] <TB2> INFO: 2746565 events read in total (121875ms).
[16:32:54.546] <TB2> INFO: 3427650 events read in total (152361ms).
[16:33:24.848] <TB2> INFO: 4108250 events read in total (182663ms).
[16:33:55.152] <TB2> INFO: 4787720 events read in total (212967ms).
[16:34:19.121] <TB2> INFO: 5324800 events read in total (236936ms).
[16:34:19.229] <TB2> INFO: Test took 237876ms.
[16:34:50.501] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[16:34:50.515] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:34:50.515] <TB2> INFO: run 1 of 1
[16:34:50.751] <TB2> INFO: Expecting 4472000 events.
[16:35:22.911] <TB2> INFO: 731090 events read in total (31569ms).
[16:35:54.525] <TB2> INFO: 1458445 events read in total (63183ms).
[16:36:25.985] <TB2> INFO: 2183180 events read in total (94643ms).
[16:36:57.413] <TB2> INFO: 2903825 events read in total (126071ms).
[16:37:29.278] <TB2> INFO: 3622650 events read in total (157936ms).
[16:38:01.381] <TB2> INFO: 4341695 events read in total (190039ms).
[16:38:07.122] <TB2> INFO: 4472000 events read in total (195780ms).
[16:38:07.234] <TB2> INFO: Test took 196720ms.
[16:38:33.323] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[16:38:33.337] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:38:33.337] <TB2> INFO: run 1 of 1
[16:38:33.619] <TB2> INFO: Expecting 4472000 events.
[16:39:06.077] <TB2> INFO: 730870 events read in total (31866ms).
[16:39:38.062] <TB2> INFO: 1458520 events read in total (63851ms).
[16:40:10.139] <TB2> INFO: 2183530 events read in total (95929ms).
[16:40:42.195] <TB2> INFO: 2904300 events read in total (127984ms).
[16:41:14.010] <TB2> INFO: 3623190 events read in total (159799ms).
[16:41:45.487] <TB2> INFO: 4342480 events read in total (191276ms).
[16:41:51.269] <TB2> INFO: 4472000 events read in total (197058ms).
[16:41:51.350] <TB2> INFO: Test took 198013ms.
[16:42:19.889] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[16:42:19.903] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:42:19.903] <TB2> INFO: run 1 of 1
[16:42:20.139] <TB2> INFO: Expecting 4472000 events.
[16:42:52.296] <TB2> INFO: 731100 events read in total (31566ms).
[16:43:23.862] <TB2> INFO: 1459050 events read in total (63132ms).
[16:43:55.386] <TB2> INFO: 2184300 events read in total (94656ms).
[16:44:27.042] <TB2> INFO: 2905255 events read in total (126312ms).
[16:44:58.442] <TB2> INFO: 3625185 events read in total (157712ms).
[16:45:31.507] <TB2> INFO: 4344740 events read in total (190777ms).
[16:45:37.634] <TB2> INFO: 4472000 events read in total (196904ms).
[16:45:37.737] <TB2> INFO: Test took 197834ms.
[16:46:01.715] <TB2> INFO: PixTestTrim80::trimBitTest() done
[16:46:01.716] <TB2> INFO: PixTestTrim80::doTest() done, duration: 2773 seconds
[16:46:02.349] <TB2> INFO: enter test to run
[16:46:02.349] <TB2> INFO: test: exit no parameter change
[16:46:02.548] <TB2> QUIET: Connection to board 149 closed.
[16:46:02.549] <TB2> INFO: pXar: this is the end, my friend